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Semiconductor device manufacturing methodRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization)Semiconductor device manufacturing method description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070087559, Semiconductor device manufacturing method. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device manufacturing method and for example to a method for manufacturing a semiconductor device having a gate electrode and a resistive interconnection. [0003] 2. Description of the Background Art [0004] In a semiconductor substrate having an element isolation film of the background art, a resistive interconnection having a relatively high resistance value (e.g. a resistance value of about several hundred to several thousand ohms) is formed on the element isolation film and a gate electrode is formed on the semiconductor substrate in isolation from the resistive interconnection. [0005] In the semiconductor device thus structured, impurity ions are implanted into the resistive interconnection to control its resistance value, and impurity ions are also implanted into the semiconductor substrate to form diffusion layers in areas on both sides of the gate electrode. Subsequently a heat treatment is applied to activate the diffusion layers. [0006] Related prior arts include the following (for example, refer to the First to Third Patent Documents): Japanese Patent Application Laid-Open Nos. 2-128465 (1990), 2-228065 (1990), and 2000-216254. [0007] However, in the method above, the heat treatment causes out-diffusion of ions from the resistive interconnection. This makes it impossible to precisely control the resistance value of the resistive interconnection. [0008] Also, while First Patent Document discloses a technique in which an oxide film is formed on the resistive interconnection after formation of transistors, the oxide film formation involves an additional heat treatment, which varies the characteristics of the transistors and makes it impossible to provide highly precise transistors. [0009] Also, even when the resistive interconnection is formed after the formation of the gate electrode, the formation of the resistive interconnection involves an additional heat treatment, which may vary the transistor characteristics. SUMMARY OF THE INVENTION [0010] An object of the present invention is to provide a semiconductor device manufacturing method that is capable of suppressing variation of the resistance value of resistive interconnection and preventing variation of transistor performance. [0011] According to the present invention, a semiconductor device manufacturing method includes the following steps (a) to (d). The step (a) is forming a resistive interconnection and a gate electrode on a substrate. The step (b) is implanting impurity ions into a surface of the substrate to form a diffusion layer. The step (c) is forming an insulating film to cover the resistive interconnection and the gate electrode. The step (d) is heating the substrate after the step (c) to activate the diffusion layer. [0012] The resistive interconnection is covered by the insulating film before the heat treatment for activating the diffusion layer. This prevents impurity ions contained in the resistive interconnection from diffusing outward during the heat treatment. This consequently suppresses variation of the resistance value of the resistive interconnection due to the heat treatment. [0013] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0014] FIGS. 1 to 9 are cross-sectional views illustrating a manufacturing method according to a first preferred embodiment; [0015] FIG. 10 is a cross-sectional view illustrating a manufacturing method according to a second preferred embodiment; [0016] FIGS. 11 and 12 are cross-sectional views illustrating a manufacturing method according to a third preferred embodiment; [0017] FIGS. 13 to 16 are cross-sectional views illustrating a manufacturing method according to a fourth preferred embodiment; [0018] FIG. 17 is a plan view used to explain the sizing of openings with respect to the sizing of contact areas with via plugs; [0019] FIGS. 18 to 20 are cross-sectional views illustrating the manufacturing method of the fourth preferred embodiment; [0020] FIG. 21 is a cross-sectional view illustrating a manufacturing method according to a fifth preferred embodiment; [0021] FIGS. 22 to 26 are cross-sectional views illustrating a manufacturing method according to a sixth preferred embodiment; Continue reading about Semiconductor device manufacturing method... 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