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Semiconductor device manufacturing: process November recently filed with US Patent Office 11/10

20100297781 - Method for manufacturing mems structures: A method for manufacturing MEMS structures having at least one functional layer of silicon that contains structures that are exposed by removing a sacrificial layer, at least one sacrificial layer and at least one functional layer being deposited such that they grow in a monocrystalline manner, and the sacrificial layer... Agent: Kenyon & Kenyon LLP

20100297783 - Plasma processing method: A method for performing a plasma process using a plasma processing apparatus which includes a vacuum process chamber, an exhaust device, a mass flow controller supplying a process gas, a stage electrode which receives and holds a workpiece by adsorption, a transfer device, and a high-frequency electrical source. The method... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100297782 - Techniques for processing a substrate: Herein, an improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be realized with a system for processing one or more substrates. The system may comprise an ion source for generating ions of desired species, the ions generated from the ion source being... Agent: Varian Semiconductor Equipment Assc., Inc.

20100297784 - Nitride based semiconductor optical device, epitaxial wafer for nitride based semiconductor optical device, and method of fabricating semiconductor light-emitting device: In the nitride based semiconductor optical device LE1, the strained well layers 21 extend along a reference plane SR1 tilting at a tilt angle α from the plane that is orthogonal to a reference axis extending in the direction of the c-axis. The tilt angle α is in the range... Agent: Venable LLP

20100297785 - Manufacture of defect cards for semiconductor dies: A method for producing a defect card for individual dies located on a wafer, comprising: producing first and second defect cards, where the defective individual dies whose adjoining individual dies form an environment having a defect density up to a first value (δ1) are classified as defective on the first... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20100297788 - Arrangements and methods for improving bevel etch repeatability among substrates: A method, performed in connection with bevel etching of a substrate, for improving bevel-etch repeatability among substrates, is disclosed. The method includes providing an optical arrangement and ascertaining at least one bevel edge characteristic of a bevel edge of said substrate. The method also includes deriving at least one compensation... Agent: Ipsg, P.C.

20100297786 - Method for manufacturing compound semiconductor and apparatus for manufacturing the same: Each of first and second thin film layers is formed by growing a crystal of each thin film layer one over another on a silicon substrate 2 in first and second vapor deposition chambers 6a and 6b for exclusive use, corresponding to the respective thin film layers. As this crystal... Agent: Birch Stewart Kolasch & Birch

20100297790 - Method for producing semiconductor devices: A method for producing semiconductor devices according to the present invention includes a dislocation-density evaluation step of measuring a dislocation density of sections of GaN substrates, the sections intersecting with principal surfaces of the GaN substrates, and selecting a GaN substrate in which the dislocation density is a predetermined value... Agent: Drinker Biddle & Reath (dc)

20100297789 - Method for producing semiconductor optical device: A method for producing a semiconductor optical device, includes the steps of: (a) forming a semiconductor region on a substrate, the substrate including first and second areas; the first area including device sections (b) forming a first mask on the semiconductor region, the first mask including first patterns periodically arranged... Agent: Smith, Gambrell & Russell

20100297787 - System and method for backside circuit editing on full thickness silicon device: A system for accessing circuitry on a flip chip circuit device with active circuitry and full-thickness bulk silicon includes a moveable surface for supporting and locating the circuit device in a plane, an infrared (IR) imaging device located at a defined perpendicular distance from a surface of the bulk silicon,... Agent: Kathy Manke Avago Technologies Limited

20100297791 - Method for inspecting photoresist pattern: A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a... Agent: North America Intellectual Property Corporation

20100297792 - Semiconductor device having a semiconductor chip, and method for the production thereof: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on... Agent: Dicke, Billig & Czaja

20100297793 - In line test circuit and method for determining interconnnect electrical properties and integrated circuit incorporating the same: A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and... Agent: Texas Instruments Incorporated

20100297794 - Efficient led array: An efficient LED array. In an aspect, an LED apparatus includes a metal substrate having a reflective surface, and LED chips mounted directly to the reflective surface to allow for thermal dissipation, and wherein at least a portion of the LED chips are spaced apart from each other to allow... Agent: Haynes And Boone, LLPIPSection

20100297796 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device including growing an InAlGaAsP layer having a thickness of 1.0 μm or more on a surface of an InP semiconductor layer at a growth temperature of 680 degrees C. or more, a composition ratio “X” of Ga in InAlGa of the InAlGaAsP being... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100297795 - Method for producing semiconductor optical device: A method for producing a semiconductor optical device, includes the steps of: forming a semiconductor region including a semiconductor layer on a substrate; preparing a mold including a pattern surface, the pattern surface including an arrangement of patterns each including first to n-th pattern portions; forming a first mask on... Agent: Smith, Gambrell & Russell

20100297797 - Manufacturing method of an electronic device including overmolded mems devices: A method manufactures an electronic device comprising a MEMS device overmolded in a protective casing. The MEMS device includes an active surface wherein a portion of the MEMS device is integrated, and is sensitive, through a membrane, to chemical/physical variations of a fluid. Prior to the molding step, at least... Agent: Seed Intellectual Property Law Group PLLC

20100297798 - Individually encapsulated solar cells and/or solar cell strings: Methods and devices are provided for improved environmental protection for photovoltaic devices and assemblies. In one embodiment, the device comprises of an individually encapsulated solar cell, wherein the encapsulated solar cell includes at least one protective layer coupled to at least one surface of the solar cell and the protective... Agent: Director Of Ip

20100297799 - Image capture unit: An image capture unit and its manufacturing method. The image capture unit includes a thinned-down integrated circuit chip having an image sensor on its upper surface side. A wall extends above a peripheral upper surface ring-shaped area, and a lens rests on the high portion of the wall.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20100297800 - Solar cell panels and method of fabricating same: A solar cell panel and method of forming a solar cell panel. The method includes a: forming an electrically conductive bus bar on a top surface of a bottom cover plate; forming an electrically conductive contact frame proximate to a bottom surface of a top cover plate, the top cover... Agent: Lieberman & Brandsdorfer, LLC

20100297801 - Method for producing electric contacts on a semiconductor component: Process for producing strip-shaped and/or point-shaped electrically conducting contacts on a semiconductor component like a solar cell, includes the steps of applying a moist material forming the contacts in a desired striplike and/or point-like arrangement on at least one exterior surface of the semiconductor component; drying the moist material by... Agent: Dennison, Schultz & Macdonald

20100297802 - Solar cell assemblies and method of manufacturing solar cell assemblies: Solar cell assemblies and method of making solar cell assemblies. The method, including: fabricating solar cell chips on solar cell wafers; dicing the solar cell wafers into individual solar cell chips; packaging the individual solar cell chips in molded plastic packages to form solar cell chip packages; and mounting on... Agent: Lieberman & Brandsdorfer, LLC

20100297803 - Nanophotovoltaic devices: The present invention provides nanophotovoltaic devices having sizes in a range of about 50 nm to about 5microns, and method of their fabrication. In some embodiments, the nanophotovoltaic device includes a semiconductor core, e.g., formed of silicon, sandwiched between two metallic layers, one of which forms a Schottky barrier junction... Agent: Nutter Mcclennen & Fish LLP

20100297804 - Method of making backside illumination image sensor: An exemplary method for making a backside illumination image sensor includes the follow steps. A substrate having a top surface is firstly provided. Secondly, many recesses are formed in the top surface. Thirdly, a light pervious layer is applied on the top surface. The light pervious layer has a plurality... Agent: Altis Law Group, Inc. Attn: Steven Reiss

20100297805 - Solid-state imaging device, production method of the same, and imaging apparatus: In a solid-state imaging device, the pixel circuit formed on the first surface side of the semiconductor substrate is shared by a plurality of light reception regions. The second surface side of the semiconductor substrate is made the light incident side of the light reception regions. The second surface side... Agent: Sonnenschein Nath & Rosenthal LLP

20100297806 - Method of manufacturing solar cell module: While using the same laser device, a slit (S4) is formed by cutting an photoelectric conversion unit and a backside electrode formed over a transparent electrode to a surface of the transparent electrode and a slit (S5) is formed by cutting the photoelectric conversion unit and the backside electrode formed... Agent: Ditthavong Mori & Steiner, P.C.

20100297807 - Cmos imager having a nitride dielectric: An imaging device formed as a CMOS semiconductor integrated circuit includes a nitrogen containing insulating material beneath a photogate. The nitrogen containing insulating material, preferably be one of a silicon nitride layer, an ONO layer, a nitrode/oxide layer and an oxide/nitrode layer. The nitrogen containing insulating layer provides an increased... Agent: Dickstein Shapiro LLP

20100297808 - Molecular electronic device including organic dielectric thin film and method of fabricating the same: Provided are a molecular electronic device and a method of fabricating the molecular electronic device. The molecular electronic device includes a substrate, an organic dielectric thin film formed over the substrate, a molecular active layer formed on the organic dielectric thin film and having a charge trap site, and an... Agent: Ladas & Parry LLP

20100297809 - Organic transistor, manufacturing method of semiconductor device and organic transistor: It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a... Agent: Robinson Intellectual Property Law Office, P.C.

20100297810 - Power semiconductor device and method for its production: A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power... Agent: Edell, Shapiro & Finnan, LLC

20100297811 - Semiconductor device and method of manufacturing the same: A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10,... Agent: Young & Thompson

20100297812 - Method for stacking serially-connected integrated circuits and multi-chip device made from same: A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial... Agent: Borden Ladner Gervais LLP Anne Kinsman

20100297813 - Semiconductor package with position member: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and... Agent: Stmicroelectronics, Inc.

20100297814 - Electronic system modules and method of fabrication: A trace routing method for a multi-layer interconnection circuit includes the steps of providing stacked contacts with trace stubs at input/output pads of said interconnection circuit, and limiting contacts between conductive layers to two-level contacts in routing areas where maximum routing density is desired.... Agent: Townsend And Townsend And Crew, LLP

20100297815 - Transistor layout for manufacturing process control: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate... Agent: Texas Instruments Incorporated

20100297816 - Nanowire mesh device and method of fabricating same: A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and... Agent: Scully, Scott, Murphy & Presser, P.C.

20100297817 - Method for manufacturing thin film transistor: A method for manufacturing a thin film transistor (TFT) is disclosed. The method is achieved by forming and defining a source and a drain of a thin film transistor through two lithographic processes cycles so that the channel length (L) of the thin film transistor can be reduced to 1.5... Agent: Bacon & Thomas, PLLC

20100297818 - Semiconductor devices having pfet with sige gate electrode and embedded sige source/drain regions and methods of making the same: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate... Agent: Slater & Matsil, L.L.P.

20100297819 - Trench dram cell with vertical device and buried word lines: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each... Agent: Wells St. John P.s.

20100297820 - Embedded semiconductor device including planarization resistance patterns and method of manufacturing the same: An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substrate, source/drain regions formed on both sides of the gates in the... Agent: F. Chau & Associates, LLC

20100297821 - Method of manufacturing semiconductor device: A method for fabricating a semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. The method includes forming an isolation region in a semiconductor substrate; forming a gate electrode over an element region defined by the isolation region... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100297822 - Methods of forming capacitor structures, methods of forming threshold voltage implant regions, and methods of implanting dopant into channel regions: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in... Agent: Wells St. John P.s.

20100297823 - Method for angular doping of source and drain regions for odd and even nand blocks: Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped... Agent: Vierra Magen/sandisk Corporation

20100297824 - Memory structure with reduced-size memory element between memory material portions: A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100297825 - Passive components in the back end of integrated circuits: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set... Agent: Ibm Microelectronics Intellectual Property Law

20100297826 - Method of manufacturing nonvolatile memory device: In one embodiment of a method of manufacturing a nonvolatile memory device, a tunnel insulating layer and a charge trap layer are first formed over a semiconductor substrate that defines active regions and isolation regions. The tunnel insulating layer, the charge trap layer, and the semiconductor substrate formed in the... Agent: Marshall, Gerstein & Borun LLP

20100297827 - Method for manufacturing semiconductor device: An adhesion layer and a supporting substrate are provided on the entire surface of the first surface side of a substrate with a metal seed film provided on the first surface side of the substrate. After the removal of the adhesion layer and the supporting substrate provided on the first... Agent: Young & Thompson

20100297828 - Method for fabricating a semiconductor on insulator type substrate: A method for fabricating a substrate of the semiconductor on insulator type by forming an epitaxial layer of semiconducting material on a donor substrate having oxygen precipitates with a density of less than 1010/cm3 or a mean size of less than 500 nm, forming an oxide layer on either a... Agent: Winston & Strawn LLP Patent Department

20100297829 - Method of temporarily attaching a rigid carrier to a substrate: Method for temporarily attaching a substrates to a rigid carrier is described which includes forming a sacrificial layer of a thermally-decomposable polymer, e.g., poly(alkylene carbonate), and bonding the flexible substrate to the rigid carrier with the sacrificial layer positioned therebetween. Electronic components and/or circuits may then be fabricated or other... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20100297830 - Laser processing method for semiconductor wafer: A laser processing method for a semiconductor wafer including a groove forming step of applying a pulsed laser beam having an absorption wavelength to the semiconductor wafer along a division line formed on the semiconductor wafer to thereby form a laser processed groove along the division lines on the semiconductor... Agent: Greer, Burns & Crain

20100297831 - Laser processing method for semiconductor wafer: A laser processing method for a semiconductor wafer including a groove forming step of applying a pulsed laser beam having an absorption wavelength to the semiconductor wafer along a division line formed on the semiconductor wafer to thereby form a laser processed groove along the division line on the semiconductor... Agent: Greer, Burns & Crain

20100297833 - Complexes of carbon nanotubes and fullerenes with molecular-clips and use thereof: Separation of carbon nanotubes or fullerenes according to diameter through non-covalent pi-pi interaction with molecular clips is provided. Molecular clips are prepared by Diels-Alder reaction of polyacenes with a variety of dienophiles. The pi-pi complexes of carbon nanotrubes with molecular clips are also used for selective placement of carbon nanotubes... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20100297834 - Method for reducing dielectric overetch using a dielectric etch stop at a planar surface: A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch... Agent: Dugan & Dugan, PC

20100297832 - Semiconductor device manufacturing method, substrate processing apparatus, substrate manufacturing method: Provided is a substrate processing apparatus, a semiconductor device manufacturing method, and a substrate manufacturing method. The substrate processing apparatus comprises: a reaction chamber configured to process substrates; a first gas supply system configured to supply at least a silicon-containing gas and a chlorine-containing gas or at least a gas... Agent: Brundidge & Stanger, P.C.

20100297835 - Methods for fabricating copper indium gallium diselenide (cigs) compound thin films: A method for fabricating a copper-indium-gallium-diselenide (CIGS) compound thin film is provided. In this method, a substrate is first provided. An adhesive layer is formed over the substrate. A metal electrode layer is formed over the adhesive layer. A precursor stacked layer is formed over the metal electrode layer, wherein... Agent: Pai Patent & Trademark Law Firm

20100297836 - Plasma doping apparatus and method, and method for manufacturing semiconductor device: A top plate, disposed on an upper portion of a vacuum container so as to face a substrate-placing area of a sample electrode, is provided with an impurity-containing film that contains an impurity, and is formed on a top plate peripheral edge portion area that is a face exposable to... Agent: Mcdermott Will & Emery LLP

20100297837 - Implantation using a hardmask: A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes... Agent: Innovation Interface, LLC

20100297838 - Independently accessed double-gate and tri-gate transistors in same process flow: A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20100297839 - Method of fabricating semiconductor device having multiple gate insulating layer: A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing... Agent: F. Chau & Associates, LLC

20100297840 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, sequentially forming a silicon layer and a metal layer over the gate insulation layer, performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the... Agent: Ip & T Group LLP

20100297842 - Conductive bump structure for semiconductor device and fabrication method thereof: A conductive bump structure for a semiconductor device and a method for fabricating the same are provided. A metal bump is formed on an under bump metallurgy (UBM) structure electrically connected to and formed on a connection pad of the semiconductor device, wherein the metal bump is sized smaller than... Agent: Bacon & Thomas, PLLC

20100297841 - Method for providing a redistribution metal layer in an integrated circuit: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder... Agent: Lisa K. Jorgenson, Esq. Stmicroelectronics, Inc.

20100297843 - Method for forming vias in a semiconductor substrate and a semiconductor device having the semiconductor substrate: The present invention relates to a method for forming vias in a semiconductor substrate, including the following steps: (a) providing a semiconductor substrate having a first surface and a second surface; (b) forming a groove on the semiconductor substrate; (c) filling the groove with a conductive metal; (d) removing part... Agent: Mccracken & Frank LLP

20100297844 - Integrated circuit system with through silicon via and method of manufacture thereof: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation... Agent: Law Offices Of Mikio Ishimaru

20100297845 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming an interlayer dielectric layer having a plurality of contact holes over a substrate, forming a conductive layer by filling the contact holes to cover the interlayer dielectric layer, performing a first main etch process to partially etch the conductive layer to... Agent: Ip & T Group LLP

20100297846 - Method of manufacturing a semiconductor device and substrate processing apparatus: A method of manufacturing a semiconductor device includes the steps of: forming a first metal film on the substrate placed in a processing chamber by alternately supplying at least one type of a metal compound that is an inorganic raw material and a reactant gas that has reactivity to the... Agent: Oliff & Berridge, PLC

20100297847 - Method of forming sub-lithographic features using directed self-assembly of polymers: Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes... Agent: Daniel E. Johnson IBM Corporation, Almaden Research Center

20100297848 - Etching of tungsten selective to titanium nitride: The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF6) and oxygen (O2), in which the ratio of sulfur hexafluoride (SF6) to oxygen (O2)... Agent: Scully, Scott, Murphy & Presser, P.C.

20100297849 - Plasma etching method for etching an object: The invention provides a plasma etching method capable of suppressing bowing of an opening of the object to be etched, and solving the lack of opening at a high aspect ratio portion in deep hole processing having a high aspect ratio. A plasma etching method for etching an object to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100297850 - Selective self-aligned double patterning of regions in an integrated circuit device: A selective self-aligned dual patterning method. The method includes performing a single lithography operation to form a patterned mask having a narrow feature in a region of a substrate that is to a have pitch-reduced feature and a wide feature in a region of the substrate that is to have... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20100297851 - Compositions and methods for multiple exposure photolithography: Compositions for use in multiple exposure photolithography and methods of forming electronic devices using a multiple exposure lithographic process are provided. The compositions find particular applicability in semiconductor device manufacture for making high-density lithographic patterns.... Agent: Jonathan D. Baskin Rohm And Haas Electronic Materials LLC

20100297852 - Method of forming line/space patterns: A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern... Agent: Volentine & Whitt PLLC

20100297853 - Method for purifying acetylene gas for use in semiconductor processes: Acetylene is treated to remove some residual storage solvent that may be present with the acetylene in a source of acetylene such as a container. Such treatment may be performed prior to supplying the acetylene to a deposition chamber or other reactor where acetylene is a reactant. After treatment, the... Agent: Weaver Austin Villeneuve & Sampson LLP - Novl Attn.: Novellus Systems, Inc.

20100297854 - High throughput selective oxidation of silicon and polysilicon using plasma at room temperature: Methods of fabricating an oxide layer on a semiconductor structure are provided herein. In some embodiments, a method of selectively forming an oxide layer on a semiconductor structure includes providing a substrate having one or more metal-containing layers and one or more non metal-containing layers to a substrate support in... Agent: MoserIPLaw Group / Applied Materials, Inc.

20100297855 - Device processing method: A device processing method for improving the die strength of a device divided from a semiconductor wafer. The device processing method includes a chamfering step of applying a pulsed laser beam having an absorption wavelength to the device along the periphery of the device to thereby chamfer the periphery of... Agent: Greer, Burns & Crain

20100297856 - Pulse train annealing method and apparatus: The present invention generally describes apparatuses and methods used to perform an annealing process on desired regions of a substrate. In one embodiment, pulses of electromagnetic energy are delivered to a substrate using a flash lamp or laser apparatus. The pulses may be from about 1 nsec to about 10... Agent: Patterson & Sheridan, LLP - - Appm/tx

20100291713 - Method of forming highly conformal amorphous carbon layer: A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer... Agent: Snell & Wilmer L.L.P. (asm Japan)

20100291714 - Method and system for the in-situ determination of the material composition of optically thin layers: A system and method for in situ determination of a material composition of optically thin layers deposited from a vapor phase onto a substrate includes irradiating the substrate with incoherent light of at least three different wavelengths, optically detecting in a spatially resolved manner a reflection intensity of a diffuse... Agent: Leydig, Voit And Mayer

20100291715 - Mounted structure, liquid droplet ejection head, liquid droplet ejection apparatus and manufacturing method: A liquid droplet ejection head includes: a first substrate having a pressurizing chamber with a nozzle aperture that ejects liquid droplets, and a first surface on which is formed a first wiring electrically connected to the drive element; a second substrate disposed on the first surface of the first substrate... Agent: Harness, Dickey & Pierce, P.L.C

20100291716 - Organic electroluminescence device and method of manufacturing the same: An EL device with low manufacturing costs and improved yield due to simplified structure and use of an organic light emitting transistor and a method of manufacturing the same are disclosed. The EL device includes: a first organic light emitting transistor including a first source electrode; a first drain electrode... Agent: Knobbe Martens Olson & Bear LLP

20100291717 - Optimized process for fabricating light-emitting devices using artificial materials:

20100291719 - Method for manufacturing nitride based single crystal substrate and method for manufacturing nitride based semiconductor device: A method for manufacturing a nitride based single crystal substrate and a method for manufacturing a nitride based semiconductor device. The method for manufacturing the nitride based single crystal substrate includes forming a nitride based single crystal layer on a preliminary substrate; forming a polymer support layer by applying a... Agent: Mcdermott Will & Emery LLP

20100291718 - Method of fabricating semiconductor laser: A substrate product is formed, and the substrate product includes a first region, a second region, a protrusion structure, and first and second scribe marks. The first region includes sections arranged in first and second axes to form an array, and the second region is provided adjacent to the array.... Agent: Smith, Gambrell & Russell

20100291720 - Method of fabricating organic light emitting diode display: A method of fabricating an organic light emitting diode display device includes: sequentially forming a thin film transistor (TFT) array, a first electrode, a bank pattern, a spacer, and a first relevant layer on an acceptor substrate; sequentially forming a metal pattern and an organic light emission material layer on... Agent: Mckenna Long & Aldridge LLP

20100291721 - Processes for forming electronic devices including spaced-apart radiation regions: Processes for forming an electronic device include forming a first radiation region, a second radiation region spaced apart from the first radiation region, and an insulating region. The insulating region can have a first side and a second side opposite the first side. The first radiation region can lie immediately... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20100291722 - Etchant and method of manufacturing an array substrate using the same: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01... Agent: F. Chau & Associates, LLC

20100291723 - Method of manufacturing an organic electronic or optoelectronic device: A method of manufacturing an organic electronic or optoelectronic device, the method comprising the steps of: (a) providing a substrate having a plurality of banks formed thereon with alternating well formations formed therebetween, the surface of said banks having imprint formations formed thereon of a dimension conferring a selected wetting... Agent: Townsend And Townsend And Crew, LLP

20100291724 - Method of producing high performance photovoltaic and thermoelectric nanostructured bulk and thin films: Embodiments of the invention provide methods of forming photovoltaic or thermoelectric materials, including photovoltaic or thermoelectric films. In one embodiment, the invention provides a method of forming a photovoltaic material, the method comprising: depositing an inorganic capped nanoparticle solution onto a substrate; and heating the substrate.... Agent: Hoffman Warnick LLC

20100291725 - Method of forming a flexible nanostructured material for photovoltaic panels: An efficient and low-cost method is intended for forming a flexible nanostructured material suitable for use as an active element of a photovoltaic panel. The method consists of evaporating a colloidal solution, which contains nanoparticles of various sizes and/or masses, from a flat surface of a rotating body on which... Agent: Boris Gilman

20100291726 - Method of fabricating a radiation detector:

20100291727 - Roll-to-roll processing method and tools for electroless deposition of thin layers: A deposition method and a system are provided to deposit a CdS buffer layer on a surface of a solar cell absorber layer of a flexible workpiece from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited from the deposition solution while the... Agent: Pillsbury Winthrop Shaw Pittman LLP

20100291728 - Manufacturing method of the solar cell: A method of manufacturing a solar cell, which can improve productivity by improving a surface texturing process for effectively capturing incident light during a process for manufacturing the solar cell, is provided. The method includes cleaning a substrate, texturing a surface of the substrate, doping and diffusing impurities into the... Agent: Gifford, Krass, Sprinkle,anderson & Citkowski, P.c

20100291730 - Backside illuminated imaging device, semiconductor substrate, imaging apparatus and method for manufacturing backside illuminated imaging device: A backside illuminated imaging device performs imaging by illuminating light from a back side of a p substrate to generate electric charges in the substrate based on the light and reading out the electric charges from a front side of the substrate. The device includes n layers located in the... Agent: Birch Stewart Kolasch & Birch

20100291729 - Method of manufacturing photoelectric conversion device: A method of manufacturing a photoelectric conversion device having a semiconductor substrate, comprises a first step of forming an insulating film on the semiconductor substrate, a second step of forming first holes in the insulating film, a third step of forming, in the insulating film, second holes shallower than the... Agent: Fitzpatrick Cella Harper & Scinto

20100291731 - Method of field-controlled diffusion and devices formed thereby: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/−50... Agent: JasIPConsulting

20100291732 - Manufacturing method for electronic devices: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying... Agent: Mcginn Intellectual Property Law Group, PLLC

20100291734 - Semiconductor device with an improved solder joint: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA... Agent: Texas Instruments Incorporated

20100291733 - Semiconductor package with improved size, reliability, warpage prevention, and heat dissipation and method for manufacturing the same: The semiconductor package includes a semiconductor package module with circuit patterns formed on an insulation substrate, at least two semiconductor chips electrically connected to each of the circuit patterns using bumps, and an insulation member filled in any open space in the semiconductor module. A cover plate is formed on... Agent: Ladas & Parry LLP

20100291735 - Stackable semiconductor chip layer comprising prefabricated trench interconnect vias: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations... Agent: Foley & Lardner LLP

20100291736 - Stacking multiple devices using single-piece interconnecting element: An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity... Agent: Blakely Sokoloff Taylor & Zafman LLP

20100291737 - Method of manufacturing semiconductor package: A method of manufacturing a semiconductor package that includes: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and... Agent: Staas & Halsey LLP

20100291738 - Patterned die attach and packaging method using the same: A semiconductor die is attached to a packaging substrate by a patterned layer of conductive metal that includes voids. The voids provide a space into which the metal may expand when heated in order to avoid placing mechanical stress on the bonds caused by mismatches in the thermal coefficients of... Agent: Duke W. Yee

20100291739 - Dicing die bonding film and dicing method: The present invention relates to a dicing die bonding film, which is able to maintain good workability and reliability in any semiconductor packaging process, such as adhesive property, gap filling property and pick-up property, while controlling burr incidence in a dicing process and thus contamination of die, and a dicing... Agent: Mckenna Long & Aldridge LLP

20100291740 - Semiconductor device and method for manufacturing the same: A semiconductor device includes at least one thin film transistor including a semiconductor layer that has a crystalline region including a channel region, a source region and a drain region, a gate insulating film disposed at least on the channel region, the source region and the drain region of the... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20100291741 - Method of fabricating array substrate: A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming... Agent: Mckenna Long & Aldridge LLP

20100291742 - Reverse construction memory cell: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a... Agent: Knobbe Martens Olson & Bear LLP

20100291743 - Semiconductor device and method of forming the same: A method of forming a semiconductor device includes the following processes. A first pillar and a second pillar are formed on a semiconductor substrate. A semiconductor film is formed which includes first and second portions. The first portion is disposed over a side surface of the first pillar. The second... Agent: Mcginn Intellectual Property Law Group, PLLC

20100291744 - High density trench mosfet with single mask pre-defined gate and contact trenches: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench.... Agent: Joshua D. Isenberg Jdi Patent

20100291745 - Method for manufacturing a nonvolatile semiconductor memory device: Bit line diffusion layers are formed in an upper part of a semiconductor substrate with a bit line contact region being interposed between the bit line diffusion layers. A conductive film is formed over the semiconductor substrate, the bit line diffusion layers, and first gate insulating films. Then, control gate... Agent: Mcdermott Will & Emery LLP

20100291746 - Shared contact structure, semiconductor device and method of fabricating the semiconductor device: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The... Agent: Harness, Dickey & Pierce, P.L.C

20100291747 - Phase change memory device and manufacturing method: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20100291748 - Method for making pmc type memory cells: A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100291749 - Method for fabrication of a semiconductor device and structure: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based... Agent: Venable LLP

20100291750 - Method of fabricating flash memory device: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side... Agent: Townsend And Townsend And Crew, LLP

20100291751 - Method for fabricating an isolation structure: The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide;... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)

20100291755 - Manufacturing method of soi substrate: An SOI substrate is manufactured by a method in which a first insulating film is formed over a first substrate over which a plurality of first single crystal semiconductor films is formed; the first insulating film is planarized; heat treatment is performed on a single crystal semiconductor substrate attached to... Agent: Robinson Intellectual Property Law Office, P.C.

20100291752 - Method for manufacturing soi substrate and soi substrate: A method is demonstrated to form an SOI substrate having a silicon layer with reduced surface roughness in a high yield. The method includes the step of bonding a base substrate such as a glass substrate and a bond substrate such as a single crystal semiconductor substrate to each other,... Agent: Robinson Intellectual Property Law Office, P.C.

20100291754 - Semiconductor substrate and method for manufacturing the same, and method for manufacturing semiconductor device: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in... Agent: Robinson Intellectual Property Law Office, P.C.

20100291753 - Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device: A single crystal semiconductor layer is formed over a substrate having an insulating surface by the following steps: forming an ion doped layer at a given depth from a surface of a single crystal semiconductor substrate; performing plasma treatment to the surface of the single crystal semiconductor substrate; forming an... Agent: Robinson Intellectual Property Law Office, P.C.

20100291756 - Method for the production of a semiconductor structure: Semiconductor structures are produced by providing a 3C—SiC semiconductor layer containing a monocrystalline 3C—SiC layer by implantation of carbon in silicon on a first silicon substrate and applying an epitaxial layer of nitride compound semiconductor suitable for the generation of optoelectronic components onto the 3C—SiC semiconductor layer structure, wherein the... Agent: Brooks Kushman P.C.

20100291757 - Method of forming, modifying, or repairing a semiconductor device using field-controlled diffusion: A technique for altering or repairing the operating state of a semiconductor device comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/−50 V) the dopant atoms are... Agent: JasIPConsulting

20100291759 - Complexes of carbon nanotubes and fullerenes with molecular-clips and use thereof: Separation of carbon nanotubes or fullerenes according to diameter through non-covalent pi-pi interaction with molecular clips is provided. Molecular clips are prepared by Diels-Alder reaction of polyacenes with a variety of dienophiles. The pi-pi complexes of carbon nanotubes with molecular clips are also used for selective placement of carbon nanotubes... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20100291758 - Thin-film devices formed from solid particles: Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be... Agent: Director Of Ip

20100291760 - Method and system for spatially selective crystallization of amorphous silicon: The manufacturing methodology to produce polycrystalline silicon in time and cost efficient manner uses a spatially selective crystallization approach to greatly reduce the amount of energy delivered to the work surface. The amorphous silicon film is subjected to laser radiation substantially exclusively at localized areas where TFTs are to be... Agent: Rosenberg, Klein & Lee

20100291761 - Method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of sige deposited on the front side: e

20100291762 - Method of manufacturing silicon carbide semiconductor device: A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100291763 - Method of manufacturing semiconductor device and substrate processing apparatus: Oxidation of a metal film disposed under a high permittivity insulation film can be suppressed, and the productivity of a film-forming process can be improved. In a method of manufacturing a semiconductor device, a first high permittivity insulation film is formed on a substrate by alternately repeating a process of... Agent: North Star Intellectual Property Law, PC

20100291764 - Methods of removing noble metal-containing nanoparticles, methods of forming nand string gates, and methods of forming integrated circuitry: Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the... Agent: Wells St. John P.s.

20100291765 - Method for fabricating semiconductor device: An aspect of the present disclosure, there is provided a method for fabricating a semiconductor device, including, forming a gate insulating film on a semiconductor substrate, forming a metal film on the gate insulating film, depositing a metal-silicon compound film on the metal film without exposing the semiconductor substrate into... Agent: Turocy & Watson, LLP

20100291766 - Transistor constructions and processing methods: A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second... Agent: Wells St. John P.s.

20100291767 - Manufacturing method of semiconductor device: In MOSFET having SBD as a protection element, a TiW (alloy having tungsten as a main component) film is used as an aluminum-diffusion barrier metal film below an aluminum source electrode in order to secure properties of SBD. The present inventors have found that a tungsten-based barrier metal film is... Agent: Mattingly & Malur, P.C.

20100291768 - Method for fabricating a semiconductor device: An exposure mask for recess gate includes a transparent substrate and a recess gate pattern. The recess gate pattern is disposed over the transparent substrate. The recess gate pattern includes a first portion having a first line width and a second portion having a second line width smaller than the... Agent: Marshall, Gerstein & Borun LLP

20100291769 - Alternative methods for fabrication of substrates and heterostructures made of silicon compounds and alloys: The present invention relates to alternative methods for the production of crystalline silicon compounds and/or alloys such as silicon carbide layers and substrates. In one embodiment, a method of the present invention comprises heating a porous silicon deposition surface of a porous silicon substrate to a temperature operable for epitaxial... Agent: Kilpatrick Stockton LLP - 46872 J. Steven Gardner

20100291770 - Method of forming openings in a semiconductor device and a semiconductor device fabricated by the method: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, and forming a mask over the dielectric layer. The mask comprises a plurality of mask openings arranged in a regular pattern extending over the dielectric layer... Agent: Larson Newman & Abel, LLP

20100291771 - Methods of forming patterns on substrates: Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material.... Agent: Wells St. John P.s.

20100291772 - Semiconductor manufacturing method: The present invention discloses a semiconductor manufacturing method. The method for activating a p-type impurity doped in a semiconductor element in a chamber comprises that a vacuum pressure is exerted to the chamber first, and the semiconductor element is heated to a preset temperature and the heating is persisted for... Agent: Sinorica, LLC

20100285613 - In-plane switching mode liquid crystal display device and fabrication method thereof: An in-plane switching mode liquid crystal display device includes a first substrate including a pixel electrode in a pixel region, a second substrate facing the first substrate and including a common electrode, a first alignment layer on the pixel electrode, a second alignment layer on the common electrode, a first... Agent: Mckenna Long & Aldridge LLP

20100285614 - Semiconductor wafer metrology apparatus and method: A semiconductor wafer metrology technique comprising performing atmospheric buoyancy compensated weighing of a wafer, in which the wafer is weighed in a substantially upright condition. A vertical or near vertical wafer orientation causes the surface area in the direction of a force (weight) sensor to be reduced compared with a... Agent: Stites & Harbison PLLC

20100285615 - Fabrication method of semiconductor device: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an... Agent: Miles & Stockbridge PC

20100285616 - Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20100285617 - Liquid discharge head substrate, liquid discharge head using the substrate, and manufacturing method therefor: Provided is a liquid discharge head substrate including: a substrate; a heating resistor layer formed on the substrate; a flow path for a liquid; a wiring layer stacked on the heating resistor layer and having an end portion which forms a step portion on the heating resistor layer; and a... Agent: Fitzpatrick Cella Harper & Scinto

20100285618 - Pixel structure of lcd and fabrication method thereof: In this pixel structure, a metal layer/a dielectric layer/a heavily doped silicon layer constitutes a bottom electrode/a capacitor dielectric layer/a top electrode of a storage capacitor. At the same time, a metal shielding layer is formed under the thin film transistor to decrease photo-leakage-current.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100285620 - Led packaging methods and led-based lighting products: A method of packaging a light-emitting diode (LED) chip includes coupling the LED chip to a printed circuit board (PCB) and forming a conductor on a cover plate. Conductive epoxy is applied to at least one of the LED chip and the conductor. The cover plate is coupled to the... Agent: Lathrop & Gage LLP

20100285619 - Pixel structure of lcd and fabrication method thereof: A method for manufacturing a laser-active solid having a bonded passive Q-switch is provided, which is particularly suitable for large quantities.... Agent: Kenyon & Kenyon LLP

20100285622 - Light emitting device and method of manufacturing the same: Provided is a light emitting device and a method of manufacturing the same. The light emitting device comprises a transparent substrate, an n-type compound semiconductor layer formed on the transparent substrate, an active layer, a p-type compound semiconductor layer, and a p-type electrode sequentially formed on a first region of... Agent: Buchanan, Ingersoll & Rooney PC

20100285621 - Method of making diode having reflective layer: A method of forming a light emitting diode includes forming a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A... Agent: Mckenna Long & Aldridge LLP

20100285623 - Array substrate and method for fabricating thereof: The invention provides a method for manufacturing an array substrate utilizing a laser ablation process. A conductive layer can be selectively patterned by the laser ablation process without a photo mask due to different adhesions between the conductive layer and other materials. The patterned conductive layer thus formed adjoins an... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100285624 - Display device and manufacturing method of the same: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a... Agent: Nixon Peabody, LLP

20100285625 - Light-emitting element assembly and method for manufacturing the same: A method for making a light-emitting element assembly including a support substrate having a first surface, a second surface facing the first surface, a recessed portion, and a conductive material layer formed over the first surface and the inner surface of the recessed portion, and a light-emitting element. The light-emitting... Agent: Sonnenschein Nath & Rosenthal LLP

20100285626 - Fabrication method of light emitting diode: A fabrication method of light emitting diode is provided. A first type doped semiconductor layer is formed on a substrate. Subsequently, a light emitting layer is formed on the first type doped semiconductor layer. A process for forming the light emitting layer includes alternately forming a plurality of barrier layers... Agent: Jianq Chyun Intellectual Property Office

20100285627 - Micro-electro-mechanical device and manufacturing method for the same: It is an object of the present invention to provide a micro-electro-mechanical-device having a microstructure and a semiconductor element over one surface. In particular, it is an object of the present invention to provide a method for simplifying the process of forming the microstructure and the semiconductor element over one... Agent: Fish & Richardson P.C.

20100285628 - Micromachined microphone and multisensor and method for producing same: A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top silicon layer of the wafer. Various polysilicon microphone structures are formed above a front side of the top silicon layer by depositing at least one oxide... Agent: Sunstein Kann Murphy & Timbers LLP

20100285629 - Method for plasma deposition and plasma cvd system: In a film-forming process with a capacitively-coupled plasma (CCP) chemical vapor deposition (CVD) device, pulse control is performed on a low-frequency radio-frequency power source. During the pulse control, an ON time and an OFF time form one period. Furthermore, in the pulse control, a time interval between a time period... Agent: J C Patents

20100285630 - Method of manufacturing an image sensor having improved anti-reflective layer: In a method of manufacturing an image sensor, a photodiode may be formed in a light receiving region of a substrate having a first surface. A conductive wiring may be formed on the first surface of the substrate. After removing a portion of the substrate opposite to the first surface,... Agent: Harness, Dickey & Pierce, P.L.C

20100285631 - Method of selectively doping a semiconductor material for fabricating a solar cell: The present disclosure provides a method of selectively doping a semiconductor material for fabricating a solar cell. The method comprises forming at least one angled groove in the semiconductor material and forming a diffusion barrier on the semiconductor material. The diffusion barrier comprises a diffusion barrier material that is selected... Agent: Ganz Law, P.C.

20100285633 - Non volatile memory cells including a filament growth layer and methods of forming the same: A non volatile memory cell that includes a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including dielectric material and metal atoms; and a second electrode. In other embodiments, a memory array is... Agent: Campbell Nelson Whipps, LLC

20100285632 - Tft substrate and method for manufacturing tft substrate: An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate includes: a substrate; a gate... Agent: Millen, White, Zelano & Branigan, P.C.

20100285634 - Inductively coupled integrated circuit with magnetic communication path and methods for use therewith: An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die,... Agent: Garlick Harrison & Markison

20100285635 - Chip stack package and method of manufacturing the chip stack package: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode... Agent: Mills & Onello LLP

20100285636 - Manufacturing method of a packaging structure of electronic components: A manufacturing method of a packaging structure of electronic components includes the steps of: providing a substrate including a plurality of electronic components; covering the electronic components disposed on the substrate with a molding body; forming a plurality of pre-cut grooves on the molding body so as to define a... Agent: Rosenberg, Klein & Lee

20100285637 - Die down ball grid array packages and method for making same: A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of a substrate, the opening of the substrate extending through the substrate, such that a portion of the heat spreader is accessible... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20100285638 - Method for fabricating qfn semiconductor package: A method for making a quad flat non-lead (QFN) semiconductor package includes half etching a first side of a carrier to form top portions of a lead array and a die attach surface of a die attach pad, wherein the lead array includes at least one inner terminal lead disposed... Agent: North America Intellectual Property Corporation

20100285639 - Devices with graphene layers: A method includes an act of providing a crystalline substrate with a diamond-type lattice and an exposed substantially (111)-surface. The method also includes an act of forming a graphene layer or a graphene-like layer on the exposed substantially (111)-surface.... Agent: Docket Administrator - Room 3d-201e Alcatel-lucent Usa Inc.

20100285640 - Etchant for etching metal wiring layers and method for forming thin film transistor by using the same: The present invention discloses an etchant for etching at least two different metal layers, the etchant comprising hydrogen peroxide (H2O2) and one of carboxylic acid, carboxylate salt, and acetyl group (CH3CO—). The present invention also discloses a method of fabricating a metal wiring on a substrate, the method comprising forming... Agent: Mckenna Long & Aldridge LLP

20100285641 - Mask rom device, semiconductor device including the mask rom device, and methods of fabricating mask rom device and semiconductor device: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure... Agent: F. Chau & Associates, LLC

20100285642 - Method of doping impurity ions in dual gate and method of fabricating the dual gate using the same: A method of doping impurity ions in a dual gate includes doping first conductivity type impurity ions in a gate conductive layer over a semiconductor substrate having a first region and a second region, wherein the doping is performed with a concentration gradient so that a doping concentration in an... Agent: Marshall, Gerstein & Borun LLP

20100285643 - Modifying work function in pmos devices by counter-doping: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the... Agent: Slater & Matsil, L.L.P.

20100285644 - Methods of forming semiconductor devices having recessed channels: A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner... Agent: Myers Bigel Sibley & Sajovec

20100285645 - Methods of manufacturing vertical channel semiconductor devices: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart... Agent: Myers Bigel Sibley & Sajovec

20100285647 - Insulated gate silicon carbide semiconductor device and method for manufacturing the same: An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n− semiconductor layer on an SiC n+ substrate, a p-type base region and highly doped p-region both buried in the... Agent: Rossi, Kimms & Mcdowell LLP.

20100285646 - Method of fabricating power semiconductor device: Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer... Agent: North America Intellectual Property Corporation

20100285648 - Semiconductor device and method of fabricating the same: A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased... Agent: Lowe Hauptman Ham & Berner, LLP

20100285649 - Field-effect heterostructure transistors: An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located... Agent: Docket Administrator - Room 3d-201e Alcatel-lucent Usa Inc.

20100285650 - Method of fabricating semiconductor transistor devices with asymmetric extension and/or halo implants: A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions... Agent: Ingrassia Fisher & Lorenz, P.C. (gf)

20100285651 - Semiconductor device and its manufacturing method: To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100285652 - Method for manufacturing a semiconductor device that is less prone to dc failures brought about by unwanted defects on capacitors therein: A method for manufacturing a semiconductor device that is less prone to DC failures brought about by unwanted defects on capacitors in the device is presented. Manufacturing defects such as scratches are known to occur when making capacitors and that these defects are thought to be a primary cause of... Agent: Ladas & Parry LLP

20100285653 - Method of manufacturing semiconductor device: The method of manufacturing a semiconductor device includes a first conductor over a semiconductor substrate; forming a first insulator over the first conductor; forming a second insulator, having an etching characteristic different from an etching characteristic of the first insulator, over the first insulator; forming a second conductor on the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100285654 - Semiconductor device having reduced die-warpage and method of manufacturing the same: A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer... Agent: Volentine & Whitt PLLC

20100285655 - Method of producing bonded wafer: In the production of a bonded wafer by bonding a silicon wafer for active layer with an internal oxide film to a silicon wafer for support layer directly or indirectly with an insulating layer to form a silicon wafer composite and removing an upperlayer-side silicon portion and the internal oxide... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20100285656 - Formation of metal-containing nano-particles for use as catalysts for carbon nanotube synthesis: The present invention relates to a method for forming metal-silicide catalyst nanoparticles with controllable diameter. The method according to embodiments of the invention leads to the formation of ‘active’ metal-suicide catalyst nanoparticles, with which is meant that they are suitable to be used as a catalyst in carbon nanotube growth.... Agent: Knobbe Martens Olson & Bear LLP

20100285657 - Growth reactor for gallium-nitride crystals using ammonia and hydrogen chloride: The present invention in one preferred embodiment discloses a new design of HVPE reactor, which can grow gallium nitride for more than one day without interruption. To avoid clogging in the exhaust system, a second reactor chamber is added after a main reactor where GaN is produced. The second reactor... Agent: K&l Gates LLPIPDocketing

20100285658 - Integrating a first contact structure in a gate last process: A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the... Agent: Haynes And Boone, LLPIPSection

20100285659 - Method for fabricating dual poly gate in semiconductor device: A method for fabricating a dual poly gate in a semiconductor device, comprising: forming a gate insulation layer and a polysilicon layer on a semiconductor substrate that defines a first region and a second region; implanting first and second conductive type impurity ions into the first region and the second... Agent: Marshall, Gerstein & Borun LLP

20100285660 - Copper deposition for filling features in manufacture of microelectronic devices: A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal thereon, electrolessly depositing copper onto the initial... Agent: Senniger Powers LLP

20100285661 - Semiconductor element and display device using the same: Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor, a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin... Agent: Nixon Peabody, LLP

20100285662 - Methods of fabricating integrated circuit devices including air spacers separating conductive structures and contact plugs: An integrated circuit device includes first and second conductive structures spaced apart from one another on a substrate along a first direction. The first and second conductive structures extend in a second direction substantially perpendicular to the first direction. A contact plug is interposed between the first and second conductive... Agent: Myers Bigel Sibley & Sajovec

20100285663 - Composition and method for low temperature deposition of silicon-containing films such as films including silicon, silicon nitride, silicon dioxide and/or silicon-oxynitride: Silicon precursors for forming silicon-containing films in the manufacture of semiconductor devices, such as low dielectric constant (k) thin films, high k gate silicates, low temperature silicon epitaxial films, and films containing silicon nitride (Si3N4), siliconoxynitride (SiOxNy) and/or silicon dioxide (SiO2). The precursors of the invention are amenable to use... Agent: Intellectual Property / Technology Law

20100285664 - Composition and methods for forming metal films on semiconductor substrates using supercritical solvents: Compositions and methods for forming metal films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing at least one metal precursor comprising at least one ligand, an excess amount... Agent: Buchanan, Ingersoll & Rooney PC

20100285666 - Process sequence to achieve global planarity using a combination of fixed abrasive and high selectivity slurry for pre-metal dielectric cmp applications: A method and apparatus for polishing or planarizing a pre-metal dielectric layer by a chemical mechanical polishing process are provided. The method comprises providing a semiconductor substrate having feature definitions formed thereon, forming a pre-metal dielectric layer over the substrate, wherein the as-deposited pre-metal dielectric layer has an uneven surface... Agent: Patterson & Sheridan, LLP - - Appm/tx

20100285665 - Semiconductor wafer manufacturing method: In a method of manufacturing semiconductor wafers, front and hack surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine that includes: a carrier for accommodating the semiconductor wafer; and an upper press platen and a lower press platen for sandwiching the carrier. The method includes: accommodating... Agent: Holtz, Holtz, Goodman & Chick, PC

20100285667 - Method to preserve the critical dimension (cd) of an interconnect structure: A method of restoring the dielectric constant, loss and leakage of an exposed surface of a low k dielectric material caused during dry etching of the low k dielectric material prior to the removal of the damaged layer by wet etch chemistries is provided. Once restored, the surface of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20100285668 - Technique for compensating for a difference in deposition behavior in an interlayer dielectric material: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop... Agent: Advanced Micro Devices, Inc. C/o Williams, Morgan & Amerson, P.C.

20100285669 - Dry etching method: After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100285670 - Plasma processing apparatus including etching processing apparatus and ashing processing apparatus and plasma processing method using plasma processing apparatus: A diameter of a mounting unit of the stage of an asking processing apparatus is less than a diameter of a mounting unit of the stage of an etching processing apparatus, and the diameter of the mounting unit of the stage of the etching processing apparatus is less than a... Agent: Mcdermott Will & Emery LLP

20100285671 - Strip with reduced low-k dielectric damage: A method for forming etched features in a low-k dielectric layer disposed below the photoresist mask in a plasma processing chamber is provided. Features are etched into the low-k dielectric layer through the photoresist mask. The photoresist mask is stripped, wherein the stripping comprising at least one cycle, wherein each... Agent: Beyer Law Group LLP

20100279434 - Functionalized nitride nanomaterials for electrochemistry and biosensor applications: This invention refers to surface modification/functionalization of Nitride nanomaterials and electrochemistry and optical measurement based upon such functionalized Nitride materials. With this invention a variety of bio-molecules such as DNA, protein, and antigens can be immobilized on the surface for measurement to realize ultra-sensitive chemical- and bio-sensing applications.... Agent: Law Offices Of Lai And Associates, P.C.

20100279435 - Temperature control of chemical mechanical polishing: A chemical mechanical polishing apparatus including a platen for holding a pad having a polishing surface, a subsystem for holding a substrate and the polishing surface together during a polishing step, and a temperature sensor oriented to measure a temperature of the polishing surface, wherein the subsystem accepts the temperature... Agent: Fish & Richardson P.C.

20100279438 - Apparatus and method of in-situ identification for contamination control in semiconductor fabrication: An apparatus is provided that includes a load port for receiving a container that houses a wafer and a detector disposed proximate the load port such that the detector detects a metal characteristic of the wafer. The detected metal characteristic indicates whether the wafer is at a proper location. Also,... Agent: Haynes And Boone, LLPIPSection

20100279437 - Controlling edge emission in package-free led die: Light emitting diode (LED) structures are fabricated in wafer scale by mounting singulated LED dies on a carrier wafer or a stretch film, separating the LED dies to create spaces between the LED dies, applying a reflective coating over the LED dies and in the spaces between the LED dies,... Agent: Philips Intellectual Property & Standards

20100279436 - Inspection method for integrated circuit manufacturing processes: The present disclosure provides a method for manufacturing integrated circuit devices including an electron beam inspection. The method includes forming a silicide region on a substrate. In an embodiment, the silicide region is formed to provide contact to a device feature such as a source or drain region. An electron... Agent: Haynes And Boone, LLPIPSection

20100279439 - Automated substrate handling and film quality inspection in solar cell processing: The present invention generally provides an apparatus and a method for automatically calibrating the placement of fragile substrates into a substrate carrier. Embodiments of the present invention also provide an apparatus and a method for inspecting the fragile substrates prior to processing to prevent damaged substrates from being further processed... Agent: Patterson & Sheridan, LLP - - Appm/tx

20100279441 - Method for fabricating a semiconductor device by considering the extinction coefficient during etching of an interlayer insulating film: The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20100279440 - Nitride semiconductor wafer and method of processing nitride semiconductor wafer: Circular nitride wafers having a diameter larger than 45 mm are made and polished. Gross-polishing polishes the nitride wafers in a pressureless state with pressure less than 60 g/cm2 by lifting up the upper turntable for remedying distortion. Distortion height H at a center is reduced to H≦12 μm. Minute-polishing... Agent: Mcdermott Will & Emery LLP

20100279442 - Semiconductor process evaluation methods including variable ion implanting conditions: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.... Agent: Myers Bigel Sibley & Sajovec

20100279443 - Light emitting diode and fabricating method thereof: A light emitting diode and its fabricating method are disclosed. A light emitting diode epitaxy structure is formed on a substrate, and then the light emitting diode epitaxy structure is etched to form a recess. The recess is then filled with a transparent dielectric material. An adhesive layer is utilized... Agent: Ingrassia Fisher & Lorenz, P.C.

20100279444 - Organic electro-luminescence display device and method for fabricating the same: An organic electro-luminance display device includes a first substrate and a second substrate; an array element on the first substrate, the array element including at least one thin film transistor (TFT) in each sub-pixel; a first electrode on the second substrate; a buffer on the first electrode including a first... Agent: Mckenna Long & Aldridge LLP

20100279445 - Transflective type diode substrate and a method for fabrication the same: A transflective diode substrate for a liquid crystal display device, includes: a reflective zone including a diode having a scan electrode, an insulating pattern on the scan electrode and a pixel electrode over the scan electrode, organic patterns around the diode, and a reflection electrode over the organic patterns; and... Agent: Mckenna Long & Aldridge LLP

20100279447 - Dbr laser with improved thermal tuning efficiency: A distributed Bragg reflector (DBR) includes a base substrate and a gain medium formed on the base substrate. A waveguide positioned above the base substrate in optical communication with the gain medium and defines a gap extending between the base substrate and the waveguide along a substantial portion of the... Agent: Workman Nydegger 1000 Eagle Gate Tower

20100279446 - Optical phase conjugation laser diode: A phase-conjugating resonator that includes a semiconductor laser diode apparatus that comprises a phase-conjugating array of retro-reflecting hexagon apertured hexahedral shaped corner-cube prisms, an electrically and/or optically pumped gain-region, a distributed bragg reflecting mirror-stack, a gaussian mode providing hemispherical shaped laser-emission-output metalized mirror. Wherein, optical phase conjugation is used to... Agent: K&l Gates LLP

20100279448 - Method of manufacturing vertical light emitting device: Provided is a method of manufacturing a vertical light emitting device. The method of manufacturing the vertical light emitting device may include forming an emissive layer including a n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a substrate, forming a first trench dividing the emissive layer... Agent: Harness, Dickey & Pierce, P.L.C

20100279450 - Active device array substrate and method for fabricating the same: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20100279449 - Display device provided with semiconductor element and manufacturing method thereof, and electronic device installed with display device provided with semiconductor element: According to one feature of the invention, a region of an insulating film surface at least overlapped with a part of a gate electrode or wiring is coated with an organic agent; a fluid in which conductive fine particles are dispersed in an organic solvent is discharged by a droplet... Agent: Nixon Peabody, LLP

20100279451 - Direct contact heat control of micro structures: A method of providing thermal tuning of microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is disclosed. A heater is provided integrated with the MEMS for controllably heating the MEMS to control performance characteristics thereof.... Agent: Freedman & Associates

20100279452 - Image sensor chip package method: In an image sensor chip package method, a transparent substrate having an upper surface, a lower surface, and through holes is provided. The through holes pass through the transparent substrate. Conductive posts are formed in the through holes. A sealing ring is formed on the lower surface of the transparent... Agent: J C Patents

20100279453 - Method for making an anti-reflection film of a solar cell: A method is disclosed for making an anti-reflection film of a solar cell. The method includes the step of providing a laminate. The laminate includes a ceramic substrate, a titanium-based compound film, a p+ type poly-silicon back surface field, a p− type poly-silicon light-soaking film and an n+ type poly-silicon... Agent: Jackson Intellectual Property Group PLLC

20100279454 - Method of manufacturing a solar cell: A method of manufacturing a solar cell. The method includes the steps of providing a substrate, applying a first dopant to a first surface, applying a second dopant to a second surface, covering the doped first surface with a hard mask, applying a third dopant to the substrate side, removing... Agent: Ibm Corporation, T.j. Watson Research Center

20100279455 - Methods, facilities and simulations for a solar power plant: In an embodiment, the present invention discloses methods and simulations for constructing a solar power plant meeting a criterion of either a desired power selling price or a capital investment. The present methods can provide design considerations for a solar power plant that is affordable and cost effective. For example,... Agent: Tue Nguyen

20100279456 - Compound solar and manufacturing method thereof: On a surface of a GaAs substrate, layers to be a top cell are formed by epitaxial growth. On the top cell, layers to be a bottom cell are formed. Thereafter, on a surface of the bottom cell, a back surface electrode is formed. Thereafter, a glass plate is adhered... Agent: Nixon & Vanderhye, PC

20100279457 - Method for manufacturing a semiconductor light-receiving device: Disclosed is a method for manufacturing a semiconductor light-receiving device having high reproducibility and reliability. Specifically disclosed is a semiconductor light-receiving device 100 with a mesa structure wherein a light-absorbing layer 6, an avalanche multiplication layer 4 and an electric-field relaxation layer 5 are formed on a semiconductor substrate 2.... Agent: Sughrue Mion, PLLC

20100279459 - Method for reducing contact resistance of cmos image sensor: A method for performing a CMOS Image Sensor (CIS) silicide process is provided to reduce pixel contact resistance. In one embodiment, the method comprises forming a Resist Protect Oxide (RPO) layer on the CIS, forming a Contact Etch Stop Layer (CESL), forming an Inter-Layer Dielectric (ILD) layer, performing contact lithography/etching,... Agent: Lowe Hauptman Ham & Berner, LLP (tsmc)

20100279458 - Process for making partially transparent photovoltaic modules: A process for making a partially transparent photovoltaic cell or a partially transparent photovoltaic module comprising series-connected or parallel-connected photovoltaic cells comprises the step of forming a patterned back electrode(s) by screen printing, jet printing, roll-to-roll processing or depositing through a shadow mask with openings. The pattern of the back... Agent: Sughrue Mion, PLLC

20100279460 - Organic thin film transistor: To provide an organic thin film transistor including a pair of electrodes for allowing a current to flow through an organic semiconductor layer made of an organic semiconductor material, and a third electrode, wherein the organic semiconductor material is composed mainly of an arylamine polymer having a weight-average molecular weight... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100279462 - Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like.... Agent: Fitzpatrick Cella Harper & Scinto

20100279461 - Method of fabricating zinc oxide film having matching crystal orientation to silicon substrate: A zinc oxide (ZnO) film is fabricated. Metal-organic chemical vapor deposition (MOCVD) is used to obtain the film with few defects, high integrity and low cost through an easy procedure. The ZnO film above a silicon substrate has a matching crystal orientation to the substrate. Thus, the ZnO film is... Agent: Jackson Intellectual Property Group PLLC

20100279464 - Fabrication method of semiconductor integrated circuit device: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100279463 - Method of forming stacked-die packages: A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure... Agent: Lowe Hauptman Ham & Berner, LLP

20100279465 - Semiconductor manufacturing method of die pick-up from wafer: A manufacturing method of a semiconductor device comprising the steps of: affixing a die attach film and a dicing film to a back surface of a semiconductor wafer: thereafter dicing the semiconductor wafer and the die attach film to divide the semiconductor wafer into a plurality of semiconductor chips: thereafter... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100279466 - Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components: Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals... Agent: Perkins Coie LLP Patent-sea

20100279468 - Laminated film and process for producing semiconductor device: The present invention provides a laminated film which includes a pressure-sensitive adhesive sheet including a pressure-sensitive adhesive layer, and a die-adhering layer laminated on the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet, the laminated film being for use in a production step of a semiconductor device, in which the... Agent: Sughrue-265550

20100279469 - Low-voiding die attach film, semiconductor package, and processes for making and using same: This invention is a low-voiding adhesive film prepared from a composition. The composition comprises a toughening polymer, a curable resin, a curing agent for the curable resin, a void reduction compound, and a curing agent for the void reduction compound. The void reduction compound has at least two Si—O moieties... Agent: Henkel Corporation

20100279467 - Methodology for processing a panel during semiconductor device fabrication: A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel... Agent: Meschkow & Gresham, P.L.C

20100279470 - Package with multiple dies: A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second... Agent: Townsend And Townsend And Crew, LLP

20100279471 - Underfill dispensing system for integrated circuits: A system for dispensing an underfill material between an integrated circuit (IC) chip and a substrate includes a platform at which the underfill material is supplied. The IC chip and the substrate are mounted at the periphery of the platform. The platform rotates and facilitates the movement of the underfill... Agent: Onda Techno Intl. Patent Attys.

20100279472 - Manufacturing method of non-volatile memory: In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region... Agent: Jianq Chyun Intellectual Property Office

20100279473 - Thin film transistor substrate and fabricating method thereof: A thin film transistor substrate and a fabricating method that includes an opening hole that separates a gate shorting line connected to a gate shorting bar used upon a lighting-inspecting of a gate line into an odd and an even gate shorting line is provided.... Agent: Brinks Hofer Gilson & Lione

20100279474 - Method for manufacturing semiconductor device: A formation of a gate electrode provided over an oxide semiconductor layer of a thin film transistor is performed together with a patterning of the oxide semiconductor layer.... Agent: Robinson Intellectual Property Law Office, P.C.

20100279475 - Thin film transistor, display device having thin film transistor, and method for manufacturing the same: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed... Agent: Robinson Intellectual Property Law Office, P.C.

20100279476 - Manufacturing method for field-effect transistor: To provide a manufacturing method for a field-effect transistor, such as a thin-film transistor, enabling reductions in the number patterning steps and the number of photomasks and improvements in the throughput and the yield. In the method, an oxide film is formed by processing the surface of a crystalline semiconductor... Agent: Husch Blackwell Sanders, LLP Husch Blackwell Sanders LLP Welsh & Katz

20100279477 - Method for manufacturing semiconductor device: A highly responsive semiconductor device in which the subthreshold swing (S value) is small and reduction in on-current is suppressed is manufactured. A semiconductor layer in which a thickness of a source region or a drain region is larger than that of a channel formation region is formed. A semiconductor... Agent: Nixon Peabody, LLP

20100279478 - Trench mosfet having trench contacts integrated with trench schottky rectifiers having planar contacts: An integrated configuration comprising trench MOSFET having trench contacts and trench Schottky rectifier having planar contacts is disclosed. The trench contacts for trench MOSFET provide a lower specific on-resistance. Besides, for trench gate connection, planar gate contact is employed in the present invention to avoid shortage issue between gate and... Agent: Bacon & Thomas, PLLC

20100279479 - Formation of raised source/drain on a strained thin film implanted with cold and/or molecular carbon: A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing one or more cold-carbon or molecular carbon ion implantation steps to implant carbon ions within the semiconductor structure to create strain layers on either side of a channel region. Raised... Agent: Varian Semiconductor Equipment Associates

20100279480 - Method of making small geometry features: A method of forming a small geometry feature. The method includes forming a source layer on a top surface of a substrate; forming a mandrel on a top surface of the source layer, the mandrel having a sidewall; sputtering material from the source layer onto the sidewall of the mandrel... Agent: Schmeiser, Olsen & Watts

20100279481 - Control of dopant diffusion from buried layers in bipolar integrated circuits: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the... Agent: Texas Instruments Incorporated

20100279482 - Semiconductor device and method of manufacturing the same: In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed... Agent: Fish & Richardson P.C.

20100279483 - Lateral passive device having dual annular electrodes: A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate... Agent: Hoffman Warnick LLC

20100279484 - Method of making multi-layer structure for metal-insulator-metal capacitor: The present invention discloses a method of making a multi-layer structure for metal-insulator-metal capacitors, in which, a bottom electrode plate layer is formed on a substrate, wherein a Ti/TiN layer serving as a top anti-reflection coating (top ARC) of the bottom electrode plate layer including a titanium layer and a... Agent: North America Intellectual Property Corporation

20100279485 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first contact plug is formed in a first insulating film. A barrier film is formed on the first insulating film. A second insulating film is formed on the barrier film. A support... Agent: Sughrue Mion, PLLC

20100279486 - Nonvolatile memory having conductive film between adjacent memory cells: A floating gate MOS transistor having a conductive floating gate electrode insulated from a semiconductor material having a main surface by a gate dielectric layer. At least one isolation region formed lateral to the gate electrode. An evacuation is formed in the isolation region and beneath the main surface of... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP

20100279488 - Method for preparing soi substrate having backside sandblasted: Provided is a method of preparing an SOI substrate having a backside roughened which the SOI substrate has a reduced number of defects in a silicon layer at the front surface in spite of sandblasting having been applied to the backside of the SOI substrate. Specifically provided is the method... Agent: Myers Bigel Sibley & Sajovec

20100279487 - Method for transferring a layer from a donor substrate onto a handle substrate: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes... Agent: Traskbritt, P.C.

20100279489 - Semiconductor bond pad patterns and method of formation: In a semiconductor wafer, the polyimide film underneath a power metal structure is partially etched to create corresponding surface depressions of the conformal top power metal. The depressions at the surface of power metal are visible under optical microscopy. Arrangement of the depressions in a pattern facilitates the alignment of... Agent: James Jen-ho Wang

20100279490 - Methods and apparatus for laser scribing wafers: A method for singulating dies from a wafer includes laser scribing a continuous line on each side of the die, and laser ablating an area adjacent the laser scribed continuous line on each side of the die. The laser ablations in the area adjacent the laser scribed continuous line on... Agent: Schwegman, Lundberg & Woessner/intel

20100279491 - Die attach film-provided dicing tape and production process of semiconductor device: The present invention provides a die attach film-provided dicing tape, which includes a dicing tape, a supporting tape and a die attach film laminated in this order, wherein the supporting tape is a tape having a self-rolling peelability, and a process for producing a semiconductor device by using the die... Agent: Sughrue-265550

20100279492 - Method of fabricating upgraded metallurgical grade silicon by external gettering procedure: Upgraded metallurgical grade silicon (UMG-Si) is fabricated by a ‘green’ (environmental protected) external gettering procedure. Impurities concentration of the fabricated UMG-Si is reduced for 100 times than its source material. The UMG-Si obtained has a purity ratio reaching 4N to 6N. Thus, substrates made of the UMG-Si can be used... Agent: Jackson Intellectual Property Group PLLC

20100279493 - Doping of semiconductor layer for improved efficiency of semiconductor structures: A system and method for intentional doping, including variable doping, within a semiconductor structure for improved efficiency is described. One embodiment includes a method for forming a semiconductor structure, the method comprising forming a first semiconductor layer, wherein the first semiconductor layer comprises a first semiconductor material, and forming a... Agent: Cooley LLP Attn: Patent Group

20100279494 - Method for releasing a thin-film substrate: The present disclosure relates to methods for selectively etching a porous semiconductor layer to separate a thin-film semiconductor substrate (TFSS) having planar or three-dimensional features from a corresponding semiconductor template. The method involves forming a conformal sacrificial porous semiconductor layer on a template. Next, a conformal thin film silicon substrate... Agent: HulseyIPIntellectual Property Lawyers, P.C.

20100279495 - Method of forming p-type gallium nitride based semiconductor, method of forming nitride semiconductor device, and method of forming epitaxial wafer: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10.... Agent: Venable LLP

20100279496 - Manufacturing method of semiconductor device: To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal... Agent: Mcdermott Will & Emery LLP

20100279497 - Method for manufacturing semiconductor device with a recessed channel: A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region... Agent: Marshall, Gerstein & Borun LLP

20100279498 - Semiconductor structure and method for making the same: A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition... Agent: North America Intellectual Property Corporation

20100279499 - Method for manufacturing a memory: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region,... Agent: North America Intellectual Property Corporation

20100279500 - Semiconductor device and method of fabricating the same: A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitoring region. The monitoring pattern includes sub-patterns that... Agent: F. Chau & Associates, LLC

20100279501 - Semiconductor device and method of manufacturing the same: After a plurality of pads (2) are formed on an insulation film (1), a passivation film (3) is formed on the entire surface thereof, and opening parts (3a) which exposes all the pads (2) are formed in the passivation film (3). Next, another passivation film is formed on the entire... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20100279502 - Method of manufacturing a semiconductor integrated circuit device and a method of manufacturing a thin film probe sheet for using the same: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming... Agent: Miles & Stockbridge PC

20100279503 - Method for producing an electrically conductive connection: A method for producing an electrically conductive connection between a first surface of a semiconductor substrate and a second surface of the semiconductor substrate includes producing a hole, forming an electrically conductive layer that includes tungsten, removing the electrically conductive layer from the first surface of the semiconductor substrate, filling... Agent: Slater & Matsil, L.L.P.

20100279504 - Integrated circuit package system including honeycomb molding: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts and an integrated circuit; providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate;... Agent: Law Offices Of Mikio Ishimaru

20100279505 - Method for fabricating patterns on a wafer through an exposure process: A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First... Agent: Marshall, Gerstein & Borun LLP

20100279507 - method for chemical mechanical polishing a substrate: A method for chemical mechanical polishing of a substrate, comprising: providing a substrate, wherein the substrate comprises silicon dioxide; providing a chemical mechanical polishing composition, wherein the chemical mechanical polishing composition comprises: water, an abrasive; a diquaternary cation according to formula (I); and optionally a quaternary alkylammonium compound; providing a... Agent: Rohm And Haas Electronic Materials Cmp Holdings, Inc.

20100279506 - Polishing silicon carbide: The invention provides a method of chemically-mechanically polishing a substrate comprising at least one layer of single crystal silicon carbide. The method utilizes a chemical-mechanical polishing composition comprising a liquid carrier, an abrasive, a catalyst comprising a transition metal composition, and an oxidizing agent.... Agent: Steven Weseman Associate General Counsel, I.p.

20100279508 - Method for reducing amine based contaminants: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department

20100279509 - Silicon-based hardmask composition and process of producing semiconductor integrated circuit device using the same: t

20100279510 - Etching method and recording medium: An etching method by which a fluorine-added carbon film formed on a substrate is etched by plasma includes a first step of etching the fluorine-added carbon film with plasma of an oxygen-containing processing gas, and a second step of etching the fluorine-added carbon film with plasma of a fluorine-containing processing... Agent: Cantor Colburn, LLP

20100279511 - Wafer through silicon via forming method and equipment therefor: Provided are a wafer through silicon via (TSV) forming method and equipment therefor. The wafer TSV forming method includes the operations of arranging a wafer having a front surface having a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the... Agent: St. Onge Steward Johnston & Reens, LLC

20100279512 - Plasma processing apparatus and method for plasma-processing semiconductor substrate: A plasma processing apparatus includes an antenna unit for generating plasma by using microwaves as a plasma source in such a way that a first region having a relatively high electron temperature of plasma, and a second region having a lower electron temperature of plasma than the first region are... Agent: Cantor Colburn, LLP

20100279514 - Multilayer dielectric: A method forms a first inorganic dielectric layer having a first concentration of defects and a second inorganic dielectric layer in contact with a first layer and having a second lesser concentration of defects.... Agent: Hewlett-packard Company Intellectual Property Administration

20100279513 - Systems and methods for nanowire growth and manufacturing: The present invention is directed to compositions of matter, systems, and methods to manufacture nanowires. In an embodiment, a buffer layer is placed on a nanowire growth substrate and catalytic nanoparticles are added to form a catalytic-coated nanowire growth substrate. Methods to develop and use this catalytic-coated nanowire growth substrate... Agent: Nanosys Inc.

20100279515 - Atomic layer deposition: A method for forming an atomic deposition layer is provided, which includes: (a) performing a first water pulse on a substrate; (b) performing a precursor pulse on the hydroxylated substrate, wherein the precursor reacts with the hydroxyl groups and forms a layer; (c) purging the substrate with an inert carrier... Agent: Birch, Stewart, Kolasch & Birch, LLP

20100279516 - Apparatus and method of aligning and positioning a cold substrate on a hot surface: Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat... Agent: Patterson & Sheridan, LLP - - Appm/tx