|Semiconductor device manufacturing: process patents - Monitor Patents|
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Semiconductor device manufacturing: process July category listing 07/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/29/2010 > patent applications in patent subcategories. category listing
20100190272 - Rework method of metal hard mask: A rework method of a metal hard mask layer is provided. First, a material layer is provided. A dielectric layer, a first metal hard mask layer, and a patterned first dielectric hard mask layer have been sequentially formed on the material layer. There is a defect on a region of... Agent: North America Intellectual Property Corporation
20100190273 - Method for manufacturing high-frequency signal transmission circuit and high-frequency signal transmission circuit device: A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first... Agent: Wolf Greenfield & Sacks, P.C.
20100190276 - Method and apparatus for irradiating laser: A laser irradiation process includes: scanning a substrate with laser having a predetermined lasing frequency at different irradiation intensities to form a plurality of first irradiation areas corresponding to the irradiation intensities; illuminating the first irradiation areas to reflected light receive from the first irradiation areas; determining microcrystallization intensity based... Agent: Dickstein Shapiro LLP
20100190274 - Rtp spike annealing for semiconductor substrate dopant activation: A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first... Agent: Duane Morris LLP (tsmc)IPDepartment
20100190275 - Scribing device and method of producing a thin-film solar cell module: A laser scribing device is provided which comprises at least a laser light source. The laser light source may generate a laser beam for scribing cell lines to form a patterned solar cell module. Furthermore, the laser may emit a light beam for generating a light spot on the surface... Agent: Townsend And Townsend And Crew, LLP
20100190277 - Power network stacked via removal for congestion reduction: A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop... Agent: Bever, Hoffman & Harms, LLP
20100190278 - Testing for correct undercutting of an electrode during an etching step: A probe electrode structure on a substrate is described, comprising a first probe electrode and a neighboring second probe electrode on a layer sequence that generally includes, in a direction from the substrate to the probe electrodes, an electrically conductive bottom layer, an electrically insulating center layer and a electrically... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100190279 - Light emitting device: Methods of making a light emitter are disclosed herein. An embodiment of a method comprises fabricating a line of first leads, the line of first leads comprising a plurality connected individual first leads; fabricating a line of second leads, the line of second leads comprising a plurality of connected individual... Agent: Kathy Manke Avago Technologies Limited
20100190280 - Manufacturing method of light-emitting diode: A manufacturing method of an LED comprises attaching an LED epitaxial wafer (LED wafer) to an expanding tape, dicing the LED wafer on the expanding tape longitudinally and laterally to a certain element size to divide into a plurality of LED elements, expanding the expanding tape to a certain size... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw
20100190281 - Organic electroluminescent device, method of manufacturing the same, and electronic apparatus: An organic electroluminescent device including an organic thin-film transistor element having at least an active layer made of an organic material; and an organic electroluminescent element driven by the organic thin-film transistor element.... Agent: Harness, Dickey & Pierce, P.L.C
20100190282 - Method for manufacturing multiple-wavelength semiconductor laser: A method for manufacturing a multiple-wavelength semiconductor laser comprises: forming a first bar having an array of first semiconductor chips, wherein at least two semiconductor lasers producing light of different wavelengths are monolithically formed; forming a second bar having an array of second semiconductor chips, wherein a semiconductor laser producing... Agent: Leydig Voit & Mayer, Ltd
20100190283 - Method to form semiconductor laser diode with mesa structure buried by current blocking layer: A method to form a an LD with the buried mesa type is disclosed, in which the n-type current blocking layer is stably kept with a distance to the active layer in the buried mesa. The method of the invention includes a step to form the mesa by iterating the... Agent: Smith, Gambrell & Russell
20100190284 - Method of fabricating nitride-based semiconductor optical device: In the method of fabricating a nitride-based semiconductor optical device by metal-organic chemical vapor deposition, a barrier layer is grown at a first temperature while supplying a gallium source to a reactor. The barrier layer comprises a first gallium nitride-based semiconductor. After the growth of the barrier layer, a nitrogen... Agent: Venable LLP
20100190285 - Microeletromechanical systems having stored charge and methods for fabricating and using same: Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on... Agent: Kenyon & Kenyon LLP
20100190286 - Method for manufacturing solar cell: Disclosed is a method for manufacturing a solar cell, which includes the steps of: applying a first diffusing agent containing n-type impurities and a second diffusing agent containing p-type impurities onto a semiconductor substrate; forming a protective layer covering at least one of the first diffusing agent and the second... Agent: Nixon & Vanderhye, PC
20100190287 - Semiconductor image sensor and method for fabricating the same: A semiconductor image sensor includes: a semiconductor imaging element including an imaging area, a peripheral circuit area, and an electrode area; cylindrical electrodes provided on electrode terminals so as to be electrically connected with an external device; and a transparent resin layer provided on the upper surface of the semiconductor... Agent: Mcdermott Will & Emery LLP
20100190288 - Thin silicon or germanium sheets and photovolatics formed from thin sheets: Thin semiconductor foils can be formed using light reactive deposition. These foils can have an average thickness of less than 100 microns. In some embodiments, the semiconductor foils can have a large surface area, such as greater than about 900 square centimeters. The foil can be free standing or releasably... Agent: Dardi & Herbert, PLLC Suite 2000
20100190289 - Solid-state imaging device: An n/p semiconductor substrate is formed in such a manner that an n type semiconductor layer is deposited on a p+ semiconductor substrate. An imaging area including a plurality of n type semiconductor regions making photoelectric conversion and a plurality of p type semiconductor region for isolation formed around the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100190290 - Solar cell patterning and metallization: Embodiments of the present invention generally provide methods for forming conductive structures on the surfaces of a solar cell. In one embodiment, conductive structures are formed on the front surface of a solar cell by depositing a sacrificial polymer layer, forming patterned lines in the sacrificial polymer via a fluid... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100190292 - Method for the preparation of group ib-iiia-via quaternary or higher alloy semiconductor films: This invention relates to a method for producing group IB-IIIA-VIA quaternary or higher alloy semiconductor films wherein the method comprises the steps of (i) providing a metal film comprising a mixture of group IB and group IIIA metals; (ii) heat treating the metal film in the presence of a source... Agent: Knobbe Martens Olson & Bear LLP
20100190291 - Semiconductor memory device with three dimensional solid electrolyte structure, and manufacturing method thereof: The semiconductor memory device includes a variable resistance device having a solid electrolyte in a three-dimensional structure. The variable resistance device includes a first electrode; the solid electrolyte, which has at least two regions with different heights, formed on the first electrode; and a second electrode made of a conductive... Agent: Harness, Dickey & Pierce, P.L.C
20100190293 - Manufacturing method of semiconductor device: applying a static pressure larger than an ambient pressure by 0.05 MPa or more to a stacked body including the adhesive film one or more times, at any point between adhering the wafer to the adhesive film and fixing the chip to the chip mounting substrate.... Agent: Cahn & Samuels LLP
20100190294 - Methods for controlling wafer and package warpage during assembly of very thin die: Various exemplary embodiments provide materials and methods for flip-chip packaging a thin TSV semiconductor die, which uses other packaging components, for example, a second die, as a packaging carrier to attach the thin TSV semiconductor die to a package substrate. Warpage and mis-alignment can be reduced or eliminated during the... Agent: Texas Instruments Incorporated
20100190295 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, includes the steps of: (a) providing a support including a plane having a first region for mounting a chip thereon and a second region provided around the first region; (b) forming an insulating resin layer in a semi-curing state on the plane; (c)... Agent: Rankin, Hill & Clark LLP
20100190296 - Method of manufacturing semiconductor device: The present invention provides a method of manufacturing a semiconductor device in which a thinned substrate of a semiconductor or semiconductor device is handled without cracks in the substrate and treated with heat to improve a contact between semiconductor back surface and metal in a high yield and a semiconductor... Agent: Stevens Law Group
20100190297 - Method of making a semiconductor chip assembly with a post/base heat spreader and a cavity in the post: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the... Agent: David M. Sigmond
20100190298 - Semiconductor device and production method therefor: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver... Agent: Birch Stewart Kolasch & Birch
20100190299 - Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof: A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the... Agent: Slater & Matsil, L.L.P.
20100190300 - Method of making a semiconductor chip assembly with a base heat spreader and a cavity in the base: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the... Agent: David M. Sigmond
20100190301 - Cavity closure process for at least one microelectronic device: m
20100190302 - Electronic packages with fine particle wetting and non-wetting zones: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking... Agent: Trop, Pruner & Hu, P.C.
20100190303 - Semiconductor device having sufficient process margin and method of forming same: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed... Agent: Harness, Dickey & Pierce, P.L.C
20100190305 - Method for forming semiconductor device: A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric... Agent: Marshall, Gerstein & Borun LLP
20100190304 - Semiconductor storage device and method of fabricating the same: A semiconductor storage device, has a first conductive type semiconductor region formed on a semiconductor substrate, a plurality of second conductive type semiconductor regions formed separately from each other on the first conductive type semiconductor region, a plurality of MOSFETs each formed on the plurality of second conductive type semiconductor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100190306 - Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100190307 - High density trench mosfet with single mask pre-defined gate and contact trenches: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench.... Agent: Joshua D. Isenberg Jdi Patent
20100190308 - Electronic device including a fin-type transistor structure and a process for forming the electronic device: An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin... Agent: Larson Newman & Abel, LLP
20100190309 - Method for adjusting the height of a gate electrode in a semiconductor device: By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce... Agent: Williams, Morgan & Amerson
20100190310 - Gap-filling composition with excellent shelf life by end-capping: A composition with improved shelf life for filling small gaps in a semiconductor device is provided. The composition comprises an end-capped silicone polymer. The molecular weight of the end-capped silicone polymer is not varied during storage. In addition, the dissolution rate (DR) of the composition in an alkaline developing solution... Agent: Lee & Morse, P.C.
20100190311 - Method of forming a mems topped integrated circuit with a stress relief layer: The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and... Agent: Law Office Of Mark C. Pickering
20100190312 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device which is higher functional and reliable and a technique capable of manufacturing the semiconductor device with a high yield at low cost without complexing the apparatus or process. At least one of a first conductive layer and a second conductive layer is formed containing one... Agent: Robinson Intellectual Property Law Office, P.C.
20100190313 - Method for manufacturing nonvolatile storage element and method for manufacturing nonvolatile storage device: A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride... Agent: Wenderoth, Lind & Ponack L.L.P.
20100190314 - Methods of forming semiconductor structures: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy... Agent: Wells St. John P.s.
20100190315 - Method of manufacturing semiconductor memory device: There is provided a method of manufacturing a semiconductor memory device. According to the method, a tunnel insulating layer and a charge trap layer are formed in a cell region of a semiconductor substrate defining the cell region and a peripheral region. A gate insulation layer and a first conductive... Agent: Ip & T Law Firm PLC
20100190316 - Method of selective oxygen implantation to dielectricallly isolate semiconductor devices using no extra masks: A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also... Agent: Dergosits & Noah LLP (nsc) Counsel For National Semiconductor Corporation
20100190317 - Semiconductor device manufacturing method and silicon oxide film forming method: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100190318 - Method of recovering and reproducing substrates and method of producing semiconductor wafers: A method of recovering a first substrate, including the steps of: sticking a second substrate on a semiconductor layer epitaxially grown on the first substrate; and separating the semiconductor layer and the first substrate. Furthermore, a method of reproducing a first substrate, including the step of surface processing the first... Agent: Mcdermott Will & Emery LLP
20100190319 - Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the... Agent: Vierra Magen/sandisk Corporation
20100190320 - Methods of removing water from semiconductor substrates and methods of depositing atomic layers using the same: Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing... Agent: Myers Bigel Sibley & Sajovec
20100190321 - Method of fabricating phase-change memory device having tic layer: Provided is a method of fabricating a phase-change memory device. The phase-change memory device includes a memory cell having a switching device and a phase change pattern. The method includes; forming a TiC layer on a contact electrically connecting the switching device using a plasma enhanced cyclic chemical vapor deposition... Agent: Volentine & Whitt PLLC
20100190322 - Compound semiconductor substrate: A substrate for epitaxial growth, which is capable of improving a surface state of an epitaxial layer at microroughness level. In a substrate for epitaxial growth, when haze is defined as a value calculated by dividing intensity of scattered light obtained when light is incident from a predetermined light source... Agent: Birch Stewart Kolasch & Birch
20100190323 - Modifying catalytic behavior of nanocrystals: The present invention provides a method of providing a desired catalyst electron energy level. The method includes providing a donor material quantum confinement structure (QCS) having a first Fermi level, and providing an acceptor QCS material having a second Fermi level, where the first Fermi level is higher than the... Agent: Lumen Patent Firm
20100190324 - Reducing photoresist layer degradation in plasma immersion ion implantation: A method of plasma immersion ion implantation of a workpiece having a photoresist mask on its top surface prevents photoresist failure from carbonization of the photoresist. The method includes performing successive ion implantation sub-steps, each of the ion implantation sub-steps having a time duration over which only a fractional top... Agent: Law Office Of Robert M. Wallace
20100190325 - Semiconductor device having multi-channel and method of fabricating the same: An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate,... Agent: Lowe Hauptman Ham & Berner, LLP
20100190326 - Method for fabricating semiconductor memory device: A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in... Agent: Marshall, Gerstein & Borun LLP
20100190328 - Self aligned silicided contacts: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is... Agent: Slater & Matsil LLP
20100190327 - Semiconductor device manufacturing method and design support apparatus: A semiconductor device manufacturing method includes: forming a conductive film over a substrate; forming an assist pattern on the conductive film; forming a metal film to cover the conductive film and the assist pattern; etching back the metal film to form at least one side wall film on a side... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100190329 - Method and structure for performing a chemical mechanical polishing process: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface... Agent: Townsend And Townsend And Crew, LLP
20100190330 - Nonvolatile semiconductor device and method of manufacturing nonvolatile semiconductor device: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate,... Agent: Mcdermott Will & Emery LLP
20100190331 - System for depositing a film onto a substrate using a low vapor pressure gas precursor: A method for depositing a film onto a substrate is provided. The substrate is contained within a reactor vessel at a pressure of from about 0.1 millitorr to about 100 millitorr. The method comprises subjecting the substrate to a reaction cycle comprising i) supplying to the reactor vessel a gas... Agent: Dority & Manning, P.A.
20100190332 - Method of forming a copper topped interconnect structure that has thin and thick copper traces: A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide... Agent: Law Office Of Mark C. Pickering
20100190333 - Method of forming connection terminal: A method of forming a connection terminal may include preparing a substrate, forming a first conductor of a tube shape having an opened upper portion on the substrate, forming a second conductor on the first conductor, and annealing the second conductor so that a portion of the second conductor extends... Agent: Stanzione & Kim, LLP
20100190334 - Three-dimensional semiconductor structure and method of manufacturing the same: A semiconductor circuit structure includes a support substrate which carries an interconnect region and electronic circuitry. The semiconductor circuit structure includes a device substrate coupled to the interconnect region through a conductive bonding layer. The device substrate includes a planarized surface which faces the conductive bonding layer. The device substrate... Agent: Schmeiser Olsen & Watts
20100190335 - Method of manufacturing semiconductor device: In a method of manufacturing a semiconductor device according to the present invention, a wiring trench is formed on the surface of an insulating film, and the inner surface of this wiring trench is thereafter coated with an alloy film made of an alloy material containing copper and a prescribed... Agent: Rabin & Berdo, PC
20100190336 - Semiconductor device manufacturing method: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100190337 - Method of forming metal wirings of semiconductor device: A method of forming metal wirings of a semiconductor device includes providing a semiconductor substrate having a number of underlying conductive patterns separated from each other with a first insulating layer interposed between the underlying conductive patterns. The method also includes forming auxiliary patterns over the underlying conductive patterns, respectively,... Agent: Marshall, Gerstein & Borun LLP
20100190338 - Method for manufacturing semiconductor device: An insulator layer is formed on a part of semiconductor substrate to form an isolation layer that insulates and separates active elements from each other in the first region, and to form a dummy portion which is composed of a base material of the semiconductor substrate exposed in the insulator... Agent: Rabin & Berdo, PC
20100190339 - Compositions and methods for chemical-mechanical polishing of phase change materials: The present invention provides a chemical-mechanical polishing (CMP) composition suitable for polishing a substrate comprising a phase change material (PCM), such as a germanium-antimony-tellurium (GST) alloy. The composition comprises a particulate abrasive material in combination with lysine, an optional oxidizing agent, and an aqueous carrier therefor. CMP methods for polishing... Agent: Steven Weseman Associate General Counsel, I.p.
20100190341 - Apparatus, method for depositing thin film on wafer and method for gap-filling trench using the same: Provided are an apparatus and method for depositing a thin film, and a method for gap-filling a trench in a semiconductor device. The thin film depositing apparatus includes a plurality of substrates provided on the same space inside a reactor, wherein deposition of the thin film and partial etching of... Agent: Ladas & Parry LLP
20100190343 - Load lock having secondary isolation chamber: A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second... Agent: Knobbe, Martens, Olson & Bear LLP
20100190340 - Methods of forming fine patterns using a nanoimprint lithography: In a method of forming fine patterns, a photocurable coating layer is formed on a substrate. A first surface of a template makes contact with the photocurable coating layer. The first surface of the template includes at least two first patterns having a first dispersion degree of sizes, and at... Agent: Mills & Onello LLP
20100190344 - Methods of forming semiconductor constructions: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed... Agent: Wells St. John P.s.
20100190342 - Pattern generating method, method of manufacturing semiconductor device, computer program product, and pattern-shape-determination-parameter generating method: A pattern generating method includes: extracting, from a shape of a pattern generated on a substrate, a contour of the pattern shape; setting evaluation points as verification points for the pattern shape on the contour; calculating curvatures on the contour in the evaluation points; and verifying the pattern shape based... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100190345 - Selective etch-back process for semiconductor devices: A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to... Agent: Slater & Matsil, L.L.P.
20100190346 - Method of processing resist, semiconductor device, and method of producing the same: A surface component film (2) is etched using a resist (3) as a mask, and the surface component film (2) is patterned according to the shape of an aperture (3a). This results in a step portion (4) having the same shape as the aperture (3a), with the sidewall (4a) of... Agent: Kratz, Quintos & Hanson, LLP
20100190348 - Manufacturing method of semiconductor substrate and substrate processing apparatus: A first processing gas containing a first element and a second processing gas containing a second element are alternately supplied to a surface of a substrate placed in a processing chamber, to thereby form a first thin film, and a second processing gas and a third processing containing the first... Agent: Oliff & Berridge, PLC
20100190347 - Removal chemistry for selectively etching metal hard mask: Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100190349 - Method for backside polymer reduction in dry-etch process: A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture,... Agent: Duane Morris LLP (tsmc)IPDepartment
20100190350 - Plasma etching apparatus, plasma etching method and storage medium: A plasma etching method for forming a hole in an etching target film by a plasma processing apparatus is provided. The apparatus includes an RF power supply for applying RF power for plasma generation to at least one of upper and lower electrodes, and a DC power supply for applying... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100190351 - Methods for removing dielectric materials: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric layer, contacting the substrate at a first temperature with an acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate... Agent: Trask Britt, P.C./ Micron Technology
20100190352 - Use of a biased precoat for reduced first wafer defects in high-density plasma process: According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces... Agent: Texas Instruments Incorporated
20100190354 - Interlayer dielectric under stress for an integrated circuit: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD... Agent: Freescale Semiconductor, Inc. Law Department
20100190353 - Nanolayer deposition process: A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self-limiting, then a second step... Agent: Fliesler Meyer LLP
20100190355 - Substrate processing apparatus and manufacturing method of semiconductor device: A substrate processing apparatus, including: a reaction container in which a substrate is processed; a seal cap, brought into contact with one end in an opening side of the reaction container via a first sealing member and a second sealing member so as to seal the opening of the reaction... Agent: Oliff & Berridge, PLC
20100190356 - Reflectors, substrate processing apparatuses and methods for the same: A substrate processing apparatus may include a processing chamber including a plasma generating unit arranged in an upper region thereof. A grid system, which may extract ions from plasma formed by the plasma generating unit and may accelerate the ions to have substantially uniform directivity. The grid system may be... Agent: Harness, Dickey & Pierce, P.L.C07/22/2010 > patent applications in patent subcategories. category listing
20100184239 - Manufacturing method of semiconductor integrated circuit device using magnetic memory: Side wall spacers are formed on side walls of a conductive layer arranged above a tunneling magnetoresistive film, and scattered substances of a material constituting the tunneling magnetoresistive film during processing are deposited. Thereafter, by removing the side wall spacers, the redepositions of the material are also removed. The side... Agent: Miles & Stockbridge PC
20100184240 - Semiconductor device and method of manufacturing the same: Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of: forming a hydrogen diffusion preventing insulating film covering capacitors; forming a capacitor protecting insulating film on the hydrogen diffusion preventing insulating film; and forming a first insulating film on the capacitor protecting insulating film by a... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100184241 - Method for manufacturing thin type light emitting diode assembly: A method is applied to manufacture a thin type light emitting diode (LED) assembly, and comprises the steps of: pressing a light-transmissible conductive film onto a carrier; etching an etched circuit on the light-transmissible conductive film to form an etched light-transmissible conductive film; bonding a LED chip on the etched... Agent: Rosenberg, Klein & Lee
20100184243 - Mask applied to a workpiece: A method of fabricating a workpiece is disclosed. A material defining apertures is applied to a workpiece. A species is introduced to the workpiece through the apertures and the material is removed. For example, the material may be evaporated, may form a volatile product with a gas, or may dissolve... Agent: Varian Semiconductor Equipment Assc., Inc.
20100184242 - Method of implantation: Provided is a method of implanting dopant ions to an integrated circuit. The method includes forming a first pixel and a second pixel in a substrate, forming an etch stop layer over the substrate, forming a hard mask layer over the etch stop layer, patterning the hard mask layer to... Agent: Haynes And Boone, LLPIPSection
20100184244 - Systems and methods for depositing patterned materials for solar panel production: Method and system for forming one or more predetermined patterns on a substrate for making a photovoltaic device. The method includes aligning at least a first droplet source with a substrate, dispensing one or more first droplets associated with one or more first materials from the first droplet source, and... Agent: Jones Day
20100184245 - Method for manufacturing a bolometric detector: The method is designed for manufacturing a bolometric detector equipped with a membrane suspended above a substrate by means of heat-insulating arms fixed to the substrate by anchoring points. The membrane has a heat-sensitive thin layer with a base comprising at least a semiconducting iron oxide. The method comprises at... Agent: Oliff & Berridge, PLC
20100184246 - Method for manufacturing solid-state image pick-up device: There is provided a method for manufacturing a solid-state image device which includes the steps of: forming a silicon epitaxial growth layer on a silicon substrate; forming photoelectric conversion portions, transfer gates, and a peripheral circuit portion in and/or on the silicon epitaxial growth layer and further forming a wiring... Agent: Sonnenschein Nath & Rosenthal LLP
20100184247 - Semiconductor chip having a photodiode, semiconductor device and manufacturing method thereof: A semiconductor chip that has a photodiode formed on it, a semiconductor device including the semiconductor chip, and manufacturing methods thereof. A second semiconductor region 11 is formed in light-receiving region R of first semiconductor region 10. First bumps 12 are formed outside light-receiving region R. Second bump 13 is... Agent: Texas Instruments Incorporated
20100184248 - Creation and translation of low-relieff texture for a photovoltaic cell: Low-relief texture can be created by applying and firing frit paste on a silicon surface. Where frit contacts the surface at high temperature, it etches silicon, dissolving silicon in the softened glass frit. The result is a series of small, randomly located pits, which produce a near-Lambertian surface, suitable for... Agent: The Mueller Law Office, P.C.
20100184249 - Continuous deposition process and apparatus for manufacturing cadmium telluride photovoltaic devices: A continuous deposition process and apparatus for depositing semiconductor layers containing cadmium, tellurium or sulfur as a principal constituent on transparent substrates to form photovoltaic devices as the substrates are continuously conveyed through the deposition apparatus is described. The film deposition process for a photovoltaic device having an n-type window... Agent: Bing K. Yen
20100184250 - Self-aligned selective emitter formed by counterdoping: An improved method of doping substrates, such as a solar cell, is disclosed. Conductors, such as metal lines, are often deposited on the surface of a substrate. In some embodiments, the conductivity of the substrate beneath the conductors is different than the conductivity of other regions of the substrate. Therefore,... Agent: Nields, Lemack & Frame, LLC
20100184251 - Plasma inside vapor deposition apparatus and method for making multi-junction silicon thin film solar cell modules and panels: A plasma inside vapor deposition apparatus for making silicon thin film solar cell modules including means for supporting a substrate, the substrate having an outer surface and an inner surface; plasma torch means located proximal to the inner surface for depositing at least one thin film layer on the inner... Agent: Patton Boggs LLP
20100184252 - Method for manufacturing organic thin film transistor and organic thin film transistor: A method for manufacturing an organic thin film transistor having excellent characteristics by a simple process, and an organic thin film transistor are provided. In a manufacture method of an organic thin film transistor element having a gate electrode, a gate insulation layer, an organic semiconductor layer and a source... Agent: Sidley Austin LLP
20100184254 - Method for manufacturing semiconductor device: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost. A method for manufacturing a semiconductor device includes the following steps:... Agent: Cook Alex Ltd
20100184253 - Process for manufacturing thin film transistor: Disclosed is a process for manufacturing a thin film transistor, the process comprising the steps of providing an oxide semiconductor precursor solution for an oxide semiconductor layer in which an oxide semiconductor precursor is dissolved in a solvent, coating the oxide semiconductor precursor solution on a substrate to form an... Agent: Cantor Colburn, LLP
20100184255 - Manufacturing method for package structure: A manufacturing method for package structure is provided. The manufacturing method includes the follow steps. Firstly, a substrate is provided. Next, a number of chips are provided. Then, the chips are electrically connected with the substrate. After that, the chips are encapsulated with a sealant, so that the chips and... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100184256 - Resin sealing method of semiconductor device: A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization... Agent: Rankin, Hill & Clark LLP
20100184257 - Method of manufacturing semiconductor device: There is provided a method of manufacturing a semiconductor device. The method includes the successive steps of: (a) providing a semiconductor substrate; (b) forming a plurality of semiconductor chips having electrode pads on the semiconductor substrate; (c) forming internal connection terminals on the electrode pads; (d) forming an insulating layer... Agent: Rankin, Hill & Clark LLP
20100184258 - Method and apparatus for forming an integrated circuit electrode having a reduced contact area: A method and an apparatus for manufacturing a memory cell having a nonvolatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is... Agent: Round Lerner, David, Littenberg, Krumholz & Mentlik, LLP
20100184259 - Method for fabricating a 3-d integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an... Agent: Vierra Magen/sandisk Corporation
20100184260 - Dual high-k oxides with sige channel: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a... Agent: Hamilton & Terrile, LLP - Freescale
20100184261 - Semiconductor device and method for manufacturing the same: There is provided a semiconductor device including: convex semiconductor layers formed on a semiconductor substrate via an insulating film; gate electrodes formed on a pair of facing sides of the semiconductor layers via a gate insulating film; a channel region formed of silicon between the gate electrodes in the semiconductor... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100184262 - High electron mobility transistor having self-aligned miniature field mitigating plate and protective dielectric layer and fabrication method thereof: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source... Agent: Posz Law Group, PLC
20100184263 - Methods of fabricating flash memory devices having shared sub active regions: Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub... Agent: Myers Bigel Sibley & Sajovec
20100184264 - Manufacturing method of semiconductor power devices: Disclosed is a power semiconductor device, in particular, a trench type power semiconductor device for use in power electronic devices. A method of manufacturing the same is provided. The method of manufacturing the power semiconductor device adopts a trench MOSFET to decrease the size of the device, in place of... Agent: Christopher Paul Mitchell
20100184266 - method of manufacturing a non-volatile nand memory semiconductor integrated circuit: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100184265 - Methods for fabricating semiconductor devices minimizing under-oxide regrowth: Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)
20100184268 - Method for producing a semiconductor device having a portion in which a groove is embedded with an oxide film: A coating composition for forming an oxide film, which can suppress the phenomenon of an increased wet etching rate caused by a part of the SOG film embedded inside a groove becoming low-density, and which can suppress the volume expansion coefficient to a low level, and a method for producing... Agent: Young & Thompson
20100184267 - Method of forming silicon oxide film and method of production of semiconductor memory device using this method: To form a good quality silicon oxide film provided with both a superior Qbd characteristic and Rd characteristic, a wafer W is loaded into a plasma treatment apparatus where the surface of a silicon layer 501 of the wafer W is treated by plasma oxidation to form on the silicon... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100184269 - Method for manufacturing soi substrate and semiconductor device: To provide a method for manufacturing a semiconductor substrate provided with a single crystal semiconductor layer which can be used practically even when a substrate with a low upper temperature limit, such as a glass substrate, is used. An oxide film is formed on a single crystal semiconductor substrate; accelerated... Agent: Robinson Intellectual Property Law Office, P.C.
20100184270 - Method for producing bonded wafer: A bonded wafer is produced by comprising a step of implanting oxygen ions from a surface of a wafer for active layer to form an oxygen ion implanted layer at a given position inside the wafer for active layer; a step of bonding the wafer of active layer to a... Agent: Townsend And Townsend And Crew, LLP
20100184271 - Laser processing method and chip: An object to be processed 1 is irradiated with laser light while locating a converging point within a silicon wafer 11, and the converging point is relatively moved along a line to cut 5, so as to form modified regions M1, M2 positioned within the object 1 along the line... Agent: Drinker Biddle & Reath (dc)
20100184272 - Semiconductor die singulation method: In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700
20100184273 - Group iii nitride compound semiconductor device: Disclosed is a group III nitride compound semiconductor device having a substrate, buffer layers on the substrate, and a group III nitride compound semiconductor layer on the top layer of the buffer layers. The buffer layers comprises a first buffer layer formed on the substrate and a second buffer layer... Agent: H.c. Park & Associates, PLC
20100184274 - Method for manufacturing a transistor with parallel semiconductor nanofingers: A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20100184275 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100184276 - Low-temperature formation of polycrystalline semiconductor films via enhanced metal-induced crystallization: A method for forming polycrystalline semiconductor film from amorphous semiconductor film at reduced temperatures and/or accelerated rates. The inclusion of a small percentage of semiconductor material, such as 2% within the metal layer, reduces the temperatures required for crystallization of the amorphous semiconductor by at least 50° C. in comparison... Agent: John P. O'banion O'banion & Ritchey LLP
20100184277 - Method of fabricating semiconductor device: A semiconductor device is fabricated by forming a first crystalline region by irradiating a laser beam to a first region of an amorphous semiconductor film by relatively moving the laser beam with respect to the first region of the amorphous semiconductor film. A second crystalline region is formed by irradiating... Agent: Fish & Richardson P.C.
20100184278 - Method for epitaxial growth: There is provided a method for epitaxial growth, wherein a quantum dot is formed on an epitaxial layer using a quantum-dot forming material with an excellent lattice matching property, and the formed quantum dot is positioned on a defect in the epitaxial layer, thereby minimizing transfer of the defect into... Agent: Jae Y. Park
20100184279 - Method of making an epitaxial structure having low defect density: A method of making an epitaxial structure includes: (a) forming laterally a first epitaxial layer on a base layer, the first epitaxial layer having an epitaxial surface; (b) etching the first epitaxial layer using a wet etching agent so that the epitaxial surface has a plurality of first recesses; (c)... Agent: Whyte Hirschboeck Dudek S C Intellectual Property Department
20100184280 - Method of forming metal ion transistor: A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the... Agent: Hoffman Warnick LLC
20100184281 - Method for treating layers of a gate stack: A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer,... Agent: Haynes And Boone, LLPIPSection
20100184282 - Methods of manufacturing semiconductor memory devices: A method of manufacturing a semiconductor memory device, the method including forming a tunnel insulation layer on a substrate, forming a preliminary charge trapping layer on the tunnel insulation layer, forming an etch stop layer on the preliminary charge trapping layer, wherein a portion of the preliminary charge trapping layer... Agent: Lee & Morse, P.C.
20100184283 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device comprises forming a gate insulating layer on a semiconductor substrate, forming silicon seed crystals on a surface of the gate insulating layer by reacting a nitrogen or oxygen atmosphere gas and a silicon source gas, forming a first layer for a floating... Agent: Marshall, Gerstein & Borun LLP
20100184284 - Method of manufacturing semiconductor memory device: A method of manufacturing a semiconductor memory device comprises providing a semiconductor substrate, forming gate lines over the semiconductor substrate, wherein each of the gate lines has a stack structure comprising an upper layer having a blocking layer formed on a polysilicon layer, forming a dielectric interlayer between the gate... Agent: Marshall, Gerstein & Borun LLP
20100184285 - Method to prevent corrosion of bond pad structure: There is provided a method of fabrication an integrated circuit comprising providing a substrate with a bond pad formed thereover, the bond pad having a top surface for the formation of bonding connections. A passivation layer is provided over the bond pad followed by an overlying masking layer. The passivation... Agent: HorizonIPPte Ltd
20100184286 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device comprises forming a metal wiring on a semiconductor substrate, forming an insulating film over the semiconductor substrate with the metal wiring, forming a through hole in the insulating film, performing sputter-etching to enlarge an cross section of the through hole, and forming a... Agent: Young & Thompson
20100184287 - Method of forming patterns of semiconductor device: A method of forming patterns of a semiconductor device includes forming a hard mask layer and a first sacrificial layer over a first region and a second region of a semiconductor substrate, etching the first sacrificial layer to form a first sacrificial pattern having a first width in the first... Agent: Marshall, Gerstein & Borun LLP
20100184288 - Method of forming pattern structure: A method of forming a pattern structure includes forming a thin film pattern on a substrate, the thin film pattern including depression portions with first bottom widths, forming a protection layer on the thin film pattern by implanting ions into the thin film pattern, and etching a lower portion of... Agent: Lee & Morse, P.C.
20100184289 - Substrate and method of manufacturing the same: A photosensitive transparent resin film, provided selectively with a groove reaching a transparent substrate is formed on the transparent substrate, and a wiring portion is provided in the groove substantially in flush with the photosensitive transparent resin film. The wiring portion can be formed quickly while controlling the thickness easily... Agent: Birch Stewart Kolasch & Birch
20100184290 - Substrate support with gas introduction openings: Embodiments disclosed herein generally relate to an apparatus and a method for placing a substrate substantially flush against a substrate support in a processing chamber. When a large area substrate is placed onto a substrate support, the substrate may not be perfectly flush against the substrate support due to gas... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100184293 - Planarization process for pre-damascene structure including metal hard mask: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP... Agent: Jianq Chyun Intellectual Property Office
20100184292 - Systems, methods and slurries for chemical-mechanical rough polishing of gaas wafers: Chemical polishing systems, methods and slurries are disclosed for the chemical-mechanical rough polishing of GaAs wafers. An exemplary polishing slurry consistent with the innovations herein may comprise dichloroisocyanurate, sulfonate, pyrophosphate, bicarbonate and silica sol. An exemplary chemical polishing method may comprise polishing a wafer in a chemical polishing apparatus in... Agent: Dla Piper LLP (us )
20100184294 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The... Agent: Myers Bigel Sibley & Sajovec
20100184295 - Multiple depth shallow trench isolation process: A method for manufacturing a semiconductor die may have the steps of:—Providing a semiconductor substrate;—Processing the substrate to a point where shallow trench isolation (STI) can be formed;—Depositing at least one underlayer having a predefined thickness on the wafer;—Depositing a masking layer on top of the underlayer;—Shaping the masking layer... Agent: King & Spalding LLP
20100184297 - Method for protecting semiconductor wafer and process for producing semiconductor device: [Means for Solution] A wafer, on which the dry etching reaction products remain, is protected by the reaction products. The wafer is held in an inert gas protective atmosphere having a pressure of 50 Pa or more and an atmospheric pressure or less, or is held in air equivalent to... Agent: Birch Stewart Kolasch & Birch
20100184296 - Semiconductor device manufacturing method, wafer treatment system, and recording medium: A semiconductor device manufacturing method includes loading plural dry-etched wafers one by one in a container having a side door so as to be disposed substantially horizontally and in layers vertically therein; and blowing out a purge gas horizontally to those wafers loaded in the container for 30 sec or... Agent: Mcginn Intellectual Property Law Group, PLLC
20100184298 - Composite showerhead electrode assembly for a plasma processing apparatus: A showerhead electrode for a plasma processing apparatus includes an interface gel between facing surfaces of an electrode plate and a backing plate. The interface gel maintains thermal conductivity during lateral displacements generated during temperature cycling due to mismatch in coefficients of thermal expansion. The interface gel comprises, for example,... Agent: Buchanan, Ingersoll & Rooney PC
20100184299 - Substrate processing method: There is provided a substrate processing method to suppress popping while increasing the throughput in a photoresist removing process. The substrate processing method comprises: loading a substrate, which is coated with photoresist into which a dopant is introduced, into a process chamber; heating the substrate; supplying a reaction gas to... Agent: Brundidge & Stanger, P.C.
20100184300 - Self-aligned masks using multi-temperature phase-change materials: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning... Agent: Marger Johnson & Mccollom/parc
20100184301 - Methods for preventing precipitation of etch byproducts during an etch process and/or subsequent rinse process: Methods for processing a microelectronic topography include selectively etching a layer of the topography using an etch solution which includes a fluid in a supercritical or liquid state. In some embodiments, the etch process may include introducing a fresh composition of the etch solution into a process chamber while simultaneously... Agent: Daffer Mcdaniel LLP
20100184302 - Method of forming conformal dielectric film having si-n bonds by pecvd: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the... Agent: Knobbe Martens Olson & Bear LLP
20100184303 - Method for revealing emergent dislocations in a germanium-base crystalline element: The invention relates to a method for detecting defects, more particularly emergent dislocations of an element having at least one crystalline germanium-base superficial layer. The method comprises an annealing step of the element in an atmosphere having a base that is a mixture of at least an oxidizing gas and... Agent: Oliff & Berridge, PLC07/15/2010 > patent applications in patent subcategories. category listing
20100178714 - Method of forming magnetic memory device: There are provided a magnetic memory device and a method of forming the magnetic memory device. The method of forming the magnetic memory device includes sequentially forming a first magnetic conductor, a tunnel barrier layer, and a second magnetic conductor on a substrate, forming a mask pattern on the second... Agent: Mills & Onello LLP
20100178715 - Mram with storage layer and super-paramagnetic sensing layer: An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external... Agent: Saile Ackerman LLC
20100178716 - Method and apparatus to remove a segment of a thin film solar cell structure for efficiency improvement: The present inventions relate to methods and apparatus for detecting and mechanically removing defects and a surrounding portion of the photovoltaic layer and the substrate in a thin film solar cell such as a Group IBIIIAVIA compound thin film solar cell to improve its efficiency.... Agent: Pillsbury Winthrop Shaw Pittman LLP
20100178717 - Method of manufacturing mems device: A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas... Agent: Harness, Dickey & Pierce, P.L.C
20100178718 - Methods for improving performance variation of a solar cell manufacturing process: A method for optimizing a solar cell manufacturing process is described. The method includes determining a reference finger spacing value and a reference bulk lifetime for the solar cell manufacturing process. The method also includes measuring an actual bulk lifetime of a wafer with an in-line measurement tool. The method... Agent: Foley & Lardner LLP
20100178719 - Diamond led devices and associated methods: LED devices incorporating diamond materials and methods for making such devices are provided. One such method may include forming epitaxially a substantially single cyrstal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to... Agent: Thorpe North & Western, LLP.
20100178720 - Method of manufacturing semiconductor light emitting device: A method of manufacturing a semiconductor light emitting device may include forming an insulating layer on a substrate, forming a plurality of first holes in the insulating layer, forming a plurality of GaN rods in the plurality of first holes, and laterally growing an n-GaN layer on the plurality of... Agent: Harness, Dickey & Pierce, P.L.C
20100178721 - Semiconductor device, method for fabricating an electrode, and method for manufacturing a semiconductor device: A semiconductor device includes a p-type nitride semiconductor layer (14); and a p-side electrode (18) including a palladium oxide film (30) connected to a surface of the nitride semiconductor layer (14).... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100178722 - Methods and applications of non-planar imaging arrays: System, devices and methods are presented that provide an imaging array fabrication process method, comprising fabricating an array of semiconductor imaging elements, interconnecting the elements with stretchable interconnections, and transfer printing the array with a pre-strained elastomeric stamp to a secondary non-planar surface.... Agent: Gtc Law Group LLP & Affiliates
20100178723 - Method and structure for fabricating solar cells using a thick layer transfer process: A photovoltaic cell device, e.g., solar cell, solar panel, and method of manufacture. The device has an optically transparent substrate comprises a first surface and a second surface. A first thickness of material (e.g., semiconductor material, single crystal material) having a first surface region and a second surface region is... Agent: Townsend And Townsend And Crew, LLP
20100178724 - Organic electroluminescent display and method of fabricating the same: An organic electroluminescent display (“OELD”) includes an organic light-emitting diode (“OLED”), a circuit region, and an interlayer dielectric (“ILD”) layer. The OLED is disposed in each of a plurality of pixels arranged on a substrate. The circuit region includes two or more thin film transistors (“TFTs”) and a storage capacitor.... Agent: Cantor Colburn, LLP
20100178725 - Solid state image pickup device: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the... Agent: Robert J. Depke Lewis T. Steadman
20100178726 - Conductive paste, solar cell manufactured using conductive paste, screen printing method and solar cell formed using screen printing method: The conductive paste contains a conductive metal powder and an organic vehicle. The conductive paste has characteristics that the viscosity falls within the range of 200 Pa·s to 350 Pa·s when the shear rate of 10 s−1 is applied and within the range of 80 Pa·s to 120 Pa·s when... Agent: Hogan Lovells US LLP
20100178728 - Aryl dicarboxylic acid diimidazole-based compounds as n-type semiconductor materials for thin film transistors: A process for fabricating a thin film semiconductor device includes the following steps, but not necessarily in the noted order. Firstly, a thin film of organic semiconductor material is deposited onto a substrate. This thin film of organic semiconductor material comprises organic semiconductor material that comprises one or more aryl... Agent: Raymond L. Owens Patent Legal Staff
20100178727 - Method of manufacturing organic film transistor: A method of fabricating an organic thin film transistor exhibiting excellent semiconductor performance by which an organic TFT can be formed continuously on a flexible base such as a polymer support through a simple coating process, and thus the fabrication cost can be reduced sharply, and an organic semiconductor layer... Agent: Lucas & Mercanti, LLP
20100178729 - Resistance-type random access memory device having three-dimensional bit line and word line patterning: Provided is a resistance random access memory device and a method of fabricating, the same. The method includes forming a bit-line stack in which a plurality of local bit-lines are vertically stacked on a substrate, forming a word-line including a plurality of local word-lines that extend in a vertical direction... Agent: Myers Bigel Sibley & Sajovec
20100178730 - Direct-current plasma cvd apparatus and method for producing diamond using the same: The present invention is a direct-current plasma CVD apparatus comprising at least a fixed electrode and a substrate stage having a top flat face and combined with an electrode for placing a substrate, in which the substrate stage top face is not located on a line extended from a center... Agent: Oliff & Berridge, PLC
20100178731 - Semiconductor device having a plurality of semiconductor constructs: A semiconductor device includes a plurality of semiconductor constructs, each of the semiconductor constructs including a semiconductor substrate and external connection electrodes provided on an upper surface of the semiconductor substrate. The semiconductor substrates of the semiconductor constructs are different in a planar-size. The plurality of semiconductor constructs are stacked... Agent: Frishauf, Holtz, Goodman & Chick, PC
20100178732 - Laser bonding for stacking semiconductor substrates: Methods and structures using laser bonding for stacking semiconductor substrates are described. In one embodiment, a method of forming a semiconductor device includes forming a trench in a first substrate, and a bond pad on a second substrate comprising active circuitry. A top surface of the bond pad includes a... Agent: Slater & Matsil, L.L.P.
20100178733 - Thin quad flat package with no leads (qfn) fabrication methods: Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor... Agent: Fountainhead Law Group, PC Chad R. Walsh
20100178734 - Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to... Agent: Yen Jung Sung
20100178735 - Fusible i/o interconnection systems and methods for flip-chip packaging involving substrate-mounted stud bumps: A semiconductor device is made by providing a semiconductor die having bond pads formed on a surface of the semiconductor die, forming a UBM over the bond pads of the semiconductor die, forming a fusible layer over the UBM, providing a substrate having bond pads formed on a surface of... Agent: Robert D. Atkins
20100178736 - Method of fabricating a semiconductor device: One method includes fabricating a semiconductor device including providing a dielectric layer. At least one semiconductor chip is provided defining a first surface including contact elements and a second surface opposite to the first surface. The semiconductor chip is placed onto the dielectric layer with the first surface facing the... Agent: Dicke, Billig & Czaja
20100178737 - Semiconductor ic and its manufacturing method, and module with embedded semiconductor ic and its manufacturing method: A semiconductor IC includes a semiconductor IC main body having a predetermined circuit formed on a main surface, a metal layer selectively provided on substantially the whole back surface of the semiconductor IC main body excluding the periphery. According to the present invention, the metal layer provided on the semiconductor... Agent: Young Law Firm, P.C. Alan W. Young
20100178738 - Transistor, method of fabricating the same and organic light emitting display including the transistor: A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline... Agent: Cantor Colburn, LLP
20100178739 - Integration scheme for an nmos metal gate: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method... Agent: Texas Instruments Incorporated
20100178740 - Bipolar transistors with resistors: Complementary MOS (CMOS) integrated circuits include MOS transistors, resistors and bipolar transistors formed on a common substrate. An emitter region of a bipolar transistor is implanted with a first dopant in an implantation process that implants source/drain regions of an MOS transistor, and is also implanted with a second dopant... Agent: Texas Instruments Incorporated
20100178741 - Access transistor for memory device: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.... Agent: Dickstein Shapiro LLP
20100178742 - Methods of forming nand flash memory with fixed charge: A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may... Agent: Vierra Magen/sandisk Corporation
20100178743 - Method for making asymmetric double-gate transistors: A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100178745 - Flash memory device and fabrication method thereof: The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence... Agent: Marshall, Gerstein & Borun LLP
20100178744 - Manufacture method for semiconductor device whose gate insulating film contains hf and o: An insulating film having Hf and O is formed over a semiconductor substrate. A cap film having oxygen and titanium as constituent elements is formed over the insulating film. The insulating film and cap film are thermally treated in a nitrogen gas or noble gas to diffuse titanium in the... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100178746 - Method of fabricating hetero-junction bipolar transistor (hbt): A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a... Agent: Hoffman Warnick LLC
20100178747 - Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3d wafer-to-wafer modular integration scheme: Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or... Agent: Maxim/bstz Blakely Sokoloff Taylor & Zafman LLP
20100178748 - Methods of etching trenches into silicon of a semiconductor substrate, methods of forming trench isolation in silicon of a semiconductor substrate, and methods of forming a plurality of diodes: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma... Agent: Wells St. John P.s.
20100178749 - Method of fabricating epitaxially grown layers on a composite structure: A method of fabricating materials by epitaxy by epitaxially growing at least one layer of a material upon a composite structure that has at least one thin film bonded to a support substrate and a bonding layer of oxide formed by deposition between the support substrate and the thin film.... Agent: Winston & Strawn LLP Patent Department
20100178750 - Method for producing bonded wafer: A bonded wafer is produced by removing a part or all of native oxide films formed on each surface of both a wafer for active layer and a wafer for support substrate to be bonded; forming a uniform oxide film with a thickness of less than 5 nm on at... Agent: Christensen, O'connor, Johnson, Kindness, PLLC
20100178751 - Laser processing method and semiconductor chip: This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the quality... Agent: Drinker Biddle & Reath (dc)
20100178752 - Semiconductor device and fuse blowout method: A fuse includes a fuse portion laid in such a manner that the direction of each turn of the fuse portion is parallel to the direction in which pads are arranged. The distance between the pads and the fuse portion is defined as the distance between the side of a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100178753 - Silicon wafer and method for manufacturing the same: A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20100178754 - Method of manufacturing cmos transistor: A method of manufacturing a complementary metal-oxide semiconductor (CMOS) transistor includes: forming a semiconductor layer in which an n-MOS transistor region and a p-MOS transistor region are defined; forming an insulation layer on the semiconductor layer; forming a conductive layer on the insulation layer; forming a mask pattern exposing the... Agent: Mills & Onello LLP
20100178755 - Method of fabricating nonvolatile memory device: A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material... Agent: Mills & Onello LLP
20100178756 - Nitride semiconductor device and method for manufacturing the same: A nitride semiconductor device includes: a substrate having a principal surface; a first nitride semiconductor layer formed on the principal surface of the substrate and includes one or more convex portions whose side surfaces are vertical to the principal surface; and a second nitride semiconductor layer selectively grown on the... Agent: Mcdermott Will & Emery LLP
20100178757 - Process simulation method, semiconductor device manufacturing method, and process simulator: A process simulation method includes: converting condition data of plasma doping for introducing an impurity into a semiconductor in a plasma atmosphere to corresponding condition data of ion implantation for implanting impurities as an ion beam into the semiconductor; and calculating device structure data on the basis of the ion... Agent: Turocy & Watson, LLP
20100178759 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer.... Agent: Lee & Morse, P.C.
20100178758 - Methods for fabricating dielectric layer and non-volatile memory: The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein... Agent: J C Patents
20100178760 - Semiconductor device and fabrication method for the same: A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate; a second interlayer insulating film formed on the first interlayer film and including a plurality of grooves; a first barrier metal formed on inner surfaces of the grooves; a first interconnect part and a first bonding... Agent: Foley And Lardner LLP Suite 500
20100178761 - Stacked integrated chips and methods of fabrication thereof: Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the... Agent: Slater & Matsil, L.L.P.
20100178762 - Manufacture method for semiconductor device suitable for forming wirings by damascene method and semiconductor device: An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100178763 - Method and apparatus for fabricating semiconductor device: A method for fabricating a semiconductor device includes the steps of: (a) forming an alloy film containing a precious metal on a substrate having a semiconductor layer or on a conductive film formed on the substrate; (b) heat-treating the substrate to allow the precious metal to react with silicon forming... Agent: Mcdermott Will & Emery LLP
20100178764 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, includes the steps of (a) forming a metal film containing a precious metal on a substrate having a semiconductor layer containing silicon or on a conductive film containing silicon formed on the substrate, (b) after step (a), heat-treating the substrate to allow the... Agent: Mcdermott Will & Emery LLP
20100178767 - Chemical-mechanical polishing composition comprising metal-organic framework materials: The present invention relates to compositions for chemical-mechanical polishing comprising A 0.01% to 40% by weight based on the total amount of the composition of abrasive particles of at least one porous metal-organic framework material, wherein the framework material comprises at least one at least bidentate organic compound which is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100178768 - Controlling passivating film properties using colloidal particles, polyelectrolytes, and ionic additives for copper chemical mechanical planarization: The present invention provides for a copper CMP slurry composition which comprises a complexing agent, an oxidizer, an abrasive and a passivating agent. The present invention also provides for a method of chemical mechanical planarization of a copper conductive structure which comprises administering the copper CMP slurry composition during the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100178766 - High-yield method of exposing and contacting through-silicon vias: An assembly including a main wafer having a body with a front side and a back side, and a handler wafer, is obtained. The main wafer has a plurality of blind electrical vias terminating above the back side. The blind electrical vias have conductive cores with surrounding insulator adjacent side... Agent: Ryan, Mason & Lewis, LLP
20100178765 - Metal polishing slurry and method of polishing a film to be polished: The present invention provides a metal polishing liquid capable of CMP at a high Cu polishing rate and solving the problems: (a) generation of scratches attributable to solid particles, (b) generation of deteriorations in flatness such as dishing and erosion, (c) complexity in a washing process for removing abrasive particles... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100178770 - Method of etching a thin film using pressure modulation: A method for transferring a feature pattern to a thin film on a substrate is described. The method comprises disposing a substrate comprising one or more mask layers overlying a thin film in a plasma processing system, and forming a feature pattern in the one or more mask layers. The... Agent: Tokyo Electron U.s. Holdings, Inc.
20100178769 - Spacer formation for array double patterning: A method for forming an array area with a surrounding periphery area, wherein a substrate is disposed under an etch layer, which is disposed under a patterned organic mask defining the array area and covers the entire periphery area is provided. The patterned organic mask is trimmed. An inorganic layer... Agent: Beyer Law Group LLP
20100178771 - Methods of forming dual-damascene metal interconnect structures using multi-layer hard masks: Methods of forming dual-damascene metal interconnect structures include forming an electrically insulating layer on an integrated circuit substrate and then forming a hard mask layer on the electrically insulating layer. The hard mask layer may include a stacked composite of at least four electrically insulating material layers therein. The hard... Agent: Myers Bigel Sibley & Sajovec
20100178772 - Method of fabricating high-k metal gate devices: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process,... Agent: David M. O Dell Haynes And Boone, LLP
20100178773 - Method of forming semiconductor devices employing double patterning: A first material film is formed on a substrate. Linear second material film patterns are formed on the first material film. Spacer patterns are formed on sidewalls of the second material film patterns, and the second material film patterns are removed to expose portions of the first material film between... Agent: Myers Bigel Sibley & Sajovec
20100178774 - Plasma confinement rings including rf absorbing material for reducing polymer deposition: Plasma confinement rings are adapted to reach sufficiently high temperatures on plasma-exposed surfaces of the rings to substantially reduce polymer deposition on those surfaces. The plasma confinement rings include an RF lossy material effective to enhance heating at portions of the rings. A low-emissivity material can be provided on a... Agent: Buchanan, Ingersoll & Rooney PC
20100178775 - Shower plate sintered integrally with gas release hole member and method for manufacturing the same: A shower plate is disposed in a processing chamber in a plasma processing apparatus, and plasma excitation gas is released into the processing chamber so as to generate plasma. A ceramic member having a plurality of gas release holes having a diameter of 20 μm to 70 μm, and/or a... Agent: Cantor Colburn, LLP
20100178776 - Heat treatment apparatus and method for heating substrate by light-irradiation: A light-emission output of a flash lamp for performing a light-irradiation heat treatment on a substrate in which impurities are implanted is increased up to a target value L1 over a period of time from 1 to 100 milliseconds, is kept for 5 to 100 milliseconds within a fluctuation range... Agent: Ostrolenk Faber Gerb & Soffen07/08/2010 > patent applications in patent subcategories. category listing
20100173431 - Wafer reclamation method and wafer reclamation apparatus: Provided is a wafer reclamation method for reclaiming a semiconductor wafer, on which a different material layer is formed, by removing the different material layer. The wafer reclamation method includes a physically removing step of physically removing the different material layer, a film forming step of forming a film on... Agent: Hamre, Schumann, Mueller & Larson P.C.
20100173432 - Gap maintenance for opening to process chamber: A semiconductor processing apparatus includes a reaction chamber, a movable susceptor, a movement element, and a control system. The reaction chamber includes a baseplate. The baseplate includes an opening. The movable susceptor is configured to hold a workpiece. The movable element is configured to move a workpiece held on the... Agent: Knobbe, Martens, Olson & Bear LLP
20100173433 - Liquid crystal display panel and method of manufacturing the same: The present invention provides a liquid crystal display panel and a method of manufacturing the liquid crystal display panel capable of reducing or eliminating metal erosion in an area in which a conductive dot is formed. In some embodiments, a display panel comprises a common electrode formed on an upper... Agent: Innovation Counsel LLP
20100173434 - Nanocrystal electroluminescence device and fabrication method thereof: A nanocrystal electroluminescence device comprising a polymer hole transport layer, a nanocrystal light-emitting layer and an organic electron transport layer wherein the nanocrystal light-emitting layer is independently and separately formed between the polymer hole transport layer and the organic electron transport layer. According to the nanocrystal electroluminescence device, since the... Agent: Cantor Colburn, LLP
20100173435 - Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same: An array substrate for an IPS mode LCD device comprises a substrate; a gate line along a first direction; a data line along a second direction; a TFT connected to the gate and data lines; a common electrode having a plate shape on the substrate and formed of a first... Agent: Brinks Hofer Gilson & Lione
20100173436 - Method of making biomems devices: A MEMS device is manufactured by first forming a self-aligned monolayer (SAM) on a carrier wafer. Next, a first polymer layer is formed on the self-aligned monolayer. The first polymer layer is patterned form a microchannel cover, which is then bonded to a patterned second polymer layer on a device... Agent: Marks & Clerk
20100173437 - Method of fabricating cmuts that generate low-frequency and high-intensity ultrasound: The present invention provides a method of fabricating low-frequency and high-intensity ultrasound CMUTs that includes using deep reactive ion (DRIE) etching to etch at least one cavity in a first surface of a conductive silicon wafer, growing an insulating layer on at least the first surface of the conductive silicon... Agent: Lumen Patent Firm
20100173438 - Method for manufacturing thermoelectric converter: A method of manufacturing a thermoelectric converter is provided, wherein an alcohol dispersion liquid comprising a ceramic particle having the average size of 1 to 100 nm and a salt of an element constituting the thermoelectric conversion material is prepared, and thereafter the dispersion liquid is dropped into a solution... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100173441 - Method for processing elongate substrates and substrate securing apparatus: A method for processing elongate substrates, including forming a plurality of parallel elongate openings (102) through a semiconductor wafer (104) to form a corresponding plurality of elongate substrates (106) between the openings, each of the elongate substrates (106) having opposite edges coplanar with opposite surfaces of the wafer, opposite faces... Agent: Townsend And Townsend And Crew, LLP
20100173439 - Methods and systems of transferring a substrate to minimize heat loss: A method of transferring one or more substrates between process modules or load lock stations while minimizing heat loss is provided. In some embodiments the method comprising the steps of: identifying a destination location D1 for a substrate S1 present at an initial processing location P1; if the destination location... Agent: Morgan, Lewis & Bockius, LLP. (pa)
20100173440 - Nozzle-based, vapor-phase, plume delivery structure for use in production of thin-film deposition layer: A physical vapor deposition effusion method comprising translating a strip material through a physical vapor deposition zone in a deposition chamber and providing first and second substantially closed vessels located serially along the processing path in the same deposition chamber, each vessel emitting different source materials to produce overlapping plumes... Agent: Ratnerprestia
20100173442 - Image sensor and method for manufacturing the same: An image sensor and a method for manufacturing the same are provided. In the method, a photoresist is formed on a substrate including a photodiode region and a gate electrode opposite to the photodiode region on the basis of the gate electrode. An oxide layer is formed to a specific... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100173443 - Method of manufacturing a photo-detector array device with roic monolithically integrated for laser-radar image signal: A method of manufacturing a photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal. A detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate. In addition, after the... Agent: Rabin & Berdo, PC
20100173444 - Manufacturing method of a photoelectric conversion device: A manufacturing method of a photoelectric conversion device comprises a first step of forming a gate electrode, a second step of forming a semiconductor region of a first conductivity type, a third step of forming an insulation film, and a fourth step of forming a protection region of a second... Agent: Fitzpatrick Cella Harper & Scinto
20100173445 - Production method for a sensor unit of an x-ray detector: A production method for a sensor unit of an X-ray detector is disclosed, which can be implemented easily and precisely, is specified, the sensor unit including a scintillator with photodiodes integrated in its septa for lateral readout. In at least one embodiment of the method, individual scintillator strips are initially... Agent: Harness, Dickey & Pierce, P.L.C
20100173446 - Layered contact structure for solar cells: Formulations and methods of making semiconductor devices and solar cell contacts are disclosed. The invention provides a method of making a semiconductor device or solar cell contact including ink-jet printing onto a silicon wafer an ink composition, typically including a high solids loading (20-80 wt %) of glass fit and... Agent: Rankin, Hill & Clark LLP
20100173447 - Solar cell and method of fabricating the same: A solar cell (100) comprising a semiconductor solar cell substrate (66) having a light receiving surface formed on the first major surface and generating photovoltaic power based on the light impinging on the light receiving surface, wherein the light receiving surface of the semiconductor solar cell substrate (66) is coated... Agent: Oliff & Berridge, PLC
20100173448 - High frequency plasma enhanced chemical vapor deposition: The present invention generally comprises a method for forming a thin film transistor device in a capacitively coupled PECVD processing chamber. The method comprises forming an active layer on a substrate by a method comprising depositing a silicon nitride layer adjacent to the substrate with a first frequency power source,... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100173449 - Methods of fabricating p-i-n diodes, structures for p-i-n diodes and design structure for p-i-n diodes: Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon... Agent: Schmeiser, Olsen & Watts
20100173450 - Matrix type display device with optical material at predetermined positions and manufacturing method thereof: In order to achieve the object, a difference in height, a desired distribution of liquid repellency and affinity to liquid, or a desired potential distribution is formed by utilizing first bus lines in a passive matrix type display device or utilizing scanning lines, signal lines, common current supply lines, pixel... Agent: Oliff & Berridge, PLC
20100173451 - Organic thin film transistor substrate and method of manufacturing the same: The organic thin film transistor according to the present invention comprises a gate line formed on a substrate; a data line which intersects the gate line with an organic gate insulating layer interposed therebetween to define a pixel area; a thin film transistor connected with the gate line and the... Agent: Innovation Counsel LLP
20100173452 - Method to form high efficiency gst cell using a double heater cut: Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation... Agent: Schwabe, Williamson & Wyatt, P.C.
20100173454 - Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member... Agent: Perkins Coie LLP Patent-sea
20100173453 - Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent: Michael J. Ure
20100173455 - Semiconductor device having sealing film and manufacturing method thereof: A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes... Agent: Frishauf, Holtz, Goodman & Chick, PC
20100173456 - Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuit: The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded... Agent: Wells St. John P.s.
20100173457 - Highly scalable thin film transistor: Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20100173458 - Lateral double diffused mosfet transistor with a lightly doped source: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.... Agent: Fish & Richardson P.C.
20100173459 - Multiple doping level bipolar junctions transistors and method for forming: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for... Agent: Hitt Gaines, PC Lsi Corporation
20100173460 - Vertical transistor, memory cell, device, system and method of forming same: A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the substrate and a body region and a second source/drain region are formed within the pillar.... Agent: Trask Britt, P.C./ Micron Technology
20100173461 - Method of fabricating semiconductor device: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including... Agent: Mattingly & Malur, P.C.
20100173462 - Method and apparatus for fabricating a carbon nanotube transistor: A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least... Agent: Wall & Tong, LLP IBM Corporation
20100173463 - Lateral double diffused metal oxide semiconductor: The method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) transistor, includes implanting impurity ions onto a semiconductor substrate to form a drift region and a body region, forming a photoresist pattern to expose a region where an insulating oxide film is to be formed on the semiconductor... Agent: Sherr & Vaughn, PLLC
20100173464 - Non-volatile memory structure and method of fabrication: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least... Agent: Eitan Mehulal Law Group
20100173465 - Semiconductor device having silicide transistors and non-silicide transistors formed on the same substrate and method for fabricating the same: A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma... Agent: Mcdermott Will & Emery LLP
20100173466 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device includes providing a substrate sequentially having a polysilicon layer and an insulating layer formed thereon; patterning the polysilicon layer and the insulating layer to form at least a gate structure on the substrate; forming lightly doped regions in the substrate respectively at two... Agent: North America Intellectual Property Corporation
20100173467 - Thin film and semiconductor device manufacturing method using the thin film: A thin film is used in a semiconductor device manufacturing process. The thin film contains silicon, germanium, and oxygen.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100173468 - Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or... Agent: Dla Piper LLP (us )
20100173469 - Methods of manufacturing charge trap-type non-volatile memory devices: Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A... Agent: Myers Bigel Sibley & Sajovec
20100173470 - Methods of forming a silicon oxide layer and methods of forming an isolation layer: In a method of forming a silicon oxide layer, a spin-on-glass (SOG) layer may be formed on an object including a recess using an SOG composition. The SOG layer may be pre-baked and then cured by contacting with at least one material selected from the group consisting of water, a... Agent: Harness, Dickey & Pierce, P.L.C
20100173471 - Nonvolatile semiconductor memory and fabrication method for the same: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100173472 - Method for manufacturing soi substrate and method for manufacturing semiconductor device: A method for manufacturing an SOI substrate and a method for manufacturing a semiconductor device, in each of which peeling of a single crystal semiconductor layer from an end portion due to laser irradiation is suppressed, are provided. A fragile region is formed in a single crystal semiconductor substrate by... Agent: Robinson Intellectual Property Law Office, P.C.
20100173473 - Method for manufacturing soi substrate and semiconductor device: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is... Agent: Robinson Intellectual Property Law Office, P.C.
20100173474 - Method of manufacturing semiconductor chip: In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, in the semiconductor wafer 1, a protection... Agent: Pearne & Gordon LLP
20100173475 - Method for improving the quality of a sic crystal: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer... Agent: The Webb Law Firm, P.C.
20100173476 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device according to the invention irradiates a first pulse laser beam with an irradiation energy density of 1.0 J/cm2 or higher to blow off particles on the surface of wafer in activating an impurity layer positioned at a shallow location from the surface of... Agent: Rossi, Kimms & Mcdowell LLP.
20100173477 - Method of manufacturing semiconductor device and semiconductor manufacturing apparatus: A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to... Agent: Foley And Lardner LLP Suite 500
20100173478 - Concentric gate nanotube transistor devices: Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube... Agent: Aka Chan LLP
20100173479 - Variable resistance memory devices and methods of forming variable resistance memory devices: Provided are variable resistance memory devices and methods of forming the variable resistance memory devices. The methods can include forming an etch stop layer on an electrode, forming a molding layer on the etch stop layer, forming a recess region including a lower part having a first width and an... Agent: Myers Bigel Sibley & Sajovec
20100173480 - Laser annealing apparatus and semiconductor device manufacturing method: This invention is intended to provide a laser annealing method by employing a laser annealer lower in running cost so as to deal with a large-sized substrate, for preventing or decreasing the generation of a concentric pattern and to provide a semiconductor device manufacturing method including a step using the... Agent: Nixon Peabody, LLP
20100173481 - Laser mask and crystallization method using the same: A crystallization method using a mask includes providing a substrate having a semiconductor layer; positioning a mask over the substrate, the mask having first, second and third blocks, each block having a periodic pattern including a plurality of transmitting regions and a blocking region, the periodic pattern of the first... Agent: Mckenna Long & Aldridge LLP
20100173482 - Method and apparatus for fabricating ib-iiia-via2 compound semiconductor thin films: Methods and apparatus for fabricating IB-IIIA-VIA2 compound semiconductor thin films are provided. A method for fabricating IB-IIIA-VIA2 compound semiconductor thin films includes providing a substrate with a precursor film thereover, wherein the precursor film includes elements of group IB and group IIIA. An annealing process is performed on the substrate... Agent: Quintero Law Office, PC
20100173483 - Gan single-crystal substrate, nitride type semiconductor epitaxial substrate, nitride type semiconductor device, and methods of making the same: The GaN single-crystal substrate 11 in accordance with the present invention has a polished surface subjected to heat treatment for at least 10 minutes at a substrate temperature of at least 1020° C. in a mixed gas atmosphere containing at least an NH3 gas. As a consequence, an atomic rearrangement... Agent: Mcdermott Will & Emery LLP
20100173484 - Safe handling of low energy, high dose arsenic, phosphorus, and boron implanted wafers: A method of preventing toxic gas formation after an implantation process is disclosed. Certain dopants, when implanted into films disposed on a substrate, may react when exposed to moisture to form a toxic gas and/or a flammable gas. By in-situ exposing the doped film to an oxygen containing compound, dopant... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100173485 - Method of manufacturing a non-volatile memory device: A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on the cell region and the peripheral region,... Agent: Lee & Morse, P.C.
20100173486 - Semiconductor device with mushroom electrode and manufacture method thereof: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100173487 - Semiconductor apparatus and method of manufacturing the semiconductor apparatus: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100173488 - Non-volatile memory with erase gate on isolation zones: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1).... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100173489 - Method for manufacturing lower substrate of liquid crystal display device: A method for manufacturing a lower substrate of a liquid crystal display device is disclosed. The method comprises the steps of: (a) forming a patterned first metal layer, a first insulating layer, a patterned second metal layer and a second insulating layer on a substrate in sequence; (b) coating a... Agent: Bacon & Thomas, PLLC
20100173490 - High density plasma chemical vapor deposition process: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be... Agent: North America Intellectual Property Corporation
20100173491 - Method of manufacturing a semiconductor device: A method of forming an insulating layer on an conductive layer; forming a first mask layer and a second mask layer on the insulating layer; forming a resist layer on the second mask layer; patterning the resist layer; patterning the second mask layer by using the resist layer as a... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100173492 - Method of forming semiconductor device patterns: Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first... Agent: Myers Bigel Sibley & Sajovec
20100173494 - Method and apparatus for anisotropic etching: We suggest a method of anisotropic etching of the substrates, where ultra-thin and conformable layers of materials are used to passivate sidewalls of the etched features. According to an exemplary embodiment such sidewall passivation layer is a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. According... Agent: Boris Kobrin
20100173495 - Substrate processing apparatus using a batch processing chamber: Aspects of the invention include a method and apparatus for processing a substrate using a multi-chamber processing system (e.g., a cluster tool) adapted to process substrates in one or more batch and/or single substrate processing chambers to increase the system throughput. In one embodiment, a system is configured to perform... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100173493 - Substrate processing method: The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method... Agent: Cantor Colburn, LLP
20100173496 - Profile and cd uniformity control by plasma oxidation treatment: A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on... Agent: Beyer Law Group LLP
20100173497 - Method of fabricating semiconductor integrated circuit device: A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each... Agent: Mills & Onello LLP
20100173498 - Trim process for critical dimension control for integrated circuits: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist... Agent: Knobbe Martens Olson & Bear LLP
20100173499 - Low k dielectric surface damage control: A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying... Agent: Duane Morris LLP (tsmc)IPDepartment
20100173500 - Semiconductor wafer structure with balanced reflectance and absorption characteristics for rapid thermal anneal uniformity: Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20100173501 - Semiconductor device producing method: Disclosed is a producing method of a semiconductor device, including: loading at least one substrate formed on a surface thereof with a tungsten film into a processing chamber; and forming a silicon oxide film on the surface of the substrate which includes the tungsten film by alternately repeating following steps... Agent: Birch Stewart Kolasch & Birch
20100173502 - Low k1 hole printing using two intersecting features: A method of forming one or more features during semiconductor device fabrication can comprise exposing a photosensitive layer to a first pattern at an exposure energy which is insufficient to fully expose the photosensitive layer, then exposing the photosensitive layer to a second pattern at an exposure energy which is... Agent: Texas Instruments Incorporated
20100173503 - Trap charge equalizing method and threshold voltage distribution reducing method: A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside... Agent: Volentine & Whitt PLLC07/01/2010 > patent applications in patent subcategories. category listing
20100167423 - Semiconductor package and methods of manufacturing the same: A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from... Agent: Harness, Dickey & Pierce, P.L.C
20100167425 - Method of producing bonded silicon wafer: A bonded silicon wafer is produced by a method comprising a step of implanting oxygen ions from one surface of a silicon wafer for active layer to form an oxygen ion implanted layer, a step of bonding the one surface of the silicon wafer for active layer to one surface... Agent: Christensen, O'connor, Johnson, Kindness, PLLC
20100167426 - Plasma etching apparatus and plasma etching method: The invention provides a method for overcoming the drawbacks of deteriorated throughput, deteriorated reproducibility and plasma discharge instability when continuous discharge is performed during multiple steps of plasma etching. The present invention provides a gas switching method for switching from gas supply source 101 to gas supply source 111, wherein... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100167424 - Variable thickness single mask etch process: The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semiconductor body (e.g., wafer). An etch mask... Agent: Texas Instruments Incorporated
20100167427 - Passive device trimming: The present invention relates to a method for trimming passive devices during fabrication to account for process variations. More particularly, the present invention relates to a method by which an adjustable device layer comprised within a passive device (e.g., resistor body, capacitor electrodes) can be measured and subsequently trimmed (e.g.,... Agent: Texas Instruments Incorporated
20100167428 - Method and system for determining semiconductor characteristics: Method and system for determining semiconductor characteristics. In a specific embodiment, the present invention provides a method for determining one or more characteristics of a partially processed integrated circuit. The method includes a step for providing a substrate material. The method further includes a step for forming at least one... Agent: Townsend And Townsend And Crew, LLP
20100167429 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device estimates the level of erosion generated in CMP of a plug by using a monitoring pattern that defines uniformly a hole array size (split a) and the length (split b) of the space between arrays.... Agent: Sherr & Vaughn, PLLC
20100167430 - Apparatus and method for testing a transducer and/or electronic circuitry associated with a transducer: A method and apparatus for applying a test signal to a node of a signal path of an integrated circuit using a parasitic capacitance of the integrated circuit associated with the node. For example, a parasitic capacitance associated with a bond pad may be used to apply a test signal... Agent: Dickstein Shapiro LLP
20100167431 - Laser processing apparatus: A laser processing apparatus which achieves both shorter TAT and reduction in processing defects. In the apparatus, a laser radiation section, an undulation measurement section for measuring undulation of a substrate or a film thickness measuring section for measuring the thickness of a thin film formed on the substrate, and... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100167432 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes: forming a first pad and a second pad over a substrate; forming a first insulating film over the second pad without forming the first insulating film over the first pad; forming a metal film over the first pad and the second pad;... Agent: Mcginn Intellectual Property Law Group, PLLC
20100167433 - Piezoelectric inkjet printhead and method of manufacturing the same: A piezoelectric inkjet printhead including an upper substrate formed of a single crystal silicon substrate or an SOI substrate and having an ink inlet therethrough, and a lower substrate formed of an SOI substrate having a sequentially stacked structure with a first silicon layer, an intervening oxide layer, and a... Agent: Stanzione & Kim, LLP
20100167434 - Method for fabricating light emitting diode chip: A method for fabricating a light emitting diode chip is provided. Firstly, a semiconductor device layer is formed on a substrate. Afterwards, a current spreading layer is formed on a portion of the semiconductor device layer. Then, a current blocking layer and a passivation layer are formed on a portion... Agent: Jianq Chyun Intellectual Property Office
20100167435 - Organic electro luminescence device and fabrication method thereof: Provided is a method of fabricating an organic electro luminescence device, the method comprising: forming a thin film transistor on a substrate; forming a passivation layer and a first electrode on the substrate including the thin film transistor; forming a contact hole exposing an upper surface of a drain electrode... Agent: Mckenna Long & Aldridge LLP
20100167436 - Method of making a semiconductor chip assembly with a post/base heat spreader and a signal post: A method of making a semiconductor chip assembly includes providing a thermal post, a signal post and a base, mounting an adhesive on the base including inserting the thermal post into a first opening in the adhesive and the signal post into a second opening in the adhesive, mounting a... Agent: David M. Sigmond
20100167438 - Method of making a semiconductor chip assembly with an aluminum post/base heat spreader and a silver/copper conductive trace: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a copper layer on the adhesive including aligning the post with an aperture in the copper layer, then... Agent: David M. Sigmond
20100167437 - Peeling method and method for manufacturing display device using the peeling method: The present invention provides a simplifying method for a peeling process as well as peeling and transcribing to a large-size substrate uniformly. A feature of the present invention is to peel a first adhesive and to cure a second adhesive at the same time in a peeling process, thereby to... Agent: Eric Robinson
20100167440 - Light emissive device: e
20100167439 - Method of manufacturing printing plate and method of manufacturing liquid crystal display device using the same: A method of manufacturing a precise printing plate, and a method of manufacturing an LCD device using the same are disclosed, the method of manufacturing the precise printing plate comprising forming a mask layer of a predetermined pattern on a substrate; etching the substrate with an etchant including an anionic... Agent: Brinks Hofer Gilson & Lione
20100167441 - Method of manufacturing a light emitting, photovoltaic or other electronic apparatus and system: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality... Agent: Gamburd Law Group LLC
20100167442 - Array substrate for display device and method of manufacturing the same: An array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line,... Agent: Innovation Counsel LLP
20100167443 - Active matrix substrate, method of making the substrate, and display device: An active matrix substrate includes base substrate, gate lines, data lines, thin-film transistors and pixel electrodes. The gate lines are formed on the base substrate. The data lines are formed over the gate lines. Each of the data lines crosses all of the gate lines with an insulating film interposed... Agent: Edwards Angell Palmer & Dodge LLP
20100167444 - Fabrication method for thermoelectric device: A method for fabricating thermoelectric device is provided. The method comprises placing a first electrode in a die, forming a first interlayer on an upper surface of the first electrode; positioning a separating plate on an upper surface of the first interlayer to divide an inner space of the die... Agent: Corning Incorporated
20100167446 - Method for manufacturing a junction: The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP
20100167445 - Method for manufacturing back side illumination image sensor: Disclosed is a method for manufacturing a back side illumination image sensor. The method includes defining a pixel area by forming a first isolation area in a first substrate; forming a photo detecting unit buried in the pixel area; forming an ion implantation layer on the photo detecting unit; growing... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20100167447 - Method for manufacturing back side illuminaton image sensor: A method of manufacturing a back side illumination image sensor according to an embodiment includes: forming an ion implantation layer by implanting ions throughout the front side of a first substrate; defining a pixel region by forming a device isolation region on the front side of the first substrate; forming... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20100167448 - Solid-state imaging device and manufacturing method thereof: A solid-state imaging device includes a photoelectric conversion unit, a transistor, and an element separation region separating the photoelectric conversion unit and the transistor. The photoelectric conversion unit and the transistor constitute a pixel. The element separation region is formed of a semiconductor region of a conductivity type opposite to... Agent: Rader Fishman & Grauer PLLC
20100167449 - Solid-state imaging device and method of manufacturing the same: A solid-state imaging device with a semiconductor substrate; a pixel formation region in the substrate and including a pixel made of a photoelectric conversion element; and an element isolation portion in the substrate and including an element isolation insulating layer and an impurity element isolation region. The element isolation insulating... Agent: Sonnenschein Nath & Rosenthal LLP
20100167450 - Solid-state imaging element and method for producing the same: There is provided a solid-state imaging element having a light receiving part generating charges by light irradiation, and a source/drain region of a transistor, both formed in a semiconductor layer. The solid-state imaging element includes a non-silicided region including the light receiving part, in which surfaces of the source/drain region... Agent: Rader Fishman & Grauer PLLC
20100167451 - Methods of manufacturing imaging device packages: Methods of manufacturing an imaging device package are provided. In accordance with an embodiment a sensor die may be coupled to bond pads on a transparent substrate. Electrically conductive paths comprising bond wires are formed through the bond pads from the sensor die to an outer surface of the imaging... Agent: Fletcher Yoder (micron Technology, Inc.)
20100167452 - Method for manufacturing back side illumination image sensor: A method of manufacturing a back side illumination image sensor is provided. The method can include forming an ion implantation layer in a front side of a first substrate, forming a photodetector and a readout circuit on the first substrate, forming an interlayer dielectric layer and a metal line on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20100167453 - Methods of forming an image sensor: Provided is a method of forming an image sensor. The method may include providing a single crystalline semiconductor layer including at least one photodiode onto a support substrate; forming a material layer including dopants on the single crystalline semiconductor layer; and forming a dopant diffusion layer in the single crystalline... Agent: Harness, Dickey & Pierce, P.L.C
20100167454 - Double-sided donor for preparing a pair of thin laminae: A method for forming a photovoltaic cell is disclosed which comprises the steps of providing a semiconductor donor body having a first surface and a second surface opposite the first surface, cleaving a first portion from the first surface of the semiconductor donor body to form a first lamina of... Agent: The Mueller Law Office, P.C.
20100167455 - Method for fabrication of cmos image sensor: Disclosed is a method for fabrication of a CMOS image sensor capable of improving adhesion between an interlayer insulating film and photoresist. According to embodiments in this disclosure, the CMOS image sensor fabrication method may include: forming a plurality of photodiodes over a semiconductor substrate at regular intervals; forming an... Agent: Sherr & Vaughn, PLLC
20100167456 - Image sensor and method of fabricating the same: An image sensor and a method of fabricating the same are provided. A pad region is disposed on a substrate. The pad region has a higher concentration of impurity ions than the substrate. The pad region is selectively removed using the substrate as an etch mask, thereby forming a hole.... Agent: F. Chau & Associates, LLC
20100167457 - Laser firing apparatus for high efficiency solar cell and fabrication method thereof: Disclosed are a laser firing apparatus for a high efficiency solar cell including laser generating unit and a fabrication method thereof. The laser firing apparatus for a high efficiency solar cell includes at least one laser generating unit that irradiates a laser irradiation on to an electrode region formed on... Agent: Birch Stewart Kolasch & Birch
20100167459 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor which reduces occurrence of a dark current. The method includes forming a photodiode in a semiconductor substrate, forming an insulating film over and contacting the semiconductor substrate and the photodiode, respectively, forming a hard mask film over and contacting the insulating film,... Agent: Sherr & Vaughn, PLLC
20100167458 - Thin film type solar cell and method for manufacturing the same: A thin film type solar cell and a method for manufacturing the same is disclosed, which is capable of providing a wide light-transmission area without lowering cell efficiency and increasing processing time, so that the solar cell can be used as a substitute for a glass window in a building.... Agent: Royal W. Craig Ober, Kaler, Grimes & Shriver
20100167460 - Zinc oxide film forming method and apparatus: In the zinc oxide film forming apparatus (1), the deposit containing zinc oxide is formed on the conductive layer of the resin substrate (9) by electrodeposition in the deposition part (2), and the resin substrate (9) is carried to the applying part (4). Subsequently, the film forming material which is... Agent: Ostrolenk Faber Gerb & Soffen
20100167461 - Dry cleaning of silicon surface for solar cell applications: A method and apparatus for cleaning layers of solar cell substrates is disclosed. The substrate is exposed to a reactive gas that may comprise neutral radicals comprising nitrogen and fluorine, or that may comprise anhydrous HF and water, alcohol, or a mixture of water and alcohol. The reactive gas may... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100167463 - Method for fabricating resistive memory device: A method for fabricating a resistive memory device includes forming a lower electrode including a metal nitride layer over a substrate, forming a metal oxide layer used as a variable resistance material by oxidizing a part of the metal nitride layer, and forming an upper electrode on the metal oxide... Agent: Ip & T Law Firm PLC
20100167462 - Method for manufacturing resistance ram device: Manufacturing a resistance RAM device includes the steps of forming an insulation layer on a semiconductor substrate having a bottom electrode contact; etching the insulation layer to define a hole exposing the bottom electrode contact; depositing sequentially a bottom electrode material layer and a TMO material layer selectively within the... Agent: Ladas & Parry LLP
20100167464 - Semiconductor device and manufacturing method thereof: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at... Agent: Eric Robinson
20100167465 - Multiphase synchronous buck converter: Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dies and at least nine parallel leads. The dies are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding.... Agent: Hiscock & Barclay, LLP
20100167466 - Semiconductor package substrate with metal bumps: An apparatus and method of making a package substrate with metal bumps is presented. The package substrate comprises a substrate base and a plurality of metal bumps which are formed on the substrate base. A microelectronic die may thereafter be attached to the package substrate. Also presented is a method... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP
20100167467 - Method for fabricating semiconductor device: At least three or more plurality of chips are stacked to form a three-dimensional integrated circuit. When the plurality of chips are stacked, at least two or more of three stacking methods are used which are a wafer-to-wafer stacking method that bonds together the mutually corresponding chips each on a... Agent: Mcdermott Will & Emery LLP
20100167468 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes a bonding step of bonding a chip on a wiring board by means of a bonding layer, and a wire bonding step of bonding a wire to a pad on the chip while applying ultrasonic vibration after the bonding step. A material... Agent: Mcdermott Will & Emery LLP
20100167470 - Power module for low thermal resistance and method of fabricating the same: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a... Agent: Hiscock & Barclay, LLP
20100167469 - Resin sealing method of semiconductor device: A resin sealing method of a semiconductor device, is provided with: providing a semiconductor device on which a dummy dump is formed; providing a support body including an adhesive layer provided on a surface of the support body; forming a recess in the adhesive layer; inserting the dummy bump of... Agent: Rankin, Hill & Clark LLP
20100167471 - Reducing warpage for fan-out wafer level packaging: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially... Agent: Stmicroelectronics, Inc.
20100167472 - Implantation shadowing effect reduction using thermal bake process: A method of forming a resist feature includes forming a resist layer over a semiconductor body, and selectively exposing the resist layer. The method further includes performing a first bake of the selectively exposed resist layer, and developing the selectively exposed resist layer to form a resist feature having a... Agent: Texas Instruments Incorporated
20100167473 - Semiconductor device and fabrication method for the semiconductor device: A semiconductor device and a fabrication method for the semiconductor device which can remove the sacrifice layer deposited on the semiconductor device surface in a short time and whose manufacturing yield can be improved are provided. The semiconductor device and the fabrication method for the semiconductor device includes a field... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100167474 - Methods of forming semiconductor-on-insulating (soi) field effect transistors with body contacts: Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also... Agent: Myers Bigel Sibley & Sajovec
20100167475 - Semiconductor device and producing method thereof: A semiconductor device manufacturing method includes forming a fin region over a substrate, forming a dummy gate electrode over the fin region, forming a first insulating film over the dummy gate electrode and the fin region, polishing the first insulating film until the dummy gate electrode is exposed, removing part... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100167477 - Localized temperature control during rapid thermal anneal: Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20100167478 - Field effect transistor having reduced cotnact resistance and method for fabricating the same: A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of InxAlyGa1-yN (wherein 0<x≦1, 0—y<1 and 0<x+y≦1). A non-alloy source electrode and a non-alloy drain electrode are formed on the... Agent: Mcdermott Will & Emery LLP
20100167479 - Embedded trap direct tunnel non-volatile memory: The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the... Agent: Leffert Jay & Polglaze, P.A.
20100167480 - Method for manufacturing flash memory device: The present invention relates to a method for fabricating a flash memory device capable of reducing charge loss. The method includes forming a gate pattern on a semiconductor substrate, forming a sidewall spacer layer on the gate pattern using SiO2, introducing nitrogen into the sidewall spacer layer to form a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20100167481 - Manufacturing process of a vertical-conduction misfet device with gate dielectric structure having differentiated thickness and vertical-conduction misfet device thus manufacture: According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to... Agent: Graybeal Jackson LLP
20100167482 - Semiconductor device manufacturing method: The method forms two types of field-effect transistors including gate insulating films having different film thickness in a first region and a second region on a silicon substrate, respectively, and includes forming a silicon-germanium film (Si1-xGex, 0<x<1) in each of the first and second regions, forming a first gate insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100167483 - Method for fabricating pmos transistor: A method for fabricating a PMOS transistor is disclosed herein. In one embodiment, the method can include forming a gate insulation layer and a polysilicon layer over a semiconductor substrate; asymmetrically etching the polysilicon layer; doping the asymmetrically etched polysilicon layer with a P-type dopant; diffusing the dopant in the... Agent: Marshall, Gerstein & Borun LLP
20100167484 - Gate line edge roughness reduction by using 2p/2e process together with high temperature bake: A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a... Agent: Texas Instruments Incorporated
20100167485 - Contact barrier structure and manufacturing methods: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric... Agent: Slater & Matsil, L.L.P.
20100167486 - Method of fabricating transistor for semiconductor device: A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in... Agent: Ip & T Law Firm PLC
20100167487 - Mask rom devices and methods for forming the same: A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including... Agent: F. Chau & Associates, LLC
20100167488 - Integrated circuit comprising a gradually doped bipolar transistor and corresponding fabrication process: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20100167489 - Mim capacitor and method of fabricating the same: A method of fabricating an MIM capacitor may include a first electrode formed on and/or over a semiconductor substrate, a dielectric layer composed of an oxygen material formed on and/or over the first electrode under an oxygen atmosphere. A second electrode is formed on and/or over the dielectric layer. Because... Agent: Sherr & Vaughn, PLLC
20100167491 - Method for fabricating flash memory device: A method for fabricating a flash memory device includes forming device isolation films in a semiconductor substrate, defining active regions between the device isolation films, and patterning floating gates on the semiconductor substrate to correspond to the active regions. Portions where the active regions and the floating gates are not... Agent: Sherr & Vaughn, PLLC
20100167490 - Method of fabricating flash memory device: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include... Agent: Myers Bigel Sibley & Sajovec
20100167492 - Semiconductor device and method of manufacturing the same: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100167493 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes a process of forming a STI trench in a substrate, a process of forming a thermal oxide film on a sidewall and a bottom surface of the STI trench, a process of performing a plasma treatment on a surface of the thermal... Agent: Young & Thompson
20100167494 - Selective etching method and method for forming an isolation structure of a memory device: A disclosed selective etching method comprises mixing a polymer with carbon nanotubes, applying the mixture to an etching target layer to form a carbon nanotube-polymer composite layer, forming a hard mask by patterning the carbon nanotube-polymer composite layer, such that a part of the etching target layer is selectively exposed,... Agent: Marshall, Gerstein & Borun LLP
20100167495 - Semiconductor device manufacturing method, semiconductor device and wafer: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer... Agent: Mccormick, Paulding & Huber LLP
20100167496 - Method for forming device isolation layer of semiconductor device and non-volatile memory device: A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a... Agent: Ip & T Law Firm PLC
20100167497 - Use of field oxidation to simplify chamber fabrication in microfluidic devices: A method includes growing a first oxide region concurrently with a second oxide region in a substrate and forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region. The method also includes removing the first oxide region to form... Agent: Stmicroelectronics, Inc.
20100167498 - Substrate level bonding method and substrate level package: Disclosed are a substrate level bonding method and a substrate level package formed thereby. The substrate level package includes a plurality of unit substrate sections, a base substrate, and a plurality of substrate adhesion sections. The unit substrate sections are separated from each other by holes. The base substrate is... Agent: Staas & Halsey LLP
20100167499 - Method for making a stressed structure designed to be dissociated: A method of making a complex microelectronic structure by assembling two substrates through two respective linking surfaces, the structure being designed to be dissociated at a separation zone. Prior to assembly, in producing a state difference in the tangential stresses between the two surfaces to be assembled, the state difference... Agent: Brinks Hofer Gilson & Lione
20100167500 - Method of recycling an epitaxied donor wafer: A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of... Agent: Winston & Strawn LLP Patent Department
20100167501 - Separation of semiconductor devices: A method of fabricating semiconductor devices is disclosed. The method comprises providing a substrate with a plurality of epitaxial layers mounted on the substrate and separating the substrate from the plurality of epitaxial layers while the plurality of epitaxial layers is intact. This preserves the electrical, optical, and mechanical properties... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP
20100167503 - Methods and systems of transferring, docking and processing substrates: In accordance with some embodiments described herein, a method for transferring a substrate to two or more process modules is provided, comprising loading at least one substrate into one or more mobile transverse chambers, the mobile transverse chambers being carried on a rail positioned adjacent to the two or more... Agent: Morgan, Lewis & Bockius, LLP. (pa)
20100167504 - Methods of fabricating nanostructures: A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department
20100167502 - Nanoimprint enhanced resist spacer patterning method: A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20100167505 - Methods for reducing loading effects during film formation: A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the... Agent: HorizonIPPte Ltd
20100167506 - Inductive plasma doping: In some embodiments, a method of doping a semiconductor wafer disposed on a pedestal electrode in an inductive plasma chamber includes generating a plasma having a first voltage with respect to ground in the inductive plasma chamber, and applying a radio frequency (RF) voltage with respect to ground to the... Agent: Duane Morris LLP (tsmc)IPDepartment
20100167508 - Method for introducing impurities and apparatus for introducing impurities: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous... Agent: Mcdermott Will & Emery LLP
20100167509 - Method for producing a buried n-doped semiconductor zone in a semiconductor body and semiconductor component: A method for producing a buried n-doped semiconductor zone in a semiconductor body. In one embodiment, the method includes producing an oxygen concentration at least in the region to be doped in the semiconductor body. The semiconductor body is irradiated via one side with nondoping particles for producing defects in... Agent: Dicke, Billig & Czaja
20100167507 - Plasma doping apparatus and plasma doping method: A plasma doping apparatus implants an impurity element into a surface of a processing target object W by using plasma. The apparatus includes a high frequency power supply 72 configured to supply a high frequency bias power to a mounting table 34 installed within a processing chamber 32; a gas... Agent: Pearne & Gordon LLP
20100167510 - Methods of using a set of silicon nanoparticle fluids to control in situ a set of dopant diffusion profiles: A method of forming a multi-doped junction is disclosed. The method includes providing a first substrate and a second substrate. The method also includes depositing a first ink on a first surface of each of the first substrate and the second substrate, the first ink comprising a first set of... Agent: Foley & Lardner LLP
20100167511 - Methods for simultaneously forming doped regions having different conductivity-determining type element profiles: Method for simultaneously forming doped regions having different conductivity-determining type elements profiles are provided. In one exemplary embodiment, a method comprises the steps of diffusing first conductivity-determining type elements into a first region of a semiconductor material from a first dopant to form a doped first region. Second conductivity-determining type... Agent: Honeywell International Inc. Patent Services
20100167512 - Methods for nanostructure doping: Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature... Agent: Nanosys Inc.
20100167513 - Dual alignment strategy for optimizing contact layer alignment: An improved method for optimizing layer registration during lithography in the fabrication of a semiconductor device is disclosed. In one example, the method comprises optimizing contact layer registration of an SRAM device having a plurality of transistors having active and gate region features extending generally along a channel length (X)... Agent: Texas Instruments Incorporated
20100167515 - Method for fabricating flash memory device: A method of forming a flash memory device includes forming a plurality of memory gates over a semiconductor substrate, forming an oxide film over the uppermost surface and sidewalls of the memory gates and then forming a plurality of selective gates on sidewalls of each of the memory gates.... Agent: Sherr & Vaughn, PLLC
20100167514 - Post metal gate vt adjust etch clean: A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first... Agent: Texas Instruments Incorporated
20100167516 - Semiconductor device and manufacturing method thereof: A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100167517 - Cross-contamination control for processing of circuits comprising mos devices that include metal comprising high-k dielectrics: A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein the bevel semiconductor surface and backside semiconductor surface include silicon or germanium. A metal including high-k gate dielectric layer is... Agent: Texas Instruments Incorporated
20100167518 - Cross-contamination control for semiconductor process flows having metal comprising gate electrodes: A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at... Agent: Texas Instruments Incorporated
20100167519 - Post high-k dielectric/metal gate clean: A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack... Agent: Texas Instruments Incorporated
20100167520 - Resist feature and removable spacer pitch doubling patterning method for pillar structures: A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming sidewall spacers on the at least two features and filling a space between a first sidewall spacer... Agent: Dugan & Dugan, PC
20100167521 - Semiconductor processing methods: Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a... Agent: Wells St. John P.s.
20100167522 - Structures and methods for improving solder bump connections in semiconductor devices: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department
20100167523 - Semiconductor device and method of fabricating the same: A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate; a wiring formed in predetermined pattern above the semiconductor substrate, a first insulating film lying right under the wiring, and a second insulating film lying in a peripheral portion other than a portion right under... Agent: Foley And Lardner LLP Suite 500
20100167524 - Method for fabricating metal interconnection of semiconductor device: In a method for fabricating a metal interconnection of a semiconductor device, a lower interconnection and a lower insulation layer are formed over a semiconductor substrate. An etch stop layer is formed over the lower insulation layer. An upper insulation layer is formed over the etch stop layer. A first... Agent: Sherr & Vaughn, PLLC
20100167525 - Semiconductor device and method of manufacture thereof: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100167526 - Method for improving electromigration lifetime of copper interconnection by extended post anneal: Methods for improving electromigration of copper interconnection structures are provided. In one embodiment, a method of annealing a microelectronic device includings forming microelectronic features on a substrate, forming a contact structure over the microelectronic features, and forming a copper interconnection structure over the contact structure. A passivation layer is deposited... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100167527 - Method of depositing tungsten film with reduced resistivity and improved surface morphology: A method of controlling the resistivity and morphology of a tungsten film is provided, comprising depositing a first film of a bulk tungsten layer on a substrate during a first deposition stage by (i) introducing a continuous flow of a reducing gas and a pulsed flow of a tungsten-containing compound... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100167528 - Low resistance metal silicide local interconnects and a method of making: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with... Agent: Dinsmore & Shohl LLP
20100167529 - Method for manufacturing semiconductor device: An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100167530 - Method for forming metal line of semiconductor device: Disclosed is a method for forming a metal line of a semiconductor device. The method includes forming a first photoresist pattern on at least one interlayer dielectric provided on a semiconductor substrate, etching the interlayer dielectric using the first photoresist pattern to form a trench, removing the first photoresist pattern... Agent: Sherr & Vaughn, PLLC
20100167531 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for manufacturing the same includes sequentially laminating a first dielectric film, an etch-blocking film and a second dielectric film on and/or over a semiconductor substrate, forming a photosensitive film mask to open a trench region in the second dielectric film, etching the second dielectric... Agent: Sherr & Vaughn, PLLC
20100167533 - Method of fabricating semiconductor integrated circuit device: A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress... Agent: Myers Bigel Sibley & Sajovec
20100167532 - Method of high aspect ratio plug fill: A method of plug fill for high aspect ratio plugs wherein a nucleation layer is formed at a bottom of a via and not on the sidewalls. The plug fill is in the direction from bottom to top of the via and not inwards from the sidewalls. The resulting plug... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP
20100167534 - Method for fabricating a semiconductor chip device having through-silicon-via (tsv): A semiconductor device with TSV and its fabrication method are revealed. The semiconductor device primarily comprises a chip and a flexible metal wire inside. A redistributed trace layer and a passivation layer are formed on the active surface of the chip. A through hole penetrates the chip from the active... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100167535 - Cleaning agent for semiconductor device and method for producing semiconductor device using the cleaning agent: A cleaning agent used after chemical mechanical polishing of a semiconductor device, the cleaning agent including a polycarboxylic acid and diethylenetriamine pentaacetic acid, the semiconductor device including a copper diffusion barrier film and copper wiring on an interlayer dielectric film, and the dielectric film containing SiOC and having a dielectric... Agent: Solaris Intellectual Property Group, PLLC
20100167536 - Method for removing hardened polymer residue: A method for efficiently removing hardened polymer residues generated in the process of forming metal lines. The method includes forming a metal layer over a lower film, forming a sacrificial protective film over the metal layer, forming a photosensitive pattern over the sacrificial protective film, forming a metal line by... Agent: Sherr & Vaughn, PLLC
20100167537 - Partitioning features of a single ic layer onto multiple photolithographic masks: One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from the IC layer, where the first... Agent: Texas Instruments Incorporated
20100167539 - Method for insulating wires of semiconductor device: Disclosed herein is a method for insulating wires of a semiconductor device. One embodiment of the method includes forming first bit line stacks over a cell region of a semiconductor substrate and second bit line stacks over a peripheral region of the semiconductor substrate, and forming a Spin On Dielectric... Agent: Marshall, Gerstein & Borun LLP
20100167538 - Method for removing native oxide remaining on a surface of a semiconductor device during manufacturing: A method for removing native oxide that remains on a surface of a semiconductor device is presented. The manufacturing method includes the steps of placing, supplying, moving, and annealing. The placing step includes placing a semiconductor substrate into a first process chamber. The supplying step includes supplying an etchant gas... Agent: Ladas & Parry LLP
20100167540 - Film forming method, plasma film forming apparatus and storage medium: Disclosed is a technique for embedding metal in a recess provided in the surface of a process object, such as a semiconductor wafer W, only by plasma sputtering. The metal is copper as a typical example. The recess has a microscopic hole or trench having a diameter or width of... Agent: Smith, Gambrell & Russell
20100167541 - Method of manufacturing semiconductor device, cleaning method and cleaning control apparatus: Efficient cleaning is possible although the film qualities and thicknesses of a reaction tube and a gas supply nozzle are different. There is provided a method of manufacturing a semiconductor device. The method includes forming a film on a substrate, performing a first cleaning process to remove a first deposition... Agent: Brundidge & Stanger, P.C.
20100167542 - Methods of titanium deposition: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer... Agent: Wells St. John P.s.
20100167543 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor power device may includes: performing a grinding process on a back side of a wafer, performing a first plasma process and a rapid thermal process sequentially after performing the grinding process, performing a second plasma process after performing the rapid thermal process, and performing... Agent: Sherr & Vaughn, PLLC
20100167544 - Door assembly for substrate processing chamber: A substrate processing apparatus includes an enclosure defining a reaction chamber, a substrate holder in the reaction chamber, and a door assembly. The door assembly has a substrate entrance with a tunnel extending to the reaction chamber, a door movable with respect to the substrate entrance, and a pattern of... Agent: Stmicroelectronics, Inc.
20100167545 - Method and composition for chemical mechanical planarization of a metal: A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low within a wafer non-uniformity values and low residue levels remaining after polishing.... Agent: Air Products And Chemicals, Inc. Patent Department
20100167546 - Method and composition for chemical mechanical planarization of a metal or a metal alloy: A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low dishing and erosion levels during CMP processing.... Agent: Air Products And Chemicals, Inc. Patent Department
20100167547 - Polishing liquid: A polishing liquid for a chemical mechanical polishing of a semiconductor device includes (a) a carboxylic acid compound having one or more carboxy groups, (b) colloidal silica particles having a ζ potential of −10 mV to −35 mV when used in the polishing liquid, (c) a benzotriazole derivative, (d) an... Agent: Solaris Intellectual Property Group, PLLC
20100167548 - Method for forming fine pattern using quadruple patterning in semiconductor device: A method for forming a fine pattern in a semiconductor device using a quadruple patterning includes forming a first partition layer over a first material layer which is formed over a substrate, performing a photo etch process on the first partition layer to form a first partition pattern, performing an... Agent: Ip & T Law Firm PLC
20100167549 - Substrate processing method: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100167550 - Method for manufacturing semiconductor: A method for manufacturing a semiconductor includes forming an active region for an ESD device, an active region for a first polygate and the semiconductor, and a second polygate having a form of a blanket trench on a substrate, forming an interlayer dielectric layer including first and second insulating on... Agent: Sherr & Vaughn, PLLC
20100167551 - Dual path gas distribution device: An apparatus for deploying two fluids separately into a reaction chamber is provided. The apparatus includes a first distribution network that is formed on a plate having a distribution face and a dispensing face. The first distribution network is defined by a plurality of recessed channels on the distribution face.... Agent: Martine Penilla Gencarella, LLP
20100167552 - Methods for particle removal during integrated circuit device fabrication: A method of manufacturing an IC device includes providing a workpiece having least one dielectric layer disposed on a surface of the workpiece. The method also includes processing the dielectric layer to form a plurality of apertures in the dielectric layer, where the processing includes at least one micromask-prone process.... Agent: Texas Instruments Incorporated
20100167555 - Method in depositing metal oxide materials: The present invention relates to a method for enhancing uniformity of metal oxide coatings formed by Atomic Layer Deposition (ALD) or ALD-type processes. Layers are formed using alternating pulses of metal halide and oxygen-containing precursors, preferably water, and purging when necessary. An introduction of modificator pulses following the pulses of... Agent: Oliff & Berridge, PLC
20100167554 - Methods forming high dielectric target layer: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second... Agent: Volentine & Whitt PLLC
20100167556 - Three degree of movement mover and method for controlling a three degree of movement mover: A mover (344) moving a stage (238) along a first axis and about a second axis includes a magnetic component (454), and a conductor component (456). The magnetic component (454) includes one or more magnets (454D) that are surrounded by a magnetic field. The conductor component (456) is positioned near... Agent: Roeder & Broder LLPPrevious industry: Chemistry: analytical and immunological testing
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