|Semiconductor device manufacturing: process patents - Monitor Patents|
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Semiconductor device manufacturing: process January recently filed with US Patent Office 01/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/28/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100022030 - Dry etch stop process for eliminating electrical shorting in mram device structures: The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.... Agent: Fliesler Meyer LLP
20100022032 - Method of forming organic ferroelectric film, method of manufacturing memory element, memory device, and electronic apparatus: A method of forming an organic ferroelectric film configured to include an organic ferroelectric material with a crystalline property as a principal material includes (a) forming a low crystallinity film having a crystallinity lower than a crystallinity of the organic ferroelectric film on one surface of a substrate, and (b)... Agent: Oliff & Berridge, PLC
20100022031 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100022033 - Process for wafer temperature verification in etch tools: A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness... Agent: Beyer Law Group LLP
20100022035 - Electronic apparatus and manufacturing method thereof: There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the... Agent: Drinker Biddle & Reath (dc)
20100022034 - Manufacture of devices including solder bumps: Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion... Agent: Mendelsohn, Drucker, & Associates, P.C.
20100022037 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor includes developing a semiconductor substrate provided with metal pads with tetramethylammonium hydroxide (TMAH), to etch the metal pads. In accordance with the method, it is possible to realize normal output of materials, which were previously scrapped due to problems including pad corrosion,... Agent: Sherr & Vaughn, PLLC
20100022036 - Method for forming pattern, and template: According to an aspect of the present invention, there is provided a template including: a template substrate; patterns for forming device patterns on a wafer substrate; and a charging monitoring pattern, a size of the charging monitoring pattern being equal to a largest pattern in the patterns for forming the... Agent: Finnegan, Henderson, Farabow, Garret & Dunner L.L.P.
20100022038 - Method for evaluating semiconductor wafer: The present invention provides a method for evaluating a semiconductor wafer, including at least: forming an oxide film on a front surface of a semiconductor wafer; partially removing the oxide film to form windows at two positions; diffusing a dopant having a conductivity type different from a conductivity type of... Agent: Oliff & Berridge, PLC
20100022039 - Method of making light emitting diodes: A method of making LEDs simultaneously includes steps of : a) providing a wafer having LED dies on a substrate; b) forming a passivation layer on the LED dies; c) forming an electrode layer on the passivation layer and the LED dies; d) assembling a conducting board on the electrode... Agent: PCe Industry, Inc. Att. Steven Reiss
20100022040 - Method for producing light-emitting device: [Means to achieve the object] A method for producing a light-emitting device includes the steps of: (a) die-bonding a chip onto a substrate so as to prepare a die-bonded substrate; (b) preparing a mold having a cavity; (c) setting the die-bonded substrate such that the chip is placed in the... Agent: Nixon & Vanderhye, PC
20100022041 - Thin film transistor array panel including layered line structure and method for manufacturing the same: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain... Agent: Innovation Counsel LLP
20100022042 - Method for fabricating an in-plane switching mode liquid crystal display device: An in-plane switching mode liquid crystal display (LCD) device, which reduces loss in transmittance and improves reflectance, and a method for fabricating the same are disclosed. The in-plane switching mode LCD device includes gate and data lines orthogonally crossing each other on a first substrate to define pixel regions having... Agent: Mckenna Long & Aldridge LLP
20100022044 - Laser device, laser module, semiconductor laser and fabrication method of semiconductor laser: A semiconductor laser has first and second diffractive grating regions. The first diffractive grating region has segments, has a gain, and has first discrete peaks of a reflection spectrum. The second diffractive grating region has segments combined to each other, and has second discrete peaks of a reflection spectrum. Each... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100022043 - Semiconductor laser device and method of manufacturing the same: A method of manufacturing semiconductor laser device capable of reducing κL, with manufacturing restrictions satisfied, is provided. In a distributed-feedback or distributed-reflective semiconductor laser device, immediately before burying regrowth of a diffraction grating, halogen-based gas is introduced to a reactor, and etching is performed on the diffraction grating so that... Agent: Mcdermott Will & Emery LLP
20100022045 - Sensor platform using a non-horizontally oriented nanotube element: Sensor platforms and methods of making them are described. A platform having a non-horizontally oriented sensor element comprising one or more nanostructures such as nanotubes is described. Under certain embodiments, a sensor element has or is made to have an affinity for an analyte. Under certain embodiments, such a sensor... Agent: Wilmerhale/boston
20100022046 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on... Agent: Mcdermott Will & Emery LLP
20100022047 - Method of manufacturing solar cell module and method of manufacturing solar cell: A method of manufacturing the solar cell module 100 according to the embodiment of the present invention includes: a step of forming the plurality of thin line-shaped electrodes and the connecting electrode connected to one end portion of each of the plurality of thin line-shaped electrodes; a step of disposing... Agent: Mots Law, PLLC
20100022048 - Semiconductor device and manufacturing method therefor: The present invention relates to a manufacturing method for a semiconductor device, the method includes a process for forming an interlayer film on a substrate, a process for forming an opening in the interlayer, a process for forming a conductive layer which fills the opening, and a process for forming... Agent: Masuvalley & Partners
20100022049 - Mid-ir microchip laser: zns:cr2+ laser with saturable absorber material: A method of fabrication of laser gain material and utilization of such media includes the steps of introducing a transitional metal, preferably Cr2+ thin film of controllable thickness on the ZnS crystal facets after crystal growth by means of pulse laser deposition or plasma sputtering, thermal annealing of the crystals... Agent: Fish & Richardson, PC
20100022050 - Standoff height improvement for bumping technology using solder resist: A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second... Agent: Robert D. Atkins
20100022052 - Method for manufacturing package on package with cavity: A manufacturing method of a package on package with a cavity. The method can include forming a first upper substrate cavity in one side of an upper substrate; mounting an upper semiconductor chip on the other side of the upper substrate; forming a lower substrate cavity in one side of... Agent: Staas & Halsey LLP
20100022051 - Method of fabricating electronic device having stacked chips: A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer... Agent: Harness, Dickey & Pierce, P.L.C
20100022053 - Method for packaging components: The invention relates to a method for the manufacture of packaged components. The invention is based here on the problem of facilitating the application of covers with lateral dimensions that are smaller than the lateral dimensions of the functional substrate. For this purpose, a plate-like cover substrate is mounted on... Agent: Demont & Breyer, LLC
20100022054 - Semiconductor package and method for manufacturing the same: A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin... Agent: Drinker Biddle & Reath (dc)
20100022055 - Thin film transistor, thin film transistor substrate including the same and method of manufacturing the same: A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a... Agent: Frank Chau, Esq. F. Chau & Associates, LLC
20100022056 - Method of manufacturing a bipolar transistor: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100022057 - Method for forming a semiconductor device having a fin channel transistor: The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof. The semiconductor device additionally has a fin channel region protruded over the device isolation structure in a longitudinal direction of a... Agent: Townsend And Townsend And Crew, LLP
20100022058 - Method for preparing multi-level flash memory: A method for preparing a multi-level flash memory comprising the steps of forming a recess in a semiconductor substrate, forming a plurality of storage structures at the sides of the recess, and forming a gate structure having a lower block in the recess and an upper block on the lower... Agent: Wpat, PC Intellectual Property Attorneys
20100022059 - Method of fabricating high voltage semiconductor devices with jfet regions containing dielectrically isolated junctions: A high-voltage field-effect device contains an extended drain or “drift” region having a plurality of JFET regions separated by portions of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and at least two sides of... Agent: Patentability Associates
20100022060 - Bi-axial texturing of high-k dielectric films to reduce leakage currents: The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation... Agent: Lsi Corporation
20100022061 - Spacer shape engineering for void-free gap-filling process: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after... Agent: Slater & Matsil, L.L.P.
20100022062 - Transitor having a germanium implant region located therein and a method of manufacture therefor: The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of... Agent: Texas Instruments Incorporated
20100022063 - Method of forming on-chip passive element: Various methods of forming a passive element such as an inductor raised off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned... Agent: Hoffman Warnick LLC
20100022064 - High voltage sensor device and method therefor: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700
20100022065 - Deep trench device with single sided connecting structure and fabrication method thereof: A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting... Agent: Quintero Law Office, PC
20100022066 - Method for producing high-resistance simox wafer: A method for producing a high-resistance SIMOX wafer wherein oxygen diffused inside of a wafer by the heat treatment at a high temperature in an oxidizing atmosphere can be reduced to suppress the occurrence of thermal donor. In one embodiment, a heating-rapid cooling treatment is conducted after the heat treatment... Agent: Christensen, O'connor, Johnson, Kindness, PLLC
20100022067 - Deposition methods for releasing stress buildup: A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material is provided. The feature includes lines separated by a gap. The method includes forming a liner layer over the feature on the semiconductor substrate in a chamber. A stress of the liner... Agent: Townsend And Townsend And Crew LLP
20100022069 - Method for manufacturing semiconductor device: An oxide film and a liner film are formed on an inner wall of a trench in a semiconductor substrate. After filling an SOD film in the trench, a heat treatment is carried out. Part of the liner film in contact with the SOD film is removed to expose part... Agent: Morrison & Foerster LLP
20100022068 - Sti film property using sod post-treatment: A method of forming a shallow trench isolation region includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; filling a precursor into the opening using spin-on; performing a steam cure to the precursor to generate a dielectric material;... Agent: Slater & Matsil, L.L.P.
20100022070 - Method for manufacturing soi substrate: It is an object to provide a method for, after a semiconductor film is separated, reprocessing a separated bond substrate into a reprocessed bond substrate which can be used for manufacturing an SOI substrate. The method for, after a semiconductor film is separated, reprocessing a separated bond substrate into a... Agent: Eric Robinson
20100022071 - Method of manufacturing semiconductor chip: In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, laser light 5a is irradiated from the... Agent: Pearne & Gordon LLP
20100022072 - Semiconductor fabrication: This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate... Agent: Fish & Richardson P.C.
20100022073 - Method of fabricating cmos inverter and integrated circuits utilizing strained silicon surface channel mosfets: A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to... Agent: Goodwin Procter LLP Patent Administrator
20100022074 - Substrate release methods and apparatuses: The present disclosure relates to methods and apparatuses for fracturing or breaking a buried porous semiconductor layer to separate a 3-D thin-film semiconductor semiconductor (TFSS) substrate from a 3-D crystalline semiconductor template. The method involves forming a sacrificial porous semiconductor layer on the 3-D features of the template. A variety... Agent: HulseyIPIntellectual Property Lawyers, P.C.
20100022075 - Semiconductor device and method of manufacturing the semiconductor device: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to... Agent: Rossi, Kimms & Mcdowell LLP.
20100022076 - Ion implantation with heavy halogenide compounds: A method of plasma doping includes providing a dopant gas comprising a dopant heavy halogenide compound gas to a plasma chamber. A plasma is formed in the plasma chamber with the dopant heavy halogenide compound gas and generates desired dopant ions and heavy fragments of precursor dopant molecule. A substrate... Agent: Rauschenbach Patent Law Group, LLC
20100022077 - Semiconductor device and method of fabricating a semiconductor device: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation.... Agent: Katten Muchin Rosenman LLP (c/o Patent Administrator)
20100022078 - Aluminum inks and methods of making the same, methods for depositing aluminum inks, and films formed by printing and/or depositing an aluminum ink: Aluminum metal ink compositions, methods of forming such compositions, and methods of forming aluminum metal layers and/or patterns are disclosed. The ink composition includes an aluminum metal precursor and an organic solvent. Conductive structures may be made using such ink compositions by printing or coating the aluminum precursor ink on... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20100022079 - Systems and methods for reducing contact to gate shorts: A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100022080 - Method of manufacturing semiconductor device: The method of manufacturing the semiconductor device includes nitridizing a silicon substrate with ammonia while heating the silicon substrate, then heating the silicon substrate in an atmosphere containing nitrogen and oxygen to form a gate insulating film including a silicon-based insulating film containing nitrogen and oxygen, then annealing the silicon... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100022081 - Non-volatile sonos-type memory device: A semiconductor memory device with the thickness of both a tunnel film and a top film provided thereon configured to be in the FN tunneling region (4 nm or more). Data retention characteristics can be improved by configuring both a tunnel film and a top film to have a thickness... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20100022083 - Carbon nanotube interconnect structures: A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100022082 - Method for making a nanotube-based electrical connection between two facing surfaces: Facing surfaces made from semiconductor material are formed and then transformed into a porous semiconductor. The porous semiconductor is then transformed into a porous metallic material by silicidation. The porous metallic material then acts as catalyst for growth of the carbon nanotubes which electrically connect the facing surfaces made from... Agent: Oliff & Berridge, PLC
20100022084 - Method for forming interconnect structures: Methods of fabricating interconnect structures in a semiconductor integrated circuit (IC) are presented. A preferred embodiment comprises forming interconnect lines and vias through a dual-damascenes process. It includes forming a via dielectric layer, an etch stop layer directly over the via dielectric layer, and a trench dielectric layer over the... Agent: Slater & Matsil, L.L.P.
20100022085 - Method of forming support structures for semiconductor devices: Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support... Agent: Slater & Matsil LLP
20100022086 - Method of manufacturing a metal wiring structure: In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first... Agent: Volentine & Whitt PLLC
20100022087 - Semiconductor device and method of fabricating the same: A semiconductor device includes an insulating film formed above an upper surface of a semiconductor substrate and including a contact hole, the contact hole including an upper portion and a lower portion located on the upper portion via a boundary as a first lower end of the upper portion and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100022088 - Multiple exposure and single etch integration method: A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features.... Agent: International Business Machines Corporation Dept. 18g
20100022089 - Method for manufacturing semiconductor device using quadruple-layer laminate: There is provided a laminate used as an underlayer layer for a photoresist in a lithography process of a semiconductor device and a method for manufacturing a semiconductor device by using the laminate. The method comprising: laminating each layer of an organic underlayer film (layer A), a silicon-containing hard mask... Agent: Oliff & Berridge, PLC
20100022090 - Resist underlayer film forming composition for lithography, containing aromatic fused ring-containing resin: There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than... Agent: Oliff & Berridge, PLC
20100022091 - Method for plasma etching porous low-k dielectric layers: Described herein are methods and apparatuses for etching low-k dielectric layers to form various interconnect structures. In one embodiment, the method includes forming an opening in a resist layer. The method further includes etching a porous low-k dielectric layer with a process gas mixture that includes a fluorocarbon gas and... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP
20100022092 - Method of producing semiconductor device using resist underlayer film by photo-crosslinking curing: There is provided a resist underlayer film forming composition used in a lithography process for producing semiconductor devices. A method of producing a semiconductor device comprising: forming a coating film by applying a resist underlayer film forming composition containing a polymer, a crosslinker and a photoacid generator on a semiconductor... Agent: Oliff & Berridge, PLC
20100022093 - Vacuum processing apparatus, method of operating same and storage medium: In a vacuum processing apparatus including a processing chamber having a transfer port, and a transfer chamber connected via a gate chamber to the transfer port, diffusion of a gas remaining in the processing chamber into the transfer chamber is suppressed. In order to suppress diffusion of gas from the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100022094 - Elevator and apparatus and method for processing substrate using the same: In an apparatus and a method for processing a substrate, a plurality of chucks are disposed parallel with each other in a process chamber. The chucks fully support back surfaces of substrates and have a plurality of through-holes. Supports are disposed through the through-holes and movable in a vertical direction.... Agent: Daly, Crowley, Mofford & Durkee, LLP
20100022095 - Selective etching and formation of xenon difluoride: This invention relates to a process for selective removal of materials, such as: silicon, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, tantalum, niobium, boron, phosphorus, germanium, arsenic, and mixtures thereof, from silicon dioxide, silicon nitride, nickel, aluminum, TiNi alloy, photoresist, phosphosilicate glass, boron phosphosilicate glass, polyimides, gold, copper, platinum, chromium, aluminum... Agent: Air Products And Chemicals, Inc. Patent Department
20100022096 - Material removal methods employing solutions with reversible etch selectivities: A method for removing (e.g., etching) different dielectric materials from a semiconductor substrate includes exposing the semiconductor substrate to a solution at temperatures below and at or above a set threshold. Below the threshold temperature, the solution removes one dielectric material (e.g., silicon nitride) faster than it removes another, different... Agent: Trask Britt, P.C./ Micron Technology
20100022098 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes: performing modifying a surface of a semiconductor wafer including a silanol group on the surface with an alkylsilyl group; and fluorinating an alkyl group of the alkylsilyl group with which the surface was modified.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100022099 - Method of forming non-conformal layers: In one aspect, non-conformal layers are formed by variations of plasma enhanced atomic layer deposition, where one or more of pulse duration, separation, RF power on-time, reactant concentration, pressure and electrode spacing are varied from true self-saturating reactions to operate in a depletion-effect mode. Deposition thus takes place close to... Agent: Knobbe, Martens, Olson & Bear LLP
20100022097 - Vaporizer, semiconductor production apparatus and process of semiconductor production: A vaporizer, a semiconductor production apparatus and process capable of improving the efficiency in the use of a raw material gas noticeably, enabling uniform deposition according to the raw material gas used, diminishing maintenance frequency to improve productivity. At the time of ALD operation, carrier gas continues to be supplied... Agent: Darby & Darby P.C.
20100022100 - Bi-layer capping of low-k dielectric films: A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100022101 - Method for changing physical vapor deposition film form: A method for changing a physical vapor deposition film form comprises: providing at least one sample with an active area; delivering the sample to a physical vapor deposition machine with one adjustable angle of one collimator; changing the angle of the collimator in the physical vapor deposition machine; performing physical... Agent: Rosenberg, Klein & Lee
20100022102 - Laser annealing method and device: A laser annealing method for executing laser annealing by irradiating a semiconductor film formed on a surface of a substrate with a laser beam, the method including the steps of, generating a linearly polarized rectangular laser beam whose cross section perpendicular to an advancing direction is a rectangle with an... Agent: Fish & Richardson P.C.01/21/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100015730 - Magnetic self-assembly for integrated circuit packages: An integrated circuit package may include a substrate and an integrated circuit. The substrate may include at least one region, and a first magnetic material associated with the at least one region. The integrated circuit may have a second magnetic material associated therewith. The second magnetic material may be attracted... Agent: Tyco International Ltd
20100015729 - Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same: In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic... Agent: Myers Bigel Sibley & Sajovec
20100015731 - Method of low-k dielectric film repair: An apparatus, system and method for repairing a carbon depleted low-k material in a low-k dielectric film layer includes identifying a repair chemistry having a hydrocarbon group, the repair chemistry configured to repair the carbon depleted low-k material and applying the identified repair chemistry meniscus to the low-k dielectric film... Agent: Martine Penilla & Gencarella, LLP
20100015732 - Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip: Base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet, which provides the same functionality as one of the at least one non-functional chiplet is designed to provide, is vertically... Agent: Scully, Scott, Murphy & Presser, P.C.
20100015733 - Method and device for monitoring a heat treatment of a microtechnological substrate: A method of monitoring a heat treatment of a microtechnological substrate includes placement of the substrate to be treated in a heating zone and applying a heat treatment to the substrate, under predetermined temperature conditions, while monitoring the change over the course of time in the vibratory state of the... Agent: Brinks Hofer Gilson & Lione
20100015734 - Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a preexisting semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing... Agent: Fish & Richardson P.C.
20100015736 - Method of fabricating a chip: A method of fabricating a chip may include the step of providing a first electrical part. The method may also include the step of forming a shell with the first electrical part embedded in a first side portion of the shell and a cavity in a second side portion of... Agent: Sawyer Law Group PC
20100015735 - Observation method of wafer ion implantation defect: An analysis method of wafer ion implant is presented, the steps of the method comprises: (a) cleave a wafer for analysis, and (b) from these pieces of wafers determine which ones are wafer with defect and set an insulator on the wafer with defect, (c) finally, use scanning electron microscope... Agent: Rosenberg, Klein & Lee
20100015737 - Semiconductor device, method of manufacturing thereof, and method of manufacturing base material: It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective... Agent: Eric Robinson
20100015738 - Light emitting elements and methods of fabricating the same: Methods of fabricating light emitting elements and light emitting devices, light emitting elements and light emitting devices are provided. In some embodiments, the methods of fabricating a light emitting element includes forming a buffer layer on at least one first substrate, bonding the at least one first substrate on a... Agent: Mills & Onello LLP
20100015739 - Semiconductor light emitting device having improved luminance and manufacturing method thereof: In the semiconductor light emitting device manufacturing method, a surface of a substrate, on which the semiconductor light emitting device is to be manufactured, is etched, thus forming a plurality of deep trenches. Semiconductor films are sequentially grown on the surface of the substrate in which the deep trenches are... Agent: The Nath Law Group
20100015740 - Liquid crystal display device and fabricating method thereof: A liquid crystal display device, including: first and second substrates; a gate line on the first substrate; a data line crossing the gate line having a gate insulating film therebetween to define a pixel area; a pixel electrode formed of a transparent conductive film in a pixel hole passing through... Agent: Mckenna Long & Aldridge LLP
20100015741 - Fabrication process for silicon ridge waveguide ring resonator: An embodiment of a method for manufacturing an optical ring resonator device is disclosed. The method forms a ring resonator waveguide on a semiconductor substrate, forms an unoriented electro-optic polymer cladding over the ring resonator waveguide, and forms electrodes on the semiconductor substrate. The unoriented electro-optic polymer cladding is configured... Agent: Hugh P. Gortler
20100015743 - Etched-facet ridge lasers with etch-stop: A photonic device incorporates an epitaxial structure having an active region, and which includes a wet etch stop layer above, but close to, the active region. An etched-facet ridge laser is fabricated on the epitaxial structure by dry etching followed by wet etching. The dry etch is designed to stop... Agent: Jones, Tullar & Cooper, P.C.
20100015742 - Method for fabricating light emitting diode chip: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention,... Agent: Jianq Chyun Intellectual Property Office
20100015744 - Micro-electromechanical device and method of making the same: A method of manufacturing a cantilever-based micro-electromechanical device comprising the steps of providing a first conductive material layer on a substrate to from a plurality of electrodes. Then, depositing a sacrificial material layer on the electrodes and substrate, thereby defining a non-exposed surface and an exposed surface of the sacrificial... Agent: Patterson & Sheridan, L.L.P.
20100015745 - Method and structure for a cmos image sensor using a triple gate process: A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method form a first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a... Agent: Townsend And Townsend And Crew, LLP
20100015746 - Method of manufacturing image sensor: Provided is a method in which a photodiode layer is formed on a metal interconnection layer, and a hard mask layer is formed on the photodiode layer. Then, a photoresist pattern is formed on the hard mask layer to define a contact hole region, and a first hole is formed... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20100015747 - Methods of fabricating image sensors including impurity layer isolation regions: Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation... Agent: Myers Bigel Sibley & Sajovec
20100015748 - Image sensor and method for manufacturing the same: A method for manufacturing an image sensor includes forming first to third photodiodes and first to third color filters corresponding thereto; forming a photoresist film including photosensitive materials on the upper surfaces of the first to third color filters; forming a first exposed part by exposing the photoresist film with... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20100015751 - Hybrid heterojunction solar cell fabrication using a metal layer mask: Embodiments of the invention contemplate the formation of a high efficiency solar cell using a novel processing sequence to form a solar cell device. In one embodiment, the methods include the use of various etching and patterning processes that are used to define active regions of the device and regions... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100015750 - Process of manufacturing solar cell: A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d)... Agent: Bacon & Thomas, PLLC
20100015749 - Rapid thermal oxide passivated solar cell with improved junction: A method of manufacturing a solar cell is provided. One surface of a semiconductor substrate is doped with a n-type dopant. The substrate is then subjected to a thermal oxidation process to form an oxide layer on one or both surfaces of the substrate. The thermal process also diffuses the... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100015752 - Methods of preparing photovoltaic modules: Methods of preparing photovoltaic modules, as well as related components, systems, and devices, are disclosed.... Agent: Fish & Richardson PC
20100015753 - High power efficiency, large substrate, polycrystalline cdte thin film semiconductor photovoltaic cell structures grown by molecular beam epitaxy at high deposition rate for use in solar electricity generation: Solar cell structures formed using molecular beam epitaxy (MBE) that can achieve improved power efficiencies in relation to prior art thin film solar cell structures are provided. A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device using MBE are described. A... Agent: Wilson, Sonsini, Goodrich & Rosati
20100015754 - Method and apparatus to form thin layers of photovoltaic absorbers: A method and a system are provide for forming planar precursor structures which are subsequently converted into thin film solar cell absorber layers. A precursor structure is first formed on the front surface of the foil substrate and then planarized through application of force or pressure by a smooth surface... Agent: Pillsbury Winthrop Shaw Pittman LLP
20100015755 - Manufacturing method of semiconductor memory device: In a step of forming an InGeSbTe film which contains GeSbTe made of germanium (Ge), antimony (Sb) and tellurium (Te) as its base material and to which indium (In) is added, an InGeSbTe film is formed by sputtering on a semiconductor substrate while keeping a temperature of the semiconductor substrate... Agent: Miles & Stockbridge PC
20100015756 - Hybrid heterojunction solar cell fabrication using a doping layer mask: Embodiments of the invention contemplate the formation of a high efficiency solar cell using a novel processing sequence to form a solar cell device. In one embodiment, the methods include forming a doping layer on a back surface of a substrate, heating the doping layer and substrate to cause the... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100015757 - Bridge resistance random access memory device and method with a singular contact structure: A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20100015758 - Nonvolatile memory device and fabrication method thereof: A nonvolatile memory device and a method for its fabrication may ensure uniform operating characteristics of ReRAM. The ReRam may include a laminated resistance layer that determines phase of ReRAM on an upper edge of a lower electrode for obtaining a stable threshold drive voltage level.... Agent: Marshall, Gerstein & Borun LLP
20100015759 - Pop semiconductor device manufacturing method: The objective of the invention is to prevent electrostatic destruction of semiconductor chips during resin molding. With the semiconductor device manufacturing method, a substrate 400 that includes on the surface multiple semiconductor chips 410 and liquid resin 434 supplied to multiple semiconductor devices is supported by an electrically insulated lower... Agent: Texas Instruments Incorporated
20100015760 - Semiconductor device and manufacturing method thereof: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package... Agent: Miles & Stockbridge PC
20100015761 - Thermally enhanced single inline package (sip): In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A leadframe (210, 310, 410) having a die pad (220, 320, 420) to attach an IC die (230, 330), a first plurality of conductive leads (240,... Agent: Texas Instruments Incorporated
20100015762 - Solder interconnect: Various solder interconnect methods and apparatus are disclosed. In aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a circuit board with plural solder joints whereby an interstitial space is left between the semiconductor chip and the circuit board. The semiconductor chip and the circuit... Agent: Timothy M Honeycutt Attorney At Law
20100015763 - Rescue structure and method for laser welding: A rescue structure to repair an open wire includes a first metal layer having at least a rescue line, an isolation layer formed on the first metal layer, and a second metal layer formed on the isolation layer. The second metal layer has at least a signal line crossing the... Agent: Birch Stewart Kolasch & Birch
20100015764 - Semiconductor device and manufacturing method thereof: The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film... Agent: Fish & Richardson P.C.
20100015765 - Shallow and deep trench isolation structures in semiconductor integrated circuits: A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A... Agent: Schmeiser, Olsen & Watts
20100015766 - Complementary stress memorization technique layer method: A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous... Agent: Texas Instruments Incorporated
20100015767 - Cell region layout of semiconductor device and method of forming contact pad using the same: A cell region layout of a semiconductor device formed by adding active regions in the outermost portion of a cell region, and a method of forming a contact pad using the same are provided. The layout and the method include a first active region formed at the outermost portion of... Agent: Joricel Celis
20100015768 - Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (seg) layer: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.... Agent: Lee & Morse, P.C.
20100015770 - Double gate manufactured with locos techniques: This invention discloses a method for manufacturing a trenched semiconductor power device that includes step of opening a trench in a semiconductor substrate. The method further includes a step of opening a top portion of the trench first then depositing a SiN on sidewalls of the top portion followed by... Agent: Bo-in Lin
20100015769 - Power device with trenches having wider upper portion than lower portion: A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and... Agent: Townsend And Townsend And Crew, LLP
20100015771 - Method of fabricating strained silicon transistor: A method of fabricating a strained silicon transistor is provided. Amorphous silicon is formed below the transistor region before the transistor is formed. By using the tensile/compressive strainer, amorphous silicon is recrystallized to form a strained silicon layer. In addition, the dopants in the well can be driven in and... Agent: North America Intellectual Property Corporation
20100015772 - Method of manufacturing semiconductor device: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a... Agent: Morrison & Foerster LLP
20100015773 - Sonos memory device having curved surface and method for fabricating the same: A radius of curvature of the upper surface of a blocking oxide can be designed to be larger than that of the lower surface of a tunneling oxide, which restrains electrons from passing through the blocking oxide by back-tunneling on erasing. As a result, a SONOS memory device shows an... Agent: F. Chau & Associates, LLC
20100015774 - Semiconductor device and method of manufacturing the same: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100015775 - Method for fabricating semiconductor device with recess gate: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening... Agent: Ip & T Law Firm PLC
20100015777 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device, includes forming an amorphous silicon film above a semiconductor substrate, partially removing each of the amorphous silicon film and the semiconductor substrate, thereby forming an element isolation trench in a surface of the semiconductor substrate, forming an insulating film above the amorphous silicon... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100015776 - Shallow trench isolation corner rounding: A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in... Agent: Slater & Matsil, L.L.P.
20100015778 - Method of forming finned semiconductor devices with trench isolation: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)
20100015779 - Method for producing bonded wafer: m
20100015780 - Transfer method with a treatment of a surface to be bonded: A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor wafer... Agent: Winston & Strawn LLP Patent Department
20100015781 - Semiconductor substrate, and semiconductor device and method of manufacturing the semiconductor device: In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of... Agent: Steptoe & Johnson LLP
20100015783 - Method of cutting an object to be processed: A method of cutting an object which can accurately cut the object is provided. An object to be processed 1 such as a silicon wafer is irradiated with laser light L while a light-converging point P is positioned therewithin, so as to form a modified region 7 due to multiphoton... Agent: Drinker Biddle & Reath (dc)
20100015782 - Wafer dicing methods: Semiconductor wafer dicing methods are disclosed. These methods include forming etch patterns between adjacent semiconductor dice to be separated. Various etch processes can be used to form the etch patterns. The etch patterns generally reach a pre-determined depth into the wafer substrate significantly beyond the wafer top layer where pre-fabricated... Agent: Slater & Matsil, L.L.P.
20100015784 - Semiconductor device manufacturing method: In a semiconductor device manufacturing method in which a wafer formed with devices in a plurality of areas sectioned by a plurality of streets formed in a lattice-like pattern on the front surface is divided into the individual devices along the streets, when the wafer is divided into the individual... Agent: Greer, Burns & Crain
20100015785 - Method for reducing a reset current for resetting a portion of a phase change material in a memory cell of a phase change memory device and the phase change memory device: According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the... Agent: Harness, Dickey & Pierce, P.L.C
20100015786 - Vapor growth apparatus, vapor growth method, and method for manufacturing semiconductor device: A vapor growth apparatus forming a film on a substrate using a first source gas and a second source gas different form the first source gas, includes: a reaction chamber in which the substrate is disposed; a first source gas introduction path that communicates with the reaction chamber and introduces... Agent: Patterson & Sheridan, L.L.P.
20100015787 - Realizing n-face iii-nitride semiconductors by nitridation treatment: A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition.... Agent: Slater & Matsil, L.L.P.
20100015788 - Method for manufacturing semiconductor device: Plasma doping is performed by exposing a support substrate 11 made of a semiconductor to a plasma generated from a mixed gas of boron 51 which is an impurity and hydrogen 52 and helium 53 which are diluents so as to implant the boron 51 into the support substrate 11.... Agent: Mcdermott Will & Emery LLP
20100015789 - Manufacturing method of semiconductor device, and semiconductor device: A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls 112 formed on the sidewalls of the gate electrode 108; a silicide layer 132 formed lateral to the sidewalls 112 of the first gate... Agent: Young & Thompson
20100015790 - Tic as a thermally stable p-metal carbide on high k sio2 gate stacks: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the... Agent: Scully, Scott, Murphy & Presser, P.C.
20100015791 - Supply apparatus, semiconductor manufacturing apparatus and semiconductor manufacturing method: A film of uniform thickness can be formed on the entire surface of a substrate. A processing solution supply apparatus includes: a nozzle provided with a supply hole for discharging a plating solution toward a processing surface of a substrate held in a substantially horizontal direction; a temperature controller for... Agent: Pearne & Gordon LLP
20100015792 - Bonding metallurgy for three-dimensional interconnect: A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive... Agent: Slater & Matsil, L.L.P.
20100015793 - Contact surrounded by passivation and polymide and method therefor: A semiconductor device has contact between the last interconnect layer and the bond pad that includes a barrier metal between the bond pad and the last interconnect layer. Both a passivation layer and a polyimide layer separate the last interconnect layer and the bond pad. The passivation layer is patterned... Agent: Freescale Semiconductor, Inc. Law Department
20100015794 - Packaging conductive structure and method for forming the same: A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100015795 - Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof: A semiconductor device includes a semiconductor substrate, and a plurality of wiring lines provided on one side of the semiconductor substrate, each of the wiring lines having a connection pad portion. An overcoat film is provided on the wiring lines and the one side of the semiconductor substrate. The overcoat... Agent: Frishauf, Holtz, Goodman & Chick, PC
20100015796 - Semiconductor device, manufacturing method and apparatus for the same: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on... Agent: Sughrue Mion, PLLC
20100015797 - Manufacturing method of semiconductor device: When a tungsten film (43) is embedded inside of a conductive groove (4A) formed in a wafer (W2) and a silicon oxide film (36) thereon and having a high aspect ratio, film formation and etch back of the tungsten film (43) are successively performed in a chamber of the same... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100015798 - Method for forming a ruthenium metal cap layer: A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface... Agent: Tokyo Electron U.s. Holdings, Inc.
20100015800 - Method for forming metal film using carbonyl material, method for forming multi-layer wiring structure, and method for manufacturing semiconductor device: A film forming method includes a first step of supplying a carbonyl material including a metallic element onto a surface of a substrate to be processed in a form of gas phase molecules along with a suppressor gas suppressing a decomposition of the carbonyl material, wherein a partial pressure of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100015799 - Semiconductor device manufacturing method, semiconductor device manufacturing apparatus, computer program and storage medium: A semiconductor device, which suppresses formation of an organic impurity layer and has excellent adhesiveness to a copper film and a metal to be a base, is manufactured. A substrate (wafer W) coated with a barrier metal layer (base film) 13 formed of a metal having a high oxidation tendency,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100015801 - Method of forming a seam-free tungsten plug: A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of... Agent: Mills & Onello LLP
20100015802 - Dynamic schottky barrier mosfet device and method of manufacture: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically... Agent: Lemaire Patent Law Firm, P.l.l.c.
20100015803 - Method for fabricating semiconductor device using dual damascene process: A method for fabricating a semiconductor device using a dual damascene process is provided. The method includes forming a dielectric layer over a conductive layer, forming a via hole exposing the conducting layer by selectively etching the dielectric layer, projecting a portion of the dielectric layer at an edge of... Agent: Ip & T Law Firm PLC
20100015804 - Methods for removing a metal-comprising material from a semiconductor substrate: Methods for removing metal-comprising materials from semiconductor materials are provided. In accordance with an exemplary embodiment, a method comprises providing a metal-comprising material overlying a semiconductor material and exposing the metal-comprising material to an aqueous non-chlorine-comprising acid solution having a pH of about less 7.... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)
20100015805 - Wet etching methods for copper removal and planarization in semiconductor processing: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments,... Agent: Weaver Austin Villeneuve & Sampson LLP - Novl Attn.: Novellus Systems, Inc.
20100015807 - Chemical mechanical polishing composition for copper comprising zeolite: The present invention relates to a CMP slurry composition for polishing a copper film in a semiconductor device fabricating process. The CMP composition for polishing a substrate comprising copper comprises zeolite, an oxidizer and a complexing agent and a content of the complexing agent is 0.01˜0.8 weight % with respect... Agent: The Webb Law Firm, P.C.
20100015806 - Cmp polishing slurry, additive liquid for cmp polishing slurry, and substrate-polishing processes using the same: The invention relates to a CMP polishing slurry containing cerium oxide particles, a dispersing agent, a water-soluble polymer and water, wherein the water-soluble polymer includes a polymer obtained by polymerizing a monomer including at least one of a carboxylic acid having an unsaturated double bond and a salt thereof, using... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100015808 - Impact sensor and method for manufacturing the impact sensor: An impact sensor comprises a silicon substrate; an insulating layer formed over the silicon substrate; a plurality of beams having flexibility that are formed of conductive silicon material; a fixing portion to fix a fixed end of each of the beams, the fixing portion being formed of conductive silicon material;... Agent: Rabin & Berdo, PC
20100015809 - Organic line width roughness with h2 plasma treatment: A method for reducing very low frequency line width roughness (LWR) in forming etched features in an etch layer disposed below a patterned organic mask is provided. The patterned organic mask is treated to reduce very low frequency line width roughness of the patterned organic mask, comprising flowing a treatment... Agent: Beyer Law Group LLP
20100015810 - Surface processing method and surface processing apparatus: A processing object 2 is sucked and fixed by a sucker 11 and rotated by a rotator 12. In that state, a processing liquid supplied from a processing liquid supply 22 is applied through a processing liquid application tube 21 onto a surface of the processing object 2. Thermal electrons... Agent: Drinker Biddle & Reath (dc)
20100015812 - Method and apparatus for processing workpiece: The present invention is a processing method for applying predetermined processing to a workpiece with said workpiece mounted on a mounting stage arranged in a process chamber in a depressurized atmosphere, in which when no workpiece is mounted on the mounting stage, an inactive gas is discharged from at least... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100015811 - Substrate processing apparatus and semiconductor device manufacturing method for forming film: Provided is a substrate processing apparatus. The substrate processing apparatus includes a process chamber, a gas supply system, a gas discharge system, an RF (radio frequency) unit, an electrode, and a control device. The control device controls the gas supply system, the gas discharge system, and the RF unit. While... Agent: Brundidge & Stanger, P.C.
20100015813 - Gap processing: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf... Agent: Brooks, Cameron & Huebsch , PLLC
20100015814 - Mosfet device with localized stressor: MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material... Agent: Slater & Matsil, L.L.P.
20100015815 - Plasma oxidizing method, plasma processing apparatus, and storage medium: A plasma oxidizing method includes a step of placing an object to be processed and having a surface containing silicon on a susceptor disposed in a processing vessel of a plasma processing apparatus, a step of producing a plasma from a processing gas containing oxygen in the processing vessel, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100015816 - Methods to promote adhesion between barrier layer and porous low-k film deposited from multiple liquid precursors: A method for processing a substrate is provided, wherein a first organosilicon precursor, a second organosilicon precursor, a porogen, and an oxygen source are provided to a processing chamber. The first organosilicon precursor comprises compounds having generally low carbon content. The second organosilicon precursor comprises compounds having higher carbon content.... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100015817 - Vertical heat treatment boat and heat treatment method for semiconductor wafer: The present invention provides a vertical heat treatment boat that has at least four or more support portions per processing target substrate to be supported, the support portions horizontally supporting the processing target substrate, support auxiliary members on which the processing target substrate is mounted being detachably attached to the... Agent: Oliff & Berridge, PLC
20100015818 - Method for producing a stop zone in a semiconductor body and semiconductor component having a stop zone: A method for producing a buried stop zone in a semiconductor body and a semiconductor component having a stop zone, the method including providing a semiconductor body having a first and a second side and a basic doping of a first conduction type. The method further includes irradiating the semiconductor... Agent: Coats & Bennett/infineon Technologies01/14/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100009467 - Novel magnetic tunnel junction (mtj) to reduce spin transfer magnetization switching current: A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×106 A/cm2 is disclosed. The MTJ has a Co60Fe20B20/MgO/Co60Fe20B20 configuration where the CoFeB AP1 pinned and free layers are amorphous and the crystalline MgO tunnel barrier is formed by a ROX or NOX process. The capping layer... Agent: Saile Ackerman LLC
20100009466 - Semiconductor device and manufacturing method of the same: An interlayer insulating film (14) covering a ferroelectric capacitor is formed and a contact hole (19) reaching a top electrode (11a) is formed in the interlayer insulating film (14). An Al wiring (17) connected to the top electrode (11a) via the contact hole (19) is formed on the interlayer insulating... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100009468 - Method of manufacture for semiconductor package with flow controller: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate... Agent: Law Offices Of Mikio Ishimaru
20100009469 - Plasma doping method and apparatus: During a plasma discharging process, a laser beam having a certain exciting wavelength is applied to a surface of a process substrate, so as to measure, using scattered light, an impurity density and a crystal state on the surface of the process substrate.... Agent: Mcdermott Will & Emery LLP
20100009470 - Within-sequence metrology based process tuning for adaptive self-aligned double patterning: An apparatus for adaptive self-aligned dual patterning and method thereof. The method includes providing a substrate to a processing platform configured to perform an etch process and a deposition process and a metrology unit configured for in-vacuo critical dimension (CD) measurement. The in-vacuo CD measurement is utilized for feedforward adaptive... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP
20100009471 - Adapter board and method for manufacturing same, probe card, method for inspecting semiconductor wafer, and method for manufacturing semiconductor device: An adapter board includes a package substrate having a first surface and a second surface and further including a board having wirings formed therein, pads disposed in the device side, and the pads disposed in the bump side, an insulating resin layer joined to the first surface, through holes formed... Agent: Mcginn Intellectual Property Law Group, PLLC
20100009472 - Edge exclusion zone patterning for solar cells and the like: The edge profile (and optionally the physical and electrical characteristics) of a wafer is determined. Useful regions of the wafer in an edge exclusion zone may then be identified. A customized grid array layout is created specific to that wafer from an analysis of the edge profile, for example having... Agent: JasIPConsulting
20100009473 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes preparing two substrates having a first and a second surface and having first and second pads and a second testing-dedicated pad, the first pads in the first surface, the second pads in the second surface and arranged with an inter-pad distance that... Agent: Mcginn Intellectual Property Law Group, PLLC
20100009474 - Method of growing carbon nanotubes and method of manufacturing field emission device using the same: A method of growing carbon nanotubes and a method of manufacturing a field emission device using the same is provided. The method of growing carbon nanotubes includes steps of preparing a substrate, forming a catalyst metal layer on the substrate to promote growing of carbon nanotubes, forming an inactivation layer... Agent: Robert E. Bushnell & Law Firm
20100009475 - Disk laser including an amplified spontaneous emission (ase) suppression feature: A laser system may include a first portion of laser host material adapted for amplification of laser radiation and a second portion of laser host material surrounding the first portion which may be adapted for suppression of ASE. The first portion of laser host material and the second portion of... Agent: Moore And Van Allen PLLC For Boeing
20100009477 - Semiconductor light emitting device and method of manufacturing the same: Provided is a semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device. The semiconductor light emitting device includes a substrate, at least two light emitting cells located on the substrate and formed by stacking semiconductor material layers, a reflection layer and a transparent insulating layer... Agent: Buchanan, Ingersoll & Rooney PC
20100009476 - Substrate structure and method of removing the substrate structure: A method of removing a substrate structure is described. A plurality of pillars is formed on a substrate by using a photolithography etching process. A group III nitride semiconductor layer is grown on the plurality of pillars. The plurality of pillars is etched to separate the group III nitride semiconductor... Agent: Wpat, PC Intellectual Property Attorneys
20100009478 - Ips mode liquid crystal display device and method for fabricating thereof: An IPS mode LCD device and a method for fabricating the same are disclosed. A switching device is formed at each unit pixel and then a passivation layer is formed thereon. A first concave pattern and a second concave pattern at each unit pixel by using one mask are formed,... Agent: Birch Stewart Kolasch & Birch
20100009479 - Liquid crystal display and thin film transistor panel therefor: A thin film transistor panel for a liquid crystal display includes a substrate, a plurality of data lines formed over the substrate and extending in a first direction, and a plurality of gate lines formed over the substrate and extending in a second direction. The plurality of gate lines cross... Agent: F. Chau & Associates, LLC
20100009480 - Method for fabricating liquid crystal display device: A thin film transistor including: an active layer on a substrate, the active layer having at least two unit channels; and source and drain electrodes on the active layer, wherein an interval D between each of the channels is larger than a unit channel width W.... Agent: Mckenna Long & Aldridge LLP
20100009481 - Method for fabricating thin film transistor array substrate: A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and... Agent: Jianq Chyun Intellectual Property Office
20100009482 - Photoresist composition, method of forming a metal pattern, and method of manufacturing a display substrate using the same: A photoresist composition includes 5% to 50% by weight of an alkali-soluble resin, 0.5% to 30% by weight of a quinone diazide compound, 0.1% to 15 % by weight of a curing agent, and a remainder of an organic solvent. A method of forming a metal pattern includes coating a... Agent: H.c. Park & Associates, PLC
20100009483 - Method for fabricating a nitride-based semiconductor light emitting device: An exemplary method includes the following steps. First, a substrate is provided. Second, a nitride-based multi-layered structure is epitaxially grown on the substrate. The multi-layered structure includes a first-type layer, an active layer, and a second-type layer arranged one on the other in that order along a direction away from... Agent: PCe Industry, Inc. Att. Steven Reiss
20100009484 - Method of fabricating quantum well structure: In the method of fabricating a quantum well structure which includes a well layer and a barrier layer, the well layer is grown at a first temperature on a sapphire substrate. The well layer comprises a group III nitride semiconductor which contains indium as a constituent. An intermediate layer is... Agent: Venable LLP
20100009485 - Semiconductor light emitting device, method of manufacturing same, and optical module: A semiconductor light emitting device capable of realizing a long life, and a method of manufacturing the same. The impurity concentration of hydrogen in the active layer is 3×1019 cm−3 or less, and the impurity concentration of aluminum in the active layer is 1×1018 cm−3 or less. Thereby, the operating... Agent: Sonnenschein Nath & Rosenthal LLP
20100009486 - Light emitting diode and method of making the same: A light emitting diode (LED) and a method of making the same are disclosed. The present invention uses a metal layer of high conductivity and high reflectivity to prevent the substrate from absorbing the light emitted. This invention also uses the bonding technology of dielectric material thin film to replace... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100009488 - Method to form a photovoltaic cell comprising a thin lamina: A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or... Agent: The Mueller Law Office, P.C.
20100009487 - Ono spacer etch process to reduce dark current: A method of forming a CMOS image sensor device. The method includes providing a semiconductor substrate having a P-type impurity characteristic. The semiconductor substrate includes a surface region. The method includes forming a gate oxide layer overlying the surface region and forming a first gate structure overlying a first portion... Agent: Townsend And Townsend And Crew, LLP
20100009489 - Method and system for producing a solar cell using atmospheric pressure plasma chemical vapor deposition: A process and system for producing a thin-film solar cell using atmospheric pressure plasma chemical vapor deposition is disclosed. A plasma at substantially atmospheric pressure is used to deposit P-type layers, intrinsic layers and N-type layers to form one or more P-N junctions for use in a solar cell. The... Agent: Murabito, Hao & Barnes, LLP
20100009490 - Method for fabricating a solid-state imaging device: A method for manufacturing a solid-state imaging device. A solid-state image sensor is mounted on the semiconductor package support and electrically connected to first terminals and second terminals by bonding wires. The second terminals to which the bonding wires are connected are sealed with a sealing member. The optically-transparent member... Agent: Sonnenschein Nath & Rosenthal LLP
20100009491 - Joined wafer, fabrication method thereof, and fabrication method of semiconductor devices: A method of fabricating a joined wafer has an exposure process which comprises a device formed-area exposure process of exposing by a stepper such that parts of the photosensitive adhesive layer formed over a surface of the transparent wafer or the device formed wafer are removed, the parts corresponding to... Agent: Rabin & Berdo, PC
20100009492 - Method for production of thin semiconductor solar cells and integrated circuits: The invention relates to the formation of thin-film crystalline silicon using a zone-melting recrystallization process in which the substrate is a ceramic material. Integrated circuits and solar cells are fabricated in the recrystallized silicon thin film and lifted off the substrate. Following lift-off, these circuits and devices are self-sustained, lightweight... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw
20100009494 - Dye-sensitized solar cell and fabrication method thereof: Disclosed is a dye-sensitized solar cell with enhanced photoelectric conversion efficiency. The dye-sensitized solar cell includes a first electrode of a light transmission material, a second electrode facing the first electrode, and a dye-absorbed porous layer formed on the first electrode. An electrolyte is injected between the first and the... Agent: Christie, Parker & Hale, LLP
20100009493 - Methods of manufacturing an image sensor: The method of manufacturing an image sensor includes providing a semiconductor substrate including a first pixel region, first forming a first pattern on the first pixel region, first performing a reflow of the first pattern to form a sub-micro lens on the first pixel region, second forming a second pattern... Agent: Harness, Dickey & Pierce, P.L.C
20100009495 - Anti-reflective device having an anti-reflective surface formed of silicon spikes with nano-tips: Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate.... Agent: Tope-mckay & Associates
20100009496 - Structuring device for structuring plate-like elements, in particular thin-film solar modules: A structuring device is for structuring a plate-like element. A solar module and/or a thin-film solar module comprises a plurality of structuring tools which are configured respectively for introducing a track into the plate-like element, characterised by a first structuring unit which has a plurality of these structuring tools, at... Agent: Fay Kaplun & Marcin, LLP
20100009497 - Performance improvements of ofets through use of field oxide to control ink flow: An OFET includes a thick dielectric layer with openings in the active region of a transistor. After the field dielectric layer is formed, semiconductor ink is dropped in the active region cavities in the field dielectric layer, forming the semiconductor layer. The ink is bounded by the field dielectric layer... Agent: Weyerhaeuser Company Intellectual Property Dept., Ch 1j27
20100009498 - Planar interconnect structure for hybrid circuits: Described herein is an electronic device in which one or more planar interconnect structure are interposed between two substrates each incorporating a hybrid circuit. The planar interconnect structure has a plurality of conductive traces formed on one of its faces for electrically connecting sets of interconnection points of each of... Agent: Schwegman, Lundberg & Woessner, P.A.
20100009499 - Stacked microelectronic layer and module with three-axis channel t-connects: A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted... Agent: Foley & Lardner LLP
20100009500 - Aluminum leadframes for semiconductor qfn/son devices: A post-mold plated semiconductor device has an aluminum leadframe (105) with a structure including a chip mount pad and a plurality of lead segments without cantilevered lead portions. A semiconductor chip (210) is attached to the chip mount pad, and conductive connections (212) span from the chip to the aluminum... Agent: Texas Instruments Incorporated
20100009501 - Packaging structure, method for manufacturing the same, and method for using the same: A packaging structure applied for a surface mounting process, comprising: a chip module having a packaging surface; and a pre-cured layer formed on the packaging surface of the chip module. As above-mentioned, the structure is employed for protecting the external surface of the wafer. The pre-cured layer is formed on... Agent: Rosenberg, Klein & Lee
20100009502 - Semiconductor fabrication process including an sige rework method: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions... Agent: Brinks Hofer Gilson & Lione
20100009503 - Method of forming dielectric layer above floating gate for reducing leakage current: A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed... Agent: Vierra Magen/sandisk Corporation
20100009504 - Systems and methods for a high density, compact memory array: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to... Agent: Baker & Mckenzie LLP Patent Department
20100009505 - Semiconductor device having a vertical transistor and method for manufacturing the same: A semiconductor device having a vertical transistor comprises a silicon substrate; a drain region, a channel region and a source region vertically stacked on the silicon substrate; a buried type bit line formed under the drain region in the silicon substrate to contact with the drain region and to extend... Agent: Townsend And Townsend And Crew, LLP
20100009506 - Dopant implantation method and integrated circuits formed thereby: A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without... Agent: Duane Morris LLP (tsmc)IPDepartment
20100009507 - Method of constructing cmos device tubs: The present invention provides a method of fabricating an integrated circuit comprising at least one bipolar transistor and at least one field effect transistor. The method includes implanting a dopant species of a first type in a semiconductor layer that is doped with a dopant of a second type opposite... Agent: Williams, Morgan & Amerson
20100009509 - Dual-damascene process to fabricate thick wire structure: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch... Agent: Greenblum & Bernstein, P.L.C
20100009508 - Methods of fabricating stack type capacitors of semiconductor devices: Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas... Agent: Harness, Dickey & Pierce, P.L.C
20100009510 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device including implanting an impurity ion into a predetermined region of a semiconductor layer using a resist film as a mask, wherein in case when a mask data ratio for implanting the impurity ion only into the predetermined region in the resist film is... Agent: Mcginn Intellectual Property Law Group, PLLC
20100009511 - Programmable capacitor associated with an input/output pad: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first... Agent: Dorsey & Whitney LLP Intellectual Property Department
20100009512 - Methods of forming a plurality of capacitors: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps... Agent: Wells St. John P.s.
20100009513 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a gate electrode film on the gate insulating film, and forming a plurality of trenches by etching the gate electrode film, the gate insulating film and the semiconductor substrate so that an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100009514 - Method of fabricating micro-vertical structure: A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a... Agent: Ampacc Law Group
20100009515 - Laser lift-off method: The present invention discloses a laser lift-off method, which applies to lift off a transient substrate from an epitaxial layer grown on the transient substrate after a support substrate having an adhesion metal layer is bonded to the epitaxial layer. Firstly, the epitaxial layer is etched to define separation channels... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20100009516 - Method for growth of gan single crystal, method for preparation of gan substrate, process for producing gan-based element, and gan-based element: A GaN-based thin film (thick film) is grown using a metal buffer layer grown on a substrate. (a) A metal buffer layer (210) made of, for example, Cr or Cu is vapor-deposited on a sapphire substrate (120). (b) A substrate obtained by vapor-depositing the metal buffer layer (210) on the... Agent: Cowan Liebowitz & Latman P.c
20100009517 - Process for inhibiting corrosion and removing contaminant from a surface during wafer dicing and composition useful therefor: Adherence of contaminant residues or particles is suppressed, corrosion of exposed surfaces is substantially reduced or eliminated during the process of dicing a wafer by sawing. A fluoride-free aqueous composition comprising a dicarboxylic acid and/or salt thereof; a hydroxycarboxylic acid and/or salt thereof or amine group containing acid, a surfactant... Agent: Air Products And Chemicals, Inc. Patent Department
20100009518 - Particle free wafer separation: A method for singulating semiconductor wafers is disclosed. A preferred embodiment comprises forming scrub lines on one side of the wafer and filling the scrub lines with a temporary fill material. The wafer is then thinned by removing material from the opposite side of the wafer from the scrub lines,... Agent: Slater & Matsil, L.L.P.
20100009519 - Method of thinning a semiconductor wafer: A method for manufacturing a thin semiconductor wafer. A semiconductor wafer is thinned from its backside followed by the formation of a cavity in a central region of the backside of the semiconductor wafer. Forming the cavity also forms a ring support structure in a peripheral region of the semiconductor... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700
20100009521 - Method of producing semiconductor wafer: The method is characterized by comprising a slicing step of cutting out a thin disc-shaped raw wafer from a crystalline ingot; a fixed grain bonded abrasive grinding step of sandwiching the raw wafer between a pair of upper and lower platens each having a pad of fixed grain bonded abrasive... Agent: Christensen, O'connor, Johnson, Kindness, PLLC
20100009520 - Wafer processing method for improving gettering capabilities of wafers made therefrom: A wafer processing method for improving gettering capabilities of wafers made therefrom is presented. The method includes the steps of preparing, annealing and ion-implanting. The preparing step involves preparing the wafer from a silicon ingot. The annealing step involves forming first gettering sites in both sides of the wafer by... Agent: Ladas & Parry LLP
20100009522 - Method for forming chalcogenide switch with crystallized thin film diode isolation: A three-dimensional memory array formed of one or more two-dimensional memory arrays of one-time programmable memory elements arranged in horizontal layers and stacked vertically upon one another; and a two-dimensional memory array of reprogrammable phase change memory elements stacked on the one or more two-dimensional memory arrays as the top... Agent: David W. Schumaker Energy Conversion Devices, Inc.
20100009523 - Mask and method of fabricating a polysilicon layer using the same: A mask includes a primary opaque pattern and a number of clusters of secondary opaque patterns. The primary opaque pattern defines a number of strip transparent slits whose extending directions are substantially the same. The clusters of the secondary opaque patterns are connected to the primary opaque pattern, and each... Agent: Jianq Chyun Intellectual Property Office
20100009524 - Method for improving semiconductor surfaces: A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atom percent of the semiconductor material... Agent: Schmeiser, Olsen & Watts
20100009525 - Method including producing a monocrystalline layer: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface... Agent: Dicke, Billig & Czaja
20100009526 - Fabrication method and fabrication apparatus of group iii nitride crystal substance: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group... Agent: Mcdermott Will & Emery LLP
20100009527 - Integrated circuit system employing single mask layer technique for well formation: A method for manufacturing an integrated circuit system that includes: providing a substrate; forming a mask layer over the substrate; implanting a first well through an opening in the mask layer into the substrate; and implanting a second well through the mask layer and the opening via a single implant... Agent: Law Offices Of Mikio Ishimaru
20100009528 - Method for rapid thermal treatment using high energy electromagnetic radiation of a semiconductor substrate for formation of dielectric films: A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer... Agent: Townsend And Townsend And Crew, LLP
20100009529 - Method of manufacturing a semiconductor device: Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching... Agent: Miles & Stockbridge PC
20100009530 - Semiconductor device fabrication method: A semiconductor device fabrication method including the steps of: forming an interlayer insulating film on a substrate; forming an opening in the interlayer insulating film; forming an alloy layer containing manganese and copper to cover the inner surface of the opening; forming a first copper layer of a material containing... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100009531 - Methods of forming a contact structure: In a method of forming a contact structure, a first insulation layer including a first contact hole is formed on a substrate. A metal layer including tungsten is formed to fill the first contact hole. A planarization process is performed on the metal layer until the first insulation layer is... Agent: Volentine & Whitt PLLC
20100009532 - Manufacturing method of semiconductor device and semiconductor manufacturing apparatus therefor: Provided is a manufacturing method for improving the reliability of a semiconductor device having a back electrode. After formation of semiconductor elements on the surface of a silicon substrate, the backside surface thereof, which is opposite to the element formation surface, is subjected to the following steps in a processing... Agent: Mattingly & Malur, P.C.
20100009533 - Conformal films on semiconductor substrates: A layer of diffusion barrier or seed material is deposited on a semiconductor substrate having a recessed feature. The method may include a series of new deposition cycles, for example, a first net deposition cycle and a second net deposition cycle. The first net deposition cycle includes depositing a first... Agent: Weaver Austin Villeneuve & Sampson LLP - Novl Attn.: Novellus Systems, Inc.
20100009534 - Method for patterning a semiconductor device: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer, forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the... Agent: Sherr & Vaughn, PLLC
20100009535 - Methods and systems for barrier layer surface passivation: This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate... Agent: Larry Williams
20100009536 - Multilayer low reflectivity hard mask and process therefor: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20100009537 - Method of polishing nickel-phosphorous: The invention is directed to a method of chemically-mechanically polishing a a surface of a substrate, comprising contacting a surface of a substrate comprising nickel-phosphorous with a chemical-mechanical polishing composition comprising wet-process silica, an agent that oxidizes nickel-phosphorous, and an aminopolycarboxylic acid, wherein the polishing composition has a pH of... Agent: Steven Weseman Associate General Counsel, I.p.
20100009538 - Silicon nitride polishing liquid and polishing method: A silicon nitride polishing liquid for chemical mechanical polishing of a body to be polished in a planarization process for manufacturing of a semiconductor integrated circuit, the body to be polished including at least a first layer containing silicon nitride and a second layer containing at least one silicon-including material... Agent: Akerman Senterfitt
20100009539 - Cerium oxide powder, method for preparing the same, and cmp slurry comprising the same: Disclosed is cerium oxide powder for a CMP abrasive, which can improve polishing selectivity of a silicon oxide layer to a silicon nitride layer and/or within-wafer non-uniformity (WIWNU) during chemical mechanical polishing in a semiconductor fabricating process. More particularly, the cerium oxide powder is obtained by using cerium carbonate having... Agent: Mckenna Long & Aldridge LLP
20100009540 - Polishing compound, its production process and polishing method: A polishing compound for chemical mechanical polishing of a substrate, which comprises (A) abrasive grains, (B) an aqueous medium, (C) tartaric acid, (D) trishydroxymethylaminomethane and (E) at least one member selected from the group consisting of malonic acid and maleic acid, and more preferably, which further contains a compound having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100009541 - Process for adjusting the size and shape of nanostructures: In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto... Agent: Polster, Lieder, Woodruff & Lucchesi
20100009542 - Substrate processing method: A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100009543 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. The method includes sequentially depositing a polishing stop film and a mask oxide film on a semiconductor substrate, forming a photosensitive film pattern on the mask oxide film to expose a device isolation region, sequentially etching the mask oxide film and... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20100009544 - Manufacturing method of semiconductor device: A coating solution of SOG is applied on a silicon oxynitride film (11) and precured. As a result, moisture contained in the coating solution volatilizes, and an SOG film (12) is formed. Next, a coating solution of SOG is applied on the SOG film (12) and precured. As a result,... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100009545 - Methods of fabricating oxide layers on silicon carbide layers utilizing atomic oxygen: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C.,... Agent: Myers Bigel Sibley & Sajovec, P.A.
20100009546 - Aminosilanes for shallow trench isolation films: t
20100009547 - Laser working method: An object to be processed is restrained from warping at the time of laser processing. A modified region M2 is formed within a wafer 11, and fractures a2, b2 extending in directions parallel to the thickness direction of the wafer 11 and tilted with respect to a plane including lines... Agent: Drinker Biddle & Reath (dc)
20100009548 - Method for heat-treating silicon wafer: Provided is a heat treatment method wherein generation of slip dislocation in silicon wafer RTP is suppressed, in order to solve a problem of not sufficiently suppressing generation of slip dislocation of silicon wafers in conventional RTP. A step is provided for suspending temperature rising for 10 seconds or longer... Agent: Kratz, Quintos & Hanson, LLP
20100009549 - Wafer treating method: A wafer treating method includes the steps of irradiating a wafer, provided with devices on the face side, from the back side with a laser beam capable of being transmitted through the wafer, while converging the laser beam to a predetermined depth, so as to form a denatured layer between... Agent: Greer, Burns & Crain
20100009550 - Method and apparatus for modifying integrated circuit by laser: [MEANS FOR SOLVING PROBLEMS] A method is provided for selectively cutting a plurality of conductive links embedded in a protection layer which covers at least the conductive links in a semiconductor device formed on a semiconductor substrate. A focused beam is aligned with a target link, a first pulsed laser... Agent: Pearne & Gordon LLP
20100009551 - Semiconductor device and method for manufacturing the same: A p-n junction is formed at the interface of a low-concentration n-type impurity layer and a p-type diffusion region in the vicinity of the upper major surface of an n-type semiconductor substrate of a semiconductor device. A mask composed of an absorber is placed on the upper major surface of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.01/07/2010 > patent applications in patent subcategories. recently filed with US Patent Office
20100003767 - Magnetic tunnel junction device, memory cell having the same, and method for fabricating the same: A method for fabricating a magnetic tunnel junction device includes forming an insulation layer having a plurality of openings, forming a first electrode over the bottom and the sidewall of an opening of the plurality of openings, forming a magnetic tunnel junction layer over the first electrode, and forming a... Agent: Ip & T Law Firm PLC
20100003768 - System and method for processing substrates with detachable mask: Apparatus and methods are provided that enable processing of patterned layers on substrates using a detachable mask. Unlike prior art where the mask is formed directly over the substrate, according to aspects of the invention the mask is made independently of the substrate. During use, the mask is positioned in... Agent: Nixon Peabody, LLP
20100003770 - Elemental analysis method and semiconductor device manufacturing method: Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present... Agent: Mcdermott Will & Emery LLP
20100003769 - Method relating to the accurate positioning of a semiconductor wafer: Disclosed is a method involving repeatedly measuring a pressure within a flow of processing gas that is provided in a semiconductor processing apparatus for treatment of a semiconductor substrate, such as a semiconductor wafer. The flow of processing gas is made to extend between a surface of the substrate and... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP
20100003771 - Production method of semiconductor device and bonding film: To provide a method of manufacturing semiconductor devices, the method being capable of efficiently obtaining a singulated semiconductor chip upon which an adhesive is adhered and also capable of excellently bonding a semiconductor chip to a wiring substrate, and provide an adhesive film. A layered product 60 in which a... Agent: Griffin & Szipl, PC
20100003772 - Wafer level hermetic bond using metal alloy with raised feature: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the... Agent: Jaquelin K. Spong
20100003773 - Method for manufacturing liquid discharge head: A method for manufacturing a liquid discharge head provided with a substrate which has a layer made of silicon nitride and with a discharge port forming member which is disposed above the layer made of silicon nitride and has a discharge port for discharging liquid. The method includes providing a... Agent: Canon U.s.a. Inc. Intellectual Property Division
20100003774 - Method for fabricating pixel structure: A pixel structure fabricating method is provided. A gate is formed on a substrate. A gate insulation layer covering the gate is formed on the substrate. A channel layer, a source, and a drain are simultaneously formed on the gate insulation layer above the gate. The gate, channel layer, source,... Agent: Jianq Chyun Intellectual Property Office
20100003776 - Manufacturing method of array substrate for liquid crystal display device with color filter layer on thin film transistor: A method of manufacturing a liquid crystal display device includes forming a gate line and a gate electrode on a substrate, forming a gate insulating layer on substantially an entire surface of the substrate, forming an active layer, an ohmic contact layer, a source electrode, a drain electrode and a... Agent: Birch Stewart Kolasch & Birch
20100003775 - Method of fabricating array substrate for in-plane switching mode liquid crystal display device having double-layered metal patterns: An array substrate of an in-plane switching liquid crystal display device includes, among other features, a gate electrode and a gate line having a first double-layered structure consisting of a first barrier layer and a first low resistance metallic layer; a data line defining a pixel region with the gate... Agent: Mckenna Long & Aldridge LLP
20100003777 - Quantum photonic imagers and methods of fabrication thereof: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100003778 - Method of manufacturing semiconductor laser: A method of manufacturing a semiconductor laser includes sequentially forming a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on top of one another on a semiconductor substrate; forming a ridge in the second conductivity type semiconductor layer; forming a first insulating film... Agent: Leydig Voit & Mayer, Ltd
20100003779 - Method of producing solid-state imaging device: A method of producing a solid-state imaging device according to one embodiment of the present invention is characterized in that, in a method of producing a solid-state imaging device such that a solid-state imaging element wafer is bonded to a light transmissive substrate on one surface of which spacers are... Agent: Birch Stewart Kolasch & Birch
20100003780 - Methods and apparatus for depositing a microcrystalline silicon film for photovoltaic device: Methods for depositing a microcrystalline silicon film layer with improved deposition rate and film quality are provided in the present invention. Also, a photovoltaic (PV) cell having a microcrystalline silicon film is provided. In one embodiment, the method produces a microcrystalline silicon film on a substrate at a deposition rate... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100003781 - Roll-to-roll non-vacuum deposition of transparent conductive electrodes: Methods and devices are provided for improved photovoltaic devices. Non-vacuum deposition of transparent conductive electrodes in a roll-to-roll manufacturing environment is disclosed. In one embodiment, a method is provided for forming a photovoltaic device. The method comprises processing a precursor layer in one or more steps to form a photovoltaic... Agent: Director Of Ip
20100003782 - Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over... Agent: Wells St. John P.s.
20100003783 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode.... Agent: Nixon Peabody, LLP
20100003784 - Method for mounting electronic component on printed circuit board: A method for assembling an electronic component on a printed circuit board includes following steps. Firstly, a printed circuit board substrate including a central main portion and a peripheral unwanted portion is provided. Secondly, electrically conductive patterns and reinforcing patterns are formed on the main portion and the unwanted portion... Agent: PCe Industry, Inc. Att. Steven Reiss
20100003785 - Stacked integrated circuit assembly: In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is... Agent: Pillsbury Winthrop Shaw Pittman LLP (raytheon Sas)
20100003786 - Chip-level underfill process and structures thereof: A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern. The alignment pattern is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. This is... Agent: Ibm - Yor Shimokaji & Associates, P.C.
20100003787 - Method of making a semiconductor chip assembly with a post/base heat spreader and horizontal signal routing: The present invention provides a method of making a semiconductor chip assembly that includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in... Agent: David M. Sigmond
20100003788 - Method of making a semiconductor chip assembly with a post/base heat spreader and vertical signal routing: The present invention provides a method of making a semiconductor chip assembly that includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in... Agent: David M. Sigmond
20100003789 - Method of encapsulating a microelectronic device by a getter material: A method of encapsulating a microelectronic device arranged on a substrate, comprising at least the following steps: a) formation of a portion of sacrificial material covering at least one part of the microelectronic device, the volume of which occupies a space intended to form at least one part of a... Agent: Nixon Peabody LLP
20100003790 - Method for producing a micromechanical component having a thin-layer capping: A capping technology is provided in which, despite the fact that structures which are surrounded by a silicon-germanium filling layer are exposed using ClF3 etching through micropores in the silicon cap, an etching attack on the silicon cap is prevented, namely, either by particularly selective (approximately 10,000:1 or higher) adjustment... Agent: Kenyon & Kenyon LLP
20100003791 - Method for manufacturing electronic circuit component: The method for manufacturing an electronic circuit component according to the invention includes heating a layer containing at least one of a polyimide and a precursor thereof at a temperature of 200° C. or lower to form an insulating layer 4 having a contact angle with water of 80° or... Agent: Mcdermott Will & Emery LLP
20100003792 - Method for fabricating pixel structure: A pixel structure fabricating method is provided. A gate and a gate insulation layer covering the gate are formed on a substrate. A channel layer is formed on the gate insulation layer. A conductive layer is formed on the channel layer and gate insulation layer. A black matrix having a... Agent: Jianq Chyun Intellectual Property Office
20100003793 - Method for forming silicide in semiconductor device: A method for forming silicide in a semiconductor device includes simultaneously performing a cleaning process and an etching process to remove a silicide metal layer if an excessive delay in time lapses after forming the silicide metal layer. This may prevent the occurrence of liquid marks due to an oxidation... Agent: Sherr & Vaughn, PLLC
20100003794 - Method for defect reduction for memory cell capacitors: A method for forming a cylindrical stack capacitor structure. A semiconductor substrate is provided. Storage node structures are formed in a memory cell region. A dielectric layer is formed overlying the storage node structures. A patterning and a first etching process expose the storage nodes. A polysilicon layer and a... Agent: Townsend And Townsend And Crew, LLP
20100003795 - Method for fabricating flash memory device having vertical floating gate: A method for fabricating a flash memory device includes forming a control gate having a hollow donut shape over an insulation layer formed over a substrate. The method also includes forming an inter-poly dielectric of a spacer shape on an inner wall of the control gate, filling a conductive layer... Agent: Marshall, Gerstein & Borun LLP
20100003796 - Manufacturing method of semiconductor device having self-aligned contact: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on... Agent: Jianq Chyun Intellectual Property Office
20100003797 - Method for forming transistor with high breakdown voltage: Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolaton structures. The shallow trench isolaton structures are formed by dielectric material filling trenches that are formed by pitch multiplication. During pitch multiplication,... Agent: Knobbe Martens Olson & Bear LLP
20100003798 - Semiconductor device and manufacturing method thereof: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100003799 - Method for forming p-type lightly doped drain region using germanium pre-amorphous treatment: A method for forming a MOS device with an ultra shallow lightly doped diffusion region. The method includes providing a semiconductor substrate including a surface region. The method provides a gate dielectric layer overlying the surface region and forms a gate structure overlying a portion of the gate dielectric layer.... Agent: Townsend And Townsend And Crew, LLP
20100003800 - Bipolar transistor with silicided sub-collector: Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region... Agent: International Business Machines Corporation Dept. 18g
20100003801 - Method of manufacturing a semiconductor device: A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a... Agent: Marshall, Gerstein & Borun LLP
20100003802 - Method for fabricating fin transistor: A method for fabricating a fin transistor includes patterning a first pad layer provided over a substrate using an isolation mask, etching the substrate using the isolation mask and the first pad layer to form trenches, filling the trenches with an insulating material to form isolation structures, etching the isolation... Agent: Townsend And Townsend And Crew, LLP
20100003803 - Manufacturing method of strained si substrate: According to the present invention, there is provided a manufacturing method of a strained Si substrate including at least steps of: forming a lattice-relaxed SiGe layer on a silicon single crystal substrate; flattening a surface of the SiGe layer by CMP; and forming a strained Si layer on the surface... Agent: Oliff & Berridge, PLC
20100003804 - Electronic device and method for manufacturing same: A method to provide an improved production yield of electronic devices. A thin film device 41 is manufactured by the following method. Semiconductor elements 11 are formed on the substrate 10. Then, a protective film is adhered onto the upper portions of the semiconductor elements 11 using an adhesive agent.... Agent: Smith, Gambrell & Russell
20100003806 - Deterministic generation of an integrated circuit identification number: The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of... Agent: Stmicroelectronics, Inc.
20100003805 - Semiconductor device fabrication method: A semiconductor device fabrication method for dividing a semiconductor wafer into individual devices along a plurality of streets. The method includes a masking step of attaching a mask member having a plurality of openings to the back side of the semiconductor wafer, the openings respectively corresponding to the devices formed... Agent: Greer, Burns & Crain
20100003807 - Semiconductor device manufacturing method, semiconductor manufacturing apparatus and storage medium: Provided is a method for performing etching process or film forming process to a substrate W whereupon a prescribed pattern is formed with an opening. The method is provided with a step of mixing a liquid and a gas, at least one of which contains a component that contributes to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100003809 - Method for destruction of metallic carbon nanotubes, method for production of aggregate of semiconducting carbon nanotubes, method for production of thin film of semiconducting carbon nanotubes, method for destruction of semiconducting carbon nanotubes, m: A method for destruction of metallic carbon nanotubes is provided. The method includes irradiating a mixture of semiconducting carbon nanotubes and metallic carbon nanotubes with energy beams (such as laser light), thereby selectively destroying metallic carbon nanotubes or semiconducting carbon nanotubes. The energy beams have energy components for resonance absorption... Agent: K&l Gates LLP
20100003810 - Method of forming p-type compound semiconductor layer: A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied... Agent: H.c. Park & Associates, PLC
20100003811 - Method for manufacturing epitaxial wafer: A method for manufacturing an epitaxial wafer is provided, which can alleviate distortions on a back surface of the epitaxial wafer. The method for manufacturing an epitaxial wafer using a susceptor for a vapor phase growth system having a concave shaped wafer placement portion on an upper face thereof, on... Agent: Greenblum & Bernstein, P.L.C
20100003812 - Solar cell fabrication using extrusion mask: Large-area ICs (e.g., silicon wafer-based solar cells) are produced by positioning a mask between an extrusion head and the IC wafer during extrusion of a dopant bearing material or metal gridline material. The mask includes first and second peripheral portions that are positioned over corresponding peripheral areas of the wafer,... Agent: Bever, Hoffman & Harms, LLP
20100003813 - Semiconductor device and method of fabricating the same: r
20100003814 - Interconnections having double capping layer and method for forming the same: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer... Agent: Mills & Onello LLP
20100003815 - Semiconductor device and method for manufacturing the same: A semiconductor device and method for manufacturing the same is provided, capable of gap-filling a copper metal wiring while minimizing void generation. A semiconductor device according to an embodiment includes a copper sulfide layer formed on a first barrier metal formed in a via and trench; and a via plug... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20100003816 - Method of manufacturing a semiconductor device from which damage layers and native oxide films in connection holes have been removed: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100003817 - Method of light induced plating on semiconductors: Methods of light induced plating of nickel onto semiconductors are disclosed. The methods involve applying light at an initial intensity for a limited amount of time followed by reducing the intensity of the light for the remainder of the plating period to deposit nickel on a semiconductor.... Agent: Rohm And Haas Electronic Materials LLC
20100003818 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device according to one embodiment includes: forming a porous film above a semiconductor substrate; forming an altered layer by applying alteration treatment to a first pattern region of the porous film up to a predetermined depth; forming a first concave portion by etching a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100003819 - Design layout data creating method, computer program product, and method of manufacturing semiconductor device: A design layout data creating method includes creating design layout data of a semiconductor device such that patterns formed on a wafer when patterns corresponding to the design layout data are formed on the wafer have a pattern coverage ratio within a predetermined range in a wafer surface and total... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100003820 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming in order a barrier film, an insulating film, a first mask, and a second mask having etching properties different from those of the first mask on a substrate, removing the insulating film, the first mask, and the second mask to form... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100003822 - Method for producing columnar structured material: A microcolumnar structured material having a desired material. The columnar structured material includes columnar members obtained by introducing a filler into columnar holes formed in a porous material. The porous material has the columnar holes formed by removing columnar substances from a structured material in which the columnar substances containing... Agent: Fitzpatrick Cella Harper & Scinto
20100003823 - Method for forming trenches with wide upper portion and narrow lower portion: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion... Agent: Townsend And Townsend And Crew, LLP
20100003824 - Clamped showerhead electrode assembly: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which includes an inner electrode mechanically attached to a backing plate by a clamp ring and an outer electrode attached to the backing plate by a series of spaced apart... Agent: Buchanan, Ingersoll & Rooney PC
20100003825 - Plasma etching method, control program and computer storage medium: A plasma etching method, for plasma-etching a target substrate including at least a film to be etched, an organic film to become a mask of the to-be-etched film, and a Si-containing film which are stacked in order from bottom, includes the first organic film etching step, the treatment step and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100003826 - Corrosion resistant component of semiconductor processing equipment and method of manufacture thereof: A corrosion resistant component of a plasma chamber includes a liquid crystalline polymer. In a preferred embodiment, the liquid crystalline polymer (LCP) is provided on an aluminum component having an anodized or non-anodized surface. The liquid crystalline polymer can also be provided on an alumina component. The liquid crystalline polymer... Agent: Buchanan, Ingersoll & Rooney PC
20100003827 - Method and device for etching a substrate by means of plasma: In a method and device for etching a substrate by a plasma, the plasma is generated and accelerated at substantially sub-atmospheric pressure between a cathode and an anode of a plasma source (1) in a channel of system of at least one conductive cascaded plate between the cathode and anode.... Agent: Young & Thompson
20100003828 - Methods for adjusting critical dimension uniformity in an etch process with a highly concentrated unsaturated hydrocarbon gas: Methods for etching a metal material layer disposed on a substrate to form features with desired profile and uniform critical dimension (CD) of the features across the substrate. In one embodiment, a method for etching a material layer disposed on a substrate includes providing a substrate having a metal layer... Agent: Patterson & Sheridan, LLP - - Appm/tx
20100003829 - Clamped monolithic showerhead electrode: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which... Agent: Buchanan, Ingersoll & Rooney PC
20100003830 - Imprint mask manufacturing method, imprint mask manufacturing device, and semiconductor device manufacturing method: A pattern is formed on a mask substrate. Positional deviation information between an actual position of the pattern formed on the mask substrate and a design position decided at the time of designing the pattern is calculated. A heterogeneous layer of which a volume expands more greatly than that of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20100003831 - Semiconductor device manufacturing method and semiconductor device manufacturing apparatus: A predicted film formation rate value is computed based on a film formation rate prediction formula obtained in advance and apparatus parameters obtained during a previously-performed film formation process. A processing time required for an amount of film formed on a wafer to reach a predetermined target film thickness is... Agent: Mcdermott Will & Emery LLP
20100003832 - Vapor phase deposition apparatus, method for depositing thin film and method for manufacturing semiconductor device: A vapor phase deposition apparatus 100 for forming a thin film comprising a chamber 1060, a piping unit 120 for supplying a source material of the thin film into the chamber 1060 in a gaseous condition, a vaporizer 202 for vaporizing the source material in a source material container 112... Agent: Sughrue Mion, PLLC
20100003833 - Method of forming fluorine-containing dielectric film: A method of forming a fluorine-containing dielectric film on a substrate by plasma CVD, includes: introducing as a process gas a fluorinated carbon compound having at least two double bonds in its molecule and an unsaturated hydrocarbon compound into a reaction space wherein a substrate is placed; and applying RF... Agent: Knobbe Martens Olson & Bear LLP
20100003834 - Mram: Disclosed is a method to convert a low resistance cell in a MRAM device to a capacitive cell. The low resistance cell has a plurality of layers on a substrate. At least one layer remote from the substrate is sensitive to oxygen infusion. The method includes removing a cap layer... Agent: Sughrue Mion, PLLC
20100003835 - Low-k precursors based on silicon cryptands, crown ethers and podands: Disclosed herein is the use of a silicon podand, silicon crown ether, or silicon cryptand to form a low-k dielectric film on a substrate.... Agent: Air Liquide Intellectual PropertyPrevious industry: Chemistry: analytical and immunological testing
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