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USPTO Class 438 | Browse by Industry: Previous - Next | All 10/2009 | Recent | 09: Oct | Sept | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 08: Dec | Nov | Oct | Sp | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 07: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 06: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Semiconductor device manufacturing: process inventions 10/09Recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.Listing format for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 10/01/2009 > patent applications in patent subcategories. 20090246890 - Method for manufacturing a tunnel junction magnetoresistive sensor with improved performance and having a cofeb free layer: A method for manufacturing a magnetoresistive sensor that provides increased magnetoresistive performance. The method includes forming a series of sensor layers with at least one layer containing CoFeB, and having a first capping layer thereover. A high temperature annealing is performed to optimize the grains structure of the sensor layers.... Agent: Zilka-kotab, Pc- Hit 20090246891 - Mark forming method and method for manufacturing semiconductor device: A mark forming method includes forming a first mask layer on a semiconductor substrate; forming at least three first patterns having periodicity on the first mask layer; forming a second mask layer on the first mask layer having the first patterns formed thereon; and forming an opening in the second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP 20090246892 - Sensor, method, and design structure for a low-k delamination sensor: The invention generally relates to a design structure of a circuit design, and more particularly to a design structure of a delamination sensor for use with low-k materials. A delamination sensor includes at least one first sensor formed in a layered semiconductor structure and a second sensor formed in the... Agent: Greenblum & Bernstein, P.L.C 20090246894 - Fabrication and test methods and systems: Methods and systems for fabricating and testing semiconductor devices are disclosed. In one embodiment, a method of forming a material includes providing a first workpiece, forming a material on the first workpiece using a first process condition, and measuring a defect state of the material using a test that utilizes... Agent: Slater & Matsil LLP 20090246893 - Semiconductor integrated circuit manufacturing process evaluation method: A method for evaluating a process of manufacturing a semiconductor integrated circuit including a deposition step and a polishing step after the deposition step, the method includes: dividing the semiconductor integrated circuit into a plurality of areas; determining a deposition height after the deposition step for each of the areas;... Agent: Greer, Burns & Crain 20090246895 - Apparatus and methods for combining light emitters: Provided are methods and apparatus for combining light emitters and devices including the same. Embodiments include methods of selecting combinations of multiple light emitters that are grouped into multiple bins. The multiple bins correspond to multiple emitter group regions in a multiple axis color space and multiple luminosity ranges. Such... Agent: Myers Bigel Sibley & Sajovec, P.a. 20090246896 - Method and apparatus for improved printed cathodes for organic electronic devices: Rapid thermal processing of printed electrodes and cathodes for organic electronic devices and light-emitting polymer devices (LEPDs) to prevent detrimental cathode ink/underlying layer interactions is described herein. The ink layer printed cathode can be thinned during fabrication using high mesh count screens, calendered mesh screens, high squeegee pressures, high hardness... Agent: Pillsbury Winthrop Shaw Pittman LLP 20090246897 - Led chip package structure and method for manufacturing the same: An LED chip package structure includes a substrate unit, a light-emitting unit, and a colloid unit. The substrate unit has a substrate body, and a positive electrode trace and a negative electrode trace is respectively formed on the substrate body. The light-emitting unit has a plurality of LED chips arranged... Agent: Rosenberg, Klein & Lee 20090246899 - Method of manufacturing light emitting diode: A method of manufacturing light emitting diode has steps of providing a package base, providing a light emitting structure and bonding the light emitting structure on the package base. The package base has a first metal layer and a second metal layer respectively formed on a top and a bottom... Agent: Posz Law Group, Plc 20090246900 - Shaped articles comprising semiconductor nanocrystals and methods of making and using same: A shaped article comprising a plurality of semiconductor nanocrystals. Devices incorporating shaped articles are also provided. Methods of manufacturing shaped articles by various molding processes are also provided.... Agent: Kenyon & Kenyon LLP 20090246898 - Vertically emitting, optically pumped semiconductor having and external resonator on a separate substrate: A method for fabricating an optically pumped semiconductor apparatus, having the following steps: provision of a connection carrier assembly (50) comprising a plurality of connection carriers (14) which are permanently connected to one another mechanically, arrangement of a surface-emitting semiconductor body (1) on a connection carrier (14) in the connection... Agent: Cohen, Pontani, Lieberman & Pavane LLP 20090246901 - Process of making a microelectronic light-emitting device on semi-conducting nanowire formed on a metallic substrate: A process of making a microelectronic light-emitting device, including: a) growth on a metallic support of multiple wires based on one or more semi-conducting materials designed to emit radiant light, and b) formation of at least one electrical conducting zone of contact on at least one of the wires.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c. 20090246902 - Thiophene derivative and organic electroluminescent element: p 20090246903 - Manufacturing method for semiconductor device: The present invention includes forming an optical guide layer on a substrate, forming a cap layer on the optical guide layer, and forming openings in parts of the optical guide layer and the cap layer to form a diffraction grating from part of the optical guide layer. The substrate is... Agent: Leydig Voit & Mayer, Ltd 20090246904 - Method for manufacturing a photovoltaic module: For manufacturing a photovoltaic module (1) having on a transparent substrate (2) a transparent front electrode layer (3), a semiconductor layer (4) and a back electrode layer (5) as functional layers, the functional layers (3-5) are removed in the edge area (10) of the substrate (2) with a laser emitting... Agent: Flynn Thiel Boutell & Tanis, P.c. 20090246905 - Electro-optic integrated circuits and methods for the production thereof: An electro-optic integrated circuit including an integrated circuit substrate at least one optical signal providing element and at least one discrete reflecting optical element mounted onto the integrated circuit substrate, cooperating with the at least one optical signal providing element and being operative to direct light from the at least... Agent: Perkins Coie LLP 20090246906 - High-throughput printing of semiconductor precursor layer from microflake particles: Methods and devices are provided for high-throughput printing of semiconductor precursor layer from microflake particles. In one embodiment, the method comprises of transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that... Agent: Director Of Ip 20090246907 - Higher selectivity, method for passivating short circuit current paths in semiconductor devices: A method for passivating short circuit defects in a thin film large area photovoltaic device in accordance with an exemplary embodiment is provided. The method employs a passivation agent and a counter electrode disposed in said passivation agent. The method includes controlling an application of current between the substrate of... Agent: Energy Conversion Devices, Inc. 20090246908 - Roll-to-roll processing method and tools for electroless deposition of thin layers: A deposition method and a system are provided to deposit a CdS buffer layer on a surface of a solar cell absorber layer of a flexible workpiece from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited from the deposition solution while the... Agent: Pillsbury Winthrop Shaw Pittman LLP 20090246909 - Semiconductor device and method of manufacturing the same: In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The... Agent: Kratz, Quintos & Hanson, LLP 20090246910 - Semiconductor device manufacturing method: A semiconductor device manufacturing method includes the steps of preparing a semiconductor element having a first electrode, a second electrode, and a third electrode facing the first electrode and second electrode, the first electrode and second electrode being electrically separated by an insulating layer; arranging a first conductive bonding material... Agent: Kanesaka Berner And Partners LLP 20090246911 - Substrate for mounting electronic components and its method of manufacture: A substrate for mounting electronic components includes an insulating layer and a pad formed on a surface of the insulating layer, the pad configured to mount an electronic component to the substrate. A solder bump is formed on the pad and configured to connecting the pad to a bump of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c. 20090246913 - Adhesive composition, adhesive sheet and production method of semiconductor device: s 20090246912 - Method of producing semiconductor packages: Semiconductor chips are fixed to one of two opposite surfaces of a leadframe, and the leadframe is electrically connected to each semiconductor chip with wires. After having applied water-soluble masking ink to the other surface of the leadframe, a sealed structure is molded. Then, when the sealed structure is cut... Agent: Birch Stewart Kolasch & Birch 20090246914 - Semiconductor package and method of manufacturing the same: A package may include a semiconductor chip mounted on a film substrate. A method of manufacturing the same may involve providing a semiconductor chip. The semiconductor chip may include recesses and bumps. A film substrate including a through hole may be provided. The semiconductor chip may be inserted into the... Agent: Harness, Dickey & Pierce, P.L.C 20090246915 - Adhesive composition, adhesive sheet and production method of semiconductor device: p 20090246916 - Chip package with pin stabilization layer: Various methods and apparatus for semiconductor packing are disclosed. In one aspect, a method of manufacturing is provided that includes coupling first ends of plural conductor pins to a first surface of a semiconductor chip package substrate. A layer is formed on the first surface that engages and resists lateral... Agent: Timothy M Honeycutt Attorney At Law 20090246917 - Linked chip attach and underfill: A method for attaching an integrated circuit chip to a package substrate includes placing the integrated circuit onto the package substrate, and performing reflow to attach the integrated circuit to the package substrate. The temperature of the integrated circuit and package assembly is maintained at or above a predetermined temperature... Agent: Cool Patent, P.c. C/o Cpa Global 20090246918 - Method of manufacturing semiconductor device: The present invention provides a method of manufacturing a semiconductor device in which a semiconductor element is mounted on a wiring circuit board and a clearance between the wiring circuit board and the semiconductor element is sealed with a sealing material, the method including: a sealing material arranging step of... Agent: Sughrue-265550 20090246919 - Method for manufacturing pixel structure: A method for manufacturing a pixel structure includes forming a first conductive layer on a substrate and patterning the first conductive layer with use of a first mask as an etching mask to form a gate. A dielectric layer is formed over the substrate to cover the gate. A semiconductor... Agent: J C Patents, Inc. 20090246920 - Methods for normalizing strain in a semiconductor device: The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing... Agent: Brinks Hofer Gilson & Lione 20090246921 - Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the... Agent: Greenblum & Bernstein, P.L.C 20090246922 - Method of forming cmos transistor: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is... Agent: North America Intellectual Property Corporation 20090246923 - Method of forming shielded gate fet with self-aligned features: A method for forming a shielded gate field effect transistor includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A shield electrode is formed in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield... Agent: Townsend And Townsend And Crew, LLP 20090246924 - Method of producing field effect transistor: The laser beam with a wavelength having a higher energy than the band gap energy of the material forming the carrier moving layer is irradiated to activate the impurities contained in the constituent layer of the field effect transistor in the method of producing the field effect transistor. The method... Agent: Kubotera & Associates, Llc 20090246925 - Nitride read only memory device with buried diffusion spacers and method for making the same: A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO... Agent: Stout, Uxa, Buyan & Mullins LLP 20090246927 - Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence: By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.... Agent: Williams, Morgan & Amerson 20090246926 - Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode: After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during... Agent: Williams, Morgan & Amerson 20090246928 - Semiconductor device with bipolar transistor and method of fabricating the same: Disclosed is a semiconductor device with a bipolar transistor and method of fabricating the same. The device may include a collector region in a semiconductor substrate. A base pattern may be disposed on the collector region. A hard mask pattern may be disposed on the base pattern. The hard mask... Agent: Harness, Dickey & Pierce, P.L.C 20090246929 - Membrane suspended mems structures: A method for micro-machining a varactor that is part of a membrane suspended MEMS tunable filter. In one non-limiting embodiment, the method includes providing a main substrate; depositing a membrane on the main substrate; depositing and patterning a plurality of sacrificial photoresist layers at predetermined times during the fabrication of... Agent: Miller Ip Group, Plc Emag Technologies, Inc. 20090246930 - Metal capacitor including lower metal electrode having hemispherical metal grains: Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, a dielectric layer formed on the lower metal electrode containing Ti and... Agent: Marger Johnson & Mccollom, P.c. 20090246931 - Methods for forming roughened surfaces and applications thereof: Methods of forming a roughened metal surface on a substrate are provided, along with structures comprising such roughened surfaces. In preferred embodiments roughened surfaces are formed by selectively depositing metal or metal oxide on a substrate surface to form discrete, three-dimensional islands. Selective deposition may be obtained, for example, by... Agent: Knobbe Martens Olson & Bear LLP 20090246932 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP 20090246934 - Method for manufacturing soi substrate and method for manufacturing semiconductor device: A method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced is provided. An oxide film containing halogen is formed on each of surfaces of a single crystal semiconductor substrate and of a semiconductor substrate provided with a single crystal semiconductor layer... Agent: Eric Robinson 20090246933 - Method of producing a strained layer: A method of producing a strained layer on a substrate includes assembling a layer with a first structure or first means of straining including at least one substrate or one layer capable of being deformed within a plane thereof under the influence of an electric or magnetic field or a... Agent: Brinks Hofer Gilson & Lione 20090246936 - Method for manufacturing soi substrate and method for manufacturing semiconductor device: A method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even if a single crystal semiconductor substrate including crystal defects is used. A first oxide film is formed on a single crystal semiconductor substrate; the first oxide film is removed; a... Agent: Eric Robinson 20090246937 - Method for manufacturing soi substrate and method for manufacturing semiconductor device: It is an object to provide a method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even when a single crystal semiconductor substrate in which crystal defects exist is used. Such an SOI substrate can be manufactured through the steps of... Agent: Eric Robinson 20090246935 - Method for producing soi substrate: Provided is a method for producing an SOI substrate comprising a transparent insulating substrate and a silicon film formed on a first major surface of the insulating substrate wherein a second major surface of the insulating substrate which is opposite to the major surface is roughened, the method suppressing the... Agent: Lerner, David, Littenberg, Krumholz & Mentlik 20090246938 - Semiconductor device and method of fabricating the same: A method of forming a semiconductor device includes forming a first chip region, a second chip region, and a scribe lane region between the first and second chip regions in a wafer, the wafer having a first surface and a second surface facing the first surface, and forming a penetrating... Agent: F. Chau & Associates, Llc 20090246939 - Method for dehydrogenation treatment and method for forming crystalline silicon film: A dehydrogenation treatment method which includes forming a hydrogenated amorphous silicon film above a non-heat-resistant substrate, and eliminating bonded hydrogen from the hydrogenated amorphous silicon film by irradiating an atmospheric thermal plasma discharge to the hydrogenated amorphous silicon film for a time period of 1 to 500 ms. The surface... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c. 20090246942 - Apparatus for depositing silicon-based thin film and method for depositing silicon-based thin film: A silicon-based thin film depositing apparatus, including a plurality of transparent electrodes disposed to face corresponding counter electrodes with a space therebetween. Subsequently, while injecting a raw material gas from raw material gas injection orifices toward the supporting electrodes and also injecting a barrier gas from barrier gas injection orifices... Agent: Burr & Brown 20090246943 - Apparatus for mass-producing silicon-based thin film and method for mass-producing silicon-based thin film: A silicon-based thin film mass-producing apparatus, including transparent electrodes placed to face in parallel to corresponding counter electrodes with a space therebetween, and silicon-based thin films are deposited on the transparent electrodes by feeding a raw material gas for depositing the silicon-based thin films into the chamber and by applying... Agent: Burr & Brown 20090246941 - Deposition apparatus, deposition system and deposition method: A deposition system is provided to avoid cross contamination in each layer formed in a manufacturing process of organic electroluminescent device, etc., and also provided to reduce footprint. Provided is an apparatus 13 for forming a film onto a substrate which includes a first deposition mechanism 35 for forming a... Agent: Pearne & Gordon LLP 20090246944 - Method for heteroepitaxial growth of high-quality n-face gan, inn, and aln and their alloys by metal organic chemical vapor deposition: Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also... Agent: Gates & Cooper LLP Howard Hughes Center 20090246945 - Method for manufacturing nitride semiconductor substrate: A method for manufacturing a nitride semiconductor substrate includes the steps of growing a first nitride semiconductor on a substrate, patterning the first nitride semiconductor to obtain a pattern surrounded by a plane equivalent to the (11-20) plane and having at least two concave portions that are similar in their... Agent: Global Ip Counselors, LLP 20090246940 - System and method for depositing a material on a substrate: A method and apparatus for depositing a film on a substrate includes a plasma source positioned proximate to a distributor configured to provide a semiconductor coating on a substrate.... Agent: Steptoe & Johnson LLP 20090246946 - Method of fabricating a microelectronic structure of a semiconductor on insulator type with different patterns: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary... Agent: Brinks Hofer Gilson & Lione 20090246947 - Method for manufacturing semiconductor device: Disclosed herein is a method of manufacturing a semiconductor device that includes forming a metal catalytic pattern on a semiconductor substrate; etching the semiconductor substrate using the metal catalytic pattern as an etching mask to form a recess; forming an insulating layer over a structure including the recess, the metal... Agent: Marshall, Gerstein & Borun LLP 20090246948 - Method of preparing p-type doped zno or znmgo: s 20090246949 - Methods of manufacturing semiconductor devices: In a semiconductor device and a method of manufacturing a semiconductor device, a lower electrode is formed on a semiconductor substrate. A first zirconium oxide layer is formed on the lower electrode by performing a first deposition process using a first zirconium source and a first oxidizing gas. A zirconium... Agent: Mills & Onello LLP 20090246950 - Laser annealing method for manufacturing semiconductor device: A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes forming an insulation layer on the semiconductor substrate and on the... Agent: Ladas & Parry LLP 20090246951 - Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material: By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree... Agent: Williams, Morgan & Amerson 20090246952 - Method of forming a cobalt metal nitride barrier film: A method is provided for forming a cobalt metal nitride barrier film on a substrate for semiconductor devices. According to one embodiment of the invention, the method includes depositing a plurality of metal nitride layers on the substrate, and depositing a cobalt layer between each of the plurality of metal... Agent: Tokyo Electron U.s. Holdings, Inc. 20090246953 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive... Agent: Cook Alex Ltd 20090246954 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, includes forming a plurality of core portions arranged in a predetermined direction, on a to-be-processed film, forming a stacked sidewall portion in which a first sidewall portion and a second sidewall portion are stacked in that order, on each of side surfaces, of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP 20090246955 - Wafer processing method and wafer processing apparatus: A wafer processing method is provided comprising the steps of: holding a wafer (20) having devices formed on its front surface (21) so that a back surface (22) of the wafer is exposed; grinding the back surface of the wafer to form a brittle fracture layer (Z) on the back... Agent: Christie, Parker & Hale, LLP 20090246956 - Metal polishing composition and chemical mechanical polishing method: The invention provides a metal polishing composition that is used in chemical mechanical polishing in production of a semiconductor device, and includes an oxidizing agent, an abrasive grain, and at least one compound selected from compounds represented by the following formula (I) and the following formula (II). The invention also... Agent: Moss & Burke, Pllc 20090246957 - Polishing liquid and polishing method: A polishing liquid is provided with which a polishing rate relative to a conductive metal wiring typically represented by a copper wiring on a substrate having a barrier layer containing manganese and/or a manganese alloy and an insulating layer on the surface (particularly, copper oxide formed at the boundary) is... Agent: Moss & Burke, Pllc 20090246958 - Method for removing residues from a patterned substrate: The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said... Agent: International Business Machines Corporation Dept. 18g 20090246959 - Two step optical planarizing layer etch: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or... Agent: Ingrassia Fisher & Lorenz, P.c. (amd) 20090246960 - Method of fabricating a semiconductor device: In a method of fabricating a semiconductor device, an additive gas is mixed with an etching gas to reduce a fluorine ratio of the etching gas. The etching gas having a reduced fluorine rate is utilized in the process for etching a nitride layer formed on an oxide layer to... Agent: Townsend And Townsend And Crew, LLP 20090246961 - Method for forming pattern of a semiconductor device: A method for forming a pattern of a semiconductor device includes: forming a first mask film and a second mask film over an underlying layer; partially etching the first and second mask films using a photoresist mask pattern as an etching mask to form a intermediate mask pattern having a... Agent: Marshall, Gerstein & Borun LLP 20090246962 - Substrate processing method: A substrate processing method for use in a substrate processing apparatus having a stocker therein which stores a multiplicity of dummy substrates; a reaction chamber for producing semiconductor products; and a transferring unit for transferring into the reaction chamber a process substrate and the dummy substrate stored in the stocker... Agent: Bacon & Thomas, Pllc 20090246963 - Exposure apparatus applying polarization illuminator and exposure method using the same: An exposure apparatus for transferring patterns on a phase shift mask into a wafer according to the present invention comprises a light source, a polarized light illuminator that selectively passes through a TM mode polarized light of light from the light source to cause it to be incident onto the... Agent: Marshall, Gerstein & Borun LLP 20090246964 - Etching process for phase-change films: The invention is directed to a method for etching a phase change material layer comprising steps of providing a phase change material layer and performing a first etching process on the phase change material layer. The etching process is performed with an etchant comprising a fluoride-based gas with a concentration... Agent: J C Patents, Inc. 20090246965 - Etching method and manufacturing method of semiconductor device: Provided is an etching method capable of increasing a selectivity of a polysilicon film with respect to a silicon oxide film and suppressing the formation of recesses in a silicon base material. A wafer includes a gate oxide film, a polysilicon film and a hard mask film having an opening... Agent: Pearne & Gordon LLP 20090246966 - Method of fine patterning semiconductor device: For integrated circuit fabrication, at least one spacer support structure is formed in a first area over a semiconductor substrate, and a mask material is deposited on exposed surfaces of the spacer support structure and on a second area over the semiconductor substrate. A masking structure is formed on a... Agent: Law Office Of Monica H Choi 20090246967 - Semiconductor surface treatment agent: A semiconductor surface treatment agent containing a fluorine compound, a water-soluble organic solvent and an inorganic acid, with the balance being water and a method for manufacturing a semiconductor device by etching a high dielectric constant insulating material using the subject semiconductor surface treatment agent are provided. According to the... Agent: Antonelli, Terry, Stout & Kraus, LLP 20090246968 - Substrate treating apparatus and substrate treating method: A substrate treating apparatus for performing treatment of substrates with a treating liquid. The apparatus includes a treating tank for storing the treating liquid and performing a predetermined treatment of the substrates; a treating liquid supply unit for supplying the treating liquid to the treating tank; a treating liquid discharge... Agent: Ostrolenk Faber Gerb & Soffen 20090246969 - Method for texturing silicon wafers for producing solar cells: In a method for texturing silicon wafers for producing solar cells, the step of introducing a silicon wafer involves the use of a texturing solution which is at a temperature of at least 80 degrees Celsius and which comprises water admixed with 1 percent by weight to 6 percent by... Agent: Baker & Daniels LLP 20090246970 - Fabrication of semiconductor device oxide at lower temperature using pre-dissociated chlorohydrocarbon: The invention provides a method of fabricating a semiconductor device. In one aspect, the method comprises heating a gas mixture comprising chlorohydrocarbon having a general formula of CxHxClx, wherein x=2, 3, or 4, by passing it through a first chamber packed with surface area expanding members heated to a temperature... Agent: Texas Instruments Incorporated 20090246971 - In-situ hybrid deposition of high dielectric constant films using atomic layer deposition and chemical vapor deposition: An in-situ hybrid film deposition method for forming a high-k dielectric film on a plurality of substrates in a batch processing system. The method includes loading the plurality of substrates into a process chamber of the batch processing system, depositing by atomic layer deposition (ALD) a first portion of a... Agent: Tokyo Electron U.s. Holdings, Inc. 20090246972 - Methods for manufacturing high dielectric constant film: Processes for making a high K (dielectric constant) film using an ultra-high purity hafnium containing organometallic compound are disclosed. Also described are devices incorporating high K films made with high purity hafnium containing organometallic compounds.... Agent: Diehl Servilla Llc 20090246974 - Method of forming a stressed passivation film using a microwave-assisted oxidation process: A method for forming a stressed passivation film. In one embodiment, the method includes depositing a silicon nitride film over an integrated circuit structure on a substrate and embedding oxygen into a surface of the silicon nitride film by exposing the silicon nitride film to a process gas containing an... Agent: Tokyo Electron U.s. Holdings, Inc. 20090246973 - Method of forming a stressed passivation film using a non-ionizing electromagnetic radiation-assisted oxidation process: A method for forming a stressed passivation film. In one embodiment, the method includes depositing a silicon nitride film over an integrated circuit structure on a substrate and embedding oxygen into a surface of the silicon nitride film by exposing the silicon nitride film to a process gas containing oxygen... Agent: Tokyo Electron U.s. Holdings, Inc. 20090246975 - Multiple technology node mask: A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main... 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