|Semiconductor device manufacturing: process patents - Monitor Patents|
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Semiconductor device manufacturing: process July category listing 07/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 07/30/2009 > patent applications in patent subcategories. category listing
20090191651 - Positioning apparatus, exposure apparatus, and method of manufacturing device: A positioning apparatus comprises a detector which detects the mark and outputs a mark signal and a controller. The controller includes a calculating unit which calculates position data of the mark based on the mark signal, a processing unit which calculates a parameter representing a displacement of the object, based... Agent: Locke Lord Bissell & Liddell LLP Attn:IPDocketing
20090191654 - Method of manufacturing color filter substrate and method of manufacturing thin film transistor substrate: A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent... Agent: F. Chau & Associates, LLC
20090191652 - Pixel structure and method for manufacturing the same: A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer,... Agent: Bacon & Thomas, PLLC
20090191653 - Transflective liquid crystal display device and method of fabricating the same: An array substrate for a transflective liquid crystal display device includes: a substrate; a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area;... Agent: Holland & Knight LLP
20090191655 - Method of etching amorphous silicon layer and method of manufacturing liquid crystal display using the same: A method of etching an amorphous silicon layer includes providing a substrate with an amorphous silicon layer formed thereon into an atmospheric pressure plasma etching device, providing a plasma generation gas and etching gas to a plasma generator of the atmospheric pressure plasma etching device and generating an atmospheric pressure... Agent: F. Chau & Associates, LLC
20090191657 - All-silicon raman amplifiers and lasers based on micro ring resonators: Methods of manufacturing a lasing device are provided by some embodiments, the methods including: creating a silicon micro ring with a predetermined radius and a predetermined first cross-sectional dimension; creating a silicon waveguide with a predetermined second cross-sectional dimension, the silicon waveguide spaced from the silicon micro ring by a... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090191658 - Semiconductor light emitting device with lateral current injection in the light emitting region: A semiconductor light emitting device includes an active region, an n-type region, and a p-type region comprising a portion that extends into the active region. The active region may include multiple quantum wells separated by barrier layers, and the p-type extension penetrates at least one of the quantum well layers.... Agent: Philips Intellectual Property & Standards
20090191659 - Single-crystal nitride-based semiconductor substrate and method of manufacturing high-quality nitride-based light emitting device by using the same: A nitride-based light emitting device is manufactured by using a single-crystal nitride-based semiconductor substrate. A seed material layer is deposited on a first substrate where organic residues including a natural oxide layer are removed from an upper surface of the first substrate. A multifunctional substrate is grown from the seed... Agent: Cantor Colburn, LLP
20090191660 - Method for manufacturing a sensor device: A motion sensor in the form of an angular rate sensor and a method of making a sensor are provided and includes a support substrate and a silicon sensing ring supported by the substrate and having a flexive resonance. Drive electrodes apply electrostatic force on the ring to cause the... Agent: Delphi Technologies, Inc.
20090191661 - Placing a mems part on an application platform using a guide mask: A method for fabricating a micro-electro-mechanical system (MEMS) device. The method comprises placing a guiding mask on an application platform, the guiding mask including an opening that defines the position of a MEMS part to be placed on the application platform. The method further comprises placing the MEMS part into... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090191662 - Image sensor applied with device isolation technique for reducing dark signals and fabrication method thereof: The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090191663 - Method for producing a photovoltaic module: For producing a photovoltaic module (1), the front electrode layer (3), the semi-conductor layer (4) and the back electrode layer (5) are patterned by separating lines (6, 7, 8) to form series-connected cells (C1, C2, . . . Cn, Cn+1) with a laser (14) emitting infrared radiation. During patterning of... Agent: Flynn Thiel Boutell & Tanis, P.C.
20090191664 - Apparatus for improved power distribution in wirebond semiconductor packages: A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting... Agent: Texas Instruments Incorporated
20090191665 - Electronic device and method of manufacturing same: This application relates to a method of manufacturing an electronic device comprising placing a first chip on a carrier; applying an insulating layer over the first chip and the carrier; applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness;... Agent: Infineon Technologies Ag Patent Department
20090191667 - semiconductor device and a manufacturing method of the same: A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the... Agent: Mattingly & Malur, P.C.
20090191666 - Method of manufacturing stacked-type semiconductor device: A method of manufacturing a stacked-type semiconductor device, including the steps of: forming dividing grooves, having a depth corresponding to a finished thickness for a plurality of first chips formed on the face side of a wafer, on the face side of the wafer along planned dividing lines; stacking existing... Agent: Greer, Burns & Crain
20090191668 - Method for manufacturing ic tag inlet: An IC tag inlet (100) is configured by: an upper side antenna (102) and a lower side antenna (103) sandwiching a semiconductor chip (101) that includes an upper electrode (132) and a lower electrode (133) from both upper and lower directions; and a support resin (104) covering the semiconductor chip... Agent: Miles & Stockbridge PC
20090191669 - Method of encapsulating an electronic component: A procedure of packaging an electronic component is provided, comprising the following steps: step A for mount at which a conductor and a chip are temporarily mounted on a carrier removable, and next step B for encapsulation at which the conductor and the chip are encapsulated with colloid and mounted... Agent: Sinorica, LLC
20090191671 - Semiconductor substrate, semiconductor device, and manufacturing methods for them: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop... Agent: Nixon & Vanderhye, PC
20090191670 - Silicon thin film transistors, systems, and methods of making same: Systems and methods of fabricating silicon-based thin film transistors (TFTs) on flexible substrates. The systems and methods incorporate and combine deposition processes such as chemical vapor deposition and plasma-enhance vapor deposition, printing, coating, and other deposition processes, with laser annealing, etching techniques, and laser doping, all performed at low temperatures... Agent: Patterson, Thuente, Skaar & Christensen, P.A.
20090191672 - Method for production of thin-film semiconductor device: Disclosed herein is a method for production of a thin-film semiconductor device which includes, a first step to form a gate electrode on a substrate, a second step to form a gate insulating film of silicon oxynitride on the substrate in such a way as to cover the gate electrode,... Agent: Rader Fishman & Grauer PLLC
20090191673 - Method of manufacturing thin film transistor: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film... Agent: Lee & Morse, P.C.
20090191674 - Aigan/gan high electron mobility transistor devices: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where... Agent: Knobbe Martens Olson & Bear LLP
20090191675 - Method for forming cmos transistors having fusi gate electrodes and targeted work functions: A method for making CMOS transistors that includes forming a NMOS transistor and a PMOS transistor having an undoped polysilicon gate electrode and a hardmask. The method also includes forming a layer of insulating material and then removing the hardmasks and a portion of the layer of insulating material. A... Agent: Texas Instruments Incorporated
20090191676 - Flash memory having a high-permittivity tunnel dielectric: A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert
20090191677 - Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines: A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to... Agent: Knobbe Martens Olson & Bear LLP
20090191678 - Method of forming a shielded gate field effect transistor: A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa... Agent: Townsend And Townsend And Crew, LLP
20090191679 - Local stress engineering for cmos devices: A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A... Agent: Scully, Scott, Murphy & Presser, P.C.
20090191680 - Dual-gate memory device with channel crystallization for multiple levels per cell (mlc): A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an... Agent: Haynes And Boone, LLPIPSection
20090191681 - Nor-type flash memory device with twin bit cell structure and method of fabricating the same: A NOR-type flash memory device comprises a plurality twin-bit memory cells arranged so that pairs of adjacent memory cells share a source/drain region and groups of four adjacent memory cells are electrically connected to each other by a single bitline contact.... Agent: Volentine & Whitt PLLC
20090191682 - Fabrication method of semiconductor device: A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger... Agent: Mcdermott Will & Emery LLP
20090191683 - Method of forming transistor having channel region at sidewall of channel portion hole: According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of... Agent: Marger Johnson & Mccollom, P.C.
20090191684 - Novel approach to reduce the contact resistance: A method for fabricating a semiconductor device is disclosed. First, a semiconductor substrate having a doped region(s) is provided. Thereafter, a pre-amorphous implantation process and neutral (or non-neutral) species implantation process is performed over the doped region(s) of the semiconductor substrate. Subsequently, a silicide is formed in the doped region(s).... Agent: Haynes And Boone, LLPIPSection
20090191685 - Method for forming capacitor in dynamic random access memory: A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor;... Agent: Morris Manning Martin LLP
20090191686 - Method for preparing doped polysilicon conductor and method for preparing trench capacitor structure using the same: A method for preparing a doped polysilicon conductor according to this aspect of the present invention comprises the steps of (a) placing a substrate in a reaction chamber, (b) performing a deposition process to form a polysilicon layer on the substrate, (c) performing a grain growth process to form a... Agent: Wpat, PC Intellectual Property Attorneys
20090191687 - Method of filling a trench and method of forming an isolating layer structure using the same: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of... Agent: Volentine & Whitt PLLC
20090191688 - Shallow trench isolation process using two liners: A method for making STI structure includes etching a STI trench through a nitride layer, through an oxide layer, and into a silicon layer. The method also includes forming a sacrificial liner, pulling-back the nitride layer, and removing a remaining portion of the sacrificial liner. Furthermore, the method includes forming... Agent: Texas Instruments Incorporated
20090191689 - Method of arranging dies in a wafer for easy inkless partial wafer process: In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle pattern (602) that is configured by arranging the dies in an array having m rows and n columns, where the m rows start in... Agent: Texas Instruments Incorporated
20090191690 - Increasing die strength by etching during or after dicing: A semiconductor wafer having an active layer is mounted on a carrier with the active layer away from the carrier and at least partially diced on the carrier from a major surface of the semiconductor wafer. The at least partially diced semiconductor wafer is etched on the carrier from the... Agent: Seyfarth Shaw LLP
20090191691 - Method for singulating semiconductor devices: Disclosed is a method for singulating semiconductor devices. The substrate has a plurality of scribe lines between the substrate units. A protecting film is provided having a patterned adhesive layer formed thereon corresponding to the scribe lines. The protecting film is attached and aligned to the substrate in a manner... Agent: Joe Mckinney Muncy
20090191692 - Wafer processing method: A method of processing a wafer having a plurality of devices which are composed of a laminate consisting of an insulating film and a functional film on the front surface of a substrate, along streets for sectioning the plurality of devices, the method comprising a first blocking groove forming step... Agent: Smith, Gambrell & Russell
20090191693 - Wafer processing method: A method of processing a wafer having a plurality of devices which are composed of a laminate consisting of an insulating film and a functional film laminated on the front surface of a substrate, along streets for sectioning the plurality of devices, comprising a first trip blocking groove forming step... Agent: Smith, Gambrell & Russell
20090191694 - Manufacturing method of semiconductor substrate: A surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region, an insulating layer is formed over the surface of the single crystal semiconductor substrate, and a surface of a substrate having an insulating surface is made to be in contact with a surface... Agent: Eric Robinson
20090191695 - Method of manufacturing nitride semiconductor substrate: A method of manufacturing a nitride semiconductor substrate according to example embodiments may include forming a buffer layer on a (100) plane of a silicon (Si) substrate. The buffer layer may have a hexagonal crystal system and a (1010) plane. A nitride semiconductor layer may be epitaxially grown on the... Agent: Harness, Dickey & Pierce, P.L.C
20090191696 - Method for increasing the penetration depth of material infusion in a substrate using a gas cluster ion beam: A method for infusing material below the surface of a substrate is described. The method comprises modifying a surface condition of a surface on a substrate to produce a modified surface layer, and thereafter, infusing material into the modified surface in the substrate by exposing the substrate to a gas... Agent: Wood, Herron & Evans, LLP (tokyo Electron)
20090191697 - Method for manufacturing a nonvolatile memory device: In a method for manufacturing a nonvolatile memory device, an etch mask layer formed on a dielectric layer to define contact holes in the dielectric layer is slope-etched to form an etch mask pattern having an opening wider at the upper end thereof than the lower end thereof. Thus, the... Agent: Townsend And Townsend And Crew, LLP
20090191698 - Tft array panel and fabricating method thereof:
20090191699 - Methods for forming silicide conductors using substrate masking: A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating... Agent: Myers Bigel Sibley & Sajovec
20090191700 - Semiconductor device with integrated flash memory and peripheral circuit and its manufacture method: A non-volatile semiconductor memory device includes: a nonvolatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090191701 - Microelectronic devices and methods for forming interconnects in microelectronic devices: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled... Agent: Perkins Coie LLP Patent-sea
20090191702 - Semiconductor device and manufacturing method thereof: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More... Agent: Fujitsu Patent Center C/o Cpa Global
20090191703 - Process with saturation at low etch amount for high contact bottom cleaning efficiency for chemical dry clean process: A method for removing oxides from the bottom surface of a contact hole is provided. The method provides efficient cleaning of the bottom surface without distortion of the contact hole upper and sidewall surfaces.... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090191704 - Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing... Agent: Fish & Richardson P.C.
20090191706 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device, including forming a dielectric film above a substrate; forming a metal containing film above the dielectric film; forming at least one carbon containing film of a silicon carbon containing film containing silicon and carbon and a nitrogen carbon containing film containing nitrogen and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090191705 - Semiconductor contact barrier: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions... Agent: Slater & Matsil, L.L.P.
20090191707 - Method of manufacturing a semiconductor device: To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate 1, by carrying out a first thermal treatment at a... Agent: Miles & Stockbridge PC
20090191708 - Method for forming a through silicon via layout: A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the... Agent: Freescale Semiconductor, Inc. Law Department
20090191709 - Method for manufacturing a semiconductor device: A polymer for immersion lithography comprising a repeating unit represented by Formula 1 and a photoresist composition containing the same. A photoresist film formed by the photoresist composition of the invention is highly resistant to dissolution, a photoacid generator in an aqueous solution for immersion lithography, thereby preventing contamination of... Agent: Marshall, Gerstein & Borun LLP
20090191710 - Cmp method for improved oxide removal rate: The invention provides a method for the chemical-mechanical polishing of a substrate with a chemical-mechanical polishing composition that comprises an abrasive, a halide salt, water and a polishing pad.... Agent: Steven Weseman Associate General Counsel, I.p.
20090191711 - Hardmask open process with enhanced cd space shrink and reduction: Methods for forming an ultra thin structure. The method includes a polymer deposition and etching process. In one embodiment, the methods may be utilized to form fabricate submicron structure having a critical dimension less than 30 nm and beyond. The method further includes a multiple etching processes. The processes may... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090191712 - Manufacturing method of semiconductor device: In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090191713 - Method of forming fine pattern using block copolymer: Provided is a method of forming a fine pattern using a block copolymer. The method comprises forming a coating layer including a block copolymer having a plurality of repeating units on a substrate. A mold is provided having a first pattern comprising a plurality of ridges and valleys. The first... Agent: Marger Johnson & Mccollom, P.C.
20090191714 - Method of removing oxides: The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching... Agent: North America Intellectual Property Corporation
20090191715 - Method for etching interlayer dielectric film: In the fine processing of holes and/or trenches by dry-etching an interlayer dielectric film covered with a resist mask formed by ArF-photolithography within a plasma atmosphere, the etching gas used comprises a halogen atom-containing gas (the halogen atom being selected from F, I and/or Br) or a fluorinated carbon atom-containing... Agent: Arent Fox LLP
20090191716 - Polysilicon layer removing method and storage medium: A polysilicon layer removing method capable of substantially removing etching residue, while improving the shape of an etching boundary is disclosed. The method for removing the polysilicon layer from a beveled portion of a wafer W through wet etching includes hydrophilizing the polysilicon layer, without removing the polysilicon layer from... Agent: Cantor Colburn, LLP
20090191717 - Atomic layer deposition apparatus: An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality... Agent: F. Chau & Associates, LLC
20090191718 - Substrate processing apparatus, method of manufacturing semiconductor device, and reaction vessel: A method of manufacturing a semiconductor device includes the steps of: conveying a plurality of substrates disposed in a direction perpendicular to a substrate processing surface into a processing chamber provided inside of a reaction tube, with an outer periphery surrounded by a heating device; and processing the substrates by... Agent: Oliff & Berridge, PLC
20090191719 - Methods for fabricating compound material wafers: Methods are disclosed for preparing a reconditioned donor substrate by providing a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and depositing an additional layer onto the opposite surface of the remainder substrate to... Agent: Winston & Strawn LLP Patent Department
20090191720 - Coating process and equipment for reduced resist consumption: A coating system and method of coating semiconductor wafers is disclosed that is able to maintain a wet condition on the outer portion of the semiconductor wafer to provide ease of spreading for a photo-resist or anti-reflective coating (ARC) that is being dispensed. The system can include a plurality of... Agent: Banner & Witcoff, Ltd.
20090191721 - Sequential tantalum-nitride deposition: An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a multi-step process within a vacuum chamber which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang.... Agent: Tokyo Electron U.s. Holdings, Inc.
20090191722 - Film formation method and apparatus for semiconductor process: A film formation method is used for forming a silicon nitride film on a target substrate by repeating a plasma cycle and a non-plasma cycle a plurality of times, in a process field configured to be selectively supplied with a first process gas containing a silane family gas and a... Agent: Smith, Gambrell & Russell
20090191723 - Method of performing lithographic processes: Method of performing lithographic processes on a wafer in a lithographic apparatus having multiple stages. First, a lithographic apparatus including a first wafer chuck and a second wafer chuck is provided. Subsequently, a cassette including a plurality of wafers is provided in the lithographic apparatus, and each wafer has a... Agent: North America Intellectual Property Corporation
20090191724 - Substrate heating apparatus, heating method, and semiconductor device manufacturing method: A substrate heating apparatus having a conductive heater which heats a substrate includes a filament arranged in the conductive heater and connected to a filament power supply to generate thermoelectrons, and an acceleration power supply which accelerates the thermoelectrons between the filament and conductive heater. The filament has inner peripheral... Agent: Fitzpatrick Cella Harper & Scinto07/23/2009 > patent applications in patent subcategories. category listing
20090186424 - Pattern generation method, computer-readable recording medium, and semiconductor device manufacturing method: A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090186425 - Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus: A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090186426 - Plasma doping method and apparatus employed in the same: In the plasma doping method by which plasma is generated within a vacuum chamber, and impurity ions contained in the plasma are caused to collide with the surface of the sample so as to quality-change the surface of the sample into an amorphous state thereof, a plasma irradiation time is... Agent: Mcdermott Will & Emery LLP
20090186427 - Characterizing films using optical filter pseudo substrate: A system and method of characterizing a parameter of an ultra thin film, such as a gate oxide layer. A system is disclosed that includes a structure having a pseudo substrate positioned below an ultra thin film, wherein the pseudo substrate includes an optical mirror for enhancing an optical response;... Agent: Hoffman Warnick LLC
20090186428 - Method for constructing module for optical critical dimension (ocd) and measureing method of module for optical critical dimension using the module: An optical critical dimension measuring method, applicable in measuring a pattern, that includes a plurality of polysilicon layers, of a device, is provided. The method includes obtaining a real curve corresponding to the to-be-measured device. Then, determining whether an ion implantation process has been performed on the polysilicon layers, a... Agent: J C Patents, Inc.
20090186429 - Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device: A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090186430 - Test patterns for detecting misalignment of through-wafer vias: A semiconductor chip including a test pattern is provided. The semiconductor chip includes a semiconductor substrate; a through-wafer via in the semiconductor substrate; and a plurality of conductive patterns over the semiconductor substrate and adjacent to each other. The bottom surfaces of the plurality of conductive patterns and a top... Agent: Steven H. Slater Slater & Matsil, L.L.P.
20090186431 - Light-emitting device and its manufacturing method: In a light-emitting device and its manufacturing method, mounting by batch process with surface-mount technology, high light extraction efficiency, and low manufacturing cost are realized. The light-emitting device comprises semiconductor layers of p-type and n-type nitride semiconductor, semiconductor-surface-electrodes to apply currents into each of the semiconductor layers, an insulating layer... Agent: Greenblum & Bernstein, P.L.C
20090186432 - Multi-chip device and method for manufacturing the same: A multi-chip device includes LED sensors for sensing light separated by a predetermined interval in a wafer, LEDs for emitting light formed over the wafer respectively corresponding to the LED sensors, a driving circuit formed between the LEDs over the wafer, an insulating film over the wafer, and trenches in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090186434 - Led chip package structre with a plurality of thick guiding and a method for manufactruing the same: An LED chip package structure with thick guiding pin includes a plurality of conductive pins separated from each other, an insulative casing, a plurality of LED chips, and a packaging colloid. The insulative casing covers a bottom side of each conductive pin to form an injection concave groove for exposing... Agent: Rosenberg, Klein & Lee
20090186433 - Method of making phosphor containing glass plate, method of making light emitting device: A method of making a light emitting device includes mixing a glass powder with a phosphor powder including at least one of a sulfide phosphor, an aluminate phosphor and a silicate phosphor to produce a mixed powder in which the phosphor powder is dispersed in the glass powder, heating and... Agent: Mcginn Intellectual Property Law Group, PLLC
20090186436 - Array substrate, method of manufacturing the same and liquid crystal display apparatus having the same: An array substrate includes a plate, a switching element, an insulating layer and a pixel electrode. The plate includes a pixel region, and the switching element is disposed on the plate. The insulating layer is disposed on the plate to include an opening for a multi-domain disposed in the pixel... Agent: Haynes And Boone, LLPIPSection
20090186435 - Surface roughening method for light emitting diode substrate: The present invention discloses a surface roughening method for an LED substrate, which uses a grinding technology and an abrasive paper of from No. 300 to No. 6000 to grind the surface of a substrate to form a plurality of irregular concave zones and convex zones on the surface of... Agent: Joe Mckinney Muncy
20090186437 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode.... Agent: Nixon Peabody, LLP
20090186438 - Array substrate for liquid crystal display device and method of manufacturing the same: An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line and including a gate electrode, an active... Agent: Brinks Hofer Gilson & Lione
20090186439 - Thin film forming apparatus: There is provided a thin film forming apparatus for precisely forming a film of an organic EL material made of a polymer without a positional deviation and at a high throughput. A pixel portion is divided into a plurality of pixel lines by banks, and a head portion of the... Agent: Cook Alex Ltd
20090186440 - Methods, apparatus, and rollers for cross-web forming of optoelectronic devices: Apparatus and methods for forming optoelectronic devices such as an array of light emitting diodes or photovoltaic cells in one embodiment a roll-to-roll process in which a uniquely configured roller having a raised spiral coating surface is aligned with a plurality of first electrodes disposed on an angle on a... Agent: General Electric Company Global Research
20090186442 - Method for producing a photovoltaic module: For producing a photovoltaic module (1), the front electrode layer (3), the semi-conductor layer (4) and the back electrode layer (5) are patterned by separating lines (6, 7, 8) to form series-connected cells (C1, C2, . . . Cn, Cn+1). The patterning of the front electrode layer (3) and of... Agent: Flynn Thiel Boutell & Tanis, P.C.
20090186441 - Ultrashallow photodiode using indium: The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to decrease transient enhanced diffusion effects, minimize fixed pattern noise and fill factor loss.... Agent: Dickstein Shapiro LLP
20090186443 - Method to enhance performance of complex metal oxide programmable memory: A method of incorporating oxygen vacancies near an electrode/oxide interface region of a complex metal oxide programmable memory cell which includes forming a first electrode of a metallic material which remains metallic upon oxidation, forming a second electrode facing the first electrode, forming an oxide layer in between the first... Agent: Cantor Colburn LLP-ibm Yorktown
20090186445 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode.... Agent: Nixon Peabody, LLP
20090186444 - Transistor, method of manufacturing transistor, and method of operating transistor: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially... Agent: Harness, Dickey & Pierce, P.L.C
20090186447 - Process for sealing and connecting parts of electromechanical, fluid and optical microsystems and device obtained thereby: A process for connecting two bodies forming parts of an electromechanical, fluid and optical microsystem, wherein a welding region is formed on a first body; an electrically conductive region and a spacing region are formed on a second body; the spacing region extends near the electrically conductive region and has... Agent: Seed Intellectual Property Law Group PLLC
20090186446 - Semiconductor device packages and methods of fabricating the same: Provided are semiconductor device packages and methods for fabricating the same. In some embodiments, the method includes providing a semiconductor chip on a substrate with through electrodes formed in the substrate, and providing a capping layer on the substrate to receive the semiconductor chip in a recess formed in the... Agent: Mills & Onello LLP
20090186449 - Method for fabricating package structures for optoelectronic devices: A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090186448 - Method for providing an led chip with a peripheral protective film before cutting the same from a wafer: A method is disclosed to divide a wafer into chips. In the method, a substrate is provided. The substrate is made of an isolating material. An epitaxial laminate is provided on the substrate. At least one slit is made through the epitaxial laminate completely to form at least two chips... Agent: Charles E. Baxley, Esquire
20090186450 - Ic packaging process by photo-curing adhesive: A IC packaging process includes the steps of mounting at least one retaining member on a top side of a substrate, the retaining member defining a receiving space, a chip being mounted to the substrate and located in the receiving space; forming a photo-curing adhesive layer in the receiving space,... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw
20090186451 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device includes providing an adhesive on a supporting board, the supporting board being where a semiconductor element is to be mounted; providing a member configured to block flow of the adhesive on a first main surface of the semiconductor element, the semiconductor element having... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090186452 - Dual metal stud bumping for flip chip applications: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive... Agent: Townsend And Townsend And Crew, LLP
20090186453 - Power semiconductor devices having integrated inductor: An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a ferromagnetic body (111) and a wire (104) wrapped around the body to form at least a portion of a loop; the wire ends (104a) are... Agent: Texas Instruments Incorporated
20090186454 - Method for manufacturing electronic device: A method for manufacturing an electronic device with a plurality of lead frames for individually supporting an electronic component 6 surrounded by a casing 8, which method includes the steps of charging a resin 10 into each casing 8 on a substrate 5 on which the plurality of supporting lead... Agent: Posz Law Group, PLC
20090186455 - Disposable metallic or semiconductor gate spacer: A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate... Agent: Scully, Scott, Murphy & Presser, P.C.
20090186456 - Method of manufacturing semiconductor device using salicide process: A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a... Agent: Marshall, Gerstein & Borun LLP
20090186457 - Anneal sequence integration for cmos devices: The present invention relates to semiconductor devices, and more particularly to a method for forming a CMOS semiconductor device, the method including a first integration anneal sequence for each NFET and a second integration anneal sequence for each PFET of the semiconductor device. The method includes providing a structure having... Agent: Scully, Scott, Murphy & Presser, P.C.
20090186458 - Method for manufacturing a cmos device having dual metal gate: A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer... Agent: North America Intellectual Property Corporation
20090186459 - Manufacturing method of non-volatile memory: A method of manufacturing a non-volatile memory is provided. A substrate is provided and then a number of stacked gate structures are formed on the substrate. Each of the stacked gate structures includes a tunneling dielectric layer, a floating gate, a first inter-gate dielectric layer, a control gate and a... Agent: Jianq Chyun Intellectual Property Office
20090186460 - Method for manufacturing an eeprom cell: A method for manufacturing an EEPROM cell including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with a stack of first and second layers, forming at least one first opening in the second layer, forming, in the first layer, a second opening continuing... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20090186461 - Narrow width metal oxide semiconductor transistor: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20090186462 - Semiconductor device and fabrication method: A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting... Agent: Infineon Technologies Ag Patent Department
20090186463 - Method for manufacturing soi structure in desired region of a semiconductor device: Manufacturing a semiconductor device includes defining bulb-type trenches having spherical portions in a silicon substrate. Oxide layers are formed in surfaces of spherical portions of the bulb-type trenches by conducting an oxidation process for the silicon substrate having the bulb-type trenches defined therein. An insulation layer is formed on the... Agent: Ladas & Parry LLP
20090186464 - Method for producing bonded wafer: In the method for producing a bonded wafer by bonding a wafer for active layer to a wafer for support layer and then thinning the wafer for active layer, when oxygen ions are implanted into the wafer for active layer, the implantation step is divided into two stages conducted under... Agent: Sughrue Mion, PLLC
20090186465 - Wafer dividing method: A wafer dividing method for dividing a wafer into individual devices, the front side of the wafer being formed with a plurality of crossing streets for partitioning a plurality of areas where the devices are respectively formed. The wafer dividing method includes the steps of coating the front side of... Agent: Greer, Burns & Crain
20090186466 - Self-masking defect removing method: A method for removing defects from a semiconductor surface is disclosed. The surface of the semiconductor is first coated with a protective layer, which is later thinned to selectively reveal portions of the protruding defects. The defects are then removed by etching. Finally, also the protective layer is removed. According... Agent: Ladas & Parry
20090186467 - Substrate processing apparatus and producing method of semiconductor device: A substrate treatment apparatus includes a reaction tube and a heater heating a silicon wafer. Trimethyl aluminum (TMA) and ozone (O3) are alternately fed into the reaction tubeto generate Al2O3 film on the surface of the wafer. The apparatus also includes supply tubes and for flowing the ozone and TMA... Agent: Birch Stewart Kolasch & Birch
20090186468 - Laser annealing method: In crystallizing an amorphous silicon film by illuminating it with linear pulse laser beams having a normal-distribution type beam profile or a similar beam profile, the linear pulse laser beams are applied in an overlapped manner. There can be obtained effects similar to those as obtained by a method in... Agent: Fish & Richardson P.C.
20090186469 - Apparatus and method for doping: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a... Agent: Fish & Richardson P.C.
20090186470 - Method for manufacturing silicon carbide semiconductor element: A method of producing a silicon carbide semiconductor device, including: step (A) of forming an impurity-doped region by implanting impurity ions 3 into at least a portion of a silicon carbide layer 2 formed on a first principal face of a silicon carbide substrate 1 having first and second principal... Agent: Mark D. Saralino (pan) Renner, Otto, Boisselle & Sklar, LLP
20090186471 - Method of fabricating semiconductor device for reducing thermal burden on impurity regions of peripheral circuit region: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate... Agent: Mills & Onello LLP
20090186472 - Method for manufacturing semiconductor device: According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate in the first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090186473 - Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry: A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally outward of the circuit component. Insulative material is deposited above the first metal routing level over the conductive... Agent: Wells St. John P.s.
20090186474 - Nonvolatile semiconductor storage device and manufacturing method therefor: A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090186475 - Method of manufacturing a mos transistor: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap... Agent: North America Intellectual Property Corporation
20090186477 - Method of forming metal wiring of nonvolatile memory device: A method of forming metal wirings of a nonvolatile memory device include forming a first insulating layer over a semiconductor substrate including a first junction area and a second junction area, forming first and second contact holes through which the first and second junction areas are respectively exposed in the... Agent: Lowe Hauptman Ham & Berner, LLP
20090186476 - Structure and method for improved sram interconnect: A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a... Agent: International Business Machines Corporation Dept. 18g
20090186478 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes the steps of forming a first insulation layer on a substrate; forming a damascene pattern in the first insulation layer; conducting a first process for forming metal lines in the damascene pattern; conducting a second process for forming a second insulation layer,... Agent: Marshall, Gerstein & Borun LLP
20090186480 - Optical article: An optical article and method of making the same are provided. The optical article has optical multi-aperture operation. The optical article has one or more electrically conductive and selectively passivated patterns.... Agent: John J. Piskorski Rohm And Haas Electronic Materials LLC
20090186479 - Semiconductor processing system including vaporizer and method for using same: A semiconductor processing system including a semiconductor processing apparatus and a gas supply apparatus for supplying a process gas into the semiconductor processing apparatus includes a control section configured to control an operation of a pressure adjusting mechanism for adjusting the pressure inside a vaporizing chamber. The control section is... Agent: Smith, Gambrell & Russell
20090186481 - Method for integrating selective low-temperature ruthenium deposition into copper metallization of a semiconductor device: A method for integrating low-temperature selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. The method includes providing a patterned substrate containing a recessed feature in a dielectric layer, where the recessed feature is at least substantially filled with planarized... Agent: Tokyo Electron U.s. Holdings, Inc.
20090186482 - Method of forming capping structures on one or more material layer surfaces: Methods of forming capping structures on one or more different material surfaces are provided. One embodiment includes disposing a semiconductor structure in a reduced pressure chamber, forming a capping GCIB within the reduced pressure chamber, and directing the capping GCIB onto at least one of the one or more different... Agent: Wood, Herron & Evans, LLP (tokyo Electron)
20090186483 - Etching amount calculating method, storage medium, and etching amount calculating apparatus: An etching amount calculating method that can stably and accurately calculate the amount of etching even if a disturbance is added. Superposed interference light resulting from superposition of interference light of reflected light from a mask film and reflected light from the bottom of a concave portion on other interference... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090186484 - Pattern formation method: After forming a resist film made from a chemically amplified resist material pattern exposure is carried out by selectively irradiating the resist film with exposing light while supplying, onto the resist film, water that includes triphenylsulfonium nonaflate, that is, an acid generator, and is circulated and temporarily stored in a... Agent: Mcdermott Will & Emery LLP
20090186486 - Method of forming damascene patterns of semiconductor devices: A method of forming damascene patterns of semiconductor devices comprise forming a first insulating layer and contact plugs, formed in the first insulating layer, over a semiconductor substrate, forming an etch barrier layer and a second insulating layer over the first insulating layer, forming damascene patterns in the second insulating... Agent: Lowe Hauptman Ham & Berner, LLP
20090186485 - Sub-lithographic printing method: A method to form sub-lithographic trench structures in a substrate and an integrated circuit comprising sub-lithographic trench structures in a substrate. The method includes forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which... Agent: Law Office Of Ido Tuchman (yor)
20090186487 - Edge ring assembly with dielectric spacer ring: An edge ring assembly surrounds a substrate support surface in a plasma etching chamber. The edge ring assembly comprises an edge ring and a dielectric spacer ring. The dielectric spacer ring, which surrounds the substrate support surface and which is surrounded by the edge ring in the radial direction, is... Agent: Buchanan, Ingersoll & Rooney PC
20090186488 - Single wafer etching apparatus: A single wafer etching apparatus is an apparatus that supplies etching liquid to an upper face of a thin discoid wafer obtained by slicing a semiconductor ingot while rotating the wafer to etch the upper face and an edge face of the wafer. The apparatus includes: a first nozzle for... Agent: Greenblum & Bernstein, P.L.C
20090186489 - Thermal treatment apparatus, method for manufacturing semiconductor device, and method for manufacturing substrate: A substrate support 30 is formed from a main body portion 56 and a supporting portion 58. In the main body portion 56, a plurality of placing portions 66 extend parallel, and supporting portions 58 are provided on the placing portions 66. A substrate 68 is placed on the supporting... Agent: Oliff & Berridge, PLC
20090186490 - Organic semiconductor device, field-effect transistor, and their manufacturing methods: An organic semiconductor device is provided which includes an organic semiconductor layer and an insulating layer. The insulating layer is made of a cured material formed from a composition containing a resin and a crosslinking agent. The resin contains an organic resin having a hydroxyl group. The crosslinking agent contains... Agent: Fitzpatrick Cella Harper & Scinto07/16/2009 > patent applications in patent subcategories. category listing
20090181473 - Magnetically enhanced power inductor with self-aligned hard axis magnetic core produced in an applied magnetic field using a damascene process sequence: A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel... Agent: Dergosits & Noah LLP (nsc) Counsel For National Semiconductor Corporation
20090181474 - Method of manufacturing semiconductor device and thermal annealing apparatus: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the... Agent: Fujitsu Patent Center C/o Cpa Global
20090181475 - Detecting the presence of a workpiece relative to a carrier head: A carrier head for a workpiece includes a capacitive sensor that is configured to detect the presence of the workpiece during a chemical mechanical planarization/polishing procedure. The sensor subsystem can detect a wafer unloaded condition, a wafer loaded condition, and different in-process conditions that might occur during processing of the... Agent: Ingrassia Fisher & Lorenz, P.C. (nvls)
20090181476 - Assembly method for reworkable chip stacking with conductive film: A method of stacking a chip, including an integrated circuit, onto a substrate including applying an anisotropic conductive film (ACF) or a solder-filled conductive film onto a surface thereof, the surface being configured to electrically couple to the film, placing the chip onto the film, the chip being configured to... Agent: Cantor Colburn LLP-ibm Yorktown
20090181477 - Integrated circuit on corrugated substrate: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Bever, Hoffman & Harms, LLP
20090181478 - Methods of depositing nanomaterial & methods of making a device: Methods for depositing material and nanomaterial onto a substrate are disclosed. Also disclosed are methods of making devices including nanomaterials, and a system useful for depositing materials and nanomaterials.... Agent: Martha Ann Finnegan Qd Vision, Inc.
20090181479 - End-face-processing jig, and method of manufacturing semiconductor laser using end-face-processing jig: The invention provides an end-face-processing jig that allows the formation of a reflectance control film on an end face of a semiconductor laser body while preventing possible degradation due to catastrophic optical damage (COD) of a semiconductor laser, and a method of manufacturing a semiconductor laser employing such an end-face-processing... Agent: Leydig Voit & Mayer, Ltd
20090181480 - Led heat-radiating substrate and method for making the same: A method for making an LED is proposed. First a light-emitting structure is formed on a temporary substrate, and then a heat radiating substrate is formed on the light-emitting structure. Next the temporary substrate is removed. The heat radiating substrate includes a low expansion body and a high thermal conductivity... Agent: North America Intellectual Property Corporation
20090181482 - Flat panel display and method of fabricating the same: A flat panel display apparatus includes a gate insulating layer having openings which define pixels. The flat panel display apparatus includes: a substrate; a source electrode and a drain electrode formed on the substrate; a semiconductor layer contacting the source electrode and the drain electrode; a gate formed on the... Agent: Robert E. Bushnell & Law Firm
20090181481 - Method of manufacturing an led: A method of manufacturing an LED of high reflectivity includes forming a substrate; depositing an n-type GaN layer on the substrate; depositing an active layer on a first portion of the n-type GaN layer; attaching an n-type metal electrode to a second portion of the n-type GaN layer; depositing a... Agent: Kamrath & Associates P.A.
20090181483 - Crystallization apparatus, optical member for use in crystallization apparatus, crystallization method, manufacturing method of thin film transistor, and manufacturing method of matrix circuit substrate of display: A crystallization method includes wavefront-dividing an incident light beam into a plurality of light beams, condensing the wavefront-divided light beams in a corresponding phase shift portion of a phase shift mask or in the vicinity of the phase shift portion to form a light beam having an light intensity distribution... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090181484 - Semiconductor light emitting device and method of manufacturing the same: Provided are a semiconductor light emitting device having a nano pattern and a method of manufacturing the semiconductor light emitting device. The semiconductor light emitting device includes: a semiconductor layer comprising a plurality of nano patterns, wherein the plurality of nano patterns are formed inside the semiconductor layer; and an... Agent: Buchanan, Ingersoll & Rooney PC
20090181485 - Method of manufacturing vertical gallium-nitride based light emitting diode: A vertical GaN-based LED and a method of manufacturing the same are provided. The vertical GaN-based LED can prevent the damage of an n-type GaN layer contacting an n-type electrode, thereby stably securing the contact resistance of the n-electrode. The vertical GaN-based LED includes: a support layer; a p-electrode formed... Agent: Mcdermott Will & Emery LLP
20090181486 - method for producing a transistor-type hydrogen sensor: A method for producing a transistor-type hydrogen sensor is invented. This method combines conventional semiconductor fabrication process with an electroless plating technique. The fabrication process comprises steps as follows: (a) preparing a semiconductor substrate, (b) forming a semiconductor-based material with an exposed surface on the substrate, (c) washing and then... Agent: Rabin & Berdo, PC
20090181488 - Mems thermal actuator and method of manufacture: A separated MEMS thermal actuator is disclosed which is largely insensitive to creep in the cantilevered beams of the thermal actuator. In the separated MEMS thermal actuator, a inlaid cantilevered drive beam formed in the same plane, but separated from a passive beam by a small gap. Because the inlaid... Agent: Jaquelin K. Spong
20090181487 - Method of making microminiature moving device: A microminiature moving device has disposed on a single-crystal silicon substrate movable elements such as a movable rod and a movable comb electrode that are displaceable in parallel to the substrate surface and stationary parts that are fixedly secured to the single-crystal silicon substrate with an insulating layer sandwiched between.... Agent: Gallagher & Lathrop, A Professional Corporation
20090181489 - Microphone manufacturing method: A sacrifice layer 36 is exposed through a chemical charging port 31 so that the sacrifice layer 36 and sacrifice layer 35 are etched and removed by an etchant introduced from the chemical charging port 31. Since the surface of an Si substrate 22 is exposed to an etching window... Agent: Osha Liang L.L.P.
20090181490 - Image sensing devices and methods for fabricating the same: Image sensing devices and methods for fabricating the same are provided. An exemplary image sensing device comprises a first substrate having a first side and a second side opposing each other. A plurality of image sensing elements is formed in the first substrate at the first side. A conductive via... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090181491 - High-resolution integrated x-ray cmos image sensor: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20090181492 - Nano-cleave a thin-film of silicon for solar cell fabrication: An approach for nano-cleaving a thin-film of silicon for solar cell fabrication is described. In one embodiment, there is a method of forming a substrate for use as a solar cell substrate. In this embodiment, a substrate of silicon is provided and implanted with an ion flux. A non-silicon substrate... Agent: Scott Faber, Esq. Varian Semiconductor Equipment Associates, Inc
20090181493 - Vertical organic fet and method for manufacturing same: The present invention provides a vertical organic FET with increased carrier mobility and suppressed molecular orientation of an active layer composed of an organic semiconductor. The present invention relates to a vertical organic FET having a structure in which at least a source electrode layer, a drain electrode layer, a... Agent: Mcdermott Will & Emery LLP
20090181495 - Semiconductor module: A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to... Agent: Dicke, Billig & Czaja
20090181494 - Stack package and method for manufacturing the same: A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via... Agent: Ladas & Parry LLP
20090181498 - Method for fabricating a flip chip system in package: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first... Agent: Volentine & Whitt PLLC
20090181497 - Method for processing a base: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both... Agent: Fujitsu Patent Center C/o Cpa Global
20090181496 - Multi-layer substrate and manufacture method thereof: Disclosed are a multi-layer substrate and a manufacture method thereof. The multi-layer substrate of the present invention comprises a surface dielectric layer and at least one bond pad layer. The surface dielectric layer is located at a surface of the multi-layer substrate. The bond pad layer is embedded in the... Agent: Austin Rapp & Hardman
20090181499 - Ic packaging process: An IC packaging process includes the steps of forming a photo-curing adhesive layer on a bottom side of a lead frame and then harden the photo-curing adhesive layer; mounting a chip fixedly on a top side of the lead frame and electrically connecting the chip to the lead frame; proceeding... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw
20090181500 - Fabrication of compact semiconductor packages: A wafer-level method of fabricating a chip-to-wafer or wafer-to-wafer semiconductor packages includes etching a cavity into a first semiconductor wafer and etching vias in a bottom of the cavity. The cavity and sidewalls of the vias are selectively metallized. The cavity can be used to house either an electrical circuit... Agent: Fish & Richardson P.C.
20090181501 - Method for manufacturing a charge coupled device: A method for manufacturing a semiconductor device includes steps of forming an embedded channel 12 in a semiconductor substrate 11, forming a resist layer on the embedded channel 12 through an oxide film 14, exposing the resist layer using a grating mask the light transmissivity of which varies toward transfer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090181502 - Method for fabricating graphene transistors on a silicon or soi substrate: A method of fabricating graphene transistors, comprising providing an SOI substrate, performing an optional threshold implant on the SOI substrate, forming an upper silicon layer mesa island, carbonizing the silicon layer into SiC utilizing a gaseous source, converting the SiC into graphene, forming source/drain regions on opposite longitudinal ends of... Agent: Texas Instruments Incorporated
20090181503 - Planar split-gate high-performance mosfet structure and manufacturing method: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting... Agent: Bo-in Lin
20090181504 - Method for manufacturing a cmos device having dual metal gate: A method for manufacturing a CMOS device includes providing a substrate having a first active region and a second active region defined thereon, forming a first conductive type transistor and a second conductive type transistor respectively in the first and the second active regions, performing a salicide process, forming an... Agent: North America Intellectual Property Corporation
20090181505 - Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device: In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last... Agent: Wall & Tong, LLP IBM Corporation
20090181506 - Novel method to form memory cells to improve programming performance of embedded memory technology: An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region... Agent: Texas Instruments Incorporated
20090181507 - Sige channel epitaxial development for high-k pfet manufacturability: A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to... Agent: International Business Machines Corporation Dept. 18g
20090181508 - Method and structure for nfet with embedded silicon carbon: A method forms a gate stack over a channel region of a substrate and then forms disposable spacers on sides of the gate stack. Trenches are then recessed in regions of the substrate not protected by the gate stack and the disposable spacers. Carbon-doped Silicon lattice structures are then formed... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090181509 - Polymer semiconductors with high mobility: m
20090181510 - Method of manufacturing semiconductor device including isolation process: Provided may be a method of manufacturing a semiconductor device. The method may include forming a plurality of isolation patterns including conductive patterns on a semiconductor substrate and forming gaps between the isolation patterns, forming active patterns filling the gaps on the semiconductor substrate, forming a gate insulation layer on... Agent: Harness, Dickey & Pierce, P.L.C
20090181511 - Methods of forming semiconductor devices having self-aligned bodies: A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the... Agent: Myers Bigel Sibley & Sajovec
20090181512 - Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench, which reaches down to the insulator and surrounds a region of the monocrystalline silicon of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer... Agent: Coats & Bennett/infineon Technologies
20090181513 - Vertical organic transistor: A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings... Agent: Sinorica, LLC
20090181514 - Heat treatment apparatus and method for manufacturing soi substrate using the heat treatment apparatus: A heat treatment apparatus is disclosed, which enables suppression of a warp of a base substrate to which a plurality of single crystal semiconductor substrates are bonded. An example of the apparatus comprises a treatment chamber, a supporting base provided in the treatment chamber, a plurality of supports which are... Agent: Eric Robinson
20090181515 - Selective germanium deposition for pillar devices: A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device.... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20090181516 - Method of forming isolation layer of semiconductor device: A method of forming an isolation layer of a semiconductor device is disclosed. In the method according to one aspect, a semiconductor substrate having a trench formed therein is provided. A first insulating layer is formed over an entire surface of the semiconductor substrate including a surface of the trench.... Agent: Marshall, Gerstein & Borun LLP
20090181517 - Method of forming flash memory device: The present invention relates to a method of forming a flash memory device, which is capable of forming floating gates. According to a method of forming a flash memory device in accordance with the present invention, isolation mask patterns are first formed over a semiconductor substrate. Trenches are formed by... Agent: Lowe Hauptman Ham & Berner, LLP
20090181518 - Manufacturing method and manufacturing apparatus of semiconductor substrate: It is an object to provide a homogeneous semiconductor substrate in which defective bonding is reduced. Such a semiconductor substrate can be formed by the steps of: disposing a first substrate in a substrate bonding chamber which includes a substrate supporting base where a plurality of openings is provided, substrate... Agent: Eric Robinson
20090181519 - Lamination device manufacturing method: A lamination device manufacturing method for manufacturing a lamination device using a reinforced wafer formed with an annular reinforced portion, includes a wafer lamination step in which a rear surface of the reinforced wafer corresponding to the device area is faced to and joined to the front surface of an... Agent: Greer, Burns & Crain
20090181520 - Method and structure for dividing a substrate into individual devices: A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on... Agent: Townsend And Townsend And Crew, LLP
20090181521 - Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of... Agent: Oliff & Berridge, PLC
20090181522 - Method for producing semiconductor optical device: To grasp a removable particle contamination and appropriately removing a particle contamination exposing from a surface of a semiconductor layer, this production method of the semiconductor optical device includes a surface treatment step in which particle contaminations removed from a surface of a cap layer 5 by etching are limited... Agent: Smith, Gambrell & Russell
20090181523 - Method of manufacturing semiconductor device and apparatus for processing substrate: A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant... Agent: Oliff & Berridge, PLC
20090181524 - Method of manufacturing semiconductor device and apparatus for processing substrate: A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant... Agent: Oliff & Berridge, PLC
20090181525 - Wafer structure and epitaxial growth method for growing the same: A wafer structure and epitaxial growth method for growing the same. The method may include forming a mask layer having nano-sized areas on a wafer, forming a porous layer having nano-sized pores on a surface of the wafer by etching the mask layer and a surface of the wafer, and... Agent: Harness, Dickey & Pierce, P.L.C
20090181526 - Plasma doping method and apparatus: The plasma doping apparatus of the invention introduces a predetermined mass flow of gas from a gas supply device (2) into a vacuum chamber (1) while discharging the gas through an exhaust port (11) by a turbo-molecular pump (3), which is an exhaust device in order to maintain the vacuum... Agent: Mcdermott Will & Emery LLP
20090181527 - Graphite member for beam-line internal member of ion implantation apparatus: The problem of the present invention is to provide, in high current-low energy type ion implantation apparatuses, a graphite member for a beam line inner member of an ion implantation apparatus, which graphite member can markedly reduce particles incorporated in a wafer surface. This problem can be solved by the... Agent: Wenderoth, Lind & Ponack, L.L.P.
20090181528 - Method of forming gate electrode: The present invention discloses to a method of forming a gate electrode, the method according to the present invention comprises the steps of forming a lower amorphous silicon layer using silane (SiH4) gas and nitrous oxide (N2O) gas; forming an upper amorphous silicon layer on the lower amorphous silicon layer;... Agent: Marshall, Gerstein & Borun LLP
20090181529 - Method of forming a contact hole and method of manufacturing a semiconductor device having the same: In a method of forming a contact hole and a method of manufacturing a semiconductor device having the same, a first insulation interlayer is formed on a substrate. A dummy pattern is formed on the first insulation interlayer. A second insulation interlayer is formed to cover the dummy pattern. A... Agent: Mills & Onello LLP
20090181530 - high-k dielectric stack and method of fabricating same: A method for improving the reliability of a high-k dielectric layer or a high-k dielectric stack by forming an amorphous high-k dielectric layer over an insulating layer, doping the amorphous high-k dielectric layer with nitrogen atoms, and subsequently heating the resulting structure at a temperature greater than or equal to... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20090181531 - Methods of manufacturing non-volatile memory devices having insulating layers treated using neutral beam irradiation: Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a... Agent: Myers Bigel Sibley & Sajovec
20090181532 - Integration scheme for extension of via opening depth: An interconnect structure having an incomplete via opening is processed to deepen a via opening and to expose a metal line. In case the interconnect structure comprises a metal pad or a blanket metal layer, the metal pad or the metal layer is removed selective to an underlying dielectric layer... Agent: Scully, Scott, Murphy & Presser, P.C.
20090181533 - Alignment verification for c4np solder transfer: A method is provided for the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and determines if any off-set resulted between the solder mold array and the wafer capture array during the transfer process. The... Agent: Law Office Of Delio & Peterson, LLC.
20090181534 - Charging-free electron beam cure of dielectric material: An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the... Agent: Scully, Scott, Murphy & Presser, P.C.
20090181535 - Method of manufacturing a semiconductor device: Scale down design has posed problems in an increase in the resistance value of an interconnection structure and a decrease in the resistance to electromigration and stress migration. The present invention provides an interconnection structure of a high-reliability semiconductor device which has a low resistance value even in the case... Agent: Young & Thompson
20090181536 - Method of manufacturing semiconductor device: In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is used to form a wiring groove 111, allowing the shape of the wiring groove 111 to be stabilized. Furthermore,... Agent: Steptoe & Johnson LLP
20090181537 - Semiconductor structure comprising an electrical connection and method of forming the same: A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second... Agent: Mark W. Sincell Williams, Morgan & Amerson, P.C.
20090181538 - Film forming method, film forming apparatus and storage medium: A film forming method is provided with a substrate placing step wherein a substrate is placed in a process chamber in an airtight status; a first film forming step wherein the process chamber is supplied with water vapor and a material gas including an organic compound of copper, and an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090181540 - Chemical mechanical polishing method: A chemical mechanical polishing method, including: chemically and mechanically polishing a polishing target surface by continuously performing a first polishing step and a second polishing step having a polishing rate lower than a polishing rate of the first polishing step, a chemical mechanical polishing aqueous dispersion used in the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090181541 - Polishing process of a semiconductor substrate: A polishing composition containing at least one or more aminocarboxylic acids selected from the group consisting of serine, cysteine and dihydroxyethylglycine, ceria particles and an aqueous medium; a polishing process of a semiconductor substrate, including the step of polishing a semiconductor substrate with a polishing composition for a semiconductor substrate,... Agent: Birch Stewart Kolasch & Birch
20090181539 - Polishing agent for semiconductor integrated circuit device, polishing method, and method for manufacturing semiconductor integrated circuit device: An object of the present invention is to provide a polishing agent for a semiconductor, which is used for polishing a to-be-polished surface of a silicon dioxide-based material layer in the production of a semiconductor integrated circuit device and which is excellent in the dispersion stability and produces less defects... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090181542 - Method of forming bonding pad opening: A method of forming a bonding pad opening is provided. A passivation layer and a mask layer are sequentially formed on a substrate having a bonding pad formed thereon. Thereafter, the passivation layer is etched to form an opening with use of an anti-reflection coating (ARC) layer of the bonding... Agent: J C Patents, Inc.
20090181543 - Method of forming a pattern of a semiconductor device: In a method of forming patterns of a semiconductor device, a to-be-etched layer is formed on a semiconductor substrate. First etch mask patterns are formed over the to-be-etched layer. An auxiliary layer is formed on the first etch mask patterns and the to-be-etched layer. The auxiliary layer is thicker on... Agent: Townsend And Townsend And Crew, LLP
20090181544 - Method for preventing backside defects in dielectric layers formed on semiconductor substrates: A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled... Agent: Schmeiser, Olsen & Watts
20090181545 - Dry-etching method and apparatus: A resist damage free dry-etching process is proposed. A time duration defined until bias electric power is applied is controlled according to a plasma ignition detection signal. Wafer back-side gas pressure for a certain constant time after starting of an etching process operation is set to be lower than that... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090181546 - Single-wafer etching method for wafer and etching apparatus thereof: A single-wafer etching apparatus according to the present invention supplies an etchant to an upper surface of a wafer while rotating the wafer, thereby etching the upper surface of the wafer. Further, wafer elevating means moves up and down the wafer, and a lower surface blow mechanism which blows off... Agent: Greenblum & Bernstein, P.L.C
20090181547 - Method of producing semiconductor device: Disclosed is a substrate processing apparatus, including: a processing space to provide a space in which a substrate is to be processed; a heating member to heat the processing space; a gas supply member to supply at least first and second processing gases to the processing space; an exhaust member... Agent: Birch Stewart Kolasch & Birch
20090181548 - Vertical plasma processing apparatus and method for semiconductor process: A vertical plasma processing apparatus for a semiconductor process includes a process container having a process field configured to accommodate a plurality of target substrates at intervals in a vertical direction, and a marginal space out of the process field. In processing the target substrates, a control section simultaneously performs... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090181549 - Method for forming a gate insulating film: In formation of a gate insulating film made of a high dielectric constant metal silicate, atomic layer deposition (ALD) is performed by setting exposure time to a precursor containing a metal or the like to saturation time of a deposition rate by a surface adsorption reaction and by setting exposure... Agent: Mcdermott Will & Emery LLP
20090181550 - Film formation method and apparatus for semiconductor process: A film formation process is performed to form a silicon nitride film on a target substrate within a process field configured to be selectively supplied with a first process gas containing a silane family gas and a second process gas containing a nitriding gas. The method is preset to compose... Agent: Smith, Gambrell & Russell
20090181551 - Integrated circuit system employing multiple exposure dummy patterning technology: An integrated circuit system that includes: providing a substrate coated with a photoresist material; exposing the photoresist material to an energy source through a first mask to form a first substrate feature and a second substrate feature therein; and exposing the photoresist material to the energy source through a second... Agent: Law Offices Of Mikio Ishimaru
20090181552 - Laser processing apparatus and method for manufacturing semiconductor substrate: An SOI substrate having a single crystal semiconductor layer the surface of which has high planarity is manufactured. A semiconductor substrate is doped with hydrogen to form a damaged region containing a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each... Agent: Eric Robinson
20090181553 - Apparatus and method of aligning and positioning a cold substrate on a hot surface: Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat... Agent: Patterson & Sheridan, LLP - - Appm/tx07/09/2009 > patent applications in patent subcategories. category listing
20090176320 - Method for fabrication of floating gate in semiconductor device: A method for manufacturing a floating gate includes: forming a tunnel oxide film on a semiconductor substrate; forming a polysilicon layer on a surface of the tunnel oxide film; forming a photosensitive film pattern on a surface of the polysilicon layer; depositing a by-product on the photosensitive film to generate... Agent: Sherr & Vaughn, PLLC
20090176321 - Template for forming solder bumps, method of manufacturing the template and method of inspecting solder bumps using the template: A template for forming solder bumps includes a transparent substrate on which a plurality of cavities is formed at an upper surface portion thereof, and a light-reflective layer and a protective layer formed on a lower surface of the transparent substrate. When a nozzle makes close contact with the template... Agent: Daly, Crowley, Mofford & Durkee, LLP
20090176322 - Method for fabricating an ink jetting device: A method for forming an ink jetting device includes providing a silicon chip including a silicon substrate having a first surface and a second surface opposite to the first surface, the first surface having formed thereon a plurality of electrical heater elements and a silicon oxide ink ejection chamber layer... Agent: Lexmark International, Inc. Intellectual Property Law Department
20090176323 - Process for producing light-emitting semiconductor device: A process for producing a light-emitting semiconductor device includes: (i) mixing at least one low-molecular silane or at least one silanol with an alcohol solution containing an alkoxysiloxane to prepare a mixture solution, the amount of the silane or silanol being from 10% by weight to 50% by weight based... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090176325 - Halftone mask, method of manufacturing the same, and method of manufacturing an array substrate using the same: A halftone mask includes a transparent substrate, a light-blocking layer, a first semi-transparent layer and a second semi-transparent layer. The transparent substrate includes a light-blocking area, a light-transmitting area, a first halftone area transmitting first light, and a second halftone area transmitting second light that is less than the first... Agent: F. Chau & Associates, LLC
20090176326 - System for displaying images and method for fabricating the same: An exemplary embodiment of a system comprises an active matrix organic electroluminescent device, having a substrate, and a plurality of scan lines and data lines disposed on the substrate, for defining a plurality of pixel regions. Each pixel structure comprises: a switching thin film transistor, a driving thin film transistor,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090176327 - Photodiode and method for fabricating same: A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film... Agent: Hayes Soloway P.C.
20090176328 - Semiconductor device and semiconductor device manufacturing method: A semiconductor device is provided and includes a substrate, a photoelectric converting portion, a plurality of optical waveguide portions stacked above the photoelectric conversion portion, each of the plurality of optical waveguide portions including a translucent material and being shaped in a taper.... Agent: Birch Stewart Kolasch & Birch
20090176329 - Phase-change memory device and method of manufacturing the same: In a method of forming a phase-change memory device, a variable resistance member may be formed on a s semiconductor substrate having a contact region, and a first electrode may be formed to contact a first portion of the variable resistance member and to be electrically connected to the contact... Agent: Harness, Dickey & Pierce, P.L.C
20090176330 - Photodiode having increased proportion of light-sensitive area to light-insensitive area: A photodiode having an increased proportion of light-sensitive area to light-insensitive area includes a semiconductor having a backside surface and a light-sensitive frontside surface. The semiconductor includes a first active layer having a first conductivity, a second active layer having a second conductivity opposite the first conductivity, and an intrinsic... Agent: Panitch Schwarze Belisario & Nadel LLP
20090176331 - Method for processing a base: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both... Agent: Fujitsu Patent Center C/o Cpa Global
20090176332 - Multi-chip device and method for manufacturing the same: A multi-chip device includes a plurality of chips, a metal pad on a first one of the chips, a through-hole plug electrode in the first one of the chips, a contact node in the first one of the chips connecting the metal pad to the through-hole plug electrode in the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090176333 - Method of manufacturing semiconductor device: To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090176334 - Method for forming a die-attach layer during semiconductor packaging processes: Disclosed is a method for forming a die-attach layer during semiconductor packaging processes. A chip carrier includes a substrate core and a stiffener. Top surface of the substrate core includes a plurality of die-attaching units and a peripheral area enclosed by the stiffener. A non-planar printing stencil is also provided.... Agent: Joe Mckinney Muncy
20090176335 - Method of manufacturing a semiconductor device: According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead 1e is smaller than that of a silver plating formed on each lead. Thereafter, a semiconductor... Agent: Mattingly & Malur, P.C.
20090176336 - Method of manufacturing a semiconductor device: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface... Agent: Texas Instruments Incorporated
20090176338 - Fully-depleted (fd)(soi) mosfet access transistor and method of fabrication: A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.... Agent: Dickstein Shapiro LLP
20090176337 - Negative photoresist composition and method of manufacturing array substrate using the same: A negative photoresist composition and a method of manufacturing an array substrate. The negative photoresist composition includes a photocurable composition including an ethylene unsaturated compound containing an ethylene unsaturated bond and a photopolymerization initiator, a thermosetting composition including an alkali-soluble resin crosslinked by heat and an organic solvent. The negative... Agent: Cantor Colburn, LLP
20090176339 - Method of multi-port memory fabrication with parallel connected trench capacitors in a cell: A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates... Agent: International Business Machines Corporation Dept. 18g
20090176340 - Manufacturing method of semiconductor device: A method of manufacturing a semiconductor device, particularly a vertical transistor, including forming a contact hole and forming a pillar using an epitaxial growth process.... Agent: Marshall, Gerstein & Borun LLP
20090176341 - Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process: A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of... Agent: Gardere Wynne Sewell LLP Intellectual Property Section
20090176342 - Method of fabricating semiconductor device having deifferential gate dielectric layer and related device: A semiconductor device and method of fabricating a semiconductor device are provided. The method includes forming a gate trench in a semiconductor substrate to define source/drain regions. The source/drain regions are separated from each other by the gate trench, and the semiconductor substrate is exposed through the gate trench. The... Agent: Harness, Dickey & Pierce, P.L.C
20090176343 - P-channel mos transistor and fabrication process thereof: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090176344 - Mos devices with corner spacers: A MOS device having corner spacers and a method for forming the same are provided. The method includes forming a gate structure overlying a substrate, forming a first dielectric layer over the gate structure and the substrate, forming a second dielectric layer on the first dielectric layer, forming a third... Agent: Slater & Matsil, L.L.P.
20090176345 - Process for producing thin-film capacitor: It is an object of the invention to provide a process for production of a thin-film capacitor that can simultaneously achieve improved capacity density and reduced leakage current density for barium strontium titanate thin-films. There is provided a process for production of thin-film capacitors that includes a metal oxide thin-film... Agent: Oliff & Berridge, PLC
20090176346 - Monitor pattern of semiconductor device and method of manufacturing semiconductor device: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090176347 - Hybrid orientation substrate compatible deep trench capacitor embedded dram: Method of limiting the lateral extent of a trench capacitor by a dielectric spacer in a hybrid orientations substrate is provided. The dielectric spacer separates a top semiconductor portion from an epitaxially regrown portion, which have different crystallographic orientations. The deep trench is formed as a substantially straight trench within... Agent: Scully, Scott, Murphy & Presser, P.C.
20090176348 - Removable layer manufacturing method: A method (200) is described for an electronic assembly (30). An electronic die (24) with a sacrificial layer (28) on its back (27) and electrical contacts (26) on its front (25) is temporarily attached by its front (25) to a substrate (32). The back (27) is over-molded by a first... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)
20090176349 - Method and device for machining a wafer, in addition to a wafer comprising a separation layer and a support layer: A process and an apparatus are described for the treatment of wafers, in particular for the thinning of wafers. A wafer with a carrier layer and an interlayer arranged between the carrier layer and the wafer is also described, in which the interlayer is a plasmapolymeric layer that adheres to... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.
20090176350 - Integration of ion gettering material in dielectric: A method embodiment deposits a first dielectric layer over a transistor and then implants a gettering agent into the first dielectric layer. After this first dielectric layer is formed, the method forms a second (thicker) dielectric layer over the first dielectric layer. After this, the standard contacts are formed through... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090176351 - Structure and method to improve mosfet reliability: A method embodiment deposits a dielectric layer over a transistor and then implants a gettering agent into the dielectric layer. The insulating layer into which the gettering agent is implanted comprises a single continuous insulating layer and is the insulating layer that borders the next layer of metallization. After this... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090176352 - Semiconductor device, method of manufacturing the same, and substrate for manufacturing the same: A semiconductor device includes a substrate, a buffer layer that is formed with an aluminum nitride layer on the substrate and has a film thickness of 5 nm to 40 nm, an operating layer that is formed with a gallium nitride-based semiconductor on the buffer layer, and a control electrode... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090176353 - Crystalline-type device and approach therefor: Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material, such as Ge or a semiconductor compound, is crystallized... Agent: Crawford Maunu PLLC
20090176354 - Method for fabrication of single crystal diodes for resistive memories: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous... Agent: Scully, Scott, Murphy & Presser, P.C.
20090176355 - Plasma doping method and plasma processing device: In a plasma doping device according to the invention, a vacuum chamber (1) is evacuated with a turbo-molecular pump (3) as an exhaust device via a exhaust port 11 while a predetermined gas is being introduced from a gas supply device (2) in order to maintain the inside of the... Agent: Mcdermott Will & Emery LLP
20090176356 - Methods for fabricating semiconductor devices using thermal gradient-inducing films: Methods for fabricating semiconductor devices using thermal gradient-inducing films are provided. One method comprises providing a substrate having a first region and a second region and forming a film overlying the second region and exposing the first region. The substrate is subjected to a thermal process wherein the film induces... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)
20090176357 - Semiconductor device and method of manufacturing the same: In one embodiment, a semiconductor device comprises a conductive pad formed in a semiconductor substrate. The semiconductor device further includes a conductive pattern overlying a peripheral region of the conductive pad. The conductive pattern has an opening to expose another region of the conductive pad. The semiconductor device also includes... Agent: Marger Johnson & Mccollom, P.C.
20090176358 - Discrete trap memory (dtm) mediated by fullerenes: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical... Agent: Slater & Matsil LLP
20090176359 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090176360 - Methods for processing a substrate with a flow controlled meniscus: A method for processing a substrate is provided which includes applying fluid onto a surface of the substrate from a portion of a plurality of inlets and removing at least the fluid from the surface of the substrate where the removing being processed as the fluid is applied to the... Agent: Martine Penilla & Gencarella, LLP
20090176361 - Semiconductor device preventing electrical short and method of manufacturing the same: A semiconductor device capable of preventing an electrical short between contacts and their adjacent contact pads and a method of manufacturing the same are provided. A first interlayer insulating layer is formed on the semiconductor substrate including the active region. Contact pads pass through the first interlayer insulating layer and... Agent: Mills & Onello LLP
20090176362 - Methods of forming interconnects in a semiconductor structure: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure... Agent: Trask Britt, P.C./ Micron Technology
20090176363 - Etching composition for an under-bump metallurgy layer and method of forming a bump structure using the same: In an etching composition for an under-bump metallurgy (UBM) layer and a method of forming a bump structure, the etching composition includes about 40% by weight to about 90% by weight of hydrogen peroxide (H2O2), about 1% by weight to about 20% by weight of an aqueous basic solution including... Agent: Lee & Morse, P.C.
20090176364 - Semiconductor device having a refractory metal containing film and method for manufacturing the same: A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2 film provided... Agent: Young & Thompson
20090176365 - Contact formation: The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of... Agent: Brooks, Cameron & Huebsch , PLLC
20090176366 - Micropad formation for a semiconductor: A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at... Agent: Freescale Semiconductor, Inc. Law Department
20090176367 - Optimized sicn capping layer: A back-end-of-line (BEOL) interconnect structure and a method of forming an interconnect structure. The interconnect structure comprises a conductor, such as copper, embedded in a dielectric layer, and a low-k dielectric capping layer, which acts as a diffusion barrier, on the conductor. A method of forming the BEOL interconnect structure... Agent: Intellectual Property Law IBM Corporation
20090176368 - Manufacturing method for an integrated circuit structure comprising a selectively deposited oxide layer: The present invention provides a manufacturing method for an integrated circuit structure comprising a selectively deposited oxide layer. An integrated circuit structure including a first and second region is provided, the first region being a metal region and the second region being a non-metal region. Then an oxide layer is... Agent: Coats & Bennett/qimonda
20090176369 - Low-h plasma treatment with n2 anneal for electronic memory devices: A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN... Agent: Thomas G. Eschweiler, Esq. Eschweiler & Associates, LLC
20090176370 - Single soi wafer accelerometer fabrication process: Methods for producing a MEMS device from a single silicon-on-insulator (SOI) wafer. An SOI wafer includes a silicon (Si) handle layer, a Si mechanism layer and an insulator layer located between the Si handle and Si mechanism layers. An example method includes etching active components from the Si mechanism layer.... Agent: Honeywell International Inc.
20090176372 - Chemical mechanical polishing slurry and semiconductor device manufacturing method: A chemical mechanical polishing slurry includes at least one water-soluble polymer selected from a group consisting of polyacrylic acid, polymethacrylic acid and a salt thereof each having a weight-average molecular weight of 1,000,000 to 10,000,000, β-cyclodextrin, colloidal silica, and water.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090176371 - Method for the preferential polishing of silicon nitride versus silicon oxide: The present invention provides a method of removing silicon nitride in preference to silicon dioxide by CMP. The method utilizes a polishing slurry that includes colloidal silica abrasive particles dispersed in water and an additive that suppresses the silicon dioxide removal rate but enhances the silicon nitride removal rate. In... Agent: Rankin, Hill & Clark LLP
20090176373 - Polishing agent for semiconductor integrated circuit device, polishing method, and method for manufacturing semiconductor integrated circuit device: The present invention is to provide a polishing technique ensuring that when polishing a to-be-polished surface in the production of a semiconductor integrated circuit device, appropriate polishing rate ratios can be obtained between a borophosphosilicate glass material layer and other materials and high planarization of the to-be-polished surface containing a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090176374 - Pattern forming method, semiconductor device manufacturing apparatus and storage medium: A pattern forming method includes (a) forming pairs of deposits on sidewalls of mask portions in first mask patterns by forming a thin film thereon, etching it to leave deposits, and exposing a top surface of a second-layer film between the deposits; (b) forming second mask patterns formed of mask... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090176375 - Method of etching a high aspect ratio contact: Methods and an etch gas composition for etching a contact opening in a dielectric layer are provided. Embodiments of the method use a plasma generated from an etch gas composed of C4F8 and/or C4F6, an oxygen source, and a carrier gas in combination with tetrafluoroethane (C2F4) or a halofluorocarbon analogue... Agent: Whyte Hirschboeck Dudek S.c. Intellectual Property Department
20090176376 - Method of fine patterning semiconductor device: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first... Agent: Law Office Of Monica H Choi
20090176378 - Manufacturing method of dual damascene structure: A manufacturing method of a dual damascene structure is provided. First, a first dielectric layer, a second dielectric layer, and a mask layer are formed. A first trench structure is formed in the mask layer. A via structure is formed in the mask layer, the second dielectric layer, and the... Agent: Jianq Chyun Intellectual Property Office
20090176377 - Method of forming patterns of semiconductor device: The present invention relates to a method of forming patterns of a semiconductor device. In an aspect of the present invention, the method may include providing a semiconductor substrate, including a first area in which patterns are formed at a first interval and a second area formed wider than the... Agent: Townsend And Townsend And Crew, LLP
20090176379 - Semiconductor processing methods, and methods for forming silicon dioxide: Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate may have an inner region and an outer region laterally outward of said inner region, and may have a deposition surface that extends across the inner and outer regions. The... Agent: Wells St. John P.s.
20090176380 - Plasma treatment method and plasma treatment device: Provided are a plasma treatment method and a plasma treatment device capable of forming a silicon nitride film having high compressive stress. In the plasma treatment method for depositing the silicon nitride film on a process target substrate by use of plasma of raw material gas containing silicon and hydrogen... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090176381 - Method of manufacturing semiconductor device and substrate processing apparatus: There are provided a method of manufacturing a semiconductor device and a substrate processing apparatus that are designed to suppress a popping phenomenon and reduce residues remaining on a substrate in a photoresist removing process. Oxygen gas and hydrogen gas are supplied to a plasma generating chamber while maintaining the... Agent: Mattingly & Malur, P.C.07/02/2009 > patent applications in patent subcategories. category listing
20090170221 - Etch residue reduction by ash methodology: Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the... Agent: Texas Instruments Incorporated
20090170222 - Control of implant critical dimensions using an sti step height based dose offset: A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is... Agent: Texas Instruments Incorporated
20090170223 - Methods for calibrating a process for growing an epitaxial silicon film and methods for growing an epitaxial silicon film: Methods are provided for calibrating a process for growing an epitaxial silicon-comprising film and for growing an epitaxial silicon-comprising film. One method comprises epitaxially growing a first silicon-comprising film on a first silicon substrate that has an adjacent non-crystalline-silicon structure that extends from said first silicon substrate. The step of... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)
20090170225 - Method for manufacturing semiconductor light emitting device: A method for manufacturing a semiconductor light emitting device includes forming an insulating film on a semiconductor substrate, the insulating film having an opening therein, forming a Pd electrode in the opening and on the insulating film, and removing the portion of the Pd electrode on the insulating film by... Agent: Leydig Voit & Mayer, Ltd
20090170224 - Process for fabrication of nitride semiconductor light emitting device: The present invention relates to a process for fabrication of a nitride semiconductor light emitting device comprising a substrate, a nitride semiconductor layer on the substrate and electrodes on the nitride semiconductor, the process for fabrication of a nitride semiconductor light emitting device being characterized by device working by laser,... Agent: Sughrue Mion, PLLC
20090170227 - Mask and container and manufacturing: The present invention provides a large mask with a high mask accuracy for conducting selective deposition on a substrate with a large surface area. In accordance with the present invention, the mask body is fixed in a fixing position disposed on a line passing through a thermal expansion center in... Agent: Nixon Peabody, LLP
20090170226 - Package for a semiconductor light emitting device: A semiconductor light emitting device package includes a substrate with a core and a copper layer overlying the core. The light emitting device is connected to the substrate directly or indirectly through a wiring substrate. The core of the substrate may be, for example, ceramic, Al2O3, AlN, alumina, silicon nitride,... Agent: Patent Law Group LLP
20090170228 - Method of forming pattern having step difference and method of making thin film transistor and liquid crystal display using the same: A method of forming a pattern having a step difference and a method of making a thin film transistor and an LCD device using the method of forming the pattern. The method of forming a pattern having a step difference includes forming a first pattern having a predetermined shape in... Agent: Brinks Hofer Gilson & Lione
20090170229 - Method for producing a modulated grating for an optimal reflection spectrum: Method for producing a modulated grating for an optimal reflection spectrum, which grating is a multiple wavelength reflector. The method includes the following steps: a) Determining wavelengths to be reflected b) Calculating a preliminary grating c) Comparing the reflection spectrum ro(f) with the characteristics of the wanted modulated grating d)... Agent: Young & Thompson
20090170230 - Manufacturing method of display apparatus and manufacturing apparatus: A manufacturing method including applying a light emitting material solution for forming a light emitting function layer of the light emitting elements each of which has any one of a plurality of luminescent colors which carry out a color display arranged along a plurality of rows and along a plurality... Agent: Frishauf, Holtz, Goodman & Chick, PC
20090170232 - Method for manufacturing iamge sensor: In a method for manufacturing an image sensor, an interlayer insulating layer including a metal line is formed on a semiconductor substrate. A lower electrode layer is formed on the metal line such that the lower electrode is connected with the metal line. A photoresist pattern corresponding to the metal... Agent: Sherr & Vaughn, PLLC
20090170233 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor for preventing corrosion of a metal pad. The method for fabricating the CMOS image sensor can include sequentially forming a dielectric film, a metal pad having an opening, and a first passivation film on a semiconductor substrate having a scribe lane and... Agent: Sherr & Vaughn, PLLC
20090170234 - Image sensor and method for manufacturing thereof: Disclosed is a method for manufacturing an image sensor. The method includes a process for removing foreign matter from a non-device area of a wafer before forming contacts in a device area of the wafer. According to an embodiment, an insulating layer formed in the non-device area is removed by... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090170236 - Manufacturing method of image sensor: A manufacturing method of an image sensor includes forming lower electrodes over a semiconductor substrate having metal wires and an interlayer insulating film formed thereover; removing a photoresist polymer produced by the formation of the lower electrodes by performing a primary treatment using a first substance; and then removing an... Agent: Sherr & Vaughn, PLLC
20090170235 - Method for manufacturing image sensor: A method for manufacturing an image sensor includes forming a photolithography key in a scribe lane of a first substrate over which circuitry is formed in an active region. A photodiode is formed on an active region of a second substrate. The second substrate is bonded to the first substrate... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20090170238 - Printed organic logic circuits using a floating gate transister as a load device: A method of forming an organic inverter includes providing a first metal layer having a first portion for coupling a source of a first OFET to a first power supply voltage, a second portion for coupling a drain of the first OFET to an output terminal and to a source... Agent: Weyerhaeuser Company Intellectual Property Dept., Ch 1j27
20090170237 - Printed organic logic circuits using an organic semiconductor as a resistive load device: A method of forming an organic inverter includes providing a first metal layer having a first portion for coupling a source of an OFET to a first power supply voltage, a second portion for coupling a drain of the OFET to an output terminal and a first load resistor terminal,... Agent: Weyerhaeuser Company Intellectual Property Dept., Ch 1j27
20090170240 - Optimized circuit design layout for high performance ball grid array packages: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top... Agent: Texas Instruments Incorporated
20090170239 - Utilizing aperture with phase shift feature in forming microvias: A method, comprises drilling a set of one or more microvias in a semiconductor package with an aperture, wherein drilling the set of microvias comprises to use an aperture that has a phase shift region to reduce a spot size of a drilling beam that is used to form the... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090170241 - Semiconductor device and method of forming the device using sacrificial carrier: A semiconductor device is made by forming contact pads on a sacrificial carrier. The contact pads may be formed on a pillar. A semiconductor die is mounted to electrically connect to the contact pads with solder bumps or wire bonds. The semiconductor die is encapsulated with molding compound. The sacrificial... Agent: Robert D. Atkins
20090170243 - Stacked integrated circuit module: The present invention provides an improvement on the use of flexible circuit connectors for electrically coupling IC devices to one another in a stacked configuration by use of the flexible circuit to provide the connection of the stacked IC module to other circuits. Use of the flexible circuit as the... Agent: Fish & Richardson P.C.
20090170242 - System-in-package having integrated passive devices and method therefor: A method of manufacturing a semiconductor device involves providing a substrate, forming a first passivation layer over the substrate, and forming an integrated passive circuit over the substrate. The integrated passive circuit can include inductors, capacitors, and resistors. A second passivation layer is formed over the integrated passive circuit. System... Agent: Quarles & Brady LLP
20090170245 - Electronic apparatus manufacturing method: An electronic apparatus manufacturing method comprises applying a first adhesive agent to a mounting portion, a first heating, in such a way that connection pads and bumps, come into contact, by pressing a heating head against a non-mounting surface of the electronic component, heating the electronic component, hardening the first... Agent: Staas & Halsey LLP
20090170244 - Method for manufacturing a flip chip package: A method for manufacturing a flip chip package uses a dipping method to cohere liquid-state stannum onto a plurality of gold bumps of a chip. The gold bumps are correspondingly connected to a plurality of first pads of a substrate so as to connect the chip and the substrate. Finally,... Agent: Volentine & Whitt PLLC
20090170246 - Forming a 3-d semiconductor die structure with an intermetallic formation: A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different... Agent: Freescale Semiconductor, Inc. Law Department
20090170247 - Magnetic particles for low temperature cure of underfill: Electronic devices and methods for fabricating electronic devices are described. One embodiment includes a method comprising providing a first body and a second body, and electrically coupling the first body to the second body using a plurality of solder bumps, wherein a gap remains between the first body and the... Agent: Konrad Raynes & Victor, LLP. Attn: Int77
20090170248 - Method for manufacturing thin film transistor: A method for manufacturing a thin film transistor with improved current characteristics and high electron mobility. According to the method, when an amorphous silicon thin film is crystallized into a polycrystalline silicon thin film by metal-induced crystallization, annealing conditions of the amorphous silicon thin film and the amount of a... Agent: Iphorgan, Ltd.
20090170249 - Compound semiconductor device and method for fabricating the same: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode... Agent: Kratz, Quintos & Hanson, LLP
20090170250 - Transistor of semiconductor device and method of fabricating the same: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive... Agent: Ladas & Parry LLP
20090170251 - Fabrication of germanium nanowire transistors: In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement... Agent: RyderIPLaw C/o Cpa Global
20090170252 - Formation method of metallic compound layer, manufacturing method of semiconductor device, and formation apparatus for metallic compound layer: A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic... Agent: Mcginn Intellectual Property Law Group, PLLC
20090170253 - Method of manufacturing semiconductor device: To this end, a method of manufacturing a semiconductor device of the present invention comprises the steps of: forming a buffer layer formed in a dual structure of a buffer oxide film and a buffer nitride film on a semiconductor substrate formed with a certain lower structure; defining a gate... Agent: Morgan Lewis & Bockius LLP
20090170255 - Integrated circuit modification using well implants: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions... Agent: Ladas & Parry
20090170254 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a... Agent: F. Chau & Associates, LLC
20090170256 - Annealing method for sige process: A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further... Agent: Texas Instruments Incorporated
20090170257 - Method of manufacturing mos transistor: A method of manufacturing a transistor may include: forming a first well over a silicon substrate; forming a first mask pattern over the silicon substrate and using the formed first mask pattern to form a second well; removing the first mask pattern; forming a second mask pattern over the silicon... Agent: Sherr & Vaughn, PLLC
20090170258 - Methods for full gate silicidation of metal gate structures: One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to... Agent: Texas Instruments Incorporated
20090170259 - Angled implants with different characteristics on different axes: One embodiment relates to a method of forming an integrated circuit. In this method, at least one dopant species of a first conductivity type is implanted in a first manner along a first axis to form first pocket implant regions extending at least partially under some gates. At least one... Agent: Texas Instruments Incorporated
20090170260 - Non-volatile memory cell circuit with programming through band-to-band tunneling and impact ionization gate current: Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090170261 - Method for manufacturing semiconductor device having 4f2 transistor: Provided is a method for manufacturing a semiconductor device having a 4F2 transistor. In the method, a gate stack is formed on a semiconductor substrate. A first interlayer dielectric including a contact hole which includes a first region and second regions Spacer layers are formed on both sides of the... Agent: Marshall, Gerstein & Borun LLP
20090170262 - Virtual ground memory array and method therefor: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer... Agent: Freescale Semiconductor, Inc. Law Department
20090170263 - Method of manufacturing flash memory device: Disclosed is a method of manufacturing a flash memory device. With this method, the surface area of a floating gate is increased by using a buffer film or a dummy pattern, without increasing the size of the flash memory device. Therefore, a coupling ratio is increased, and as a result,... Agent: Sherr & Vaughn, PLLC
20090170264 - Method of producing semiconductor device: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A first conductive type impurity is diffused in the silicon carbide substrate. A method of producing a semiconductor device includes preparing the silicon carbide substrate forming a first conductive type... Agent: Kubotera & Associates, LLC Suite 202
20090170265 - Method of fabricating a recess gate type transistor: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the... Agent: Marshall, Gerstein & Borun LLP
20090170266 - Method for simultaneously manufacturing semiconductor devices: Methods for manufacturing semiconductor devices simultaneously to implement low-voltage and high-voltage devices in a single chip. In one example embodiment, a method includes various acts. An isolation layer is formed on a wafer. A gate oxide layer and a lower gate poly are sequentially formed on a first low-voltage transistor... Agent: Workman Nydegger 1000 Eagle Gate Tower
20090170267 - Tri-gate patterning using dual layer gate stack: In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker... Agent: RyderIPLaw C/o Cpa Global
20090170268 - Process for fabricating a semiconductor device having embedded epitaxial regions: A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers adjacent the gate electrode. The epitaxial regions are formed by... Agent: Brinks Hofer Gilson & Lione
20090170269 - High voltage mosfet devices containing tip compensation implant: Semiconductor devices and methods for making semiconductor devices are described in this application. The semiconductor devices comprise a MOSFET device in a semiconductor substrate, with the MOSFET device containing source and drain regions with a tip implant region near the surface of the substrate. The tip implant region contains a... Agent: Intel Corporation C/o Cpa Global
20090170270 - Integration schemes to avoid faceted sige: Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel... Agent: Texas Instruments Incorporated
20090170271 - Transistor and method of forming the same: According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover... Agent: Marger Johnson & Mccollom, P.C.
20090170272 - Semiconductor device and method of forming the same: A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the first hole. The capacitor may include bottom and... Agent: Sughrue Mion, PLLC
20090170273 - Dual layer hard mask for block salicide poly resistor (bsr) patterning: In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride... Agent: RyderIPLaw C/o Cpa Global
20090170274 - Method of forming metal trench pattern in thin-film device: A method of forming a metal trench pattern in a thin-film device includes a step of depositing an electrode film on a substrate or on a base layer, a step of forming a resist pattern layer having a trench forming portion used to make a trench pattern, on the deposited... Agent: Oliff & Berridge, PLC
20090170277 - Implant damage of layer for easy removal and reduced silicon recess: A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one... Agent: Texas Instruments Incorporated
20090170275 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes forming a spin-on-carbon (SOC) film that facilitates a low temperature baking process, can prevent collapse of vertical transistors while forming a bit line, thereby providing a more simple manufacturing method and improving manufacturing yields.... Agent: Marshall, Gerstein & Borun LLP
20090170276 - Method of forming trench of semiconductor device: The present invention relates to a method of forming trenches of a semiconductor device. According to the method, a hard mask pattern is formed on a semiconductor substrate so that an isolation region of the semiconductor substrate is opened. First trenches are formed in the isolation region by performing a... Agent: Marshall, Gerstein & Borun LLP
20090170278 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided that can comprise: forming a hard mask on a semiconductor substrate; forming a trench by etching the semiconductor substrate using the hard mask; performing a Chemical Mechanical Polishing (CMP) process after insulating film is buried in the trench; removing the hard... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090170281 - Method of forming isolation layer of semiconductor: The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor... Agent: Townsend And Townsend And Crew, LLP
20090170280 - Method of forming isolation layer of semiconductor device: A method of forming isolation layers of a semiconductor device, comprising providing a semiconductor substrate in which a tunnel dielectric layer and a conductive layer are formed in active regions having two ends and trenches are formed in isolation regions; rounding both ends of each active region by performing an... Agent: Marshall, Gerstein & Borun LLP
20090170279 - Method of preparing active silicon regions for cmos or other devices: A method of preparing active silicon regions for CMOS devices includes providing a structure including a silicon substrate (210, 410) having formed thereon first and second silicon diffusion lines (110, 420), both of which include first and second silicon layers (211, 213, 421, 423), a silicon germanium layer (212, 422),... Agent: Intel Corporation C/o Cpa Global
20090170282 - Method of forming isolation layer in semiconductor device: A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including... Agent: Marshall, Gerstein & Borun LLP
20090170283 - Method of fabricating non-volatile memory device: A method of fabricating a non-volatile memory device, A tunnel insulating layer, a floating gate, and a pad nitride layer is formed on a semiconductor substrate. A isolation region of the semiconductor substrate is formed by etching to a predetermined depth, and a liner insulating layer is formed on an... Agent: Marshall, Gerstein & Borun LLP
20090170285 - Method for manufacturing bonded wafer: The present invention provides a method for manufacturing a bonded wafer by an ion implantation delamination method, the method including at least the steps of bonding a base wafer with a bond wafer having a microbubble layer formed by ion implantation, delaminating the wafers along the micro bubble layer as... Agent: Oliff & Berridge, PLC
20090170286 - Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device: A semiconductor substrate is manufactured in which a plurality of single crystal semiconductor layers is fixed to a base substrate having low heat resistance such as a glass substrate with a buffer layer interposed therebetween. A plurality of single crystal semiconductor substrates is prepared, each of which includes a buffer... Agent: Eric Robinson
20090170287 - Method for manufacturing soi substrate: A single crystal semiconductor substrate and a base substrate are prepared; a first insulating film is formed over the single crystal semiconductor substrate; a separation layer is formed by introducing ions at a predetermined depth through a surface of the single crystal semiconductor substrate; plasma treatment is performed on the... Agent: Eric Robinson
20090170288 - Method of manufacturing semiconductor device: After a semiconductor element is formed and before resin sealing is performed, a surface of a scribe line between the adjacent semiconductor elements of a semiconductor wafer is scraped thinly. A laser is irradiated on a broken layer of the surface of the scribe line thus scraped thinly to recrystallize... Agent: Drinker Biddle & Reath (dc)
20090170289 - Wafer dividing method: A laser beam is applied to an intersection area of each second street of a wafer by using a dicing apparatus to thereby form a first modified layer along the intersection area. Thereafter, the wafer is divided along each first street intersecting each second street at right angles to obtain... Agent: Greer, Burns & Crain
20090170290 - Semiconductor manufacturing method of die pick-up from wafer: A manufacturing method of a semiconductor device comprising the steps of: affixing a die attach film and a dicing film to a back surface of a semiconductor wafer: thereafter dicing the semiconductor wafer and the die attach film to divide the semiconductor wafer into a plurality of semiconductor chips: thereafter... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090170291 - Method of fabricating an organic thin film transistor: An organic thin film transistor that prevents the surface of an organic semiconductor layer from being damaged and reduces turn-off current, a method of fabricating the same, and an organic light-emitting device incorporating the organic thin film transistor. The organic thin film transistor includes a substrate, source and drain electrodes... Agent: Robert E. Bushnell & Law Firm
20090170292 - Method for producing semiconductor substrate and semiconductor substrate: A production method for a semiconductor substrate for producing a high quality SGOI substrate 10 in which the dislocation density in a silicon germanium Si1-yGey layer (SGOI layer) formed on an embedded oxide film is reduced and the occurrence of defects is suppressed, by employing the SIMOX method, or a... Agent: Husch Blackwell Sanders, LLP Husch Blackwell Sanders LLP Welsh & Katz
20090170293 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer on the first semiconductor layer, etching the second semiconductor layer and the first semiconductor layer to form a first groove passing through the second semiconductor layer and the... Agent: Harness, Dickey & Pierce, P.L.C
20090170294 - Method for film depositing group iii nitride such as gallium nitride: [Solving Means] A reactor chamber 12 is filled with a pure nitrogen of approximately atmospheric pressure of about 40 kPa. A c-face sapphire substrate 90 is placed on an electrode 14. The substrate temperature is brought to 650 degree centigrade by a heater 15. An electric field is applied between... Agent: Sughrue Mion, PLLC
20090170295 - Manufacturing method for a semi-conductor on insulator substrate comprising a localised ge enriched step: condensation of the germanium of the layer of Si1-xGex on the island to obtain an island comprising a layer that is enriched in germanium, or even a layer of germanium, on the buried insulating layer, with a silicon oxide layer on top of it.... Agent: Pearne & Gordon LLP
20090170296 - Method and apparatus for activating compound semiconductor: A compound semiconductor is placed in a reaction vessel (12) of which the inner gas is subjected to replacement with a low-vapor-pressure gas (2) whose equilibrium vapor pressure at the melting point of the compound semiconductor is 1 atm or lower. The low-vapor-pressure gas is urged to flow along the... Agent: Griffin & Szipl, PC
20090170297 - Method of fabricating semiconductor device having gate spacer layer with uniform thickness: A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and... Agent: Marshall, Gerstein & Borun LLP
20090170298 - Crystal film fabrication: Processes and machines for producing large area sheets or films of crystalline, polycrystalline, or amorphous material are set forth; the production of such sheets being valuable for the manufacturing of solar photovoltaic cells, flat panel displays and the like. In one embodiment the surface of a rotating cylindrical workpiece (10)... Agent: Adam Alexander Brailove
20090170299 - Forming a metal contact in a semiconductor device: Methods for forming a metal contact in a semiconductor device. In one example embodiment, a method for forming a metal contact in a semiconductor device includes various steps. First, an interlayer insulating film is formed over a silicon substrate. Next, an insulating film is formed over the interlayer insulating film.... Agent: Workman Nydegger 1000 Eagle Gate Tower
20090170300 - Semiconductor element and manufacturing method thereof: The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film 104 is formed by sputtering a Hf metal film 103 on a SiO2 film (or a SiON film) 102 on a Si wafer... Agent: Fitzpatrick Cella Harper & Scinto
20090170301 - Method for fabricating semiconductor device: A semiconductor device is fabricated having a stack gate structure where a first gate electrode, a second gate electrode and a gate hard mask are stacked. The stack gate structure secures a contact open margin while reducing a loss of the gate hard mask during a self-aligned contact (SAC) etching... Agent: Townsend And Townsend And Crew, LLP
20090170302 - Method for manufacturing semiconductor device having vertical transistor: A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on... Agent: Ladas & Parry LLP
20090170303 - Methods for forming quantum dots and forming gate using the quantum dots: Methods for forming a gate using quantum dots are disclosed. More particularly, the present invention relates to a method for forming quantum dots for fabrication of an ultrafine semiconductor device comprising a gate with quantum dots. The present invention is capable of forming quantum dots in uniform sizes and at... Agent: Workman Nydegger 1000 Eagle Gate Tower
20090170304 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is provided, which can reduce the contact resistance of an ohmic electrode to a p-type nitride semiconductor layer and can achieve long-term stable operation. In forming, in an electrode forming step, a p-type ohmic electrode of a metal film by successive lamination of... Agent: Leydig Voit & Mayer, Ltd
20090170305 - Method for improving electromigration lifetime for cu interconnect systems: A method for forming a single damascene and/or dual damascene interconnect structure, comprising: performing front end processing, depositing copper, annealing the copper, performing CMP planarization, performing a post copper CMP clean process, performing a BTA rinse, performing IPA drying process, performing doping during thermal ramp up and performing remaining back... Agent: Texas Instruments Incorporated
20090170306 - Process for filling recessed features in a dielectric substrate: A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than ≦200 nm, a conductive layer being present on at... Agent: Freescale Semiconductor, Inc. Law Department
20090170307 - Method of manufacturing semiconductor device: A metal layer is formed on an upper surface of a resin layer provided to cover a plurality of semiconductor chips at a side on which an internal connecting terminal is disposed and the internal connecting terminal, and the metal layer is pressed to cause the metal layer in a... Agent: Rankin, Hill & Clark LLP
20090170308 - Method for forming metal line of semiconductor device: A method for forming metal lines of a semiconductor device is disclosed. The metal line forming method includes forming plugs by perforating via-holes in an interlayer dielectric layer formed on a semiconductor substrate and burying a conductive material in the via-holes, sequentially forming at least two metal layers on the... Agent: Workman Nydegger 1000 Eagle Gate Tower
20090170309 - Barrier process/structure for transistor trench contact applications: A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration... Agent: Lee & Hayes, PLLC C/o Intellevate, LLC
20090170310 - Method of forming a metal line of a semiconductor device: In a method of forming a metal line of a semiconductor device, a dielectric film is formed on a semiconductor substrate. A plurality of parallel photoresist patterns are formed over the entire structure including the dielectric film. A spacer is formed on sidewalls of the photoresist patterns. The dielectric film... Agent: Townsend And Townsend And Crew, LLP
20090170311 - Method for fabricating contact in semiconductor device: A method for fabricating a contact in a semiconductor device includes forming an insulating film having a contact hole over a bottom film, forming a thin metal film in the exposed portion of the bottom film by supplying a reaction gas containing a metal component to a surface of the... Agent: Marshall, Gerstein & Borun LLP
20090170313 - Method for manufacturing semiconductor device: A semiconductor device and method for manufacturing the same are provided. A dielectric can be formed on a silicon substrate, and a contact hole can be formed in the dielectric. A portion of the silicon substrate can etched through the contact hole.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090170314 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes the steps of: (a) forming a low dielectric constant film over a semiconductor substrate; (b) forming a recess in the low dielectric constant film; (c) after the step (b), sequentially performing the steps of (c1) applying an organic solution to the low... Agent: Mcdermott Will & Emery LLP
20090170315 - Method for forming tungsten plug: A method for forming a tungsten plug is provided. The method can include forming a first tungsten seed layer on an insulating layer having a via hole, forming a second tungsten seed layer on the first tungsten seed layer, and forming a tungsten-buried layer in the via hole. The second... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090170316 - Double patterning with single hard mask: In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to... Agent: RyderIPLaw C/o Cpa Global
20090170323 - Chemical mechanical polishing method and chemical mechanical polishing device: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have... Agent: Dickstein Shapiro LLP
20090170317 - Cmp process for processing sti on two distinct silicon planes: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from... Agent: Texas Instruments Incorporated
20090170320 - Cmp system and method using individually controlled temperature zones: By creating a temperature profile across a polishing pad, a respective temperature profile may be obtained in a substrate to be polished, which may result in a respective varying removal rate across the substrate for a chemically reactive slurry material or for an electro-chemically activated polishing process. Hence, highly sensitive... Agent: Williams, Morgan & Amerson
20090170318 - Method for forming pattern of semiconductor device: A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a first patterning process... Agent: Marshall, Gerstein & Borun LLP
20090170322 - Method for manufacturing semiconductor device including vertical transistor: A method for manufacturing a semiconductor device including a vertical transistor comprises: depositing a n-layered (here, n is an integer ranging from 2 to 6) mask film over a semiconductor substrate; forming a photoresist pattern over the n-layered mask film; etching the mask film with the photoresist pattern as an... Agent: Marshall, Gerstein & Borun LLP
20090170319 - Method of forming an interlayer dielectric material having different removal rates during cmp: By providing an interlayer dielectric material with different removal rates, a desired minimum material height above gate electrode structures of sophisticated transistor devices of the 65 nm technology or 45 nm technology may be obtained. The reduced removal rate above the gate electrode may thus provide enhanced process robustness during... Agent: Williams, Morgan & Amerson
20090170321 - Method of forming isolation layer of semiconductor memory device: A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened... Agent: Marshall, Gerstein & Borun LLP
20090170328 - Method for manufacturing semiconductor device and substrate processing method: The method according to the invention includes the steps of: purging an inside of the processing chamber with gas while applying a thermal impact onto the thin film deposited on the inside of the processing chamber by decreasing the temperature in the processing chamber, so as to forcibly generate a... Agent: Oliff & Berridge, PLC
20090170325 - Method of forming a semiconductor device pattern: In a method of forming patterns of a semiconductor device, first etch mask patterns are formed over a semiconductor substrate. An auxiliary film is formed over the first etch mask patterns to a thickness in which a step corresponding to the first etch mask patterns can be maintained. Second etch... Agent: Townsend And Townsend And Crew, LLP
20090170326 - Method of forming micro pattern of semiconductor device: The present invention relates to a method of forming micro patterns of a semiconductor device. In the method according to an aspect of the present invention, first etch mask patterns having a second pitch, which is twice larger than a first pitch of target patterns, are formed in a column... Agent: Townsend And Townsend And Crew, LLP
20090170327 - Method of manufacturing a semiconductor device: In this method of manufacturing a semiconductor device, the remaining layer of an etching mask layer remains in a predetermined thickness when the stamping face of a nano-stamper is pressed on the surface of the etching mask layer. Therefore, the remaining layer of the etching mask layer functions as a... Agent: Smith, Gambrell & Russell
20090170329 - Photo mask: A photo mask comprises a H-type light-shield pattern. In an exposure process, a photo mask is used to form a STAR (Step Asymmetry Recess) gate region, thereby stably securing a storage node contact region and improving a refresh characteristic of a semiconductor device.... Agent: Townsend And Townsend And Crew, LLP
20090170324 - Reducing adherence in a mems device: In one embodiment, an apparatus for reducing adherence in a micro-electromechanical system (MEMS) device comprises a substrate. A MEMS is disposed outwardly from the substrate. The MEMS comprises structures and corresponding landing pads. Dibs are disposed outwardly from the substrate. Each dib has a surface with depressions. An adherence-reducing material... Agent: Texas Instruments Incorporated
20090170330 - Method of forming a micro pattern of a semiconductor device: In a method of forming micro patterns of a semiconductor device, first etch mask patterns are formed over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. Second etch mask patterns are formed between the auxiliary films formed... Agent: Townsend And Townsend And Crew, LLP
20090170331 - Method of forming a bottle-shaped trench by ion implantation: Disclosed is a method of forming a bottle shaped trench in a substrate which includes forming at least one trench having an upper portion and a lower portion into a semiconductor substrate, the at least one trench having vertical sidewalls that extend to a common bottom wall; implanting ions into... Agent: Scully, Scott, Murphy & Presser, P.C.
20090170332 - Processing gas supplying system and processing gas supplying method: A gas supplying system includes a processing gas supply pipe for supplying a processing gas from a gas cylinder 210 into a processing apparatus and a nonreactive gas supply source 230 for supplying a nonreactive gas into the gas supply pipe. While the system is in operation, the gas supply... Agent: Pearne & Gordon LLP
20090170334 - Copper discoloration prevention following bevel etch process: A method of bevel edge etching a semiconductor substrate having exposed copper surfaces with a fluorine-containing plasma in a bevel etcher in which the semiconductor substrate is supported on a semiconductor substrate support comprises bevel edge etching the semiconductor substrate with the fluorine-containing plasma in the bevel etcher; evacuating the... Agent: Buchanan, Ingersoll & Rooney PC
20090170333 - Shallow trench isolation etch process: Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate... Agent: MoserIPLaw Group / Applied Materials, Inc.
20090170335 - Plasma etching method, plasma etching apparatus, control program and computer-readable storage medium: A plasma etching method for performing an etching process for forming on an insulating film formed on a substrate a hole shape having a ratio of depth to opening width of more than 20. The hole shape is formed on the insulating film by converting processing gas containing at least... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090170336 - Method for forming pattern of semiconductor device: A method for forming a pattern of a semiconductor device of the present invention comprises: forming an underlying layer and a hard mask layer over a semiconductor substrate; forming a sacrificial pattern over the hard mask layer; forming a spacer at both sides of the sacrificial pattern; removing the sacrificial... Agent: Townsend And Townsend And Crew, LLP
20090170337 - Device for processing substrate and method of manufacturing semiconductor device: Provided is a substrate processing apparatus and a method of manufacturing a semiconductor device, which are hard to cause a defect in processing a substrate owing to that a pressure inside a process chamber is not kept constant, and which enable a better processing of a substrate. The substrate processing... Agent: Oliff & Berridge, PLC
20090170338 - Substrate treatment device and manufacturing method of semiconductor device: An object of the invention is to provide a substrate treatment device that can lengthen the maintenance cycle, and prevent any by-product from falling on substrates even if it is accumulated, and a manufacturing method of such a substrate treatment device, and an embodiment of the invention is directed, comprising:... Agent: Mcginn Intellectual Property Law Group, PLLC
20090170339 - Reducing the creation of charge traps at gate dielectrics in mos transistors by performing a hydrogen treatment: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in... Agent: Williams, Morgan & Amerson
20090170340 - Method of forming dielectric films: A method of forming dielectric films including a metal silicate on a silicon substrate comprises a first step of oxidizing a surface layer portion of the silicon substrate and forming a silicon dioxide film; a second step of irradiating ion on the surface of the silicon dioxide film and making... Agent: Fitzpatrick Cella Harper & Scinto
20090170341 - Process for forming dielectric films: A process for forming dielectric films containing at least metal atoms, silicon atoms, and oxygen atoms on a silicon substrate comprises a first step of oxidizing a surface portion of the silicon substrate to form a silicon dioxide film; a second step of forming a metal film on the silicon... Agent: Fitzpatrick Cella Harper & Scinto
20090170342 - Dielectric nanostructure and method for its manufacture: The present invention relates to dielectric nanostructures useful in semiconductor devices and other electronic devices and methods for manufacturing the dielectric nanostructures. The nanostructures generally comprises an array of isolated pillars positioned on a substrate. The methods of the present invention involve using semiconductor technology to manufacture the nanostructures from... Agent: Robert Martin
20090170343 - Method and apparatus for treating a semi-conductor substrate: This invention relates to a method of treating a semiconductor wafer and in particular, but not exclusively, to planarisation. The method consists of depositing a liquid short-chain polymer formed from a silicon containing bas or vapour. Subsequently water and OH are removed and the layer is stabilised.... Agent: Volentine & Whitt PLLC
20090170344 - Method for forming dielectric films: A method for forming dielectric films including metal nitride silicate on a silicon substrate, comprises a first step of depositing a film containing metal and silicon on a silicon substrate in a non-oxidizing atmosphere using a sputtering method; a second step of forming a film containing nitrogen, metal and silicon... Agent: Fitzpatrick Cella Harper & Scinto
20090170345 - Method for manufacturing semiconductor device and substrate processing apparatus: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the... Agent: Oliff & Berridge, PLC
20090170346 - Low temperature polysilicon oxide process for high-k dielectric/metal gate stack: A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum... Agent: Texas Instruments IncorporatedPrevious industry: Chemistry: analytical and immunological testing
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