|Semiconductor device manufacturing: process patents - Monitor Patents|
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Semiconductor device manufacturing: process June invention type 06/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 06/25/2009 > patent applications in patent subcategories. invention type
20090162947 - Aerodynamic shapes for wafer structures to reduce damage caused by cleaning processes: Wafer structures and associated methods of fabrication are described. The wafer structures are fabricated to have aerodynamic shapes. Even if the structures on the wafer are fragile, the aerodynamic shapes of the structures create less resistance to a fluid flow of a cleaning process, and are less likely to be... Agent: Duft Bornsen & Fishman, LLP
20090162948 - Method for eliminating defects from semiconductor materials: Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvins for a period of ninety-six hours. At these low temperatures, alloys such as GaAs,... Agent: K&l Gates LLP
20090162949 - Method of manufacturing organic light-emitting device: The present invention provides a method of manufacturing an organic light-emitting device which is applicable to a large-screen display device. The method includes the steps of: forming, over a drive substrate, an element region including a drive transistor, and an organic electroluminescence element in which, an anode, an organic layer... Agent: Sonnenschein Nath & Rosenthal LLP
20090162950 - Dry etching equipment and method for producing semiconductor device: A dry etching equipment includes a topography simulator and a control section. The topography simulator controls an amount of deposition species incident upon a sidewall to be processed in accordance with a wafer opening ratio and a solid angle of a local pattern, the deposition amount being represented by a... Agent: Robert J. Depke Lewis T. Steadman
20090162951 - Enhanced endpoint detection in non-volatile memory fabrication processes: A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge... Agent: Vierra Magen/sandisk Corporation
20090162952 - Apparatus and method for controlling edge performance in an inductively coupled plasma chamber: The present invention generally provides methods and apparatus for controlling edge performance during process. One embodiment of the present invention provides an apparatus comprising a chamber body defining a process volume, a gas inlet configured to flow a process gas into the process volume, and a supporting pedestal disposed in... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090162953 - Predicting dose repeatability in an ion implantation: An approach for predicting dose repeatability in an ion implantation is described. In one embodiment, an ion source is tuned to generate an ion beam with desired beam current. Beam current measurements are obtained from the tuned ion beam. The dose repeatability is predicted for the ion implantation as a... Agent: Scott Faber, Esq. Varian Semiconductor Equipment Associates, Inc
20090162954 - Ac impedance spectroscopy testing of electrical parametric structures: Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be... Agent: Texas Instruments Incorporated
20090162955 - Led device with improved life performance: A light-emitting diode with an improved service life is provided. The diode is formed from a transparent outer shell that contains a heat-resistant encapsulant at least partially surrounding a light-emitting diode clip. The first encapsulant is compressed between the outer shell and a second encapsulant when it is sealed into... Agent: Kathy Manke Avago Technologies Limited
20090162956 - Led fabrication method employing a water washing process: An LED fabrication method for fabricating LEDs comprises: covering all the P-contacts and N-contacts on a wafer with a hydrophilic resin mask layer, packaging the wafer with an organic or inorganic polymer compound containing a yellow fluorescent powder (or a mixture of red and green fluorescent powders), employing a water... Agent: Pai Patent & Trademark Law Firm
20090162957 - Mold for forming molding member and method of manufacturing led package using the same: Provided is a method of manufacturing a light emitting diode (LED) package, the method including the steps of: preparing a package substrate having an LED chip mounted thereon; preparing a mold which has a convex portion, a plane portion extending outward from the convex portion, and a projecting portion formed... Agent: Staas & Halsey LLP
20090162958 - Array substrate, method of manufacturing the same and liquid crystal display apparatus having the same: An array substrate includes a transparent substrate, an organic insulation layer, a pixel electrode, a reflective layer, a light blocking pattern and a switching part. The transparent substrate includes a reflective window that reflects an ambient light and a transmissive window that transmits an artificial light. The organic insulation layer... Agent: Cantor Colburn, LLP
20090162959 - Method for fabricating light emitting diode element: The present invention discloses a method for fabricating a light emitting diode element, which incorporates an epitaxial process with an etching process to etch LED epitaxial layers bottom up and form side-protrudent structures, whereby the LED epitaxial layers have non-rectangular inclines, which can solve the problem of total reflection and... Agent: Joe Mckinney Muncy
20090162960 - Method for manufacturing high efficiency light-emitting diodes: A method for manufacturing a light-emitting device comprising the steps of cutting a light-emitting unit by a laser beam, and cleaning the light-emitting unit by an acid solution to remove by-products resulted from the laser cutting.... Agent: Bacon & Thomas, PLLC
20090162961 - Active matrix device with photo sensor: An active matrix pixel device is provided, for example an electroluminescent display device, the device comprising circuitry supported by a substrate and including a polysilicon TFT (10) and an amorphous silicon thin film PIN diode (12). Polysilicon islands are formed before an amorphous silicon layer is deposited for the PIN... Agent: Philips Intellectual Property & Standards
20090162962 - Method of manufacturing nitride semiconductor laser: The invention provides a high-reliability nitride semiconductor laser that reduces the stress of a nitride dielectric film formed on a resonator's end face, thus reducing possible damage to the resonator's end face, which may occur during the formation of the nitride dielectric film. A method of manufacturing a nitride semiconductor... Agent: Leydig Voit & Mayer, Ltd
20090162963 - Gallium nitride-based device and method: A gallium nitride-based device has a first GaN layer and a type II quantum well active region over the GaN layer. The type II quantum well active region comprises at least one InGaN layer and at least one GaNAs layer comprising 1.5 to 8% As concentration. The type II quantum... Agent: Saul Ewing LLP (harrisburg) Attn: Patent Docket Clerk
20090162964 - Methods of forming double pinned photodiodes: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first... Agent: Dickstein Shapiro LLP
20090162965 - Optical die-down quad flat non-leaded package: An optical sensor package that includes an optical sensor die is mounted by flip chip interconnect onto a lead frame in a “die-down” orientation, that is, with the active side of the optical sensor die facing the lead frame. An opening is provided in the lead frame die paddle (pad),... Agent: Robert D. Atkins
20090162966 - Structure and method of formation of a solar cell: A semiconductor device is formed on a low cost substrate 312 onto which is deposited a metal film 314 that serves as an intermediate bonding layer with a transferred film 324 of semiconducting material from a bulk semiconductor substrate 322. The metal film forms an intermetallic compound such as a... Agent: Fortkort & Houston P.C.
20090162967 - Method for forming light-transmitting regions: A method for forming a light-transmitting region comprises providing a support feature. A sacrificial layer is formed over a portion of the support feature, wherein the sacrificial layer comprises an energy-induced swelling material. A light-blocking layer is conformably formed over the support feature to cover the sacrificial layer and the... Agent: Joe Mckinney Muncy
20090162968 - Method and apparatus for producing a semitransparent photovoltaic module: For producing a semitransparent photovoltaic module (1), the transparent substrate (2) is coated with a transparent front electrode layer (3), a semiconductor layer (4) and a metallic back electrode layer (5) and then partial areas (9) of the semiconductor layer (4) and of the back electrode layer (5) are removed.... Agent: Flynn Thiel Boutell & Tanis, P.C.
20090162969 - Method and apparatus to form solar cell absorber layers with planar surface: A method and a system are provided for forming planar absorber layers or structures by planarizing and reacting precursor layers in a reactor. A precursor structure is first formed over the front surface of a foil substrate and then planarized through application of pressure by a smooth surface while heated... Agent: Pillsbury Winthrop Shaw Pittman LLP
20090162970 - Material modification in solar cell fabrication with ion doping: An approach for material modification in solar cell fabrication with ion doping is described. In one embodiment, there is a method of forming a thin-film solar cell. In this embodiment, a substrate is provided and a thin-film layer is deposited on the substrate. The thin-film solar cell layer is exposed... Agent: Scott Faber, Esq. Varian Semiconductor Equipment Associates, Inc
20090162971 - Photo diode and related method for fabrication: A method for fabricating a photo diode first involves providing a substrate. A doping area is then formed on the substrate. Afterwards, a dielectric layer, and a first poly-silicon layer are formed on the substrate. An opening is then formed to expose a surface of the doping area. A second... Agent: North America Intellectual Property Corporation
20090162972 - Metallization contact structures and methods for forming multiple-layer electrode structures for silicon solar cells: Metallization contact structures and methods for forming a multiple-layer electrode structure on a solar cell include depositing a conductive contact layer on a semiconductor substrate and depositing a metal bearing ink onto a portion of the conductive contact layer, wherein the exposed portions of the conductive contact layer are adjacent... Agent: Oliff & Berridge, PLC
20090162973 - Germanium precursors for gst film deposition: A method for depositing a germanium containing film on a substrate is disclosed. A reactor, and at least one substrate disposed in the reactor, are provided. A germanium containing precursor is provided and introduced into the reactor, which is maintained at a temperature of at least 100° C. Germanium is... Agent: Air Liquide Intellectual Property
20090162974 - Semiconductor package board using a metal base: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within... Agent: Sughrue Mion, PLLC
20090162975 - Method of forming a wafer level package: A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern... Agent: Tessera Lerner David Et Al.
20090162976 - Method of manufacturing pins of miniaturization chip module: A method of manufacturing a miniaturization chip module includes steps of providing a chip module having a substrate, wherein the substrate has a plurality of bonding pads spaced on a rear surface of substrate; providing a lead frame including a plurality of spaced metallic studs, wherein the metallic studs are... Agent: Rosenberg, Klein & Lee
20090162977 - Non-volatile memory fabrication and isolation for composite charge storage structures: Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed... Agent: Vierra Magen/sandisk Corporation
20090162978 - Method of forming a sige diac esd protection structure: A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of... Agent: Law Office Of Mark C. Pickering
20090162979 - Thyristor device with carbon lifetime adjustment implant and its method of fabrication: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal... Agent: Walter D. Fields Fields Ip, P.s.
20090162980 - Method of manufacturing semiconductor device: An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus, the oxide... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090162981 - Thin film transistor and method of manufacturing the same: A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a substrate; a buffer layer formed on the substrate; a source and a drain spaced apart from each other on the buffer layer; a channel layer formed on the buffer layer to... Agent: Buchanan, Ingersoll & Rooney PC
20090162982 - Array substrate, display device having the same and method of manufacturing the same: An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer.... Agent: H.c. Park & Associates, PLC
20090162983 - Method of fabricating schottky barrier transistor: (b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a... Agent: Harness, Dickey & Pierce, P.L.C
20090162984 - Method for manufacturing semiconductor device: Disclosed are methods for manufacturing a semiconductor device. One method includes the steps of forming a gate electrode on a semiconductor substrate, sequentially forming a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate electrode, dry-etching the second oxide layer, wet-etching... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090162985 - Method of fabricating semiconductor device: Methods of fabricating a semiconductor device are provided. An insulating layer can be formed on a semiconductor substrate, a sacrificial layer can be formed on the insulating layer, and a trench can be formed in the sacrificial layer. A first gate material layer can be formed on the sacrificial layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090162986 - Copolymers, polymer resin composition for buffer layer method of forming a pattern using the same and method of manufacturing a capacitor using the same: wherein the variables L, M and N represent the relative molar fractions of the monomers and satisfy the expressions 0<L≦0.8; 0<M≦0.2; 0<L≦0.35; and L+M+N=1; and, wherein R1, R2 and R3 are independently selected from C1-C6 alkyls and derivatives thereof. The invention is also directed to polymer compositions that, when used... Agent: Harness, Dickey & Pierce, P.L.C
20090162987 - Method for fabricating mim structure capacitor: A method for fabricating a metal/insulator/metal (MIM) structure capacitor includes forming a nitride film that is an insulating layer on a bottom electrode metal layer; forming titanium/titanium nitride (Ti/TiN) that is a top electrode metal layer on the nitride film; coating photo-resist on the top electrode metal layer and patterning... Agent: Sherr & Vaughn, PLLC
20090162988 - Method of forming low capacitance esd device and structure therefor: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700
20090162989 - Methods of manufacturing a semiconductor device using a layer suspended across a trench: In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and... Agent: Myers Bigel Sibley & Sajovec
20090162990 - Method for manufacturing a semiconductor device capable of preventing the decrease of the width of an active region: A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially... Agent: Ladas & Parry LLP
20090162992 - Method for manufacturing semiconductor device: There are provided a semiconductor device having a structure which can realize not only suppression of a punch-through current but also reuse of a silicon wafer used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. A semiconductor film into which an impurity... Agent: Eric Robinson
20090162993 - Method for fabricating semiconductor device: An object is to provide a technology capable of improving a manufacturing yield of semiconductor devices by preventing scattering of irregular-shaped scraps formed at the time of dicing. To achieve the above object, for dicing lines, by which an irregular-shaped outer periphery may possibly be cut off, among a plurality... Agent: Miles & Stockbridge PC
20090162994 - Laser processing method: A laser processing method which can securely prevent particles from attaching to chips obtained by cutting a planar object is provided. When applying a stress to an object to be processed 1 through an expandable tape 23, forming materials of the object 1 (the object 1 formed with molten processed... Agent: Drinker Biddle & Reath (dc)
20090162995 - Semiconductor device manufacturing method and semiconductor manufacturing apparatus: By hydrogen-terminating a semiconductor surface using a solution containing HF2− ions and an oxidant, the hydrogen termination can be quickly carried out. In this case, the semiconductor surface is silicon having a (111) surface, a (110) surface, or a (551) surface.... Agent: Foley And Lardner LLP Suite 500
20090162996 - Removal of surface dopants from a substrate: A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma,... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090162998 - Methods of manufacturing memory units, and methods of manufacturing semiconductor devices: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers... Agent: Myers Bigel Sibley & Sajovec
20090162997 - Thin diamond like coating for semiconductor processing equipment: Accordingly, systems and methods of thin diamond like coatings for semiconductor processing equipment. A semiconductor substrate processing system includes an enclosure for containing a semiconductor processing gas. The enclosure has an interior surface that is at least partially coated with a diamond-like Carbon coating to a desired thickness that is... Agent: Murabito Hao & Barnes LLP
20090162999 - Method of growing nitride semiconductor material: A method of growing nitride semiconductor material and particularly a method of growing Indium nitride is disclosed can increase surface flatness of a nitride semiconductor material and decrease density of V-defects therein. Further, the method can increase light emission efficiency of a quantum well or quantum dots of the produced... Agent: Hdls Patent & Trademark Services
20090163000 - Method for fabricating vertical channel transistor in a semiconductor device: A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed.... Agent: Lowe Hauptman Ham & Berner, LLP
20090163001 - Separate injection of reactive species in selective formation of films: Methods and apparatuses for selective epitaxial formation of films separately inject reactive species into a CVD chamber. The methods are particularly useful for selective deposition using volatile combinations of precursors and etchants. Formation processes include simultaneous supply of precursors and etchants for selective deposition, or sequential supply for cyclical blanket... Agent: Knobbe, Martens, Olson & Bear LLP
20090163002 - Method of forming p-type compound semiconductor layer: A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied... Agent: H.c. Park & Associates, PLC
20090163003 - Manufacturing method of self-separation layer: A manufacturing method of a self separation layer includes the steps of: forming a plurality of convex portions on a substrate; growing a main material layer on the convex portions; and separating the main material layer from the substrate.... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090163004 - Method of fabricating semiconductor device: Methods of fabricating a semiconductor device are provided. A photoresist pattern can be formed on an implantation target layer, and conductive impurities can be implanted into the implantation target layer using the photoresist pattern as a mask. A portion of the photoresist pattern can be removed, conductive impurities implanted in... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090163005 - Schottky barrier source/drain n-mosfet using ytterbium silicide: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium... Agent: Saile Ackerman LLC
20090163006 - Method for fabricating vertical channel transistor: A method for fabricating a vertical channel transistor includes forming a structure including a plurality of trimmed pillar patterns, forming a conductive layer for a gate electrode including a seam over a resultant structure with the pillar patterns, performing an etch-back process until the seam is exposed, and forming a... Agent: Lowe Hauptman Ham & Berner, LLP
20090163007 - Method for manufacturing semiconductor device: A semiconductor device is manufactured suppressing generation of “vacancy-oxygen complex defects”. A general etching treatment is done using a general plasma gas including HBr, Cl2 and O2 till a time point when at least a part of a gate oxide film is exposed during a dry-etching step. After this time... Agent: Sughrue Mion, PLLC
20090163008 - Lithographically space-defined charge storage regions in non-volatile memory: Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between... Agent: Vierra Magen/sandisk Corporation
20090163009 - Composite charge storage structure formation in non-volatile memory using etch stop technologies: Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length... Agent: Vierra Magen/sandisk Corporation
20090163010 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a tungsten electrode over a substrate, performing a plasma oxidation process to form a capping layer on the surfaces of the gate patterns, forming an etch barrier layer over the substrate where the capping layer... Agent: Townsend And Townsend And Crew, LLP
20090163011 - Mask layout and method for forming vertical channel transistor in semiconductor device using the same: A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has... Agent: Lowe Hauptman Ham & Berner, LLP
20090163014 - Method for fabricating non-volatile memory device with charge trapping layer: A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to... Agent: Marshall, Gerstein & Borun LLP
20090163013 - Method for forming gate of non-volatile memory device: Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region... Agent: Marshall, Gerstein & Borun LLP
20090163015 - Method of fabricating flash memory device: The present invention relates to a method of fabricating a flash memory device. According to a method of fabricating a flash memory device in accordance with an aspect of the present invention, a semiconductor substrate over which a tunnel insulating layer and a first conductive layer are formed is provided.... Agent: Marshall, Gerstein & Borun LLP
20090163012 - Method of forming high-dielectric constant films for semiconductor devices: A method is provided for forming high dielectric constant (high-k) films for semiconductor devices. According to one embodiment, a metal-carbon-oxygen high-k film is deposited by alternately and sequentially exposing a substrate to a metal-carbon precursor and near saturation exposure level of an oxidation source containing ozone. The method is capable... Agent: Tokyo Electron U.s. Holdings, Inc.
20090163016 - Method of fabricating a semiconductor device including metal gate electrode and electronic fuse: A method of fabricating a semiconductor device including a metal gate electrode and an electronic fuse. The method may include forming a gate dielectric layer on a semiconductor substrate, forming a first metal layer on the gate dielectric layer, forming a portion of the first metal layer in a first... Agent: Marger Johnson & Mccollom, P.C.
20090163017 - Method for fabricating semiconductor device with vertical channel transistor: A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding... Agent: Lowe Hauptman Ham & Berner, LLP
20090163018 - Method to prevent alloy formation when forming layered metal oxides by metal oxidation: The present method of fabricating a resistive memory device includes the steps of providing a first electrode, oxidizing a portion of the first electrode with an oxidizing agent, providing a metal body on the oxidized portion of the first electrode, oxidizing the entire metal body with an oxidizing agent, and... Agent: Paul J. Winters
20090163019 - Forming robust solder interconnect structures by reducing effects of seed layer underetching: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier... Agent: Cantor Colburn LLP - IBM Fishkill
20090163020 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. A first interlayer dielectric film can be formed on a semiconductor substrate, and a metal wire can be formed on the first interlayer dielectric film. A second interlayer dielectric film can be formed on the first interlayer dielectric film, including the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090163021 - Method of fabricating semiconductor device: Provided is a method of fabricating a semiconductor device with a dual damascene pattern. According to the method, a diffusion barrier layer, dielectric, a capping layer, and an organic bottom anti-reflection coating (BARC) are sequentially formed on a substrate where a metal interconnection is formed. A photoresist pattern on the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20090163022 - Tft array panel: Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed... Agent: Cantor Colburn, LLP
20090163023 - Phase change memory and method of fabricating the same: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a... Agent: Lee & Morse, P.C.
20090163024 - Methods of depositing a ruthenium film: A method of depositing includes: loading a substrate into a reactor; and conducting a plurality of atomic layer deposition cycles on the substrate in the reactor. At least one of the cycles includes steps of: supplying a ruthenium precursor to the reactor; supplying a purge gas to the reactor; and... Agent: Knobbe Martens Olson & Bear LLP
20090163025 - Methods for forming all tungsten contacts and lines: Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion... Agent: Weaver Austin Villeneuve & Sampson LLP - Novl Attn.: Novellus Systems, Inc.
20090163026 - Immersion lithography wafer edge bead removal for wafer and scanner defect prevention: A method of performing a single step/single solvent edge bead removal (EBR) process on a photolithography layer stack including a photoresist layer and a top coat layer using propylene glycol monomethyl ether acetate (PGMEA) or a mixture of PGMEA and gamma-butyrolactone (GBL) is disclosed. The single step/single solvent EBR process... Agent: Texas Instruments Incorporated
20090163027 - Method for fabricating vertical channel transistor in semiconductor device: A method for fabricating a vertical channel transistor in a semiconductor device includes forming a plurality of pillars arranged in a first direction and a second direction crossing the first direction over a substrate, wherein each of the pillars includes a hard mask pattern thereon, forming a bit line region... Agent: Lowe Hauptman Ham & Berner, LLP
20090163028 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming an organic bottom anti-reflective coating over an etch target layer, forming a photoresist pattern over the organic bottom anti-reflective coating, and etching the organic bottom anti-reflective coating using a sulfur-containing gas.... Agent: Townsend And Townsend And Crew, LLP
20090163029 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device has forming a first nitride layer over a substrate, forming a first oxide layer on the first nitride layer, forming a second nitride layer on the first oxide layer, forming a photoresist layer over the second nitride layer, forming a opening in the... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090163030 - Semiconductor device manufacturing method: A first silicon containing film, an organic material film, a second silicon containing film are formed. The second silicon containing film is patterned to have a narrow width pattern and a wide width pattern. The organic material film is patterned to have a narrow width pattern and a wide width... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090163031 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a hard mask pattern and a spacer at both sides of the hard mask pattern. The method also includes forming a spacer pattern, so that the spacer remains in one direction to form a spacer pattern, forming a photoresist pattern having... Agent: Marshall, Gerstein & Borun LLP
20090163032 - Method of forming a dual damascene pattern of a semiconductor device: In a method of forming a dual damascene pattern of a semiconductor device, horns that occur while forming a trench constituting the dual damascene pattern are removed in an intermediate process of forming the trench. Thus, the source of particles, which occur due to the horns in a cleaning process... Agent: Townsend And Townsend And Crew, LLP
20090163033 - Methods for extending chamber component life time: Methods for extending service life of chamber components for semiconductor processing are provided. In one embodiment, the method includes maintaining a substrate support assembly disposed in a processing chamber at a first temperature, performing a first plasma process on a first substrate in the processing chamber while the substrate support... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090163034 - Composite showerhead electrode assembly for a plasma processing apparatus: A showerhead electrode for a plasma processing apparatus includes an elastomeric sheet adhesive bond between mating surfaces of an electrode and a backing member to accommodate stresses generated during temperature cycling due to mismatch in coefficients of thermal expansion. The elastomeric sheet comprises a thermally conductive silicone adhesive able to... Agent: Buchanan, Ingersoll & Rooney PC
20090163035 - Etch with high etch rate resist mask: A method for etching features into an etch layer is provided. A patterned mask is formed over the etch layer, wherein the patterned mask is of a high etch rate photoresist material, wherein the patterned mask has patterned mask features. A protective layer is deposited on the patterned mask of... Agent: Beyer Law Group LLP
20090163036 - Substrate treating method: A substrate processing method includes the step of forming an oxide film by oxidizing a silicon substrate surface and the step of nitriding the oxide film to form an oxynitride film, wherein there is provided a step of purging oxygen after the oxidizing step but before said nitriding step from... Agent: Crowell & Moring LLP Intellectual Property Group
20090163037 - Manufacturing method of semiconductor device and substrate processing apparatus: Provided is a substrate processing apparatus which is capable of suppressing the erosion of a metal member installed inside the processing chamber. The substrate processing apparatus includes: a processing chamber for performing a processing of forming a high dielectric constant film on a substrate; a processing gas supply system for... Agent: Mattingly & Malur, P.C.
20090163039 - Composition for forming insulating film and method for fabricating semiconductor device: A method for fabricating a semiconductor device utilizing the step of forming a first insulating film of a porous material over a substrate; the step of forming on the first insulating film a second insulating film containing a silicon compound containing Si—CH3 bonds by 30-90%, and the step of irradiating... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090163038 - Heat treatment method, heat treatment apparatus and substrate processing apparatus: Disclosed is a heat treatment unit 4 serving as a heat treatment apparatus, which includes a chamber 42 for containing a wafer W on which a low dielectric constant interlayer insulating film is formed, a formic acid supply device 44 for supplying gaseous formic acid into the chamber 42, and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090163040 - Substrate processing apparatus and manufacturing method of semiconductor device: A substrate processing apparatus, including: a reaction container in which a substrate is processed; a seal cap, brought into contact with one end in an opening side of the reaction container via a first sealing member and a second sealing member so as to seal the opening of the reaction... Agent: Oliff & Berridge, PLC
20090163041 - Low wet etch rate silicon nitride film: The present invention pertains to methods of depositing low wet etch rate silicon nitride films on substrates using high-density plasma chemical vapor deposition techniques at substrate temperatures below 600° C. The method additionally involves the maintenance of a relatively high ratio of nitrogen to silicon in the plasma and a... Agent: Townsend And Townsend And Crew LLP
20090163042 - Thermal reactor with improved gas flow distribution: Embodiments of the present invention provide apparatus and method for improving gas distribution during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is... Agent: Patterson & Sheridan, LLP - - Appm/tx06/18/2009 > patent applications in patent subcategories. invention type
20090155931 - Ferroelectric layer with domains stabilized by strain: The present invention describes a method including: providing a substrate; forming an underlying layer over the substrate; heating the substrate; forming a ferroelectric layer over the underlying layer, the ferroelectric layer having a thickness below a critical thickness, the underlying layer having a smaller lattice constant than the ferroelectric layer;... Agent: Intel Corporation C/o Cpa Global
20090155932 - Method of manufacturing magnetic field detector: Disclosed is a method of manufacturing a magnetic field detector having various structures that can be used as a high-density magnetic biosensor. An embodiment of the invention provides a method of manufacturing a magnetic field detector including a magnetoresistive element using a magnetic bead detecting thin film. The method includes:... Agent: Ladas & Parry LLP
20090155935 - Back side wafer dicing: Systems and methods for scribing a semiconductor wafer with reduced or no damage or debris to or on individual integrated circuits caused by the scribing process. The semiconductor wafer is scribed from a back side thereof. In one embodiment, the back side of the wafer is scribed following a back... Agent: Electro Scientific Industries/stoel Rives, LLP
20090155934 - Deposition apparatus and deposition method: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing heat from the processing object to generate a heat... Agent: Frishauf, Holtz, Goodman & Chick, PC
20090155933 - Manufacturing method of display device: To suppress the occurrence of image quality irregularities in a liquid crystal display device having a TFT substrate which is manufactured by performing steps a plurality of times in such a manner that one region is divided into a plurality of exposure regions, and the plurality of exposure regions is... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090155936 - Modular flow cell and adjustment system: A combinatorial processing system having modular dispense heads is provided. The modular dispense heads are disposed on a rail system enabling an adjustable pitch of the modular dispense heads for the combinatorial processing. The modular dispense heads are configured so that sections of the modular dispense heads are detachable in... Agent: Martine Penilla Gencarella, LLP
20090155937 - Method for packaging led device: A method for packaging LED device comprises following steps: (1) A substrate with a cavity is provided; (2) A electrode layer is formed and located on the cavity and the surface of the substrate; (3) A opening through the cavity is formed, whereby a anode and a cathode are separated... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090155938 - Light emitting diode package with diffuser and method of manufacturing the same: The invention relates to an LED package for facilitating color mixing using a diffuser and a manufacturing method of the same. The LED package includes a substrate with an electrode formed thereon, and an LED chip mounted on the substrate. The LED package also includes an encapsulant applied around the... Agent: Mcdermott Will & Emery LLP
20090155939 - Method of isolating semiconductor laser diodes: Provided is a method of isolating semiconductor laser diodes (LDs), the method including the steps of: preparing a substrate; forming a plurality of semiconductor LDs on the substrate, each semiconductor LD including an n-type semiconductor layer, an active layer, a p-type semiconductor layer, an n-electrode, a ridge portion, and a... Agent: Mcdermott Will & Emery LLP
20090155942 - Hybrid metal bonded vertical cavity surface emitting laser and fabricating method thereof: Provided is a method of fabricating a vertical cavity surface emitting laser among semiconductor optical devices, comprising: bonding a dielectric mirror layer to an epi-structure having a mirror layer and an active layer; bonding these on a new substrate using a metal bonded method; removing the existing substrate; and fabricating... Agent: Ladas & Parry LLP
20090155941 - Light emitting device and method of manufacturing method thereof and thin film forming apparatus: A method of manufacturing a light emitting device of upward emission type and a thin film forming apparatus used in the method are provided. A plurality of film forming chambers are connected to a first transferring chamber. The plural film forming chambers include a metal material evaporation chamber, an EL... Agent: Fish & Richardson P.C.
20090155943 - Luminescent ceramic element for a light emitting device: A semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is attached to a compound substrate including a host which provides mechanical support to the device and a ceramic layer including a luminescent material. In some embodiments the compound substrate includes a crystalline... Agent: Philips Intellectual Property & Standards
20090155940 - Method of manufacturing thin film transistor and method of manufacturing organic light emitting display having thin film transistor: A method of manufacturing a thin film transistor having a compound semiconductor with oxygen as a semiconductor layer and a method of manufacturing an organic light emitting display having the thin film transistor include: forming a gate electrode on an insulating substrate; forming a gate insulating layer on the gate... Agent: Stein Mcewen, LLP
20090155944 - Surface emitting laser device and production method: A surface emitting laser device is disclosed that is able to selectively add a sufficiently large loss to a high order transverse mode so as to efficiently suppress a high order transverse mode oscillation and to oscillate at high output in a single fundamental transverse mode. The surface emitting laser... Agent: Dickstein Shapiro LLP
20090155945 - Method of manufacturing substrate for forming device, and method of manufacturing nitride-based semiconductor laser diode: Provided is a method of manufacturing a semiconductor laser diode. The method includes the steps of: preparing a GaN substrate having an a-plane or m-plane GaN layer formed thereon; forming a plurality of laser diode structures on the GaN layer; etching the GaN substrate such that a cutting reference line... Agent: Mcdermott Will & Emery LLP
20090155946 - Method of varying transmittance of transparent conductive layer, flat panel display device and manufacturing method thereof: A method of varying a transmittance of a transparent conductive film includes forming the transparent conductive film on a substrate and injecting a high energy source into the transparent conductive film to vary the transmittance of the transparent conductive film.... Agent: Stein Mcewen, LLP
20090155947 - Method of growing semi-polar nitride single crystal thin film and method of manufacturing nitride semiconductor light emitting diode using the same: A method of growing a semi-polar nitride single crystal thin film. The method includes forming a semi-polar nitride single crystal base layer on an m-plane hexagonal system single crystal substrate, forming a dielectric pattern layer on the semi-polar nitride single crystal base layer, and growing the semi-polar nitride single crystal... Agent: Mcdermott Will & Emery LLP
20090155948 - Methods for manufacturing cmos compatible bio-sensors: A manufacture method for CMOS sensor, which comprise of steps such as: forming protection layer on a substrate having multiple device structural layers, then using first photo-resist layer as mask for etching to form patterned molecular sensing layer, then forming third photo resist layer and etching protection layer and substrate... Agent: Birch Stewart Kolasch & Birch
20090155949 - Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to... Agent: Dickstein Shapiro LLP
20090155950 - Cmos image sensor and method for fabricating the same: A method for fabricating a CMOS image sensor includes sequentially forming an insulating film, a metal pad and a first passivation film over a semiconductor substrate including photodiodes, forming a planarization layer over the first passivation film, forming color filter layers over the planarization layer, forming an overcoating layer over... Agent: Sherr & Vaughn, PLLC
20090155951 - Exponentially doped layers in inverted metamorphic multijunction solar cells: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell, including providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the... Agent: Emcore Corporation
20090155952 - Exponentially doped layers in inverted metamorphic multijunction solar cells: A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell, including providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the... Agent: Emcore Corporation
20090155953 - Semiconductor device fabricating method and fabricating apparatus: Respective attracting openings of a bonding head are disposed so as to avoid joining regions at which bump electrodes (obverse electrodes) of a semiconductor chip are joined with bump electrodes of a package substrate. Bump electrodes (reverse electrodes) that are connected to the bump electrodes are provided at a reverse... Agent: Rabin & Berdo, PC
20090155954 - Thermal enhanced low profile package structure and method for fabricating the same: A thermal enhanced low profile package structure and a method for fabricating the same are provided. The package structure typically includes a metallization layer with an electronic component thereon which is between two provided dielectric layers. The metallization layer as well as the electronic component is embedded and packaged while... Agent: Volpe And Koenig, P.C.
20090155955 - Thermal mechanical flip chip die bonding: A thermal mechanical process for bonding a flip chip die to a substrate. The flip chip die includes a plurality of copper pillar bumps, each copper pillar bump of the plurality of copper pillar bumps having a copper portion attached to the die and a bonding cap attached to the... Agent: Lowrie, Lando & Anastasi, LLP S2059
20090155957 - Multi-die wafer level packaging: A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically... Agent: Slater & Matsil, L.L.P.
20090155956 - Semiconductor device: A semiconductor device and method. One embodiment provides an encapsulation plate defining a first main surface and a second main surface opposite to the first main surface. The encapsulation plate includes multiple semiconductor chips. An electrically conductive layer is applied to the first and second main surface of the encapsulation... Agent: Dicke, Billig & Czaja
20090155958 - Robust die bonding process for led dies: Systems and methods are provided to mitigate excess die attachment material accrual, and parasitic conductive paths formed thereby. A die attachment material (e.g., solder) is melted using a combination of localized heat sources and ultrasonic energy. The heat sources bring the die attachment material close to its melting point, which... Agent: Fay Sharpe LLP
20090155959 - Semiconductor device and method of forming integrated passive device module: A method of manufacturing a semiconductor device includes providing a substrate with an insulation layer disposed on a top surface of the substrate, forming a passive device over the top surface of the substrate, removing the substrate, depositing an insulating polymer film layer over the insulation layer, and depositing a... Agent: Quarles & Brady LLP
20090155960 - Integrated circuit package system with offset stacking and anti-flash structure: An integrated circuit package system includes: mounting a device structure in an offset location over a carrier with the device structure having a bond pad and a contact pad; connecting an electrical interconnect between the bond pad and the carrier; forming an anti-flash structure over the device structure with the... Agent: Law Offices Of Mikio Ishimaru
20090155961 - Integrated circuit package system with package integration: An integrated circuit package system comprising: providing a base substrate; attaching a base integrated circuit die over the base substrate; forming a support over the base substrate near only one edge of the base substrate; and attaching a stack substrate over the support and the base integrated circuit die.... Agent: Law Offices Of Mikio Ishimaru
20090155962 - Method for fabricating pitch-doubling pillar structures: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a... Agent: Sandisk Corporation C/o Foley & Lardner LLP
20090155963 - Forming thin film transistors using ablative films: An ablative film arranged in a stack having a flexible substrate disposed in the stack; an active layer, disposed in the stack, including at least a semiconductor material; and at least one ablative layer, disposed in the stack over the active layer, that is removable by image wise exposure to... Agent: Frank Pincelli Patent Legal Staff
20090155965 - Method of fabricating a non-floating body device with enhanced performance: Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions... Agent: Haynes And Boone, LLPIPSection
20090155964 - Methods for fabricating an electronic device: A method for fabricating an electronic device is provided. The method for fabricating the electrical device comprises providing a substrate. A patterned first self-assembled monolayer (SAM) and an adjacent patterned second SAM are formed on the substrate, wherein the patterned first SAM has a higher affinity then that of the... Agent: Quintero Law Office, PC
20090155966 - Dram with nanofin transistors: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a... Agent: Schwegman, Lundberg & Woessner/micron
20090155968 - Method of forming a dielectric layer pattern and method of manufacturing a non-volatile memory device using the same: In a method of forming a dielectric layer pattern, lower patterns are formed on a substrate. A first dielectric layer is formed on sidewalls and upper surfaces of the lower patterns and a surface of the substrate. A mask pattern is formed on the first dielectric layer to partially expose... Agent: Myers Bigel Sibley & Sajovec
20090155967 - Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the... Agent: Vierra Magen/sandisk Corporation
20090155969 - Protection of sige during etch and clean operations: A method of making a semiconductor device includes forming a transistor structure having one of an embedded epitaxial stressed material in a source and drain region and a stressed channel and well, subjecting the transistor structure to plasma oxidation, and removing spacer material from the transistor structure.... Agent: Greenblum & Bernstein, P.L.C
20090155970 - Enhanced multi-bit non-volatile memory device with resonant tunnel barrier: A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or LaAlO3. A charge trapping layer is formed over the tunnel barrier. A high-k charge blocking layer is formed over the charge trapping layer. A control... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20090155971 - Method of manufacturing a semiconductor device: In a semiconductor device and a method of manufacturing the same, a conductive structure is formed on an active region defined by a device isolation layer on a semiconductor substrate. The conductive structure includes a gate pattern and source/drain regions adjacent to the gate pattern. A first semiconductor layer is... Agent: F. Chau & Associates, LLC
20090155972 - Method of producing semiconductor memory: A semiconductor memory includes a plurality of memory cell transistors each having a laminated gate. A method of producing the semiconductor memory includes the steps of: forming a plurality of element separation regions for separating the memory cell transistors; forming a first conductive layer through a gate oxide film; etching... Agent: Kubotera & Associates, LLC Suite 202
20090155973 - Semiconductor device having mosfet with offset-spacer, and manufacturing method thereof: A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first offset-spacer which is formed in contact with one side surface of the gate electrode, a first spacer which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090155974 - Method of manufacturing a semiconductor device having a channel extending vertically: In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first... Agent: Mills & Onello LLP
20090155976 - Atomic layer deposition of dy-doped hfo2 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing... Agent: Schwegman, Lundberg & Woessner/micron
20090155975 - Method for manufacturing metal-insulator-metal capacitor of semiconductor device: A method for manufacturing a metal-insulator-metal capacitor of a semiconductor device method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a logic metal and a capacitor lower metal is formed on a first insulating film that is formed... Agent: Workman Nydegger 1000 Eagle Gate Tower
20090155977 - Methods for forming a gate and a shallow trench isolation region and for planarizating an etched surface of silicon substrate: There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching... Agent: Squire, Sanders & Dempsey L.L.P.
20090155978 - Recessed shallow trench isolation: e
20090155979 - Method of manufacturing a semiconductor device: In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively... Agent: Mills & Onello LLP
20090155980 - Methods of forming trench isolation and methods of forming floating gate transistors: A method of forming trench isolation includes etching first trench lines into semiconductive material of a semiconductor substrate. First isolation material is formed within the first trench lines within the semiconductive material. After forming the first isolation material within the first trench lines, second trench lines are etched into semiconductive... Agent: Wells St. John P.s.
20090155981 - Method and apparatus for singulating integrated circuit chips: A method of singulating integrated circuit chips. The method includes forming, from a bottom surface of a substrate, trenches part way through the substrate in the kerf regions surrounding integrated circuit regions previously formed in the substrate; placing a top surface of the substrate on a singulation fixture having compartments,... Agent: Schmeiser, Olsen & Watts
20090155982 - Method of manufacturing semiconductor device having semiconductor formation regions of different planar sizes: A wafer process material is prepared which has a plurality of semiconductor formation regions of different planar sizes, each including a low dielectric constant film/wiring line stack structure component. A laser beam is applied onto a dicing street of the necessary semiconductor formation region and onto its straight extension in... Agent: Frishauf, Holtz, Goodman & Chick, PC
20090155984 - Backside protection film, method of forming the same and method of manufacturing a semiconductor package using the same: A method of forming a backside protection film includes forming a first coating layer on a first heterogeneous film, the first coating layer being at a C-stage state, forming a second coating layer on a second heterogeneous film, the second coating layer being at a B-stage state, separating the first... Agent: Lee & Morse, P.C.
20090155983 - Inhibition of metal diffusion arising from laser dicing: Method of inhibiting metal diffusion arising from laser dicing is provided. The method includes dividing a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the method... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090155985 - Inhibition of metal diffusion arising from laser dicing: A method divides a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the process exposes the chip to a heated ambient environment having a given pressure... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090155986 - Method for manufacturing gallium nitride single crystalline substrate using self-split: The present invention relates to a method for manufacturing a gallium nitride single crystalline substrate, including (a) growing a gallium nitride film on a flat base substrate made of a material having a smaller coefficient of thermal expansion than gallium nitride and cooling the gallium nitride film to bend convex... Agent: Greer, Burns & Crain
20090155987 - Method of fabricating gallium nitride substrate: A method of fabricating a gallium nitride (GaN) substrate provides a GaN thick film without causing bending and cracks which may occur in a growing process. To this end, a nitride embedding layer having a plurality of voids therein is embedded between a GaN layer and a base substrate. The... Agent: Lerner, David, Littenberg, Krumholz & Mentlik
20090155988 - Element of low temperature poly-silicon thin film and method of making poly-silicon thin film by direct deposition at low temperature and inductively-coupled plasma chemical vapor deposition equipment therefor: A low temperature poly-silicon thin film element, method of making poly-silicon thin film by direct deposition at low temperature, and the inductively-coupled plasma chemical vapor deposition equipment utilized, wherein the poly-silicon material is induced to crystallize into a poly-silicon thin film at low temperature by means of high density plasma... Agent: Birch Stewart Kolasch & Birch
20090155989 - Nitride semiconductor substrate and method of producing same: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts Π, forming outlining concavities on mask-covered parts not burying the... Agent: Mcdermott Will & Emery LLP
20090155990 - Manufacturing method of a semiconductor device and method for creating a layout thereof: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090155991 - Methods of fabricating a semiconductor device: A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer... Agent: Harness, Dickey & Pierce, P.L.C
20090155992 - High k stack for non-volatile memory: A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having... Agent: Harrity & Harrity, LLP
20090155993 - Terminal pad structures and methods of fabricating same: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.... Agent: Schmeiser, Olsen & Watts
20090155994 - Forming thin film transistors using ablative films with pre-patterned conductors: An ablative film comprising a substrate; at least one ablative layer that is removable by exposure to radiation; one or more deposited conductors; and an active layer including a semiconductor material surrounded at least partially by a dielectric.... Agent: Frank Pincelli Patent Legal Staff
20090155995 - Self-aligned contact formation utilizing sacrificial polysilicon: In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon layer is deposited over the substrate to fill the trenches. A patterning layer is deposited over the substrate and patterned to... Agent: RyderIPLaw C/o Cpa Global
20090155996 - Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement: An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement.... Agent: Scully, Scott, Murphy & Presser, P.C.
20090155997 - Method for forming ta-ru liner layer for cu wiring: A method of forming a Ta—Ru metal liner layer for Cu wiring includes: (i) conducting atomic deposition of Ta X times, each atomic deposition of Ta being accomplished by a pulse of hydrogen plasma, wherein X is an integer such that a surface of an underlying layer is not covered... Agent: Knobbe Martens Olson & Bear LLP
20090155998 - Atomic layer deposited tantalum containing adhesion layer: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including... Agent: Intel Corporation C/o Cpa Global
20090155999 - Method for fabricating metal silicide: A method for fabricating a metal silicide film is described. After providing a silicon material layer, a metal alloy layer is formed to cover the silicon material layer. A thermal process is performed to form a metal alloy silicide layer in a self-aligned way. A wet etching process is performed... Agent: J C Patents, Inc.
20090156000 - Method of manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided, which includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090156001 - Structure for reducing stress for vias and fabricating method thereof: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating... Agent: Harness, Dickey & Pierce, P.L.C
20090156002 - Manufacturing method for semiconductor device and manufacturing apparatus for semiconductor device: A wafer is placed on a lower electrode disposed in a reaction chamber; process gas is introduced into the reaction chamber; a magnetic field is applied at a position spaced from a surface of the wafer to be processed; plasma is generated by applying a high-frequency voltage between the lower... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090156003 - Method for depositing tungsten-containing layers by vapor deposition techniques: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten-containing layer by sequentially exposing a substrate to a processing gas and a tungsten-containing gas during an atomic layer deposition process, wherein the processing gas comprises a boron-containing gas and a... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090156004 - Method for forming tungsten materials during vapor deposition processes: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090156005 - Cleaning liquid used in process for forming dual damascene structure and a process for treating substrate therewith: It is disclosed a cleaning liquid used in a process for forming a dual damascene structure comprising steps of etching a low dielectric layer (low-k layer) accumulated on a substrate having thereon a metallic layer to form a first etched-space; charging a sacrifice layer in the first etched-space; partially etching... Agent: Wenderoth, Lind & Ponack, L.L.P.
20090156006 - Compositions and methods for cmp of semiconductor materials: The present invention provides a chemical-mechanical polishing (CMP) composition suitable for polishing semi-conductor materials. The composition comprises an abrasive, an organic amino compound, an acidic metal complexing agent and an aqueous carrier A CMP method for polishing a surface of a semiconductor material utilizing the composition is also disclosed.... Agent: Steven Weseman Associate General Counsel, I.p.
20090156008 - Polishing composition and polishing method using the same: A polishing composition includes an abrasive, at least one compound of azoles and derivatives thereof, and water. The polishing composition is used in applications for polishing surfaces of semiconductor substrates in a suitable manner.... Agent: Vidas, Arrett & Steinkraus, P.A.
20090156007 - Polishing slurry and polishing method: The present invention relates to polishing slurry and polishing method used for polishing in a process for forming wirings of a semiconductor device, and the like. There are provided polishing slurry giving a polished surface having high flatness even if the polished surface is made of two or more substances,... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090156009 - Method for manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device capable of providing a stable trench depth, including: forming, on a semiconductor substrate, a first film having a high etching selectivity with respect to the semiconductor substrate; forming, on the first film, a second film having a high etching selectivity with... Agent: Bruce L. Adams, Esq Adams & Wilks
20090156011 - Method of controlling cd bias and cd microloading by changing the ceiling-to-wafer gap in a plasma reactor: In a plasma etch process, critical dimension (CD), CD bias and CD bias microloading are controlled independently of plasma process conditions or parameters, such as RF power levels, pressure and gas flow rate, by depressing or elevating the workpiece support pedestal to vary the gap between the workpiece and the... Agent: Law Office Of Robert M. Wallace
20090156010 - Thin film etching method and semiconductor device fabrication using same: A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of... Agent: Brinks Hofer Gilson & Lione
20090156012 - Method for fabricating low k dielectric dual damascene structures: Methods for forming dual damascene structures in low-k dielectric materials that facilitate reducing photoresist poison issues are provided herein. In some embodiments, such methods may include plasma etching a via through a first mask layer into a low-k dielectric material disposed on a substrate. The first mask layer may then... Agent: MoserIPLaw Group / Applied Materials, Inc.
20090156013 - Method and apparatus for removing polymer from the wafer backside and edge: Polymer is removed from the backside of a wafer held on a support pedestal in a reactor using an arcuate side gas injection nozzle extending through the reactor side wall with a curvature matched to the wafer edge and supplied with plasma by-products from a remote plasma source.... Agent: Law Office Of Robert M. Wallace
20090156014 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device of the present invention includes: forming a first film, a second film and a third film in sequence on a silicon substrate; patterning a resist film formed on the third film by conducting an exposure and developing process for the resist film employing... Agent: Young & Thompson
20090156015 - Deposition apparatus: A deposition apparatus configured to form a thin film on a substrate includes: a reactor wall; a substrate support positioned under the reactor wall; and a showerhead plate positioned above the substrate support. The showerhead plate defines a reaction space together with the substrate support. The apparatus also includes one... Agent: Knobbe Martens Olson & Bear LLP
20090156016 - Method for transfer of a thin layer: A method for transferring a thin layer from an initial substrate includes forming an assembly of the initial substrate with one face of a silicone type polymer layer, this face having been treated under an ultraviolet radiation, and processing the initial substrate to form the thin layer on the silicone... Agent: Brinks Hofer Gilson & Lione
20090156017 - Method for forming dielectric film using siloxane-silazane mixture: A method of forming a dielectric film, includes: introducing a siloxane gas essentially constituted by Si, O, C, and H and a silazane gas essentially constituted by Si, N, H, and optionally C into a reaction chamber where a substrate is placed; depositing a siloxane-based film including Si—N bonds on... Agent: Knobbe Martens Olson & Bear LLP
20090156018 - Laser mask and crystallization method using the same: A crystallization method includes providing a substrate having a silicon thin film; positioning a laser mask having first to fourth blocks on the substrate, each block having a periodic pattern including a plurality of transmitting regions and a blocking region; and crystallizing the silicon thin film by irradiating a laser... Agent: Mckenna Long & Aldridge LLP
20090156019 - Substrate processing apparatus and method: A substrate processing apparatus is used for radiating UV rays onto a target film formed on a target surface of a substrate to perform a curing process of the target film. The apparatus includes a hot plate configured to heat the substrate to a predetermined temperature, a plurality of support... Agent: Smith, Gambrell & Russell06/11/2009 > patent applications in patent subcategories. invention type
20090148962 - Substrate structure and method for wideband power decoupling: A substrate structure and method of wideband power decoupling comprising one or more embedded capacitors each comprising a ferroelectric material.... Agent: C. James Bushman
20090148963 - Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is... Agent: Cook Alex Ltd
20090148964 - Method for forming dielectric sioch film having chemical stability: A method for determining conditions for forming a dielectric SiOCH film, includes: (i) forming a dielectric SiOCH film on a substrate under conditions; (ii) evaluating the conditions using a ratio of Si—CH3 bonding strength to Si—O bonding strength of the film as formed in step (i); (iii) if the ratio... Agent: Knobbe Martens Olson & Bear LLP
20090148965 - Method and apparatuses for high pressure gas annealing: Novel methods and apparatuses for annealing semiconductor devices in a high pressure gas environment. According to an embodiment, the annealing vessel has a dual chamber structure, and potentially toxic, flammable, or otherwise reactive gas is confined in an inner chamber which is protected by pressures of inert gas contained in... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090148966 - Method of manufacturing a system in package: A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has bee mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090148967 - Methods of making and using integrated and testable sensor array: A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer... Agent: General Electric Company Global Research
20090148968 - Organic electroluminescence device and method for manufacturing same: An organic electroluminescence device includes a substrate; first electrodes arranged on the luminous portion of the substrate in a single direction; an insulating layer pattern formed on the first electrodes and the substrate in a lattice shape to define plural pixel openings on the first electrodes; partition layers formed on... Agent: Bacon & Thomas, PLLC
20090148969 - Microelectronic imaging units: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the... Agent: Dickstein Shapiro LLP
20090148971 - Forming method of contact hole and manufacturing method of semiconductor device, liquid crystal display device and el display device: When forming a contact hole by a conventional manufacturing step of a semiconductor device, a resist is required to be formed on almost entire surface of a substrate so as to be applied on a film other than an area in which a contact hole is to be formed, leading... Agent: Nixon Peabody, LLP
20090148970 - Method for manufacturing semiconductor device: To provide a manufacturing method of a highly reliable TFT, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate TFT structure is adopted in which a photoresist is selectively exposed to light by rear... Agent: John F. Hayden Fish & Richardson P.c
20090148972 - Method for fabricating pixel structure: A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the... Agent: Jianq Chyun Intellectual Property Office
20090148974 - Method for manufacturing an in-plane switching mode liquid display device: In an IPS mode LCD device and method, a plurality of sub-blocks are utilized to maintain a maximum transmittance even when a voltage above a predetermined value is applied to the device. The IPS mode LCD device includes a common electrode including a plurality of first segments and a plurality... Agent: Mckenna Long & Aldridge LLP
20090148973 - Method of fabricating pixel structure of liquid crystal display: A method of fabricating a pixel structure of liquid crystal display is described. A transparent conductive layer and a first metal layer are formed over a substrate sequentially. The first metal layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A... Agent: J C Patents, Inc.
20090148975 - Method of manufacturing nitride semiconductor device: A method of manufacturing a nitride semiconductor device includes: a working region forming step of forming a working region in a group III nitride semiconductor substrate by converging a laser beam having a wavelength of 500 nm to 700 nm in the group III nitride semiconductor substrate and by scanning... Agent: Rabin & Berdo, PC
20090148976 - Method for fabricating semiconductor epitaxial layers using metal islands: Disclosed is a method for fabricating a GaN semiconductor epitaxial layer. The method includes the steps of: (a) providing a substrate within a reaction furnace; (b) setting a temperature range of the substrate to be 200° C.˜1,300° C.; (C) supplying a Ga metallic source on the substrate; (d) changing the... Agent: The Farrell Law Firm, P.C.
20090148977 - Packaging method for image sensor ic: The method contains the following steps. First, a number of circuit blocks are formed in one or more tightly populated array on an uncut substrate. The substrate is then placed on a flat platform where a number of pins on the platform threading through corresponding holes of the substrate. A... Agent: Leong C Lei
20090148978 - Processes for forming photovoltaic conductive features from multiple inks: Photovoltaic conductive features and processes for forming photovoltaic conductive features are described. The process comprises (a) providing a substrate comprising a passivation layer disposed on a silicon layer; (b) depositing a surface modifying material onto at least a portion of the passivation layer; (c) depositing a composition comprising at least... Agent: Patent Administrator Cabot Corporation
20090148979 - Fabricating apparatus with doped organic semiconductors: A method includes forming a semiconducting region including polyaromatic molecules on a surface of a substrate. The method also includes forming over the region a substantially oxygen impermeable dielectric layer. The act of forming a semiconducting region includes exposing the molecules to oxygen while exposing the molecules to visible or... Agent: Hitt Gaines, PC Alcatel-lucent
20090148980 - Method for forming phase-change memory element: A method for forming a phase-change memory element. The method includes providing a substrate with an electrode formed thereon; sequentially forming a conductive layer and a first dielectric layer on the substrate; forming a patterned photoresist layer on the first dielectric layer; subjecting the patterned photoresist layer to a trimming... Agent: Quintero Law Office, PC
20090148981 - Method for forming self-aligned thermal isolation cell for a variable resistance memory array: A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090148982 - Method of manufacturing compound semiconductor devices: A compound semiconductor device and method of manufacturing the same. The method includes coating a plurality of spherical balls on a substrate and selectively growing a compound semiconductor thin film on the substrate on which the spherical balls are coated. The entire process can be simplified and a high-quality compound... Agent: Marshall, Gerstein & Borun LLP
20090148983 - Method of manufacturing flexible semiconductor assemblies: A method for producing flexible semiconductor assemblies is described. For example, an integrated circuit package consisting of an X-Y axes sensor die and a Z-axis sensor die disposed at 90 degrees to each other may be formed by applying a flexible dielectric membrane to a semiconductor wafer, creating bending gaps... Agent: Honeywell International Inc.
20090148984 - Bulk gan and algan single crystals: Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example... Agent: Dr. Allan C. Entis, Intellectual Property Ltd.
20090148985 - Method for fabricating a nitride fet including passivation layers: A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current... Agent: MillerIPGroup, PLC Northrop Grumman Corporation
20090148986 - Method of making a finfet device structure having dual metal and high-k gates: A method of making a FinFET device structure, includes: providing a semiconductor-on-insulator (SOI) substrate having a semiconductor layer on an insulating layer on a base (e.g., semiconductor) layer; forming a cap layer (e.g., silicon nitride) on the SOI substrate; forming, on the insulating layer, first and second semiconductor fins with... Agent: International Business Machines Corporation Dept. 18g
20090148987 - Method for fabricating pixel structure: A method for fabricating a pixel structure is disclosed. A substrate is provided. A first conductive layer is formed on the substrate, and a first shadow mask exposing a portion of the first conductive layer is disposed over the first conductive layer. Laser is used to irradiate the first conductive... Agent: Jianq Chyun Intellectual Property Office
20090148988 - Method of reducing embedded sige loss in semiconductor device manufacturing: Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of... Agent: International Business Machines Corporation Dept. 18g
20090148989 - Semiconductor device comprising capacitor and method of fabricating the same: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in... Agent: Mcdermott, Will & Emery
20090148990 - Semiconductor devices and methods of forming the same: A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide gap regions exposing an upper surface... Agent: Lee & Morse, P.C.
20090148991 - Method of fabricating semiconductor device having vertical channel transistor: A method of fabricating a semiconductor device having a vertical channel transistor, the method including forming a hard mask pattern on a substrate, forming a preliminary active pillar by etching the substrate using the hard mask pattern as an etch mask, reducing a width of the preliminary active pillar to... Agent: Lee & Morse, P.C.
20090148992 - Semiconductor device and method of manufacturing the same: A semiconductor device includes: a semiconductor substrate; multiple active regions of a first conductive type isolated from one another by shallow-trench isolation regions provided on one surface of the semiconductor substrate; multiple silicon pillars including channel silicon pillars formed in the active regions; multiple first semiconductor regions of a second... Agent: Young & Thompson
20090148993 - Method of fabricating semiconductor device having a recess channel structure therein: A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner... Agent: Jianq Chyun Intellectual Property Office
20090148994 - Method of manufacturing semiconductor device with recess gate transistor: A method of manufacturing a semiconductor device includes forming a plurality of recesses in a semiconductor substrate, forming a gate insulating film in the plurality of recesses, and a plurality of gate electrodes on the gate insulating film in the plurality of recesses, forming an insulating layer on the semiconductor... Agent: Mcginn Intellectual Property Law Group, PLLC
20090148995 - Processes for manufacturing mosfet devices with excessive round-hole shielded gate trench (sgt): This invention discloses an improved method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) device. The method includes a step of opening a trench in substrate and covering trench walls of the trench with a linen layer followed by removing a portion of the linen layer from... Agent: Bo-in Lin
20090148996 - Method of making a semiconductor element: A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; forming a dielectric... Agent: Dicke, Billig & Czaja
20090148997 - Process for manufacturing semiconductor device: Reduction of damage to a semiconductor device due to a marking process while inhibiting deterioration of a mark can not be achieved in conventional processes for manufacturing semiconductor devices. A process for manufacturing the semiconductor device 100 involves irradiating the marking film 21 with an energy beam through the transparent... Agent: Young & Thompson
20090148998 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an orientation-dependent etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first... Agent: Hvvi Semiconductors, Inc.
20090148999 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At... Agent: Hvvi Semiconductors, Inc.
20090149000 - Combined semiconductor apparatus with thin semiconductor films: A semiconductor apparatus includes two thin semiconductor films bonded to a substrate, and a thin-film interconnecting line electrically connecting a semiconductor device such as a light-emitting device in the first thin semiconductor film to an integrated circuit in the second thin semiconductor film. Typically, the integrated circuit drives the semiconductor... Agent: Rabin & Berdo, PC
20090149001 - Producing soi structure using high-purity ion shower: Disclosed are methods for making SOI and SOG structures using purified ion shower for implanting ions to the donor substrate. The purified ion shower provides expedient, efficient, low-cost and effective ion implantation while minimizing damage to the exfoliation film.... Agent: Corning Incorporated
20090149002 - Method of forming a modified layer in a substrate: First, mapping data storing interrupted areas is obtained. In a first modified-layer forming step, before a stacked article is stacked on a front surface of a substrate, a laser beam is directed to the interrupted areas based on the mapping data to form modified layers only at the interrupted areas.... Agent: Greer, Burns & Crain
20090149003 - Dicing die-bonding film: The invention relates to a dicing die-bonding film having a pressure-sensitive adhesive layer (2) on a substrate material (1) and a die-bonding adhesive layer (3) on the pressure-sensitive adhesive layer (2), wherein the adhesion of the pressure-sensitive adhesive layer (2) to the die-bonding adhesive layer (3), as determined under the... Agent: Knobbe Martens Olson & Bear LLP
20090149004 - Micromirror manufacturing method: A micro-mirror manufacturing method for dividing a plurality of micro-mirror devices each having at least one mirror, formed on a semiconductor wafer into individual micro-mirror devices can be provided. The manufacturing method comprises a step of depositing an inorganic protection layer on the mirror before separating the micro-mirror devices from... Agent: Bo-in Lin
20090149005 - Method for making a dismountable substrate: The invention further concerns methods for forming a crystalline thin film and transferring this thin film onto a host substrate.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090149006 - Methods of forming a phase-change material layer pattern, methods of manufacturing a phase-change memory device and related slurry compositions: In methods of forming a phase-change material layer pattern, an insulation layer having a recessed portion may be formed on a substrate, and a phase-change material layer may be formed on the insulation layer to fill the recessed portion. A first polishing process may be performed on the phase-change material... Agent: Harness, Dickey & Pierce, P.L.C
20090149007 - Electronic device and method of manufacturing the same: Provided are an electronic device and a method of manufacturing the same. The device includes a plastic substrate, a transparent thermal conductive layer stacked on the plastic substrate, a polysilicon layer stacked on the thermal conductive layer; and a functional device disposed on the polysilicon layer. The functional device is... Agent: Buchanan, Ingersoll & Rooney PC
20090149008 - Method for depositing group iii/v compounds: Embodiments of the invention generally relate to methods for forming Group III-V materials by a hydride vapor phase epitaxy (HVPE) process. In one embodiment, a method for forming a gallium nitride material on a substrate within a processing chamber is provided which includes heating a metallic source to form a... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090149009 - Semiconductor structure and method of manufacture: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an electrochemical etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first... Agent: Hvvi Semiconductors, Inc.
20090149010 - Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and soi mos devices by gate stress engineering with sige and/or si:c: Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer... Agent: Scully, Scott, Murphy & Presser, P.C.
20090149011 - Non-volatile semiconductor memory device and process of manufacturing the same: In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090149012 - Method of forming a nonplanar transistor with sidewall spacers: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090149013 - Method of forming a crack stop laser fuse with fixed passivation layer coverage: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which... Agent: Ibm Microelectronics Intellectual Property Law
20090149015 - Manufacturing method of contact structure: A manufacturing method of a contact structure includes first providing a substrate on which a contact pad has already been formed. Afterwards, a polymer bump is formed on the contact pad. Next, a conductive layer is formed on the polymer bump. The conductive layer covers the polymer bump and extends... Agent: Jianq Chyun Intellectual Property Office
20090149014 - Method for producing a semiconductor device: At step S101, a TiW film is formed by a sputtering method so as to cover a surface protection film and pad electrodes formed on a surface of a semiconductor element. Subsequently, an Au film is formed on the TiW film. At step S103, Au bumps are formed on the... Agent: Nixon & Vanderhye, PC
20090149016 - Semiconductor device and method of fabricating the same: Provided is a semiconductor device and a method of fabricating the same. The method of fabricating the semiconductor device includes forming a mask pattern having an opening corresponding to an electrode pad formed on a semiconductor substrate; forming a bump by filling the opening with a conductive first material; forming... Agent: Marger Johnson & Mccollom, P.C.
20090149017 - Method of cleaning semiconductor substrate, and method of manufacturing semiconductor device and semiconductor substrate processing apparatus for use in the same: A semiconductor substrate processing apparatus is provided with a cleaning process chamber containing a semiconductor substrate for performing a cleaning process on the semiconductor substrate. Connected to the cleaning process chamber is a cleaning liquid feeding pipe for supplying a cleaning liquid to the semiconductor substrate. A gas dissolving unit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090149018 - Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases: The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality... Agent: Young & Thompson
20090149019 - Semiconductor device and method for fabricating the same: A semiconductor device has a first interlayer insulating film formed on a substrate, having a first interconnection buried therein, and having a depressed portion and an insulating barrier film formed on the first interlayer insulating film. A second interlayer insulating film is formed to fill in the depressed portion, cover... Agent: Mcdermott Will & Emery LLP
20090149020 - Method of manufacturing a semiconductor device: A technology is provided which allows, in a coupling portion obtained by burying a conductive material within a coupling hole bored in an insulating film, the removal of a natural oxide film on the surface of a silicide layer which is present at the bottom portion of the coupling hole.... Agent: Miles & Stockbridge PC
20090149021 - Spray dispensing method for applying liquid metal: Embodiments of a method for applying a thermal-interface material are described. During this method, a first surface of a heat-removal device and a second surface of a semiconductor die are prepared. Next, a region on a given surface, which is at least one of the first surface and the second... Agent: Pvf -- Apple Inc. C/o Park, Vaughan & Fleming LLP
20090149022 - Method for improving uniformity and adhesion of low resistivity tungsten film: Methods of improving the uniformity and adhesion of low resistivity tungsten films are provided. Low resistivity tungsten films are formed by exposing the tungsten nucleation layer to a reducing agent in a series of pulses before depositing the tungsten bulk layer. According to various embodiments, the methods involve reducing agent... Agent: Weaver Austin Villeneuve & Sampson LLP - Novl Attn.: Novellus Systems, Inc.
20090149023 - Method of fabricating semiconductor device having three-dimensional stacked structure: The trench 13, the inner wall face of which is covered with the insulating film 14, is formed in the surface of the semiconductor substrate 11 of the first semiconductor circuit layer 1a. Then, the inside of the trench 13 is filled with a conductive material, thereby forming the conductive... Agent: Griffin & Szipl, PC
20090149024 - Pattering method for a semiconductor substrate: A patterning method for a semiconductor substrate is disclosed. A substrate is provided and a stack structure is laid thereon. The stack layer includes at least a target layer and a pad layer sequentially formed on the substrate. Follow by a lithography process, wherein photoresists are laid on the stack... Agent: Rosenberg, Klein & Lee
20090149025 - Remover compositions: A remover composition containing 1,3-propanediamine (a), 1-hydroxyethylidene-1,1-diphosphonic acid (b) and water, wherein the remover composition contains the component (a) in an amount of from 0.2 to 30% by weight, the component (b) in an amount of from 0.05 to 10% by weight, and the water in an amount of from... Agent: Birch Stewart Kolasch & Birch
20090149026 - Method for forming high density patterns: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting... Agent: Knobbe Martens Olson & Bear LLP
20090149027 - Method of fabricating an integrated circuit: Embodiments of the invention relate to a method of fabricating an integrated circuit, including etching of a layer that includes a high k material in the form of a metal oxide composition, wherein an etchant is used that includes a silicon halogen composition.... Agent: Slater & Matsil, L.L.P.
20090149028 - Methods and apparatus for a hybrid capacitively-coupled and an inductively-coupled plasma processing system: A capacitively-coupled plasma (CCP) processing system having a plasma processing chamber for processing a substrate is provided. The capacitively-coupled Plasma (CCP) processing system includes an upper electrode and a lower electrode for processing the substrate, which is disposed on the lower electrode during plasma processing. The capacitively-coupled Plasma (CCP) processing... Agent: Ipsg, P.C.
20090149029 - Production method for semiconductor device: An inventive semiconductor device production method is a method for producing a semiconductor device having a metal interconnection by etching a metal film including a lower layer of a first metal material and an upper layer of a second metal material different from the first metal material. In the production... Agent: Rabin & Berdo, PC
20090149030 - Oxide etching method: There is provided an etching method of an amorphous oxide layer containing In and at least one of Ga and Zn, which includes etching the amorphous oxide layer using an etchant containing any one of acetic acid, citric acid, hydrochloric acid, and perchloric acid.... Agent: Fitzpatrick Cella Harper & Scinto
20090149031 - Method of making a semiconductor device with residual amine group free multilayer interconnection: The present invention provides a semiconductor device that can restrict the dissolution hindering phenomenon in a chemically amplified resist film. More specifically, after the formation of a contact pattern on a semiconductor substrate, a wiring pattern is formed on the contact pattern. A SiC film, a first SiOC film, a... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090149032 - Method for manufacturing semiconductor device and substrate processing apparatus: The present invention suppresses metallic contamination in a processing chamber and a breakage of a quartz member, while suppressing decrease in film formation rate in a thin film formation process immediately after dry cleaning of the inside of the processing chamber, and enhances the operation rate of a apparatus. The... Agent: Oliff & Berridge, PLC
20090149033 - Systems and methods for forming metal oxide layers: A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.... Agent: Mueting, Raasch & Gebhardt, P.A.
20090149034 - Semiconductor module and method of manufacturing the same: A plurality of interconnect layers, each including an interlayer dielectric film 405 and a copper interconnect 407, is stacked and a solder resist layer 408 is formed on an uppermost layer. Elements 410a and 410b are formed on a surface of the solder resist layer 408. The elements 410a and... Agent: Mcdermott Will & Emery LLP
20090149035 - Method for manufacturing of a crystal oscillator: A method of manufacturing a crystal oscillator, in which method semiconductor components and the crystal or another resonator (1) are joined to a bottom base (4), most suitably to the printed circuit board material. The components (2, 3, 5) are joined by soldering or gluing to said bottom base and... Agent: Stites & Harbison PLLC06/04/2009 > patent applications in patent subcategories. invention type
20090142857 - Package design of small diameter sensor: A small sensor assembly is produced by encapsulating an inner package within an outer package. The inner assembly can have electrical components and sensors attached to a lead frame. The electrical components can be protected within inner packages that have alignment indentations. The alignment indentations are positioned over the outside... Agent: Honeywell International Inc.
20090142858 - Power-measured pulses for thermal trimming: A circuit for trimming a thermally-trimmable resistor, measuring a temperature coefficient of resistance of the thermally-trimmable resistor, and annealing a thermally-trimmable resistor post-trimming, the circuit comprising: a thermally-isolated area on a substrate housing the thermally-trimmable resistor; heating circuitry for applying a signal to a heating resistor; and a constant-power module... Agent: Ogilvy Renault LLP
20090142859 - Plasma control using dual cathode frequency mixing: Methods for processing a substrate in a processing chamber using dual RF frequencies are provided herein. In some embodiments, a method of processing a substrate includes forming a plasma of a polymer forming chemistry to etch a feature into a substrate disposed on a substrate support in a process chamber... Agent: MoserIPLaw Group / Applied Materials, Inc.
20090142860 - System and method for enhanced control of copper trench sheet resistance uniformity: A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined... Agent: Duane Morris LLP (tsmc)IPDepartment
20090142861 - Method of manufacturing flash memory device: Disclosed are methods of manufacturing a flash memory device. The method can include performing a first test on memory banks of chips on a wafer to record an availability of the banks; performing an inking process on each of the chips according to a number of available banks in the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090142862 - Luminescent semi-conductive polymer material, method of preparing the same and organic light emitting element having the same: The present invention is related to a luminescent material generated by polymerization of a pyrromethene complex by glow discharge. The polymer material of the present invention exhibits semi-conductive properties and has a luminescence maximum in a spectrum region in the range of about 540 nm to about 585 nm with... Agent: Haynes And Boone, LLPIPSection
20090142864 - Method for manufacturing thin film transistor array substrate: A method for manufacturing a thin film transistor (TFT) array substrate needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs... Agent: Jianq Chyun Intellectual Property Office
20090142863 - Organic el display panel for reducing resistance of electrode lines: Method for fabricating an organic EL display panel having an EL region at every cross of first and second electrodes, including the steps of forming a plurality of first electrodes at regular intervals on a transparent substrate, forming an insulating layer in regions other than the EL regions, forming second... Agent: Ked & Associates, LLP
20090142865 - Liquid crystal display: A liquid crystal display using a ferroelectric liquid crystal, which can give mono-domain alignment of the ferroelectric liquid crystal without forming alignment defects such as zigzag defects, hairpin defects and double domains and which is so remarkably good in alignment stability that the alignment thereof can be maintained even if... Agent: Ladas & Parry LLP
20090142866 - Method for cutting liquid crystal display panel and method for fabricating liquid crystal display panel using the same: A method for cutting a liquid crystal display panel including: forming prearranged cut lines on a pair of attached mother substrates on which a plurality of panel regions have been disposed; and separating the liquid crystal display panel from a dummy glass around the liquid crystal display panel through a... Agent: Mckenna Long & Aldridge LLP
20090142867 - Method for manufacturing semiconductor device: The number of photomasks is reduced in a method for manufacturing a liquid crystal display device which operates in a fringe field switching mode, whereby a manufacturing process is simplified and manufacturing cost is reduced. A first transparent conductive film and a first metal film are sequentially stacked over a... Agent: Fish & Richardson P.C.
20090142868 - Organic electro-luminance device and method for fabricating the same: Provided is an organic EL device and fabrication method thereof that can prevent the performance of the organic EL layer and the TFT from being lowered in forming the cathode using an E-beam heating evaporation process. The organic EL device includes a substrate, an anode, an organic EL layer, a... Agent: Ked & Associates, LLP
20090142869 - Method of producing semiconductor optical device: Si atoms obtained by thermal decomposition of SiH4 are adsorbed in advance on one surface of a semiconductor substrate and side surfaces of a semiconductor mesa part. Thereby, prior to the growth of a buried layer, a diffusion protection layer composed of Si-doped InP with high impurity concentration is formed.... Agent: Smith, Gambrell & Russell
20090142870 - Manufacturing method of group iii nitride semiconductor light-emitting device: The present invention provides a manufacturing method of a group III nitride semiconductor light-emitting device, including a lamination step of forming a plurality of lamination films including a group III nitride semiconductor on a substrate, in which a substrate on which is formed a foundation layer including a monocrystalline group... Agent: Sughrue Mion, PLLC
20090142871 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O2, O3, NO, N2O,... Agent: Leydig Voit & Mayer, Ltd
20090142872 - Fabrication of capacitive micromachined ultrasonic transducers by local oxidation: Fabrication methods for capacitive micromachined ultrasonic transducers (CMUTS) with independent and precise gap and post thickness control are provided. The fabrication methods are based on local oxidation or local oxidation of silicon (LOCOS) to grow oxide posts. The process steps enable low surface roughness to be maintained to allow for... Agent: Lumen Patent Firm
20090142873 - Method for manufacturing a sensor array including a monolithically integrated circuit: A method for producing a sensor array including a monolithically integrated circuit is described as well as a sensor array. This sensor array has a micromechanical sensor structure, in which a first partial structure which is associated with the sensor structure is produced at the same time as a second... Agent: Kenyon & Kenyon LLP
20090142874 - Method for manufacturing photoelectric conversion device: A method for manufacturing a photoelectric conversion device typified by a solar cell, having an excellent photoelectric conversion characteristic with a silicon semiconductor material effectively utilized. The point is that the surface of a single crystal semiconductor layer bonded to a supporting substrate is irradiated with a pulsed laser beam... Agent: Eric Robinson
20090142875 - Method of making an improved selective emitter for silicon solar cells: A method for forming a selective emitter on a silicon solar cell is provided including forming an oxide layer on a surface of the P-type silicon substrate, implanting phosphorus doping atoms into the oxide layer on the substrate using plasma immersion ion implantation, patterning the oxide layer, annealing the substrate... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090142876 - Ink composition and fabrication method for color conversion film: An ink composition of a color conversion film is disclosed. The ink composition includes a fluorescent polymer (Formula I, II, III), an aromatic transparent unsaturated resin containing a phenyl or fluorene functional group (Formula IV, V), and a solvent of a cyclic compound, wherein the molecular structure of the aromatic... Agent: Pai Patent & Trademark Law Firm
20090142877 - Method for making a thin-film poly-crystalline silicon solar cell on an indium tin oxide-glass substrate at a low temperature: A method is disclosed for making a thin-film poly-crystalline silicon solar cell. In the method, there is provided an ITO-glass substrate by coating a glass substrate with a transparent and conductive ITO film. An amorphous silicon film is grown on the ITO-glass substrate. An aluminum film is grown on the... Agent: Troxell Law Office PLLC
20090142879 - Method of manufacturing photoelectric conversion device: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting... Agent: Fish & Richardson P.C.
20090142878 - Plasma treatment between deposition processes: Embodiments of the present invention include an improved method of forming a thin film solar cell device using a plasma processing treatment between two or more deposition steps. Embodiments of the invention also generally provide a method and apparatus for forming the same. The present invention may be used to... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090142880 - Solar cell contact formation process using a patterned etchant material: Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active region(s) and the metal contact structure of a solar cell device. In one embodiment, the methods include the use of various etching and patterning processes that are used to define... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090142882 - Phase change memories with improved programming characteristics: A phase change memory may be made with improved speed and stable characteristics over extended cycling. The alloy may be selected by looking at alloys that become stuck in either the set or the reset state and finding a median or intermediate composition that achieves better cycling performance. Such alloys... Agent: Trop, Pruner & Hu, P.C.
20090142881 - Tellurium (te) precursors for making phase change memory materials: Tellurium (Te)-containing precursors, Te containing chalcogenide phase change materials are disclosed in the specification. A method of making Te containing chalcogenide phase change materials using ALD, CVD or cyclic CVD process is also disclosed in the specification in which at least one of the disclosed tellurium (Te)-containing precursors is introduced... Agent: Air Products And Chemicals, Inc. Patent Department
20090142883 - Leaded stacked packages having elevated die paddle: A semiconductor package includes a leadframe, an elevated die paddle disposed above the leadframe, a first die attached to a lower surface of the elevated die paddle to support the first die within the semiconductor package, and a second die attached to the first die. A method of manufacturing a... Agent: Robert D. Atkins
20090142884 - Method of manufacturing a semiconductor device: s
20090142885 - Method for protecting porous low-k dielectric post chemical mechanical planarization: A method of forming a semiconductor structure chemically-mechanically polishes (CMP) a semiconductor structure before applying a sealant layer over the porous low-k dielectric. The process of applying the sealant layer is a selective process that causes the sealant to adhere to or deposit onto the porous low-k dielectric and to... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090142886 - Method of fabricating thin film transistor structure: A method of fabricating a thin film transistor (TFT) includes first providing a strip-shaped silicon island which is a thin film region with a predetermined long side and short side. Next, the strip-shaped silicon island is subject to an ion implantation to form a first ion doping region and a... Agent: Jianq Chyun Intellectual Property Office
20090142888 - Manufacturing method of semiconductor device: A semiconductor device which has higher integration and is further reduced in thickness and size. A semiconductor device with high performance and low power consumption. A semiconductor element layer separated from a substrate by using a separation layer is stacked over a semiconductor element layer formed by using another substrate... Agent: Eric Robinson
20090142887 - Methods of manufacturing an oxide semiconductor thin film transistor: Methods of manufacturing an oxide semiconductor thin film transistor are provided. The methods include forming a gate on a substrate, and a gate insulating layer on the substrate to cover the gate. A channel layer, which is formed of an oxide semiconductor, may be formed on the gate insulating layer.... Agent: Harness, Dickey & Pierce, P.L.C
20090142889 - Oxide isolated metal silicon-gate jfet: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric... Agent: Baker Botts L.L.P.
20090142890 - Phosphorus activated nmos using sic process: A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure... Agent: Texas Instruments Incorporated
20090142891 - Maskless stress memorization technique for cmos devices: In one embodiment, the present invention provides a method of manufacturing a semiconducting device that includes providing a silicon containing substrate having PFET device and NFET device, wherein the NFET device includes an amorphous silicon containing region; depositing a tensile strain silicon nitride layer atop the NFET device and the... Agent: Scully, Scott, Murphy & Presser, P.C.
20090142892 - Method of fabricating semiconductor device having thin strained relaxation buffer pattern and related device: A method of fabricating a semiconductor device includes forming a buffer pattern on a substrate, the buffer pattern including germanium, recrystallizing the buffer pattern to form a strained relaxation buffer pattern, and forming a tensile silicon cap on the strained relaxation buffer pattern, the cap being under tensile strain.... Agent: Lee & Morse, P.C.
20090142893 - Oxide epitaxial isolation: Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A... Agent: Schwegman, Lundberg & Woessner/micron
20090142894 - Method for fabricating a semiconductor structure: A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor... Agent: Schmeiser, Olsen & Watts
20090142896 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having first and second low voltage transistor regions and first and second high voltage transistor regions. A dielectric layer is formed over the semiconductor substrate-in the low and high voltage transistor. Gates are formed over the dielectric layer... Agent: Sherr & Vaughn, PLLC
20090142895 - Method of forming a via: A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an... Agent: Freescale Semiconductor, Inc. Law Department
20090142897 - Field effect transistor with narrow bandgap source and drain regions and method of fabrication: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090142898 - Coupling well structure for improving hvmos performance: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation... Agent: Slater & Matsil, L.L.P.
20090142899 - Interfacial layer for hafnium-based high-k/metal gate transistors: A method of forming an interfacial layer for hafnium-based high-k/metal gate transistors comprises depositing a hafnium-based high-k dielectric layer on a semiconductor substrate and then annealing the high-k dielectric layer and the semiconductor substrate in a nitric oxide atmosphere for a time duration and at a temperature sufficient to drive... Agent: Rahul D. Engineer Intel Corporation
20090142900 - Method for creating tensile strain by selectively applying stress memorization techniques to nmos transistors: By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an... Agent: Williams, Morgan & Amerson
20090142901 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is disclosed. The method includes: forming a photoresist film on a semiconductor substrate including a silicide forming region and non-silicide forming region; forming a photoresist pattern as a non-salicide pattern by patterning the photoresist film, so as to cover the non-silicide forming region... Agent: Sherr & Vaughn, PLLC
20090142902 - Methods of etching trenches into silicon of a semiconductor substrate, methods of forming trench isolation in silicon of a semiconductor substrate, and methods of forming a plurality of diodes: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma... Agent: Wells St. John P.s.
20090142903 - Chip on wafer bonder: The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.... Agent: Haynes And Boone, LLPIPSection
20090142904 - Method for manufacturing soi substrate: A second single crystal semiconductor film is formed over a first single crystal semiconductor film; a separation layer is formed by addition of ions into the second single crystal semiconductor film; a second insulating film functioning as a bonding layer is formed over the second single crystal semiconductor film; a... Agent: Eric Robinson
20090142905 - Method for manufacturing soi substrate: Adhesion defects between a single crystal semiconductor layer and a support substrate are reduced to manufacture an SOI substrate achiving high bonding strength between the single crystal semiconductor layer and the support substrate. Plasma is produced by exciting a source gas, ion species contained in the plasma are added from... Agent: Eric Robinson
20090142906 - Method of dividing wafer: A method of dividing a wafer includes: a denatured layer forming step of forming a denatured layer in the inside of the wafer along streets; a first feeding step in which the whole area of the wafer's back-side surface is suction held, and the wafer is mounted on a support... Agent: Greer, Burns & Crain
20090142907 - Semiconductor manufacturing apparatus and manufacturing method of semiconductor device: The present invention provides means for making appropriate a preheat condition at a sapphire substrate preheating step and thereby smoothing sucking and holding of a sapphire substrate. The means includes a hot plate for heating up a sapphire substrate in the atmosphere, support portions for supporting the sapphire substrate with... Agent: Rabin & Berdo, PC
20090142908 - Method of manufacturing photoelectric conversion device: A photoelectric conversion device having an excellent photoelectric conversion characteristic is provided while effectively utilizing limited resources. A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer, a first... Agent: Fish & Richardson P.C.
20090142909 - Method for manufacturing microcrystalline semiconductor film, thin film transistor having microcrystalline semiconductor film, and photoelectric conversion device having microcrystalline semiconductor film: A method for forming a microcrystalline semiconductor film over a base formed of a different material, which has high crystallinity in the entire film and at an interface with the base, is proposed. Further, a method for manufacturing a thin film transistor including a microcrystalline semiconductor film with high crystallinity... Agent: Eric Robinson
20090142910 - Manufacturing method of multi-level non-volatile memory: A manufacturing method of a multi-level non-volatile memory includes following steps. First, a tunneling dielectric layer and a charge storage layer are sequentially formed on the substrate. At least two stacked layers are formed on the charge storage layer. Every two stacked layers include an inter-gate dielectric layer, a control... Agent: Jianq Chyun Intellectual Property Office
20090142911 - Masking paste, method of manufacturing same, and method of manufacturing solar cell using masking paste: A masking paste used as a mask for controlling diffusion when diffusing a p-type dopant and an n-type dopant into a semiconductor substrate and forming a high-concentration p-doped region and a high concentration n-doped region is provided that contains at least a solvent, a thickening agent, and SiO2 precursor and/or... Agent: Nixon & Vanderhye, PC
20090142912 - Method of manufacturing thin film semiconductor device and thin film semiconductor device: A method of manufacturing a thin film semiconductor device that includes forming a thin film transistor on a substrate, forming a layer insulation film on the substrate, the layer insulation film containing no hydroxyl group in at least a film constituting a lowermost layer in the state of covering said... Agent: Sonnenschein Nath & Rosenthal LLP
20090142913 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and... Agent: Mcdermott Will & Emery LLP
20090142914 - Method for manufacturing semiconductor device: Disclosed are methods for manufacturing a semiconductor device, capable of inhibiting an undercut from occurring in a dielectric layer formed between a floating gate and a control gate. In one method, the dielectric layer can be protected using a covering of a nitride layer that can be used as a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090142915 - Gate structure and method of forming the same: A semiconductor device includes a semiconductor substrate, a dielectric layer on the substrate, and a gate on the dielectric layer. The gate has first and second ends containing a first material, a middle region between the first and second ends containing a second material. The first material has a different... Agent: Cypress Semiconductor Corporation
20090142916 - Apparatus and method of manufacturing an integrated circuit: On aspect is a method to manufacture an integrated circuit including a reshaping process of the wafer edge region and an apparatus to perform the reshaping process.... Agent: Dicke, Billig & Czaja
20090142917 - Method for fabricating metal line of semiconductor device: Methods for fabricating a metal line of a semiconductor device are disclosed. In a disclosed example, the method includes a first step of forming a passivation film on a semiconductor substrate having a semiconductor device, a second step of forming contact holes in the passivation film to form a first... Agent: Workman Nydegger 1000 Eagle Gate Tower
20090142918 - Semiconductor device fabricating method: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises providing a substrate with a logic device region and a memory device region. A logic device with a first silicide region and a first silicide block region and a memory device with a second silicide region and... Agent: Quintero Law Office, PC
20090142919 - Semiconductor device and manufacturing method of the same: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming... Agent: Stanley P. Fisher Reed Smith LLP
20090142920 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes can prevent defects of a semiconductor device due to the deterioration of electro migration (EM)/stress migration (SM) properties of the device as a result of metal corrosion and void generation in burying a novolac material. Embodiments can also prevent the generation of... Agent: Sherr & Vaughn, PLLC
20090142921 - Method for reducing dielectric overetch when making contact to conductive features: In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will... Agent: Dugan & Dugan, PC
20090142922 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a dielectric layer is formed on the whole surface of a semiconductor substrate that includes an upper surface of a transistor. Next, a trench and a contact hole... Agent: Workman Nydegger 1000 Eagle Gate Tower
20090142923 - Copper gate electrode of liquid crystal display device and method of fabricating the same: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy... Agent: Bacon & Thomas, PLLC
20090142924 - Reduced electromigration and stressed induced migration of cu wires by surface coating: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by... Agent: Connolly Bove Lodge & Hutz LLP
20090142925 - Method for forming tungsten film having low resistivity and good surface roughness and method for forming wiring of semiconductor device using the same: A method for forming a tungsten film includes forming a tungsten nucleation layer having an amorphous-phase or a β-phase over a semiconductor substrate. A first tungsten layer having a crystalline α-phase is then formed over the tungsten nucleation layer to form a low resistivity tungsten film. A second tungsten layer... Agent: Ladas & Parry LLP
20090142927 - Fabricating sub-lithographic contacts: A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing to be overcome to... Agent: Trop, Pruner & Hu, P.C.
20090142926 - Line edge roughness reduction and double patterning: Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP
20090142928 - Manufacturing method of semiconductor device: A manufacturing method for a semiconductor device simplifies a process for forming an oxide film of a high-voltage device, thereby reducing the manufacturing costs and manufacturing time of the high-voltage device. The manufacturing method includes applying a gate oxide material over a semiconductor wafer, applying a photoresist material over the... Agent: Sherr & Vaughn, PLLC
20090142930 - Gate profile control through effective frequency of dual hf/vhf sources in a plasma etch process: A method of processing a wafer in a plasma, in which target values of two different plasma process parameters are simultaneously realized under predetermined process conditions by setting respective power levels of VHF and HF power simultaneously coupled to the wafer to respective optimum levels.... Agent: Law Office Of Robert M. Wallace
20090142929 - Method for plasma processing over wide pressure range: A method for treating a substrate with plasma over a wide pressure range is described. The method comprises exposing the substrate to a low pressure plasma in a process chamber. Further, the method comprises exposing the substrate to a high pressure plasma in the process chamber.... Agent: Tokyo Electron U.s. Holdings, Inc.
20090142931 - Cleaning method following opening etch: A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment... Agent: North America Intellectual Property Corporation
20090142932 - Method of forming a hard mask pattern in a semiconductor device: In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely disposed active regions.... Agent: Townsend And Townsend And Crew, LLP
20090142933 - Manufacturing apparatus for semiconductor device and manufacturing method for semiconductor device: A manufacturing apparatus for a semiconductor device, includes: a reaction chamber to which a wafer w is loaded; a gas supply port for supplying first process gas including source gas from an upper portion of the reaction chamber; a first rectifying plate for supplying the first process gas onto the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090142934 - Method of forming semiconductor device having nanotube structures: A semiconductor device having upright dielectric nanotubes at an inter-layer dielectric level and method of manufacturing such a device is disclosed. The use of a catalyst is proposed in the disclosed manufacturing flow that facilitates growth of upright dielectric nanotubes having ultra low-k values that form all or part of... Agent: Larson Newman Abel & Polansky, LLP
20090142935 - Method for forming silazane-based dielectric film: A method of forming a dielectric film includes: introducing a source gas essentially constituted by Si, N, H, and optionally C and having at least one bond selected from Si—N, Si—Si, and Si—H into a reaction chamber where a substrate is placed; depositing a silazane-based film essentially constituted by Si,... Agent: Knobbe Martens Olson & Bear LLP
20090142936 - Method of forming gated, self-aligned micro-structures and nano-structures: Methods of forming a gated, self-aligned nano-structures for electron extraction are disclosed. One method of forming the nano-structure comprises irradiating a first surface of a thermally conductive laminate to melt an area across the first surface of the laminate. The laminate comprises a thermally conductive film and a patterned layer... Agent: Brinks Hofer Gilson & LionePrevious industry: Chemistry: analytical and immunological testing
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