Semiconductor device manufacturing: process inventions 04/09

20090111198 - Method for manufacturing semiconductor device: A manufacturing method of the present invention includes a process using a first multi-tone mask, in which a first conductive layer in which a transparent conductive layer and a metal layer are stacked over a substrate, a gate electrode formed of a first conductive layer, and a pixel electrode formed... Agent: Fish & Richardson P.C.

20090111199 - Method of manufacturing flat panel display: The present invention relates to a method for manufacturing a flat panel display. Herein, the same mask is used to form contact holes and pixel electrodes in the display substrate. Hence, the number of masks needed for manufacturing the flat panel display can be reduced to decrease the manufacturing cost.... Agent: Bacon & Thomas, PLLC

20090111200 - Method for fabricating electronic and photonic devices on a semiconductor substrate: A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the... Agent: Dillon & Yudell LLP

20090111201 - Ridge and mesa optical waveguides: Apparatus including: a substrate layer having a substantially planar top surface; an optically conductive peak located and elongated on, and spanning a first thickness measured in a direction generally away from, the top surface; the optically conductive peak having first and second lateral walls each including distal and proximal lateral... Agent: Jay M. Brown

20090111202 - Method for self bonding epitaxy: A method for self bonding epitaxy includes forming a passivation layer on a substrate surface of a semiconductor lighting element; etching to form recesses and protrusive portions with the passivation layer located thereon; starting forming epitaxy on the bottom surface of the recesses; filling the recesses with an Epi layer;... Agent: Joe Mckinney Muncy

20090111203 - Method for manufacturing semiconductor light emitting device: A laminated structure having light-emitting units is formed on a single-crystal wafer. Electrode patterns are formed on the single-crystal wafer opposite the light-emitting units. Dummy patterns are formed on the single-crystal wafer at a location spaced apart from a location opposite the light-emitting units, and offset from a desired cleavage... Agent: Leydig Voit & Mayer, Ltd

20090111204 - Vertically aligned mode liquid crystal display: A plurality of gate lines and a plurality of data lines intersecting each other are formed on a first insulating substrate having a plurality of first cutouts are formed on the respective pixel areas defined by the data lines and the gate lines. A thin film transistor is connected to... Agent: Haynes And Boone, LLPIPSection

20090111205 - Method of seperating two material systems: An embodiment of this invention discloses a method of separating two material systems, which comprises steps of providing a bulk sapphire; forming a nitride system on the bulk sapphire; forming at least two channels between the bulk sapphire and the nitride system; etching at least one inner surface of the... Agent: Bacon & Thomas, PLLC

20090111206 - Collector grid, electrode structures and interrconnect structures for photovoltaic arrays and methods of manufacture: The invention teaches novel structure and methods for producing electrical current collectors and electrical interconnection structure. Such articles find particular use in facile production of modular arrays of photovoltaic cells. The current collector and interconnecting structures may be initially produced separately from the photovoltaic cells thereby allowing the use of... Agent: Daniel Luch

20090111208 - Colors only process to reduce package yield loss: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical... Agent: Duane Morris LLP (tsmc)IPDepartment

20090111207 - Method of fabricating an integrated detection biosensor: A method of fabricating an integrated detection biosensor, the biosensor comprising an assembly (10) of photodetectors (12) of CCD or CMOS type on which there is deposited or formed a filter for rejecting excitation light λe, the filter comprising at least one absorbent layer (14) together with a Bragg mirror... Agent: Alston & Bird LLP

20090111209 - Method for patterning mo layer in a photovoltaic device comprising cigs material using an etch process: A processing method described herein provides a method of patterning a MoSe2 and/or Mo material, for example a layer of such material(s) in a thin-film structure. According to one aspect, the invention relates to etch solutions that can effectively etch through Mo and/or MoSe2. According to another aspect, the invention... Agent: Applied Materials C/o Pillsbury Winthrop Shaw Pittman LLP

20090111211 - Flat panel display and manufacturing method of flat panel display: The present disclosure relates to a display device comprising an insulating substrate; a source electrode and a drain electrode on the insulating substrate and separated by a channel area; an organic semiconductor layer formed in the channel area and on at least a portion of the source electrode and at... Agent: Haynes And Boone, LLPIPSection

20090111210 - Method for organic semiconductor material thin-film formation and process for producing organic thin film transistor: A method for the formation of an organic semiconductor material film having improved mobility on a substrate, and a process for producing an organic thin film transistor which can develop high performance by utilizing the method. The production process of an organic thin film transistor utilizes the method for organic... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090111212 - Method and apparatus for chalcogenide device formation: Chalcogenide devices are delineated and sidewalls of the devices are sealed, in an anaerobic and/or anhydrous environment environment. Throughout the delineation and sealing steps, and any intervening steps, the sidewalls are not exposed to oxygen or water. In an illustrative embodiment, a cluster tool includes an etching tool and a... Agent: Ovonyx, Inc

20090111213 - High-density fine line structure and method of manufacturing the same: A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer... Agent: Lin & Associates Intellectual Property, Inc.

20090111216 - Application of hipims to through silicon via metallization in three-dimensional wafer packaging: A method of magnetically enhanced sputtering an electrically-conductive material onto interior surfaces of a trench described herein includes providing a magnetic field adjacent to a target formed at least in part from the electrically-conductive material, and applying a DC voltage between an anode and the target as a plurality of... Agent: Pearne & Gordon LLP

20090111214 - Method for improved power distribution in a three dimensional vertical integrated circuit: A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20090111217 - Method of manufacturing chip-on-chip semiconductor device: Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed... Agent: Harness, Dickey & Pierce, P.L.C

20090111215 - Modular chip integration techniques: Modular chip integration and operation techniques are provided. In one aspect, a method of integrating chips, chip macros or at least one chip in combination with at least one chip macro is provided. The method comprises the following steps. The chips, chip macros or at least one chip in combination... Agent: Michael J. Chang, LLC

20090111218 - Stack mcp and manufacturing method thereof: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090111219 - Wafer-level chip scale package and method for fabricating and using the same: A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense... Agent: Kenneth E. Horton Kirton & Mcconkle

20090111220 - Coated lead frame: A lead frame having a coating of organic compounds on its lead fingers prevents tin and flux from contaminating the lead fingers after die attach. The coating is removed prior to wire bonding. The coating allows for reliable second bonds (bond between wires and lead fingers) to be formed, decreasing... Agent: Freescale Semiconductor, Inc. Law Department

20090111221 - Fabrication method of semiconductor device: A fabrication method of semiconductor device includes providing a substrate which has a plurality of electrical connection pads and is covered with an insulative layer, wherein the insulative layer has an opening formed for exposing the electrical connection pads; forming a filling material on the insulative layer of the substrate... Agent: Edwards Angell Palmer & Dodge LLP

20090111222 - Semiconductor chip mounting method, semiconductor mounting wiring board producing method and semiconductor mounting wiring board: A method of producing a wiring board on which a semiconductor chip is to be mounted, includes: adhering an aluminum foil to one surface of a resin substrate; providing a heat-hardening resin layer having a predetermined shape on the aluminum foil; removing a part of the aluminum foil which is... Agent: Dickstein Shapiro LLP

20090111223 - Soi device having a substrate diode formed by reduced implantation energy: By removing material during the formation of trench openings of isolation structures in an SOI device, the subsequent implantation process for defining the well region for a substrate diode may be performed on the basis of moderately low implantation energies, thereby increasing process uniformity and significantly reducing cycle time of... Agent: Williams, Morgan & Amerson

20090111224 - Fusi integration method using sog as a sacrificial planarization layer: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer... Agent: Texas Instruments Incorporated

20090111225 - Cmos structure and method including multiple crystallographic planes: A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater... Agent: Scully, Scott, Murphy & Presser, P.C.

20090111226 - Method for integrating nvm circuitry with logic circuitry: A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer)... Agent: Freescale Semiconductor, Inc. Law Department

20090111227 - Method for forming trench gate field effect transistor with recessed mesas using spacers: A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well... Agent: Townsend And Townsend And Crew, LLP

20090111229 - Method of forming a split gate non-volatile memory cell: A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control... Agent: Freescale Semiconductor, Inc. Law Department

20090111228 - Self aligned ring electrodes: The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least... Agent: Scully, Scott, Murphy & Presser, P.C.

20090111231 - Method for forming shielded gate field effect transistor using spacers: A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the... Agent: Townsend And Townsend And Crew, LLP

20090111230 - Method of manufacturing semiconductor device: A p− RESURF region is formed as a surface layer in an n− semiconductor layer. Then, trenches, gate insulating films, and a thick insulating film, gate electrodes, and a gate polysilicon interconnection are formed in this order. Subsequently, a p-well region is formed using the gate polysilicon interconnection as a... Agent: Rossi, Kimms & Mcdowell LLP.

20090111232 - Semiconductor device having decoupling capacitor and method of fabricating the same: A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of... Agent: Mills & Onello LLP

20090111233 - Method of forming junction of semiconductor device: The present invention relates to a method of forming junctions of a semiconductor device. According to the method of forming junctions of a semiconductor device in accordance with an aspect of the present invention, there is provided a semiconductor substrate in which a transistor including the junctions are formed. A... Agent: Townsend And Townsend And Crew, LLP

20090111234 - Method for forming min capacitor in a copper damascene interconnect: A method for forming a metal-insulator-metal capacitor in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition... Agent: Duane Morris LLP (tsmc)IPDepartment

20090111235 - Semiconductor integrated circuit devices having high-q wafer back-side capacitors: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a... Agent: Frank V. Derosa, Esq. F. Chau & Associates, LLC

20090111237 - Method for manufacturing semiconductor substrate: A gate oxide film provided on an SOI substrate is obtained by laminating a low-temperature thermal oxide film 13 grown at a temperature of 450° C. or below and an oxide film 14 obtained based on a CVD method. Since the thermal oxide film 13 is a thin film of... Agent: Oliff & Berridge, PLC

20090111236 - Method for manufacturing soi substrate: An object is to reduce occurrence of defective bonding between a base substrate and a semiconductor substrate even when a silicon nitride film or the like is used as a bonding layer. Another object is to provide a method for manufacturing an SOI substrate by which an increase in the... Agent: Fish & Richardson P.C.

20090111238 - Method for manufacturing semiconductor device capable of increasing current drivability of pmos transistor: A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor... Agent: Ladas & Parry LLP

20090111239 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes determining an active region in a semiconductor substrate, forming a recess in a gate region crossing over the active region, annealing an oxide layer formed in the recess to oxidize the active region in the gate region, and etching the active region... Agent: Marshall, Gerstein & Borun LLP

20090111240 - Method of manufacturing semiconductor device: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a mask including a first silicon nitride film over a semiconductor substrate, forming a trench in a surface of the semiconductor substrate using the mask, forming a silicon oxide film over the mask to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090111241 - Wafer bonding method: A method includes steps of providing first and second substrates, and forming a bonding interface between them using a conductive bonding region. A portion of the second substrate is removed to form a mesa structure. A vertically oriented semiconductor device is formed with the mesa structure. A portion of the... Agent: Schmeiser Olsen & Watts

20090111244 - Method for manufacturing semiconductor device: A single crystal semiconductor substrate is irradiated with ions that are generated by exciting a hydrogen gas and are accelerated with an ion doping apparatus, thereby forming a damaged region that contains a large amount of hydrogen. After the single crystal semiconductor substrate and a supporting substrate are bonded, the... Agent: Eric Robinson

20090111242 - Method for producing semiconductor substrate: An object of the present invention is to provide a method by which bonding at a low temperature is possible and an amount of metal contaminants in an SOI film is decreased. An embodiment of the present invention is realized in the following manner. A single crystal silicon substrate 10... Agent: Oliff & Berridge, PLC

20090111243 - Soi substrates with a fine buried insulating layer: A method of producing a semiconductor structure having a buried insulating layer having a thickness between 2 and 25 nm, by: forming at least one insulating layer on a surface of a first or second substrate, or both, wherein the surfaces are free from an insulator or presenting a native... Agent: Winston & Strawn LLP Patent Department

20090111245 - Method for manufacturing bonded wafer: The present invention provides a method for manufacturing a bonded wafer comprising steps of forming an oxide film on at least a surface of a base wafer or a surface of a bond wafer; bringing the base wafer and the bond wafer into close contact via the oxide film; subjecting... Agent: Oliff & Berridge, PLC

20090111246 - Inhibitors for selective deposition of silicon containing films: A method for depositing a single crystalline silicon film comprises: providing a substrate disposed within a chamber; introducing to the chamber under chemical vapor deposition conditions a silicon precursor, a chlorine-containing etchant and an inhibitor source for decelerating reactions between the silicon precursor and the chlorine-containing etchant; and selectively depositing... Agent: Knobbe, Martens, Olson & Bear LLP

20090111247 - Formation method of single crystal semiconductor layer, formation method of crystalline semiconductor layer, formation method of polycrystalline layer, and method for manufacturing semiconductor device: A method for forming a single crystal semiconductor layer in which a first porous layer and a second porous layer are formed over a single crystal semiconductor ingot, a groove is formed in a part of the second porous layer and a single crystal semiconductor layer is formed over the... Agent: Nixon Peabody, LLP

20090111248 - Manufacturing method of soi substrate: A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate;... Agent: Eric Robinson

20090111249 - Multilevel phase change memory: A multilevel phase change memory may be formed of a chalcogenide material formed between a pair of spaced electrodes. The cross-sectional area of the chalcogenide material may decrease as the material extends from one electrode to another. As a result, the current density decreases from one electrode to the other.... Agent: Trop, Pruner & Hu, P.C.

20090111250 - Method for preparing compound semiconductor substrate: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate... Agent: Ladas & Parry LLP

20090111251 - Exposure mask and method for fabricating thin-film transistor: An exposure mask includes a transparent substrate; a first pattern portion formed on the transparent substrate using at least one light-shielding pattern having a predetermined shape; and a translucent layer which is formed at a section including a first pattern region having the first pattern portion, which allows exposure light... Agent: Oliff & Berridge, PLC

20090111252 - Method for forming deep well region of high voltage device: A method of fabricating a deep well region of a high voltage device is provided. The method includes designating a deep well region that includes a designated highly doped region and a designed scarcely doped region in a substrate. A mask layer, which covers a periphery of the designated deep... Agent: J C Patents, Inc.

20090111253 - Method for producing a transistor gate with sub-photolithographic dimensions: Methods of fabricating compound semiconductor devices are described.... Agent: Kathy Manke Avago Technologies Limited

20090111254 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate including a pattern for forming a multi-plane channel, forming a columnar polysilicon layer over the insulation layer and filling in the pattern, and performing a thermal treatment process.... Agent: Townsend And Townsend And Crew, LLP

20090111255 - Method for fabricating transistor in semiconductor device: Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer... Agent: Marshall, Gerstein & Borun LLP

20090111256 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed... Agent: Townsend And Townsend And Crew, LLP

20090111257 - Techniques for impeding reverse engineering: Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the... Agent: Michael J. Chang, LLC

20090111258 - Method for manufacturing a semiconductor device: A manufacturing method of a semiconductor device wherein a metal pad is etched to form a trench in which a central part is concave in form, or to form a trench in the shape of a cylinder or a parallelepiped on the edge part of a metal pad. Accordingly, the... Agent: Marshall, Gerstein & Borun LLP

20090111259 - Methods for forming connective elements on integrated circuits for packaging applications: Methods for forming connective elements on integrated circuits for packaging applications are provided herein. In some embodiments, a method of forming connective elements on an integrated circuit for flipchip packaging may include providing a resist layer on the integrated circuit; forming a plurality of holes through the resist layer; filling... Agent: MoserIPLaw Group / Applied Materials, Inc.

20090111260 - Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument: The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such... Agent: Oliff & Berridge, PLC

20090111261 - Over-passivation process of forming polymer layer over ic chip: A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees... Agent: Mou-shiung Lin

20090111262 - Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation: A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower... Agent: Mcdermott Will & Emery LLP

20090111263 - Method of forming programmable via devices: A device is formed by providing a contact via in a dielectric layer, providing a capping layer overlying at least a portion of the contact via, and forming a conductive element in physical contact with the capping layer. The conductive element is formed using a masked deposition process. This process... Agent: Ryan, Mason & Lewis, LLP

20090111264 - Plasma-enhanced cyclic layer deposition process for barrier layers: In one embodiment, a method for depositing materials on a substrate is provided which includes forming a titanium nitride barrier layer on the substrate by sequentially exposing the substrate to a titanium precursor containing a titanium organic compound and a nitrogen plasma formed from a mixture of nitrogen gas and... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090111265 - Selective silicide formation using resist etchback: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask... Agent: Amin, Turocy & Calvin, LLP

20090111266 - Method of forming gate of semiconductor device: A method of forming a gate of a semiconductor device comprising providing a semiconductor substrate over which a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed, the semiconductor substrate defining gate line regions; removing he second conductive layer between gate... Agent: Marshall, Gerstein & Borun LLP

20090111267 - Method of anti-stiction dimple formation under mems: A method for making a MEMS structure comprises patterning recesses in a dielectric layer overlying a substrate, each recess being disposed between adjacent mesas of dielectric material. A conformal layer of semiconductor material is formed overlying the recesses and mesas. The conformal layer is chemical mechanically polished to form a... Agent: Freescale Semiconductor, Inc. Law Department

20090111268 - Reworking method for integrated circuit devices: A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming... Agent: North America Intellectual Property Corporation

20090111270 - Method for forming patterns in semiconductor memory device: A method for forming patterns in a semiconductor memory device, wherein first spacers arranged at a first spacing and second spacers arranged at a second spacing are formed on a target layer which is formed on a semiconductor substrate. A mask pattern is formed to cover a portion of the... Agent: Marshall, Gerstein & Borun LLP

20090111269 - Silicon wafer reclamation process: By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels... Agent: Duane Morris LLP (tsmc)IPDepartment

20090111271 - Isotropic silicon etch using anisotropic etchants: Methods for isotropically etching a monocrystalline silicon wafer. An example method includes applying a layer of material at least one of onto a first side or into a first side of the monocrystalline silicon wafer and isotropically etching a non-linear pit into the monocrystalline silicon wafer using an anisotropic etchant.... Agent: Honeywell International Inc.

20090111273 - Method for manufacturing semiconductor device: The invention defines a pillar pattern or an island pattern by forming a contact hole and filling the contact hole with a hard mask material by using a spacer formation process, so that the mask pattern formation process margin for island (e.g., pillar) pattern formation is increased. Accordingly, the yield... Agent: Marshall, Gerstein & Borun LLP

20090111272 - Method of forming strain-causing layer for mos transistors and process for fabricating strained mos transistors: A method of forming a strain-causing layer for MOS transistors is provided, which is applied to a substrate having a plurality of gate structures of the MOS transistors thereon. A non-conformal stressed film that is thicker on the gate structures than between the gate structures is formed over the substrate.... Agent: J C Patents, Inc.

20090111274 - Methods of manufacturing a semiconductor device and apparatus and etch chamber for the manufacturing of semiconductor devices: Methods of manufacturing a semiconductor device, apparatus and etch chamber for the manufacturing of semiconductor devices are provided. Embodiments are related to the rotating of a semiconductor substrate round an axis perpendicular to its surface during etching or reactive deposition processes, and irradiating a semiconductor substrate non-uniformly during etching or... Agent: Slater & Matsil, L.L.P.

20090111275 - Plasma etching method and storage medium: A plasma etching method that can prevent residues from becoming attached to bottoms and sides of via holes and trenches. An interlayer insulation film formed of CwFx (x and w are predetermined natural numbers) and a metallic layer or a metal-containing layer formed on a substrate are exposed at the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090111276 - Temperature control module using gas pressure to control thermal conductance between liquid coolant and component body: A temperature control module for a semiconductor processing chamber comprises a thermally conductive component body, one or more channels in the component body and one or more tubes concentric therewith, such that gas filled spaces surround the tubes. By flowing a heat transfer liquid in the tubes and adjusting the... Agent: Buchanan, Ingersoll & Rooney PC

20090111277 - Wet photoresist strip for wafer bumping with ozonated acetic anhydride: Methods for stripping a photoresist from a substrate and for fabricating wafer bumps are provided herein. In some embodiments, a method of stripping a photoresist from a substrate includes providing a substrate having a patterned photoresist deposited thereon; and stripping the photoresist from the substrate using a stripping solution comprising... Agent: MoserIPLaw Group / Applied Materials, Inc.

20090111278 - Manufacturing method for semiconductor device and manufacturing apparatus for semiconductor device: A manufacturing method for a semiconductor device includes retaining a wafer in a reaction chamber, supplying first process gas including source gas and second process gas containing H2 or inert gas onto the wafer in a rectified state alternately in a predetermined cycle, rotating the wafer, and heating the wafer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090111279 - Functional film containing structure and method of manufacturing functional film: A method of manufacturing a functional film by which a functional film formed on a film formation substrate can be easily peeled from the film formation substrate. The method includes the steps of: (a) forming a separation layer on a substrate by using an inorganic material which is decomposed to... Agent: Sughrue Mion, PLLC

20090111280 - Method for removing oxides: A method for removing native oxides from a substrate surface is provided. In one embodiment, the method comprises positioning a substrate having an oxide layer into a processing chamber, generating a plasma of a reactive species from a gas mixture within the processing chamber, exposing the substrate to the reactive... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090111281 - Frequency doubling using a photo-resist template mask: A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20090111282 - Methods of using thin metal layers to make carbon nanotube films, layers, fabrics, ribbons, elements and articles: Methods of using thin metal layers to make Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles are disclosed. Carbon nanotube growth catalyst is applied on to a surface of a substrate, including one or more thin layers of metal. The substrate is subjected to a chemical vapor deposition of... Agent: Wilmerhale/boston

20090111283 - Method for forming interlayer insulating film of semiconductor device: A method for forming an interlayer insulating film of a semiconductor device comprises forming an active pattern over a substrate, forming a spin-on dielectric film over the substrate including the active pattern, and irradiating an electron beam over the spin on dielectric film to form an interlayer insulating film.... Agent: Marshall, Gerstein & Borun LLP

20090111284 - Method for silicon based dielectric chemical vapor deposition: Embodiments of the invention generally provide a method for depositing silicon-containing films. In one embodiment, a method for depositing silicon-containing material film on a substrate includes heating a substrate disposed in a processing chamber to a temperature less than about 550 degrees Celsius; flowing a nitrogen and carbon containing chemical... Agent: MoserIPLaw Group / Applied Materials, Inc.

20090111285 - Substrate treatment apparatus, method for manufacturing substrate, and method for manufacturing semiconductor device: [Means for Resolution] A substrate treatment apparatus 100 includes: a reaction tube 42 for treating a substrate 54; a heater 46 for heating the substrate 54 in the reaction tube 42; a cooling air channel 72 for circulating cooling air 70 outside the reaction tube 42; and a thermocouple 82... Agent: Oliff & Berridge, PLC

20090104718 - Method of magnetic tunneling layer processes for spin-transfer torque mram: A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers... Agent: Saile Ackerman LLC

20090104720 - Photoresist coating apparatus having nozzle monitoring unit and method for supplying photoresist using the same: Provided are a photoresist coating apparatus and a method of coating photoresist using the same. The apparatus includes a photoresist supply line through which photoresist is supplied. A fluid control valve is connected to the photoresist supply line to control the flow of the photoresist. A nozzle assembly is connected... Agent: Greenlee Winner And Sullivan P C

20090104719 - Plasma doping system with in-situ chamber condition monitoring: A method of in-situ monitoring of a plasma doping process includes generating a plasma comprising dopant ions in a chamber proximate to a platen supporting a substrate. A platen is biased with a bias voltage waveform having a negative potential that attracts ions in the plasma to the substrate for... Agent: Rauschenbach Patent Law Group, LLC

20090104721 - Deposition method and method for manufacturing light emitting device: An object is to provide a deposition method by which a film having a desired shape can be formed with high productivity. Further, a method for manufacturing a light emitting device by which a light emitting device having high definition can be manufactured with high productivity is provided. Specifically, even... Agent: Cook Alex Ltd.

20090104722 - Method for manufacturing pixel structure: A method for manufacturing a pixel structure includes providing a substrate having an active device thereon and forming a dielectric layer covering the active device. The dielectric layer has a contact hole disposed over the active device. Next, a first photoresist layer is formed on the dielectric layer over the... Agent: Jianq Chyun Intellectual Property Office

20090104725 - Liquid crystal display device and method for manufacturing the same: A liquid crystal display device includes first and second substrates bonded to each other, first column spacers on the first substrate, protrusions on the second substrate that contact a center portion of an upper surface of the spacers, respectively, recesses formed in the second substrate surrounding the protrusions, respectively, and... Agent: Holland & Knight LLP

20090104723 - Method for manufacturing display device: Etching is performed using mask layers formed by a multi-tone mask which is a light-exposure mask through which light is transmitted to have a plurality of intensity, in a method for manufacturing a display device including an inverted staggered thin film transistor with a channel-etched structure. Further, a gate wiring... Agent: Fish & Richardson P.C.

20090104724 - Method of manufacturing liquid crystal display device: A method of manufacturing a liquid crystal display device which includes pixel electrodes and common electrodes which are alternatively arranged in each pixel defined on a substrate, including the steps of: forming a conductive film on the substrate; forming a mask layer, of which etching selection ratio is different from... Agent: Mckenna Long & Aldridge LLP

20090104726 - Led fabrication via ion implant isolation: A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the... Agent: Summa, Additon & Ashe, P.A.

20090104727 - High power semiconductor laser diodes: A high power laser source comprises a bar of laser diodes, a submount onto which said laser bar is affixed, and a cooler onto which said submount is affixed. The laser bar has a first coefficient of thermal expansion (CTEbar), the submount has a second coefficient of thermal expansion (CTEsub),... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20090104728 - Gallium nitride-based compound semiconductor multilayer structure and production method thereof: An object of the present invention is to provide a gallium nitride compound semiconductor multilayer structure useful for producing a gallium nitride compound semiconductor light-emitting device which operates at low voltage while maintaining satisfactory light emission output. The inventive gallium nitride compound semiconductor multilayer structure comprises a substrate, and an... Agent: Sughrue Mion, PLLC

20090104729 - Solid-state image sensor and imaging system: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.... Agent: Canon U.s.a. Inc. Intellectual Property Division

20090104730 - Methods for fabricating a cmos image sensor: A method for fabricating a CMOS image sensor includes providing a substrate having a sensor array region and a peripheral region defined thereon, forming at least a contact pad on the substrate of the peripheral region, forming a first dielectric layer covering the contact pad on the substrate, performing a... Agent: North America Intellectual Property Corporation

20090104731 - Semiconductor device and manufacturing method thereof: A semiconductor device manufacturing method including a process of forming a silicon oxide film by thermally oxidizing silicon in the atmosphere of oxygen gas or in the atmosphere of mixed gas of oxygen and hydrogen at a temperature of 800° C. or more in the state in which at least... Agent: Sonnenschein Nath & Rosenthal LLP

20090104732 - Cvd process gas flow, pumping and/or boosting: The present invention generally comprises a method and apparatus for supplemental pumping, gas feed, and/or RF current for a process. When depositing amorphous silicon, the amount of process gases, RF current, and vacuum may be less than the amount of process gases, RF current, and vacuum necessary to deposit microcrystalline... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090104733 - Microcrystalline silicon deposition for thin film solar applications: Embodiments of the invention as recited in the claims relate to thin film multi-junction solar cells and methods and apparatuses for forming the same. In one embodiment a method of forming a thin film multi-junction solar cell over a substrate is provided. The method comprises positioning a substrate in a... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090104734 - Power semiconductor module method: A method for assembling a power module includes providing a casing with a plurality of receiving elements. At least one substrate carrying at least one semiconductor chip is provided within the casing. At least one support element is provided. An elastically stressed cover is arranged over the at least one... Agent: Dicke, Billig & Czaja

20090104735 - Semiconductor package having increased resistance to electrostatic discharge: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to... Agent: Lsi Corporation

20090104736 - Stacked packaging improvements: A plurality of microelectronic assemblies (60) are made by severing an in-process unit including an upper substrate (40) and lower substrate (20) with microelectronic elements (36) disposed between the substrates. In a further embodiment, a lead frame (452) is joined to a substrate (440) so that the leads project from... Agent: Tessera Lerner David Et Al.

20090104737 - Method for manufacturing tft substrate: To provide a method for manufacturing a TFT substrate in which a channel length can be stably formed while the number of masks is reduced, and a method for manufacturing a TFT substrate which can individually control impurity concentrations for channels of an n-type TFT and a p-type TFT without... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090104738 - Method of forming vias in silicon carbide and resulting devices and circuits: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for... Agent: Summa, Additon & Ashe, P.A.

20090104739 - Method of forming conformal silicon layer for recessed source-drain: Processes for non-selectively forming one or more conformal silicon-containing epitaxial layers on recess corners are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of a non-selective epitaxial layer... Agent: Diehl Servilla LLC

20090104740 - Semiconductor device producing method: Disclosed is a producing method of a semiconductor device, including: loading a silicon substrate into a processing chamber, the silicon substrate having a silicon nitride film or a silicon oxide film on at least a portion of a surface thereof and a silicon surface being exposed from the surface; and... Agent: Birch Stewart Kolasch & Birch

20090104741 - Methods of fabricating semiconductor devices using a plasma process with non-silane gas including deuterium: Semiconductor devices are fabricated using a plasma process with a non-silane gas that includes deuterium, and which may result in improved device reliability and/or other improved device operational characteristics. One such method can include forming a gate oxide layer on a transistor region, which is defined on a substrate, and... Agent: Myers Bigel Sibley & Sajovec

20090104742 - Methods for forming gate electrodes for integrated circuits: A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of semiconducting multilayer features on the substrate surface, the features comprising a base layer and a compositionally different capping layer on the base layer. The method can... Agent: Texas Instruments Incorporated

20090104743 - Nitrogen profile in high-k dielectrics using ultrathin disposable capping layers: Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric... Agent: Texas Instruments Incorporated

20090104744 - Vertical gated access transistor: According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of... Agent: Knobbe Martens Olson & Bear LLP

20090104745 - Integration method for dual doped polysilicon gate profile and cd control: In accordance with the present teachings, methods of making dual doped polysilicon gates are provided. The method can include providing a semiconductor structure including a plurality of polysilicon gates having a first critical dimension disposed over a dielectric layer and planarizing the plurality of polysilicon gates with a spin-on material... Agent: Texas Instruments Incorporated

20090104746 - Channel strain induced by strained metal in fet source or drain: A process for forming a FET (e.g., an n-FET or a p-FET), in which during formation a metal which makes up a source or drain of the transistor is stressed so that stress is induced in a semiconductor channel of the transistor.... Agent: Sonnenschein Nath & Rosenthal LLP

20090104747 - Method for fabricating deep trench dram array: A method for fabricating deep trench DRAM array is disclosed. A substrate having thereon a memory array area is provided. An array of deep trench patterns is formed in the memory array area. The deep trench (DT) capacitor patterns include first dummy DT patterns in a first column, second dummy... Agent: North America Intellectual Property Corporation

20090104748 - Method for fabricating self-aligned recess gate trench: A method for forming a recess gate trench includes a plurality of trench capacitors formed into a substrate having thereon a pad layer. A portion of the trench top oxide layer of each trench capacitor is etched away to form a hole. The hole is filled with a silicon layer... Agent: North America Intellectual Property Corporation

20090104749 - Methods of manufacturing semiconductor devices having contact plugs in insulation layers: Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from... Agent: Myers Bigel Sibley & Sajovec

20090104750 - Method for manufacturing semiconductor substrate, display panel, and display device: If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single... Agent: Eric Robinson

20090104751 - Narrow semiconductor trench structure: Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20090104752 - Method for producing soi wafer: The present invention relates to a method for producing an SOI wafer, having at least a step of a bonding heat treatment for increasing bonding strength by heat-treating a bonded wafer obtained by bonding a base wafer and a bond wafer, in which argon is ion-implanted from a surface of... Agent: Oliff & Berridge, PLC

20090104753 - Process of forming a curved profile on a semiconductor substrate: A semiconductor substrate is shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The... Agent: Edwards Angell Palmer & Dodge LLP

20090104754 - Method to improve electrical leakage performance and to minimize electromigration in semiconductor devices: Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices are generally described herein. Other embodiments may be described and claimed.... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20090104755 - High quality silicon oxide films by remote plasma cvd from disilane precursors: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a... Agent: Townsend And Townsend And Crew LLP

20090104756 - Method to form a rewriteable memory cell comprising a diode and a resistivity-switching grown oxide: A method is described to form a rewriteable memory cell including a diode and an oxide layer, wherein the resistivity of the oxide layer can be reversibly switched. In preferred embodiments, the oxide layer is a grown oxide. The diode is preferably formed of polysilicon which has been crystallized in... Agent: Dugan & Dugan, PC

20090104758 - Gallium nitride materials and methods: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in... Agent: Wolf Greenfield & Sacks, P.C.

20090104757 - Method for producing group iii nitride-based compound semiconductor: An object of the present invention is to remove micro-scratches on a surface of a GaN substrate cut from a GaN ingot. The invention is directed to establish a method for surface treatment of a GaN substrate, including heating the surface in an atmosphere containing trimethylgallium, ammonia, and hydrogen. It... Agent: Mcginn Intellectual Property Law Group, PLLC

20090104759 - Methods of manufacturing semiconductor devices including a doped silicon layer: Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon... Agent: Myers Bigel Sibley & Sajovec

20090104760 - Vertical cvd appparatus for forming silicon-germanium film: A vertical CVD apparatus is arranged to process a plurality of target substrates all together to form a silicon germanium film. The apparatus includes a reaction container having a process field configured to accommodate the target substrates, and a common supply system configured to supply a mixture gas into the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090104761 - Plasma doping system with charge control: A method of plasma doping includes generating a plasma comprising dopant ions proximate to a platen supporting a substrate in a plasma chamber. The platen is biased with a bias voltage waveform having a negative potential that attracts ions in the plasma to the substrate for plasma doping. At least... Agent: Rauschenbach Patent Law Group, LLC

20090104762 - Semiconductor device and method for fabricating the same: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions... Agent: Mcdermott Will & Emery LLP

20090104763 - Method of fabricating flash memory device: The present disclosure relates to a method of fabricating a flash memory device. According to the present disclosure, a hard mask layer to which surface roughnesses have been transferred by a metal silicide layer, including the surface roughness, is polished before or during a gate etch process in order to... Agent: Marshall, Gerstein & Borun LLP

20090104764 - Methods and systems for forming at least one dielectric layer: A method for forming a structure includes forming at least one feature across a surface of a substrate. A nitrogen-containing dielectric layer is formed over the at least one feature. A first portion of the nitrogen-containing layer on at least one sidewall of the at least one feature is removed... Agent: Townsend And Townsend And Crew LLP

20090104765 - Semiconductor device having diffusion layers as bit lines and method for manufacturing the same: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films... Agent: Mcdermott Will & Emery LLP

20090104766 - Method of forming micro metal bump: The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate. The method comprises the steps... Agent: Birch Stewart Kolasch & Birch

20090104767 - Methods for fabricating residue-free contact openings: A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disposed over a metal-containing trace disposed... Agent: Trask Britt, P.C./ Micron Technology

20090104768 - Method for forming metal line in semiconductor device: A method for forming a metal line in a semiconductor device may include forming a silicon (Si) monolayer as an etching prevention layer over an exposed portion of a lower metal layer and sidewalls of an upper metal layer, middle metal layer, and the entire surface of curved photoresist patterns.... Agent: Sherr & Vaughn, PLLC

20090104769 - Semiconductor chip with coil element over passivation layer: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first... Agent: Mou-shiung Lin

20090104770 - Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor.... Agent: Sonnenschein Nath & Rosenthal LLP

20090104771 - Method for making a self-converged void and bottom electrode for memory cell: A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090104772 - Process of fabricating circuit structure: A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded... Agent: J C Patents, Inc.

20090104773 - Method of forming contact: A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process... Agent: Jianq Chyun Intellectual Property Office

20090104775 - Method for forming tantalum nitride film: A tantalum nitride film rich in tantalum atoms is formed, according to the CVD technique, by simultaneously introducing a raw gas consisting of a coordination compound constituted by an elemental tantalum (Ta) having a coordinated ligand represented by the general formula: N=(R, R′) (in the formula, R and R′ may... Agent: Arent Fox LLP

20090104774 - Method of manufacturing a semiconductor device: This invention relates to a method of manufacturing a semiconductor device. In this method, a semiconductor device is provided comprising a substrate (10), the substrate (10) being covered with a low-k precursor layer (20) having a surface (25). After this step, a partial curing step is performed in which a... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090104776 - Methods for forming nested and isolated lines in semiconductor devices: A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein... Agent: Cantor Colburn LLP - IBM Fishkill

20090104777 - Methods of depositing a ruthenium film: Cyclical methods of depositing a ruthenium layer on a substrate are provided. In one process, initial or incubation cycles include supplying alternately and/or simultaneously a ruthenium precursor and an oxygen-source gas to deposit ruthenium oxide on the substrate. The ruthenium oxide deposited on the substrate is reduced to ruthenium, thereby... Agent: Knobbe Martens Olson & Bear LLP

20090104778 - Polishing composition for cmp and device wafer producing method using the same: wherein R represents one selected from a hydroxyl-substituted or unsubstituted alkyl group having one to eighteen carbon atoms, a hydroxyl-substituted or unsubstituted alkenyl or alkapolyenyl group having two to eighteen carbon atoms, an acyl group having two to twenty-four carbon atoms, and hydrogen atom; and “n” denotes an average degree... Agent: Birch Stewart Kolasch & Birch

20090104779 - Method of producing phase change memory device: An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be... Agent: Foley And Lardner LLP Suite 500

20090104780 - Method for manufacturing semicondcutor device: A method for manufacturing a semiconductor device includes forming an ONO layer in a memory region and forming several gate oxide layer patterns in a logic region, a nitride layer in the logic region can be used as a hard mask, enabling a reduction in the number of masks used.... Agent: Sherr & Vaughn, PLLC

20090104781 - Plasma processing apparatus, ring member and plasma processing method: [Solution] A ring member formed of an insulating material is disposed to surround a to-be-treated substrate in a processing vessel and an electrode is installed in the ring member for adjusting a plasma sheath region. For example, a first DC voltage is applied to the electrode when a first process... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090104782 - Selective etching of silicon nitride: Methods for etching dielectric layers comprising silicon and nitrogen are provided herein. In some embodiments, such methods may include providing a substrate having a dielectric layer comprising silicon and nitrogen disposed thereon, forming reactive species from a process gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) using a remote plasma;... Agent: MoserIPLaw Group / Applied Materials, Inc.

20090104783 - Asher, ashing method and impurity doping apparatus: The invention provides the asher for plasma ashing the surface hardening layer formed on the resist and the internal nonhardening layer, the resist for use as a mask coated on the semiconductor substrate and doped with impurity, characterized by comprising an elipsometer for causing a linearly polarized light to enter... Agent: Mcdermott Will & Emery LLP

20090104784 - Functional film containing structure and method of manufacturing functional film: A method of manufacturing a functional film by which the functional film formed on a film formation substrate can be easily peeled from the film formation substrate. The method includes the steps of: (a) forming a separation layer by using an inorganic material on a substrate containing a material having... Agent: Sughrue Mion, PLLC

20090104785 - Patterning method for light-emitting devices: A method of patterning a substrate by mechanically locating a first masking film over the substrate; removing one or more first opening portions in first locations in the first masking film to form one or more first masking portions in the first masking film. First materials are deposited over the... Agent: David Novais Patent Legal Staff

20090104786 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device includes depositing a first film on a workpiece film so that a resist is formed on the first film, processing the first film with the resist serving as a mask, depositing a second film along the first film, processing the second film so... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090104787 - Plasma nitriding method, method for manufacturing semiconductor device and plasma processing apparatus: A nitriding process is performed at a process temperature of 500° C. or more by causing microwave-excited high-density plasma of a nitrogen-containing gas to act on silicon in the surface of a target object, inside a process container of a plasma processing apparatus. The plasma is generated by supplying microwaves... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090104788 - Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device: A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a... Agent: Robert J. Depke Lewis T. Steadman

20090104789 - Method and system for improving dielectric film quality for void free gap fill: A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing... Agent: Townsend And Townsend And Crew LLP

20090104790 - Methods for forming a dielectric layer within trenches: A method for forming a semiconductor structure includes reacting a silicon precursor and an atomic oxygen or nitrogen precursor at a processing temperature of about 150° C. or less to form a silicon oxide or silicon-nitrogen containing layer over a substrate. The silicon oxide or silicon-nitrogen containing layer is ultra-violet... Agent: Townsend And Townsend And Crew LLP

20090104791 - Methods for forming a silicon oxide layer over a substrate: A method of depositing a silicon oxide layer over a substrate includes providing a substrate to a deposition chamber. A first silicon-containing precursor, a second silicon-containing precursor and a NH3 plasma are reacted to form a silicon oxide layer. The first silicon-containing precursor includes at least one of Si—H bond... Agent: Townsend And Townsend And Crew LLP

20090104792 - Semiconductor device producing method: Disclosed is a producing method of a semiconductor device, including: loading at least one substrate formed on a surface thereof with a tungsten film into a processing chamber; and forming a silicon oxide film on the surface of the substrate which includes the tungsten film by alternately repeating following steps... Agent: Birch Stewart Kolasch & Birch

20090098664 - Ferroelectric thin film device and method of manufacturing the same: The present invention relates to a method of manufacturing a ferroelectric thin film device, and, more particularly, to a method of manufacturing a ferroelectric thin film device having high crystallinity, good surface roughness and high deposition efficiency through on-axis type sputtering, and to a ferroelectric thin film device manufactured using... Agent: Intellectual Property Group Fredrikson & Byron, P.A.

20090098665 - Methodology of implementing ultra high temperature (uht) anneal in fabricating devices that contain sige: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high... Agent: Texas Instruments Incorporated

20090098666 - Chip package assembly using chip heat to cure and verify: Methods of assembling a chip package are disclosed that employ heat from test pattern operation of the chip to cure a thermal interface material. The methods may also simultaneously verify thermal performance of the package using the heat from test pattern operation. Further, the heat may be used to cure... Agent: Hoffman Warnick LLC

20090098667 - Method for picking up semiconductor chips from a wafer table and method for mounting semiconductor chips on a substrate: The invention relates to a method for picking up semiconductor chips from a wafer table and, optionally, their mounting on a substrate by means of a pick-and-place system. The position and orientation of the semiconductor chip to be mounted next are determined by means of a first camera and made... Agent: Nixon Peabody LLP

20090098668 - Method and apparatus to facilitate testing of printed semiconductor devices: A printing platform receives (102) (preferably in-line with a semiconductor device printing process (101)) a substrate having at least one semiconductor device printed thereon and further having a test structure printed thereon, which test structure comprises at least one printed semiconductor layer. These teachings then provide for the automatic testing... Agent: Motorola/fetf

20090098669 - Semiconductor device manufacturing method and semiconductor device manufacturing apparatus: A semiconductor device manufacturing method and a semiconductor device manufacturing apparatus which enable to detect an etching end-point with high accuracy are provided. In etching of a lower layer formed on a semiconductor wafer using a mask which comprises a plurality of patterns extending in a predetermined direction (line-and-space patterns)... Agent: Mcdermott Will & Emery LLP

20090098670 - Semiconductor device for monitoring current characteristic and monitoring method for current characteristic of semiconductor device: A method for monitoring current characteristics of a semiconductor device includes forming an isolation layer and a well area over a substrate, and then forming a P+ area and an N+ area spaced apart by the isolation layer to define active areas, and then forming a gate oxide layer over... Agent: Sherr & Vaughn, PLLC

20090098671 - Nanotube assembly including protective layer and method for making the same: Nanotube assemblies and methods for manufacturing the same, including one or more protective layers. A nanotube assembly may include a substrate, a nanotube array, formed on the substrate, and a protective layer, formed on a first area of the substrate where the nanotube array is not, the protective layer reducing... Agent: Harness, Dickey & Pierce, P.L.C

20090098672 - Method for making a heat dissipating device for led installation: A method for making a heat dissipating device for LED installation, comprising the steps of a) preparing a thermal member having a metal surface, b) covering at least a part of the metal surface of the thermal member with a electrically insulative thermal conductivity layer, and c) providing multiple conducting... Agent: Bacon & Thomas, PLLC

20090098673 - Thin film transistor array panel and method for manufacturing the same: A TFT array panel-including a substrate, a gate line having a gate electrode, a gate insulating layer formed on the gate line, a data line having a source electrode and a drain electrode spaced apart from the source electrode, a passivation layer formed on the data line and the drain... Agent: Macpherson Kwok Chen & Heid LLP

20090098674 - Manufacturing method of semiconductor device: To realize high performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type... Agent: Eric Robinson

20090098675 - Method for manufacturing semiconductor light-emitting device: A method of manufacturing a semiconductor light-emitting device includes steps of forming a vertical cavity structure including a layer to be oxidized on a semiconductor substrate, and then forming a circular groove having a depth which penetrates at least the layer to be oxidized from an upper surface of the... Agent: Rader Fishman & Grauer PLLC

20090098676 - Method of manufacturing light emitting diode: A method of manufacturing a light emitting diode includes forming an active layer of a nitride semiconductor on a first conductive type of a nitride semiconductor layer, thermally treating the active layer at a first temperature, and forming a second conductive type of a nitride semiconductor layer on the active... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090098677 - Group iii-v nitride-based semiconductor substrate, group iii-v nitride-based device and method of fabricating the same: A group III-V nitride-based semiconductor substrate has: a first layer made of GaN single crystal; and a second layer formed on the first layer, the second layer made of group III-V nitride-based semiconductor single crystal represented by AlxGa1-xN, where 0.9>x≦1, wherein a top surface and a back surface of the... Agent: Foley And Lardner LLP Suite 500

20090098678 - Vacuum jacketed electrode for phase change memory element: A memory device having a vacuum jacket around the first electrode element for improved thermal isolation. The memory unit includes a first electrode element; a phase change memory element in contact with the first electrode element; a dielectric fill layer surrounding the phase change memory element and the first electrode... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090098679 - Cmos solid-state imaging device and method of manufacturing the same as well as drive method of cmos solid-state imaging device: Adjacent pixels are separated by an element isolation portion formed of a diffusion layer and an insulating layer thereon, and the insulating layer of the element isolation portion is formed in a position equal to or shallower than the position of a pn junction on the side of an accumulation... Agent: Sonnenschein Nath & Rosenthal LLP

20090098680 - Backplane structures for solution processed electronic devices: There is provided a backplane for an organic electronic device. The backplane has a TFT substrate having a multiplicity of electrode structures thereon; a bank structure defining pixel areas over the electrode structures; and a thin layer of insulative inorganic material between the electrode structures and the bank structures. The... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20090098681 - Process for manufacturing a cbram memory having enhanced reliability: The invention relates to a process for manufacturing a plurality of CBRAM memories, each comprising a memory cell in a chalcogenide solid electrolyte, an anode, and a cathode, the process comprising implementing a sublayer of a high thermal conductivity material, higher than 1.3 W/m/K, which covers the set of contacts,... Agent: Pearne & Gordon LLP

20090098682 - Method for singulating a group of semiconductor packages that contain a plastic molded body: A method for singulating a group of semiconductor packages containing a plastic molded body. The singulation of the semiconductor packages is effected along a predetermined separation area, wherein, in the predetermined separation area, a metallic layer extending over at least a partial section of the predetermined separation area has to... Agent: Lerner Greenberg Stemer LLP

20090098683 - Method for cutting solid-state image pickup device: A method for cutting a solid-state image pickup device with high accuracy and high quality is provided which does not cause any chipping and prevents damages to a wafer surface. A temporary bonding agent is coated to a back surface of a glass cover plate which is opposite to the... Agent: Birch Stewart Kolasch & Birch

20090098684 - Method of producing a thin semiconductor chip: A method of fabricating a semiconductor chip includes the providing an adhesive layer on the outer area of the active surface of a device wafer and attaching a rigid body to the active surface by the adhesive layer. The device wafer is thinned by treating the passive surface of the... Agent: Edell , Shapiro & Finnan , LLC

20090098685 - Low cost hermetically sealed package: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the... Agent: Texas Instruments Incorporated

20090098686 - Method of forming premolded lead frame: A method of forming a pre-molded lead frame having increased stand-offs includes the steps of attaching a first tape to a first side of the lead frame and a second tape to a second side of the lead frame. The taped lead frame is placed in a mold and a... Agent: Freescale Semiconductor, Inc. Law Department

20090098687 - Integrated circuit package including wire bonds: It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 μm or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding... Agent: Mendelsohn & Associates, P.C.

20090098688 - Imprint method, chip production process, and imprint apparatus: An imprint method is constituted by a step of curing a resin material formed on a substrate in a state in which an imprint pattern of a mold is in contact or proximity with the resin material, and a step of parting the mold from the cured resin material. The... Agent: Fitzpatrick Cella Harper & Scinto

20090098689 - Electrical fuse and method of making: A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing... Agent: Greenblum & Bernstein, P.L.C

20090098690 - Manufacturing method of semiconductor device: To realize high 2 performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity... Agent: Eric Robinson

20090098691 - Manufacturing process of thin film transistor: A thin film transistor includes a gate, a gate insulator layer, a channel layer, a source, a drain, and an ohmic contact layer. The gate insulator layer covers the gate; the channel layer is disposed on the gate insulator layer above the gate; the source and the drain are disposed... Agent: J C Patents, Inc.

20090098692 - Method for fabricating a semiconductor gate structure: A method of making a semiconductor device is disclosed. A mask if formed over a first and a second region of a semiconductor body, and a vertical diffusion barrier is formed in a region between the first and second regions. A mask is then formed over the second region and... Agent: Slater & Matsil LLP

20090098693 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes: forming a first region and a second region at a main surface of a semiconductor substrate; forming a gate insulating film containing Hf or Zr and oxygen on the first region and the second region; forming a first metallic film on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090098694 - Cd gate bias reduction and differential n+ poly doping for cmos circuits: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of... Agent: Texas Instruments Incorporated

20090098695 - Differential offset spacer: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a... Agent: Texas Instruments Incorporated

20090098696 - Fabrication process of a semiconductor device having a capacitor: A method of manufacturing a semiconductor device includes forming a first trench in a capacitor device region of a semiconductor substrate, forming a capacitor insulation film over a sidewall surface of the first trench, forming a semiconductor film to cover the first trench, a resistor device region of the semiconductor... Agent: Ipusa, P.l.l.c

20090098697 - Ferroelectric capacitor and ferroelectric memory with ir-ru alloy electrode and method of manufacturing the same: A ferroelectric capacitor comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer. A ferroelectric memory comprises a substrate and a plurality of memory cells arranged on the substrate. Each memory cell... Agent: Buchanan, Ingersoll & Rooney PC

20090098698 - Memory device and fabrication thereof: A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface... Agent: Quintero Law Office, PC

20090098699 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device. In one example embodiment of the present invention, a method for manufacturing a semiconductor device includes various steps. First, a gate pattern is formed on a substrate. Next, a first oxide layer is formed on the gate pattern. Then, a second oxide layer,... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090098700 - Method of fabricating a non-volatile memory device: A method of fabricating a non-volatile memory device prevents the threshold voltage of a program-inhibited cell from rising by preventing hot carriers, generated in a semiconductor substrate near a select line, from being injected into a floating gate of the program-inhibited cell. The program-inhibited cell shares a word line adjacent... Agent: Townsend And Townsend And Crew, LLP

20090098701 - Method of manufacturing an integrated circuit: The present invention provides a method of manufacturing an integrated circuit comprising the steps of: providing a semiconductor substrate, etching at least one trench into a surface of said semiconductor substrate, performing an ion implantation step, wherein a direction of said ion implantation step is parallel to a vertical centre... Agent: Fay Kaplun & Marcin, LLP

20090098702 - Method to form cmos circuits using optimized sidewalls: A method of forming reduced width STI field oxide elements using sidewall spacers on the isolation hardmask to reduce the STI trench width is disclosed. The isolation sidewall spacers are formed by depositing a conformal layer of spacer material on the isolation hardmask and performing an anisotropic etch. The isolation... Agent: Texas Instruments Incorporated

20090098703 - Methods of fabricating semiconductor devices having resistors: A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower... Agent: Myers Bigel Sibley & Sajovec

20090098704 - Method for manufacturing soi substrate: A method is demonstrated to manufacture SOI substrates with high throughput while resources can be effectively used. The present invention is characterized by the feature in which the following process A and process B are repeated. The process A includes irradiation of a surface of a semiconductor wafer with cluster... Agent: Eric Robinson

20090098705 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device according to one embodiment includes: forming a gate electrode by shaping a semiconductor film formed above a semiconductor substrate; forming a protective film on a side face of the gate electrode by plasma discharge of a first gas or a second gas, the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090098706 - Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench.... Agent: Myers Bigel Sibley & Sajovec

20090098707 - Method for producing bonded wafer: In a method for producing a bonded wafer by bonding a wafer for active layer to wafer for support layer and then thinning the wafer for active layer, a terrace grinding for forming a terrace portion is carried out prior to a step of exposing the oxygen ion implanted layer... Agent: Sughrue Mion, PLLC

20090098710 - Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device: An SOI substrate having a single crystal semiconductor layer with high surface planarity is manufactured. A semiconductor substrate is doped with hydrogen, whereby a damaged region which contains large quantity of hydrogen is formed. After a single crystal semiconductor substrate and a supporting substrate are bonded together, the semiconductor substrate... Agent: Eric Robinson

20090098708 - Method for producing a thin chip comprising an integrated circuit: In a method for producing a very thin chip including an integrated circuit, a circuit structure is produced in a defined section of a semiconductor wafer. The defined wafer section is subsequently released from the semiconductor wafer. For this purpose, the wafer section is firstly freed such that it is... Agent: Harness, Dickey & Pierce, P.L.C

20090098709 - Method of manufacturing semiconductor device: To provide a method of manufacturing a semiconductor device, which prevents impurities from entering an SOI substrate. A source gas including one or plural kinds selected from a hydrogen gas, a helium gas, or halogen gas are excited to generate ions, and the ions are added to a bonding substrate... Agent: Eric Robinson

20090098711 - Micromachine device processing method: A micromachine device processing method for dividing a functional wafer, which has micromachine devices formed in a plurality of regions demarcated by streets formed in a lattice pattern on a face of the functional wafer, along the streets into the individual micromachine devices, each micromachine device having a moving portion... Agent: Greenblum & Bernstein, P.L.C

20090098712 - Substrate dividing method: A method of dividing a substrate 10 into individual pieces by setting dividing lines A used to dividing the substrate 10 into individual pieces at a predetermined interval in a vertical direction and a horizontal direction and then dividing the substrate 10 along the dividing lines A, includes a step... Agent: Rankin, Hill & Clark LLP

20090098713 - Object cutting method: An object cutting method which can reliably remove particles remaining on cut sections of chips is provided. An expandable tape 23 is electrically charged in a state where a plurality of semiconductor chips 25 obtained by cutting a planar object to be processed along a line to cut are separated... Agent: Drinker Biddle & Reath (dc)

20090098714 - Method for forming iii-nitrides semiconductor epilayer on the semiconductor substrate: GaN layer on semiconductor substrate is grown by using GaN nanorod buffer layer. Firstly, semiconductor substrate is cleaned and thermally degassed to remove the contaminant in the growth chamber. After the above step, the GaN nanorods layer is grown under the N-rich condition. Then, GaN epilayer is overgrown on the... Agent: Bacon & Thomas, PLLC

20090098715 - Process for manufacturing silicon wafers for solar cell: A process for manufacturing silicon wafers for solar cell is disclosed wherein one first breaks the refined metallurgical silicon, then remove visible impurities, then performs chemical cleaning and then places the silicon into a crystal growing furnace. Gallium or gallium phosphide is added to the silicon, where the concentration of... Agent: Fulwider Patton LLP

20090098716 - Method for making a self-converged memory material element for memory cell: A self-converged memory material element is created during the manufacture of a memory cell comprising a base layer, with a bottom electrode, and an upper layer having a third, planarization stop layer over the base layer, a second layer over the third layer, and the first layer over the second... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090098717 - Co-sputter deposition of metal-doped chalcogenides: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped... Agent: Dickstein Shapiro LLP

20090098718 - Multiple mask and method for producing differently doped regions: In order to produce doping regions (DG) in a substrate (S) having different dopings with the aid of a single mask (DM) different mask regions are provided which have elongated mask openings (MO) having different orientations relative to the spatial direction of an oblique implantation. The substrate is rotated between... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090098719 - Method for manufacturing silicon carbide semiconductor device: An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b)... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090098720 - Semiconductor device and method for manufacturing the same: A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition... Agent: Eric Robinson

20090098721 - Method of fabricating a flash memory: A method of fabricating a flash memory includes providing a semiconductor substrate with STIs and an active area between two adjacent STIs along a first direction; successively forming a floating-gate insulating layer, a conductive layer, a dielectric layer, a control gate, and a cap layer on the semiconductor substrate; forming... Agent: North America Intellectual Property Corporation

20090098722 - Method of forming a semiconductor memory device: A method of forming a semiconductor memory device includes forming a tunnel insulating layer on a semiconductor substrate, and forming a silicon layer, including metal material, on the tunnel insulating layer. Accordingly, an increase in the strain energy of the conductive layer may be prohibited and, therefore, the growth of... Agent: Townsend And Townsend And Crew, LLP

20090098724 - Method of forming metallic bump and seal for semiconductor device: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM.... Agent: Lin & Associates Intellectual Property, Inc.

20090098723 - Method of forming metallic bump on i/o pad: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM.... Agent: Lin & Associates Intellectual Property, Inc.

20090098725 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, the method includes forming a metal line over a substrate, the metal line having a stacked structure of a conductive layer and a barrier layer, forming an inter-metal dielectric layer over the barrier layer, etching the inter-metal dielectric layer by using a carbon-rich... Agent: Townsend And Townsend And Crew, LLP

20090098726 - Method for forming inlaid interconnect: After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the... Agent: Mcdermott Will & Emery LLP

20090098727 - Method of forming metal line of semiconductor device: Disclosed herein is a method of forming a metal line of a semiconductor device. According to the method, a contact hole is formed in a second insulating layer over a semiconductor substrate. A first barrier metal layer, including a TiN layer, is formed on a surface of the second insulating... Agent: Marshall, Gerstein & Borun LLP

20090098728 - Structure cu liner for interconnects using a double-bilayer processing scheme: The disclosed method forms a via between metallization layers in a semiconductor structure by patterning an insulator layer overlying a first metallization layer to include a via opening. The method lines the via opening with TaN and Ta liners and then sputter etches the via opening deeper through the TaN... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090098729 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes that can prevent formation of fences of reaction by-products around chain holes during a dual damascene process, so subsequent metal gap fill defects are prevented, making it possible to prevent device failure. The method may include forming a via hole in an... Agent: Sherr & Vaughn, PLLC

20090098730 - Semiconductor device and method of fabricating the same: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a lower wire, an interlayer insulating film formed on the lower wire and having a via hole exposing the upper surface of the lower wire, a diffusion barrier formed on the inner wall of... Agent: Mills & Onello LLP

20090098731 - Methods for forming a through via: A through via is constructed in a two-stage process. A void in a portion of the depth of the substrate is filled from a first surface of the semiconductor substrate creating an enclosed volume within the substrate. Thereafter, the enclosed volume is exposed and the remaining portion of the void... Agent: Smith Frohwein Tempel Greenlee Blaha, LLC

20090098732 - Semiconductor device and method of forming contact plug of semiconductor device: The present invention relates to a semiconductor device and a method of forming a contact plug of a semiconductor device. According to the method, a first dielectric layer is formed on a semiconductor substrate in which junction regions are formed. A hard mask is formed on the first dielectric layer.... Agent: Townsend And Townsend And Crew, LLP

20090098733 - Method of forming metal layer used in the fabrication of semiconductor device: A method of forming a metal layer on the conductive region of a semiconductor device includes concurrently supplying a mixture gas including a hydrogen gas and a metal chloride compound gas, and a purge gas into a chamber having a sealed space for a predetermined time, thereby forming a first... Agent: Marger Johnson & Mccollom, P.C.

20090098734 - Method of forming shallow trench isolation structure and method of polishing semiconductor structure: A method of forming an STI structure is described. A patterned mask layer is formed over a substrate of a wafer. A portion of the substrate exposed by the patterned mask layer is removed to form trenches. A dielectric layer is formed over the substrate filling the trenches. A first... Agent: J C Patents, Inc.

20090098735 - Method of forming isolation layer in semicondcutor device: A method of forming an isolation layer in a semiconductor device which prevents formation of voids in the isolation layer by sequentially forming an insulating layer and an anti-reflective layer on and/or over a semiconductor substrate, and then forming a photoresist pattern on and/or over the anti-reflective layer, and then... Agent: Sherr & Vaughn, PLLC

20090098736 - Dry-etching method: A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090098737 - Method of patterning multilayer metal gate structures for cmos devices: A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing... Agent: Cantor Colburn LLP - IBM Fishkill

20090098738 - Method of fabricating semiconductor device: A method of fabricating a flash memory device is disclosed. The method comprises forming a first insulating layer on a semiconductor substrate; accumulating nitrogen at an interface between the semiconductor substrate and the first insulating layer to form a second insulating layer at the interface; and implanting oxygen into the... Agent: Marshall, Gerstein & Borun LLP

20090098739 - Method for manufacturing soi substrate: An object of the present invention is to provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even where a substrate having a low upper temperature limit such as a glass substrate is used. The manufacturing method compromises the steps of... Agent: Fish & Richardson P.C.

20090098740 - Method of forming isolation layer in semiconductor device: The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method,... Agent: Marshall, Gerstein & Borun LLP

20090098741 - Method for forming ultra-thin boron-containing nitride films and related apparatus: Boron-containing nitride films, including silicon boron nitride and boron nitride films, are deposited during, e.g., integrated circuit fabrication. The films are deposited in a process chamber having a reaction space that is defined as an open volume of the chamber directly above the substrate. The boron-containing nitride films are formed... Agent: Knobbe Martens Olson & Bear LLP

20090098742 - System and process for heating semiconductor wafers by optimizing absorption of electromagnetic energy: An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly linear lamps for emitting light energy onto a wafer. The linear lamps can be placed in various configurations. In accordance with the present invention, tuning devices which are used to adjust... Agent: Dority & Manning, P.A.

20090093070 - Capacitor, method of manufacturing the same, method of manufacturing ferroelectric memory device, method of manufacturing actuator, and method of manufacturing liquid jet head: A method of manufacturing a capacitor, including: forming a lower electrode on a substrate; forming a dielectric film of a ferroelectric or a piezoelectric on the lower electrode; forming an upper electrode on the dielectric film; and forming a silicon oxide film so that at least the dielectric film is... Agent: Harness, Dickey & Pierce, P.L.C

20090093071 - Thermal treatment apparatus, thermal treatment method and method of manufacturing semiconductor device: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090093072 - Electronic assemblies with hot spot cooling and methods relating thereto: A composite of two or more thermal interface materials (“TIMs”) is placed between a die and a heat spreader to improve cooling of the die in an integrated circuit package. The two or more TIMs vary in heat-dissipation capability depending upon the locations of die hot spots. In an embodiment,... Agent: Schwegman, Lundberg & Woessner, P.A.

20090093073 - Method of making circuitized substrate with internal optical pathway using photolithography: A method of making a circuitized substrate (e.g., PCB) including at least one and possibly several internal optical pathways as part thereof such that the resulting substrate will be capable of transmitting and/or receiving both electrical and optical signals. The method involves forming at least one opening between a side... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20090093074 - Light emission from silicon-based nanocrystals by sequential thermal annealing approaches: A method for enhancing photoluminescence includes providing a film disposed over a substrate, the film including at least one of a semiconductor and a dielectric material. Light emission may be activated by thermal annealing post growth treatments when thin film layers of SiO2 and SiNx or Si-rich oxide are used.... Agent: Goodwin Procter LLP Patent Administrator

20090093075 - Method of separating semiconductor dies: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed... Agent: Patterson & Sheridan, L.L.P.

20090093076 - Method for manufacturing monolithic semiconductor laser: First and second semiconductor lasers interelement-separated from each other are formed. Total thickness of a fourth upper cladding layer and a second contact layer of the second semiconductor laser is smaller than total thickness of a second upper cladding layer and the first contact layer of the first semiconductor laser.... Agent: Leydig Voit & Mayer, Ltd

20090093077 - Method of manufacturing gan substrate, method of manufacturing epitaxialwafer, method of manufacturing semiconductor device and epitaxialwafer: r

20090093078 - System and method for high temperature compact thermoelectric generator (teg) device construction: A method for creating an array of thermoelectric elements includes applying a first coating of dielectric material to P-type wafers and N-type wafers to form coated P-type wafers and coated N-type wafers. A P/N-type ingot is formed from the coated P-type wafers and the coated N-type wafers. The coated P-type... Agent: Baker Botts L.L.P.

20090093079 - Method of producing an asymmetric architecture semi-conductor device: A method is for producing an asymmetric architecture semi-conductor device. The device includes a substrate, and in stacked relation, a first photosensitive layer, a non-photosensitive layer, and a second photosensitive layer. The method includes a first step of exposing a first zone in each of the photosensitive layers by a... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20090093080 - Solar cells and methods and apparatuses for forming the same including i-layer and n-layer chamber cleaning: Embodiments of the present invention generally provide an apparatus and method for forming an improved thin film single or multi-junction solar cell in a substrate processing device. One embodiment provides a system that contains at least one processing chamber that is adapted to deposit one or more layers that form... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090093081 - Process of phosphorus diffusion for manufacturing solar cell: This invention discloses a process of phosphorus diffusion for manufacturing solar cell, comprising annealing a mono-crystalline silicon wafer in a nitrogen atmosphere at 900-950° C. for twenty to thirty minutes, carrying oxidation treatment in a hydrogen chloride atmosphere at 850-1050° C. to form a 10 to 30 nm thick oxide... Agent: Fulwider Patton LLP

20090093082 - Organic light-emitting diode and method of fabricating the same: An organic light-emitting diode and method of fabricating the same. The organic light-emitting diode includes a first substrate, a first electrode installed on an inner surface of the first substrate, an organic light-emitting layer installed on the first electrode, a second electrode installed on the organic light-emitting layer, an oxide... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090093083 - Method of depositing chalcogenide film for phase-change memory: Provided is a method of depositing a chalcogenide film for phase-change memory. When the chalcogenide film for phase-change memory is deposited through a method using plasma such as plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD), a plasma reaction gas including He is used such... Agent: Ladas & Parry LLP

20090093084 - Die offset die to bonding: A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge... Agent: Paul J. Winters

20090093085 - Carrier structure for stacked-type semiconductor device, method of producing the same, and method of fabricating stacked-type semiconductor device: A carrier structure for fabricating a stacked-type semiconductor device includes: a lower carrier that has laminated thin plates and has first openings for mounting first semiconductor packages thereon; and an upper carrier having second openings for mounting second semiconductor packages on the first semiconductor packages. The lower carrier composed of... Agent: Paul J. Winters

20090093086 - Lead forming apparatus and method of fabricating semiconductor device: A lead forming apparatus has a function of bending leads of a semiconductor device having leads into a gull wing shape. The lead forming apparatus includes: a lead bending die, as a lower die, allowing thereon placement of the semiconductor device and accepting the leads in the bending leads; a... Agent: Young & Thompson

20090093087 - Method of manufacturing semiconductor device: In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090093088 - Roll-on encapsulation method for semiconductor packages: A low-viscosity resin is deposited using an apparatus with a movable and heatable wheel and a heater stage. A tape is provided, which includes a layer (140) of an adhesive polymeric resin and a film (141) of an inert plastic compound. The tape is wrapped around the wheel (150) so... Agent: Texas Instruments Incorporated

20090093089 - Method for fabricating heat dissipating semiconductor package: A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface... Agent: Edwards Angell Palmer & Dodge LLP

20090093090 - Method for producing a power semiconductor module comprising surface-mountable flat external contacts: A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as... Agent: Dicke, Billig & Czaja

20090093091 - Method of fabricating semiconductor package: A semiconductor package of this invention achieves higher wiring densities and increases the degree of freedom of the wiring design. The semiconductor package includes a first substrate having first and second faces, and first wiring provided on the first face of the first substrate. The semiconductor package also includes a... Agent: Rabin & Berdo, PC

20090093093 - Method of fabricating thin film transistor: A method for fabricating a thin film transistor (TFT) is provided. A substrate having a gate, a dielectric layer, a channel layer and an ohmic contact layer formed thereon is provided. Next, a metal layer is formed over the substrate covering the ohmic contact layer. Next, the metal layer and... Agent: J C Patents, Inc.

20090093092 - Soi substrate contact with extended silicide area: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of... Agent: Schmeiser, Olsen & Watts

20090093094 - Selective formation of silicon carbon epitaxial layer: Methods for formation of epitaxial layers containing n-doped silicon are disclosed, including methods for the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. Formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition... Agent: Diehl Servilla LLC

20090093095 - Method to improve transistor tox using si recessing with no additional masking steps: A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity... Agent: Texas Instruments Incorporated

20090093096 - Semiconductor device and manufacturing method thereof: To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned... Agent: Miles & Stockbridge PC

20090093097 - Method for manufacturing dual gate in semiconductor device: Provided is a method for manufacturing a dual gate in a semiconductor device. The method includes forming a gate insulating layer and a gate conductive layer on a semiconductor substrate, forming a diffusion barrier layer on the gate conductive layer, forming a barrier metal layer on the diffusion barrier layer,... Agent: Marshall, Gerstein & Borun LLP

20090093098 - Manufacturing method of semiconductor device having trench isolation: A manufacturing method of semiconductor device includes: forming a nitride film above a silicon substrate including a first region and a second region which respectively correspond to an outside of a memory cell region and the memory cell region; forming trenches reaching from the nitride film to the silicon substrate;... Agent: Foley And Lardner LLP Suite 500

20090093099 - Layout method and layout apparatus for semiconductor integrated circuit: In a layout method for a semiconductor integrated circuit by using cell library data, a plurality of cell patterns are arranged in a first direction. One of gate patterns in one of the plurality of cell patterns is specified as a reference gate pattern. An additional cell pattern is arranged... Agent: Mcginn Intellectual Property Law Group, PLLC

20090093100 - Method for forming an air gap in multilevel interconnect structure: The present invention generally provides a method for forming multilevel interconnect structures, including multilevel interconnect structures that include an air gap. One embodiment provides a method for forming conductive lines in a semiconductor structure comprising forming trenches in a first dielectric layer, wherein air gaps are to be formed in... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090093101 - Method for manufacturing a transistor of a semiconductor memory device: A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first... Agent: Marshall, Gerstein & Borun LLP

20090093103 - Method and device for controlled cleaving process: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of... Agent: Townsend And Townsend And Crew, LLP

20090093102 - Method for manufacturing semiconductor substrate: When a single crystal semiconductor layer is bonded to a base substrate, a silicon oxide film is preferably used for one or both of the base substrate and a single crystal semiconductor substrate. According to this structure, an SOI layer having a strong bonding strength in a bonding portion can... Agent: Eric Robinson

20090093104 - Manufacturing method for semiconductor chips: By forming dividing-groove portions in accordance with dividing regions on the second surface of a semiconductor wafer where an insulating film is placed in the dividing regions of the first surface and performing etching of the entire second surface and the surfaces of the dividing-groove portions by performing plasma etching... Agent: Wenderoth, Lind & Ponack L.L.P.

20090093105 - Particle deposition apparatus, particle deposition method, and manufacturing method of light-emitting device: To provide a (homogeneous) particle deposit without any impurity contamination, on which only particles with a desired size are deposited. A solution, with particles dispersed in a solvent, is jetted as a flow of fine liquid droplets from a tip part of a capillary, and the jetted fine liquid droplets... Agent: Oliff & Berridge, PLC

20090093106 - Bonded soi substrate, and method for manufacturing the same: This bonded SOI substrate includes: an SOI layer having a low density impurity layer in which dopants are present at low density and a high density impurity layer in which dopants are present at high density; a wafer for a support substrate which supports said SOI layer; and a buried... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090093107 - Semiconductor substrate cleaning methods, and methods of manufacture using same: In a cleaning composition, a method of cleaning a semiconductor substrate and a method of manufacturing a semiconductor device, the cleaning composition includes about 0.5 to about 5% by weight of an organic ammonium hydroxide compound, about 0.1 to about 3% by weight of a fluoride compound, about 0.1 to... Agent: Volentine & Whitt PLLC

20090093108 - Semiconductor fabrication process including silicide stringer removal processing: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the... Agent: Freescale Semiconductor, Inc. Law Department

20090093109 - Method for producing a semiconductor device using a solder alloy: In producing a semiconductor device, a solder alloy is prepared to contain antimony in a range of from 3 to 5 wt %, a trace amount of germanium, and a balance of tin. An insulative substrate having conductor patterns on both surfaces thereof is prepared, and a heat sink plate... Agent: Kanesaka Berner And Partners LLP

20090093110 - Bga package having half-etched bonding pad and cut plating line and method of fabricating same: A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad... Agent: Darby & Darby P.C.

20090093111 - Sprocket opening alignment process and apparatus for multilayer solder decal: A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the center axes of the sprocket openings... Agent: Robert J. Eichelburg, Esq. The Law Offices Of Robert J. Eichelburg

20090093113 - Electrochemical etching of through silicon vias: A process is disclosed to form through silicon vias in a silicon wafer. The method comprises, forming a dielectric layer on a silicon wafer, forming a masking layer using photolithography, etching the dielectric layer, and electrochemically etching a through silicon via in the silicon wafer.... Agent: Jason P. Mueller Adams And Reese, LLP

20090093112 - Methods and apparatus of creating airgap in dielectric layers for the reduction of rc delay: A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090093114 - Method of forming a dual-damascene structure using an underlayer: A method of forming a dual-damascene wire. The method includes forming a via opening in a dielectric layer, filling the via opening with a polymeric formation including at least about 6% by weight of solids of thermal acid generator; heating the polymeric underlayer to a temperature greater than room temperature... Agent: Schmeiser, Olsen & Watts

20090093115 - Method for forming metal line of semiconductor device by annealing aluminum and copper layers together: A metal line is formed to realize an improved electrical conductivity over the conventional aluminum metal lines. The metal line of a semiconductor device is made by forming an interlayer dielectric having a metal line forming region on a semiconductor substrate. A diffusion barrier on the interlayer dielectric is formed... Agent: Ladas & Parry LLP

20090093116 - Method for forming zener zap diodes and ohmic contacts in the same integrated circuit: A method for forming an ohmic contact and a zener zap diode in an integrated circuit includes forming a first contact opening in the insulating layer over a first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact... Agent: Patent Law Group LLP

20090093117 - Method of manufacturing substrate: A method of manufacturing a substrate, includes: (a) forming the through hole by etching the silicon substrate from a first surface of the silicon substrate by a Bosch process; (b) forming a thermal oxide film such that the thermal oxide film covers the first surface of the silicon substrate, a... Agent: Rankin, Hill & Clark LLP

20090093119 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device is disclosed, by which thickness of a gate oxide layer can be controlled for uniformity. Embodiments include sequentially forming a pad oxide layer and a nitride layer over a semiconductor substrate having an epi-layer grown thereon, the semiconductor substrate having a backside over... Agent: Sherr & Vaughn, PLLC

20090093118 - Polishing composition: In order to polish a wiring metal, a polishing composition ensuring that etching and erosion are suppressed and the residual wiring metal on the portion other than wiring is decreased, is provided, in which a polishing composition comprising (A) an azole group-containing compound having 3 or more azole groups within... Agent: Sughrue Mion, PLLC

20090093120 - Hole pattern forming method and semiconductor device manufacturing method: A hole pattern forming method that forms a fine hole pattern in a work target layer that is formed on a semiconductor substrate, includes: forming a three-layer structure by laminating a carbon film layer, an intermediate mask layer, and a photoresist layer in that order on the work target layer;... Agent: Young & Thompson

20090093121 - Method for fabricating a fine pattern: In a method for fabricating a fine pattern, a target layer to be patterned is formed on a semiconductor substrate. A sacrificial pattern is formed on the target layer. The sacrificial pattern includes first sacrificial patterns arranged at a first spacing, and second and third sacrificial patterns arranged in pairs... Agent: Marshall, Gerstein & Borun LLP

20090093122 - Method for producing group iii-v nitride semiconductor substrate: The present invention provides a method for producing a group III-V nitride semiconductor substrate. The method for producing a group III-V nitride semiconductor substrate comprises the steps of (I-1) to (I-6): (I-1) placing inorganic particles on a template, (I-2) dry-etching the template by using the inorganic particles as an etching... Agent: Fitch, Even, Tabin & Flannery

20090093123 - Spin head, chuck pin used in the spin head, and method for treating a substrate with the spin head: Provided is a spin head for supporting a substrate. The spin head includes a rotatable body, and chuck pins protruding upward from the body and configured to support an edge of a substrate placed at the body when the body is rotated. Each of the chuck pins includes a vertical... Agent: Harness, Dickey & Pierce, P.L.C

20090093124 - Method of manufacturing semiconductor device: To provide a method of manufacturing a semiconductor device, which includes a process capable of excellently removing a photoresist in which a high dose of ion is implanted. A photoresist with a high dose of ion implanted therein is removed from a wafer through a first removing process for carrying... Agent: Oliff & Berridge, PLC

20090093125 - Chemistry and compositions for manufacturing integrated circuits: In the manufacture of integrated circuits, reactive compositions that include a reactive etchant species and an oxygen-containing species can provide selective removal of target material and can reduce contamination of gas delivery lines.... Agent: Mueting, Raasch & Gebhardt, P.A.

20090093126 - Method of and an apparatus for processing a substrate: A method of processing a semiconductor substrate (3) comprises spinning the semiconductor substrate (3) while dispensing a reactive etching agent (7) onto a first surface of the spinning substrate (3) to etch a first region (8) of the surface (3). Simultaneously, a neutralising agent (9) is dispensed onto the first... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090093127 - Treatment of a substrate with a liquid medium: The invention relates to an arrangement of electronic semiconductor components on a carrier system for treating the semiconductor components with a liquid medium. A semiconductor component is detachably mounted on the carrier system with the active side thereof in such a way that the arrangement comprises a gap at least... Agent: Slater & Matsil LLP

20090093129 - Gas baffle and distributor for semiconductor processing chamber: Apparatus and methods for distributing gas in a semiconductor process chamber are provided. In an embodiment, a gas distributor for use in a gas processing chamber comprises a body. The body includes a baffle with a gas deflection surface to divert the flow of a gas from a first direction... Agent: Townsend And Townsend And Crew LLP

20090093131 - Low-temperature catalyzed formation of segmented nanowire of dielectric material: The present invention discloses a method of forming a segmented nanowire including: providing a substrate; pre-cleaning the substrate; pre-treating the substrate; forming and placing a catalyst over the substrate; and forming the segmented nanowire over the catalyst with recurring pulses of plasma-enhanced chemical vapor deposition (PECVD) of a dielectric material.... Agent: Intel Corporation C/o Intellevate, LLC

20090093128 - Methods for high temperature deposition of an amorphous carbon layer: Methods for high temperature deposition an amorphous carbon film with improved step coverage are provided. In one embodiment, a method for of depositing an amorphous carbon film includes providing a substrate in a process chamber, heating the substrate at a temperature greater than 500 degrees Celsius, supplying a gas mixture... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090093130 - Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090093132 - Methods to obtain low k dielectric barrier with superior etch resistivity: The present invention generally provides a method for forming a dielectric barrier with lowered dielectric constant, improved etching resistivity and good barrier property. One embodiment provides a method for processing a semiconductor substrate comprising flowing a precursor to a processing chamber, wherein the precursor comprises silicon-carbon bonds and carbon-carbon bonds,... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090093133 - Self-assembled sidewall spacer: A semiconductor structure is provided that includes a spacer directly abutting a topographic edge of at least one patterned material layer. The spacer is a non-removable polymeric block component of a self-assembled block copolymer. A method of forming such a semiconductor structure including the inventive spacer is also provided that... Agent: Scully, Scott, Murphy & Presser, P.C.

20090093134 - Semiconductor manufacturing apparatus and method for curing materials with uv light: Low dielectric constant materials are cured in a process chamber during semiconductor processing. The low dielectric constant materials are cured by irradiation with UV light. The atmosphere in the process chamber has a CO2 concentration of about 1-16% by volume during the irradiation. The CO2 limits the formation of —Si—H... Agent: Knobbe Martens Olson & Bear LLP

20090093135 - Semiconductor manufacturing apparatus and method for curing material with uv light: Low dielectric constant materials are cured in a process chamber during semiconductor processing. The low dielectric constant materials are cured by irradiation with UV light. The atmosphere in the process chamber has an O2 concentration of about 25-10,000 ppm during the irradiation. The O2 limits the formation of —Si—H and... Agent: Knobbe Martens Olson & Bear LLP

20090087928 - Copper contamination detection method and system for monitoring copper contamination: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in... Agent: Schmeiser, Olsen & Watts

20090087929 - Method and system for improving wet chemical bath process stability and productivity in semiconductor manufacturing: A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels... Agent: Duane Morris LLP (tsmc)IPDepartment

20090087930 - Inspection system, inspection method, and method for manufacturing semiconductor device: The present invention provides an inspection system of ID chips that can supply a signal or power supply voltage to an ID chip without contact, and can increase throughput of an inspection process and an inspection method using the inspection system. The inspection system according to the present invention includes... Agent: Cook Alex Ltd

20090087931 - Method of manufacturing light emitting diode package: Provided is a method of manufacturing an LED package, the method including preparing a mold die which includes an upper surface and a lower surface having an outer circumferential surface and a concave surface surrounded by the outer circumferential surface, the mold die having an outlet extending from the upper... Agent: Mcdermott Will & Emery LLP

20090087932 - Substrate supporting apparatus, substrate supporting method, semiconductor manufacturing apparatus and storage medium: A substrate supporting apparatus includes a substrate supporting portion having a substrate supporting surface facing a rear surface of a substrate; plural protruding portions provided on the substrate supporting surface, for preventing the substrate from being slid on the substrate supporting surface by friction force generated in relation with the... Agent: Pearne & Gordon LLP

20090087933 - Thin film transistor substrate for a liquid crystal display wherein a black matrix formed on the substrate comprises an inner aperture formed completely within the black matrix: Disclosed is a thin film transistor substrate for a liquid crystal display and a method for repairing the substrate. The substrate comprises an insulating substrate; a black matrix formed on the insulating substrate having apertures in areas of pixels, shaped as a net; an insulating layer covering the black matrix;... Agent: F. Chau & Associates, LLC

20090087934 - Method of manufacturing nitride semiconductor light emitting element: In a method for manufacturing a III-V nitride compound semiconductor light emitting element, light emitting element regions (21) are formed in a low dislocation region on the III-V nitride compound semiconductor substrate wherein high density dislocation sections (22) and low dislocation regions are alternately arranged repeatedly, so that stripe-shaped light... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090087935 - Fabricating method for quantum dot of active layer of led by nano-lithography: The present invention is to provide a “fabricating method for quantum dot active layer of LED by nano-lithography” for fabricating out a new active layer of LED of nano quantum dot structure in more miniature manner than that of the current fabricating facilities to have high quality LED with features... Agent: Bacon & Thomas, PLLC

20090087938 - Method for manufacturing microdevices or integrated circuits on continuous sheets: Current manufacturing of miniature or micro electronic mechanical optical chemical or biophysical devices utilizes discrete substrates holding one or more said devices. The use of discrete substrates entails several disadvantages with respect to economical manufacturing. This invention is a method of manufacturing devices using flexible carrier sheets with device substrates... Agent: Texas Instruments Incorporated

20090087939 - Column structure thin film material using metal oxide bearing semiconductor material for solar cell devices: A thin film material structure for solar cell devices. The thin film material structure includes a thickness of material comprises a plurality of single crystal structures. In a specific embodiment, each of the single crystal structure is configured in a column like shape. The column like shape has a dimension... Agent: Townsend And Townsend And Crew, LLP

20090087941 - Method for producing multijunction solar cell: There is provided a method for producing a multijunction solar cell having four-junctions, the method allowing the area of a device to be increased. On a nucleation site formed on a substrate 2, is grown a semiconductor 2a comprising the same material as the substrate 2 in the shape of... Agent: Birch Stewart Kolasch & Birch

20090087940 - Method of successive high-resistance buffer layer/window layer (transparent conductive film) formation for cis based thin-film solar cell and apparatus for successive film formation for practicing the method of successive film formation: After a metallic base electrode layer 1B and a light absorption layer 1C are formed in this order on a glass substrate 1A, a high-resistance buffer layer 1D and a window layer 1E are successively formed in this order in a multi layer arrangement on the light absorption layer 1C... Agent: Sughrue-265550

20090087942 - Manufacture of photovoltaic devices: A method and apparatus for depositing a film on a substrate includes subjecting material to an energy beam.... Agent: Steptoe & Johnson LLP

20090087943 - Method for forming large grain polysilicon thin film material: A method of forming polysilicon thin film material for photovoltaic devices. The method includes providing a polycrystalline silicon substrate. The polycrystalline silicon substrate includes a surface region, a backside region, and a thickness. In a specific embodiment, the method forms a polysilicon thin film material using a deposition process overlying... Agent: Townsend And Townsend And Crew, LLP

20090087944 - Electronic devices with hybrid high-k dielectric and fabrication methods thereof: Electronic devices with hybrid high-k dielectric and fabrication methods thereof. The electronic device includes a substrate. A first electrode is disposed on the substrate. Hybrid high-k multi-layers comprising a first dielectric layer and a second dielectric layer are disposed on the substrate, wherein the first dielectric layer and the second... Agent: Quintero Law Office, PC

20090087945 - Phase change memory cell with roundless micro-trenches: A method for constructing a phase change memory device includes forming a first dielectric layer on a substrate; forming a first conductive component in the first dielectric layer; forming a second dielectric layer over the first conductive component in the first dielectric layer; forming a conductive crown in the second... Agent: K & L Gates LLP

20090087946 - Structure and method for thin single or multichip semiconductor qfn packages: A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second... Agent: Texas Instruments Incorporated

20090087947 - Flip chip package process: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole... Agent: J C Patents, Inc.

20090087948 - Flip chip package with advanced electrical and thermal properties for high current designs: A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the substrate to a high current contact pad on interior region of the substrate. A semiconductor chip having an active surface generally faces... Agent: Texas Instruments Incorporated

20090087949 - Method of making a microelectronic package using an ihs stiffener: A method of making a microelectronic package. The method includes: providing a carrier; providing a tacky pad on the carrier; placing a die onto the tacky pad such that an active surface of the die adheres to the tacky pad, bonding an IHS onto a backside of the die after... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090087950 - Wafer packaging method: m

20090087951 - Method of manufacturing wafer level package: A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a... Agent: Staas & Halsey LLP

20090087954 - Method for fabricating pixel structure: A method for fabricating a pixel structure using a laser ablation process is provided. This fabrication method forms a gate, a channel layer, a source, a drain, a passivation layer, and a pixel electrode sequentially by using a laser ablation process. Particularly, the fabrication method is not similar to a... Agent: Jianq Chyun Intellectual Property Office

20090087955 - Method for removing hard masks on gates in semiconductor manufacturing process: A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The first gate and... Agent: Wpat, PC Intellectual Property Attorneys

20090087956 - Dummy contact fill to improve post contact chemical mechanical polish topography: State of the art Integrated Circuits (ICs) encompass a variety of circuits, which have a wide variety of contact densities as measured in regions from 10 to 1000 microns in size. Fabrication processes for contacts have difficulty with high and low contact densities on the same IC, leading to a... Agent: Texas Instruments Incorporated

20090087957 - Method of fabricating semiconductor device: Photoresist on a metal is removed with less oxidation of the metal surface by the invented ashing. During process, the matching of oxygen gas ratio and wafer temperature under downstream plasma which means no RF bias plasma is controlled for oxidation amount not to depend on ashing time with required... Agent: Mcginn Intellectual Property Law Group, PLLC

20090087958 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof which enable to secure high yield and increase the capacity of a capacitor are provided. The semiconductor device according to the present invention includes: a plurality of capacitor layers laminated, each capacitor layer including a plurality of storage electrodes, a capacity insulating... Agent: Mcdermott Will & Emery LLP

20090087959 - Method for forming a pattern of a semiconductor device: In a method for forming a fine pattern of a semiconductor device, forming a spacer for double patterning of a cell region is performed separate from forming a mask pattern that defines a dummy pattern for a pad of a peripheral circuit region.... Agent: Townsend And Townsend And Crew, LLP

20090087960 - Method for fabricating recess gate in semiconductor device: A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack... Agent: Townsend And Townsend And Crew, LLP

20090087961 - Process for fabricating semiconductor structures useful for the production of semiconductor-on-insulator substrates, and its applications: m

20090087962 - Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby: In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on... Agent: Mills & Onello LLP

20090087963 - Method for reducing pillar structure dimensions of a semiconductor device: A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20090087964 - Manufacturing method of semiconductor device and substrate processing apparatus: To realize a high productivity while maintaining excellent film deposition characteristics on a substrate even if a plurality of processing gases of different gas species are used. There are provided the step of loading a plurality of substrates into a processing chamber; supplying a first processing gas to an upper... Agent: Oliff & Berridge, PLC

20090087965 - Structure and method for manufacturing phase change memories: A method for manufacturing at least one resistively switching memory cell including generating a first electrode; depositing a phase change material layer, the phase change material layer including a composition of formula GaxGeyInzSb1-x-y-z that also incorporates at least elemental oxygen or elemental nitrogen, where x, y, and z are each... Agent: Dicke, Billig & Czaja

20090087966 - Method for manufacturing semiconductor device: A semiconductor film is formed on a GaAs substrate (semiconductor substrate). An SiO2 film (insulating film) is formed on the semiconductor film, and the SiO2 film is patterned. The semiconductor film is etched using the SiO2 film as a mask to form a mesa structure. The surface of the SiO2... Agent: Leydig Voit & Mayer, Ltd

20090087967 - Precursors and processes for low temperature selective epitaxial growth: This invention generally relates to low temperature epitaxy. More specifically, this invention relates to processes for achieving low temperature selective epitaxial growth by chemical vapor deposition of source precursors containing Si or Ge in the presence of bromine or iodine, compositions containing precursors and brominated or iodinated compounds suitable for... Agent: Schmeiser Olsen & Watts

20090087969 - Method to improve a copper/dielectric interface in semiconductor devices: Embodiments of methods for improving a copper/dielectric interface in semiconductor devices are generally described herein. Other embodiments may be described and claimed.... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20090087971 - Method for fabricating semiconductor devices with reduced junction diffusion: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the... Agent: HorizonIPPte Ltd

20090087972 - Formation of carbon and semiconductor nanomaterials using molecular assemblies: The invention is directed to a method of forming carbon nanomaterials or semiconductor nanomaterials. The method comprises providing a substrate and attaching a molecular precursor to the substrate. The molecular precursor includes a surface binding group for attachment to the substrate and a binding group for attachment of metal-containing species.... Agent: Connolly Bove Lodge & Hutz LLP

20090087973 - Retention improvement in dual-gate memory: A manufacturing process improves retention capabilties of dual-gate non-volatile memory cells by limiting the effects of lateral charge movement. The process limits lateral extents of the charge storage medium that is an integral part of the memory device within the dual-gate device.... Agent: Macpherson Kwok Chen & Heid LLP

20090087974 - Method of forming high-k gate electrode structures after transistor fabrication: A sophisticated high-k metal gate electrode structure may be formed after the deposition of a first part of an interlayer dielectric material, thereby providing a high degree of process compatibility with conventional CMOS techniques. Thus, sophisticated strain-inducing mechanisms may be readily implemented in the overall process flow, while nevertheless avoiding... Agent: Williams, Morgan & Amerson

20090087976 - Conductive spacers extended floating gates: A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090087977 - Low temperature conformal oxide formation and applications: The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090087975 - Method for manufacturing a memory: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region,... Agent: North America Intellectual Property Corporation

20090087978 - Interconnect manufacturing process: An interconnect process is provided. A substrate is provided. A plurality of gate structures is disposed on the substrate, and doped regions are disposed in the substrate and respectively located between two adjacent gate structure. A liner is conformally formed above the substrate. A dielectric layer is formed above the... Agent: J C Patents, Inc.

20090087979 - Dual damascene with amorphous carbon for 3d deep via/trench application: A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit... Agent: Vierra Magen/sandisk Corporation

20090087980 - Methods of low-k dielectric and metal process integration: An integrated process for forming metallization layers for electronic devices that use damascene structures that include low-k dielectric and metal. According to one embodiment of the present invention, the integrated process includes planarizing a gapfill metal in low-k dielectric structures, generating a protective layer on the low-k dielectric followed by... Agent: Larry Williams

20090087981 - Void-free copper filling of recessed features for semiconductor devices: A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20090087982 - Selective ruthenium deposition on copper materials: Embodiments of the invention provide processes for selectively forming a ruthenium-containing film on a copper surface over exposed dielectric surfaces. Thereafter, a copper bulk layer may be deposited on the ruthenium-containing film. In one embodiment, a method for forming layers on a substrate is provided which includes positioning a substrate... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090087983 - Aluminum contact integration on cobalt silicide junction: Embodiments herein provide methods for forming an aluminum contact on a cobalt silicide junction. In one embodiment, a method for forming materials on a substrate is provided which includes forming a cobalt silicide layer on a silicon-containing surface of the substrate during a silicidation process, forming a fluorinated sublimation film... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090087984 - Forming method of electrode and manufacturing method of semiconductor device: A forming method of an electrode includes the steps of providing an electrode material on a conductive part; exposing the electrode material at a temperature equal to or higher than a melting point of the electrode material in an oxidizing atmosphere; and exposing the melted electrode material, in a reducing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090087985 - Selective formation of a compound comprising a semi-conducting material and a metallic material in a substrate through a germanium oxide layer: An area made from a compound of a metallic material and semi-conducting material is produced selectively in a substrate made from semi-conducting material by previously forming a germanium oxide layer with a thickness comprised between 3 nm and 5 nm over a predefined part of a surface of the substrate... Agent: Oliff & Berridge, PLC

20090087987 - Method of making a semiconductor device having improved contacts: A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This... Agent: Dinsmore & Shohl LLP

20090087986 - Semiconductor devices using fine patterns and methods of forming fine patterns: Example embodiments may provide fine patterns for semiconductor devices and methods of forming fine patterns for semiconductor devices. Example methods may include forming a spacer pattern on a substrate and/or an insulating layer pattern adjacent to sides of the spacer pattern and/or disposed at the same level as the spacer... Agent: Harness, Dickey & Pierce, P.L.C

20090087988 - Polishing liquid and polishing method: A polishing liquid is provided which is used for polishing a barrier layer of a semiconductor integrated circuit, the polishing liquid including surface modified particles that include organic polymer particles having at least one inorganic atom selected from the group consisting of Ti, Al, Zr and Si bonded to the... Agent: Sughrue Mion, PLLC

20090087992 - Method of minimizing via sidewall damages during dual damascene trench reactive ion etching in a via first scheme: A method of minimizing undercut of a hard mask in an integrated circuit (IC) structure including steps of providing an IC structure having a substrate, a interlayer dielectric layer, and a hard mask, forming a via in said IC structure, and depositing an organic planarizing layer (OPL) over the IC... Agent: Katten Muchin Rosenman LLP

20090087993 - Methods and apparatus for cost-effectively increasing feature density using a mask shrinking process with double patterning: Methods and apparatus are provided for forming an array of devices. The invention includes forming a stack of material layers, forming a first hardmask over the plurality of material layers, exposing the first hardmask to ozone mixed with a halogenated additive, forming a protective layer over the first hardmask, forming... Agent: Dugan & Dugan, PC

20090087994 - Method of forming fine patterns and manufacturing semiconductor light emitting device using the same: A method of forming a fine pattern begins with providing a c-plane hexagonal semiconductor crystal. A mask having a predetermined pattern is formed on the semiconductor crystal. The semiconductor crystal is dry-etched by using the mask to form a first fine pattern on the semiconductor crystal. The semiconductor crystal including... Agent: Mcdermott Will & Emery LLP

20090087995 - Method of substrate treatment, process for producing semiconductor device, substrate treating apparatus, and recording medium: Substrate processing apparatus 100 includes supporting table 103 for not only supporting a target substrate W but also heating the target substrate W; processing chamber 101 having the supporting table 103 disposed therein; and gas supply unit 102 for supplying a processing gas into the processing chamber 101. The processing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090087996 - Line width roughness control with arc layer open: To achieve the foregoing and in accordance with the purpose of the present invention a method for etching an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The ARC layer is opened, and features are etched into the etch layer through the patterned... Agent: Beyer Law Group LLP

20090087997 - Passivation film and method of forming the same: A passivation film and a method of forming the same are provided, the passivation film being used in a plasma display panel etc. In the passivation film, a first MgO layer, an intervening layer, and a second MgO layer are laminated and a laser is then irradiated to oxidize the... Agent: Bacon & Thomas, PLLC

20090087998 - Diffusion barrier layer and method for manufacturing a diffusion barrier layer: A diffusion barrier system for a display device comprising a layer system with at least two layers of dielectric material, wherein at least two adjacent layers of that layer system comprise the same material. A respective method for manufacturing such a diffusion barrier system in a single process chamber of... Agent: Pearne & Gordon LLP

20090087999 - Technique for compensating for a difference in deposition behavior in an interlayer dielectric material: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop... Agent: Williams, Morgan & Amerson

20090088000 - Method for growing an oxynitride film on a substrate: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a first wet process gas comprising water vapor into the process chamber, and reacting the substrate with the first wet process gas to grow an oxide film... Agent: Tokyo Electron U.s. Holdings, Inc.

20090088001 - Substrate processing apparatus and manufacturing method of semiconductor device: To provide a large amount of processing gas to substrates. There are provided a processing chamber that stores stacked substrates; a gas supply part provided in the processing chamber along a stacking direction of the substrates, having a plurality of opening parts, for supplying a desired processing gas horizontally to... Agent: Oliff & Berridge, PLC

20090088002 - Method of fabricating a nitrogenated silicon oxide layer and mos device having same: A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon... Agent: Brinks Hofer Gilson & Lione