|Semiconductor device manufacturing: process patents - Monitor Patents|
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Semiconductor device manufacturing: process February patent applications/inventions, industry category 02/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/26/2009 > patent applications in patent subcategories. patent applications/inventions, industry category
20090053833 - Method of manufacturing magnetic multi-layered film: A method of manufacturing a magnetic multi-layered film including: a first magnetic layer forming step of forming a first magnetic layer on a substrate; a non-magnetic layer forming step of forming a non-magnetic layer on the first magnetic layer; and a second magnetic layer forming step of forming a second... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC
20090053834 - Use of scatterometry for in-line detection of poly-si strings left in sti divot after gate etch: One embodiment of the present invention relates to a method of forming an integrated circuit, comprising forming an STI structure in a semiconductor body, the STI structure having a divot characteristic, performing scatterometry on the STI structure and obtaining signature spectra associated therewith, and continuing fabrication of the integrated circuit... Agent: Texas Instruments Incorporated
20090053835 - Vacuum apparatus including a particle monitoring unit, particle monitoring method and program, and window member for use in the particle monitoring: A semiconductor manufacturing apparatus includes a processing chamber for performing a manufacturing processing on a wafer. A gas supply line for introducing a purge gas is connected to an upper portion of the processing chamber, a valve being installed on the gas supply line. A rough pumping line with a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090053836 - Method of wafer level transient sensing, threshold comparison and arc flag generation/deactivation: A method for processing a semiconductor wafer in a plasma reactor comprises sensing transient voltages or currents on a conductor coupled to the wafer and providing a first comparator for comparing the transient voltages or currents with a threshold level stored in the comparator. The method further includes transmitting from... Agent: Law Office Of Robert M. Wallace
20090053837 - Wafer boat for semiconductor testing: In accordance with one embodiment of the invention, a method and apparatus are provided for testing a wafer while the wafer is disposed in a wafer carrier. The test results can be utilized to adjust the manufacturing process and thereby increase processing yield.... Agent: Gregory W. Osterloth Holland & Hart, LLP
20090053839 - High power led housing and fabrication method thereof: An LED housing, in which a heat conducting part has a chip mounting area, a heat connecting area opposed to the chip mounting area and a neck between them. Fixing parts have first ends engaged with the neck. An electrical connecting part has a wire connecting area placed adjacent to... Agent: Lowe Hauptman Ham & Berner, LLP
20090053838 - Method for manufacturing semiconductor laser device and method for inspecting semiconductor laser bar: A first conductivity type cladding layer, an active layer, a second conductivity type first cladding layer, and a second conductivity type second cladding layer are laminated in this order on a semiconductor substrate by crystal growth. The second conductivity type second cladding layer is processed into a plurality of stripe-shaped... Agent: Hamre, Schumann, Mueller & Larson P.C.
20090053840 - High power light emitting device assembly with esd protection ability and the method of manufacturing the same: A high power light emitting device assembly with electro-static-discharge (ESD) protection ability and the method of manufacturing the same, the assembly comprising: at least two sub-mounts, respectively being electrically connected to an anode electrode and a cathode electrode, each being made of a metal of high electric conductivity and high... Agent: Birch Stewart Kolasch & Birch
20090053841 - Semiconductor light emitting device: A semiconductor light emitting device comprises an element that emits light and a substrate on a main surface of which the element is mounted. The main surface of the substrate composed of two areas, (i) a mount area which is rectangle and on which the element is mounted, and (ii)... Agent: Wenderoth, Lind & Ponack L.L.P.
20090053842 - Thin film transistor array panel and methods for manufacturing the same: Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is... Agent: Macpherson Kwok Chen & Heid LLP
20090053843 - Method of making a tft array with photo-imageable insulating layer over address lines: This invention is related to a thin film transistor (TFT) array and method of making same, for use in an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The TFT array and corresponding display are made by forming the TFTs and corresponding address lines on a... Agent: Mckenna Long & Aldridge LLP
20090053844 - Method for fabricating pixel structure: A method for fabricating a pixel structure is provided. A substrate having a gate thereon is provided. Next, a gate dielectric layer is formed to cover the gate. A channel layer is formed on the gate dielectric layer above the gate. A source and a drain are formed on the... Agent: Jianq Chyun Intellectual Property Office
20090053845 - Method for controlling the structure and surface qualities of a thin film and product produced thereby: A system and method for providing improved surface quality following removal of a substrate and template layers from a semiconductor structure provides an improved surface quality for a layer (such as a quantum well heterostructure active region) prior to bonding a heat sink/conductive substrate to the structure. Following the physical... Agent: JasIPConsulting
20090053846 - Methods of making electromechanical three-trace junction devices: Methods of producing an electromechanical circuit element are described. A lower structure having lower support structures and a lower electrically conductive element is provided. A nanotube ribbon (or other electromechanically responsive element) is formed on an upper surface of the lower structure so as to contact the lower support structures.... Agent: Wilmerhale/boston
20090053847 - Methods and apparatus for depositing a microcrystalline silicon film for photovoltaic device: Methods for depositing a microcrystalline silicon film layer with improved deposition rate and film quality are provided in the present invention. Also, a photovoltaic (PV) cell having a microcrystalline silicon film is provided. In one embodiment, the method produces a microcrystalline silicon film on a substrate at a deposition rate... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090053848 - Method and apparatus providing imager pixels with shared pixel components: The disclosed embodiments employ shared pixel component architectures that arrange the shared pixel components for a group of pixels within different pixels of the group.... Agent: Dickstein Shapiro LLP
20090053849 - Photoelectric conversion device and image pickup system with photoelectric conversion device: A photoelectric conversion device comprises a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type serving as a photoelectric conversion element together with a part of the first semiconductor region; a gate electrode transferring electric carriers generated in the photoelectric conversion element... Agent: Fitzpatrick Cella Harper & Scinto
20090053850 - Method of manufacturing solid state imaging device: A mask (68) is attached to a circuit assembly board (47) on which a plurality of sensor packages (4) are adhered. An upper face of a cover glass (6) of each sensor package (4) is protected by a mask section (68b) of the mask (68). The circuit assembly board (47)... Agent: Sughrue Mion, PLLC
20090053851 - Organic thin film transistor array substrate and liquid crystal display including the same: An organic thin film transistor array substrate including a substrate divided into an LCD region and an OTFT region; a first dielectric layer formed on the substrate in the LCD region and having a first uneven portion; an organic semiconducting layer formed on the substrate in the OTFT region; a... Agent: Quintero Law Office, PC
20090053852 - Manufacturing apparatus and method for an electronic apparatus: A manufacturing method for an electronic apparatus and manufacturing apparatus are provided. The manufacturing method includes applying to a surface of a sheet an adhesive to be charged into a space between a mounting board and an electronic component mounted on the mounting board, bringing the one surface of the... Agent: Staas & Halsey LLP
20090053853 - Method for manufacturing electronic component: A chip element in the form of a substantially rectangular parallelepiped having end surfaces and side surfaces is formed (step of forming chip element). An electrically conductive green sheet is formed (step of forming electrically conductive green sheet). An electrically conductive paste is applied to the end surfaces of the... Agent: Oliff & Berridge, PLC
20090053854 - Memory circuit arrangement and method for the production thereof: A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the... Agent: Brinks Hofer Gilson & Lione/infineon Infineon
20090053855 - Indented lid for encapsulated devices and method of manufacture: A method for providing improved gettering in a vacuum encapsulated device is described. The method includes forming a plurality of small indentation features in a device cavity formed in a lid wafer. The gettering material is then deposited over the indentation features. The indentation features increase the surface area of... Agent: Jaquelin K. Spong
20090053856 - Semiconductor device comprising light-emitting element and light-receiving element, and manufacturing method therefor: A semiconductor device includes a substrate for transmitting light, a wiring layer provided on the substrate, a semiconductor chip formed on the wiring layer, a columnar electrode, a sealant, and an external connection terminal electrically connected to the semiconductor chip via the wiring layer and protruding electrode. The device includes... Agent: Volentine & Whitt PLLC
20090053858 - Method of manufacturing semiconductor package using redistribution substrate: An inexpensive method of manufacturing a semiconductor package using a redistribution substrate that is relatively thin. The method includes: attaching a semiconductor chip to a redistribution substrate; attaching the redistribution substrate to which the semiconductor chip is attached to a printed circuit board; removing a support substrate of the redistribution... Agent: Marger Johnson & Mccollom, P.C.
20090053859 - Non-random array anisotropic conductive film (acf) and manufacturing process: The present invention discloses structures and manufacturing processes of an ACF of improved resolution and reliability of electrical connection using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes the steps of (i) fluidic filling of conductive particles onto a substrate or carrier web... Agent: Wang, Hartmann & Gibbs
20090053857 - Semiconductor packaging method: The present invention relates to a semiconductor packaging method. The method comprises (S1) applying a die adhesive to an upper surface of a member through screen-printing; (S2) B-stage curing the member having the die adhesive; (S3) attaching a die on the B-stage cured die adhesive; (S4) wire-bonding the die to... Agent: Jones Day
20090053860 - Method for fabricating nanocoils: A method for fabricating nanocoils and improved nanocoils fabricated therefrom. Embodiments of the method utilizing deep reactive ion etching (DRIE). A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer, in which SOI wafer includes buried oxide layer, patterning one or more devices into a layer of silicon on... Agent: Andrews Kurth LLP
20090053862 - Active matrix organic el display device and manufacturing method thereof: An active matrix organic EL display device includes pixels each having an organic EL element (7a) and a pixel circuit (3) including a polysilicon TFT for controlling the organic EL element (7a) arranged adjacently in each of the regions partitioned into a matrix shape by data line (12) and gate... Agent: Young & Thompson
20090053861 - Method for fabricating pixel structure: A method for fabricating a pixel structure is provided. A substrate is provided, and a gate is formed on the substrate. A gate dielectric layer covering the gate is formed on the substrate. A semiconductor layer is formed on the gate dielectric layer. A first shadow mask exposing parts of... Agent: Jianq Chyun Intellectual Property Office
20090053863 - Mask and manufacturing method of a semiconductor device and a thin film transistor array panel using the mask: An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about −70° to about +70°.... Agent: Macpherson Kwok Chen & Heid LLP
20090053864 - Method for fabricating a semiconductor structure having heterogeneous crystalline orientations: A method for fabricating a semiconductor structure having heterogeneous crystalline orientations by forming a region including a semiconductor material having a specified crystalline orientation using an epitaxial buffer overlying a semiconductor substrate. The buffer provides a transfer body such that the semiconductor material has a crystalline orientation that differs from... Agent: Brinks Hofer Gilson & Lione
20090053865 - Method and apparatus for de-interlacing video data: Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions... Agent: Texas Instruments Incorporated
20090053866 - Nonvolatile semiconductor memory device, method for driving the same, and method for fabricating the same: A p-type source region 2 and a p-type drain region 3 are formed on the surface of an n-type semiconductor layer 1. In the position located above a channel region interposed between the p-type source region 2 and the p-type drain region 3 and overlapping the p-type drain region 3,... Agent: Mcdermott Will & Emery LLP
20090053867 - Plasma treated metal silicide layer formation: Devices and methods for plasma treated metal silicide layer formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a metal layer on a silicon substrate, exposing the metal layer to a plasma, and thermally treating the silicon substrate and the metal layer to form... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090053868 - Semiconductor memory device and manufacturing method for semiconductor device: The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory. The solution is a manufacturing method for semiconductor memory device including a process for forming sequentially a first oxide film 102, a first nitride... Agent: Rabin & Berdo, PC
20090053869 - Method for producing an integrated circuit including a trench transistor and integrated circuit: A method for producing an integrated circuit including a trench transistor and an integrated circuit is disclosed.... Agent: Dicke, Billig & Czaja
20090053870 - Method for preparing flash memory structures: A method for preparing a flash memory structure comprises the steps of forming a plurality of dielectric blocks having block sidewalls on a substrate, forming a plurality of first spacers on the block sidewalls of the dielectric blocks, removing a portion of the substrate not covered by the dielectric blocks... Agent: Wpat, PC Intellectual Property Attorneys
20090053871 - Method of fabricating semiconductor memory device: A semiconductor memory device and method of fabricating a semiconductor memory device, wherein a tunnel insulating layer, a first charge trap layer and an isolation mask layer are sequentially stacked over a semiconductor substrate in which a cell region and a peri region are defined. The isolation mask layer, the... Agent: Lowe Hauptman Ham & Berner, LLP
20090053872 - Method of manufacturing a bipolar transistor: The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate (11) which is provided with a first, a second and a third layer (1,2,3) of a first, second and third semiconductor material respectively, all of a first conductivity type. A first portion of the second... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090053873 - Method of forming semiconductor structure: A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate. Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to... Agent: Ingrassia Fisher & Lorenz, P.C.
20090053874 - Method of forming sti regions in electronic devices: The invention relates to a method of manufacturing integrated circuits and in particular to the step of forming shallow trench isolation (STI) zones. The method according to the present invention leads to electronic devices and to integrated circuits having reduced narrow width effect and edge leakage. This is achieved by... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090053875 - Manufacturing method for ssoi substrate: Provided is a method of manufacturing a strained silicon-on-insulator (SSOI) substrate that can manufacture an SSOI substrate by separating a bonded substrate using a low temperature heat treatment. The manufacturing method includes: providing a substrate; growing silicon germanium (SiGe) on the substrate to thereby form a SiGe layer; growing silicon... Agent: Knobbe Martens Olson & Bear LLP
20090053876 - Manufacturing method of semiconductor device and manufacturing apparatus of the same: Instead of forming a semiconductor film by bonding a bond substrate (semiconductor substrate) to a base substrate (supporting substrate) and then separating or cleaving the bond substrate, a bond substrate is separated or cleaved at a plurality of positions to form a plurality of first semiconductor films (mother islands), and... Agent: Eric Robinson
20090053877 - Method for producing a multilayer structure comprising a separating layer: Process for producing a multilayer structure that includes, within the depth thereof, a separating layer, including: producing an initial multilayer structure comprising a base substrate, a surface substrate and, between the base substrate and the surface substrate, an absorbent layer that can absorb a light power flux in at least... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20090053878 - Method for fabrication of semiconductor thin films using flash lamp processing: A method for creating a Group IV semiconductor densified thin film is disclosed. The method includes applying a colloidal dispersion to a substrate, wherein the colloidal dispersion includes a plurality of Group IV semiconductor nanoparticles and an organic solvent. The method also includes removing the organic solvent by applying a... Agent: Foley & Lardner LLP
20090053879 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device includes providing a semiconductor substrate in which a gate insulating layer and a pad layer are formed in an active region. A first trench is formed in an isolation region of the substrate. A passivation film is formed to cover the pad layer... Agent: Townsend And Townsend And Crew, LLP
20090053880 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material layer on a semiconductor substrate; forming a photoresist layer on the semiconductor substrate so as to expose extension region... Agent: Mcginn Intellectual Property Law Group, PLLC
20090053881 - Method of forming dielectric layer of semiconductor memory device: A method of forming a dielectric layer of a semiconductor memory device is provided. The method includes forming a first insulating layer over a semiconductor substrate, performing a first plasma treatment process in order to densify a film of the first insulating layer, and forming a high-k insulating layer, which... Agent: Townsend And Townsend And Crew, LLP
20090053882 - Krypton sputtering of thin tungsten layer for integrated circuits: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.
20090053883 - Method of setting a work function of a fully silicided semiconductor device, and related device: A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines... Agent: Texas Instruments Incorporated
20090053884 - Semiconductor memory device and manufacturing method thereof: An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floating electrodes and control electrodes are provided on the active... Agent: Volentine & Whitt PLLC
20090053885 - Manufacturing method of semiconductor memory device using insulating film as charge storage layer: A manufacturing method of a semiconductor memory device includes forming a first gate electrode having a charge storage layer, a block layer, and a control gate electrode on a first region of a semiconductor substrate, forming a second gate electrode on a second region of the semiconductor substrate, forming a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090053886 - High density chalcogenide memory cells: A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar... Agent: Stout, Uxa, Buyan & Mullins LLP
20090053887 - Wirebond pad for semiconductor chip or wafer: In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and... Agent: Megica Corporation
20090053888 - Method of depositing a diffusion barrier layer which provides an improved interconnect: A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer.... Agent: Shirley L. Church, Esq.
20090053889 - Method for forming a metal line in a semiconductor device: A semiconductor device includes contact plugs formed in contact holes defined in an interlayer dielectric. Upper portions of the contact plugs are etched. A first barrier layer is formed on a surface of the interlayer dielectric including the contact plugs. A second barrier layer is formed on the first barrier... Agent: Townsend And Townsend And Crew, LLP
20090053890 - Selective thin metal cap process: A method of creating metal caps on copper lines within an inter-line dielectric (ILD) deposits a thin (e.g., 5 nm) metal blanket film (e.g., Ta/TaN) on top the copper lines and dielectric, after the wafer has been planarized. Further a thin dielectric cap is formed over the metal blanket film.... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20090053891 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device for preventing a poisoned via is provided. A substrate with a conductive layer formed thereon is provided. A composite layer is formed over the substrate and the conductive layer, wherein the composite layer comprises a dielectric layer and a spin-on-glass layer. A via... Agent: Quintero Law Office, PC
20090053892 - Method of fabricating an integrated circuit: A method of fabricating an integrated circuit, including the steps of forming a first mask layer in the form of a hard mask layer including a plurality of first openings and a second mask layer with at least one second opening which at least partially overlaps with one of the... Agent: Slater & Matsil, L.L.P.
20090053893 - Atomic layer deposition of tungsten materials: Embodiments of the invention provide an improved process for depositing tungsten-containing materials. The process utilizes soak processes and vapor deposition processes, such as atomic layer deposition (ALD) to provide tungsten films having significantly improved surface uniformity and production level throughput. In one embodiment, a method for forming a tungsten-containing material... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090053894 - Method for manufacturing epitaxial wafer: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface... Agent: Duane Morris LLP - Ny Patent Department
20090053895 - Film forming method of porous film and computer-readable recording medium: There is provided a method for forming a porous dielectric film stably by: forming a surface densification layer by processing a surface of an SiOCH film formed by a plasma CVD process while using an organic silicon compound source; and releasing CHx groups or OH group from the SiOCH film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090053896 - Copper polishing slurry: A water-soluble polymer is effective as a removal rate enhancer in a chemical mechanical polishing slurry to polish copper on semiconductor wafers or other copper laid structures, while keeping the etching rate low. The slurry may also include soft particles and certain metal chelating agents, or combinations thereof. The slurry... Agent: Paul D. Greeley Ohlandt, Greeley, Ruggiero & Perle, L.L.P.
20090053897 - Method of fabricating a circuit board: A method of fabricating a circuit board is disclosed. The method includes: forming a trench in a base and forming an electroless plating layer over a surface of the base and an inner surface of the trench; providing a carrier, on one side of which a plating resist is coated;... Agent: Staas & Halsey LLP
20090053898 - Formation of a slot in a silicon substrate: A slot is formed that reaches through a first side of a silicon substrate to a second side of the silicon substrate. A trench is laser patterned. The trench has a mouth at the first side of the silicon substrate. The trench does not reach the second side of the... Agent: Hewlett Packard Company
20090053899 - Method of pattern formation in semiconductor fabrication: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate, forming a photo acid generator (PAG) layer on the substrate, exposing the PAG layer to radiation, and forming a photoresist layer on the exposed PAG layer. The exposed PAG layer generates an acid. The acid... Agent: Haynes And Boone, LLPIPSection
20090053900 - Processing apparatus and processing method: A processing apparatus includes a process container having a placing table for placing a processing object, an exhaust system having vacuum pumps and a pressure control valve for exhausting atmosphere in the process container. A gas injection unit having a gas ejection hole is provided in the process container, as... Agent: Masuvalley & Partners
20090053901 - High dose implantation strip (hdis) in h2 base chemistry: Plasma is generated using elemental hydrogen, a weak oxidizing agent, and a fluorine containing gas. An inert gas is introduced to the plasma downstream of the plasma source and upstream of a showerhead that directs gas mixture into the reaction chamber where the mixture reacts with the high-dose implant resist.... Agent: Weaver Austin Villeneuve & Sampson LLP
20090053902 - Low dielectric (low k) barrier films with oxygen doping by plasma-enhanced chemical vapor deposition (pecvd): Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090053903 - Silicon oxide film forming method, semiconductor device manufacturing method and computer storage medium: A plasma processing apparatus 100 of the RLSA type includes a planar antenna with a plurality of slots formed therein, by which microwaves are supplied into a process chamber to generate plasma. In this apparatus, poly-silicon oxidation is performed at a pressure of 67 to 667 Pa inside the chamber,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090053904 - Substrate processing method and computer storage medium: In the present invention, a coating solution containing polysilazane is applied to a substrate to form a coating film. Thereafter, an ultraviolet ray is applied to the coating film formed on the substrate to cut a molecular bond of polysilazane in the coating film. Then, the coating film in which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090053905 - Method of forming dielectric layer of semiconductor memory device: The invention relates to a method of forming a dielectric layer of a semiconductor memory device. According to an aspect of the invention, the method includes forming a high-k layer over a semiconductor substrate, and performing a plasma treating the high-k layer at a temperature less than the temperature in... Agent: Marshall, Gerstein & Borun LLP
20090053906 - Semiconductor device producing method and substrate processing apparatus: Disclosed is a producing method of a semiconductor device including: loading at least one substrate into a processing chamber; forming a metal oxide film or a silicon oxide film on a surface of the substrate by repeatedly supplying a metal compound or a silicon compound, each of which is a... Agent: Birch Stewart Kolasch & Birch02/19/2009 > patent applications in patent subcategories. patent applications/inventions, industry category
20090047747 - Method of forming an amorphous ferroelectric memory device: This disclosure relates to amorphous ferroelectric memory devices and methods for forming them.... Agent: Hewlett Packard Company
20090047748 - Enhanced sensitivity non-contact electrical monitoring of copper contamination on silicon surface: Methods of measuring copper impurities on a silicon surface are disclosed. In certain embodiments, copper is electrically activated by ultra-violet illumination of the surface at room temperature. Activation can enhance the copper contribution to surface recombination and to surface voltage which are measured in a non-contact manner using a ac-surface... Agent: Fish & Richardson P.C.
20090047749 - Methods of manufacturing thin film transistor and display device: A first patterned conductive layer is formed on a substrate. A dielectric layer, a semiconductor layer, a second conductive layer and a photoresist layer are formed above the first patterned conductive layer. The photoresist layer is patterned using a photomask with multiple different transparencies, and the patterned photoresist layer has... Agent: Bacon & Thomas, PLLC
20090047750 - Thin film transistor array substrate and fabrication method thereof: A thin film transistor array substrate is disclosed. A gate electrode is disposed overlying a substrate. A gate dielectric layer covers the substrate and the gate electrode. A semiconductor layer is disposed overlying the gate dielectric layer, wherein the semiconductor layer comprises a channel. A source electrode electrically connects a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090047751 - Method of fabricating semiconductor laser: There is provided a method of fabricating a semiconductor laser including a two-dimensional photonic crystal. The method comprises the steps of growing an InX1Ga1-X1N (0<X1<1) layer on a gallium nitride-based semiconductor region in a reactor; after taking out a substrate product including the InX1Ga1-X1N layer from the reactor, forming a... Agent: Venable LLP
20090047752 - Method for manufacturing photoelectric conversion device: It is an object to form a high-quality crystalline semiconductor layer directly over a large-sized substrate with high productivity without reducing the deposition rate and to provide a photoelectric conversion device in which the crystalline semiconductor layer is used as a photoelectric conversion layer. A photoelectric conversion layer formed of... Agent: Eric Robinson
20090047753 - Scaffold-organized clusters and electronic devices made using such clusters: A method for forming arrays of metal, alloy, semiconductor or magnetic clusters is described. The method comprises placing a scaffold on a substrate, the scaffold comprising, for example, polynucleotides and/or polypeptides, and coupling the clusters to the scaffold. Methods of producing arrays in predetermined patterns and electronic devices that incorporate... Agent: Klarquist Sparkman, LLP
20090047754 - Packaging method involving rearrangement of dice: A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice... Agent: Schneck & Schneck
20090047755 - Semiconductor package and manufacturing method therefor: A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the... Agent: Shimokaji & Associates, P.C.
20090047756 - Dual port gain cell with side and top gated read transistor: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the... Agent: Scully, Scott, Murphy & Presser, P.C.
20090047757 - Semiconductor device and method of manufacturing the same: In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090047761 - Manufacturing method of semiconductor device: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated... Agent: Eric Robinson
20090047759 - Method for manufacturing semiconductor device: After a gate insulating film is formed over a gate electrode, in order to improve the quality of a microcrystalline semiconductor film which is formed in an early stage of deposition, a film near an interface with the gate insulating film is formed under a first deposition condition in which... Agent: Eric Robinson
20090047760 - Method for manufacturing semiconductor device: Electric characteristics of a thin film transistor including a channel formation region including a microcrystalline semiconductor are improved. The thin film transistor includes a gate electrode, a gate insulating film formed over the gate electrode, a microcrystalline semiconductor layer formed over the gate insulating film, a semiconductor layer which is... Agent: Eric Robinson
20090047758 - Method of manufacturing display device: In a case of forming a bottom-gate thin film transistor, a step of forming a microcrystalline semiconductor film over a gate insulating film by a plasma CVD method, and a step of forming an amorphous semiconductor film over the microcrystalline semiconductor film are performed. In the step of forming the... Agent: Nixon Peabody, LLP
20090047762 - Apparatus and method for a memory array with shallow trench isolation regions between bit lines for increased process margins: The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP
20090047763 - Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20090047764 - Non-volatile memory and manufacturing method thereof: A non-volatile memory having a gate structure and a source/drain region is provided. The gate structure is disposed on a substrate. The gate structure includes a pair of floating gates, tunneling dielectric layers, a control gate and an inter-gate dielectric layer. The floating gates are disposed on the substrate. Each... Agent: Jianq Chyun Intellectual Property Office
20090047765 - Method of manufacturing non-volatile memory: A method of manufacturing a non-volatile memory is provided. In the method, a first dielectric layer, a first conductive layer, and a first cap layer are formed sequentially on a substrate. The first cap layer and the first conductive layer are patterned to form first gate structures. A second dielectric... Agent: Jianq Chyun Intellectual Property Office
20090047766 - Method for fabricating recess channel mos transistor device: A method for fabricating recess channel MOS transistors of the present invention utilizes a lithography process to form trenches in the recess channel MOS transistors after finishing a STI process. Furthermore, the method of the present invention can make the critical dimension variation to be controlled in a range required... Agent: North America Intellectual Property Corporation
20090047767 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a silicon substrate, a strain-inducing layer, a silicon layer, a FET, and an isolation region. On the silicon substrate, the strain-inducing layer is provided. On the strain-inducing layer, the silicon layer is provided. The strain-inducing layer induces lattice strain in a channel region of the FET... Agent: Mcginn Intellectual Property Law Group, PLLC
20090047768 - Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion beams: A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm−2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation... Agent: Texas Instruments Incorporated
20090047769 - Methods of forming a plurality of capacitors: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive... Agent: Wells St. John P.s.
20090047770 - Method of forming isolation regions for integrated circuits: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces... Agent: Amd-mke C/o Foley Lardner LLP
20090047771 - Manufacturing method and manufacturing apparatus of semiconductor device: To provide a manufacturing method of a semiconductor device using an SOI substrate, by which mobility can be improved. A plurality of semiconductor films formed using a plurality of bond substrates (semiconductor substrates) are bonded to one base substrate (support substrate). At least one of the plurality of bond substrates... Agent: Eric Robinson
20090047772 - Method for improving the quality of a sic crystal: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer... Agent: The Webb Law Firm, P.C.
20090047773 - Method of forming stable functionalized nanoparticles: A novel top-down procedure for synthesis of stable passivated nanoparticles uses a one-step mechanochemical process to form and passivate the nanoparticles. High-energy ball milling (HEBM) can advantageously be used to mechanically reduce the size of material to nanoparticles. When the reduction of size occurs in a reactive medium, the passivation... Agent: Garvey Smith Nehrbass & North, LLC
20090047774 - Plasma cvd apparatus, method for manufacturing microcrystalline semiconductor layer, and method for manufacturing thin film transistor: As an electrode area of a plasma CVD apparatus is enlarged, influence of the surface standing wave remarkably appears, and there is a problem in that in-plane uniformity of quality and a thickness of a thin film formed over a glass substrate is degraded. Two or more high-frequency electric powers... Agent: Eric Robinson
20090047775 - Method for manufacturing display device: The present invention relates to a method for manufacturing a display device including a p-channel thin film transistor and an n-channel thin film transistor having a microcrystalline semiconductor film each of which are an inverted-staggered type, and relates to a method for formation of an insulating film and a semiconductor... Agent: Eric Robinson
20090047776 - Method of forming a thin film transistor: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer... Agent: Wells St. John P.s.
20090047777 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes forming a gate electrode film on a semiconductor substrate via a gate insulating film; forming a mask film on the gate electrode film; separating the gate electrode film by using the mask film to form a plurality of gate electrodes; forming a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090047778 - Plasma oxidation method and method for manufacturing semiconductor device: A plasma oxidation processing method is performed, on a structural object including a silicon layer and a refractory metal-containing layer, to form a silicon oxide film. A first plasma oxidation process is performed by use of a process gas including at least hydrogen gas and oxygen gas and a process... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090047779 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, including: forming a first conductive layer on a first insulating film; forming a second insulating film so as to cover the first conductive layer; forming a resist mask on the second insulating film; forming a hole reaching the first conductive layer in the... Agent: Young & Thompson
20090047780 - Method for forming composite barrier layer: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two... Agent: Duane Morris LLP (tsmc)IPDepartment
20090047781 - Methods of forming through substrate interconnects: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from... Agent: Wells St. John P.s.
20090047782 - Method for manufacturing a device having a high aspect ratio via: Method for manufacturing a device having a conductive via includes the following steps. A dielectric material layer including a through hole is formed on a substrate. A seed metallic layer is formed on the dielectric material layer and in the through hole. A metallic layer is formed on the seed... Agent: Lowe Hauptman Ham & Berner, LLP
20090047783 - Method of removing unwanted plated or conductive material from a substrate, and method of enabling metallization of a substrate using same: A method of removing unwanted material from a substrate includes providing a system (600) having an etchant solution (610) with an electrode (620) therein and a current supply (630) connected to the electrode, placing the substrate in the solution and connecting it to the current supply, providing an electric current... Agent: Intel Corporation C/o Intellevate, LLC
20090047784 - Resist stripping methods using backfilling material layer: A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to... Agent: Scully, Scott, Murphy & Presser, P.C.
20090047785 - Cmp polishing method, cmp polishing apparatus, and process for producing semiconductor device: When the remaining slurry and polishing residue are removed by cleaning with a cleaning liquid (preferably a cleaning liquid containing a surfactant), organic matter in the cleaning liquid containing a surfactant seeps into the interlayer insulating film 3. Therefore, the substrate is subsequently washed with an organic solvent or a... Agent: Morgan Lewis & Bockius LLP
20090047786 - Cmp abrasive slurry for polishing insulation film, polishing method, and semiconductor electronic part polished by the polishing method: The present invention provides a CMP abrasive slurry for polishing insulation film, that allow efficiently and high-speed polishing of insulation films such as SiO2 film and SiOC film in the CMP method of flattening an interlayer insulation film, a BPSG film, an insulation film for shallow trench isolation, or a... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090047787 - Slurry containing multi-oxidizer and nano-abrasives for tungsten cmp: A chemical mechanical polishing slurry containing multiple oxidizers and nano abrasive particles (including engineered nano diamond particles) suitable for polishing multilayer substrate with tungsten and Ti/TiN barrier layers. The slurry contains no metallic catalyst and has low total abrasive particle content. The absence of metal ions can be advantageous for... Agent: Day Pitney LLP
20090047788 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns at certain intervals over a substrate where an etch target layer is formed, forming a sacrificial layer along a step of the substrate where the first hard mask patterns are formed, forming a second... Agent: Townsend And Townsend And Crew, LLP
20090047789 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming an amorphous carbon layer over a substrate, forming a hard mask pattern over the amorphous carbon layer, and etching the amorphous carbon layer with an etching gas including sulfur (S) using the hard mask pattern as an etch barrier. Deformation of... Agent: Townsend And Townsend And Crew, LLP
20090047790 - Selective wet etching of hafnium aluminum oxide films: Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlOx) material relative to silicon oxide (SiOx) are provided.... Agent: Whyte Hirschboeck Dudek S.c. Intellectual Property Department
20090047791 - Semiconductor etching methods: A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon... Agent: Hoffman Warnick LLC
20090047792 - Processes and equipments for preparing f2-containing gases, as well as process and equipments for modifying the surfaces of articles: A process for preparing an F2-containing gas comprises the steps of exciting at least one fluoro compound in a fluoro compound-containing gas by conferring energy on the fluoro compound-containing gas under reduced pressure; and partially or completely converting the excited fluoro compound-containing gas containing the excited fluoro compound into F2... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw
20090047794 - Method for manufacturing semiconductor device and storage medium: [Means for Solving the Problem] There is provided a step of etching an organic film in a multi-layered resist laminated on an etching target film on a substrate, the multi-layered resist including the organic film and a resist film having a resist pattern laminated on the organic film, by a... Agent: Smith, Gambrell & Russell
20090047793 - Method of manufacturing semiconductor device: Disclosed herein is a method of manufacturing a semiconductor device, including the step of ashing away by a plasma treatment an organic material film formed over a substrate with an inter-layer insulator film therebetween, wherein the plasma treatment is conducted while electric power applied so as to draw ions in... Agent: Sonnenschein Nath & Rosenthal LLP
20090047795 - Plasma processing apparatus, plasma processing method and storage medium: A plasma processing apparatus includes a first radio frequency (RF) power supply unit for applying a first RF power for generating a plasma from a processing gas to at least one of a first and a second electrode which are disposed facing each other in an evacuable processing chamber. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090047796 - Method of manufacturing a dielectric layer having plural high-k films: Nitridizing and optionally annealing plural high-k films layer-by-layer are performed to dope nitrogen into high-k films.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090047797 - Method for producing shock and tamper resistant microelectronic devices: A method of producing a microelectronic device resistant to tampering, inspection and damage from surrounding environment or operating conditions includes: (i) applying an adhesion layer on a circuit including a die fixed and electrically connected to a laminate substrate; (ii) spraying, through a flame spray process, a tamper resistant coating... Agent: Squire Sanders & Dempsey LLP
20090047798 - Method of forming high dielectric constant films using a plurality of oxidation sources: A method is provided for depositing a high dielectric constant (high-k) film for integrated circuits (ICs) by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The method includes exposing a substrate to one or more metal precursors and plurality of oxidation sources to deposit a high-k film with a... Agent: Tokyo Electron U.s. Holdings, Inc.
20090047799 - Gate oxide leakage reduction: A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation... Agent: Haynes And Boone, LLPIPSection02/12/2009 > patent applications in patent subcategories. patent applications/inventions, industry category
20090042320 - Methods for liquid transfer coating of three-dimensional substrates: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template... Agent: HulseyIPIntellectual Property Lawyers, P.C.
20090042321 - Apparatus and method for plasma doping: Gas supplied to gas flow passages of a top plate from a gas supply device by gas supply lines forms flow along a vertical direction along a central axis of a substrate, so that the gas blown from gas blow holes can be made to be uniform, and a sheet... Agent: Mcdermott Will & Emery LLP
20090042322 - Method for inspecting semiconductor device: According to the present invention, a method for inspecting a semiconductor device includes the steps of carrying out a first test for inspecting characteristic of semiconductor devices under a shielded (dark) condition to discriminate non-defective devices; and carrying out a second test to semiconductor devices, which have been passed the... Agent: Volentine & Whitt PLLC
20090042323 - Probe card, semiconductor inspecting apparatus, and manufacturing method of semiconductor device: A frame bonded and fixed to a back face of a probe sheet so as to surround a group of pyramid-shaped or truncated pyramid-shaped contact terminals collectively formed at a central region portion of the probe sheet on a probing side thereof is protruded from a multi-layered wiring board, and... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.
20090042324 - Substrate supporting apparatus: A substrate supporting apparatus includes first and second shafts spaced by a distance that corresponds to or exceeds a width of a substrate, and at least one wire to support the substrate. The wire has ends coupled to respective ones of the first and second shafts. The wire is raised... Agent: Ked & Associates, LLP
20090042325 - Semiconductor light emitting device and method for manufacturing the same: In a semiconductor light emitting device, a semiconductor light emitting element has a light extracted surface on which a plurality of convex structures is formed. The convex structures each have a conical mesa portion constituting a refractive index gradient structure, a cylindrical portion constituting a diffraction grating structure, and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090042326 - Display device and method for manufacturing the same: According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO.... Agent: Fish & Richardson P.C.
20090042327 - Method for assembling array-type semiconductor laser device: According to an aspect of the present invention, there is provided a method for assembling a semiconductor laser device, including: preparing a laser chip including: a substrate; stripe waveguides that are formed on the substrate and that each includes a gain producing area and a window area; electrodes formed on... Agent: Mcginn Intellectual Property Law Group, PLLC
20090042329 - Laser process for reliable and low-resistance electrical contacts: Disclosed is a method for manufacturing an organic optoelectronic device. The method comprises providing a substrate, disposing a first electrode on the substrate, disposing a metal pad on the substrate, electrically separated from the first electrode, disposing a first material over the first electrode and at least partially over the... Agent: Fish & Richardson P.C.
20090042328 - Semiconductor light emitting device: At least one recess and/or protruding portion is created on the surface portion of a substrate for scattering or diffracting light generated in a light emitting region. The recess and/or protruding portion has a shape that prevents crystal defects from occurring in semiconductor layers.... Agent: Morrison & Foerster LLP
20090042330 - Etching of solar cell materials: A solar cell is fabricated by etching one or more of its layers without substantially etching another layer of the solar cell. In one embodiment, a copper layer in the solar cell is etched without substantially etching a topmost metallic layer comprising tin. For example, an etchant comprising sulfuric acid... Agent: Okamoto & Benedicto LLP
20090042331 - Pinned photodiode (ppd) pixel with high shutter rejection ratio for snapshot operating cmos sensor: A method for forming a pixel image sensor that has a high shutter rejection ratio for preventing substrate charge leakage and prevents generation of photoelectrons within a floating diffusion storage node and storage node control transistor switches of the pixel image sensor. The pixel image sensor that prevents substrate charge... Agent: Saile Ackerman LLC
20090042332 - Methods for fabricating a cmos image sensor: A method for fabricating a CMOS image sensor includes providing a substrate having a sensor array region and a peripheral region defined thereon, forming at least a contact pad on the substrate of the peripheral region, forming a first dielectric layer covering the contact pad on the substrate, performing a... Agent: North America Intellectual Property Corporation
20090042333 - Structure and method for surfaced-passivated zinc-oxide: A semiconductor device has a heterostructure including a first layer of semiconductor oxide material. A second layer of semiconductor oxide material is formed on the first layer of semiconductor oxide material such that a two dimensional electron gas builds up at an interface between the first and second materials. A... Agent: Marger Johnson & Mccollom/parc
20090042334 - Cmos image sensor and method for fabricating the same: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth,... Agent: Morgan Lewis & Bockius LLP
20090042335 - Vertical side wall active pin structures in a phase change memory and manufacturing methods: A programmable resistor memory, such as a phase change memory, with a memory element comprising narrow vertical side wall active pins is described. The side wall active pins comprise a programmable resistive material, such as a phase change material. In a first aspect of the invention, a method of forming... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20090042336 - Fabrication method of an organic substrate having embedded active-chips: The fabrication method of an organic substrate having embedded active-chips such as semiconductor chips is disclosed. The present invention previously applies the conductive adhesives in a wafer state, makes them in a B-stage state, obtains individual semiconductor chips through dicing, and positions the individual semiconductor chips previously applied with the... Agent: The Nath Law Group
20090042337 - Method of manufacturing an integrated circuit module: A method includes providing an integral array of first carriers, arranging first semiconductor chips on the first carriers, and arranging an integral array of second carriers over the semiconductor chips.... Agent: Edell , Shapiro & Finnan , LLC
20090042338 - Capping coating for 3d integration applications: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A... Agent: Scully, Scott, Murphy & Presser, P.C.
20090042339 - Packaged integrated circuits and methods to form a packaged integrated circuit: Packaged integrated circuits and methods to form a packaged integrated circuit are disclosed. A disclosed method comprises attaching an integrated circuit to a substrate, coupling a first end of a bond wire directly to the substrate without an intervening bonding pad and a second end of the bond wire to... Agent: Texas Instruments Incorporated
20090042340 - Nonvolatile storage device and method of manufacturing the same, and storage device and method of manufacturing the same: A nonvolatile storage device includes a plurality of bit lines 21 arranged in a column direction on a substrate; a plurality of word lines 35 arranged in a row direction on the substrate; a memory cell array 20 having a plurality of memory cells 31, where a store state of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090042341 - Electrical fuse with a thinned fuselink middle portion: A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces... Agent: Scully, Scott, Murphy & Presser, P.C.
20090042342 - Method for crystallization of amorphous silicon by joule heating: The present invention provides a method for preparation of crystallization of amorphous silicon thin film, which comprises providing a forming a amorphous silicon on a dielectric film formed on a transparent substrate; then forming a conductive layer on the top surface of substrate; applying an electric field to the conductive... Agent: Cantor Colburn, LLP
20090042343 - Methods of fabricating crystalline silicon, thin film transistors, and solar cells: The present invention includes methods to crystallize amorphous silicon. A structure including a conductive film with at least one conductive layer in thermal contact with an amorphous silicon (a-Si) layer to be crystallized is exposed to an alternating or varying magnetic field. The conductive film is more easily heated by... Agent: Brown & Michaels, PC 400 M & T Bank Building
20090042344 - Inp-based transistor fabrication: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to... Agent: Goodwin Procter LLP Patent Administrator
20090042345 - Methods of fabricating transistors having buried n-type and p-type regions beneath the source region: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include... Agent: Myers Bigel Sibley & Sajovec, P.A.
20090042346 - Electrolyte pattern and method for manufacturing an electrolyte pattern: A method for manufacturing a gel electrolyte pattern is disclosed, the method comprising depositing an electrolyte precursor by inkjet printing onto a gelling agent layer. A gel electrolyte pattern is also disclosed, the gel electrolyte pattern comprising either a mixture of a gelling agent and an electrolyte precursor or the... Agent: Oliff & Berridge, PLC
20090042347 - Method for manufacturing vertical mos transistor: A method for manufacturing a vertical MOS transistor comprising forming a protrusion-like region, forming a silicon oxide film on an exposed surface of the protrusion-like region and a surface of the silicon semiconductor substrate, increasing a film thickness of at least the silicon oxide film on the silicon semiconductor substrate... Agent: Sughrue Mion, PLLC
20090042348 - Method for manufacturing semiconductor device: In the present invention, there is provided a method for manufacturing a semiconductor device that has on a semiconductor substrate first and second transistor groups having different operating voltages respectively, the first transistor group having a first gate electrode, the second transistor group having a second gate electrode, the method... Agent: Sonnenschein Nath & Rosenthal LLP
20090042349 - Split gate memory cell and method therefor: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has... Agent: Freescale Semiconductor, Inc. Law Department
20090042350 - Manufacturing method of nonvolatile memory: A manufacturing method for a non-volatile memory includes first providing a substrate with a gate structure formed thereon. The gate structure includes a first gate and a gate dielectric layer located between the first gate and the substrate. A first doping and a second doping region are formed on the... Agent: Jianq Chyun Intellectual Property Office
20090042351 - Method for making a transistor with a stressor: A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming... Agent: Freescale Semiconductor, Inc. Law Department
20090042352 - Gate interface relaxation anneal method for wafer processing with post-implant dynamic surface annealing: Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation... Agent: Law Office Of Robert M. Wallace
20090042353 - Integrated circuit fabrication process for a high melting temperature silicide with minimal post-laser annealing dopant deactivation: Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel.... Agent: Robert M. Wallace Law Office Of Robert M. Wallace
20090042354 - Integrated circuit fabrication process using a compression cap layer in forming a silicide with minimal post-laser annealing dopant deactivation: Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter,... Agent: Robert M. Wallace Law Office Of Robert M. Wallace
20090042355 - Semiconductor wafer and manufacturing method therefor: A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to... Agent: Dickstein Shapiro LLP
20090042356 - Peeling method and method of manufacturing semiconductor device: There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high... Agent: Fish & Richardson P.C.
20090042357 - Method of selective oxygen implantation to dielectrically isolate semiconductor devices using no extra masks: A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also... Agent: Stallman & Pollock LLP
20090042358 - Semiconductor device and method of fabricating same: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench... Agent: Foley And Lardner LLP Suite 500
20090042359 - Structure and method of producing isolation with non-dopant implantation: A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the... Agent: Slater & Matsil LLP
20090042360 - Strained semiconductor by full wafer bonding: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined... Agent: Schwegman, Lundberg & Woessner/micron
20090042361 - Method for manufacturing soi substrate and soi substrate: According to the present invention, there is provided a method for manufacturing an SOI substrate based on a bonding method, comprising at least: forming a silicon oxide film on a surface of at least one of a single-crystal silicon substrate that becomes an SOI layer and a single-crystal silicon substrate... Agent: Oliff & Berridge, PLC
20090042362 - Manufacturing methods of soi substrate and semiconductor device: A manufacturing method of an SOI substrate and a manufacturing method of a semiconductor device are provided. When a large-area single crystalline semiconductor film is formed over an enlarged substrate having an insulating surface, e.g., a glass substrate by an SOI technique, the large-area single crystalline semiconductor film is formed... Agent: Eric Robinson
20090042363 - Method for manufacturing bonded wafer and outer-peripheral grinding machine of bonded wafer: The present invention provides a method for manufacturing a bonded wafer, which includes at least the steps of bonding a bond wafer and a base wafer, grinding an outer peripheral portion of the bonded bond wafer, etching off an unbonded portion of the ground bond wafer, and then reducing a... Agent: Oliff & Berridge, PLC
20090042364 - Method for manufacturing soi wafer and soi wafer: The present invention provides a method for manufacturing an SOI wafer in which a thickness of an SOI layer is increased by growing an epitaxial layer on the SOI layer of the SOI wafer having an oxide film and the SOI layer formed on a base wafer, wherein the epitaxial... Agent: Oliff & Berridge, PLC
20090042365 - Three-dimensional face-to-face integration assembly: A via for connecting metallization layers of chips bonded in a face-to-face configuration is provided, as well as methods of fabricating the via. The via may function as an interconnection of metallization layers in three-dimensional, stacked, integrated circuits, and may enable high density, low-resistance interconnection formation.... Agent: Wolf Greenfield & Sacks, P.C.
20090042367 - Sawing method for a semiconductor element with a microelectromechanical system: The present invention relates to a sawing method for a Micro Electro-Mechanical Systems (MEMS) semiconductor device. A gum material is disposed between a wafer having at least one MEMS and a carrier, and the gum material is disposed around the MEMS. The wafer is sawed according to the position correspondingly... Agent: Volentine & Whitt PLLC
20090042366 - Semiconductor die singulation method: In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700
20090042368 - Wafer processing method: A wafer processing method for dividing, along streets, a wafer having a device area where devices are formed in a plurality of areas sectioned by the plurality of streets arranged in a lattice pattern on the front surface of a substrate and a peripheral extra area and comprising electrodes which... Agent: Smith, Gambrell & Russell
20090042369 - Method and structure using selected implant angles using a linear accelerator process for manufacture of free standing films of materials: A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes... Agent: Townsend And Townsend And Crew, LLP
20090042370 - Method of cutting pcbs: The present invention relates to a method of cutting PCB module using a laser. The method includes steps of: providing a coverlay film, the coverlay film including at least one opening defined therein; attaching the coverlay film onto the PCB module such that the through holes of the PCB module... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang
20090042371 - Laser crystallization process and laser process: The present invention provides a laser crystallization process applicable to a fabrication of a stack device structure. The process starts with providing a substrate having active devices formed thereon. Next, a first dielectric layer is formed on the substrate, and a multi-layer reflective layer is formed on the first dielectric... Agent: Jianq Chyun Intellectual Property Office
20090042372 - Polysilicon deposition and anneal process enabling thick polysilicon films for mems applications: A method of forming a thick polysilicon layer for a MEMS inertial sensor includes forming a first amorphous polysilicon film on a substrate in an elevated temperature environment for a period of time such that a portion of the amorphous polysilicon film undergoes crystallization and grain growth at least near... Agent: Bromberg & Sunstein LLP
20090042373 - Process of forming an electronic device including a doped semiconductor layer: A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor... Agent: Larson Newman Abel & Polansky, LLP
20090042374 - Method of growing a strained layer: A method of forming a Si strained layer 16 on a Si substrate 10 includes forming a first SiGe buffer layer 12 on the Si substrate 10. Then, the first SiGe buffer layer is implanted with an amorphising implant to render the first SiGe buffer layer amorphous using ion implantation.... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090042375 - Method of manufacturing silicon carbide semiconductor device: A method of manufacturing a silicon carbide semiconductor device includes a step of ion-implanting an impurity in a surface of a silicon carbide wafer (1 and 2); a step of forming a carbon protection film (6) of a predetermined thickness over the entire surface of the silicon carbide wafer (1... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090042376 - Integrated circuit fabrication process with minimal post-laser annealing dopant deactivation: Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.... Agent: Robert M. Wallace Law Office Of Robert M. Wallace
20090042377 - Method for forming self-aligned wells to support tight spacing: Methods include utilizing a single mask layer to form tightly spaced, adjacent first-type and second-type well regions. The mask layer is formed over a substrate in a region in which the second-type well regions will be formed. The first-type well regions are formed in the exposed portions of the substrate.... Agent: Texas Instruments Incorporated
20090042378 - Use of a polymer spacer and si trench in a bitline junction of a flash memory cell to improve tpd characteristics: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one... Agent: Amin, Turocy & Calvin, LLP
20090042379 - Method for fabricating semiconductor device capable of adjusting the thickness of gate oxide layer: The present invention provides a method for fabricating semiconductor device, which is capable of adjusting a gate oxide layer thickness, including: providing a semiconductor substrate; growing a first oxide layer on a surface of the semiconductor substrate; patterning the first oxide layer to expose the first oxide layer corresponding to... Agent: Squire, Sanders & Dempsey L.L.P.
20090042380 - Semiconductor device and method of manufacturing the same: A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including... Agent: Mcdermott Will & Emery LLP
20090042381 - High-k gate dielectric and method of manufacture: A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that... Agent: Slater & Matsil, L.L.P.
20090042382 - Device packages: Low volume production of electronic devices having ball attachments, e.g. solder ball arrays, is advantageously achieved using a specific method. In particular a stencil having holes in, for example, the ball grid array pattern is formed by laser ablation of the holes in materials such as paper and polymers. The... Agent: Hitt Gaines, PC Lsi Corporation
20090042383 - Method of fabricating a semiconductor device: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and... Agent: F. Chau & Associates, LLC
20090042384 - Semiconductor device manufacturing method and target substrate processing system: A semiconductor device manufacturing method includes removing copper deposits, by use of an organic acid gas and an oxidizing gas, from a surface of a second interlayer insulation film having a groove formed therein and reaching a copper-containing electric connector member. The second interlayer insulation film is disposed on a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090042385 - Method of manufacturing metal line: A method of manufacturing a metal line according to embodiments includes forming an interlayer dielectric layer over a semiconductor substrate. A dielectric layer is formed over the interlayer dielectric layer. A trench may be formed by etching the dielectric layer and the interlayer dielectric layer. A metal material may be... Agent: Sherr & Vaughn, PLLC
20090042386 - Semiconductor device using metal nitride as insulating film and its manufacture method: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090042387 - Manufacturing method of semiconductor device: To provide a manufacturing method of a semiconductor device in which manufacturing cost can be reduced, and a manufacturing method of a semiconductor device with reduced manufacturing time and improved yield. A manufacturing method of a semiconductor device is provided, which includes the steps of forming a first layer containing... Agent: Eric Robinson
20090042389 - Double exposure semiconductor process for improved process margin: A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the... Agent: Xilinx, Inc Attn: Legal Department
20090042388 - Method of cleaning a semiconductor substrate: A semiconductor substrate is first provided. The semiconductor substrate includes a material layer and a patterned photoresist layer disposed on the material layer. Subsequently, a contact etching process is performed on the material layer by utilizing the patterned photoresist layer as an etching mask so to form an etched hole... Agent: North America Intellectual Property Corporation
20090042390 - Etchant for silicon wafer surface shape control and method for manufacturing silicon wafers using the same: It is possible to reduce workloads of a both-side simultaneous polishing process or a single-side polishing process, and to achieve both of the maintenance of the wafer flatness and the reduction in wafer front side roughness upon completing a flattening process. A method for manufacturing silicon wafers according to the... Agent: Duane Morris LLP - Ny Patent Department
20090042391 - Methods for forming patterns: A method for forming patterns comprises providing a substrate. A set of seed features is formed over the substrate. At least one bi-layer comprising a first layer followed by a second layer is formed on the set of seed features. The first layer and the second layer above the set... Agent: Quintero Law Office, PC
20090042392 - Polishing apparatus, substrate manufacturing method, and electronic apparatus manufacturing method: A polishing apparatus is configured to simultaneously polish both surfaces of a work and includes a sun gear provided around a rotational axis of one of a pair of polishing surfaces, a carrier having a hole configured to house the work, and including teeth so as to serve as a... Agent: Staas & Halsey LLP
20090042393 - Production method of polishing composition: A production method of a semiconductor device including: producing a polishing composition containing zirconium oxide sol; and planarizing a substrate having an uneven surface with said polishing composition, wherein the polishing composition containing zirconium oxide is produced by the steps comprising: baking at a temperature ranging from 400 to 1000°... Agent: Oliff & Berridge, PLC
20090042394 - Manufacturing method for wiring: In the case in which a film for a resist is formed by spin coating, there is a resist material to be wasted, and the process of edge cleaning is added as required. Further, when a thin film is formed on a substrate using a vacuum apparatus, a special apparatus... Agent: Nixon Peabody, LLP
20090042395 - Spacer process for cmos fabrication with bipolar transistor leakage prevention: A two-step spacer etch is used for the formation of a spacer in CMOS fabrication. A dry etch is first applied to remove part of the spacer material on the silicon substrate and leave a thin layer of the spacer material remained on the silicon substrate. Then, a wet etch... Agent: Rosenberg, Klein & Lee
20090042396 - Methods of forming semiconductor devices using selective etching of an active region through a hardmask: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask... Agent: Myers Bigel Sibley & Sajovec
20090042397 - Copper re-deposition preventing method, semiconductor device manufacturing method, and substrate processing apparatus: A copper re-deposition preventing method includes placing inside a chamber a target substrate with a film including a copper-containing substance and formed thereon, and performing removal of the copper-containing substance from the target substrate placed inside the chamber, by dry cleaning using an organic compound. Then, the method includes unloading... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090042398 - Method for etching low-k material using an oxide hard mask: A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiOx) layer formed on the SiCOH-containing layer, and a mask layer formed on the silicon oxide... Agent: Tokyo Electron U.s. Holdings, Inc.
20090042399 - Method for dry develop of trilayer photoresist patterns: A method of forming a feature on a multi-layer semiconductor is disclosed. A pattern feature is formed in an uppermost layer of the multi-layer semiconductor. The multilayer semiconductor is etched with a SO2 based chemistry to extend the pattern feature to a lower layer of the multi-layer semiconductor. Use of... Agent: Texas Instruments Incorporated
20090042400 - Silicon surface preparation: Methods are provided for producing a pristine hydrogen-terminated silicon wafer surface with high stability against oxidation. The silicon wafer is treated with high purity, heated dilute hydrofluoric acid with anionic surfactant, rinsed in-situ with ultrapure water at room temperature, and dried. Alternatively, the silicon wafer is treated with dilute hydrofluoric... Agent: Knobbe, Martens, Olson & Bear LLP
20090042401 - Compositions and methods for substantially equalizing rates at which material is removed over an area of a structure or film that includes recesses or crevices: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus,... Agent: Trask Britt, P.C./ Micron Technology
20090042402 - Method for fabricating semiconductor device: A semiconductor device fabrication method by which a desired pattern can be formed. After a conductive layer which is a material for a gate electrode is formed, a SiN layer to be used as a hard mask is formed. Then a photoresist layer is formed as a second mask. Then... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20090042403 - Method for fabricating semiconductor device and semiconductor device: A method for fabricating a semiconductor device includes the steps of forming a nitrogen-containing layer in an exposed portion of a copper interconnect formed in an insulating film provided on a substrate; and forming an interlayer insulating film on the nitrogen-containing layer through plasma CVD performed by using, as a... Agent: Mcdermott Will & Emery LLP
20090042404 - Semiconductor processing: Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature.... Agent: Brooks, Cameron & Huebsch , PLLC
20090042405 - Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and... Agent: Intel Corporation C/o Intellevate, LLC
20090042406 - Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands: A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more precursor compounds that include aminosilane ligands.... Agent: Mueting, Raasch & Gebhardt, P.A.
20090042407 - Dual top gas feed through distributor for high density plasma chamber: A gas distributor for use in a semiconductor process chamber comprises a body. The body includes a first channel formed within the body and adapted to pass a first fluid from a first fluid supply line through the first channel to a first opening. A second channel is formed within... Agent: Townsend And Townsend And Crew LLP
20090042408 - Semiconductor device manufacturing method and substrate processing apparatus: A semiconductor device manufacturing method comprises a process of forming a film on each of multiple substrates arrayed in a processing chamber by a thermal CVD method by supplying a film forming gas into the processing chamber while heating the interior of the processing chamber, wherein in the film forming... Agent: Kratz, Quintos & Hanson, LLP02/05/2009 > patent applications in patent subcategories. patent applications/inventions, industry category
20090035877 - Methods of forming a ferroelectric layer and methods of manufacturing a ferroelectric capacitor including the same: A method of forming a ferroelectric layer is provided. A metal-organic source gas is provided into a chamber into which an oxidation gas is provided for a first time period to form ferroelectric grains on a substrate. A ferroelectric layer is formed by performing at least twice a step of... Agent: Myers Bigel Sibley & Sajovec
20090035879 - Laser dicing device and laser dicing method: An object is to provide a laser dicing apparatus and a laser dicing method capable of speedily performing high-quality dicing without causing any working defect even in a case where wafers varying in thickness are supplied. The laser dicing apparatus is provided with a measuring device which measures thickness of... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department
20090035880 - Maunfacturing method for exposure mask, generating method for mask substrate information, mask substrate, exposure mask, manufacturing method for semiconductor device and server: There is disclosed a manufacturing method for exposure mask, which comprises acquiring a first information showing surface shape of surface of each of a plurality of mask substrates, and a second information showing the flatness of the surface of each of mask substrates before and after chucked on a mask... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090035878 - Plasma doping method and apparatus: A plasma doping method of generating a plasma in a vacuum chamber and colliding an ion in the plasma with a surface of a sample to modify a surface of a crystal sample to be amorphous, includes the steps of carrying out a plasma irradiation over a dummy sample to... Agent: Mcdermott Will & Emery LLP
20090035881 - Method for manufacturing semiconductor device: A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090035882 - Method and apparatus for affecting surface composition of cigs absorbers formed by two-stage process: A method and system to modify a surface composition of thin film Group IBIIIA VIA solar cell absorbers having non-uniformly distributed Group IIIA materials or graded materials, such as Indium (In), gallium (Ga) and aluminum (Al). The graded materials distribution varies between the surface and the bottom of the absorber... Agent: Pillsbury Winthrop Shaw Pittman LLP
20090035883 - Auto routing for optimal uniformity control: A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step;... Agent: Slater & Matsil, L.L.P.
20090035884 - Method for manufacturing surface-emitting laser: Provided is a method for manufacturing a surface-emitting laser capable of forming a photonic crystal structure inside a semiconductor highly accurately and easily without direct bonding. It is a method by laminating on a substrate a plurality of semiconductor layers including an active layer and a semiconductor layer having a... Agent: Fitzpatrick Cella Harper & Scinto
20090035885 - Methods of forming light-emitting structures: Methods of forming light-emitting structures, as well as related devices and/or systems are described. In some cases, the methods utilize a layer transfer and/or layer separation step(s) used to form such structures.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.
20090035886 - Predoped transfer gate for a cmos image sensor: A novel CMOS image sensor Active Pixel Sensor (APS) cell structure and method of manufacture. Particularly, a CMOS image sensor APS cell having a predoped transfer gate is formed that avoids the variations of Vt as a result of subsequent manufacturing steps. According to the preferred embodiment of the invention,... Agent: Scully, Scott, Murphy & Presser, P.C.
20090035887 - Solid-state image pickup element, method for manufacturing such solid-state image pickup element and optical waveguide forming device: A solid-state imaging device of the present invention includes a base 13, a plurality of photoelectric conversion portions 11 formed in a surface of the base 13, and an insulating film 18 formed above the base 13. Openings 18h are formed in the insulating film 18 so that each of... Agent: Hamre, Schumann, Mueller & Larson P.C.
20090035888 - Two epitaxial layers to reduce crosstalk in an image sensor: An image sensor includes a substrate of a first conductivity type having an image area with a plurality of photosensitive sites, wherein a portion of the charge generated in response to light is collected in the pixel; and a subcollector of a second conductivity spanning the image area that collects... Agent: Pedro P. Hernandez Patent Legal Staff
20090035889 - Cmos image sensor and method for manufacturing the same: Provided is a CMOS image sensor. The CMOS image sensor can include a semiconductor substrate, a blue photodiode region, a red photodiode region, a green photodiode region, an overcoat layer, and microlenses. The substrate can have a first photodiode region, a second photodiode region, and a transistor region. The blue... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association
20090035890 - Techniques for direct encasement of circuit board structures: A technique for processing an electronic apparatus (e.g., manufacturing an assembled circuit board, treating an assembled circuit board, etc.) involves applying encasement material to an area of the circuit board assembly while leaving at least a portion of the circuit board assembly exposed. The technique further involves causing the applied... Agent: Bainwood Huang & Associates LLC
20090035891 - Method and apparatus for flip-chip bonding: Provided are a laser flip-chip bonding method having high productivity and excellent bonding reliability and a flip-chip bonder employing the same. The flip-chip bonder includes: a bonding stage on which a substrate rests; a bonding head picking up a semiconductor chip and attaching the semiconductor chip to the substrate; and... Agent: Drinker Biddle & Reath LLP Attn: Patent Docket Dept.
20090035892 - Component bonding method, component laminating method and bonded component structure: Provided is a component bonding method of bonding a semiconductor component (13) having a thermosetting adhesive layer (13a) formed on a lower surface thereof to a circuit board (5) having a resin layer formed on a surface thereof. In the method, wettability is improved by surface modification that performs a... Agent: Pearne & Gordon LLP
20090035894 - Apparatus and method for bonding silicon wafer to conductive substrate: A system and method is disclosed for bonding a substrate to a semiconductor die that is prone to curling when subjected to an elevated temperature in a solder reflow oven, for example, thereby improving the electrical and mechanical bonding for large dies, wafers, chips, and photovoltaic cells. In one embodiment,... Agent: Andrew S. Naglestad
20090035893 - Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an... Agent: Sughrue Mion, PLLC
20090035895 - Chip package and chip packaging process thereof: A chip package comprises a substrate, a chip, a conductive layer and a molding compound. The substrate has a carrying surface and at least a ground pad disposed on the carrying surface. The chip has an active surface and a back surface opposite thereto. The chip is bonded to the... Agent: J C Patents, Inc.
20090035896 - High power mcm package with improved planarity and heat dissipation: A structure and a manufacturing method providing improved coplanarity accommodation and heat dissipation in a multi-chip module. One of the components in a multi-chip module (MCM) is provided with a recess formed in its respective top surface; and a film is applied so as to cover the top surfaces of... Agent: Ostrolenk Faber Gerb & Soffen
20090035897 - Hybrid orientation cmos with partial insulation process: The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of the devices is improved in the present invention by forming the source/drain... Agent: Scully, Scott, Murphy & Presser, P.C.
20090035898 - Method of fabricating a layer with tiny structure and thin film transistor comprising the same: A method of fabricating a layer with a tiny structure and a thin film transistor comprising the same is disclosed. The method of fabricating the layer with a tiny structure comprises providing a substrate, coating a coating composition on the substrate to form a coating layer, wherein the coating composition... Agent: Quintero Law Office, PC
20090035899 - Microelectronic device: A thin film transistor is manufactured by a process including forming an oxide semiconductor channel, patterning the oxide semiconductor channel with a photolithographic process, and exposing the patterned oxide semiconductor channel to an oxygen containing plasma.... Agent: Hewlett Packard Company
20090035900 - Method of forming high density trench fet with integrated schottky diode: A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of... Agent: Townsend And Townsend And Crew, LLP
20090035901 - Method for fabricating memory device with recess channel mos transistor: A method for fabricating line type recess channel MOS transistors utilizes a lithography process to form line type gate trenches in the line type recess channel MOS transistors before finishing a STI process. The method can further control the critical dimension variation in a range required in precision semiconductor processes.... Agent: North America Intellectual Property Corporation
20090035902 - Integrated method of fabricating a memory device with reduced pitch: Provided is a method of fabricating a memory device. A substrate including an array region and a peripheral region is provided. A first feature and a second feature are formed in the array region. The first feature and the second feature have a first pitch. A plurality of spacers abutting... Agent: Haynes And Boone, LLPIPSection
20090035904 - Methods of forming non-volatile memory having tunnel insulator of increasing conduction band offset: Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites... Agent: Leffert Jay & Polglaze, P.A. Att: Andrew C. Walseth
20090035903 - Semiconductor devices and methods of fabricating the same: Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed... Agent: Mills & Onello LLP
20090035905 - Insitu formation of inverse floating gate poly structures: Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.... Agent: Cool Patent, P.C. C/o Intellevate
20090035906 - Method of manufacturing a non-volatile semiconductor device: Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer... Agent: Harness, Dickey & Pierce, P.L.C
20090035907 - Method of forming stacked gate structure for semiconductor memory: A method of manufacturing a nonvolatile semiconductor memory comprising: forming a gate insulating film formed on a surface of a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate; forming a floating gate electrode on the gate insulating film; forming a inter-gate insulating film on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.
20090035908 - Process for fabricating a nanowire-based vertical transistor structure: The invention relates to a process for fabricating a vertical transistor structure. On a substrate (10), is a first conductive layer (11), providing the source or drain electrode function, and an upper conductive layer (17), providing the drain or source electrode function. The production of a membrane includes a stack... Agent: Lowe Hauptman & Berner, LLP
20090035909 - Method of fabrication of a finfet element: The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided... Agent: Haynes And Boone, LLPIPSection
20090035910 - Method of forming the ndmos device body with the reduced number of masks: This disclosure describes an improved process and resulting structure that allows a single masking step to be used to define both the body and the threshold adjustment layer of the body. The method consists of forming a first mask on a surface of a substrate with an opening exposing a... Agent: Barnes & Thornburg LLP
20090035911 - Method for forming a semiconductor device having abrupt ultra shallow epi-tip regions: A method for forming a semiconductor device having abrupt ultra shallow epi-tip regions comprises forming a gate stack on a crystalline substrate, performing a first ion implantation process to amorphisize a first pair of regions of the substrate disposed adjacent to and on laterally opposite sides of the gate stack,... Agent: Intel Corporation C/o Intellevate, LLC
20090035912 - Semiconductor device and fabrication method thereof: In order to diversify a current control method of a semiconductor device, improve performance (including a current drive performance) of the semiconductor device, and reduce a size of the semiconductor device, a second gate may be formed inside a substrate that forms a channel upon applying a bias voltage thereto.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20090035913 - High-capacitance density thin film dielectrics having columnar grains formed on base-metal foils: Deposited thin-film dielectrics having columnar grains and high dielectric constants are formed on heat treated and polished metal foil. The sputtered dielectrics are annealed at low oxygen partial pressures.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center
20090035914 - Isolation trench processing for strain control: A semiconductor fabrication process includes forming a hard mask, e.g., silicon nitride, over an active layer of a silicon on insulator (SOI) wafer, removing a portion of the hard mask and the active layer to form a trench, and forming an isolation dielectric in the trench where the dielectric exerts... Agent: Fsi C/o Jackson Walker, LLP
20090035916 - Method for manufacturing semiconductor device having fin gate: When manufacturing a semiconductor device, an isolation layer is formed on a semiconductor substrate to define an active region that includes gate forming area. Portions of the isolation layer that are adjacent to the gate forming area of the active region are etching by a dry cleaning process which utilizes... Agent: Ladas & Parry LLP
20090035915 - Method of high density plasma gap-filling with minimization of gas phase nucleation: A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectric material in the trench. Then, an etch... Agent: J C Patents, Inc.
20090035917 - Method for forming device isolation structure of semiconductor device using annealing steps to anneal flowable insulation layer: A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of... Agent: Ladas & Parry LLP
20090035918 - Post deposition plasma treatment to increase tensile stress of hdp-cvd sio2: Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate.... Agent: Townsend And Townsend And Crew LLP
20090035919 - In-place bonding of microstructures: A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the... Agent: Scully, Scott, Murphy & Presser, P.C.
20090035920 - Process for fabricating a substrate of the silicon-on-insulator type with reduced roughness and uniform thickness: A process for fabricating a silicon on insulator (SOI) substrate by co-implanting atomic or ionic species into a semiconductor donor substrate to form a weakened zone therein, the weakened zone forming a boundary between a thin silicon active layer and the remainder of the donor substrate. The donor substrate is... Agent: Winston & Strawn LLP Patent Department
20090035921 - Formation of lattice-tuning semiconductor substrates: A method of forming a lattice-tuning semiconductor substrate comprises defining a selected area (12) of a Si surface (15) by means of a window (13) extending through an isolating layer (11) on the Si surface (15); defining in the isolating layer (11) a depression (14) separated from the Si surface... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP
20090035923 - Method for manufacturing a semiconductor device: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.... Agent: Eric Robinson
20090035922 - Semiconductor device and manufacturing method thereof: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as... Agent: Fish & Richardson P.C.
20090035924 - Method of forming a semiconductor structure comprising an implantation of ions of a non-doping element: A method of forming a semiconductor structure includes providing a substrate having a first feature and a second feature. A mask is formed over the substrate. The mask covers the first feature. An ion implantation process is performed to introduce ions of a non-doping element into the second feature. The... Agent: Williams, Morgan & Amerson
20090035925 - Gallium nitride semiconductor device: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of... Agent: Patent Docket Administrator Lowenstein Sandler PC
20090035926 - Methods of fabricating silicon carbide devices incorporating multiple floating guard ring edge terminations: Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface... Agent: Myers Bigel Sibley & Sajovec, P.A.
20090035927 - Method of forming dielectric layers on a substrate and apparatus therefor: Methods of forming dielectric layers on a substrate comprising silicon and oxygen are disclosed herein. In some embodiments, a method of forming a dielectric layer on a substrate includes provide a substrate having an exposed silicon oxide layer; treating an upper surface of the silicon oxide layer with a plasma;... Agent: MoserIPLaw Group / Applied Materials, Inc.
20090035928 - Method of processing a high-k dielectric for cet scaling: A method of making a semiconductor device includes making a gate dielectric with an overlying gate electrode. The semiconductor device is made over a semiconductor layer. A high-k dielectric comprising hafnium zirconate is deposited over the semiconductor layer. The high-k dielectric is annealed at a temperature between 650 degrees Celsius... Agent: Freescale Semiconductor, Inc. Law Department
20090035929 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes: (a) forming an insulating layer having a contact hole on a semiconductor section in which an element is formed; (b) forming an electrode pad on the insulating layer so that a depression or a protrusion remains at a position at which the... Agent: Oliff & Berridge, PLC
20090035933 - Dendrite growth control circuit: A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is... Agent: Greenblum & Bernstein, P.L.C
20090035931 - Method for forming vias in a substrate: The present invention relates to a method for forming vias in a substrate, comprising the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a photo resist layer on the first surface of the substrate; (c) forming a pattern on the photo resist... Agent: Volentine & Whitt PLLC
20090035932 - Method for forming vias in a substrate: The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate... Agent: Volentine & Whitt PLLC
20090035930 - Method of forming a wire structure: In a method of forming a wire structure, first active regions and second active regions are formed on a substrate. Each of the first active regions has a first sidewall of a positive slope and a second sidewall opposed to the first sidewall. The second active regions are arranged along... Agent: Stanzione & Kim, LLP
20090035934 - Self-aligned cross-point memory fabrication: Fabricating a cross-point memory structure using two lithography steps with a top conductor and connector or memory element and a bottom conductor orthogonal to the top connector. A first lithography step followed by a series of depositions and etching steps patterns a first channel having a bottom conductor. A second... Agent: Molecular Imprints
20090035935 - Method of forming a metal wiring: A method of forming a metal wiring for a semiconductor device includes forming a metal-based layer on a substrate, the substrate including at least one conductive structure, forming a metal seed layer on the metal-based layer, forming a supplementary contact layer on the metal seed layer along peripheral portions of... Agent: Lee & Morse, P.C.
20090035936 - Semiconductor device having a grain orientation layer: A manufacturing process of a semiconductor device includes generating a less random grain orientation distribution in metal features of a semiconductor device by employing a grain orientation layer. The less random grain orientation, e.g., a grain orientation distribution which has a higher percentage of grains that have a predetermined grain... Agent: Williams, Morgan & Amerson
20090035937 - In-situ deposition for cu hillock suppression: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than... Agent: Slater & Matsil, L.L.P.
20090035938 - Methods of forming cosi2, methods of forming field effect transistors, and methods of forming conductive contacts: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt.... Agent: Wells St. John P.s.
20090035939 - Fabrication method to minimize ballast layer defects: A method for minimizing fabrication defects in ballast contact to a conductor in monolithically integrated semiconductor devices includes forming a sloping sidewall (318, 424) in both an insulating layer (106, 718) overlying a conductive layer (104, 714) by etching with a an RF biased fluorine based chemistry and an RF... Agent: Ingrassia Fisher & Lorenz, P.C. (mot)
20090035940 - Copper metallization of through silicon via: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ions, an organic sulfonic acid or inorganic acid, or one or more organic compounds selected... Agent: Senniger Powers LLP
20090035941 - Methods and apparatus for manufacturing a semiconductor device in a processing chamber: An apparatus for manufacturing a semiconductor device includes a process chamber configured to perform a plurality of different processes on a substrate. A gas supply unit is configured to supply at least one process gas to the process chamber. At least one upper electrode unit is positioned at an upper... Agent: Myers Bigel Sibley & Sajovec
20090035942 - Ruthenium cmp compositions and methods: The present invention provides a chemical-mechanical polishing (CMP) composition for polishing a ruthenium-containing substrate in the presence of an oxidizing agent such as hydrogen peroxide without forming a toxic level of ruthenium tetroxide during the polishing process. The composition comprises a particulate abrasive (e.g., silica, alumina, and/or titania) suspended in... Agent: Steven Weseman Associate General Counsel, I.p.
20090035943 - Method of fabricating for semiconductor device fabrication: A method of fabricating a semiconductor device, includes providing a substrate having at least one first portion and at least one second portion. The first portion includes a semiconductor material and the second portion includes an electrically isolating material. An etching step is performed using an etchant in order to... Agent: Slater & Matsil, L.L.P.
20090035944 - Methods of for forming ultra thin structures on a substrate: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond.... Agent: Patterson & Sheridan, LLP - - Appm/tx
20090035945 - Manufacturing method of semiconductor integrated circuit device: In remote plasma cleaning, it is difficult to locally excite a plasma because the condition is not suitable for plasma excitation different from that at the time of film formation and a method using light has a problem of fogginess of a detection window that cannot be avoided in a... Agent: Miles & Stockbridge PC
20090035946 - In situ deposition of different metal-containing films using cyclopentadienyl metal precursors: A method is disclosed depositing multiple layers of different materials in a sequential process within a deposition chamber. A substrate is provided in a deposition chamber. A plurality of cycles of a first atomic layer deposition (ALD) process is sequentially conducted to deposit a layer of a first material on... Agent: Knobbe Martens Olson & Bear LLP
20090035947 - Manufacturing method of semiconductor device, and substrate processing apparatus: The method comprises the steps of loading a substrate into a processing chamber; forming a thin film having a desired thickness on the substrate by setting as one cycle the step of supplying into the processing chamber adsorption auxiliary gas for aiding an adsorption of a source gas vaporized from... Agent: Oliff & Berridge, PLC
20090035948 - Substrate processing apparatus, heating apparatus for use in the same, method of manufacturing semiconductors with those apparatuses, and heating element supporting structure: A substrate treating device comprising a treatment chamber for storing and treating substrates and a heating device having a heating element and a heat insulator and heating the substrates in the treatment chamber by the heating element. The heating element is so formed that only its one end is held... Agent: Rader Fishman & Grauer PLLCPrevious industry: Chemistry: analytical and immunological testing
Next industry: Electrical connectors
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