Semiconductor device manufacturing: process inventions 01/09

20090029485 - Manufacturing method of semiconductor device: A capacitor in which a ferroelectric film (4) is held between a lower electrode (3) and an upper electrode (5) is formed above a conductive plug (1), with a conductive base structure (2) interposed therebetween. A hard mask (6) used in patterning the conductive base structure (2) is formed over... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090029487 - Semiconductor production method and semiconductor production device: The objective of the present invention is to prevent the variation in an ashing rate according to a temporal change within an ashing chamber. Then, in order to maintain the ashing rate, the decrease in the number of oxygen atoms in ashing gas within a process chamber 101 is indirectly... Agent: Mcdermott Will & Emery LLP

20090029488 - Soldering method for mounting semiconductor device on wiring board to ensure invariable gap therebetween, and soldering apparatus therefor: In a soldering method for mounting a semiconductor device on a wiring board, a plurality of solid-phase solders are provided between the semiconductor device and the wiring board, and are thermally melted to thereby produce a plurality of liquid-phase solders therebetween. A constant force is exerted on the liquid-phase solders... Agent: Mcginn Intellectual Property Law Group, Pllc

20090029486 - Substrate processing apparatus and substrate processing method: A substrate processing apparatus has: a process chamber in which a substrate is processed; a heating device that optically heats the substrate accommodated in the process chamber from an outer periphery side of the substrate; a cooling device that cools the outer periphery side of the substrate by flowing a... Agent: Oliff & Berridge, Plc

20090029489 - Endpoint detection device for realizing real-time control of plasma reactor, plasma reactor with endpoint detection device, and endpoint detection method: An endpoint detection device, a plasma reactor with the endpoint detection device, and an endpoint detection method are provided. The endpoint detection device includes an OES data operation unit, a data selector, a product generator, an SVM, and an endpoint determiner. The OES data operation unit processes reference OES data... Agent: Volpe And Koenig, P.c.

20090029490 - Method of fabricating an electronic device: It has been found that for silicon integrated circuits having capacitor structures or other p-n junctions structure at a technology node of 32 nm or smaller, photovoltaic induced corrosion of copper in the metallization stack is a significant issue. Thus processing conditions or device configurations are employed that preclude such... Agent: Bruce S. Schneider

20090029491 - Method of inspecting defect of semiconductor device: A method of inspecting defects in a semiconductor device includes forming a test pattern in a scribe lane region of a semiconductor substrate. The test pattern includes a second conductive layer formed on an isolation layer of the semiconductor substrate. Further, the method includes measuring a current flowing between the... Agent: Lowe Hauptman Ham & Berner, LLP

20090029492 - Method of making light emitting diode: A method of making a light emitting diode (LED) is disclosed. The LED of the present invention comprises a semiconductor layer of a first polarity, an active layer, and a semiconductor layer of a second polarity stacked from bottom to up, wherein a stacked structure at least composed of the... Agent: Kinney & Lange, P.a.

20090029493 - Methods of forming light emitting devices with active layers that extend into opened pits: Light emitting devices include an active region comprising a plurality of layers and a pit opening region on which the active region is disposed. The pit opening region is configured to expand a size of openings of a plurality of pits to a size sufficient for the plurality of layers... Agent: Myers Bigel Sibley & Sajovec, P.a.

20090029494 - Package structure for solid-state lighting devices and method of fabricating the same: Silicon substrates are applied to the package structure of solid-state lighting devices. Wet etching is performed to both top and bottom surfaces of the silicon substrate to form reflecting cavity and electrode access holes. Materials of the reflecting layer and electrode can be different from each other whose preferred materials... Agent: Oliff & Berridge, Plc

20090029495 - Fabrication method of gan power leds with electrodes formed by composite optical coatings: Fabrication method of GaN power LED with electrodes formed by composite optical coatings, comprising epitaxially growing N—GaN, active, and P—GaN layers successively on a substrate; depositing a mask layer thereon; coating the mask layer with photoresist; etching the mask layer into an N—GaN electrode pattern; etching through that electrode pattern... Agent: J. Michael Martinez De Andino, Esq. Hunton & Williams LLP

20090029496 - Radiation-emitting semiconductor body for a vertically emitting laser and method for producing same: The present invention concerns a radiation-emitting semiconductor body with a vertical emission direction, a radiation-generating active layer, and a current-conducting layer having a current-blocking region and a current-permeable region, the semiconductor body being provided for a vertically emitting laser with an external resonator, and the external resonator having a defined... Agent: Fish & Richardson Pc

20090029497 - Semiconductor light-emitting device and method of fabricating the same: The invention provides a semiconductor light-emitting device with II-V group (or II-IV-V group) compound contact layer and a method of fabricating the same. The semiconductor light-emitting device according to a preferred embodiment of the invention includes a substrate, a first conductive type semiconductor material layer, a light-emitting layer, a first... Agent: Birch Stewart Kolasch & Birch

20090029498 - Manufacturing method of display device: To improve a deposition rate of a microcrystalline semiconductor layer by using a deposition method and to improve productivity of a display device including a TFT of a microcrystalline semiconductor, a reactive gas containing helium is supplied to a treatment chamber surrounded with a plurality of juxtaposed waveguides and a... Agent: Eric Robinson

20090029499 - Method for manufacturing nitride semiconductor light emitting element: Provided is a method for manufacturing a nitride semiconductor light emitting element. In the method, when an isolation trench for chip isolation and for laser lift-off is formed, a degradation-free nitride semiconductor light emitting element with high luminance can be formed without doing any damages to a light emitting region.... Agent: Rabin & Berdo, Pc

20090029500 - Hermetic pacakging and method of manufacture and use therefore: An embodiment of the present invention provides a method of manufacturing hermetic packaging for devices on a substrate wafer, comprising forming a plurality of adhesive rings on a cap wafer or the substrate wafer, bonding the cap wafer to the substrate wafer with an adhesive layer, forming trenches in the... Agent: Chang-feng Wan

20090029501 - Process of forming a microphone using support member: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate... Agent: Bromberg & Sunstein LLP

20090029502 - Apparatuses and methods of substrate temperature control during thin film solar manufacturing: Embodiments of the invention generally provide apparatuses and methods of substrate temperature control during thin film solar manufacturing. In one embodiment a method for forming a thin film solar cell over a substrate is provided. The method comprises performing a temperature stabilization process on a substrate to pre-heat the substrate... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090029503 - Method for manufacturing photoelectric conversion device: To form a microcrystalline semiconductor with high quality which can be directly formed at equal to or less than 500° C. over a large substrate with high productivity without decreasing a deposition rate. In addition, to provide a photoelectric conversion device which employs the microcrystalline semiconductor as a photoelectric conversion... Agent: Eric Robinson

20090029504 - Wafer-level aca flip chip package using double-layered aca/nca: A method of manufacturing a wafer-level flip chip package is capable of being used to produce a flip chip package by directly coating a flip chip package using anisotropic conductive adhesives (ACA) and non conductive adhesives (NCA) in a solution state as a double layer on a wafer. The method... Agent: The Rafferty Patent Law Firm

20090029505 - Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically... Agent: Harness, Dickey & Pierce, P.L.C

20090029506 - Method of manufacturing semiconductor device: In a method of manufacturing a semiconductor device 10 including a wiring board 11 having a ground terminal 38, a semiconductor chip 12 and passive components 14 and 15 which are electronic components mounted on the wiring board 11, and a sealing resin 19 containing a silica filler for sealing... Agent: Drinker Biddle & Reath (dc)

20090029507 - Dielectric film, its formation method, semiconductor device using the dielectric film and its production method: A high-quality dielectric film is formed by generating plasma of a high electron density by a method such as diluting a rare gas or raising a frequency of a power supplier, and generating oxygen atoms or nitrogen atoms of a high density. The dielectric film contains silicon oxide in which... Agent: Graybeal Jackson LLP

20090029508 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device and a display device each including a thin film transistor which has excellent electric characteristics and high reliability, with high mass productivity. In a display device which includes a channel-etch inversely-staggered thin film transistor in which a microcrystalline semiconductor layer is used for... Agent: Eric Robinson

20090029509 - Substrate processing apparatus and method and a manufacturing method of a thin film semiconductor device: A substrate processing apparatus includes a plurality of evacuable treatment chambers connected to one another via an evacuable common chamber, and the common chamber is provided with means for transporting a substrate between each treatment chamber. More specifically, a substrate processing apparatus includes a plurality of evacuable treatment chambers, at... Agent: Eric Robinson

20090029510 - Multiple doping level bipolar junctions transistors and method for forming: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for... Agent: Hitt Gaines, Pc Lsi Corporation

20090029511 - Nor-type channel-program channel-erase contactless flash memory on soi: A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The... Agent: Koucheng Wu 20f.-2, No.8

20090029512 - Semiconductor memory having charge trapping memory cells and fabrication method thereof: A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a... Agent: Dicke, Billig & Czaja

20090029513 - Vertical quadruple conduction channel insulated gate transistor: A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest... Agent: Stmicroelectronics, Inc.

20090029514 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive... Agent: Nixon Peabody, LLP

20090029515 - Methods for the formation of fully silicided metal gates: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided.... Agent: Scully, Scott, Murphy & Presser, P.c.

20090029516 - Method to improve transistor tox using high-angle implants with no additional masks: A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into... Agent: Texas Instruments Incorporated

20090029517 - Method of making a semiconductor device: A method of making a semiconductor device, comprising: forming a first material and a second material; forming a first oxide on the first material and a second oxide on the second material; and etching second material so as to remove at least a portion of the second material.... Agent: Infineon Technologies Ag Patent Department

20090029518 - method of fabricating schottky barrier diode: Disclosed is a method of fabricating a Schottky barrier diode, which comprises the steps of laminating an N− type epitaxial layer having a thickness of 2 to 4 μm, on an N+ type substrate layer, to form a semiconductor substrate; forming a P+ type guard ring at a given position... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090029519 - Method of manufacturing mim capacitor: Embodiments relate to a method of manufacturing an MIM capacitor, which is capable of obtaining a desired capacitance by controlling a k value of insulator thin film formed between bottom and top electrodes by adjusting a plasma doping condition. An MIM capacitor may be manufactured by forming a bottom electrode... Agent: Sherr & Vaughn, Pllc

20090029521 - Method of forming isolation structure of semiconductor device for preventing excessive loss during recess gate formation: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch... Agent: Ladas & Parry LLP

20090029520 - Methods of forming semiconductor device: A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first... Agent: Stanzione & Kim, LLP

20090029523 - Method of fabricating flash memory device: The invention relates to a method of fabricating flash memory device. In accordance with an aspect of the invention, the method includes forming a gate insulating layer, a first conductive layer, and an isolation mask over a semiconductor substrate. The isolation mask is patterned to expose regions in which an... Agent: Marshall, Gerstein & Borun LLP

20090029522 - Method of forming isolation layer of semiconductor device: A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first... Agent: Marshall, Gerstein & Borun LLP

20090029524 - Method of manufacturing a semiconductor integrated circuit device having a trench: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090029525 - Manufacturing method of soi substrate: A manufacturing method of an SOI substrate with high throughput. A semiconductor layer separated from a semiconductor substrate is transferred to a supporting substrate, thereby manufacturing an SOI substrate. First, the semiconductor substrate serving as a base of the semiconductor layer is prepared. An embrittlement layer is formed in a... Agent: Fish & Richardson P.c.

20090029526 - Method of exposing circuit lateral interconnect contacts by wafer saw: A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the... Agent: Miller Ip Group, Plc Northrop Grumman Corporation

20090029527 - Processes for forming backplanes for electro-optic displays: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second... Agent: David J Cole E Ink Corporation

20090029528 - Method and apparatus for cleaning a substrate surface: The present invention generally provides apparatus and method for forming a clean and damage free surface on a semiconductor substrate. One embodiment of the present invention provides a system that contains a cleaning chamber that is adapted to expose a surface of substrate to a plasma cleaning process prior to... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090029531 - Hybrid orientation substrate and method for fabrication thereof: A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor... Agent: Scully, Scott, Murphy & Presser, P.c.

20090029529 - Method for cleaning semiconductor device: Disclosed is a method for cleaning a semiconductor device to remove native oxides or by-products created in the process of forming silicon germanium layers. The use of the method enables removal of native oxides or by-products created in the process of forming silicon germanium layers using hydrogen bromide and prevents... Agent: Sherr & Vaughn, Pllc

20090029530 - Method of manufacturing thin film semiconductor device: Disclosed herein is a method of manufacturing a thin film semiconductor device includes the step of forming a silicon thin film including a crystalline structure on a substrate by a plasma CVD process in which a high order silane gas represented by the formula SinH2n+2 (n=2, 3, . . .... Agent: Rader Fishman & Grauer Pllc

20090029532 - Method for forming a microcrystalline silicon film: This invention provides a method for forming a microcrystalline silicon film, which employs a three-stage deposition process to form a microcrystalline film. A microcrystalline silicon seed layer is formed on a substrate. Gaseous ions are used to bombard a surface of the microcrystalline silicon seed layer. Microcrystalline silicon is formed... Agent: Birch Stewart Kolasch & Birch

20090029533 - Method of controlling film stress in mems devices: A structural film, typically of silicon, in MEMS or NEMS devices is fabricated by depositing the film in the presence of a gas other than nitrogen, and preferably argon as the carrier gas.... Agent: Marks & Clerk

20090029534 - Liquid phase deposition of contacts in programmable resistance and switching devices: A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom composite electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer and the bottom composite electrode, and a... Agent: Energy Conversion Devices, Inc.

20090029535 - Ion implantation method and semiconductor device manufacturing method: In the ion implantation method and semiconductor device manufacturing method relating to the present invention, a disc on which multiple semiconductor substrates are mounted is positioned in the manner that a first angle β1 is made between an X-Y plane perpendicular to an ion beam and a line perpendicular to... Agent: Mcdermott Will & Emery LLP

20090029536 - Bipolar transistors with vertical structures: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a... Agent: Alcatel-lucent Docket Administrator - Room 2f-192

20090029537 - Method for forming semiconductor package and mold cast used for the same: A method for fabricating a thermally enhanced semiconductor package including the steps of providing a substrate having a first surface and a second surface; providing a die on the first surface of the substrate and electrically connecting the die with the substrate; placing the die, the substrate, and a heat... Agent: Joe Mckinney Muncy

20090029539 - Method for fabricating tungsten line and method for fabricating gate of semiconductor device using the same: A method for fabricating a tungsten (W) line includes forming a silicon-containing layer, forming a diffusion barrier layer over the silicon-containing layer, forming a tungsten layer over the diffusion barrier layer, and performing a thermal treatment process on the tungsten layer to increase a grain size of the tungsten layer.... Agent: Townsend And Townsend And Crew, LLP

20090029538 - Process for making a semiconductor device using partial etching: A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so... Agent: Freescale Semiconductor, Inc. Law Department

20090029540 - Nonvolatile semiconductor memory and manufacturing method thereof: A method for manufacturing a nonvolatile semiconductor memory device including: forming a first and a second stacked gate structures, each of which including a first polysilicon layer formed on a silicon substrate via a gate insulator, an inter-gate insulator formed on the first polysilicon layer, a second polysilicon layer formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090029541 - Method of fabricating anti-fuse and method of programming anti-fuse: A method of fabricating an anti-fuse includes firstly forming a dielectric layer on a substrate having a first conductive type. Next, a conductive layer is formed on the dielectric layer. A first ion implantation process is then performed, such that the conductive layer has the first conductive type. Thereafter, the... Agent: J C Patents, Inc.

20090029542 - Methods and systems for laser assisted wirebonding: The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for wirebonding by removing impurities such as residues from manufacturing processes, oxides, or irregularities on the bonding surface. Subsequently, a free air ball is brought into contact... Agent: Texas Instruments Incorporated

20090029543 - Cleaning process for microelectronic dielectric and metal structures: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant... Agent: Scully, Scott, Murphy & Presser, P.c.

20090029544 - Adhesion and minimizing oxidation on electroless co alloy films for integration with low k inter-metal dielectric and etch stop: A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090029546 - Method for forming metal lines of semiconductor device: Methods are disclosed for forming metal lines of a semiconductor device that can reduce interconnection or contact resistance, and can reduce defects in a barrier metal layer having a column structure. The method can include forming a first metal line on a semiconductor substrate, forming an insulating film on the... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090029545 - Method of manufacturing semiconductor device: The present invention provides a method of manufacturing a semiconductor device which method enables a reduction in via resistance. The method of manufacturing the semiconductor device includes the steps of removing a barrier metal film from a bottom surface of a via, with the barrier metal film remaining on a... Agent: Steptoe & Johnson LLP

20090029548 - Method for removing polymer residue from metal lines of semiconductor device: It is possible to substantially remove a polymer residue from metal lines formed over a semiconductor device without damage to the metal lines. The disclosed method includes forming a metal layer over a lower layer. A photoresist film is formed over the metal layer, and then patterned. The metal layer... Agent: Sherr & Vaughn, Pllc

20090029547 - Novel ladder poly etching back process for word line poly planarization: A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then... Agent: Duane Morris LLP (tsmc) Ip Department

20090029549 - Method of silicide formation for nano structures: A method forms a first layer over a second layer that comprises silicon. A mask is formed and patterned over the insulator layer. Then, a heavy inert gas such as Xenon (Xe) is implanted through the openings in the mask, through the insulator layer, and into the regions of the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, Llc

20090029550 - Method of manufacturing nitride substrate for semiconductors: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±40 μm to ±100 μm. Since with that bow device... Agent: Judge Patent Associates

20090029551 - Pad and method for chemical mechanical polishing: A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed... Agent: Bacon & Thomas, Pllc

20090029553 - Free radical-forming activator attached to solid and used to enhance cmp formulations: The present invention provides a composition for chemical-mechanical polishing which comprises at least one abrasive particle having a surface at least partially coated by a activator. The activator comprises a metal other than a metal of Group 4(b), Group 5(b) or Group 6(b). The composition further comprises at least one... Agent: Morgan Lewis & Bockius LLP

20090029552 - Method for polishing a substrate composed of semiconductor material: Semiconductor material substrates are polished by a method including at least one polishing step A by means of which the substrate is polished on a polishing pad containing an abrasive material bonded in the polishing pad and a polishing agent solution is introduced between the substrate and the polishing pad... Agent: Brooks Kushman P.c.

20090029556 - Method for forming a shallow trench isolation: A method for forming a shallow trench isolation includes providing a substrate with a trench, a first liner layer and a second liner layer sequentially in the trench with a first oxide filling the trench, performing a first wet etching to remove part of the first oxide and part of... Agent: North America Intellectual Property Corporation

20090029554 - Method of batch integration of low dielectric substrates with mmics: A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the... Agent: Miller Ip Group, Plc Northrop Grumman Corporation

20090029555 - Multi-step selective etching for cross-point memory: Multi-step selective etching. Etching an unmasked region associated with each layer of a plurality of layers, the plurality of layers comprising a stack, wherein the unmasked region of each of the plurality of layers is etched while exposed to a temperature, a pressure, a vacuum, using a plurality of etchants,... Agent: Unity Semiconductor Corporation

20090029557 - Plasma etching method, plasma etching apparatus and storage medium: A plasma etching method plasma-etches an etching target film by using a photoresist film as a mask. The plasma etching method includes loading a target object to be processed into a processing chamber where an upper and a lower electrode are provided to face each other, the target object having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090029558 - Method of manufacturing semiconductor device: The present invention relates to a method of manufacturing a semiconductor device using a substrate including an organic low dielectric constant film containing a silicon, a carbon, an oxygen, and a hydrogen, with a resist pattern being formed on an upper layer side of the low dielectric constant film. The... Agent: Smith, Gambrell & Russell

20090029559 - Photo mask of semiconductor device and method of forming pattern using the same: There is provided a photo mask for forming a specific pattern and a specific pattern formed using the photo mask. Unlike in a related method of forming a specific pattern using a photo mask including cell lines and pad lines, the photo mask is manufactured with cell lines and pad... Agent: Sherr & Vaughn, Pllc

20090029560 - Apparatus and method for single substrate processing: In a method for treating a semiconductor substrate, a single substrate is positioned in a single-substrate process chamber and subjected to wet etching, cleaning and/or drying steps. The single substrate may be exposed to etch or clean chemistry in the single-substrate processing chamber as turbulence is induced in the etch... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090029561 - Semiconductor processing apparatus: There is provided a semiconductor processing apparatus comprising a processing tube for housing a substrate support member that supports a plurality of substrates stacked at a prescribed pitch in a vertical direction; a gas supply part that extends in a direction in which the substrates are stacked in the processing... Agent: Oliff & Berridge, Plc

20090029562 - Film formation method and apparatus for semiconductor process: A film formation method for a semiconductor process includes placing a plurality of target objects at intervals in a vertical direction inside a process container of a film formation apparatus. Then, the method includes setting the process container to have a first vacuum state therein, and supplying a first film... Agent: Smith, Gambrell & Russell

20090029563 - Method and apparatus for manufacturing semiconductor nanoparticles: A method for producing semiconductor nanoparticles, wherein a reaction for forming nuclei of the semiconductor nanoparticles and a reaction for growing the nuclei of the semiconductor nanoparticles are performed in a stepwise manner. An apparatus for producing semiconductor nanoparticles includes a continuous reaction apparatus for performing a reaction for forming... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090029564 - Plasma treatment apparatus and plasma treatment method: In a plasma oxidation treatment apparatus 100, dual plate structure 60 is arranged above a susceptor 2. An upper plate 61 and a lower plate 62 are made of a dielectric material such as quartz, separately arranged in parallel at a prescribed interval, for instance an interval of 5 mm,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20090023229 - Method for managing uv irradiation for curing semiconductor substrate: A method for managing UV irradiation for curing a semiconductor substrate, includes: passing UV light through a transmission glass window provided in a chamber for curing a semiconductor substrate placed in the chamber; monitoring an illuminance upstream of the transmission glass window and an illuminance downstream of the transmission glass... Agent: Knobbe Martens Olson & Bear LLP

20090023230 - Methods and apparatus for depositing an anti-reflection coating: Systems, methods, and apparatus are provided for depositing an anti-reflection film on a substrate. A substrate is transported to a metrology tool. A characteristic of the substrate is measured, via the metrology tool. A recipe for an anti-reflection film is determined, based on the measured characteristic. The substrate is transported... Agent: Dugan & Dugan, Pc

20090023231 - Semiconductor device manufacturing method and method for reducing microroughness of semiconductor surface: Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor... Agent: Foley And Lardner LLP Suite 500

20090023232 - Organic electroluminescence element, process for preparation of the same, and electrode film: An organic electroluminescence element has a layered structure on a surface of a transparent substrate. The layered structure comprises an organic material layer including a light-emitting organic material layer, an opaque electrode layer, an insulating layer, a metal layer and a resin film in order. The organic electroluminescence element is... Agent: Nixon Peabody, LLP

20090023233 - Method of manufacturing dispersion type ac inorganic electroluminescent device and dispersion type ac inorganic electroluminescent device manufactured thereby: Disclosed herein is a method of preparing a low resistance metal line, is a method of manufacturing a dispersion type AC inorganic electroluminescent device and a dispersion type AC inorganic electroluminescent device manufactured thereby, in which a light-emitting layer and a dielectric layer between a lower electrode and an upper... Agent: Cantor Colburn, LLP

20090023234 - Method for manufacturing light emitting diode package: A method for manufacturing light emitting diode (LED) package first fabricates a silicon submount with at least one groove by wet etching, wherein a reflective layer, a transparent insulation layer and a metal bump are successively formed in the silicon submount. An LED die is mounted in the groove of... Agent: Hdsl

20090023235 - Method and apparatus for improved printed cathodes for light-emitting devices: Rapid thermal processing of printed cathodes for light-emitting polymer devices (LEPDs) to prevent detrimental cathode ink/LEP layer interactions is described herein. The ink layer printed cathode can be thinned curing fabrication using high mesh count screens, calendered mesh screens, high squeegee pressures, high hardness squeegees, high squeegee angles and combinations... Agent: Pillsbury Winthrop Shaw Pittman LLP

20090023236 - Method for manufacturing display device: A method for manufacturing display devices including thin film transistors with high reliability in a high yield is provided. A gate insulating film is formed over a gate electrode; a microcrystalline semiconductor is formed over the gate insulating film; the microcrystalline semiconductor film is irradiated with a laser beam from... Agent: Eric Robinson

20090023237 - Integrated optical isolator: There is provided an integrated optical isolator has a structure obtained by integrating a semiconductor laser and an optical isolator, simple manufacturing steps, efficiently absorbs a backward propagation light of the optical isolator, and prevents a stray light from being generated. In an integrated optical isolator in which a semiconductor... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20090023238 - Method to form an optical grating and to form a distributed feedback laser diode with the optical grating: A method for forming a grating with an adjustable pitch and a method for forming a DFB-LD with an optical grating whose pitch is adjustable during the process are disclosed. The method of the invention; first prepares a mold with a pattern to form the grating; second, pushes the mold... Agent: Smith, Gambrell & Russell

20090023239 - Light emitting device processes: Light-emitting devices, and related components, processes, systems and methods are disclosed.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.c.

20090023240 - Semiconductor laser device and manufacturing method of the same: This semiconductor laser device (100) includes the laminated structure of an n-AlInP clad layer (103), a superlattice active layer section (104), a p-AlInP first clad layer (105), a GaInP etching stop layer (106) are formed, and on top of that, there are a p-AlInP second clad layer (107), a GaInP... Agent: Rader Fishman & Grauer Pllc

20090023241 - Clean rate improvement by pressure controlled remote plasma source: The present invention generally comprises a method for cleaning a large area substrate processing chamber. As chamber volume increases, it has surprisingly been found that simply scaling up the cleaning conditions may not effectively clean silicon from the exposed chamber surfaces. Undesired silicon deposits on exposed chamber surfaces may lead... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090023242 - Vacuum jacket for phase change memory element: A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090023244 - Etching/bonding chamber for encapsulated devices and method of use: A method for activating a getter at low temperature for encapsulation in a device cavity containing a microdevice comprises etching a passivation layer off the getter material while the device wafer and lid wafer are enclosed in a bonding chamber. A plasma etching process may be used, wherein by applying... Agent: Jaquelin K. Spong

20090023243 - Method and apparatus for fabricating integrated circuit device using self-organizing function: In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor... Agent: Griffin & Szipl, Pc

20090023246 - Embedded chip package process: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer... Agent: Jianq Chyun Intellectual Property Office

20090023245 - Flip chip mounting method and bump forming method: The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing... Agent: Hamre, Schumann, Mueller & Larson P.c.

20090023247 - Method for forming side wirings: After plural semiconductor elements are stacked to form a stacked body P, side wirings are formed on the side surface of the stacked body P, thereby manufacturing a semiconductor apparatus in which the respective semiconductor elements are electrically connected to one another. In this case, as the semiconductor element, a... Agent: Drinker Biddle & Reath (dc)

20090023248 - Method of packaging a semiconductor die: A method of packaging a semiconductor die includes the steps of providing a flange (110), coupling one or more active die (341) to the flange with a lead-free die attach material (350), staking a leadframe (120) to the flange after coupling the one or more active die to the flange,... Agent: Bryan Cave LLP

20090023249 - Wire bonded wafer level cavity package: A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges... Agent: Tessera Lerner David Et Al.

20090023250 - Apparatus and method for producing semiconductor modules: An apparatus and method for producing semiconductor modules is disclosed. One embodiment provides for bonding at least one semiconductor die onto a carrier including a support film strip, the support film having applied an adhesive layer to one of its surfaces to attach the semiconductor die, and a pressure tool... Agent: Dicke, Billig & Czaja

20090023251 - Method for manufacturing semiconductor device: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is... Agent: Eric Robinson

20090023252 - Method of manufacturing semiconductor device having a heat sink with a bored portion: A heatsink plate is to be fixed to a substrate with sufficient strength, so as to prevent the heatsink plate from being stripped off, to thereby secure reliability on the performance of the semiconductor chip. The heatsink plate has both the upper and lower surfaces of the fixing section sandwiched... Agent: Young & Thompson

20090023253 - Semiconductor device and method of making same: A method for manufacturing a semiconductor device that includes a housing, formed of a polyamide-series thermoplastic resin, and a semiconductor package sealed in the housing, which is formed of a thermosetting epoxy resin. The surface of the package is modified by UV-irradiation to have adhesive properties to polyamide. A plurality... Agent: Carstens & Cahoon, LLP

20090023254 - Method of forming inorganic insulating layer and method of fabricating array substrate for display device using the same: A method of forming an inorganic insulating layer on a substrate comprises supplying a mixed gas between the substrate and a target, and generating a plasma between the substrate and the target. The target comprises a silicon-based material. The method further comprises depositing a plurality of ions from the plasma... Agent: Brinks Hofer Gilson & Lione

20090023255 - Method for reshaping silicon surfaces with shallow trench isolation: A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface... Agent: Slater & Matsil, L.l.p.

20090023256 - Method for fabricating embedded static random access memory: The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in... Agent: North America Intellectual Property Corporation

20090023257 - Method of controlling metal silicide formation: Methods of processing silicon substrates to form metal silicide layers thereover having more uniform thicknesses are provided herein. In some embodiments, a method of processing a substrate includes providing a substrate having a plurality of exposed regions comprising silicon, wherein at least two of the plurality of exposed regions have... Agent: Moser Ip Law Group / Applied Materials, Inc.

20090023258 - Method of manufacturing complementary metal oxide semiconductor transistors: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard... Agent: North America Intellectual Property Corporation

20090023259 - Method of producing non volatile memory device: A method of forming a floating gate structure is disclosed, and includes modifying the etch chemistry of a plasma treated reactive ion etch process using an inert atom to physically damage a dielectric region. The damaged dielectric region is subsequently etched using a wet etch process.... Agent: Slater & Matsil LLP

20090023261 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, includes the steps of forming a dummy gate insulating film and a dummy gate electrode, forming source and drain regions, forming a first insulating film, forming a second insulating film, removing the second insulating film, simultaneously removing the first insulating film and the... Agent: Sonnenschein Nath & Rosenthal LLP

20090023260 - Technique for forming the deep doped columns in superjunction: A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench... Agent: Panitch Schwarze Belisario & Nadel LLP

20090023262 - Method for fabricating semiconductor device: To provide a fine transistor of high precision. A method for fabricating a transistor comprises the step of forming a gate electrode (340) on the surface of a semiconductor substrate, the step of introducing an impurity across said gate electrode (340), and the step of activating said impurity, thereby to... Agent: Mcdermott Will & Emery LLP

20090023263 - Method to manufacture a thin film resistor: A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on... Agent: Texas Instruments Incorporated

20090023264 - Method of making planar-type bottom electrode for semiconductor device: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to... Agent: Muncy, Geissler, Olds & Lowe, Pllc

20090023265 - Etching solution for removal of oxide film, method for preparing the same, and method of fabricating semiconductor device: Provided are an anionic surfactant-containing etching solution for removal of an oxide film, preparation methods thereof, and methods of fabricating a semiconductor device using the etching solution. The etching solution includes a hydrofluoric acid (HF), deionized water, and an anionic surfactant. The anionic surfactant is a compound in which an... Agent: Frank Chau, Esq. F. Chau & Associates, Llc

20090023266 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device, includes forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a dummy pattern is provided above... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090023267 - Method of reducing roughness of a thick insulating layer: A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate, and then smoothing the exposed rough surface of the insulator layer by exposure to... Agent: Winston & Strawn LLP Patent Department

20090023268 - Isolation method of active area for semiconductor device: An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the... Agent: Muncy, Geissler, Olds & Lowe, Pllc

20090023271 - Glass-based soi structures: A method of forming a semiconductor on glass structure includes: establishing an exfoliation layer on a semiconductor wafer; contacting the exfoliation layer of the semiconductor wafer to a glass substrate; applying pressure, temperature and voltage to the semiconductor wafer and the glass substrate, without a vacuum atmosphere, such that a... Agent: Corning Incorporated

20090023270 - Method for manufacturing soi wafer: m

20090023269 - Method for producing soi wafer: Hydrogen gas is ion-implanted into a silicon wafer for active layer via an insulating film, and thus ion-implanted wafer is then bonded with a supporting wafer via an insulating film interposed therebetween. This bonded wafer is heated to 500° C., so that a part of the bonded wafer is cleaved... Agent: Greenblum & Bernstein, P.L.C

20090023272 - Method of producing bonded wafer: There is provided a method of producing a bonded wafer by bonding two silicon wafers for active layer and support layer to each other and then thinning the wafer for active layer, in which nitrogen ions are implanted from the surface of the wafer for active layer to form a... Agent: Sughrue Mion, Pllc

20090023273 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device comprising forming a transistor on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate to cover the transistor, forming a passivation film on the interlayer insulating film, and annealing the semiconductor substrate having the passivation film in a gas atmosphere... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090023274 - Hybrid chemical vapor deposition process combining hot-wire cvd and plasma-enhanced cvd: Hybrid chemical vapor deposition systems for depositing a semiconductor-containing thin film over a substrate comprise a reaction space, a substrate support member configured to permit movement of a substrate in a longitudinal direction and a plasma-generating apparatus disposed in the reaction space and configured to form plasma-excited species of a... Agent: Wilson Sonsini Goodrich & Rosati

20090023275 - Method for forming silicon wells of different crystallographic orientations: A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.c.

20090023276 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes forming an impurity diffusion layer in a surface of a semiconductor substrate, wherein the forming the impurity diffusion layer comprises irradiating material including M1x M2y (y/x≦1.2, where x is a ratio of M1, y is a ratio of M2, M1 is material... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090023277 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, the method includes forming an isolation layer defining an active region over a substrate, forming a conductive layer over the substrate including the isolation layer, patterning the conductive layer to form a conductive pattern over the active region defined on both sides of... Agent: Townsend And Townsend And Crew, LLP

20090023278 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device that may include forming a dielectric film pattern on a semiconductor substrate; etching the semiconductor substrate using the dielectric film pattern as a mask to form a trench; forming a first dielectric film on the semiconductor substrate including the trench; performing a... Agent: Sherr & Vaughn, Pllc

20090023280 - Method for forming high-k charge storage device: Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking... Agent: Horizon Ip Pte Ltd

20090023279 - Method of fabricating flash memory device: The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the... Agent: Marshall, Gerstein & Borun LLP

20090023281 - Solder bump forming method: A solder bump forming method of carrying out a reflow treatment over a conductive ball mounted on a plurality of pads, thereby forming a solder bump, includes a metal film forming step of forming a metal film capable of chemically reacting to a tackifying compound on the pads, an organic... Agent: Rankin, Hill & Clark LLP

20090023282 - Conductive ball mounting method and apparatus: There is provided a method of mounting conductive balls on pads on a substrate. The method includes: (a) placing the substrate having the pads coated with an adhesive over a container for containing the conductive balls therein and whose top surface is open such that the pads faces the top... Agent: Rankin, Hill & Clark LLP

20090023286 - Dielectric interconnect structures and methods for forming the same: Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In... Agent: Hoffman Warnick Llc

20090023284 - Integrated wafer processing system for integration of patternable dielectric materials: The present disclosure relates to an integrated wafer processing apparatus for fabricating semiconductor chips. This integrated wafer processing system combines the lithography patterning steps and irradiation curing steps of the patternable dielectric into one system. The patternable low-k material of the present disclosure also functions as a photoresist, i.e. is... Agent: Connolly Bove Lodge & Hutz LLP

20090023283 - Interconnection process: An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned... Agent: J C Patents, Inc.

20090023287 - Interconnection process: An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned... Agent: J C Patents, Inc.

20090023285 - Method of forming contact of semiconductor device: The present invention relates to a method of forming a contact of a semiconductor device. According to a method of forming a contact of a semiconductor device in accordance with an aspect of the present invention, first and second insulating layers are sequentially formed over a semiconductor substrate. A contact... Agent: Marshall, Gerstein & Borun LLP

20090023288 - Method of manufacturing nanoelectrode lines using nanoimprint lithography process: Provided are a method of manufacturing nanoelectrode lines. The method includes the steps of: sequentially forming an insulating layer, a first photoresist layer, and a drop-shaped second photoresist on a substrate; disposing an imprint mold having a plurality of molding patterns over the second photoresist; applying pressure to the mold... Agent: Rabin & Berdo, Pc

20090023289 - Conductor removal process: A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is... Agent: J C Patents, Inc.

20090023290 - Planarization method: A planarization method is provided. The method includes the steps of providing a substrate with a first region and a second region, and having a plurality of protrusions of different densities on a surface of said substrate; forming a first dielectric layer on the substrate to fill spaces between the... Agent: Birch Stewart Kolasch & Birch

20090023291 - Polishing methods: A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion of the abrasive material, and removing at least a majority portion of the flocculated portion from the substrate. Applying solid abrasive material can include applying a CMP slurry... Agent: Wells St. John P.s.

20090023292 - Photoelectric conversion device and method for producing photoelectric conversion device: A photoelectric conversion device according to the present invention has a plurality of photoreceiving portions provided in a substrate, an interlayer film overlying the photoreceiving portion, a large refractive index region which is provided so as to correspond to the photoreceiving portion and has a higher refractive index than the... Agent: Fitzpatrick Cella Harper & Scinto

20090023293 - Implementing state-of-the-art gate transistor, sidewall profile/angle control by tuning gate etch process recipe parameters: In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time... Agent: Texas Instruments Incorporated

20090023295 - Manufacturing method for semiconductor chips: By performing plasma etching on the second surface of a semiconductor wafer on the first surface of which an insulating film is placed in dividing regions and on the second surface of which a mask for defining the dividing regions are placed, the second surface being located opposite from the... Agent: Wenderoth, Lind & Ponack L.l.p.

20090023294 - Method for etching using advanced patterning film in capacitive coupling high frequency plasma dielectric etch chamber: A method for etching wafers using advanced patterning film (APF) to reduce bowing and improve bottom-to-top ratios includes providing a wafer having an APF layer into a processing chamber, wherein the processing chamber is configured with a power source operating at about 162 MHz, supplying a process gas into the... Agent: Townsend And Townsend And Crew LLP

20090023296 - Plasma etching method: This invention relates to a method for conducting an etching process which uses a plasma of a process gas. This etching process is conducted on a wafer W including a substrate 101, an underlying film 102, 103 formed on the substrate, and a film 104 to be etched that is... Agent: Smith, Gambrell & Russell

20090023297 - Method and apparatus for hmds treatment of substrate edges: A system for dispensing an adhesion promoting chemical includes a support plate configured to support a substrate and a dispense nozzle in fluid communication with a source of the adhesion promoting chemical, for example, HMDS. The dispense nozzle is positioned adjacent a peripheral portion of the substrate and at a... Agent: Townsend And Townsend And Crew, LLP

20090023298 - Inverse self-aligned spacer lithography: Ultrafine dimensions, smaller than conventional lithographic capabilities, are formed employing an efficient inverse spacer technique comprising selectively removing spacers. Embodiments include forming a first mask pattern over a target layer, forming a spacer layer on the upper and side surfaces of the first mask pattern leaving intermediate spaces, depositing a... Agent: Ditthavong Mori & Steiner, P.c.

20090023299 - Reduction of defects formed on the surface of a silicon oxynitride film: Methods for reducing defects on the surface of a silicon oxynitride film are disclosed. In one embodiment, the methods include forming a silicon oxynitride film on a semiconductor substrate and heating the silicon oxynitride film to increase a hydrophilicity of a surface of the silicon oxynitride film prior to treating... Agent: Spansion Llc C/o Murabito , Hao & Barnes LLP

20090023300 - Method of forming shadow layer on the wafer bevel: A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate... Agent: Jianq Chyun Intellectual Property Office

20090023301 - Film deposition apparatus, method of manufacturing a semiconductor device, and method of coating the film deposition apparatus: A method of manufacturing a semiconductor device has supplying a first reactant gas into buffer chamber provided in a reaction chamber of the film deposition apparatus to form a first film over an inner wall surface of the buffer chamber, and supplying a second reactant gas into the reaction chamber... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090023303 - Method of manufacturing a semiconductor integrated circuit device: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090023302 - Protective inserts to line holes in parts for semiconductor process equipment: Inserts are used to line openings in parts that form a semiconductor processing reactor. In some embodiments, the reactor parts delimit a reaction chamber. The reactor parts may be formed of graphite. A layer of silicon carbide is deposited on surfaces of the openings in the reactor parts and the... Agent: Knobbe Martens Olson & Bear LLP

20090017563 - Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics: A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the substrate including an etch-stop layer, a low-k dielectric layer, and a hardmask layer. The method further includes the steps of patterning a photoresist masking layer... Agent: Texas Instruments Incorporated

20090017564 - Method to detect and predict metal silicide defects in a microelectronic device during the manufacture of an integrated circuit: The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning (110) a portion of a semiconductor substrate in a field of view of an inspection tool. The method also comprises producing (120) a voltage contrast image of the portion, wherein the image... Agent: Texas Instruments Incorporated

20090017565 - Manufacturing method of semiconductor integrated circuit device: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt.... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20090017567 - Method for manufacturing semiconductor device: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is... Agent: Eric Robinson

20090017566 - Substrate removal during led formation: A light emitting diode (LED) is fabricated using an underfill layer that is deposited on either the LED or the submount prior to mounting the LED to a submount. The deposition of the underfill layer prior to mounting the LED to the submount provides for a more uniform and void... Agent: Patent Law Group LLP

20090017568 - Semiconductor device, electronic device and method for manufacturing semiconductor device: A semiconductor device of the present invention is manufactured by the following steps: forming a single-crystal semiconductor layer over a substrate having an insulating surface; irradiating a region of the single-crystal semiconductor layer with laser light; forming a circuit of a pixel portion using a region of the single-crystal semiconductor... Agent: Eric Robinson

20090017569 - Method for fabricating liquid crystal display device: A method for fabricating a liquid crystal display device is disclosed. The method includes forming a first conductive layer on an insulating substrate, forming a first insulating layer, a second conductive layer, and a third conductive layer on the first conductive layer, patterning the second conductive layer and the third... Agent: Birch Stewart Kolasch & Birch

20090017570 - Semiconductor laser device and method for fabricating the same: In a semiconductor laser device, a plurality of light-emitting elements emitting light with different wavelengths are integrated on a substrate. Each of the light-emitting elements includes, on the substrate, an active layer and cladding layers respectively provided on top and bottom of the active layer. One of the cladding layers... Agent: Mcdermott Will & Emery LLP

20090017571 - Sensing devices from molecular electronic devices: The present invention generally relates to the fabrication of molecular electronics devices from molecular wires and Single Wall Nanotubes (SWNT). In one embodiment, the cutting of a SWNT is achieved by opening a window of small width by lithography patterning of a protective layer on top of the SWNT, followed... Agent: Baker Botts L.L.P.

20090017572 - Nanoelectromechanical transistors and methods of forming same: Nanoelectromechanical transistors (NEMTs) and methods of forming the same are disclosed. In one embodiment, an NEMT may include a substrate including a gate, a source region and a drain region; an electromechanically deflectable nanotube member; and a channel member electrically insulatively coupled to the nanotube member so as to be... Agent: Hoffman Warnick LLC

20090017573 - Image sensor with improved dynamic range and method of formation: Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a... Agent: Dickstein Shapiro LLP

20090017574 - Thin film transistor, method of manufacturing the same, display apparatus having the same and method of manufacturing the display apparatus: A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and... Agent: Macpherson Kwok Chen & Heid LLP

20090017575 - Methods of forming openings: Some embodiments include methods of forming openings in which a metal-containing structure is formed over a region of a semiconductor substrate. A patterned metal-containing material is formed over the metal-containing structure, with the metal-containing material having a gap extending therethrough. An entirety of the metal-containing structure is removed through the... Agent: Wells St. John P.s.

20090017576 - Semiconductor processing methods: Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing... Agent: Wells St. John P.s.

20090017577 - Methods of forming phase change memory devices having bottom electrodes: Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis... Agent: Myers Bigel Sibley & Sajovec

20090017578 - Application of rfid labels: Disclosed is a method for producing an RFID label with the aid of a printing process. The aim of the invention is make it easy to apply the parts required onto the label while completing the label in a simple manner. Said aim is achieved by applying at least one... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20090017579 - Method of manufacturing micro electro mechanical systems device: Provided is a MEMS device which is robust to the misalignment and does not require the double-side wafer processing in the manufacture of a MEMS device such as an angular velocity sensor, an acceleration sensor, a combined sensor or a micromirror. After preparing a substrate having a space therein, holes... Agent: Miles & Stockbridge PC

20090017580 - Systems and methods for vertically integrating semiconductor devices: Systems and methods for vertically integrating semiconductor devices are described. In one embodiment, a method comprises providing an interposer, aligning and bonding a plurality of die to a first surface of the interposer, aligning and bonding a backplate to the plurality of die, and reducing at least one portion of... Agent: Fulbright & Jaworski L.L.P.

20090017581 - Method for manufacturing a semiconductor device: A single-crystal semiconductor layer is provided in a large area over a large-sized glass substrate, whereby a large-scale SOI substrate is obtained. A single-crystal semiconductor substrate provided with an embrittlement layer and a dummy substrate are bonded to each other, and the single-crystal semiconductor substrate is separated at the embrittlement... Agent: Eric Robinson

20090017583 - Double encapsulated semiconductor package and manufacturing method thereof: A double encapsulated semiconductor package and manufacturing methods of forming the same are provided. Embodiments of the semiconductor package include a complex chip having normal and random pads formed on its active surface, the complex chip being attached to a first surface of a wiring substrate. First and second windows... Agent: Marger Johnson & Mccollom, P.C.

20090017582 - Method for manufacturing semiconductor device: This invention includes a method for manufacturing a semiconductor device by which implementation of a finer pitch for a semiconductor chip can be handled, and the creation of voids inside an under-filling resin can be reduced in order to realize highly reliable flip-chip mounting. It involves a step in which... Agent: Texas Instruments Incorporated

20090017584 - Process for finfet spacer formation: A process for finFET spacer formation generally includes depositing, in order, a conformnal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source... Agent: Cantor Colburn LLP - IBM Fishkill

20090017585 - Self aligned gate jfet structure and method: A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back... Agent: Baker Botts L.L.P.

20090017586 - Channel stress modification by capped metal-semiconductor layer volume change: A method for fabricating a field effect device, such as a field effect transistor, uses a first metal-semiconductor layer, such as a first metal-silicide layer, adjacent a channel in the field effect device. The first metal-semiconductor layer has a first volume. The first metal-semiconductor layer is capped with a capping... Agent: Scully, Scott, Murphy & Presser, P.C.

20090017587 - Disposable organic spacers: A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the... Agent: Fortkort & Houston P.C.

20090017588 - Systems and methods that selectively modify liner induced stress: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a... Agent: Texas Instruments Incorporated

20090017589 - Tri-gate integration with embedded floating body memory cell using a high-k dual metal gate: Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090017590 - Method for fabricating sonos a memory: A method for fabricating a SONOS memory is disclosed. First, a semiconductor substrate is provided and a SONOS memory cell is formed on said semiconductor substrate. A passivation layer is deposited on the SONOS memory cell and a contact pad is formed on the passivation layer. Subsequently, an ultraviolet treatment... Agent: North America Intellectual Property Corporation

20090017591 - Local oxidation of silicon planarization for polysilicon layers under thin film structures: In accordance with the teachings described herein, a method for fabricating a patterned polysilicon layer having a planar surface may include the steps of: depositing a polysilicon film above a substrate material; depositing an oxide-resistant mask over the polysilicon film; patterning and etching the oxide-resistant mask to form a patterned... Agent: Patent Group 2n Jones Day

20090017592 - Siloxane polymer composition, method of forming a pattern using the same, and method of manufacturing a semiconductor using the same: wherein each of R1, R2 R3, and R4 independently represents H, OH, CH3, C2H5, C3H7, C4H9 or C5H11, R′ represents CH2, C2H4, C3H6, C4H8, C5H10 or C6H12, and n represents a positive integer so the siloxane polymer of the siloxane complex has a number average molecular weight of about 4,000... Agent: Lee & Morse, P.C.

20090017593 - Method for shallow trench isolation: Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at... Agent: Schwabe, Williamson & Wyatt, P.C.

20090017594 - Non-volatile semiconductor memory device and method of fabricating the same: There is provided a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having two trenches, an isolation oxide film provided in the trench, a floating gate electrode, an ONO film, and a control gate electrode. The... Agent: Mcdermott Will & Emery LLP

20090017595 - Reliable gap-filling process and apparatus for performing the process in the manufacturing of semiconductor devices: A reliable gap-filling process is performed in the manufacturing of a semiconductor device. An apparatus for performing the gap-filling process includes a chamber in which a wafer chuck is disposed, a plasma generator for generating plasma used to etch the wafer, an end-point detection unit for detecting the point at... Agent: Volentine & Whitt PLLC

20090017596 - Methods of forming oxides, methods of forming semiconductor constructions, and methods of forming isolation regions: Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on... Agent: Wells St. John P.s.

20090017597 - Method for manufacturing shallow trench isolation: A method for manufacturing semiconductor shallow trench isolation is performed as follows. First, a semiconductor substrate including at least one shallow trench is provided, and the shallow trench is filled with Spin-On-Dielectric (SOD) material, e.g., polysilazane, to form a SOD material layer. Then, the SOD material layer is subjected to... Agent: Wpat, PC Intellectual Property Attorneys

20090017599 - Method for manufacturing semiconductor device: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is... Agent: Eric Robinson

20090017598 - Method of manufacturing semiconductor device: To provide a method of manufacturing a semiconductor device in which the space between semiconductor films transferred at plural locations is narrowed. A first bonding substrate having first projections is attached to a base substrate. Then, the first bonding substrate is separated at the first projections so that first semiconductor... Agent: Eric Robinson

20090017600 - Wafer dividing method using laser beam with an annular spot: In a wafer dividing method of dividing a wafer into individual devices, the wafer being sectioned by streets to form the devices each made of a laminated body in which an insulating film and a function film are laminated on a front surface of a semiconductor substrate, the method includes... Agent: Greer, Burns & Crain

20090017601 - Crystalline film devices, apparatuses for and methods of fabrication: Methods of depositing thin film materials having crystalline content are provided. The methods use plasma enhanced chemical vapor deposition. According to one embodiment of the present invention, microcrystalline silicon films are obtained. According to a second embodiment of the present invention, crystalline films of zinc oxide are obtained. According to... Agent: Larry Williams

20090017602 - Method for manufacturing a semiconductor-on-insulator substrate for microelectronics and optoelectronics: t

20090017603 - Method of forming epitaxial layer: A method of forming an epitaxial layer on a silicon substrate includes (a) providing a silicon substrate; (b) performing a wet-cleaning process onto the silicon substrate; (c) performing a first plasma cleaning process onto the wet-cleaned silicon substrate by providing a chlorine (Cl2) gas and an argon (Ar) gas; and... Agent: Marger Johnson & Mccollom, P.C.

20090017604 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed... Agent: Quintero Law Office, PC

20090017606 - Method for producing a semiconductor component having regions which are doped to different extents: A method for producing a semiconductor component, in particular a solar cell, having regions which are doped to different extents. A layer is formed which inhibits the diffusion of a dopant and can be penetrated by a dopant, on at least one part of the surface of a semiconductor component... Agent: Lerner Greenberg Stemer LLP

20090017605 - Methods for doping nanostructured materials and nanostructured thin films: A method for introducing one or more impurities into nano-structured materials. The method includes providing a nanostructured material having a feature size of about 100 nm and less. The method includes subjecting a surface region of the nanostructured material to one or more impurities to form a first region having... Agent: Townsend And Townsend And Crew, LLP

20090017607 - Gate cd trimming beyond photolithography: A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a... Agent: Texas Instruments Incorporated

20090017608 - Semiconductor device fabricating method: A method for fabricating a semiconductor device is provided which has first and second regions, transistors of different conductivity types being formed on parts of a substrate corresponding to the first and second regions. The method includes the steps of: (a) forming a first insulating film to cover the parts... Agent: Mcdermott Will & Emery LLP

20090017609 - Rectangular contact used as a low voltage fuse element: A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contact is made long enough so that it makes contact at each end... Agent: Texas Instruments Incorporated

20090017610 - Junction structure of terminal pad and solder, semiconductor device having the junction structure, and method of manufacturing the semiconductor device: The present invention provides a semiconductor device which comprises a terminal pad (120) formed on an underlying base (105), solder (240), and a reactive product (260) comprising a component of the terminal pad and a Zn system material (230), which is formed between the terminal pad and the solder.... Agent: Rabin & Berdo, PC

20090017611 - Semiconductor device and method for fabricating the same: In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second... Agent: Mcdermott Will & Emery LLP

20090017613 - Method of manufacturing interconnect substrate and semiconductor device: An interconnect substrate includes an interconnect, an insulating layer, a non-photosensitive resin layer, a photosensitive resin layer, a first electrode pad, and a second electrode pad. The non-photosensitive resin layer is constructed with a non-photosensitive insulating material. Also, the non-photosensitive resin layer has a first opening. The photosensitive resin layer... Agent: Young & Thompson

20090017612 - Methods for fabricating array substrates: Methods for fabricating array substrates are provided. A method for fabricating an array substrate includes forming a first metal layer over a substrate and then patterned by a first photolithography to forming a gate line, a gate electrode connecting the gate line, and a pad over the substrate. An insulating... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090017614 - Semiconductor device: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor... Agent: Mcdermott Will & Emery LLP

20090017615 - Method of removing an insulation layer and method of forming a metal wire: A method of removing an insulation layer pattern covering metal wires includes providing an insulation layer pattern on a substrate, the insulation layer pattern having openings exposing the substrate, forming metal wires in the openings by depositing a barrier layer on inner surfaces of the openings, such that a lower... Agent: Lee & Morse, P.C.

20090017616 - Method for forming conductive structures: A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed... Agent: Schmeiser, Olsen & Watts

20090017617 - Method for formation of high quality back contact with screen-printed local back surface field: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at... Agent: Alston & Bird LLP

20090017618 - Method of fabricating semiconductor device: A method of forming a semiconductor device that includes heating a wafer on which an Al—Cu sputtering thin film is formed before patterning the Al—Cu sputtering thin film. The heating is performed at a temperature no less than a solid solution temperature of copper or at a temperature between 300°... Agent: Sherr & Vaughn, PLLC

20090017619 - Method for manufacturing metal silicide layer in a semiconductor device: A metal suicide layer is fabricated in a semiconductor device. A first metal layer is deposited on a silicon substrate formed with an S interlayer dielectric having a contact hole through PVD. A second metal layer is deposited on the first metal layer through any one of CVD and ALD.... Agent: Ladas & Parry LLP

20090017620 - Method of manufacturing semiconductor device for dual damascene wiring: A method of manufacturing a semiconductor device includes forming a via hole in an interlayer dielectric film, forming a wiring trench in said interlayer dielectric film for connecting to the via hole, and forming a dual damascene wiring trench in the interlayer dielectric film for forming a dual damascene wiring... Agent: Mcginn Intellectual Property Law Group, PLLC

20090017622 - Chemical treatment method: A chemical treatment apparatus and a method for performing a chemical treatment of a wafer, etc., by supplying a chemical via a cell. The apparatus includes a cylindrical inner cell and a cylindrical outer cell with open ends disposed at an outer circumference of the inner cell. The outer cell... Agent: Fitzpatrick Cella Harper & Scinto

20090017621 - Manufacturing method for semiconductor device and manufacturing device of semiconductor device: The semiconductor manufacturing method includes the step (ST.1) of preparing a semiconductor substrate with a copper or copper-containing metal film exposed on a surface, step (ST.2) of depositing on the copper or copper-containing metal film a metal film consisting essentially of any one of CoWB, CoWP, or W; step (ST.3)... Agent: Masuvalley & Partners

20090017623 - Wafer processing method: A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same... Agent: Greer, Burns & Crain

20090017624 - Nodule defect reduction in electroless plating: An electroless plating method and the apparatus for performing the same are provided. The method includes providing a plating solution; contacting a front surface of the wafer with the plating solution; and incurring a plating reaction substantially simultaneously on an entirety of the front surface of the wafer. The step... Agent: Slater & Matsil, L.L.P.

20090017625 - Methods for removing gate sidewall spacers in cmos semiconductor fabrication processes: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.... Agent: F. Chau & Associates, LLC

20090017626 - Semiconductor wet etchant and method of forming interconnection structure using the same: A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a... Agent: Volentine & Whitt PLLC

20090017627 - Methods of modifying oxide spacers: Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line reduction and/or smoothing the surfaces along the edges of such features through the reaction and subsequent removal of... Agent: Whyte Hirschboeck Dudek S.c. Intellectual Property Department

20090017629 - Method of forming contact structure with contact spacer and method of fabricating semiconductor device using the same: A method of forming a contact structure with a contact spacer and a method of fabricating a semiconductor device using the same. In the method of forming a contact structure, an interlayer dielectric layer is formed on a semiconductor substrate. The interlayer dielectric layer is patterned, thereby forming a contact... Agent: Marger Johnson & Mccollom, P.C.

20090017628 - Spacer lithography: Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from... Agent: Ditthavong Mori & Steiner, P.C.

20090017630 - Methods for forming contacts for dual stress liner cmos semiconductor devices: Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other... Agent: F. Chau & Associates, LLC

20090017631 - Self-aligned pillar patterning using multiple spacer masks: A method for fabricating a semiconductor mask is described. The image of a series of lines from a first spacer mask is first provided to a mask layer to form a patterned mask layer. The image of a series of lines from a second spacer mask is then provided to... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20090017632 - Methods of manufacturing semiconductor structures using rie process: A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic... Agent: Greenblum & Bernstein, P.L.C

20090017633 - Alternative method for advanced cmos logic gate etch applications: Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the... Agent: MoserIPLaw Group / Applied Materials, Inc.

20090017634 - Use of a plasma source to form a layer during the formation of a semiconductor device: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface... Agent: Schwegman, Lundberg & Woessner/micron

20090017635 - Apparatus and method for processing a substrate edge region: The present invention comprises an apparatus and method for etching at a substrate edge region. In one embodiment, the apparatus comprises a chamber having a process volume, a substrate support arranged inside the process volume and having a substrate support surface, a plasma generator coupled to the chamber and configured... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090017636 - Titanium nitride-stripping liquid, and method for stripping titanium nitride coating film: A titanium nitride-stripping liquid for stripping a titanium nitride coating film, the titanium nitride-stripping liquid being capable of stripping a titanium nitride coating film even in a semiconductor multilayer laminate having particularly a layer that includes tungsten or a tungsten alloy, without corrosion of this layer is provided, and furthermore,... Agent: Procopio, Cory, Hargreaves & Savitch LLP

20090017637 - Method and apparatus for batch processing in a vertical reactor: The present invention generally provides an apparatus and method for the processing a plurality of substrates in a batch processing chamber. One embodiment of the present invention provides a method for processing a plurality of substrates comprising positioning the plurality of substrates in an inner volume of a batch processing... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090017638 - Substrate processing apparatus and method for manufacturing semiconductor device: It is intended to provide a substrate processing apparatus and a semiconductor device manufacturing method capable of suppressing formation of a film inside a nozzle and extending a replacement or maintenance cycle of the nozzle, thereby realizing improvement in operation rate of the apparatus. A substrate processing apparatus comprising: a... Agent: Oliff & Berridge, PLC

20090017639 - Novel silicon precursors to make ultra low-k films of k<2.2 with high mechanical properties by plasma enhanced chemical vapor deposition: A method for depositing a low dielectric constant film on a substrate is provided. The low dielectric constant film is deposited by a process comprising reacting one or more organosilicon compounds and a porogen and then post-treating the film to create pores in the film. The one or more organosilicon... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090017640 - Boron derived materials deposition method: Methods of forming boron-containing films are provided. The methods include introducing a boron-containing precursor into a chamber and depositing a network comprising boron-boron bonds on a substrate by thermal decomposition or a plasma process. The network may be post-treated to remove hydrogen from the network and increase the stress of... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090017642 - Laser crystallization apparatus and laser crystallization method: A laser crystallization apparatus which capable of correcting both shift in imaging position caused by thermal lens effect of the imaging optical system and shift due to flatness of the substrate comprises an crystallization optical system which irradiates laser light to a thin film disposed on the substrate to melt... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090017641 - Substrate processing apparatus and semiconductor device producing method: Disclosed is a substrate processing apparatus, including: a chamber, made of a metal, to form a processing space for processing a substrate; at least one rod-like heating body to heat the substrate; and a tube body, made of a material different from that of the chamber, to accommodate the heating... Agent: Birch Stewart Kolasch & Birch

20090011522 - Semiconductor device package disassembly: Systems and methods are disclosed for the disassembly and preferably reassembly of semiconductor device packages. A method of the invention includes steps for excavating a portion of a semiconductor device package to expose a target surface within the interior of the package. The technique further includes steps of focusing a... Agent: Michael T. Konczal

20090011523 - Processing method and processing apparatus: A processing method of subjecting at least two stacked films, which comprise a first film and a second film of a target object to be processed, to a removing process by wet etching comprises bringing a first process liquid into contact with the first film of the target object, thereby... Agent: Smith, Gambrell & Russell

20090011524 - Method for determining suitability of a resist in semiconductor wafer fabrication: In one disclosed embodiment, the present method for determining resist suitability for semiconductor wafer fabrication comprises forming a layer of resist over a semiconductor wafer, exposing the layer of resist to patterned radiation, and determining resist suitability by using a scatterometry process prior to developing a lithographic pattern on the... Agent: Farjami & Farjami LLP

20090011525 - Method for joining adhesive tape to semiconductor wafer and method for separating protective tape from semiconductor wafer: An arithmetic processing part in a controller detects a position of a defect such as a chip or a crack that occurs at an outer periphery of a semiconductor wafer, and then a memory in the controller stores position information of the defect. The controller reads the position information of... Agent: Cheng Law Group, PLLC

20090011526 - Increasing an electrical resistance of a resistor by nitridization: A method for increasing an electrical resistance of a resistor. A semiconductor structure that includes the resistor is placed in a chamber that includes a gas including nitrogen-containing molecules at an nitrogen concentration. A fraction F of an exterior surface of a surface layer of the resistor is exposed to... Agent: Schmeiser, Olsen & Watts

20090011527 - Producing a surface-mountable radiation emitting component: A radiation-emitting surface-mountable component has a light-emitting diode chip mounted on a leadframe. A molding material encapsulates the leadframe and the light emitting diode chip.... Agent: Fish & Richardson PC

20090011528 - Method of manufacturing organic light emitting device having photo diode: A method for manufacturing an organic light emitting device including a photo diode and a transistor includes forming a first semiconductor layer and a second semiconductor layer on separate portions of a buffer layer formed on the substrate; forming a gate metal layer on the first semiconductor layer, the gate... Agent: Stein, Mcewen & Bui, LLP

20090011529 - Ir-light emitters based on swnt's (single walled carbon nanotubes), semiconducting swnts-light emitting diodes and lasers: The present invention relates to a new light emitters that exploit the use of semiconducting single walled carbon nanotubes (SWNTs). Experimental evidences are given on how it is possible, within the standard silicon technology, to devise light emitting diodes (LEDs) emitting in the infrared IR where light emission results from... Agent: Seed Intellectual Property Law Group PLLC

20090011530 - Nitride-composite semiconductor laser element, its manufacturing method, and semiconductor optical device: A nitride semiconductor laser device with a reduction in internal crystal defects and an alleviation in stress, and a semiconductor optical apparatus comprising this nitride semiconductor laser device. First, a growth suppressing film against GaN crystal growth is formed on the surface of an n-type GaN substrate equipped with alternate... Agent: Morrison & Foerster LLP

20090011531 - Semiconductor laser with narrow beam divergence: The invention relates to a method of reducing vertical divergence of a high-power semiconductor laser with a negligible threshold current and conversion efficiency penalty. The low divergence is achieved by increasing the thickness of the n-cladding layer in an asymmetric laser diode stack structure, to a value ranging from 1... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20090011533 - Isolation techniques for reducing dark current in cmos image sensors: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a... Agent: Dickstein Shapiro LLP

20090011532 - Photoelectric-conversion apparatus and image-pickup system: A photoelectric-conversion apparatus includes a photoelectric-conversion area where a plurality of photoelectric-conversion elements configured to convert incident light into electrical charges, a plurality of floating-diffusion areas, a plurality of transfer-MOS transistors configured to transfer electrical charges of the photoelectric-conversion element to the floating-diffusion area, and a plurality of amplification-MOS transistors... Agent: Fitzpatrick Cella Harper & Scinto

20090011534 - Solid-state imaging device and method of manufacturing solid-state imaging device: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being... Agent: Rader Fishman & Grauer PLLC

20090011535 - Apparatus and method of manufacturing solar cells: The present invention relates to the field of thin film solar cells and particularly to an apparatus and method for manufacturing thin film solar cells. At least one material is deposited onto a substrate, whereby the deposited material is heated by means of heating means on a limited area of... Agent: Venable LLP

20090011536 - Optical device with irox nanostruture electrode neural interface: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20090011537 - Semiconductor device and method for manufacturing same: The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090011538 - Packaging system: A mounting system is provided with a substrate loader section, a chip mounting section, and a substrate unloader section for sequentially taking out substrates whereupon chips are mounted. The mounting system is characterized in that the substrate loader section is provided with an oven capable of heat insulating a substrate... Agent: Smith Patent Office

20090011539 - Flexible structures for interconnect reliability test: A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality... Agent: Slater & Matsil, L.L.P.

20090011540 - Die-wafer package and method of fabricating same: A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated... Agent: Trask Britt, P.C./ Micron Technology

20090011541 - Stacked microelectronic devices and methods for manufacturing microelectronic devices: Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can include a support member and a first known good microelectronic die attached to the support member. The first die includes an active side, a back side opposite the active side,... Agent: Perkins Coie LLP Patent-sea

20090011542 - Structure and manufactruing method of chip scale package: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting... Agent: Mou-shiung Lin

20090011543 - Enhanced reliability of wafer-level chip-scale packaging (wlcsp) die separation using dry etching: An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each... Agent: Slater & Matsil, L.L.P.

20090011544 - Method of forming molded standoff structures on integrated circuit devices: A method of forming molding standoff structures on integrated circuit devices is disclosed which includes forming a plurality of standoff structures on a substantially rectangular sheet of transparent material and, after forming the standoff structures, singulating the substantially rectangular sheet of transparent material into a plurality of individual transparent members,... Agent: Perkins Coie LLP Patent-sea

20090011545 - Chip package process: The present invention further provides a chip package process, which includes providing a substrate, disposing a chip on the substrate and forming a buffering compound on the substrate and the chip, wherein the buffering compound covers the chip. The present invention further provides another chip package process, which includes providing... Agent: Jianq Chyun Intellectual Property Office

20090011546 - Cooling of substrate using interposer channels: A method of forming structure. A substrate and an interposer are provided. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N≧2). N interposer channels are coupled to the N substrate channels so as to form M continuous loops (1≦M≦N). Each... Agent: Schmeiser, Olsen & Watts

20090011547 - Cooling of substrate using interposer channels: A method of forming a structure. An interposer is provided. The interposer is adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made... Agent: Schmeiser, Olsen & Watts

20090011548 - Hybrid integrated circuit device and manufacturing method thereof: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on... Agent: Watchstone P+d, PLC

20090011549 - Process and system for manufacturing an encapsulated semiconductor device: A process for manufacturing a semiconductor device envisages the steps of: positioning a frame structure, provided with a supporting plate carrying a die of semiconductor material, within a molding cavity of a mold; and introducing encapsulating material within the molding cavity for the formation of a package, designed to encapsulate... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090011550 - Flat panel display device and fabricating method thereof: A flat panel display device (FPD) and fabricating method thereof are disclosed, which reduce the number of masks during fabrication and prevent electro-chemical corrosion problems. In the FPD, a cell area and a pad area are defined on a substrate. A storage electrode traverses an active layer in parallel to... Agent: Brinks Hofer Gilson & Lione

20090011551 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided, which comprises at least a steps of forming a gate insulating film over a substrate, a step of forming a microcrystalline semiconductor film over the gate insulating film, and a step of forming an amorphous semiconductor film over the microcrystalline semiconductor... Agent: Eric Robinson

20090011552 - Metal gate cmos with at least a single gate metal and dual gate dielectrics: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate... Agent: Scully, Scott, Murphy & Presser, P.C.

20090011553 - Thermally stable bicmos fabrication method and bipolar junction transistor formed according to the method: A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed... Agent: Hitt Gaines, PC Lsi Corporation

20090011554 - Component with sensitive component structures and method for the production thereof: An electrical component has electrically conducting structures placed on an electrically isolating or semiconductive substrate and component structures sensitive to a voltage or an electrical arcing and galvanically separated from one another. To prevent an arcing between the galvanically separated component structures, the component structures are short-circuited with a shunt... Agent: Mayback & Hoffman, P.A.

20090011555 - Method of manufacturing cmos integrated circuit: In a method of manufacturing a CMOS integrated circuit according to the present invention, a PSD step (step of forming P-type source/drain regions) is first carried out, and an NSD step (step of forming N-type source/drain regions) is thereafter carried out, in order to create a mixed structure of a... Agent: Rabin & Berdo, PC

20090011556 - Method for producing a microelectronic structure: A method for producing a microelectronic structure is suggested in which a layer structure (30) which partially covers a substrate (5) and which comprises at least one first conductive layer (15,20) which reaches to a side wall (35) of the layer structure (30), is covered with a second conductive layer... Agent: Altera Law Group, LLC

20090011557 - Method for manufacturing a flash memory: A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and... Agent: North America Intellectual Property Corporation

20090011558 - Method of manufacturing nonvolatile semiconductor memory: A method of manufacturing a NAND nonvolatile semiconductor memory which involves forming a bit line contact between adjacent select transistors of the NAND nonvolatile semiconductor memory, the method has patterning memory cells and said select transistors of said NAND nonvolatile semiconductor memory; forming a first insulating film between adjacent two... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090011560 - Multiple select gate architecture with select gates of different lengths: The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled... Agent: Leffert Jay & Polglaze, P.A. Att: Tod A. Myrum

20090011559 - Non-volatile semiconductor memory and method for manufacturing a non-volatile semiconductor memory: An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090011561 - Method of fabricating high-voltage mos having doubled-diffused drain: A method of fabricating high-voltage MOS having double-diffused drain (DDD) is disclosed. The original photoresist used to define a gate is used to define double-diffused drains without increasing the complexity of the whole process. A dielectric layer and a conductive layer are sequentially formed on a substrate. A patterned photoresist... Agent: Joe Mckinney Muncy

20090011562 - Process for fabricating a field-effect transistor with self-aligned gates: A first gate, formed on a substrate, is surmounted by a hard layer designed, with first spacers surrounding the first gate, to act as etching mask to bound the channel and a pad that bounds a space subsequently used to form a gate cavity. The hard layer is preferably made... Agent: Oliff & Berridge, PLC

20090011563 - Fabrication of self-aligned gallium arsenide mosfets using damascene gate methods: A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls and over a portion of the source-drain extensions. Source-drain regions... Agent: Dinsmore & Shohl LLP

20090011564 - Method of forming a gate oxide layer: A nitrogen implantation to a substrate on the edges of an active area is added before filling an insulating layer in a trench during a shallow trench isolation process to reduce the thickness of a gate oxide formed later on the edges of the active area.... Agent: Joe Mckinney Muncy

20090011565 - Field effect transistor structure with abrupt source/drain junctions: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090011566 - Method of manufacturing semiconductor device: After gate insulating films, gate electrodes, and n+ type semiconductor regions and p+ type semiconductor regions for source/drain are formed, a metal film and a barrier film are formed on a semiconductor substrate. And a first heat treatment is performed so as to make the metal film react with the... Agent: Miles & Stockbridge PC

20090011567 - Method for manufacturing display substrate: A method for manufacturing a display substrate is disclosed, which includes the following steps: providing a substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on a non-active area of the substrate; and staining the marking pattern or filling a... Agent: Bacon & Thomas, PLLC

20090011568 - Semiconductor device, method of manufacture thereof and semiconductor integrated circuit: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090011569 - Electrical device and method for fabricating the same: A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top... Agent: North America Intellectual Property Corporation

20090011570 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090011571 - Wafer working method: A wafer working method is provided which is capable of feeding a wafer diced by a laser dicing apparatus to a subsequent step without breaking up the wafer. The wafer working method comprises: a first machining step of grinding a reverse side of a wafer W and then polishing the... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department

20090011572 - Wafer working method: A wafer working method is provided which is capable of feeding a wafer diced by a laser dicing apparatus to a subsequent step without breaking up the wafer. The wafer working method comprises: a first machining step of grinding a reverse side of a wafer W and then polishing the... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department

20090011573 - Carrier used for deposition of materials on a non-planar surface: A carrier for effectuating semiconductor processing on a non-planar substrate is disclosed. The carrier is configured for holding at least one non-planar substrate throughout a semiconductor processing step and concurrently rotating non-planar substrates as they travel down a translational path of a processing chamber. As the non-planar substrates simultaneously rotate... Agent: Haverstock & Owens LLP

20090011575 - Manufacturing method of soi substrate and manufacturing method of semiconductor device: It is object to provide a manufacturing method of an SOI substrate provided with a single-crystal semiconductor layer, even in the case where a substrate having a low allowable temperature limit, such as a glass substrate, is used and to manufacture a high-performance semiconductor device using such an SOI substrate.... Agent: Eric Robinson

20090011574 - Method for surface modification of semiconductor layer and method of manufacturing semiconductor device: A method for surface modification of a semiconductor layer and a method of manufacturing a semiconductor device are provided. The method for surface modification of the silicon layer includes following steps. First, a semiconductor layer having several particles on its surface is provided. Next, these particles are removed through a... Agent: Bacon & Thomas, PLLC

20090011576 - Ultra-violet protected tamper resistant embedded eeprom: A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon... Agent: Bever Hoffman & Harms, LLP 2099 Gateway Place

20090011577 - Method of making phase change materials electrochemical atomic layer deposition: A method of making phase change materials on a substrate by electrochemical atomic layer deposition, which includes sequentially electrodepositing at least one atomic layer of a first element of a first solution and at least one atomic layer of a second element of a second solution on a substrate; and... Agent: Connolly Bove Lodge & Hutz LLP

20090011578 - Methods to fabricate mosfet devices using a selective deposition process: In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090011579 - Quantum dot array and production method therefor, and dot array element and production method therefor: The present invention is a method of manufacturing a quantum dot array having a plurality of columnar parts including a quantum dot on a substrate, the method comprising the steps of obliquely vapor-depositing a material constituting a first barrier layer to become an energy barrier against the quantum dot onto... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090011580 - Method for fabricating semiconductor memory device: A method for fabricating a semiconductor memory device includes forming a channel region in a substrate, selectively etching the substrate to form a first trench, performing an impurity ion implantation process on the channel region, and etching a lower portion of the first trench to form a second trench.... Agent: Lowe Hauptman Ham & Berner, LLP

20090011581 - Carbon controlled fixed charge process: Carbon may be implanted into a p-type silicon channel to form a carbon region in an n-type metal oxide semiconductor (NMOS) transistor. After an annealing process, the implanted carbon may diffuse from the channel into an interface of a gate dielectric layer and the channel. The diffusion may cause an... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090011582 - Method for depositing a vapour deposition material: Method for depositing a vapour deposition material on a base material, in particular for doping a semiconductor material, in which a vapour deposition batch, in which the vapour deposition material is enclosed in an air-tight manner by a shell, is introduced into a vapour deposition chamber and the shell is... Agent: Sutherland Asbill & Brennan LLP

20090011583 - Method of manufacturing a semiconductor device: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat... Agent: Myers Bigel Sibley & Sajovec

20090011584 - Method for forming transistor of semiconductor device: A method for forming a transistor of a semiconductor device, includes forming a trench by etching a semiconductor substrate on which a pad oxide film and a pad nitride film are sequentially formed; forming a isolation oxide film by filling the trench with oxide; removing an upper portion of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090011585 - Methods of etching nanodots, methods of removing nanodots from substrates, methods of fabricating integrated circuit devices, methods of etching a layer comprising a late transition metal, and methods of removing a layer comprising a late transition metal: Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing... Agent: Wells St. John P.s.

20090011586 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a first insulating film provided on a surface of a semiconductor substrate, a charge accumulation layer provided on the first insulating film, a second insulating film provided above the charge accumulation layer and contains silicon and nitrogen, a third insulating film provided on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090011587 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing... Agent: Quintero Law Office, PC

20090011588 - Flash memory and methods of fabricating flash memory: Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20090011589 - Method of manufacturing split gate type nonvolatile memory device: A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.... Agent: Volentine & Whitt PLLC

20090011591 - Film substrate, fabrication method thereof, and image display substrate: In a film substrate (FB) including a film base material (1) and conductor wiring (23) that is formed on the film base material (1), the conductor wiring (23) is arranged such that the conductor wiring thickness of an external connection portion on the film substrate to which another panel or... Agent: Steptoe & Johnson LLP

20090011590 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns... Agent: Marger Johnson & Mccollom, P.C.

20090011592 - Method of manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090011593 - Method of depositing amorphous film on capacitor assembly: A capacitor assembly includes a semiconductor substrate having an interlayer insulation film on a first main surface of the semiconductor substrate, and a conductive barrier layer formed on the interlayer insulation film. The capacitor assembly also includes a contact plug electrically connected to the conductive barrier layer through the interlayer... Agent: Volentine & Whitt PLLC

20090011594 - Methods of trench and contact formation in memory cells: Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask... Agent: J C Patents, Inc.

20090011595 - Method of forming a layer on a semiconductor substrate and apparatus for performing the same: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A... Agent: Marger Johnson & Mccollom, P.C.

20090011596 - Electronic device and manufacturing method thereof: An electronic device includes an element group which generates a specific identification number and is composed of a plurality of elements. The specific identification number is set based on irregular deviation in electric characteristic of the elements which is caused due to a random failure in a manufacturing process.... Agent: Mcdermott Will & Emery LLP

20090011597 - Mass production method of semiconductor integrated circuit device and manufacturing method of electronic device: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the... Agent: Miles & Stockbridge PC

20090011598 - Method of manufacturing semiconductor device including silicon carbide substrate: In a manufacturing method of a silicon carbide semiconductor device, a silicon carbide substrate is prepared by slicing an ingot that is made of silicon carbide single crystal. The silicon carbide substrate is heat treated for exposing a substrate defect generated at a surface portion of the silicon carbide substrate... Agent: Posz Law Group, PLC

20090011599 - Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same: Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water, and the... Agent: F. Chau & Associates, LLC

20090011602 - Film forming method of amorphous carbon film and manufacturing method of semiconductor device using the same: Disclosed is a film forming method of an amorphous carbon film, including: disposing a substrate in a processing chamber; supplying a processing gas containing carbon, hydrogen and oxygen into the processing chamber; and decomposing the processing gas by heating the substrate in the processing chamber and depositing the amorphous carbon... Agent: Pearne & Gordon LLP

20090011600 - Method and apparatus for manufacturing semiconductor device: The present invention is directed to a method and an apparatus for manufacturing a semiconductor device including step S22 to form an insulating film on a front surface of a semiconductor wafer that is a surface on which a semiconductor element is to be formed and on a back surface... Agent: Ingrassia Fisher & Lorenz, P.C.

20090011601 - Over-coating agent for forming fine patterns and a method of forming fine patterns using such agent: It is disclosed an over-coating agent for forming fine-line patterns which is applied to cover a substrate having thereon photoresist patterns and allowed to shrink under heat so that the spacing between adjacent photoresist patterns is lessened, with the applied film of the over-coating agent being removed substantially completely to... Agent: Wenderoth, Lind & Ponack, L.L.P.

20090011603 - Method of manufacturing semiconductor device: The invention prevents a wiring layer in a memory region from being exposed to prevent a change in wire resistance and degradation of reliability. A SiO2 film as an etching stopper film which transmits ultraviolet light is formed on pad electrodes and an interlayer insulation film. Then, the SiO2 film... Agent: Morrison & Foerster LLP

20090011604 - Photon induced removal of copper: Preferred embodiments provide a method for removing at least part of a copper comprising layer from a substrate, the substrate comprising at least a copper comprising surface layer. The method comprises in a first reaction chamber converting at least part of the copper comprising surface layer into a copper halide... Agent: Knobbe Martens Olson & Bear LLP

20090011605 - Method of manufacturing semiconductor device: The present invention is an apparatus for manufacturing a semiconductor device comprising: a process vessel including a stage on which a substrate is placed, the substrate having a low dielectric constant film with a resist pattern being formed in an upper layer of the low dielectric constant film; an etching-gas... Agent: Smith, Gambrell & Russell

20090011606 - Substrate processing apparatus and semiconductor device producing method: A substrate processing apparatus, comprising: a processing chamber which provides a space for flowing desired gas and for depositing a desired film on a substrate; a lamp unit group having at least one lamp unit which is disposed in the processing chamber and which includes a filament for heating the... Agent: Birch Stewart Kolasch & Birch

20090011608 - Manufacturing method of semiconductor device: The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the... Agent: Miles & Stockbridge PC

20090011607 - Silicon dioxide deposition methods using at least ozone and teos as deposition precursors: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions... Agent: Wells St. John P.s.

20090011609 - Radical oxidation process for fabricating a nonvolatile charge trap memory device: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a... Agent: Cypress/blakely Blakely Sokoloff Taylor & Zafman LLP

20090011610 - Selective implementation of barrier layers to achieve treshold voltage control in cmos device fabrication with high k dielectrics: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating... Agent: Scully, Scott, Murphy & Presser, P.C.

20090011611 - Method for manufacturing semiconductor device: It is an object to provide a method for manufacturing a semiconductor device that has a semiconductor element including a film in which mixing impurities is suppressed. It is another object to provide a method for manufacturing a semiconductor device with high yield. In a method for manufacturing a semiconductor... Agent: Nixon Peabody, LLP

20090011612 - Method of shortening photoresist coating process: A method of shortening a photoresist coating process for a plurality of wafers is provided, wherein the photoresist coating process includes a first coating operation to a first wafer using a first photoresist liquid and a second coating operation to a second wafer using a second photoresist liquid. The method... Agent: J C Patents, Inc.

20090011613 - Method for producing annealed wafer and annealed wafer: The present invention is a method for producing an annealed wafer, wherein, at least, when a boat in which a semiconductor wafer is placed is inserted into a furnace tube, the boat is inserted along with introducing an inert gas into the furnace, so that entirety of the semiconductor wafer... Agent: Oliff & Berridge, PLC

20090011614 - Reconfigurable semiconductor structure processing using multiple laser beam spots: Methods and systems selectively irradiate structures on or within a semiconductor wafer using multiple laser beams. The structures may be laser-severable conductive links, and the purpose of the irradiation may be to sever selected links. The structures are arranged in rows and may be processed in either an on-axis mode... Agent: Stoel Rives LLP

20090011615 - Advanced processing technique and system for preserving tungsten in a device structure: Removing photoresist from a workpiece is described when a region of tungsten is exposed. A plasma is generated from a gas input consisting essentially of hydrogen gas and oxygen gas in a predetermined ratio. The plasma causes the photoresist to be removed from the workpiece while the region of tungsten... Agent: Pritzkau Patent Group, LLC

20090004759 - Cobalt-doped indium-tin oxide films and methods: Methods of forming cobalt-doped indium-tin oxide structures are shown. Properties of structures include transparency, conductivity, and ferromagnetism. Monolayers that contain indium, monolayers that contain tin, and monolayers that contain cobalt are deposited onto a substrate and subsequently processed to form cobalt-doped indium-tin oxide. Devices that include oxide structures formed with... Agent: Schwegman, Lundberg & Woessner, P.A.

20090004760 - Method for producing a matrix for detecting electromagnetic radiation and method for replacing an elementary module of such a detection matrix: A method for producing a matrix of electromagnetic radiation detectors made up of a plurality of elementary detection modules mounted on an interconnection substrate. The method includes depositing on the interconnection substrate a predefined number of quantities of solder or hybridization material, intended to constitute hybridization bumps for the elementary... Agent: Burr & Brown

20090004761 - Semiconductor device and manufacturing method therefor: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090004762 - Stacking apparatus and method for stacking integrated circuit elements: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position... Agent: Morgan Lewis & Bockius LLP

20090004763 - Laser crystallization method and crystallization apparatus: The present invention discloses a laser crystallization method and crystallization apparatus using a high-accuracy substrate height control mechanism. There is provided a laser crystallization method includes obtaining a first pulse laser beam having an inverse-peak-pattern light intensity distribution formed by a phase shifter, and irradiating a thin film disposed on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090004764 - Method for manufacturing soi substrate and method for manufacturing semiconductor device: To provide a method for manufacturing an SOI substrate provided with a single-crystal semiconductor layer which is suitable for practical use even when a substrate of which heat-resistant temperature is low, such as a glass substrate, is used, and to manufacture a highly reliable semiconductor device using such an SOI... Agent: Eric Robinson

20090004765 - Method of manufacturing micro-optic device: A micro-optic device including a complicate structure and a movable mirror is made to be manufactured in a reduced length of time. A silicon substrate and a single crystal silicon device layer with an intermediate layer of silicon dioxide interposed therebetween defines a substrate on which a layer of mask... Agent: Gallagher & Lathrop, A Professional Corporation

20090004766 - Method for producing electronic components and pressure sensor: A method produces electronic components in particular electronic sensors for pressure and differential pressure measurement. Firstly, the semiconductor structure of the electronic components is produced on a wafer. An insulating oxide layer is then applied. A protective metal layer is subsequently applied. The metal layer is applied in sections only... Agent: Panitch Schwarze Belisario & Nadel LLP

20090004767 - Suspended membrane pressure sensing array: An accurate and low cost macro pressure sensor is described. The pressure sensor includes an array of capacitive sensing elements formed at the intersections of sets of conductors. A lower set of conductors is supported by a substrate and an upper set of conductors is supported on a flexible polymer... Agent: Wolf Greenfield & Sacks, P.C.

20090004768 - Radiation detecting apparatus, radiation imaging apparatus and radiation imaging system: A radiation detecting apparatus according to the present invention includes: pixels including switching elements arranged on an insulating substrate and conversion elements arranged on the switching elements to convert a radiation into electric carriers, the switching elements and the conversion elements are connected with each other, the pixels two-dimensionally arranged... Agent: Fitzpatrick Cella Harper & Scinto

20090004769 - Method for manufacturing image sensor: A method for manufacturing an image sensor is disclosed. The manufacturing method includes forming a unit pixel including a photodiode and a gate on a semiconductor substrate, forming an interlayer insulating layer on the semiconductor substrate including the unit pixel, planarizing the interlayer insulating layer, forming a protection layer with... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090004770 - Method for manufacturing vertical cmos image sensor: A method for manufacturing a vertical CMOS image sensor related to a semiconductor device is disclosed. A high-temperature double annealing process and/or an additional passivation nitride film are selectively applied in order to improve dark leakage characteristics and also to prevent or reduce an incidence of circular defects, thereby enhancing... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090004772 - Method of manufacturing semiconductor device: An object of the invention is to provide a method for manufacturing semiconductor devices that are flexible in which elements fabricated using a comparatively low-temperature (less than 500° C.) process are separated from a substrate. After a molybdenum film is formed over a glass substrate, a molybdenum oxide film is... Agent: Fish & Richardson P.C.

20090004771 - Methods for making electronic devices with a solution deposited gate dielectric: A method of making an electronic device comprises solution depositing a dielectric composition onto a substrate and polymerizing the dielectric composition to form a gate dielectric. The dielectric composition comprises a polymerizable resin and zirconium oxide nanoparticles.... Agent: 3m Innovative Properties Company

20090004773 - Methods of fabricating multi-layer phase-changeable memory devices: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a... Agent: Myers Bigel Sibley & Sajovec

20090004774 - Method of multi-chip packaging in a tsop package: A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include a leadframe having one or more semiconductor die and one or more passive components affixed thereon. The one or more passive components may be affixed by soldering with a solder... Agent: Vierra Magen/sandisk Corporation

20090004775 - Methods for forming quad flat no-lead (qfn) packages: Methods are provided for forming Quad Flat No-Lead (QFN) packages. An embodiment includes disposing an active side of a semiconductor chip on a plurality of leads, coupling a plurality of wire bonds to the active side of the semiconductor chip, coupling the plurality of wire bonds to the plurality of... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20090004776 - Method of fabricating a memory card using sip/smt hybrid technology: A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form... Agent: Vierra Magen/sandisk Corporation

20090004777 - Stacked die semiconductor package and method of assembly: A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a... Agent: Sughrue Mion, PLLC

20090004778 - Manufacturing method of light emitting diode: Disclosed is a manufacturing method of a light emitting diode. The manufacturing method comprises the steps of preparing a substrate and mounting light emitting chips on the substrate. An intermediate plate is positioned on the substrate. The intermediate plate has through-holes for receiving the light emitting chips and grooves for... Agent: Marger Johnson & Mccollom, P.C.

20090004779 - Fabrication method of semiconductor integrated circuit device: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090004780 - Method for fabricating semiconductor chip: After a film layer 6 formed from a die attach film 4 and a UV tape 5 has been provided as a mask on a semiconductor wafer 1, boundary trenches 7 for partitioning semiconductor elements 2 formed on a circuit pattern formation surface 1a are formed in the film layer... Agent: Pearne & Gordon LLP

20090004781 - Method of fabricating a semiconductor die having a redistribution layer: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a... Agent: Vierra Magen/sandisk Corporation

20090004782 - Method of fabricating a two-sided die in a four-sided leadframe based package: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.... Agent: Vierra Magen/sandisk Corporation

20090004784 - Method for fabricating semiconductor package free of substrate: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the... Agent: Edwards Angell Palmer & Dodge LLP

20090004783 - Method of package stacking using unbalanced molded tsop: A semiconductor package assembly is disclosed including a pair of stacked leadframe-based semiconductor packages. The first package is encapsulated in a mold compound so that the electrical leads emanate from the sides of the package, near a bottom surface of the package. The first package may be stacked atop the... Agent: Vierra Magen/sandisk Corporation

20090004785 - Method of fabricating a semiconductor package having through holes for molding back side of package: A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the... Agent: Vierra Magen/sandisk Corporation

20090004786 - Method for fabricating a 3-d integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an... Agent: Vierra Magen/sandisk Corporation

20090004787 - Thin film transistor array panel for liquid crystal display: There are provided two subpixels opposite each other with respect to each data line. A pair of gate lines are provided for each row of pixels. A plurality of subsidiary signal lines are provided between the adjoining columns of the pixels. The data lines and the subsidiary signal lines are... Agent: F. Chau & Associates, LLC

20090004788 - Thin film transistors and fabrication methods: A method of fabricating a low temperature semiconductor thin film device is described. The method includes: forming one or more metal lines on a substrate; forming a conductive contact to a said metal line; forming a thin film device having: a first amorphous silicon region, wherein a portion of the... Agent: Raminda U. Madurawe

20090004789 - Method of forming semiconductor device having stacked transistors: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are... Agent: Myers Bigel Sibley & Sajovec

20090004790 - Method for manufacturing junction semiconductor device: A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal,... Agent: Birch Stewart Kolasch & Birch

20090004791 - Semiconductor switching devices and fabrication methods: Methods of fabricating low temperature semiconductor thin film switching devices are described. A method includes: forming one or more metal lines on a substrate; forming a conductive contact to a said metal line thru an insulator layer above the metal lines; forming a thin film N-type and P-type conducting transistor... Agent: Raminda U. Madurawe

20090004792 - Method for forming a dual metal gate structure: A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming... Agent: Freescale Semiconductor, Inc. Law Department

20090004793 - Method of forming contact plugs: A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20090004794 - Use of dilute steam ambient for improvement of flash devices: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures... Agent: Knobbe Martens Olson & Bear LLP

20090004795 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device that prevents generation of voids when forming an interlayer dielectric film. The method may include forming a gate on a semiconductor substrate, and then sequentially stacking a first dielectric film and a second dielectric film on the semiconductor substrate, and then forming... Agent: Sherr & Vaughn, PLLC

20090004796 - Method of manufacturing non-volatile memory: A method of manufacturing a non-volatile memory includes providing a substrate and forming a patterned mask layer, a tunnel dielectric layer, and a first conductive layer on the substrate. The first conductive layer on the mask layer is removed to form second conductive layers disposed on the sidewall of the... Agent: Jianq Chyun Intellectual Property Office

20090004797 - Method for fabricating semiconductor device: A method of fabricating a semiconductor device includes forming a plurality of pillars which are arranged on a substrate in a first direction and a second direction that intersects the first direction, thereby forming a resulting structure, forming a capping layer on the resulting structure including the pillars, removing the... Agent: Townsend And Townsend And Crew, LLP

20090004798 - Recessed gate structure with stepped profile: Disclosed herein are a recess-gate structure in which junctions have a thickness significantly smaller than the thickness of a device isolation layer to thereby prevent shorting of the junctions located at opposite lateral sides of the device isolation layer close thereto, resulting in an improvement in the operational reliability of... Agent: Marshall, Gerstein & Borun LLP

20090004799 - Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure: According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is formed over the first feature. At least one etch... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20090004800 - Methods of manufacturing semiconductor devices: In a method of manufacturing a semiconductor device, a conductive layer pattern may be formed on a substrate. An oxide layer may be formed on the substrate to cover the conductive layer pattern. A diffusion barrier layer may be formed by treating the oxide layer to increase an energy required... Agent: Harness, Dickey & Pierce, P.L.C

20090004802 - Method of fabricating non-volatile memory device having charge trapping layer: A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using... Agent: Marshall, Gerstein & Borun LLP

20090004801 - Method of forming lutetium and lanthanum dielectric structures: Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control.... Agent: Schwegman, Lundberg & Woessner, P.A.

20090004804 - Method of fabricating semiconductor devices: A method of fabricating a semiconductor device may include forming a well in a semiconductor substrate, and then forming a gate oxide on and/or over the semiconductor substrate, and then forming a gate on and/or over the gate oxide, and then forming a pocket under the gate, and then performing... Agent: Sherr & Vaughn, PLLC

20090004803 - Multi-stage implant to improve device characteristics: One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure.... Agent: Texas Instruments Incorporated

20090004805 - Damage implantation of a cap layer: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In... Agent: Texas Instruments Incorporated

20090004806 - Noise reduction in semiconductor device using counter-doping: One or more embodiments describe a method of fabricating a silicon based metal oxide semiconductor device, comprising: implanting a first dopant into a first partial completion of the device, the first dopant comprising a first noise reducing species; and implanting a second dopant into a second partial completion of the... Agent: Schwegman, Lundberg & Woessner / Infineon

20090004807 - Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or... Agent: Dla Piper US LLP

20090004808 - Method for fabricating semiconductor device: A method for fabricating a capacitor includes forming a sacrificial layer having a plurality of trenches on an upper portion of a substrate, forming storage nodes in the trenches, exposing upper portions of the storage nodes by removing a portion of the sacrificial layer, forming supporters to support the exposed... Agent: Townsend And Townsend And Crew, LLP

20090004809 - Method of integration of a mim capacitor with a lower plate of metal gate material formed on an sti region or a silicide region formed in or on the surface of a doped well with a high k dielectric material: A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed... Agent: Graham S. Jones, Ii

20090004810 - Method of fabricating memory device: Disclosed herein is a method of fabricating a memory device. The method includes forming an etch stop layer, bit lines, and a first hard mask pattern over a semiconductor substrate. A first SNC plug is formed between the bit lines, and an etch process is performed to reduce the height... Agent: Marshall, Gerstein & Borun LLP

20090004811 - Semiconductor composite device, method for manufacturing the semiconductor composite device, led head that employs the semiconductor composite device, and image forming apparatus that employs the led head: A semiconductor composite apparatus includes a semiconductor thin film and a metal layer formed on a substrate. The semiconductor thin film is bonded to the metal layer formed on the substrate. A region is formed between the semiconductor thin film and the metal surface, and contains an oxide of a... Agent: Rabin & Berdo, P.C.

20090004813 - Method for fabricating semiconductor device with vertical channel transistor: A method and system are provided for fabricating a semiconductor device that includes a vertical channel transistor. An area of a buried bit line is uniformly formed by an isolation trench. The width of the isolation trench is adjusted by controlling the thickness of spacers. Consequently, the area of the... Agent: Townsend And Townsend And Crew, LLP

20090004812 - Method for producing shallow trench isolation: The present invention provides a method for producing a shallow trench isolation, comprises: forming a plurality of first grooves on a silicon substrate with a mask etching method, wherein the silicon substrate comprises a silicon layer, an oxide layer and a first polysilicon layer; conducting oxidation process on an inner... Agent: Birch Stewart Kolasch & Birch

20090004814 - Method of fabricating flash memory device: The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard... Agent: Marshall, Gerstein & Borun LLP

20090004815 - Method for manufacturing semiconductor device: Disclosed herein is a method of making a semiconductor device. According to the method, a flowable oxide (FOX) is deposited over a semiconductor substrate, and a local active region is exposed to grow an active region, by a silicon epitaxial growth (SEG) method, to prevent generation of a void when... Agent: Marshall, Gerstein & Borun LLP

20090004816 - Method of forming isolation layer of semiconductor device: A method of forming an isolation layer in a semiconductor device using rapid vapor deposition to fill in a trench of the semiconductor device comprises forming a hydrophilic layer on the trench and forming a hydrophobic layer on a region other than the trench, and selectively forming a buried insulating... Agent: Marshall, Gerstein & Borun LLP

20090004818 - Method of fabricating flash memory device: Disclosed herein is a method of fabricating a semiconductor flash memory device, which method avoids and prevents damage to the conductive layer of a floating gate. The disclosed method can prevent a reduction in the charge trap density characteristics and improve the yield of the device.... Agent: Marshall, Gerstein & Borun LLP

20090004819 - Method of fabricating flash memory device: In one aspect of the inventive method, a tunnel insulating film, a first conductive layer, and an isolation mask pattern are formed over a semiconductor substrate. The first conductive layer and the tunnel insulating film are patterned along the isolation mask pattern. A trench is formed in the semiconductor substrate.... Agent: Marshall, Gerstein & Borun LLP

20090004817 - Method of forming isolation layer of semiconductor device: A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area;... Agent: Marshall, Gerstein & Borun LLP

20090004820 - Method of forming isolation layer in flash memory device: The invention relates to a method of forming an isolation layer in a flash memory device and comprises providing a semiconductor substrate in which a tunnel insulating layer and a conductive layer are formed on an active region and a trench is formed on an isolation region; forming a first... Agent: Marshall, Gerstein & Borun LLP

20090004823 - Manufacturing method of semiconductor: A manufacturing method of a semiconductor device in which a space between semiconductor films transferred to a plurality of places can be made small. Transfer of a semiconductor film from a bond substrate to a base substrate is carried out a plurality of times. In the case where a semiconductor... Agent: Eric Robinson

20090004821 - Manufacturing method of soi substrate and manufacturing method of semiconductor device: An effect of metal contamination caused in manufacturing an SOI substrate can is suppressed. A damaged region is formed by irradiating a semiconductor substrate with hydrogen ions, and then, a base substrate and the semiconductor substrate are bonded to each other. Heat treatment is performed thereon to cleave the semiconductor... Agent: Fish & Richardson P.C.

20090004822 - Semiconductor substrate, manufacturing method of semiconductor substrate, and semiconductor device and electronic device using the same: A method of manufacturing a semiconductor substrate is demonstrated, which enables the formation of a single crystal semiconductor layer on a substrate having an insulating surface. The manufacturing method includes the steps of: ion irradiation of a surface of a single-crystal semiconductor substrate to form a damaged region; laser light... Agent: Eric Robinson

20090004826 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover... Agent: Mills & Onello LLP

20090004825 - Method of manufacturing semiconductor substrate: A method of manufacturing a semiconductor substrate having a DSB structure that enables simplification of a manufacturing process by optimizing a total thickness of oxides on surfaces of two wafers before being bonded together is provided. The method comprises a process of preparing a first semiconductor wafer and a second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090004824 - Method, apparatus for holding and treatment of a substrate: Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which... Agent: Schwegman, Lundberg & Woessner / Infineon

20090004827 - Lead cutter and method of fabricating semiconductor device: Aimed at stably forming sheared surfaces of leads of semiconductor devices, and at raising ratio of formation of plated layers onto the sheared surfaces of the leads, a lead cutter has a die 106, and a cutting punch 110 having a cutting edge at least on the surface facing the... Agent: Young & Thompson

20090004828 - Laser beam machining method for wafer: A laser beam machining method for a wafer, wherein an operation of irradiating the inside of a wafer with a laser beam L along each of planned dividing lines is repeated a plural number of times from a position proximate to a back-side surface of the wafer toward a face-side... Agent: Greer, Burns & Crain

20090004829 - Adhesive composition, adhesive sheet and production process for semiconductor device: An adhesive sheet which can actualize a high package reliability wherein there is no separation at the adhesive interface and no package cracking, in a package in which a semiconductor chip being reduced in thickness is mounted under severe reflow conditions after exposure to a hot and humid environment. The... Agent: The Webb Law Firm, P.C.

20090004830 - Device and method for depositing especially doped layers by means of ovpd or the like: The invention relates to a method for producing especially doped layers for electronic, luminescent or photovoltaic components, especially OLEDs, where one or more liquid or solid starting materials evaporate in a source (11, 12, 13, 14) or are admixed as aerosol to a carrier gas and transported in this form... Agent: Sonnenschein Nath & Rosenthal LLP

20090004831 - Method of creating defect free high ge content (> 25%) sige-on-insulator (sgoi) substrates using wafer bonding techniques: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding... Agent: Scully, Scott, Murphy & Presser, P.C.

20090004832 - Thick film semiconducting inks: A method of producing a printable composition comprises mixing a quantity of particulate semiconductor material with a quantity of a binder. The semiconductor material is typically nanoparticulate silicon with a particle size in the range from 5 nanometres to 10 microns. The binder is a self-polymerising material comprising a natural... Agent: John S. Pratt, Esq Kilpatrick Stockton, LLP

20090004833 - Method of manufacturing semiconductor storage device: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090004834 - Substrates and methods for fabricating the same: An embodiment of the invention provides a substrate. The substrate comprises a single crystal substrate. An epitaxial buffer film is on the single crystal substrate. An epitaxial ZnGa2O4 is on the epitaxial buffer film.... Agent: Quintero Law Office, PC

20090004835 - Method for producing semi-conducting material wafers by moulding and directional crystallization: Wafers of semi-conducting material are formed by moulding and directional crystallization from a liquid mass of this material. A seed, situated at the bottom of the crucible, presents an orientation along non-dense crystallographic planes. The mould is filled with the molten semi-conducting material by means of a piston or by... Agent: Oliff & Berridge, PLC

20090004836 - Plasma doping with enhanced charge neutralization: A plasma doping apparatus includes a pulsed power supply that generates a pulsed waveform having a first period with a first power level and a second period with a second power level. A plasma source generates a pulsed plasma with the first power level during the first period and with... Agent: Rauschenbach Patent Law Group, LLC

20090004837 - Method of fabricating semiconductor device: Provided is a method of fabricating a semiconductor device having an impurity region with an impurity concentration of a first dose in a substrate. In the method, first impurity ions of a first conductivity type are implanted into the substrate, and a rapid thermal processing (RTP) is performed on the... Agent: Marshall, Gerstein & Borun LLP

20090004838 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes the steps of: forming an etching layer (17) formed of silicon on a semiconductor substrate (10); forming a mask layer (20) with a pattern on the etching layer (17), which includes an intermediate layer (22) as a silicon oxide film and a... Agent: Ingrassia Fisher & Lorenz, P.C.

20090004839 - Method for fabricating an interlayer dielectric in a semiconductor device: In a method for fabricating an interlayer dielectric in a semiconductor device, conductive patterns are formed on a semiconductor substrate. A fluid dielectric is formed to cover the conductive patterns. The fluid dielectric is recessed. A buried dielectric is deposited on the conductive patterns exposed by the recessing process. The... Agent: Townsend And Townsend And Crew, LLP

20090004840 - Method of creating molds of variable solder volumes for flip attach: A method for fabricating a solder transfer mold includes masking a substrate with a masking agent. A pattern is transferred to the substrate mask. The masked substrate is etched until cavities of a first volume are formed. The cavities of the first volume are selectively coated. The masked substrate is... Agent: Frank Chau, Esq. F.chau & Associates, LLC

20090004841 - Forming vias using sacrificial material: In one embodiment, the present invention includes a method for forming a sacrificial material layer, patterning it to obtain a first patterned sacrificial material layer, embedding the first patterned sacrificial material layer into a dielectric material, treating the first patterned sacrificial material layer to remove it to thus provide a... Agent: Trop Pruner & Hu, PC

20090004842 - Method of manufacturing semiconductor device: The present invention relates to a method of fabricating a semiconductor device. According to the method, a first insulating layer having a contact hole formed therein is formed over a semiconductor substrate. A second insulating layer is gap filled within the contact hole. A third insulating layer having a trench... Agent: Marshall, Gerstein & Borun LLP

20090004843 - Method for forming dual bit line metal layers for non-volatile memory: Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed... Agent: Vierra Magen/sandisk Corporation

20090004844 - Forming complimentary metal features using conformal insulator layer: A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the... Agent: Vierra Magen/sandisk Corporation

20090004845 - Method for making semiconductor structures implementing sacrificial material: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and... Agent: Martine Penilla & Gencarella, LLP

20090004846 - Wiring board, manufacturing method thereof, semiconductor device and manufacturing method thereof: The invention provides a wiring board having a small-scale and high-performance functional circuit while realizing a multi-layer wiring with a small number of steps. In addition, the invention provides a semiconductor device in which a display device is integrated with such high-performance functional circuit on the same substrate. According to... Agent: Nixon Peabody, LLP

20090004847 - Method of manufacturing semiconductor device: In a process of forming the bit line pattern, over etching is performed to recess a lower interlayer insulating film such that the thickness of the interlayer insulating film to be etched in a subsequent process, that is, a process of etching a storage node contact hole, is reduced. In... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090004848 - Method for fabricating interconnection in semiconductor device: A method for fabricating an interconnection in a semiconductor device includes forming a hydrogenated tungsten nucleation layer on a semiconductor substrate, and forming a bulk tungsten layer on the tungsten nucleation layer. Boron ions react with a hydrogen gas supplied together with a diborane gas to be restored to a... Agent: Marshall, Gerstein & Borun LLP

20090004849 - Method for fabricating an inter dielectric layer in semiconductor device: In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the... Agent: Marshall, Gerstein & Borun LLP

20090004850 - Process for forming cobalt and cobalt silicide materials in tungsten contact applications: Embodiments of the invention described herein generally provide methods for forming cobalt silicide layers and metallic cobalt layers by using various deposition processes and annealing processes. In one embodiment, a method for forming a metallic silicide containing material on a substrate is provided which includes forming a metallic silicide material... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090004851 - Salicidation process using electroless plating to deposit metal and introduce dopant impurities: A selective electroless plating operation provides for the selective deposition of a metal film only on exposed silicon surfaces of a semiconductor substrate and not on other surfaces such as dielectric surfaces. The plating solution includes metal ions and advantageously also includes dopant impurity ions. The pure metal or metal... Agent: Duane Morris LLP (tsmc)IPDepartment

20090004853 - Method for forming a metal silicide: The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds... Agent: Texas Instruments Incorporated

20090004852 - Nanostructures containing metal semiconductor compounds: A network element (10), such as a Packet Data Serving Node, detects (31) a change in operational status of a mobile station during a communication session and, in response to detecting such a change, automatically increases (32) memory capacity as is available to support additional communication sessions while simultaneously persisting... Agent: Wolf Greenfield & Sacks, P.C.

20090004854 - Method of fabricating flash memory device: The present invention relates to a method of fabricating a flash memory device. The method may include forming a first and a second interlayer insulating film on a semiconductor substrate having a cell region, etching the second and first interlayer insulating films, thus forming a contact hole through which a... Agent: Marshall, Gerstein & Borun LLP

20090004855 - Method for fabricating semiconductor device: A method of fabricating a semiconductor device, the method includes forming gate patterns on a substrate, recessing the substrate between the gate patterns, thereby forming a first resulting structure including recesses, forming a gate spacer layer on an entire surface of the first resulting structure including the gate patterns, etching... Agent: Lowe Hauptman Ham & Berner, LLP

20090004856 - Method of forming contact plug in semiconductor device: A method of forming a contact plug in a semiconductor device comprising etching an interlayer insulating layer to form a patterned interlayer insulating layer having contact holes such that a distance between upper portions of the contact holes is minimized; forming a first insulating layer including a overhang portion for... Agent: Marshall, Gerstein & Borun LLP

20090004857 - Method of manufacturing a semiconductor device using the self aligned contact (sac) process flow for semiconductor devices with aluminum metal gates: In one embodiment, a method, comprises forming a diffusion layer on a semiconductor substrate, forming a selectively deposited metal or metal alloy on an aluminum gate structure by removing an aluminum oxide layer from the aluminum gate structure and depositing a zinc layer on the aluminum gate structure by a... Agent: Caven & Aghevli C/o Intellevate, LLC

20090004858 - Tantalum amide complexes for depositing tantalum-containing films, and method of making same: Tantalum precursors useful in depositing tantalum nitride or tantalum oxides materials on substrates, by processes such as chemical vapor deposition and atomic layer deposition. The precursors are useful in forming tantalum-based diffusion barrier layers on microelectronic device structures featuring copper metallization and/or ferroelectric thin films.... Agent: Intellectual Property / Technology Law

20090004859 - Method of machining wafer: A method of machining a wafer in which, at the time of grinding the back-side surface of the wafer, only a back-side surface region corresponding to a device formation region where semiconductor chips are formed is thinned by grinding, to form a recessed part on the back side of the... Agent: Greer, Burns & Crain

20090004860 - Atomic layer volatilization process for metal layers: A two-stage method to remove a metal layer from a substrate surface comprises using a CMP process to remove a first portion of the metal layer from the substrate surface, and using an ALV process to remove a second portion of the copper layer from the substrate surface. The ALV... Agent: Intel Corporation C/o Intellevate, LLC

20090004861 - Method for fabricating semiconductor device with vertical channel: A method for fabricating a semiconductor device with a vertical channel includes providing a substrate over which a hard mask pattern is formed, forming pillars over the substrate using the hard mask pattern thereby forming a resultant structure, forming an insulation layer over the resultant structure, planarizing the hard mask... Agent: Townsend And Townsend And Crew, LLP

20090004862 - Method for forming fine patterns in semiconductor device: A method for forming fine patterns in a semiconductor device includes forming an etch stop layer and a sacrificial layer over an etch target layer, forming photoresist patterns over the sacrificial layer, etching the sacrificial layer by using the photoresist patterns as an etch barrier to form sacrificial patterns, forming... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090004863 - Polishing liquid and polishing method using the same: The present invention provides a polishing liquid for polishing a ruthenium-containing barrier layer, the polishing liquid being used in chemical mechanical polishing for a semi-conductor device having a ruthenium-containing barrier layer and conductive metal wiring lines on a surface thereof, the polishing liquid comprising an oxidizing agent; and a polishing... Agent: Sughrue Mion, PLLC

20090004864 - Cmp method of semiconductor device: The present invention relates to a Chemical Mechanical Polishing (CMP) method of a semiconductor device. According to the method, a metal layer is formed over a semiconductor substrate in which an edge region define. A passivation layer is formed on the metal layer. The passivation layer formed in the edge... Agent: Townsend And Townsend And Crew, LLP

20090004865 - Method for treating a wafer edge: A method for treating an edge portion of a wafer with a plasma or select chemical formulation in order to enhance adhesion characteristics and inhibit delamination of a layer of material from the wafer surface only on the edge portion that is being treated. Alternatively, the method may be utilized... Agent: Hoffman Warnick LLC

20090004866 - Method of forming micro pattern of semiconductor device: A method for fabricating a semiconductor device includes forming a target etch layer over a substrate, a first auxiliary layer over the target etch layer, an isolation layer over the first auxiliary layer, and a second auxiliary layer over the isolation layer. A first exposure process is performed, where the... Agent: Townsend And Townsend And Crew, LLP

20090004867 - Method of fabricating pattern in semiconductor device using spacer: A method of fabricating patterns of a semiconductor device includes the steps of forming first sacrificial layer patterns over a pattern target layer; forming first spacers on sidewalls of the first sacrificial layer patterns; forming a second sacrificial layer pattern over the first sacrificial layer patterns and the first spacers... Agent: Marshall, Gerstein & Borun LLP

20090004868 - Amorphous silicon oxidation patterning: In one embodiment, a method comprises forming a sacrificial amorphous silicon layer on a semiconductor substrate, forming a hardmask on the amorphous silicon layer, etching one or more lines in the sacrificial amorphous silicon layer, growing oxide structures on the amorphous silicon layer, and forming a trench in the semiconductor... Agent: Caven & Aghevli C/o Intellevate, LLC

20090004869 - Mask forming and implanting methods using implant stopping layer: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing... Agent: Hoffman Warnick LLC

20090004870 - Methods for high temperature etching a high-k material gate structure: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090004871 - Processing method and plasma processing device: A plasma processing method using plasma includes steps of applying current to a coil and introducing gas into a processing chamber, applying a bias power that does not generate plasma, applying a source power to generate plasma so that a plasma density distribution is high above an outer circumference of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20090004872 - Method of manufacturing a semiconductor device: A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a... Agent: Fish & Richardson P.C.

20090004873 - Hybrid etch chamber with decoupled plasma controls: A dielectric etch chamber and method for improved control of plasma parameters. The plasma chamber comprises dual-frequency bias source that capacitively couples the RF energy to the plasma, and a single or dual frequency source that inductively couples the RF energy to the plasma. The inductive source may be modulated... Agent: Nixon Peabody, LLP

20090004874 - Inductively coupled dual zone processing chamber with single planar antenna: A dual zone plasma processing chamber is provided. The plasma processing chamber includes a first substrate support having a first support surface adapted to support a first substrate within the processing chamber and a second substrate support having a second support surface adapted to support a second substrate within the... Agent: Buchanan, Ingersoll & Rooney PC

20090004875 - Methods of trimming amorphous carbon film for forming ultra thin structures on a substrate: Methods for forming an ultra thin structure using a method that includes trimming a mask layer during an etching process are provided. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one... Agent: Patterson & Sheridan, LLP - - Appm/tx

20090004876 - Method for etching single wafer: An object of the present invention is to provide a method for etching a single wafer, which effectively realizes a high flatness of wafer and an increase in productivity thereof. In a method for etching a single wafer, a single thin disk-like wafer sliced from a silicon single crystal ingot... Agent: Duane Morris LLP - Ny Patent Department

20090004877 - Substrate processing apparatus and semiconductor device manufacturing method: Disclosed is a substrate processing apparatus which includes: a processing chamber to process a substrate; an exhaust path to exhaust the processing chamber; an exhaust device; an exhaust valve to open and close the exhaust path; a raw material gas supply member to supply raw material gas which contributes to... Agent: Birch Stewart Kolasch & Birch

20090004878 - Method of manufacturing an soi substrate and method of manufacturing a semiconductor device: It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further,... Agent: Eric Robinson

20090004880 - Mask reuse in semiconductor processing: A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers.... Agent: Eschweiler & Associates LLC

20090004879 - Test structure formation in semiconductor processing: Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another... Agent: Eschweiler & Associates LLC

20090004881 - Hybrid high-k gate dielectric film: The present invention discloses a method of forming a gate dielectric film including: providing a channel region in a transistor, the channel region including multiple segments having different sizes, some of which belong to a first surface portion while others belong to a second surface portion wherein the first surface... Agent: Intel Corporation C/o Intellevate, LLC

20090004882 - Method of forming high-k dual dielectric stack: The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer... Agent: Intel Corporation C/o Intellevate, LLC

20090004883 - Methods of fabricating oxide layers on silicon carbide layers utilizing atomic oxygen: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C.,... Agent: Myers Bigel Sibley & Sajovec

20090004884 - Oxidizing method and oxidizing apparatus: An oxidizing method and oxidizing apparatus in which a plasma generating chamber having an oxidizing gas supply port and a substrate processing chamber having an exhaust port and internally having a substrate susceptor are connected via a partition having a number of through holes, a plasma of an oxidizing gas... Agent: Buchanan, Ingersoll & Rooney PC

20090004885 - Method for fabricating semiconductor device: According to the present invention, when etching is progressed to an A-A line, a part of a BPSG film 14 is exposed from an SOG film 16. A point at which the part of the BPSG film 14 is exposed is an “exposure start point”. A change of a plasma... Agent: Rabin & Berdo, PC

20090004886 - Method of manufacturing an insulating film containing hafnium: A stacked film has an insulating film containing hafnium formed above a silicon layer and a polysilicon layer formed on the insulating film. The stacked film is heated in an atmosphere containing oxygen and nitrogen and having the total pressure approximately equal to a partial pressure of the nitrogen.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090004887 - Apparatus and method for deposition of protective film for organic electroluminescence: In a film deposition apparatus which deposition a film through SWP-CVD, a substrate holder on which a substrate is to be placed is provided with cooling means, thereby inhibiting occurrence of an increase in the temperature of the substrate, which would otherwise be caused during deposition of a film. A... Agent: Rankin, Hill & Clark LLP