Semiconductor device manufacturing: process inventions 12/08

20080318343 - Wafer reclaim method based on wafer type: A method for reclaiming a wafer is described. Embodiments of the invention describe a method in which an analytical measurement of a wafer surface is performed in order to determine a wafer type of the wafer. In an embodiment an XRF measurement is performed to determine the composition of a... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20080318344 - Indication of the end-point reaction between xef2 and molybdenum: Embodiments of the present invention relate to methods and systems for making a microelectromechanical system comprising supplying an etchant to etch one or more sacrificial structures of the system.... Agent: Knobbe, Martens, Olson & Bear, LLP

20080318346 - Manufacturing method for semiconductor integrated device: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral... Agent: Miles & Stockbridge PC

20080318345 - Plasma ion implantation process control using reflectometry: An approach that determines an ion implantation processing characteristic in a plasma ion implantation of a substrate is described. In one embodiment, there is a light source configured to direct radiation onto the substrate. A detector is configured to measure radiation reflected from the substrate. A processor is configured to... Agent: Scott Faber, Esq. Varian Semiconductor Equipment Associates, Inc

20080318347 - Manufacturing method of semiconductor device: In the semiconductor device manufacturing method of the present invention, first, the emissivity of a wafer placed in a chamber is measured. Then, the fluctuation rate of a wafer physical quantity that fluctuates in association with the given thermal energy is calculated based on an estimate expression, which are obtained... Agent: Mcdermott Will & Emery LLP

20080318348 - Method of constructing a stacked-die semiconductor structure: In constructing a multi-die semiconductor device, a plurality of semiconductor die are provided. Each die is probe tested when it is part of a wafer. Flat contacts are connected to each die when it is part of a wafer. After wafer sawing, each die is tested in a test socket,... Agent: Paul J. Winters

20080318349 - Wafer level hermetic bond using metal alloy: Systems and methods for forming an encapsulated MEMS device include a hermetic seal which seals an insulating gas between two substrates, one of which supports the MEMS device. The hermetic seal may be formed by heating at least two metal materials, in order to melt at least one of the... Agent: Jaquelin K. Spong

20080318350 - Apparatus for improving incoming and outgoing wafer inspection productivity in a wafer reclaim factory: An apparatus and method for inspecting wafers at a reclaim factory is described. Embodiments of the invention describe an apparatus in which a wafer ID and wafer thickness may be simultaneously measured. A wafer is placed onto a sloped surface and positioned by aligning a notch in the wafer with... Agent: Michael A. Bernadicou Blakely, Sokoloff, Taylor & Zafman LLP

20080318351 - Method of setting recipes of a defect test: In a method of setting recipes of a defect test, a laser intensity map of a sample is obtained. The laser intensity map is then area-scanned to obtain average laser intensity. Recipes are set based on the average laser intensity. Thus, a laser power set in a defect detector may... Agent: Marger Johnson & Mccollom, P.C.

20080318352 - Method of bonding mems integrated circuits: A method of bonding an integrated circuit to a substrate is provided. The integrated circuit is one of a plurality of integrated circuits, each having a respective frontside releasably attached to a film frame tape supported by a wafer film frame. The method comprises the steps of: (a) positioning a... Agent: Silverbrook Research Pty Ltd

20080318353 - Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers: Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed herein. In one embodiment, the imager assembly can include a workpiece with a substrate having a front side, a back side, and a plurality of imaging dies on and/or in the... Agent: Dickstein Shapiro LLP

20080318354 - Method of fabricating thin film transistor and method of fabricating liquid crystal display: A method of fabricating a thin film transistor is provided. First, a patterned dielectric layer is formed over a substrate. A metallic layer is formed over the substrate to cover the patterned dielectric layer. Thereafter, the metallic layer is planarized until the patterned dielectric layer is exposed. The remained metallic... Agent: J C Patents, Inc.

20080318355 - Semiconductor light-emitting element and method of producing the same: There is provided a semiconductor light-emitting element and a method of producing the same including high density and high quality quantum dots emitting light at a wavelength of 1.3 μm. A semiconductor light-emitting element has a first GaAs layer, a second InAs thin film layer having the plurality of InAs... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080318356 - Semiconductor apparatus and method for manufacturing the same: It is made possible to provide a highly integrated, thin apparatus can be obtained, even if the apparatus contains MEMS devices and semiconductor devices. A semiconductor apparatus includes: a first chip comprising a MEMS device formed therein; a second chip comprising a semiconductor device formed therein; and an adhesive layer... Agent: Amin, Turocy & Calvin, LLP

20080318357 - Alpha voltaic batteries and methods thereof: An alpha voltaic battery includes at least one layer of a semiconductor material comprising at least one p/n junction, at least one absorption and conversion layer on the at least one layer of semiconductor layer, and at least one alpha particle emitter. The absorption and conversion layer prevents at least... Agent: Nixon Peabody LLP - Patent Group

20080318358 - Image sensor pixel having photodiode with indium pinning layer: An active pixel using a pinned photodiode with a pinning layer formed from indium is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N− region formed within a P-type region. A pinning layer formed from indium is then formed at the surface of... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080318359 - Method of manufacturing silicon carbide semiconductor substrate: A method of manufacturing a silicon carbide semiconductor substrate is disclosed in which the density of basal plane dislocations (BPDs) in particular is reduced in an SiC crystal substrate. Irregularities in the surface of the substrate due to this reduction also can be flattened. A method of manufacturing a silicon... Agent: Rossi, Kimms & Mcdowell LLP.

20080318360 - Device and method for fabricating double-sided soi wafer scale package with optical through via connections: A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080318361 - Method for manufacturing semiconductor package: A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the... Agent: Ladas & Parry LLP

20080318362 - Manufacturing method of semiconductor integrated circuit device: After performing rough grinding to the back surface of a semiconductor wafer using the first grinding material (for example, particle size of polish fine powder from #320 to #360) and making the thickness of the semiconductor wafer, for example less than 140 □m, less than 120 □m, or less than... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080318363 - Stack circuit member and method: A stack circuit member may include a first circuit member and a second circuit member. The first and the second circuit members may be electrically and mechanically connected together using a thermocompression bonding method. A photosensitive polymer layer may be interposed between the first circuit member and the second circuit... Agent: Harness, Dickey & Pierce, P.L.C

20080318364 - Process applying die attach film to singulated die: Methods and systems of applying a plurality of pieces of die attach film to a plurality of singulated dice are provided. The method can involve making intervals between rows and columns of a plurality of pieces of die attach film. The interval can be made by expanding an underlaid expandable... Agent: Amin, Turocy & Calvin, LLP

20080318365 - Formation of alpha particle shields in chip packaging: A structure fabrication method. First, an integrated circuit including N chip electric pads is provided electrically connected to a plurality of devices on the integrated circuit. Then, an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield is provided being... Agent: Schmeiser, Olsen & Watts

20080318366 - Method for producing a support for the growth of localised elongated nanostructures: s

20080318367 - Method of manufacturing semiconductor device: To suppress an effect of metal contamination caused in manufacturing an SOI substrate. After forming a damaged region by irradiating a semiconductor substrate with hydrogen ions, the semiconductor substrate is bonded to a base substrate. Heat treatment is performed to cleave the semiconductor substrate; thus an SOI substrate is manufactured.... Agent: Fish & Richardson P.C.

20080318368 - Method of manufacturing zno-based this film transistor: Provided is a method of manufacturing a ZnO-based thin film transistor (TFT). The method may include forming source and drain electrodes using one or two wet etchings. A tin (Sn) oxide, a fluoride, or a chloride having relatively stable bonding energy against plasma may be included in a channel layer.... Agent: Harness, Dickey & Pierce, P.L.C

20080318369 - Soi device with charging protection and methods of making same: The present invention is directed to an SOI device with charging protection and methods of making same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated... Agent: Williams, Morgan & Amerson

20080318370 - Semiconductor integrated circuit switch matrix: There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080318372 - Manufacturing method of high-linearity and high-power cmos structure: This invention relates to a method for making a high-linearity and high-power CMOS structure and particularly to a field plate technology that is applied to a CMOS component, in which the field plate is formed on a dielectric layer of the CMOS, being arranged above a gate and a drain.... Agent: Nikolai & Mersereau, P.A.

20080318371 - Semiconductor device and method of forming the same: A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate... Agent: North America Intellectual Property Corporation

20080318373 - Method of fabricating self-aligned bipolar transistor having tapered collector: A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface.... Agent: International Business Machines Corporation Dept. 18g

20080318374 - Metal gated ultra short mosfet devices: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer... Agent: Innovation Interface, LLC

20080318375 - Method of fabricating a duel-gate fet: The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080318376 - Semiconductor device manufactured using a method to improve gate doping while maintaining good gate profile: In one aspect, there is provided a method of manufacturing a semiconductor device. This method includes forming gate structures over a substrate, wherein the gate structures include gate electrodes located adjacent source/drain regions. A protective layer is formed over the gate structures and a CMP layer is formed over the... Agent: Texas Instruments Incorporated

20080318377 - Method of forming self-aligned gates and transistors: Method for fabricating a self-aligned gate of a transistor including: forming a plurality of deep trench capacitors in a substrate, concurrently forming a surface strap and a contact pad on a surface of the substrate, wherein a spacing between the surface strap and the contact pad exposes a portion of... Agent: North America Intellectual Property Corporation

20080318378 - Mim capacitors with improved reliability: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top... Agent: Slater & Matsil, L.L.P.

20080318379 - Method for fabricating non-volatile storage with individually controllable shield plates between storage elements: A method for fabricating non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between... Agent: Vierra Magen/sandisk Corporation

20080318380 - Dual-gate device and method: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor... Agent: Macpherson Kwok Chen & Heid LLP

20080318382 - Methods for fabricating tunneling oxide layer and flash memory device: A method for manufacturing a tunneling oxide layer including the following steps: forming a tunneling oxide layer on a semiconductor substrate by in-situ steam generation oxidation; performing a annealing on the tunneling oxide layer. There is also provided a method for manufacturing a flash memory device. According to the invention,... Agent: Squire, Sanders & Dempsey L.L.P.

20080318381 - Methods of forming high density semiconductor devices using recursive spacer technique: High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to... Agent: Vierra Magen/sandisk Corporation

20080318383 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, including: preparing a semiconductor substrate having an element-isolating film filled in the first trench and an active region; forming a mask-forming film over the semiconductor substrate; forming a first mask having an opening traversing the active region; performing anisotropic etching using the first... Agent: Sughrue Mion, PLLC

20080318384 - Method of forming quantum wire gate device: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride... Agent: Intel Corporation C/o Intellevate, LLC

20080318385 - Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further comprises a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080318386 - Metal oxide semiconductor field effect transistor and method of fabricating the same: There are provided a MOSFET and a method for fabricating the same. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration impurities over the germanium layer, a gate structure on the epitaxial layer,... Agent: Yong Soo Cho

20080318387 - Activation of cmos source/drain extensions by ultra-high temperature anneals: A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer... Agent: Texas Instruments Incorporated

20080318388 - Method for fabricating mos transistor with recess channel: A method for fabricating a MOS transistor with a recess channel, including: providing a substrate with a plurality of trench capacitors therein, wherein a trench top oxide is positioned on top of each trench capacitor and extended away from the substrate surface; forming a first spacer on side walls of... Agent: North America Intellectual Property Corporation

20080318389 - Method of forming alignment key of semiconductor device: The formation of an alignment key for overlay measurement of a semiconductor device formed by sequentially forming an inter-metal dielectric layer and a capping layer over a semiconductor substrate, and patterning the inter-metal dielectric layer and a capping layer at an alignment key region to thereby form an alignment key... Agent: Sherr & Vaughn, PLLC

20080318390 - Method for fabricating semiconductor device and semiconductor device: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first... Agent: Nixon & Vanderhye, PC

20080318391 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device that may include steps of forming a pad oxide layer and an insulating layer on a semiconductor substrate; and then performing a first etching process on the semiconductor device to form an insulating layer pattern exposing a portion of the pad oxide layer... Agent: Sherr & Vaughn, PLLC

20080318392 - Shallow trench isolation structure and method for forming the same: A method for forming shallow trench isolation structures is provided. The method comprises the following steps: providing a substrate with a “v” shaped trench, forming a first dielectric layer to cover the upper portion of the inner wall of the trench; conducting the first etching process to pull back the... Agent: Holland & Knight LLP

20080318393 - Method for manufacturing semiconductor device: There is provided a method for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor provided on a same semiconductor substrate. The method includes forming a first gate electrode of the high breakdown voltage transistor and a second gate electrode of the low... Agent: Harness, Dickey & Pierce, P.L.C

20080318394 - Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device: A single crystal semiconductor layer is formed over a substrate having an insulating surface by the following steps: forming an ion doped layer at a given depth from a surface of a single crystal semiconductor substrate; performing plasma treatment to the surface of the single crystal semiconductor substrate; forming an... Agent: Eric Robinson

20080318396 - Grooving bumped wafer pre-underfill system: A method of forming a semiconductor device includes providing a bumped wafer. A plurality of grooves is formed in an active surface of the bumped wafer. A pre-underfill layer is disposed over the active surface, filling the plurality of grooves. A first adhesive layer is mounted to the pre-underfill layer,... Agent: Quarles & Brady LLP

20080318395 - Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces: Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart from an X-ray detector. The X-ray source can emit a... Agent: Perkins Coie LLP Patent-sea

20080318397 - Junction diode with reduced reverse current: A method for annealing a diode formed of a silicon-germanium alloy that minimizes leakage current is disclosed. The method includes the steps of forming semiconductor pillars of an alloy of silicon and germanium; heating the pillars at a first temperature for at least 30 minutes, and then heating the pillars... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20080318398 - Method for manufacturing crystalline semiconductor film and semiconductor device: There is provided a method for manufacturing a crystalline semiconductor film. An insulating film is formed over a substrate; an amorphous semiconductor film is formed over the insulating film; a cap film is formed over the amorphous semiconductor film; the amorphous semiconductor film is scanned and irradiated with a continuous... Agent: Nixon Peabody, LLP

20080318399 - Plasma doping method: It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a dose of boron is made substantially uniform, and the saturation time is comparatively long and ease to stably use, compared with a time at which... Agent: Mcdermott Will & Emery LLP

20080318400 - Method for manufacturing sic semiconductor device: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap... Agent: Posz Law Group, PLC

20080318401 - Power semiconductor device for suppressing substrate recirculation current and method of fabricating power semiconductor device: A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a first conductive type and... Agent: Sidley Austin LLP

20080318402 - Semiconductor device having a recess channel and method for fabricating the same: Provided is a semiconductor device having recess channel, comprising a semiconductor substrate having first and second trenches disposed to cross each other on both sides of an active region among adjoining regions between an active region and element-isolation films; a gate insulation film disposed on the semiconductor substrate of the... Agent: Marshall, Gerstein & Borun LLP

20080318403 - Method for fabricating semiconductor transistor: A method for fabricating a semiconductor transistor which eliminates device defects generated during an etching process for forming gates. The method may include laminating an ONO layer on and/or over a semiconductor substrate, and then coating a polysilicon layer on and/or over the ONO layer, and then forming a photoresist... Agent: Sherr & Vaughn, PLLC

20080318405 - Method of fabricating gate structure: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to... Agent: Jianq Chyun Intellectual Property Office

20080318404 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080318406 - Split gate type nonvolatile memory device and method of fabricating the same: In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible... Agent: Mills & Onello LLP

20080318407 - Method for forming storage electrode of semiconductor memory device: In order to form a storage electrode of a semiconductor memory device, an interlayer dielectric layer is formed on a semiconductor substrate having a bit line thereon. A contact hole exposing the semiconductor substrate is formed by patterning the interlayer dielectric layer. A polysilicon layer is etched to a predetermined... Agent: Marshall, Gerstein & Borun LLP

20080318408 - Method of manufacturing semiconductor device: Disclosed is a method of manufacturing a semiconductor device which includes: providing an insulating film formed above a semiconductor substrate with a processed portion; supplying a surface of the processed portion of the insulating film with a primary reactant from a reaction of a raw material including at least a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080318409 - Method for manufacturing a semiconductor device and method for etching the same: A method for manufacturing a dual damascene structure includes forming a wiring layer over a substrate, forming an inorganic insulating film over the wiring layer, forming a via hole in the inorganic insulating film using a first resist pattern with an opening as an etching mask, removing the first resist... Agent: Volentine & Whitt PLLC

20080318410 - Method of forming metal electrode of system in package: A method for forming a metal electrode of a system in package of a system in package including a multilayer semiconductor device having semiconductor devices stacked in a plurality of layers. The method may include forming a through hole extending through the plurality of layers, forming a combustible material layer... Agent: Sherr & Vaughn, PLLC

20080318412 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device has forming an interlayer insulating film over a wiring layer, forming an opening in the interlayer insulating film, performing a first plasma treatment using a gas including hydrogen or ammonia, performing a second plasma treatment with a gas including fluorocarbon after the first... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080318411 - Method of manufacturing semiconductor device: In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is used to form a wiring groove 111, allowing the shape of the wiring groove 111 to be stabilized. Furthermore,... Agent: Steptoe & Johnson LLP

20080318415 - Interconnect structures with encasing cap and methods of making thereof: A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.... Agent: Connolly Bove Lodge & Hutz LLP Suite 1100

20080318413 - Method for making an interconnect structure and interconnect component recovery process: A method is provided for making an interconnect structure. The method includes applying a removable layer to an electronic device or to a base insulative layer; applying an adhesive layer to the electronic device or to the base insulative layer; and securing the electronic device to the base insulative layer... Agent: General Electric Company Global Research

20080318414 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device according to embodiments includes forming an interlayer dielectric film with a damascene pattern over a semiconductor substrate having a lower metal wire. A seed layer may be formed over the interlayer dielectric film including the damascene pattern. Impurities generated during the formation of... Agent: Sherr & Vaughn, PLLC

20080318416 - Method of improving interconnection between aluminum and copper in semiconductor metal line process: A method for enhancing an aluminum-copper interconnection in a semiconductor metal line process. In order to solve a reduction in wafer yield due to copper segregation resulting from a time delay during a metal deposition process, copper precipitates are re-solidified into the aluminum film through a quench process of performing... Agent: Sherr & Vaughn, PLLC

20080318417 - Method of forming ruthenium film for metal wiring structure: A method of depositing a ruthenium(Ru) thin film on a substrate in a reaction chamber, includes: (i) supplying a gas of a ruthenium precursor into the reaction chamber so that the gas of the ruthenium precursor is adsorbed onto the substrate, wherein the ruthenium precursor a ruthenium complex contains a... Agent: Knobbe Martens Olson & Bear LLP

20080318418 - Process for forming continuous copper thin films via vapor deposition: A process for preparing a multi-layer substrate is described herein. In one embodiment, the process provides a multi-layer substrate comprising a first layer and a second layer where the process comprises the steps of providing the first layer comprising a barrier area and a copper area; and depositing the second... Agent: Air Products And Chemicals, Inc. Patent Department

20080318419 - Charge dissipation of cavities: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.... Agent: Mueting, Raasch & Gebhardt, P.A.

20080318421 - Methods of forming films of a semiconductor device: There is provided a method of forming a film of a semiconductor device. The method includes a step of adsorbing a liquefied metal ion source on the substrate; rinsing the substrate to remove any liquefied metal ion source that is not adsorbed to the substrate; depositing a metal layer on... Agent: Myers Bigel Sibley & Sajovec

20080318420 - Two step chemical mechanical polish: In one embodiment, a method includes providing two structures with a spacing therebetween over a semiconductor substrate, providing a conformal first layer over the two structures and within the space therebetween, depositing a conformal protective layer over the first layer, planarizing the protective layer until a top surface of the... Agent: Macpherson Kwok Chen & Heid LLP

20080318422 - Method of manufacturing semiconductor device: An aluminum gallium nitride/gallium nitride layer (III-V nitride semiconductor layer) is formed on the surface of a silicone carbide substrate. The aluminum gallium nitride/gallium nitride layer is dry-etched from an exposed surface, using a chlorine-based gas (first gas) and a surface via hole is thereby formed. A back via hole,... Agent: Leydig Voit & Mayer, Ltd

20080318423 - Process for producing metal oxide films at low temperatures: A process for producing metal oxide thin films on a substrate by the ALD method comprises the steps of bonding no more than about a molecular monolayer of a gaseous metal compound to a growth substrate, and converting the bonded metal compound to metal oxide. The bonded metal compound is... Agent: Knobbe Martens Olson & Bear LLP

20080318424 - Photoresist residue remover composition and semiconductor circuit element production process employing the same: A photoresist residue remover composition is provided that removes a photoresist residue formed by a resist ashing treatment after dry etching in a step of forming, on a substrate surface, wiring of any metal of aluminum, copper, tungsten, and an alloy having any of these metals as a main component,... Agent: L.c. Begin & Associates, PLLC

20080318425 - Semiconductor device production method: The purpose of the present invention is to stabilize the polishing film thickness during the overpolishing following the removal of barrier metal in Cu-CMP (chemical mechanical polishing). To this end, a table in which the relationship between wire perimeter and overpolishing process polishing rate is created. The polishing time is... Agent: Mcdermott Will & Emery LLP

20080318426 - Wafer recycling method: A wafer recycling method comprises varying a temperature and pressure conditions to remove a first semiconductor layer deposited on a wafer, removing a remaining semiconductor layer on the wafer through a chemical or physical process, and washing the wafer.... Agent: Birch Stewart Kolasch & Birch

20080318427 - Chemical mechanical polishing aqueous dispersion preparation set, method of preparing chemical mechanical polishing aqueous dispersion, chemical mechanical polishing aqueous dispersion, and chemical mechanical polishing method: A chemical mechanical polishing aqueous dispersion preparation set including: a first composition which includes colloidal silica having an average primary particle diameter of 15 to 40 nm and a basic compound and has a pH of 8.0 to 11.0; and a second composition which includes poly(meth)acrylic acid and an organic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080318428 - Method for achieving uniform chemical mechanical polishing in integrated circuit manufacturing: A method for planarizing a surface in an integrated circuit manufacturing process provides a first film of a first material over a non-uniform surface, such as a surface including isolation trenches. The first material includes, for example, a polysilicon layer to be used to form floating gates in a non-volatile... Agent: Macpherson Kwok Chen & Heid LLP

20080318429 - Fabrication method of semiconductor integrated circuit device: An object of the present invention is to provide a fabrication method of a semiconductor integrated circuit device capable of improving the throughput, reducing the cost of a cleaning gas and prolonging the life of a process kit by automatically detecting the end point of cleaning in a chamber. A... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080318430 - Method for manufacturing semiconductor device having porous low dielectric constant layer formed for insulation between metal lines: The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers.... Agent: Ladas & Parry LLP

20080318431 - Shower plate and plasma treatment apparatus using shower plate: A shower plate for plasma processing, which is formed by a plurality of pipes. A pipe includes a porous material member disposed along the pipe, which has a predetermined porosity with respect to a material gas, and which has an outwardly convex shape, and a metal member faced to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080318433 - Plasma confinement rings assemblies having reduced polymer deposition characteristics: Plasma confinement ring assemblies are provided that include confinement rings adapted to reach sufficiently high temperatures on plasma-exposed surfaces of the rings to avoid polymer deposition on those surfaces. The plasma confinement rings include thermal chokes adapted to localize heating at selected portions of the rings that include the plasma... Agent: Buchanan, Ingersoll & Rooney PC

20080318432 - Reactor with heated and textured electrodes and surfaces: A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing.... Agent: Fliesler Meyer LLP

20080318435 - Composition for etching a metal hard mask material in semiconductor processing: An etching solution for a metal hard mask. The etching solution comprises a mixture of a dilute HF (hydrofluoric acid) and a silicon containing precursor. The etching solution also comprises a surfactant agent, a carboxylic acid, and a copper corrosion inhibitor. The etching solution is selectively toward etching the metal... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080318434 - Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries: Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment includes sequentially exposing a portion of a semiconductor workpiece surface to a first chemistry having a first chemical composition and a second chemistry having a second chemical composition... Agent: Perkins Coie LLP Patent-sea

20080318436 - Antireflective coating material: Antireflective coatings comprising (i) a silsesquioxane resin having the formula (PhSiO (3-x)/2 (OH) x) mHSiO (3-x)/2 (OH) x) n (MeSiO (3-x)/2 (OH) x) p where Ph is a phenyl group, Me is a methyl group, x has a value of 0, 1 or 2; m has a value of 0.01... Agent: Dow Corning Corporation Co1232

20080318437 - Method for manufacturing semiconductor device utilizing low dielectric layer filling gaps between metal lines: A semiconductor device is manufactured by forming a low dielectric constant layer on a semiconductor substrate which is formed with metal lines; implementing primary ultraviolet treatment of the low dielectric constant layer; forming a capping layer on the low dielectric constant layer having undergone the primary ultraviolet treatment; and implementing... Agent: Ladas & Parry LLP

20080318438 - Method for manufacturing sic semiconductor device: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap... Agent: Posz Law Group, PLC

20080318439 - Method of manufacturing semiconductor device: A semiconductor wafer is placed in a chamber of a film-deposition apparatus, and gas in the chamber is exhausted from a gas exhaust outlet. Then, with interrupting the exhaust, an inert gas is introduced into the chamber so that the chamber has a pressure of 133 Pa or higher and... Agent: Miles & Stockbridge PC

20080318440 - Porous organosilicate layers, and vapor deposition systems and methods for preparing same: The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous organosilicate layers are useful, for example, as masks.... Agent: Mueting, Raasch & Gebhardt, P.A.

20080318441 - Process sequence for doped silicon fill of deep trenches: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080318443 - Plasma enhanced cyclic deposition method of metal silicon nitride film: The present invention relates to a method for forming a metal silicon nitride film according to a cyclic film deposition under plasma atmosphere with a metal amide, a silicon precursor, and a nitrogen source gas as precursors. The deposition method for forming a metal silicon nitride film on a substrate... Agent: Air Products And Chemicals, Inc. Patent Department

20080318442 - Semiconductor device manufacturing method and substrate processing apparatus: A semiconductor device manufacturing method comprises the steps of: forming a metal oxide film on a silicon substrate, and forming a silicate film by inducing a solid phase reaction between the metal oxide film and the silicon substrate by heat treatment, and forming a high dielectric constant insulating film on... Agent: Kratz, Quintos & Hanson, LLP

20080311682 - Microwave integrated circuit package and method for forming such package: A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20080311683 - Semiconductor device manufacturing method: A method of manufacturing a semiconductor device including forming a lower electrode over a substrate, increasing the temperature of the substrate with the lower electrode to a predetermined temperature under mixture gas atmosphere of inert gas and oxygen gas, forming a dielectric film on the lower electrode by using an... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080311685 - Methods relating to the reconstruction of semiconductor wafers for wafer level processing: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface... Agent: Trask Britt, P.C./ Micron Technology

20080311684 - Programmable chip enable and chip address in semiconductor memory: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled... Agent: Vierra Magen/sandisk Corporation

20080311686 - Method of forming semiconductor layers on handle substrates: A method of making a semiconductor thin film bonded to a handle substrate includes implanting a semiconductor substrate with a light ion species while cooling the semiconductor substrate, bonding the implanted semiconductor substrate to the handle substrate to form a bonded structure, and annealing the bonded structure, such that the... Agent: Hiscock & Barclay, LLP

20080311687 - Method and apparatus for optimizing a gate channel: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.... Agent: Tokyo Electron U.s. Holdings, Inc.

20080311688 - Method and apparatus for creating a gate optimization evaluation library: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.... Agent: Tokyo Electron U.s. Holdings, Inc.

20080311689 - Securing a transistor outline can within an optical component: The present invention relates to affixing components of optical packages. The optical packages can include an optical component, such as a TO-Can. The TO-Can can house an optical transmitter and/or an optical receiver. Another optical component of the optical package can be a barrel for aligning the TO-Can with an... Agent: Workman Nydegger

20080311690 - Eliminate release etch attack by interface modification in sacrificial layers: Methods of making a microelectromechanical system (MEMS) device are described. In some embodiments, the method includes forming a sacrificial layer over a substrate, treating at least a portion of the sacrificial layer to form a treated sacrificial portion, forming an overlying layer over at least a part of the treated... Agent: Knobbe, Martens, Olson & Bear, LLP

20080311691 - Method of manufacturing image sensor: Provided is a method of manufacturing an image sensor. A microlens of inorganic material can be formed on a substrate by forming a seed microlens having a top surface with height differences, and then blanket etching the seed microlens to form a dome shaped microlens having a curvature following the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080311692 - Top emission organic light emitting diode display using auxiliary electrode to prevent voltage drop of upper electrode and method of fabricating the same: An organic light emitting diode (OLED) display. The OLED display includes: a lower electrode formed on a layer on an insulating substrate having a thin film transistor. The lower electrode is electrically connected to the thin film transistor. An auxiliary electrode is formed on the same layer as the lower... Agent: Christie, Parker & Hale, LLP

20080311694 - Method for manufacturing semiconductor optical device: An SiO2 film is formed on a semiconductor layer stack, the SiO2 film having a thickness da and an etch rate Ra in buffered (BHF). A waveguide ridge with the SiO2 film thereon is formed using a resist pattern 76. An SiN film is formed on top and both sides... Agent: Leydig Voit & Mayer, Ltd

20080311693 - Method of aligning optical components with waveguides: A method of fabricating a photonic device comprises the steps of providing a core pattern of waveguide core material (1) on a base layer (3) and applying a cladding layer (2) over the core material 1 and the base layer (3). The height of the surface of the cladding layer... Agent: Renner Otto Boisselle & Sklar, LLP

20080311695 - Method of producing nitride semiconductor light-emitting device: In a method of producing a nitride semiconductor light-emitting device including a nitride semiconductor active layer (105) held between an n-type nitride semiconductor layer (103, 104) and a p-type nitride semiconductor layer (106 to 108) on a substrate (101), at least any one of the n-type layer, the active layer... Agent: Harness, Dickey & Pierce, P.L.C

20080311696 - Manufacturing prpcess for photodetector: A manufacturing process for a photo-detector is provided. The present manufacturing process for a photo-detector comprises the steps of: (a) providing a thin-film Ge on a cheap substrate including a first processing area and a second processing area; (b) performing a defect-reduction processing to at least one of the first... Agent: Haverstock & Owens LLP

20080311697 - Method for simultaneous recrystallization and doping of semiconductor layers and semiconductor layer systems produced according to this method: The invention relates to a method for simultaneous recrystallisation and doping of semiconductor layers, in particular for the production of crystalline silicon thin layer solar cells. In this method, in a first step a substrate base layer 1 is produced, in a step subsequent thereto, on the latter an intermediate... Agent: Indianapolis Office 27879 Brinks Hofer Gilson & Lione

20080311698 - Fabrication of self-aligned via holes in polymer thin films: A low-cost and efficient process produces self-aligned vias in dielectric polymer films that provides electrical connection between a top conductor and a bottom conductor. The process is achieved by printing conductive posts on the first patterned conductive layer, followed by the deposition of an unpatterned layer dielectric, followed by the... Agent: Weyerhaeuser Company Intellectual Property Dept., Ch 1j27

20080311699 - Phase-change memory and fabrication method thereof: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are... Agent: Quintero Law Office, PC

20080311700 - Plastic overmolded packages with mechancially decoupled lid attach attachment: The specification describes a lidded MCM IC plastic overmolded package with a chimney-type heat sink. The lid is mechanically decoupled from the chimneys by a compliant conductive polymer plug.... Agent: Lsi Corp

20080311701 - Method for fabricating semiconductor package: A method for fabricating a semiconductor package includes the steps of: forming a material layer containing conductive particles on a semiconductor chip having a plurality of bonding pads on the upper surface thereof, baking the material layers to a non-flowing state; attaching the semiconductor chip in a face down manner... Agent: Ladas & Parry LLP

20080311702 - Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area... Agent: Trask Britt, P.C./ Micron Technology

20080311703 - Lead frame and a method of manufacturing the same: A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080311704 - Radio frequency identification (rfid) tag lamination process using liner: A method of constructing an RFID unit can include using a protective layer to hold an integrated circuit chip module to a substrate layer with an antenna unit while a conductive adhesive has not yet fully set.... Agent: Fliesler Meyer LLP

20080311705 - Lead frame and method for fabricating semiconductor package employing the same: A lead frame and a method of fabricating a semiconductor package including the lead frame, where the lead frame includes a die pad, a tie bar supporting the die pad, and a plurality of leads. The leads may include inner and outer leads arranged along an outer periphery of the... Agent: Harness, Dickey & Pierce, P.L.C

20080311706 - Method for manufacturing semiconductor device: To provide a method for manufacturing a highly-reliable semiconductor device, which is not damaged by external local pressure, with a high yield, a semiconductor device is manufactured by forming an element substrate having a semiconductor element formed using a single-crystal semiconductor substrate or an SOI substrate, providing the element substrate... Agent: Eric Robinson

20080311707 - Process for producing a functional device-mounted module: The present disclosure provides an optical functional device-mounted module which needs no expensive or special members, can be reduced in size, and provide a producing process thereof. A bank to dam a liquid sealing resin is provided on a substrate around an optical functional device, the substrate being formed with... Agent: Oliff & Berridge, PLC

20080311708 - Hybrid strained orientated substrates and devices: A method for forming a semiconductor structure. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor... Agent: Schmeiser, Olsen & Watts

20080311709 - Method for manufacturing semiconductor device: A highly responsive semiconductor device in which the subthreshold swing (S value) is small and reduction in on-current is suppressed is manufactured. A semiconductor layer in which a thickness of a source region or a drain region is larger than that of a channel formation region is formed. A semiconductor... Agent: Nixon Peabody, LLP

20080311710 - Method to form low-defect polycrystalline semiconductor material for use in a transistor: A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20080311711 - Gapfill for metal contacts: A method of making a semiconductor interconnect is disclosed. A semiconductor body on which a transistor comprising a doped region is formed is provided. A dielectric region is formed over the doped region, and a contact hole is formed in the dielectric to expose the doped region. The contact hole... Agent: Slater & Matsil LLP

20080311712 - Insulated gate silicon nanowire transistor and method of manufacture: An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate and includes at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches. A first nanowire... Agent: Department Of The Air Force

20080311713 - Mobility enhancement by strained channel cmosfet with single workfunction metal-gate and fabrication method thereof: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively.... Agent: Quintero Law Office, PC

20080311714 - Semiconductor structure and method of manufacture: A complimentary metal oxide semiconductor and a method of manufacturing the same using a self-aligning process to form one of the stacks of device. The method includes depositing an oxide layer over a portion of a metal layer over an nFET region of a CMOS structure and etching the metal... Agent: Greenblum & Bernstein, P.L.C

20080311715 - Method for forming semiconductor device: A method for forming a semiconductor device is disclosed. A substrate comprising trenches are provided. Dopants are doped into a region of the substrate neighboring a sidewall of the trenches by using an isotropic doping method. A gate dielectric layer is formed on the sidewall of the substrate. A gate... Agent: Birch Stewart Kolasch & Birch

20080311716 - Methods for forming field effect transistors and epi-substrate: A semiconductor method includes thermally treating at least a portion of a substrate so as to generate a plurality of vacancies in a region at a depth substantially near to a surface of the substrate. The substrate is then quenched so as to substantially maintain the vacancies in the region... Agent: Duane Morris LLP (tsmc)IPDepartment

20080311717 - Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along... Agent: Ronald J. Meetin, Attorney At Law

20080311718 - Manufacturing method of semiconductor device: The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film on a titanium film and thus having a film stack structure and a metal film filled, via the barrier metal film, in a connecting... Agent: Miles & Stockbridge PC

20080311719 - Method of forming a field effect transistor: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than... Agent: Sanh D. Tang

20080311720 - Short channel effect of mos devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions: A method of forming a transistor comprising: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the... Agent: Intel Corporation C/o Intellevate, LLC

20080311721 - Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source/drain and semiconductor device manufactured by the method: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080311722 - Method for forming polycrystalline thin film bipolar transistors: A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The... Agent: Dugan & Dugan, PC

20080311723 - Tunable semiconductor diodes: A diode structure fabrication method. In a P− substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is formed. Then, a P+ region is formed to serve as an anode... Agent: Schmeiser, Olsen & Watts

20080311724 - Tfd lcd panel: Active devices in a thin film diode (TFD) liquid crystal display (LCD) panel used to control liquid crystal are formed by a metal layer, a transparent conductive layer, and an insulating layer sequentially on a substrate, wherein the metal layer is used as transmitting signal and the transparent conductive layer... Agent: Kusner & Jaffe Highland Place Suite 310

20080311726 - Manufacturing method of soi substrate: There is provided a method of manufacturing an SOI substrate which is practicable even when a supporting substrate having a low allowable temperature limit is used. A separation layer is formed in a region at a certain depth from a surface of a semiconductor substrate, and a first heat treatment... Agent: Eric Robinson

20080311725 - Method for assembling substrates by depositing an oxide or nitride thin bonding layer: A method for assembling by molecular bonding two substrates, at least one of which is made of a semiconductor material characterised in that one of substrates, called a first substrate, includes a surface (A), where at least one portion is flat and provided with an initial surface roughness compatible with... Agent: Brinks Hofer Gilson & Lione

20080311727 - Method of cutting a wafer: In a method of cutting a wafer, a supporting member is attached to an upper surface of the wafer on which semiconductor chips are formed. An opening is formed at a lower surface of the wafer along a scribe lane of the wafer. The lower surface of the wafer may... Agent: Stanzione & Kim, LLP

20080311728 - Method for recovering damage of low dielectric insulating film and method for manufacturing semiconductor device: A damaged functional group generated in a surface of the low dielectric insulating film by a processing is substituted with a hydrophobic functional group (ST. 2). A damaged component present under a dense layer generated in the surface of the low dielectric insulating film by the substitution process is recovered... Agent: Pearne & Gordon LLP

20080311729 - Atmospheric pressure chemical vapor deposition: A process for coating a substrate at atmospheric pressure comprises the steps of vaporizing a controlled mass of semiconductor material at substantially atmospheric pressure within a heated inert gas stream, to create a fluid mixture having a temperature above the condensation temperature of the semiconductor material, directing the fluid mixture... Agent: Fraser Clemens Martin & Miller LLC

20080311730 - Semiconductor device and method of forming gate thereof: A method of forming a gate of a semiconductor device includes providing a semiconductor substrate in which an active region is defined by isolation films, forming a gate insulating film on the active region, forming a capping film on the gate insulating film, and performing an annealing process on the... Agent: Sherr & Vaughn, PLLC

20080311731 - Low pressure chemical vapor deposition of polysilicon on a wafer: Low pressure chemical vapor deposition (LPCVD) of polysilicon on a wafer in a manner that reduces the generation of particles during the deposition process. In one example embodiment, a method of LPCVD of polysilicon on a wafer positioned in a process tube includes various steps. First, introducing a particle inhibitor... Agent: Workman Nydegger

20080311732 - Method for forming non-amorphous, ultra-thin semiconductor devices using sacrificial implantation layer: A method for forming a semiconductor device includes defining a sacrificial layer (108) over a single crystalline substrate (106). The sacrificial layer (108) is implanted with a dopant species in a manner that prevents the single crystalline substrate (106) from becoming substantially amorphized. The sacrificial layer (108) is annealed so... Agent: International Business Machines Corporation Dept. 18g

20080311733 - Method for fabricating semiconductor device with gate line of fine line width: A method for fabricating a semiconductor device including forming a gate insulation layer, a conductive layer for a gate electrode, and an insulation layer for a gate hard mask over a substrate, selectively etching the insulation layer for a gate hard mask and the conductive layer for a gate electrode... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080311734 - Semiconductor storage device and manufacturing method thereof: A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080311735 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming at least one gate pattern over a substrate, forming a first insulation layer over the gate patterns and the substrate, etching the first insulation layer in a peripheral region to form at least one gate pattern spacer in the peripheral region,... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080311736 - Methods of forming ohmic layers through ablation capping layers: A method of forming an ohmic layer for a semiconductor device includes forming a metal layer on a Silicon Carbide (SiC) layer and forming an ablation capping layer on the metal layer. Laser light is impinged through the ablation capping layer to form a metal-SiC material.... Agent: Myers Bigel Sibley & Sajovec

20080311737 - Manufacturing method for semiconductor device containing stacked semiconductor chips: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material... Agent: Fish & Richardson P.C.

20080311738 - Method of forming an interconnect joint: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering... Agent: Intel Corporation C/o Intellevate, LLC

20080311739 - Method of forming a self aligned copper capping layer: A method of forming a capping layer on a copper interconnect line (14). The method comprises providing a layer (20) of Aluminium over the interconnect line (14) and the dielectric layer (10) in which it is embedded. This may be achieved by deposition or chemical exposure. The structure is then... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080311740 - Power composite integrated semiconductor device and manufacturing method thereof: A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of... Agent: Posz Law Group, PLC

20080311741 - Selective w-cvd method and method for forming multi-layered cu electrical interconnection: A substrate provided thereon with an electrical insulating film which carries holes or the like filled with a Cu-containing electrical interconnection film is subjected to a pre-treatment in which the surface of the electrical insulating film and that of the Cu-containing electrical interconnection film are treated at a temperature of... Agent: Arent Fox LLP

20080311742 - Manufacturing method of semiconductor device: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080311743 - Method of fabricating opening and plug: A method of fabricating an opening or plug is provided. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the... Agent: Jianq Chyun Intellectual Property Office

20080311744 - Multilayer hardmask scheme for damage-free dual damascene processing of sicoh dielectrics: Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080311745 - High temperature processing compatible metal gate electrode for pfets and methods for fabrication: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen... Agent: Scully, Scott, Murphy & Presser, P.C.

20080311746 - New metal precursors for semiconductor applications: Methods and compositions for depositing metal films are disclosed herein. In general, the disclosed methods utilize precursor compounds comprising gold, silver, or copper. More specifically, the disclosed precursor compounds utilize pentadienyl ligands coupled to a metal to increase thermal stability. Furthermore, methods of depositing copper, gold, or silver are disclosed... Agent: Air Liquide Intellectual Property

20080311747 - Metal-germanium physical vapor deposition for semiconductor device defect reduction: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, germanium atoms (120) and transition metal atoms (130) to form a metal-germanium alloy layer (140) on a semiconductor substrate (150). The metal-germanium alloy layer... Agent: Texas Instruments Incorporated

20080311748 - Semiconductor integrated circuit, semiconductor device, and manufacturing method of the semiconductor integrated circuit: A chip with increased impact resistance, attractive design and reduced cost, and a manufacturing method thereof are provided. A semiconductor integrated circuit is formed on a large glass substrate, and a part of data of a ROM included therein is determined by an ink jet method or a laser cutting... Agent: Eric Robinson

20080311749 - Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from... Agent: Macpherson Kwok Chen & Heid LLP

20080311750 - Polishing composition for semiconductor wafer and polishing method: The present invention relates to a polishing composition for a semiconductor wafer which is excellent in polishing property, and a polishing method. The polishing composition for a semiconductor wafer comprises colloidal silica consisting of non-spherical silica particles having a ratio of long axis to short axis of 1.5 to 15.... Agent: Edwards Angell Palmer & Dodge LLP

20080311751 - Method for etching a layer on a substrate: A method for etching a layer that is to be removed on a substrate, in which a Si1-xGex layer is the layer to be removed, this layer being removed, at least in areas, in gas phase etching with the aid of an etching gas, in particular ClF3. The etching behavior... Agent: Kenyon & Kenyon LLP

20080311753 - Oxygen sacvd to form sacrifical oxide liners in substrate gaps: A method of forming and removing a sacrificial oxide layer is described. The method includes forming a step on a substrate, where the step has a top and sidewalls. The method may also include forming the sacrificial oxide layer around the step by chemical vapor deposition of molecular oxygen and... Agent: Townsend And Townsend And Crew LLP / Amat

20080311752 - Pore sealing and cleaning porous low dielectric constant structures: A micellar solution is used to seal pores exposed at the bottom and sidewall surfaces of a structure etched in or through a porous low dielectric constant material. The micellar solution is also effective to clean away etch residues from the etched structure.... Agent: Freescale Semiconductor, Inc. Law Department

20080311754 - Low temperature sacvd processes for pattern loading applications: A method of improving pattern loading in a deposition of a silicon oxide film is described. The method may include providing a deposition substrate to a deposition chamber, and adjusting a temperature of the deposition substrate to about 250° C. to about 325° C. An ozone containing gas may be... Agent: Townsend And Townsend And Crew LLP / Amat

20080311756 - Method for fabricating low-k dielectric and cu interconnect: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is... Agent: Slater & Matsil, L.L.P.

20080311755 - Method for treating a dielectric film to reduce damage: A method of treating a dielectric layer on a substrate is described. The method comprises forming the dielectric layer on the substrate, wherein the dielectric layer comprises a dielectric constant value less than the dielectric constant of SiO2. A feature pattern is formed in the dielectric layer using an etching... Agent: Tokyo Electron U.s. Holdings, Inc.

20080311757 - System and method for chemical dry etching system: A system and method for chemical dry etching system. The present invention provides a method for performing an etching process for manufacture of integrated circuits. The method includes providing a semiconductor wafer. The method also includes the step of maintaining the semiconductor wafer in a predetermined environment. The method includes... Agent: Townsend And Townsend And Crew, LLP

20080311758 - Methods of and apparatus for protecting a region of process exlusion adjacent to a region of process performance in a process chamber: Apparatus and methods protect a central process exclusion region of a substrate during processing of an edge environ region of process performance. Removal of undesired materials is only from the edge environ region while the central device region is protected from damage. Field strengths are configured to protect the central... Agent: Martine Penilla & Gencarella, LLP

20080311759 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device including depositing a first silicon oxide film on a silicon substrate, depositing a silicon-containing film on the first silicon oxide film, applying a coating solution for silica film formation over the silicon-containing film, and heat-treating the coating solution, thereby forming a second silicon... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080311760 - Film formation method and apparatus for semiconductor process: A silicon nitride film is formed on a target substrate by performing a plurality of cycles in a process field configured to be selectively supplied with a first process gas containing a silane family gas and a second process gas containing a nitriding gas. Each of the cycles includes a... Agent: Smith, Gambrell & Russell

20080311761 - Method for the thermal treatment of disk-shaped substrates: Disclosed is an apparatus and a method for reducing flash in an injection mold (532 or 542, 543) which molds a molded article between a first mold surface and a second mold surface. The apparatus includes an active material actuator (530 or 533a and 533b or 561a and 561b) configured... Agent: Dority & Manning, P.A.

20080311762 - Semiconductor device surface roughness reduction: Methods and apparatus relating to surface roughness reduction are described. In one embodiment, a particle beam may be directed onto the surface roughness of a semiconductor device to reduce the roughness. Other embodiments are also disclosed.... Agent: Caven & Aghevli C/o Intellevate, LLC

20080305560 - Method for eliminating defects from semiconductor materials: Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvins for a period of ninety-six hours. At these low temperatures, alloys such as GaAs,... Agent: Joseph Reid Henrichs

20080305561 - Methods of controlling film deposition using atomic layer deposition: Methods of manufacturing semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a method of forming a material layer. The method includes providing a semiconductor wafer, forming a first portion of a material layer over the semiconductor wafer at a first pressure, and forming a second portion of... Agent: Slater & Matsil, L.L.P.

20080305562 - Passive alignment of photodiode active area in three axes using microscopic focus: A fixturing system and microscope/video camera setup enables an operator to manipulate a photodiode into position optically using known good targets for the X and Y location and using microscope focus/defocus/refocus for locating the active area of the avalanche photodiode exactly at the focal point of the lens.... Agent: Bae Systems

20080305564 - Manufacturing apparatus for semiconductor device and manufacturing method for semiconductor device: A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solation, determining necessity... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080305563 - Method and system for controlling copper chemical mechanical polish uniformity: A system and method for controlling resistivity uniformity in a Copper trench structure by controlling the CMP process is provided. A preferred embodiment comprises a system and a method in which a plurality of CMP process recipes may be created comprising at least a slurry arm position. A set of... Agent: Slater & Matsil, L.L.P.

20080305565 - Fabrication method for semiconductor device: A semiconductor device fabrication method can improve yield of semiconductor devices and decrease (or prevent) waste of non-defective semiconductor chips. This fabrication method has a step of performing characteristic inspection after packaging a semiconductor chip every time a semiconductor chip layer is formed. The fabrication method makes another semiconductor chip... Agent: Rabin & Berdo, PC

20080305566 - Silicon nanocrystal embedded silicon oxide electroluminescence device with a mid-bandgap transition layer: A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080305567 - Nitride-based light emitting device and manufacturing method thereof: A light emitting device according to an exemplary embodiment of the present invention includes: an n-type cladding layer; a p-type cladding layer; an active layer interposed between the n-type cladding layer and the p-type cladding layer; and an ohmic contact layer contacting the p-type cladding layer or the n-type cladding... Agent: Cantor Colburn, LLP

20080305568 - Method for promoting light emission efficiency of led using nanorods structure: Method for the light emitting diode (LED) having the nanorods-like structure is provided. The LED employs the nanorods are subsequently formed in a longitudinal direction by the etching method and the PEC method. In addition, the plurality of the nanorods is arranged in an array so that provide the LED... Agent: Bacon & Thomas, PLLC

20080305569 - Semiconductor device and a method of manufacturing the same: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.... Agent: Cook Alex Ltd

20080305570 - Led chip production method: An LED chip production method in which the sapphire substrate used in the process for formation of a nitride semiconductor can be easily and efficiently removed. The LED chip production method is a method for LED chips that has at least one nitride semiconductor layer. An LED chip structure assembly... Agent: Roberts Mlotkowski Safran & Cole, P.C. Intellectual Property Department

20080305571 - Method of fabricating semiconductor light emitting device substrate: A method of fabricating a substrate for semiconductor light emitting devices is provided. The method includes forming a nanocrystal structure on a surface of the substrate which is a single crystal material, wherein the nanocrystal structure has an etched region and an unetched region. Next, a nitride semiconductor material is... Agent: Jianq Chyun Intellectual Property Office

20080305572 - Method of fabricating image device having capacitor and image device fabricated thereby: There are provided a method of fabricating an image device having a capacitor and an image device fabricated thereby. The method comprises preparing a substrate having a pixel region and a peripheral circuit region. A lower electrode containing silicon is formed on the substrate of the peripheral circuit region. A... Agent: Marger Johnson & Mccollom, P.C.

20080305573 - Photovoltaically active semiconductor material and photovoltaic cell: The invention relates to a photovoltaically active semiconductor material and a photovoltaic cell comprising a photovoltaically active semiconductor material, wherein the photovoltaically active semiconductor material contains a crystal lattice composed of zinc telluride and, in the zinc telluride crystal lattice, ZnTe is substituted by—0.01 to 10 mol % CoTe, —0... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080305574 - Method of manufacturing nonvolatile memory device using conductive organic polymer having nanocrystals embedded therein: The method of manufacturing a nonvolatile memory device includes forming a lower conductive layer on a substrate; forming a first conductive organic layer on the substrate using spin coating; forming a metal layer for forming nanocrystals on the first conductive organic layer, the metal layer partially overlapping the first conductive... Agent: Myers Bigel Sibley & Sajovec

20080305575 - Thin film transistor having oxide semiconductor layer and manufacturing method thereof: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080305576 - Method of reducing warpage in semiconductor molded panel: A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the... Agent: Vierra Magen/sandisk Corporation

20080305578 - Method of machining wafer: A method of machining a wafer, wherein a wafer provided with devices each having a low dielectric constant insulating film (low-k film) stacked on the face side thereof is divided into the individual devices, the devices thus divided are mounted on a wiring board, and then a grindstone is brought... Agent: Greer, Burns & Crain

20080305577 - Method of minimizing kerf width on a semiconductor substrate panel: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.... Agent: Vierra Magen/sandisk Corporation

20080305579 - Method for fabricating semiconductor device installed with passive components: A method for fabricating a semiconductor device installed with passive components is provided. The method includes: having at least a passive component make a bridge connection between a ground circuit and a power circuit of each of a plurality of substrate units; electrically connecting a conductive circuit on a cutting... Agent: Edwards Angell Palmer & Dodge LLP

20080305583 - Adhesive sheet, dicing tape integrated type adhesive sheet, and method of producing semiconductor device: The invention provides an adhesive sheet which can be stuck to a wafer at low temperatures of 100° C. or below, which is soft to the extent that it can be handled at room temperature, and which can be cut simultaneously with a wafer under usual cutting conditions; a dicing... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080305580 - Bonding of structures together including, but not limited to, bonding a semiconductor wafer to a carrier: An expandable membrane (280), e.g. a membrane that is elastic and/or has a corrugated edge, is expanded to exert more uniform pressure over a semiconductor wafer (110) or a carrier (254) to bond the wafer to the carrier.... Agent: Macpherson Kwok Chen & Heid LLP

20080305582 - Power semiconductor packaging method and structure: A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip.... Agent: General Electric Company Global Research

20080305581 - Reducing stress in a flip chip assembly: In one embodiment, the present invention includes a method for depositing lead-free bumps on a package substrate, depositing an alloy material on the lead-free bumps, attaching a semiconductor die including conductive bumps to the package substrate so that the conductive bumps contact the alloy material, and heating attached components to... Agent: Trop Pruner & Hu, PC

20080305584 - Heat spreader for center gate molding: A heat spreader for an integrated circuit has a base portion and a top portion. The base portion is attachable to a surface of the integrated circuit, and has at least one channel extending therethrough. The top portion that is larger than the base portion such that the heat spreader... Agent: Freescale Semiconductor, Inc. Law Department

20080305585 - Method for direct heat sink attachment: A system and method of attaching a heat sink to an integrated circuit chip includes providing a compliant material for constraining the heat sink's mechanical motion while simultaneously allowing for thermal expansion of the heat sink.... Agent: Michael Buchenhorner, P.A.

20080305586 - Method of manuacturing a semiconductor device: According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead 1e is smaller than that of a silver plating formed on each lead. Thereafter, a semiconductor... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080305587 - Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is... Agent: Oliff & Berridge, PLC

20080305588 - Nand-type semiconductor storage device and method for manufacturing same: According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080305589 - Semicondustor device and method for manufacturing the same: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source... Agent: Eric Robinson

20080305590 - High performance cmos devices and methods for making same: An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the... Agent: Duane Morris LLP - PhiladelphiaIPDepartment

20080305591 - Metal oxide alloy layer, method of forming the metal oxide alloy layer, and methods of manufacturing a gate structure and a capacitor including the metal oxide alloy layer: A metal oxide alloy layer comprises a first layer including a first metal oxide and having a first thickness, and a second layer formed on the first layer, the second layer including a second metal oxide and having a second thickness, wherein a value of the first thickness is such... Agent: F. Chau & Associates, LLC

20080305592 - Menufacturing method of dynamic random access memory: A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capacitors includes a lower electrode, an upper... Agent: Jianq Chyun Intellectual Property Office

20080305593 - Memory structure and method of making the same: A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the... Agent: North America Intellectual Property Corporation

20080305594 - Method for fabricating non-volatile memory: A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that... Agent: Jianq Chyun Intellectual Property Office

20080305595 - Methods of forming a semiconductor device including openings: There is provided a method of forming a semiconductor device. According to the method, a gate pattern having a capping insulating layer is formed on a substrate, a first etch stop layer is conformably formed. A first interlayer insulating layer having a planarized upper surface, a second etch stop layer... Agent: Myers Bigel Sibley & Sajovec

20080305596 - Method of fabricating non-volatile memory: A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a... Agent: Jianq Chyun Intellectual Property Office

20080305597 - Semiconductor element and manufacturing method thereof: The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film 104 is formed by sputtering a Hf metal film 103 on a SiO2 film (or a SiON film) 102 on a Si wafer... Agent: Fitzpatrick Cella Harper & Scinto

20080305599 - Gate control and endcap improvement: A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric... Agent: Steven H. Slater Slater & Matsil, L.L.P.

20080305598 - Ion implantation device and a method of semiconductor manufacturing by the implantation of ions derived from carborane molecular species: An ion implantation device and a method of manufacturing a semiconductor device is described, wherein ionized carborane cluster ions are implanted into semiconductor substrates to perform doping of the substrate. The carborane cluster ions have the chemical form C2B10Hx+, C2B8Hx+ and C4B18Hx+and are formed from carborane cluster molecules of the... Agent: Katten Muchin Rosenman LLP (c/o Patent Administrator)

20080305600 - Method and apparatus for fabricating high tensile stress film: A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a... Agent: North America Intellectual Property Corporation

20080305601 - Method for forming semiconductor device using multi-functional sacrificial dielectric layer: A composite dielectric layer including a nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a... Agent: Duane Morris LLP (tsmc)IPDepartment

20080305602 - Transistor manufacture: An oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of the oxide layer in the emitter window is smaller than the... Agent: Thompson Hine L.L.P. Intellectual Property Group

20080305603 - Forming carbon nanotube capacitors: A capacitor may be formed of carbon nanotubes. Carbon nanotubes, grown on substrates, may be formed in a desired pattern. The pattern may be defined by placing catalyst in appropriate locations for carbon nanotube growth from a substrate. Then, intermeshing arrays of carbon nanotubes may be formed by juxtaposing the... Agent: Trop Pruner & Hu, PC

20080305604 - Deep trench and fabricating method thereof, trench capacitor and fabricating method thereof: A method of fabricating a deep trench is provided, by which a trench is formed in the substrate initially. Then, a block layer is formed on the substrate surface of the upper portion of the trench. After that, a pad oxide layer is formed on the substrate surface of the... Agent: Jianq Chyun Intellectual Property Office

20080305605 - Method for forming surface strap: A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a... Agent: North America Intellectual Property Corporation

20080305606 - High capacitance density vertical natural capacitors: Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080305607 - Thin film capacitor and fabrication method thereof: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080305608 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, the method includes forming an etch stop layer and an insulation layer over a substrate having a first region and a second region, selectively removing the insulation layer and the etch stop layer in the first region to expose parts of the substrate,... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080305609 - Method for forming a seamless shallow trench isolation: A method for fabricating a seamless shallow trench isolation includes providing a semiconductor substrate having at least a shallow trench that is filled by a dielectric layer with a seam, forming a dielectric layer filling the shallow trench with a seam, forming at least one healing layer on the dielectric... Agent: North America Intellectual Property Corporation

20080305610 - Method for manufacturing shallow trench isolation structure: A method of forming a shallow trench isolation structure includes steps of providing a substrate having a patterned mask layer formed thereon, wherein a trench is located in the substrate and the patterned mask layer exposes the trench. Thereafter, a dielectric layer is formed over the substrate to fill the... Agent: Jianq Chyun Intellectual Property Office

20080305611 - Coating composition for forming oxide film and method for producing semiconductor device using the same: A coating composition for forming an oxide film, which can suppress the phenomenon of an increased wet etching rate caused by a part of the SOG film embedded inside a groove becoming low-density, and which can suppress the volume expansion coefficient to a low level, and a method for producing... Agent: Young & Thompson

20080305612 - Semiconductor device and method of fabricating the same: A semiconductor device such as a flash memory includes a semiconductor substrate, two gate insulating films formed on the substrate so as to have a first film thickness and a second film thickness smaller than the first film thickness respectively, and a polycrystalline silicon film formed on the gate insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080305613 - Method for fabricating an soi defined semiconductor device: Methods are provided for fabricating a semiconductor on insulator (SOI) component on a semiconductor layer/insulator/substrate structure. The method includes forming one or more shallow trench isolation (STI) regions extending through the semiconductor layer to the insulator. First and second openings are etched through the STI and the insulator using the... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080305614 - Precision trench formation for semiconductor device: Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20080305616 - Die singulation methods: Some embodiments include methods in which a front side region of a semiconductor substrate is placed against a surface. While the front side region is against the surface, the semiconductor substrate is thinned, and then cut into a plurality of dice. The surface may be a pliable material, and may... Agent: Wells St. John P.s.

20080305615 - Method of scribing and breaking substrate made of a brittle material and system for scribing and breaking substrate: The method comprises (a) the first scribing step in the first direction by controlling the relative moving velocity and output power of the laser beam so that local volume shrinkage and local tensile stress can be generated in the vicinity of the formed first scribed line, (b) the second scribing... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080305617 - Method for depositing a conductive capping layer on metal lines: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition... Agent: Farjami & Farjami LLP

20080305618 - Method of forming polycrystalline semiconductor film: A method of forming a polycrystalline semiconductor film, which includes irradiating an amorphous semiconductor film formed on an insulating substrate with light to convert the amorphous semiconductor into a polycrystalline semiconductor with laterally grown crystal grains, thus forming a polycrystalline semiconductor film, wherein crystal growth in the semiconductor is controlled... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080305619 - Method of forming group iv semiconductor junctions using laser processing: A method forming a Group IV semiconductor junction on a substrate is disclosed. The method includes depositing a first set Group IV semiconductor nanoparticles on the substrate. The method also includes applying a first laser at a first laser wavelength, a first fluence, a first pulse duration, a first number... Agent: Foley & Lardner LLP

20080305620 - Methods of forming devices including different gate insulating layers on pmos/nmos regions: Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region... Agent: Myers Bigel Sibley & Sajovec

20080305621 - Channel strain engineering in field-effect-transistor: There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering... Agent: International Business Machines Corporation Dept. 18g

20080305622 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming at least two gate insulating layers having different thickness on a substrate having low, medium and high voltage regions; and then depositing a gate layer material on the gate insulating layers; and then forming a first etch mask on the gate... Agent: Sherr & Vaughn, PLLC

20080305623 - Semiconductor device manufacturing methods: Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard... Agent: Slater & Matsil LLP

20080305624 - Bonding structure with buffer layer and method of forming the same: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer... Agent: Lin & Associates Intellectual Property, Inc.

20080305625 - Poison-free and low ulk damage integration scheme for damascene interconnects: A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a... Agent: Texas Instruments Incorporated

20080305627 - Method of forming a contact plug and method of forming a semiconductor device: A method of forming a contact plug includes the following processes. A dummy film is formed over a substrate. The dummy film may include amorphous carbon as a main material. At least one contact hole is formed in the dummy film. At least one contact plug is formed in the... Agent: Sughrue Mion, PLLC

20080305626 - Method of forming solid blind vias through the dielectric coating on high density interconnect substrate materials: A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second... Agent: Ppg Industries Inc Intellectual Property Dept

20080305628 - Semiconductor device with connecting via and dummy via and method of manufacturing the same: An underlying interconnect including a first barrier metal layer, an interconnect metal layer and a second barrier metal layer is formed on a semiconductor substrate, and an interlayer dielectric is formed thereon. Etching is performed with a photoresist defining an opening for a first via, and an opening for a... Agent: Young & Thompson

20080305629 - Tungsten nitride atomic layer deposition processes: In one embodiment, a method for forming a tungsten barrier material on a substrate is provided which includes depositing a tungsten layer on a substrate during a vapor deposition process and exposing the substrate sequentially to a tungsten precursor and a nitrogen precursor to form a tungsten nitride layer on... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080305630 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a first conductive film on a semiconductor substrate via a first insulating film; forming a second conductive film on the first conductive film via a second insulating film; patterning the first and the second conductive films and the second insulating film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080305631 - Method for forming electrode structure for use in light emitting device and method for forming stacked structure: A method for forming an electrode structure in a light emitting device is disclosed. The method includes the steps of: forming a mask material layer having an opening; depositing a first material layer on the mask material layer and on a portion of a compound semiconductor layer exposed through the... Agent: Bell, Boyd & Lloyd, LLP

20080305632 - Substrate processing apparatus, substrate processing method and storage medium: A substrate processing apparatus is provided to enable to efficiently remove an oxide layer and an organic material layer. A third process unit (36) of a substrate processing apparatus (10) includes a box-shaped process vessel (chamber) (50), a nitrogen gas supply system (190) and an ozone gas supply system (191).... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080305633 - Manufacturing method of a semiconductor device and substrate processing apparatus: A method of manufacturing a semiconductor device comprises carrying a substrate into a processing chamber, forming a film containing ruthenium on the substrate by supplying a material gas into the processing chamber, carrying the film-formed substrate out of the processing chamber; and cleaning an inside of the processing chamber by... Agent: Oliff & Berridge, PLC

20080305634 - Metal film separation prevention structure in metal film forming device, and semiconductor device manufacturing method using said structure: The object of this invention is to prevent unwanted separation of a deposited metal film from a member, such as an anti-adhesion plate, in the chamber of a metal film forming device. In a sputtering device, metal particles sputtered from the surface of a target 12 in a chamber 10... Agent: Texas Instruments Incorporated

20080305635 - Method for fabricating a pattern: A method for fabricating a patter is provided as followed. First, a material layer is provided, whereon a patterned hard mask layer is formed. A spacer is deposited on the sidewalls of the patterned hard mask layer. Then, the patterned hard mask layer is removed, and an opening is formed... Agent: J C Patents, Inc.

20080305636 - Method of forming fine pattern employing self-aligned double patterning: There are provided a method of forming a fine pattern employing self-aligned double patterning. The method includes providing a substrate. First mask patterns are formed on the substrate. A reactive layer is formed on the substrate having the first mask patterns. The reactive layer adjacent to the first mask patterns... Agent: Marger Johnson & Mccollom, P.C.

20080305638 - Coating compositions for use in forming patterns and methods of forming patterns: A coating composition for forming etch mask patterns may include a polymer and an organic solvent. The polymer may have an aromatic ring substituted by a vinyl ether functional group. The polymer may be, for example, a Novolak resin partially substituted by a vinyl ether functional group or poly(hydroxystyrene) partially... Agent: Harness, Dickey & Pierce, P.L.C

20080305637 - Method for forming fine pattern of semiconductor device: A method for forming a fine pattern of a semiconductor device which includes sequentially forming a non-etching layer and a sacrificial layer on a semiconductor substrate; and then forming a plurality of photo-resist layer patterns having a plurality of openings exposing the sacrificial layer; and then forming a plurality of... Agent: Sherr & Vaughn, PLLC

20080305639 - Dual damascene process: A method and system for forming dual damascene structures in a semiconductor package. In one embodiment, the method includes forming an intermediate dielectric layer on a bottom stop layer; forming an ashing removable dielectric layer on the intermediate dielectric layer; forming a patterned photoresist layer above the ashing removable dielectric... Agent: Duane Morris LLP (tsmc)IPDepartment

20080305640 - Method for preparing trench power transistors: A method for preparing a trench power transistor comprises the steps of forming a mask layer having a plurality of openings on a semiconductor substrate, removing a portion of the semiconductor substrate under the openings to form a plurality of trenches in the semiconductor substrate in an array manner, coating... Agent: Wpat, PC Intellectual Property Attorneys

20080305642 - Method for forming fine pattern of semiconductor device: A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask... Agent: Marshall, Gerstein & Borun LLP

20080305641 - Reverse masking profile improvements in high aspect ratio etch: A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous carbon followed by a layer of... Agent: Dinsmore & Shohl LLP

20080305643 - Method for the removal of doped surface layers on the back faces of crystalline silicon solar wafers: The invention relates to a method for the one-sided removal of a doped surface layer on rear sides of crystalline silicon solar wafers. In accordance with the object set, doped surface layers should be able to be removed from rear sides of such solar wafers in a cost-effective manner and... Agent: Millen, White, Zelano & Branigan, P.C.

20080305644 - Method of manufacturing semiconductor device including trench-forming process: In a manufacturing method of a semiconductor device, a trench is formed in a semiconductor substrate by an anisotropic dry etching so as to have an aspect ratio greater than or equal to 10, and a damaged layer that is generated in a wall and a bottom of the trench... Agent: Posz Law Group, PLC

20080305645 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080305646 - Atomic layer deposition: An atomic layer deposition with hydroxylation pre-treatment is provided. The atomic layer deposition comprises the steps of (a) performing a hydroxylation pre-treatment on a silicon substrate to create a predetermined number of hydroxyl groups thereon; (b) performing a precursor pulse on the pre-treated silicon substrate, wherein the precursor react with... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080305647 - Method for manufacturing a semiconductor device: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080305648 - Method for forming inorganic silazane-based dielectric film: A method of forming an inorganic silazane-based dielectric film includes: introducing a gas constituted by Si and H and a gas constituted by N and optionally H into a reaction chamber where an object is placed; controlling a temperature of the object at −50° C. to 50° C.; and depositing... Agent: Knobbe Martens Olson & Bear LLP

20080299679 - Low resistance tunneling magnetoresistive sensor with composite inner pinned layer: A high performance TMR sensor is fabricated by employing a composite inner pinned (AP1) layer in an AP2/Ru/AP1 pinned layer configuration. In one embodiment, there is a 10 to 80 Angstrom thick lower CoFeB or CoFeB alloy layer on the Ru coupling layer, a and 5 to 50 Angstrom thick... Agent: Stephen B. Ackerman

20080299680 - Methods of forming magnetic memory devices: Methods for creating a memory device can include depositing a sense layer, patterning the sense layer to form a plurality of magnetic data cells, depositing a separation layer over the plurality of data cells, depositing a reference layer over the separation layer, and patterning the reference layer to form an... Agent: Myers Bigel Sibley & Sajovec

20080299682 - Method for removing poly silicon: Methods for removing poly silicon. In one example embodiment, a method for removing poly silicon that is formed on a silicon wafer includes the steps of growing the poly silicon as a silicon oxide through a thermal oxidation process and removing the silicon oxide using an etching solution.... Agent: Workman Nydegger

20080299681 - Multi-step deposition control: For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process parameters comprises at least one process parameter. The method comprises... Agent: Williams, Morgan & Amerson

20080299683 - Estimating yield fluctuation for back-end planning: A method for production planning includes receiving a first order quantity of a first device. A first yield estimate of the first device from a production line is determined. The first yield estimate is adjusted based on a first confidence factor associated with the first order quantity. A dispatch quantity... Agent: Williams, Morgan & Amerson

20080299684 - Method and system for removing empty carriers from process tools by controlling an association between control jobs and carrier: By providing an under-specified specification for designating a destination carrier in a respective control job or control message, a high degree of flexibility in determining the destination of processed substrates may be obtained, thereby also allowing the removal of a source carrier for enhancing load port availability in complex semiconductor... Agent: Williams, Morgan & Amerson

20080299685 - One piece method for integrated circuit (ic) assembly: In a method and system for assembling a semiconductor device, a tray is configured to provide an array of bins arranged in m rows and n columns, where m and n are integers. The tray containing defect free singulated substrates is received from a substrate supplier for assembly. Each one... Agent: Texas Instruments Incorporated

20080299686 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, includes; measuring a within-wafer distribution of a physical quantity; and etching the wafer so that the physical quantity get close to constant within the wafer. Alternatively, a method for manufacturing a semiconductor device, includes, measuring a within-wafer distribution of a physical quantity of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080299687 - Top-emitting nitride-based light emitting device and method of manufacturing the same: Provided are a top-emitting N-based light emitting device and a method of manufacturing the same. The device includes a substrate, an n-type clad layer, an active layer, a p-type clad layer, and a multi ohmic contact layer, which are sequentially stacked. The multi ohmic contact layer includes one or more... Agent: Buchanan, Ingersoll & Rooney PC

20080299688 - Method of bonding a solder type light emitting diode chip: In a method of bonding a low-resistance solder type light emitting diode chip, a copper substrate is prepared; an insulating layer is coated on the copper substrate; a conductive layer is formed on the insulating layer; a solder paste is coated onto the conductive layer by silk screen printing; a... Agent: Hdsl

20080299690 - High quality and ultra large screen liquid crystal display device and production method thereof: A large screen liquid crystal display device using a transverse electric field system which is capable of dramatically improving an aperture ratio, a transmittance ratio, brightness, and contrast with low cost and high production yield. For example, the width of the common electrodes that shield the electric fields of the... Agent: Yasuo Muramatsu Muramatsu & Associates

20080299689 - Method for manufacturing semiconductor device and display device: It is an object to provide a method for manufacturing a display device suitable for mass production without complicating a manufacturing process of a thin film transistor. A microcrystalline semiconductor film is formed by use of a microwave plasma CVD apparatus with a frequency of greater than or equal to... Agent: Eric Robinson

20080299691 - Gan lasers on aln substrates and methods of fabrication: Ga(In)N-based laser structures and related methods of fabrication are proposed where Ga(In)N-based semiconductor laser structures are formed on AlN or GaN substrates in a manner that addresses the need to avoid undue tensile strain in the semiconductor structure. In accordance with one embodiment of the present invention, a Ga(In)N-based semiconductor... Agent: Corning Incorporated

20080299692 - Semiconductor laser and the method for manufacturing the same: The present invention is to provide a semiconductor laser with a feedback grating comprised of InP and AlGaInAs without InAsP put therebetween, and to provide a method for manufacturing the DFB-LD having such grating. The LD includes an n-type InP substrate, an AlInAsP intermediate layer, an AlGaInAs lower SCH layer,... Agent: Smith, Gambrell & Russell

20080299693 - Manufacturing method for display device: A manufacturing method for a display device having a first conductive type thin film transistor and a second conductive type thin film transistor, comprising the steps of: in formation regions for a first conductive type thin film transistor and a second conductive type thin film transistor forming a semiconductor layer,... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20080299694 - Method of manufacturing semiconductor light-emitting element: In a semiconductor laser manufacturing method, a GaN single-crystal substrate is formed by slicing a GaN bulk crystal, grown on a c-plane, parallel to an a-plane which is perpendicular to the c-plane. In this substrate, crystal defects extending parallel to the c-axis direction do not readily exert an influence, and... Agent: Drinker Biddle & Reath (dc)

20080299695 - Microchannels for biomems devices: A method is disclosed for making a MEMS device wherein anhydrous HF exposed silicon nitride is used as a temporary adhesion layer allowing the transfer of a layer from a Carrier Wafer to a Device Wafer.... Agent: Marks & Clerk

20080299697 - Bandgap-shifted semiconductor surface and method for making same, and apparatus for using same: Titania is a semiconductor and photocatalyst that is also chemically inert. With its bandgap of 3.2 and greater, to activate the photocatalytic property of titania requires light of about 390 nm wavelength, which is in the ultra-violet, where sunlight is very low in intensity. A method and devices are disclosed... Agent: David J. Cole

20080299698 - Front lip pin/nip diode having a continuous anode/cathode: A photodetector includes a semiconductor substrate having first and second main surfaces opposite to each other. The photodetector includes at least one trench formed in the first main surface and a first anode/cathode region having a first conductivity formed proximate the first main surface and sidewalls of the at least... Agent: Panitch Schwarze Belisario & Nadel LLP

20080299696 - Solid state imaging apparatus: A method for manufacturing a solid state imaging device includes steps of forming a photodiode layer buried in a semiconductor substrate by ion injection and of forming a shielding layer buried in the photodiode layer by ion injection. At least in the ion injection process in the step of forming... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080299699 - Methods of forming a resistance variable element: The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a deposition chamber comprising a sputtering target and a substrate to be depositing upon. The... Agent: Allen Mcteer

20080299700 - Method for fabricating photodiode: A method of fabricating photodiode includes: a substrate comprising a well is provided, next, a first doping region is formed in the well, following that a conductive layer is formed on the surface of the first doping region by an epitaxial growth process, meanwhile, the conductive layer is in-situ doped... Agent: North America Intellectual Property Corporation

20080299701 - Front-end processing of nickel plated bond pads: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.... Agent: Dickstein Shapiro LLP

20080299703 - Film growth system and method: An apparatus for depositing a solid film onto a substrate from a reagent solution includes a reservoir of reagent solution maintained at a sufficiently low temperature to inhibit homogeneous reactions within the reagent solution. The reagent solution contains multiple ligands to further control temperature stability and shelf life. The chilled... Agent: Robert J. Lauf

20080299702 - Method of manufacturing zno-based thin film transistor: A ZnO-based thin film transistor (TFT) is provided herein. Also provided is a method for manufacturing the TFT. The ZnO-based TFT is very sensitive to the oxygen concentration present in a channel layer. In order to prevent damage to a channel layer of a bottom gate TFT, and to avoid... Agent: Cantor Colburn, LLP

20080299704 - Integrated circuit die with logically equivalent bonding pads: An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the... Agent: Mark M. Friedman

20080299705 - Chip scale package having flip chip interconnect on die paddle: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.... Agent: Quarles & Brady LLP

20080299706 - Wafer level package fabrication method: Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate... Agent: Staas & Halsey LLP

20080299707 - Thermal paste containment for semiconductor modules: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080299708 - Electronic device and method for fabricating the same: An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and... Agent: Mcdermott Will & Emery LLP

20080299709 - Metal core foldover package structures: Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least one flange... Agent: Trask Britt, P.C./ Micron Technology

20080299710 - Carbon nanotube transistor fabrication: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the... Agent: Aka Chan LLP

20080299711 - Dual work-function single gate stack: Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080299712 - Manufacturing method of a thin film transistor array panel: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe, forming a data line including a... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080299713 - Thin film transistor (tft) and flat panel display including the tft and their methods of manufacture: A Thin Film Transistor (TFT) reduces interconnection resistance of source/drain electrodes, prevents contamination from an active layer, reduces contact resistance between a pixel electrode and the source/drain electrodes, smoothly supplies hydrogen to the active layer and has high mobility, on-current characteristics, and threshold voltage characteristics. The TFT includes an active... Agent: Robert E. Bushnell

20080299714 - Planar combined structure of a bipolar junction transistor and n-type/p-type metal semiconductor field-effect transistors and method for forming the same: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion... Agent: Nikolai & Mersereau, P.A.

20080299715 - Method of fabricating self aligned schotky junctions for semiconductors devices: A method of fabricating a self-aligned Schottky junction (29) in respect of a semiconductor device. After gate etching and spacer formation, a recess defining the junction regions is formed in the Silicon substrate (10) and a SiGe layer (22) is selectively grown therein. A dielectric layer (24) is then provided... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080299716 - Distributed high voltage jfet: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions... Agent: Texas Instruments Incorporated

20080299718 - Damascene process having retained capping layer through metallization for protecting low-k dielectrics: A method of forming single or dual damascene interconnect structures using either a via-first or trench first approach includes the steps of providing a substrate surface having an etch-stop layer thereon, a low-k dielectric layer on the etch-stop layer, and a dielectric capping layer on the low-k dielectric layer. In... Agent: Texas Instruments Incorporated

20080299717 - Method of forming a semiconductor device featuring a gate stressor and semiconductor device: A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an... Agent: Freescale Semiconductor, Inc. Law Department

20080299719 - Mosfet-type semiconductor device, and method of manufacturing the same: A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a gate insulating film, source and drain regions formed at the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080299721 - Cmos (complementary metal oxide semiconductor) technology: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material... Agent: Schmeiser, Olsen & Watts

20080299720 - Stabilization of ni monosilicide thin films in cmos devices using implantation of ions before silicidation: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation... Agent: Scully, Scott, Murphy & Presser, P.C.

20080299722 - Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure: m

20080299723 - Methods for forming capacitor structures: A method for forming a capacitor includes forming a dielectric layer over a substrate. A conductive layer is formed over the dielectric layer. Dopants are implanted through at least one of the dielectric layer and the conductive layer after forming the dielectric layer so as to form a conductive region... Agent: Duane Morris LLP (tsmc)IPDepartment

20080299724 - Method of making a semiconductor device with embedded stressor: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to... Agent: Freescale Semiconductor, Inc. Law Department

20080299725 - Method of manufacturing semiconductor devices: A method of manufacturing semiconductor devices comprises forming an semiconductor layer of the first conduction type on a substrate of the first conduction type; forming an anti-oxidizing layer on the surface of the semiconductor layer of the first conduction type, the anti-oxidizing layer having an aperture only through a region... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080299726 - Semiconductor apparatus and method of manufacturing semiconductor apparatus: A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a... Agent: Young & Thompson

20080299727 - Vertical trench gate transistor semiconductor device and method for fabricating the same: A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body... Agent: Mcdermott Will & Emery LLP

20080299728 - Method for manufacturing semiconductor device: A semiconductor device manufacturing method includes: forming a sidewall spacer on a sidewall surface of a gate electrode; forming a pair of second conductive type source and drain regions in an active region; covering top surfaces of a semiconductor layer, a device isolation region, the sidewall spacer and the gate... Agent: Pearne & Gordon LLP

20080299729 - Method of fabricating high voltage mos transistor device: A substrate is provided, and a sacrificial pattern having an opening partially exposing a high voltage device region is formed on the substrate. Subsequently, a gate oxide layer is formed in the opening, and the sacrificial pattern is removed. A gate electrode, and two heavily doped regions are formed. Than,... Agent: North America Intellectual Property Corporation

20080299731 - Eraseable nonvolatile memory with sidewall storage: A nonvolatile storage cell, integrated circuit (IC) including the cells and method of manufacturing the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride... Agent: Law Office Of Charles W. Peterson, Jr. Burlington

20080299730 - Metal oxynitride as a pfet material: A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080299732 - Method for reducing overlap capacitance in field effect transistors: A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations... Agent: Cantor Colburn LLP - IBM Fishkill

20080299733 - Method of forming a semiconductor structure comprising an implantation of ions in a material layer to be etched: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature having a side surface and a top surface is formed over the substrate. A material layer is formed over the substrate. The material layer covers at least the side surface of the feature. An ion implantation... Agent: Williams, Morgan & Amerson

20080299734 - Method of manufacturing a self-aligned fin field effect transistor (finfet) device: A method of manufacturing a self-aligned fin FET (FinFET) device is disclosed, in which, an insulating layer of a shallow trench isolation is etched back to partially expose sidewalls of the semiconductor substrate surrounded by the shallow trench isolation, and the sidewalls of the semiconductor substrate are then isotropically etched,... Agent: North America Intellectual Property Corporation

20080299735 - Methods for forming a transistor: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080299736 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an... Agent: Rabin & Berdo, PC

20080299737 - Semiconductor device and manufacturing method thereof: A manufacturing method of a semiconductor device which can decrease the degradation of an element due to plasma in the LDD formation process is provided. The degradation of an element due to plasma is decreased by forming an element having an LDD structure according to a manufacturing method of a... Agent: Nixon Peabody, LLP

20080299738 - Method for forming inductor on semiconductor substrate: An inductor formed on a semiconductor substrate is provided in the present invention. The inductor includes a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer includes at least one insulator slot, and each insulator slot is encompassed in the metal... Agent: Jianq Chyun Intellectual Property Office

20080299739 - Method of manufacturing semiconductor device: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a first insulating film over a rear surface of a plurality of silicon substrates, annealing the plurality of silicon substrates to degas the oxide species in the first insulating film, and oxidizing the surface... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080299741 - Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation: An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a... Agent: Birch Stewart Kolasch & Birch

20080299740 - Method for forming sti structure: A method for forming a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate, having a trench-like opening therein exposing a portion of the substrate. A thermal oxidation process is performed to the substrate. An anisotropic etching process is performed using the patterned... Agent: J C Patents, Inc.

20080299743 - Manufacturing method of semiconductor device: To provide a semiconductor device with high performance and low cost and a manufacturing method thereof. A first region including a separated (cleavage) single-crystal semiconductor layer and a second region including a non-single-crystal semiconductor layer are provided over a substrate. It is preferable that laser beam irradiation be performed to... Agent: Eric Robinson

20080299744 - Manufacturing method of semiconductor substrate and semiconductor device: It is an object of the present invention to obtain a large-sized SOI substrate by providing a single-crystal silicon layer over a large-sized glass substrate in a large area. After a plurality of rectangular single-crystal semiconductor substrates each provided with a separation layer are aligned over a dummy substrate and... Agent: Eric Robinson

20080299742 - Method for manufacturing soi wafer: There is disclosed a method for manufacturing an SOI wafer comprising: a step of implanting at least one of a hydrogen ion and a rare gas ion into a donor wafer to form an ion implanted layer; a step of bonding an ion implanted surface of the donor wafer to... Agent: Oliff & Berridge, PLC

20080299745 - Wafer separating method: A wafer separating method including a laminated member removing step for partially removing a laminated member of a wafer along streets by applying a laser beam to the wafer along the streets, and a cutting step for cutting a substrate of the wafer along the streets after the laminated member... Agent: Greer, Burns & Crain

20080299746 - Semiconductor substrate fabrication method: A semiconductor substrate fabrication method according to the first aspect of this invention is characterized by including a preparation step of preparing an underlying substrate, a stacking step of stacking, on the underlying substrate, at least two multilayered films each including a peeling layer and a semiconductor layer, and a... Agent: Cowan Liebowitz & Latman P.C. John J Torrente

20080299747 - Method for forming amorphouse silicon film by plasma cvd: A method includes introducing a silicon-containing source gas and a dilution gas to a reactor to deposit an amorphous silicon film on a substrate by plasma CVD; and adjusting a compressive film stress to 300 MPa or less and a uniformity of film thickness within the substrate surface to ±5%... Agent: Knobbe Martens Olson & Bear LLP

20080299748 - Group iii-v crystal: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. The III-V crystals are obtained by manufacturing method characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2)... Agent: Judge Patent Associates

20080299749 - Cluster ion implantation for defect engineering: A method of semiconductor manufacturing is disclosed in which doping is accomplished by the implantation of ion beams formed from ionized molecules, and more particularly to a method in which molecular and cluster dopant ions are implanted into a substrate with and without a co-implant of non-dopant cluster ion, such... Agent: Katten Muchin Rosenman LLP (c/o Patent Administrator)

20080299750 - Multiple millisecond anneals for semiconductor device fabrication: A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as... Agent: Freescale Semiconductor, Inc. Law Department

20080299751 - Schottky diode and method therefor: In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20080299752 - Fabrication method of semiconductor device: An insulating film for forming sidewall insulating films of a gate electrode is deposited on the main surface of a semiconductor wafer and then, subjected to the treatment for equalizing the film thickness distribution. In this treatment, the semiconductor wafer is fixed onto a spin stage of an etching apparatus... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080299753 - Peripheral gate stacks and recessed array gates: Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within... Agent: Knobbe Martens Olson & Bear LLP

20080299754 - Methods for forming mos devices with metal-inserted polysilicon gate stack: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon... Agent: Slater & Matsil, L.L.P.

20080299755 - Methods of fabricating non-volatile memory devices including a chlorine cured tunnel oxide layer: Fabrication of a nonvolatile memory device includes sequentially forming a tunnel oxide layer, a first conductive layer, and a nitride layer on a semiconductor substrate. A stacked pattern is formed from the tunnel oxide layer, the first conductive layer, and the nitride layer and a trench is formed in the... Agent: Myers Bigel Sibley & Sajovec

20080299756 - Method and apparatus for plating a semiconductor package: A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein... Agent: Sughrue Mion, PLLC

20080299757 - Wafer structure and method for fabricating the same: A wafer structure and a method for fabricating the same are provided. First, a wafer having a pad and a first protection layer with a first opening is provided. Next, a second protection layer with a second opening is formed on the first protection layer. Part of the pad and... Agent: Bacon & Thomas, PLLC

20080299758 - Method of manufacturing semiconductor device: A high-density N-type diffusion layer 116 formed in a separation area 115 makes it possible to reduce a collector current flowing through a parasitic NPN transistor 102. Thus, a normal CMOS process can be used to provide a driving circuit and a data line driver which make it possible to... Agent: Steptoe & Johnson LLP

20080299760 - Method for manufacturing a semiconductor device: A highly reliable method for forming contact plugs is provided. The method can prevent short circuiting from occurring between self aligned contact plugs and word lines or between self aligned contact plugs and bit lines by applying a material, whose etching speed ratio relative to that of the silicon-based insulating... Agent: Young & Thompson

20080299759 - Method to form a via: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b)... Agent: Fortkort & Houston P.C.

20080299761 - Interconnection process: An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region.... Agent: Bacon & Thomas, PLLC

20080299762 - Method for forming interconnects for 3-d applications: A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over... Agent: Fortkort & Houston P.C.

20080299763 - Method for fabricating semiconductor device: After a first insulating film is formed on a substrate, a wiring groove is formed in the first insulating film, and then a wire is formed inside the wiring groove. Subsequently, a protection film is formed on the first insulating film and on the wire, and then a hard mask... Agent: Mcdermott Will & Emery LLP

20080299764 - Interconnection having dual-level or multi-level capping layer and method of forming the same: An interconnection having a dual-level and multi-level capping layer and a method of forming the same. The interconnection may include an interlayer dielectric layer with a groove formed therein, a metal layer formed within the groove, a metal compound layer on the metal layer, a first barrier layer on the... Agent: Harness, Dickey & Pierce, P.L.C

20080299766 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080299765 - Method of fabricating a structure for a semiconductor device: There is described a method of fabricating a dual damascene structure for a semiconductor device. A halogen based pre-cursor is used during vapour deposition of a diffusion barrier layer in a trench or via formed in a substrate. Residual halogen from the deposition is allowed to remain on the barrier... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080299767 - Method for forming a semiconductor device having a salicide layer: A method for forming a semiconductor device and selectively forming a salicide layer is described. In one embodiment, the method includes depositing a metal layer over a semiconductor substrate having a first area and a second area, wherein the first area and the second area include silicon, removing the metal... Agent: Freescale Semiconductor, Inc. Law Department

20080299768 - Manufacturing method of substrate with through electrode: A manufacturing method of a substrate with through electrodes, comprising a substrate having through holes, and through electrodes received in the through holes, includes a through electrode formation step of forming the through electrodes on a support plate, a substrate formation step of forming the substrate, a through electrode reception... Agent: Rankin, Hill & Clark LLP

20080299769 - Semiconductor fabrication method suitable for mems: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is... Agent: Duane Morris LLP (tsmc)IPDepartment

20080299770 - Method for increasing etch rate during deep silicon dry etch: A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another... Agent: Dinsmore & Shohl LLP One Dayton Centre

20080299771 - Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby: A method of making a thin film transistor comprising a thin film semiconductor element comprised of a transparent zinc-oxide-based semiconductor material, wherein spaced apart first and second contacts in contact with said material are position on either side of a channel in the thin film semiconductor element such that the... Agent: Andrew J. Anderson Patent Legal Staff

20080299772 - Methods of fabricating electronic devices using direct copper plating: The present invention relates to methods and structures for the metallization of semiconductor devices. One aspect of the present invention is a method of forming a semiconductor device having copper metallization. In one embodiment, the method includes providing a patterned wafer having a diffusion barrier for copper; depositing a copperless... Agent: Larry Williams

20080299773 - Semiconductor device manufacturing method: In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080299774 - Pitch multiplication using self-assembling materials: Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed to self-assemble into a desired pattern. One of the blocks forming the block copolymers is selectively removed. The remaining blocks are used as mandrels for pitch multiplication. Spacer... Agent: Knobbe Martens Olson & Bear LLP

20080299776 - Frequency doubling using spacer mask: A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. Next,... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20080299775 - Gapfill extension of hdp-cvd integrated process modulation sio2 process: Methods are disclosed for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A silicon-containing gas, an oxygen-containing gas, and a fluent gas are flowed into the substrate processing chamber. A high-density plasma is formed... Agent: Townsend And Townsend And Crew LLP / Amat

20080299778 - silicon film dry etching method: A silicon film is dry etched by parallel plate type dry etching using a mixed gas including a fluorine gas and a chlorine gas.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080299777 - Silicon nitride film dry etching method: A silicon nitride film is dry etched by reactive ion etching using a mixed gas including a fluorine gas and an oxygen gas.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080299779 - Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device: Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a semiconductor substrate with a plurality of pillars formed thereon, depositing a first layer of dielectric material over a plurality of pillars, removing... Agent: Fulbright & Jaworski L.L.P.

20080299780 - Method and apparatus for laser oxidation and reduction: A method and apparatus using electromagnetic radiation and gas to create oxidation and reduction reactions on a device, such as a semiconductor wafer surface. In one embodiment, a scanned laser and gas may be employed in a number of oxidation and/or reduction reactions in a single system without using multiple... Agent: Wolf Greenfield & Sacks, P.C.

20080299781 - Method of forming semiconductor device and semiconductor device: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080299782 - Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing... Agent: Mueting, Raasch & Gebhardt, P.A.

20080299783 - Systems and methods for processing semiconductor structures using laser pulses laterally distributed in a scanning window: Systems and methods process structures on or within a semiconductor substrate using a series of laser pulses. In one embodiment, a deflector is configured to selectively deflect the laser pulses within a processing window. The processing window is scanned over the semiconductor substrate such that a plurality of laterally spaced... Agent: Electro Scientific Industries/stoel Rives, LLP

20080299784 - Apparatus and method for thermally treating semiconductor device capable of preventing wafer from warping: A thermal treatment apparatus and method for processing a wafer are provided. The thermal treatment apparatus includes a process chamber for thermally treating the wafer, a heating unit for heating the wafer in the process chamber, and a gas supply unit for supplying a gas and controlling a gas pressure... Agent: Townsend And Townsend And Crew, LLP