Semiconductor device manufacturing: process inventions 11/08

20080293165 - Method for manufacturing non-volatile magnetic memory: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic... Agent: Law Offices Of Imam

20080293166 - Laser processing of light reflective multilayer target structure: A solution to an interference effect problem associated with laser processing of target structures entails adjusting laser pulse energy or other laser beam parameter, such as laser pulse temporal shape, based on light reflection information of the target structure and passivation layers stacked across a wafer surface or among multiple... Agent: Electro Scientific Industries/stoel Rives, LLP

20080293167 - Fabrication method of semiconductor integrated circuit device: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080293168 - Method and system of tape automated bonding: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally... Agent: Schwegman, Lundberg & Woessner/bsc-crm

20080293169 - Lithography evaluating method, semiconductor device manufacturing method and program medium: A lithography evaluating method comprises preparing a substrate, the substrate including a semiconductor substrate and a wiring structure including at least one wiring layer formed on the semiconductor substrate, partitioning the substrate into a plurality of regions to be evaluated, and obtaining a value of property relating to the wiring... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080293170 - Method for evaluating a gate insulation film characteristic for use in a semiconductor device: A gate insulating film 3 is formed of an insulative inorganic material containing silicon and oxygen as a main material. The gate insulating film 3 contains hydrogen atoms. A part of the absorbance of infrared radiation of which wave number is in the range of 830 to 900 cm−1 is... Agent: Harness, Dickey & Pierce, P.L.C

20080293171 - Light emitting diodes (leds) with improved light extraction by roughening: Systems and methods are disclosed for fabricating a semiconductor light emitting diode (LED) device by forming an n-gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.... Agent: Patterson & Sheridan, L.L.P.

20080293172 - Method for manufacturing light emitting diode devices: A method for manufacturing LED devices is disclosed to manufacture vertical LED devices without removing nonconductive substrates. A conductive substrate is formed on the LED epitaxial layer of the nonconductive substrate to form a LED wafer by bonding or electroplating, which is further cut into a plurality of LED sticks... Agent: Troxell Law Office PLLC

20080293173 - White multi-wavelength led and its manufacturing process: A white multi-wavelength LED and its manufacturing process has bonded at the bottom of a light emitting chip in a given color a first non-conductive material containing phosphor in a corresponding color to that of the chip to become a die unit; the first non-conductive material functioning as the position... Agent: Troxell Law Office PLLC

20080293174 - Method for forming led array: A method for forming LED array is disclosed herein. First, a LED wafer, a substrate having a LED epitaxial layer thereon, is cut into a plurality of LED sticks. Then, each space layer is bonded between every two LED sticks to form a LED array.... Agent: Troxell Law Office PLLC

20080293175 - Method for mounting anisotropically-shaped members: A mounting method of the present invention includes the steps of: (I) disposing a first liquid in a first region provided on one principal surface of a substrate; (II) bringing a pillar-like member as an anisotropically-shaped member, disposed on one principal surface of a transfer substrate in a predetermined orientation,... Agent: Mcdermott Will & Emery LLP

20080293176 - Method for manufacturing semiconductor optical device: A method for manufacturing a semiconductor optical device includes: forming a first resist pattern on top surface of a laminated semiconductor structure; forming channels and a waveguide ridge by dry etching using the first resist pattern as a mask; forming an SiO2 film on the waveguide ridge and the channels,... Agent: Leydig Voit & Mayer, Ltd

20080293177 - Method of manufacturing nitride-based semiconductor light emitting diode: Provided is a method of manufacturing a nitride-based semiconductor LED including sequentially forming an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate; forming a Pd/Zn alloy layer on the p-type nitride semiconductor layer; heat-treating the p-type nitride semiconductor layer on which the... Agent: Mcdermott Will & Emery LLP

20080293178 - Process for manufacturing micromechanical devices containing a getter material and devices so manufactured: A process is provided for manufacturing micromechanical devices formed by joining two parts together by direct bonding. One of the parts (12) is made of silicon and the other one is made of a material chosen between silicon and a semiconductor ceramic or oxidic material. The joint between the two... Agent: Panitch Schwarze Belisario & Nadel LLP

20080293179 - Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers: Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including a first substrate and an image sensor on and/or in the first substrate. An embodiment of an optical device includes a stand-off having a compartment configured to contain the... Agent: Dickstein Shapiro LLP

20080293180 - Photonic crystal-based lens elements for use in an image sensor: The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a substrate and a plurality of pillars forming a photonic crystal structure over the substrate. The pillars are spaced apart from each other. Each pillar has a height... Agent: Dickstein Shapiro LLP

20080293181 - Method for manufacturing image sensor: A method for manufacturing an image sensor including forming a microlens array over a color filter array, forming a capping layer over the semiconductor substrate including the microlens array, forming a pad mask over the capping layer, and then exposing a pad in an interlayer dielectric layer.... Agent: Sherr & Vaughn, PLLC

20080293182 - Method for manufacturing image sensor: Disclosed are methods of manufacturing an image sensor. The method can include forming a microlens by depositing photoresist bubbles on a substrate. The photoresist bubbles can be formed and deposited using an inkjet scheme. A curing process of the photoresist can be performed during formation of the photoresist bubbles before... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080293183 - Phase change memory and manufacturing method thereof: Even if sizes of storage cells are reduced in a phase change memory, properties of the respective storage cells can be set to be approximately equal to one another and a current amount required for phase change can be reduced sufficiently. The phase change memory includes at least a storage... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080293184 - Method of bonding aluminum electrodes of two semiconductor substrates: A method of bonding aluminum (Al) electrodes formed on two semiconductor substrates at a low temperature that does not affect circuits formed on the two semiconductor substrates is provided. The method includes: (a) forming aluminum (Al) electrodes on the two semiconductor substrates, respectively, and depositing a metal alloy that comprises... Agent: Cantor Colburn, LLP

20080293185 - Semiconductor substrates having useful and transfer layers: A method of fabricating composite substrates by associating a transfer layer with an intermediate support to form an intermediate substrate of predetermined thickness with the transfer layer having a free surface; providing a sample carrier having a surface and a recess that has a depth that is approximate the same... Agent: Winston & Strawn LLP Patent Department

20080293186 - Method of assembling a silicon stack semiconductor package: A method of manufacturing a plurality of stacked die semiconductor packages, including: placing a phase change material between a top surface of a substrate and a bottom surface of a first die; placing a phase change material between a top surface of the first die and a bottom surface of... Agent: Sughrue Mion, PLLC

20080293188 - Reactive solder material: Reactive solder material. The reactive solder material may be soldered to semiconductor surfaces such as the backside of a die or wafer. The reactive solder material includes a base solder material alloyed with an active element material. The reactive solder material may also be applied to a portion of a... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080293187 - Substrate table and chip manufacturing method: A substrate table used for manufacturing a chip is provided. The substrate table includes a substrate stage, a substrate placement surface formed on the substrate stage, and on which a substrate is placed, and a guiding member that can project and retract from the substrate placement surface. The guiding member... Agent: Rabin & Berdo, PC

20080293189 - Method of manufacturing chip integrated substrate: There are provided the steps of connecting a chip component 13 to a first substrate 10 through a wire 14, providing an electrode 21 on a second substrate 20, attaching, to the first substrate 10, a molding tool 30 having a protruded portion 31 formed corresponding to an array of... Agent: Drinker Biddle & Reath (dc)

20080293190 - Semiconductor package, method for fabricating the same, and semiconductor device: A semiconductor device includes a semiconductor chip, leads for sending and receiving signals between the semiconductor chip and an external device, fine metal wires, an encapsulant for sealing the leads, and a lid member. On the surface of each of the leads, a metal oxide film is formed by an... Agent: Mcdermott Will & Emery LLP

20080293191 - Semiconductor package: There is provided a semiconductor package including: a substrate having a plurality of electrode pads on a surface thereof; a semiconductor chip mounted on the substrate, the semiconductor chip electrically connecting with the plurality of electrode pads; and a stiffener arranged on the substrate so as to surround the semiconductor... Agent: Shimokaji & Associates, P.C.

20080293192 - Semiconductor device with stressors and methods thereof: A semiconductor device is formed in a semiconductor layer. A gate dielectric is formed over a top surface of the semiconductor layer. A gate stack is over the gate dielectric. A sidewall spacer is formed around the gate stack. Using the sidewall spacer as a mask, an implant is performed... Agent: Zagorin O'brien Graham LLP (115)

20080293195 - Gate straining in a semiconductor device: Gate straining techniques as described herein can be utilized during the fabrication of NMOS transistor devices, PMOS transistor devices, or CMOS device structures. For an NMOS device, conductive vias are formed in TEOS oxide regions surrounding the sidewall spacers of a metal gate structure, where the metal gate structure includes... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080293194 - Method of making a p-type metal-oxide semiconductor transistor and method of making a complementary metal-oxide semiconductor transistor: A method is disclosed to make a strained-silicon PMOS or CMOS transistor, in which, a compressive stress film is formed by reacting a silane having at least one substituent selected from the group consisting of hydrocarbyl, hydrocarboxy, carbonyl, formyl, carboxylic group, ester group, and halo group and ammonia, or a... Agent: North America Intellectual Property Corporation

20080293193 - Use of low temperature anneal to provide low defect gate full silicidation: Provided is a method for manufacturing a semiconductor device that includes forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode. The method further includes forming a metal layer over the gate electrode, and forming a fully silicided gate electrode using... Agent: Texas Instruments Incorporated

20080293196 - Method for fabricating multi-resistive state memory devices: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The... Agent: Unity Semiconductor Corporation

20080293197 - Method of manufacturing semiconductor memory device: A method of manufacturing a semiconductor memory device includes forming a device separation film on a semiconductor substrate using a mask pattern for defining an entire source line region as an active region to separate a device separation region from an active region; forming a stack gate structure on the... Agent: Sherr & Vaughn, PLLC

20080293198 - Method for manufacturing semiconductor device including etching process of silicon nitride film: A manufacturing method of a semiconductor device includes the step for forming a silicon nitride film having a first part where arsenic is included and a second part where less amount of or substantially no arsenic is included, the step for removing at least a portion of the first part... Agent: Mcginn Intellectual Property Law Group, PLLC

20080293199 - Single-poly non-volatile memory device and its operation method: A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls... Agent: North America Intellectual Property Corporation

20080293200 - Method of fabricating nonvolatile semiconductor memory device: In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in... Agent: Lee & Morse, P.C.

20080293201 - Nonvolatile semiconductor memory and a fabrication method thereof: A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080293202 - method for manufacturing semiconductor device: A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the... Agent: Posz Law Group, PLC

20080293203 - Semiconductor device having a fin structure and method of manufacturing the same: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a... Agent: Harness, Dickey & Pierce, P.L.C

20080293204 - Shallow junction formation and high dopant activation rate of mos devices: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than... Agent: Slater & Matsil, L.L.P.

20080293205 - Method of forming metal silicide layer, and method of manufacturing semiconductor device using the same: A method of forming a metal silicide layer includes sequentially forming a metal layer and a first capping layer on a substrate, performing a first heat treatment on the substrate to cause the substrate to react to the metal layer, removing the first, capping layer and an unreacted metal layer,... Agent: F. Chau & Associates, LLC

20080293206 - Unique ldmos process integration: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake... Agent: Texas Instruments Incorporated

20080293207 - Integration of non-volatile charge trap memory devices and logic cmos devices: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels... Agent: Blakely, Sokoloff, Taylor & Zafman LLP

20080293208 - Method of fabricating oxide semiconductor device: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.... Agent: Fitzpatrick Cella Harper & Scinto

20080293210 - Post last wiring level inductor using patterned plate process: A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative... Agent: Schmeiser, Olsen & Watts

20080293209 - Thin film multiplayer ceramic capacitor devices and manufacture thereof: m

20080293211 - High voltage deep trench capacitor: A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type... Agent: Hamilton & Terrile, LLP

20080293212 - Method for forming storage node of capacitor in semiconductor device: A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact... Agent: Townsend And Townsend And Crew, LLP

20080293213 - Method for preparing a shallow trench isolation: A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher... Agent: Wpat, PC Intellectual Property Attorneys

20080293214 - Method of fabricating trench-constrained isolation diffusion for semiconductor devices: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density... Agent: Patentability Associates

20080293215 - Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions: Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a... Agent: Harness, Dickey & Pierce, P.L.C

20080293216 - Method of manufacturing an inkjet head through the anodic bonding of silicon members: In a method of manufacturing an inkjet head, a silicon dioxide (SiO2) layer is produced on the surface of first silicon member formed from single-crystal silicon. Next, a glass layer formed of borosilicate glass or the like is sputtered onto the surface of the silicon dioxide (SiO2) layer. A silicon... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080293217 - Semiconductor substrates having useful and transfer layers: A method of fabricating composite substrates by associating a plurality of transfer layers in spaced relation upon a single intermediate support; providing a support layer on each transfer layer to form a composite substrate; and detaching the composite substrates from the intermediate support. The support layer is made of a... Agent: Winston & Strawn LLP Patent Department

20080293218 - Wafer dividing method: A wafer dividing method is provided that includes a protective plate sticking step of sticking the face of the wafer to the face of a protective plate by a pressure sensitive adhesive material whose adhesive force is decreased by an external stimulus; a degeneration layer formation step of throwing a... Agent: Greenblum & Bernstein, P.L.C

20080293219 - Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer: The metal wirings of the uppermost layer are exposed so as to be contactable to the probe and arranged so as to be spatially separated from one another via spaces that are approximately parallel to the longitudinal direction of the dicing area, and the position and size of the space... Agent: Mcdermott Will & Emery LLP

20080293220 - Wafer dividing method: A method of dividing a wafer having a plurality of dividing lines which are formed in a lattice pattern on the front surface, into individual chips along the dividing lines, the method comprising a wafer affixing step for affixing the front surface of the wafer to the front surface of... Agent: Smith, Gambrell & Russell

20080293221 - Method for holding semiconductor wafer: m

20080293222 - Method for forming silicon-germanium epitaxial layer: A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the total process time for forming the SiGe epitaxial layer. Then, a second SEG process is performed under a second condition, consuming about 99%... Agent: Jianq Chyun Intellectual Property Office

20080293223 - Method for manufacturing strained silicon: In accordance with a particular embodiment of the present invention, a method for manufacturing strained silicon is provided. In one embodiment, the method for manufacturing strained silicon includes inducing a curvature in a silicon wafer, depositing an epitaxial layer of silicon upon an upper surface of the silicon water while... Agent: Texas Instruments Incorporated

20080293224 - Method of forming a diode and method of manufacturing a phase-change memory device using the same: In a method of forming a diode, a first amorphous thin film doped with first impurities is formed on a single crystalline substrate. A second amorphous thin film doped with second impurities is formed on the first amorphous thin film. A laser beam having sufficient energy to melt both of... Agent: Myers Bigel Sibley & Sajovec

20080293225 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device including a first conductive type impurity region formed by introducing a first conductive type impurities in a first region of a semiconductor region and heating the first region, a second conductive type impurity region formed by introducing a second conductive type impurities in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080293227 - Method for forming gate electrode of semiconductor device: Provided is a method for forming a gate electrode of a semiconductor device which can form a gate electrode having a fine line width. Disclosed method steps include forming a gate oxide film, a polysilicon film for a gate electrode, and a first sacrificial layer on the entire surface of... Agent: Workman Nydegger

20080293226 - Semiconductor device and manufacturing method therefor: A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film; forming a mask material so as to expose an upper surface of the first gate electrode while keeping... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080293228 - Cmos compatible method of forming source/drain contacts for self-aligned nanotube devices: A method is provided for forming metal contacts to nanotube devices in a standard CMOS process flow. In accordance with one feature, a method for forming source/drain contacts to nanotube devices acting as FETs is provided while minimizing metal contamination to the complementary metal oxide semiconductor (CMOS) circuitry in a... Agent: Greenberg Traurig LLP (la)

20080293229 - Semiconductor device and manufacturing method of the same: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor... Agent: Stanley P. Fisher Reed Smith LLP

20080293230 - Method of manufacturing a semiconductor device: A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080293231 - Method for forming electrode for group-iii nitride compound semiconductor light-emitting devices: A method for forming an electrode for Group-III nitride compound semiconductor light-emitting devices includes a step of forming a first electrode layer having an average thickness of less than 1 nm on a Group-III nitride compound semiconductor layer, the first electrode layer being made of a material having high adhesion... Agent: Mcginn Intellectual Property Law Group, PLLC

20080293233 - Post last wiring level inductor using patterned plate process: A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed... Agent: Schmeiser, Olsen & Watts

20080293232 - Standoff height improvement for bumping technology using solder resist: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond... Agent: Quarles & Brady LLP

20080293234 - Semiconductor device and manufacturing method of the same: A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080293235 - Compound wirebonding and method for minimizing integrated circuit damage: A method is provided for creating a compound bond in a wire bonding process. The method includes forming a free air ball (804) at a first end (702) of a bonding wire (602). The method also includes determining a dimension and/or a shape of an anchored ball (406) disposed on... Agent: Harris Corporation C/o Darby & Darby PC

20080293236 - Method of manufacturing chip integrated substrate: There are provided the steps of connecting a chip component 13 to a first substrate 10 through wire bonding, providing, on a second substrate 20, an electrode 21 having a solder coat 23 coated with a copper core 22, polishing a portion of the electrode 21 which is to be... Agent: Drinker Biddle & Reath (dc)

20080293237 - Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole: A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first insulating film is prepared on a substrate, and a layer is disposed on the above-described first insulating... Agent: Fitzpatrick Cella Harper & Scinto

20080293238 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080293239 - Interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment: A first conductive layer is formed. An insulating layer is formed so that at least a part of the insulating layer is disposed on the first conductive layer. A second conductive layer is formed so that at least a part of the second conductive layer is disposed on the insulating... Agent: Oliff & Berridge, PLC

20080293241 - Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same: First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer... Agent: F. Chau & Associates, LLC

20080293240 - Manufacturing method of a silicon carbide semiconductor device: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film... Agent: Rossi, Kimms & Mcdowell LLP.

20080293242 - Metal spacer in single and dual damascene processing: A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080293243 - Prevention and control of intermetallic alloy inclusions: In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of... Agent: The Law Offices Of Robert J. Eichelburg

20080293244 - Methods of positioning and/or orienting nanostructures: Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures,... Agent: Nanosys Inc.

20080293245 - Semiconductor device and manufacturing method thereof: A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first... Agent: Volentine & Whitt PLLC

20080293246 - Vertical fet with nanowire channels and a silicided bottom contact: A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.... Agent: Scully, Scott, Murphy & Presser, P.C.

20080293247 - Semiconductor device and method of manufacturing the same: An object of the invention is to provide a semiconductor device which includes a barrier metal having high adhesiveness and diffusion barrier properties and a method of manufacturing the semiconductor device. The invention provides a semiconductor device manufacturing method including forming a first layer made of a material containing silicon... Agent: Young & Thompson

20080293248 - Method of forming amorphous carbon film and method of manufacturing semiconductor device using the same: Further, a small amount of reaction by-product is generated during a deposition process, and it is possible to easily remove reaction by-products that are attached on the inner wall of a chamber. For this reason, it is possible to increase a cycle of a process for cleaning a chamber, and... Agent: Marger Johnson & Mccollom, P.C.

20080293249 - In-situ photoresist strip during plasma etching of active hard mask: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma... Agent: Beyer Law Group LLP

20080293250 - Deep anisotropic silicon etch method: m

20080293251 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device in which a first hole and a second hole having a lower aspect ratio than the first hole are formed in an insulating film formed on a semiconductor substrate is provided. The method includes: performing a first etching process configured to etch the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080293252 - Resist removing method and resist removing apparatus: In an inventive resist removing method, sulfuric acid and hydrogen peroxide water are supplied to a surface of a substrate to remove a resist from the substrate surface. Thereafter, hydrogen peroxide water is supplied to the substrate surface to remove the sulfuric acid from the substrate surface.... Agent: Ostrolenk Faber Gerb & Soffen

20080293253 - Wet etching of the edge and bevel of a silicon wafer: An apparatus and method used to selectively etch materials from the edge and bevel areas of a silicon wafer are provided. In one configuration, a bevel etch spin chuck, for use in a device for removing unwanted material from an edge and bevel area of a wafer, includes a fluid... Agent: John W. Goldschmidt, Jr. Esquire Dilworth Paxon LLP

20080293254 - Single-wafer process for fabricating a nonvolatile charge trap memory device: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber... Agent: Cypress/blakely

20080293255 - Radical oxidation process for fabricating a nonvolatile charge trap memory device: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking Dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a... Agent: Cypress/blakely

20080293256 - Method for forming bismuth titanium silicon oxide thin film: A bismuth titanium silicon oxide having a pyrochlore phase, a thin film formed of the bismuth titanium silicon oxide, a method for forming the bismuth-titanium-silicon oxide thin film, a capacitor and a transistor for a semiconductor device including the bismuth-titanium-silicon oxide thin film, and an electronic device employing the capacitor... Agent: Lee & Morse, P.C.

20080293257 - Dual liner capping layer interconnect structure: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer... Agent: International Business Machines Corporation Dept. 18g

20080293258 - Crystallization apparatus and crystallization method: A crystallization apparatus is provided. The crystallization apparatus includes a visible light source capable of obtaining high energy density output therein. A visible light irradiation system is formed by a plurality of visible laser beam sources arranged in a two-dimensional array. The visible light irradiation system includes a light intensity... Agent: J C Patents, Inc.

20080293259 - Method of forming metal/high-k gate stacks with high mobility: The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate... Agent: Scully, Scott, Murphy & Presser, P.C.

20080286883 - Dry etching method and production method of magnetic memory device: Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry... Agent: Rader Fishman & Grauer PLLC

20080286884 - Method for in-situ repairing plasma damage and method for fabricating transistor device: A method for in-situ repairing plasma damage, suitable for a substrate, is provided. A component is formed on the substrate. The formation steps of the component include a main etching process containing plasma. The method involves performing a soft plasma etching process in the apparatus of the main etching process... Agent: J C Patents, Inc.

20080286885 - Methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the... Agent: Baker & Mckenzie LLP

20080286887 - Method for adjusting a transistor model for increased circuit simulation accuracy: According to one exemplary embodiment, a method for adjusting a transistor model for increased circuit simulation accuracy includes determining a first gate CD offset by matching a C-V test structure having a normalized channel current to an I-V test structure having the normalized channel current. The method further includes utilizing... Agent: Farjami & Farjami LLP

20080286886 - Monitoring cool-down stress in a flip chip process using monitor solder bump structures: A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more... Agent: Schmeiser, Olsen & Watts

20080286888 - Test structures and methodology for detecting hot defects: Test structures for detecting defects arising from hybrid orientation technology (HOT) through detection of device leakage (gate leakage, junction leakage, and sub-threshold leakage), having at least one active region disposed in a re-grown region of a substrate: a layer of oxide; a layer of poly. Some test structures are dog-bone... Agent: International Business Machines Corporation Dept. 18g

20080286890 - Liquid crystal display device and method of fabricating the same: A liquid crystal display device including a first substrate, a second substrate facing and spaced away from the first substrate, a liquid crystal layer sandwiched between the first and second substrates, a switching device formed on the first substrate, a first electrically insulating film randomly patterned on the first substrate,... Agent: Young & Thompson

20080286889 - Manufacturing method of liquid crystal display: A method of manufacturing a liquid crystal display at a reduced cost is presented. The method entails: preparing an insulating substrate; forming a gate line and a data line on the insulating substrate to define a pixel area; forming a thin film transistor at an intersection of the gate line... Agent: Macpherson Kwok Chen & Heid LLP

20080286891 - Wiring and manufacturing method thereof, semiconductor device comprising said wiring, and dry etching method: A dry etching method for forming tungsten wiring having a tapered shape and having a large specific selectivity with respect to a base film is provided. If the bias power density is suitably regulated, and if desired portions of a tungsten thin film are removed using an etching gas having... Agent: Cook Alex Ltd

20080286893 - Light emitting device having protrusion and recess structure and method of manufacturing the same: The semiconductor light emitting device having a protrusion and recess structure includes: a lower clad layer disposed on a substrate; an active layer formed on one portion of a top surface of the lower clad layer; an upper clad layer formed on the active layer; a first electrode formed on... Agent: Buchanan, Ingersoll & Rooney PC

20080286892 - Method for fabricating three-dimensional photonic crystal: A method for fabricating a three-dimensional photonic crystal comprises the steps of: forming a dielectric thin film; injecting ions selectively into the dielectric thin film by using a focus ion beam to form a mask on the dielectric thin film; forming a pattern by selectively removing an exposed part of... Agent: Fitzpatrick Cella Harper & Scinto

20080286894 - Gallium nitride based semiconductor light emitting diode and process for preparing the same: A process for preparing a gallium nitride based semiconductor light emitting diode includes the step of: providing a substrate for growing a gallium nitride based semiconductor material; forming a lower clad layer on the substrate using a first conductive gallium nitride based semiconductor material; forming an active layer on the... Agent: Lowe Hauptman Ham & Berner, LLP

20080286895 - Method of manufacturing an organic device: A method of manufacturing an organic device includes the following steps. The first step is a step of forming a plurality of organic elements in the form of a matrix on a brittle substrate. Each of the organic elements is provided with an electrically connecting portion which electrically connects the... Agent: Morgan & Finnegan, L.L.P.

20080286896 - Method for manufacturing image sensor: A method for manufacturing an image sensor including forming an interlayer dielectric layer on a substrate including a photo diode; forming a color filter layer on the interlayer dielectric layer; forming an oxide film on the color filter layer; forming a plurality of micro lens patterns spaced apart on the... Agent: Sherr & Vaughn, PLLC

20080286897 - Method for manufacturing image sensor: Provided is a method for manufacturing an image sensor. In the method, a microlens is formed from an oxide layer. The oxide layer used for the microlenses can be formed using a nitrogen gas as dopant. A plurality of photoresist patterns can be formed on the oxide layer, and the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080286898 - Material composition having core-shell microstructure used for varistor: A material composition having a core-shell microstructure suitable for manufacturing a varistor having outstanding electrical properties, the core-shell microstructure of the material composition at least comprising a cored-structure made of a conductive or semi-conductive material and a shelled-structure made from a glass material to wrap the cored-structure, and electrical properties... Agent: Bacon & Thomas, PLLC

20080286899 - Method for manufacturing semiconductor device and method for manufacturing system-in-package using the same: A method for manufacturing a semiconductor device and a method for manufacturing a system-in-package using the same, which are capable of enhancing reliability and the step coverage for a trench having a high aspect ratio. The semiconductor manufacturing method includes forming a first insulating film over a substrate; and then... Agent: Sherr & Vaughn, PLLC

20080286900 - Method for adhering semiconductor devices: A method for adhering semiconductor devices is provided. The method includes forming a first semiconductor device including a first metal pad, forming a second semiconductor device including a second metal pad, adhering the first semiconductor device to the second semiconductor device, the first metal pad electrically connecting the second metal... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080286901 - Method of making integrated circuit package with transparent encapsulant: A method for making an IC package with transparent encapsulant includes providing a leadframe, where the leadframe includes a first die pad and a second die pad, disposing a first die on the first die pad and a second die on the second die pad, forming a cavity on the... Agent: Townsend And Townsend And Crew, LLP

20080286902 - Method of manufacturing a semiconductor device: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing... Agent: Miles & Stockbridge PC

20080286903 - Semiconductor device packaged into chip size and manufacturing method thereof: A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080286904 - Method for manufacturing semiconductor package: Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the... Agent: Staas & Halsey LLP

20080286905 - Fin-type antifuse: A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080286906 - Stacked bit line dual word line nonvolatile memory: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines... Agent: Kenton R. Mullins Stout, Uxa, Buyan & Mullins, LLP

20080286907 - Semiconductor layer for thin film transistors: A method for making a zinc oxide semiconductor layer for a thin film transistor using solution processing at low temperatures is disclosed. The method comprises making a solution comprising a zinc salt and a complexing agent; applying the solution to a substrate; and heating the solution to form a semiconductor... Agent: Fay Sharpe / Xerox - Rochester

20080286908 - Method of producing a semiconductor element in a substrate: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the... Agent: Slater & Matsil LLP

20080286911 - Method for manufacturing semiconductor device: To provide a low-cost high performance semiconductor device and a method for manufacturing the semiconductor device, a separate single-crystal semiconductor layer having a first region and a non-single-crystal semiconductor layer having a second region are provided over a substrate. Further, it is preferable that a cap film is formed over... Agent: Eric Robinson

20080286910 - Method for manufacturing soi substrate and method for manufacturing semiconductor device: A method for manufacturing an SOI substrate with favorable adherence without high-temperature heat treatment being performed in bonding, and a semiconductor device using the SOI substrate and a manufacturing method thereof are proposed. An SOI substrate and a semiconductor device can be manufactured by forming a single-crystalline silicon substrate with... Agent: Eric Robinson

20080286909 - Sidewall semiconductor transistors: A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The gate dielectric region is sandwiched between the semiconductor... Agent: Schmeiser, Olsen & Watts

20080286912 - Semiconductor device and method for fabricating the same: A semiconductor device in which a semiconductor layer of a thin film transistor and a first electrode of a capacitor are formed of amorphous silicon and the whole or a part of source/drain regions of the semiconductor layer and the first electrode of the capacitor are crystallized by a metal... Agent: H.c. Park & Associates, PLC

20080286913 - Field effect transistor with raised source/drain fin straps: Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080286914 - Display device, method of production of the same, and projection type display device: A display device able to raise a light resistance of pixel transistors without depending upon a light shielding structure and a method of production of same, wherein an average crystal grain size of a polycrystalline silicon film 111 forming an active layer of the pixel transistors is controlled to be... Agent: Robert J. Depke Lewis T. Steadman

20080286915 - Metal-oxide-semiconductor high electron mobility transistors and methods of fabrication: A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described.... Agent: Kathy Manke Avago Technologies Limited

20080286916 - Methods of stressing transistor channel with replaced gate: Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of... Agent: Hoffman Warnick LLC

20080286917 - Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20080286918 - Methods for fabricating semiconductor structures with backside stress layers: Methods for fabricating semiconductor structures with backside stress layers are provided. In one exemplary embodiment, the method comprises the steps of providing a semiconductor device formed on and within a front surface of a semiconductor substrate. The semiconductor device comprises a channel region. A plurality of dielectric layers is formed... Agent: Ingrassia Fisher & Lorenz, P.C.

20080286919 - Tunnel and gate oxide comprising nitrogen for use with a semiconductor device and a process for forming the device: A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and... Agent: Kevin D. Martin Mail Stop 1-525

20080286920 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. The method includes forming a negative photoresist layer on a semiconductor substrate, forming a photoresist pattern on the negative photoresist layer, forming a well region in the semiconductor substrate, implanting ions into the semiconductor substrate, using the photoresist pattern as a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080286921 - Methods of forming silicides of different thicknesses on different structures: The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing... Agent: Winstead PC

20080286923 - Method for fabricating flash memory: A method for fabricating a flash memory device is disclosed that can improve the reliability of the device by counteracting against the generation of charge traps induced by interfacial damage of an oxide film during the formation of spacers. The method may comprise forming spacers comprised of an oxide film... Agent: Workman Nydegger

20080286922 - Method of fabricating semiconductor device: In one example embodiment, a method of fabricating a semiconductor device includes various steps. First, an isolation film is formed on a semiconductor substrate to define a field region and an active region. Then, a stack gate structure is formed. Next, a first photoresist and a second photoresist are sequentially... Agent: Workman Nydegger

20080286924 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second... Agent: Amin, Turocy & Calvin, LLP

20080286925 - Nonvolatile memory with backplate: The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common.... Agent: Macpherson Kwok Chen & Heid LLP

20080286926 - Bit line of a semiconductor device and method for fabricating the same: A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film... Agent: Townsend And Townsend And Crew, LLP

20080286927 - Non-volatile memory device with buried control gate and method of fabricating the same: In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a... Agent: Mills & Onello LLP

20080286928 - method of manufacturing a semiconductor integrated circuit device: In the chip with which a plurality of MISFET from which threshold value voltage differs is intermingled, leakage current, such as GIDL current and BTBT current, is suppressed, inhibiting the short channel effect of MISFET. The concentration of the impurity for threshold value voltage adjustment implanted to the region in... Agent: Miles & Stockbridge PC

20080286929 - Method for manufacturing semiconductor device: The method for manufacturing a semiconductor device according to the invention includes the first doping step of doping source/drain regions including source/drain extension regions adjacent to a channel region of a MOS transistor, the second doping step of doping pocket implant regions disposed from the bottom of the source/drain extension... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080286930 - Nitride-encapsulated fet (nncfet): A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention... Agent: Scully, Scott, Murphy & Presser, P.C.

20080286931 - Semiconductor device including field-effect transistor using salicide (self-aligned silicide) structure and method of fabricating the same: An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the semiconductor substrate in the element region. A gate electrode is formed on the gate insulating film. Source/drain regions are... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080286932 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device may include the steps of: forming a doped polysilicon film by implanting or incorporating dopant ions simultaneously with forming a silicon film; forming a doped polysilicon pattern by patterning the doped polysilicon film; forming a spacer on sides of the doped polysilicon pattern;... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080286933 - Integrated circuit inductor with integrated vias: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the... Agent: Texas Instruments Incorporated

20080286934 - Method of forming a trench capacitor: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the... Agent: Ingrassia Fisher & Lorenz, P.C.

20080286935 - Method of fabricating an isolation shallow trench: A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and... Agent: North America Intellectual Property Corporation

20080286936 - Method for preparing a shallow trench isolation: A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher... Agent: Wpat, PC Intellectual Property Attorneys

20080286937 - Manufacturing method for bonded wafer: In a first ion implantation step (a1), a delamination-intended ion implantation layer 3 is formed by implanting ions at a dosage less than a critical dosage from the insulating film 2 side of a bond wafer 1. In an additional function layer deposition step (b2), an additional function layer 4... Agent: Snider & Associates

20080286939 - Method for manufacturing soi substrate: An object is to provide a method for manufacturing an SOI substrate, by which defective bonding can be prevented. An embrittled layer is formed in a region of a semiconductor substrate at a predetermined depth; an insulating layer is formed over the semiconductor substrate; the outer edge of the semiconductor... Agent: Eric Robinson

20080286941 - Method of manufacturing a semiconductor device: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the... Agent: Eric Robinson

20080286942 - Method of manufacturing a semiconductor device: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the... Agent: Eric Robinson

20080286940 - Process for production of soi substrate and process for production of semiconductor device: A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor... Agent: Nixon Peabody, LLP

20080286938 - Semiconductor device and fabrication methods thereof: A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080286944 - Method to manufacture a silicon wafer electronic component protected against the attacks and such a component: In general, the invention relates to manufacturing a wafer. The method includes manufacturing a wafer that includes a front side and a back side, thinning the wafer down to a thickness suitable for an intended operation of the wafer, polarizing the substrate wafer from the back side, and cutting the... Agent: Osha Liang L.L.P.

20080286943 - Motherboard cutting method, motherboard scribing apparatus, program and recording medium: A mother substrate cutting method for cutting a plurality of unit substrates out of a mother substrate, comprises the steps of: (a) forming scribe lines on the mother substrate by scribe forming means; and (b) breaking the mother substrate along the scribe lines, wherein the step (a) includes a step... Agent: Snell & Wilmer L.L.P. (main)

20080286945 - Controlled process and resulting device: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define... Agent: Townsend And Townsend And Crew, LLP

20080286948 - Fabrication method of semiconductor integrated circuit device: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080286947 - Process for separating disk-shaped substrates with the use of adhesive powers: The present invention relates to a device and a method for dividing up substrates (2) in wafer form (e.g. wafers), which is used in the semiconductor industry, MST (microstructure technology) industry and photovoltaic industry, whereby improved reliability of the process and lower reject rates are accomplished. This object is achieved... Agent: Mcglew & Tuttle, PC

20080286946 - Wafer dicing method: A wafer stacked on a mounting layer is safely diced. The mounting layer has holes partially corresponding to chips on the wafer. Thus, chips obtained after dicing the wafer can be safely removed from the mounting tape. An amount of the mounting tape used can be reduced. And a production... Agent: Troxell Law Office PLLC

20080286949 - Method of forming a rare-earth dielectric layer: Methods for forming compositions comprising a single-phase rare-earth dielectric disposed on a substrate are disclosed. In some embodiments, the method forms a semiconductor-on-insulator structure. Compositions and structures that are formed via the method provide the basis for forming high-performance devices and circuits.... Agent: Demont & Breyer, LLC

20080286950 - Semiconductor device and method for manufacturing the same: A semiconductor device using a crystalline semiconductor film is manufactured. The crystalline semiconductor film is formed by providing an amorphous silicon film with a catalyst metal for promoting a crystallization thereof and then heated for performing a thermal crystallization, following which the crystallized film is further exposed to a laser... Agent: Nixon Peabody, LLP

20080286951 - Semiconductor wafer with an epitaxially deposited layer, and process for producing the semiconductor wafer: A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes... Agent: Brooks Kushman P.C.

20080286952 - Manufacturing method of soi substrate and manufacturing method of semiconductor device: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base... Agent: Eric Robinson

20080286953 - Manufacturing method of semiconductor substrate, thin film transistor and semiconductor device: In manufacturing an SOI substrate, in a case where a step is present in a surface to be bonded, a substrate may warp and the contact area becomes small due to the step, an SOI layer having a desired shape cannot be obtained in some cases. However, the present invention... Agent: Eric Robinson

20080286954 - Method of forming pattern of semiconductor device: A method of forming a pattern of a semiconductor device comprises forming a first hard mask film, a first resist film, and a second hard mask film over an underlying layer of a semiconductor substrate; forming a second resist pattern over the second hard mask film; etching the second hard... Agent: Marshall, Gerstein & Borun LLP

20080286955 - Fabrication of recordable electrical memory: A memory cell of a memory device is fabricated by forming a first electrode on a substrate, positioning a photo mask at a first position relative to the substrate, and forming a first material layer on the first electrode based on a pattern on the photo mask. The photo mask... Agent: Occhiuti Rohlicek & Tsao, LLP

20080286956 - Method of manufacturing a semiconductor device: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the... Agent: Eric Robinson

20080286957 - Method forming epitaxial silicon structure: A method of forming an epitaxial silicon structure is disclosed. The method includes performing a first epitaxial growth process using a first source gas including silicon (Si) and hydrogen chloride (HCl) to form a first epitaxial silicon layer on a substrate, and performing a second epitaxial growth process using a... Agent: Volentine & Whitt PLLC

20080286958 - Semiconductor substrate having enhanced adhesion and method for manufacturing the same: A semiconductor substrate for having enhanced adhesion to semiconductor device and its manufacturing method are provided. The wire circuit layout on the surface of the semiconductor substrate is of a specialized design and surface treatment for enhanced adhesion between the packaged adhered material and the substrate surface (the bonding pad... Agent: Lin & Associates Intellectual Property, Inc.

20080286959 - Downhill wire bonding for qfn l - lead: s

20080286960 - Method of manufacturing semiconductor device suitable for forming wiring using damascene method: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080286961 - Semiconductor device manufacturing method: A semiconductor device manufacturing method includes: forming a via pattern in an insulating film by use of an alignment mark of a lower wiring line; forming, by use of an alignment mark of the via pattern, an upper wiring groove pattern in an upper insulating film in which the via... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080286962 - Method for fabricating metal pad: A method for fabricating a metal pad is disclosed. The fabrication method includes the step of selectively etching a wire insulation film formed on a semiconductor substrate to form a pattern, such as a dual damascene pattern, having plural vias in one trench. A metal film is deposited to fill... Agent: Workman Nydegger

20080286963 - Method for producing through-contacts in semi-conductor wafers: The invention relates to a method for producing vertical through-contacts (micro-vias) in semi-conductor wafers in order to produce semi-conductor components, i.e. contacts on the front side of the wafer through the semi-conductor wafer to the rear side of the wafer. The invention also relates to a method which comprises the... Agent: Thelen LLP

20080286964 - Semiconductor device and a method of manufacturing the same: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching... Agent: Miles & Stockbridge PC

20080286965 - Novel approach for reducing copper line resistivity: A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to... Agent: Slater & Matsil, L.L.P.

20080286966 - Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment: A new technique is disclosed in which a barrier/cap layer for a copper based metal line is formed by using a thermal-chemical treatment based on hydrogen with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma based deposition of silicon based dielectric barrier... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080286967 - Method for fabricating a body to substrate contact or topside substrate contact in silicon-on-insulator devices: A method of forming an electrical contact between an active semiconductor device layer and a base substrate. The method includes forming a first masking layer over an uppermost surface of the active semiconductor layer, patterning a window in the masking layer, and etching an opening down to the base substrate... Agent: Schwegman, Lundberg & Woessner / Atmel

20080286968 - Solderable top metal for silicon carbide semiconductor devices: A silicon carbide device includes at least one power electrode on a surface thereof, a solderable contract formed on the power electrode, and at least one passivation layer that surrounds the solderable contact but is spaced from the solderable contract, thereby forming a gap.... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20080286971 - Cmos gate structures fabricated by selective oxidation: A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges... Agent: International Business Machines Corporation Dept. 18g

20080286970 - Method for producing a semiconductor component and a semiconductor component produced according to the method: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the... Agent: Kenyon & Kenyon LLP

20080286969 - Patterning methods: The invention includes a template comprising one or both of Cbs and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent material, and the desired pattern can include two or more separated segments. The template can be utilized for patterning a plurality... Agent: Krupakar M. Subramanian

20080286972 - Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar... Agent: Law Office Of Delio & Peterson, LLC.

20080286974 - Etching solution for multiple layer of copper and molybdenum and etching method using the same: An etching solution for a multiple layer of copper and molybdenum includes: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by... Agent: Mckenna Long & Aldridge LLP

20080286973 - Method for forming semiconductor fine-pitch pattern: A method for forming a fine-pitch pattern on a semiconductor substrate is provided. The method includes patterning the semiconductor substrate to form a plurality of fine lines, forming a thermal oxide layer on the fine lines, polishing the thermal oxide layer to expose a top surface of the fine lines;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080286975 - Platinum nanodet etch process: A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a... Agent: Dinsmore & Shohl LLP

20080286976 - Method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process and etching method: A method of removing a metal suicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing... Agent: North America Intellectual Property Corporation

20080286977 - Process to open carbon based hardmask overlying a dielectric layer: A method of opening a carbon-based hardmask layer composed of amorphous carbon containing preferably at least 60% carbon and between 10 and 40% hydrogen. The hardmask is opened by plasma etching using an etching gas composed of H2, N2, and CO. The etching is preferably performed in a plasma etch... Agent: Applied Materials, Inc. Patent/legal Dept., M/s 2061

20080286978 - Etching and passivating for high aspect ratio features: An etch method includes etching a masked substrate to form a recess with a first sidewall in the substrate. A thin surface layer of the substrate on the first sidewall is then converted into a passivation layer. The masked substrate is etched again to deepen the recess in the substrate.... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20080286979 - Method of controlling sidewall profile by using intermittent, periodic introduction of cleaning species into the main plasma etching species: A method of removing a silicon-containing hard polymeric material from an opening leading to a recessed feature during the plasma etching of said recessed feature into a carbon-containing layer in a semiconductor substrate. The method comprises the intermittent use of a cleaning step within a continuous etching process, where at... Agent: Shirley L. Church, Esq.

20080286980 - Substrate processing apparatus and semiconductor device producing method: Disclosed is a substrate processing apparatus, including: a processing container; a gas supply section to supply a desired processing gas to the processing container; a gas exhaust section to exhaust a surplus of the processing gas from the processing container; a substrate placing member to place a plurality of substrates... Agent: Birch Stewart Kolasch & Birch

20080286981 - In situ silicon and titanium nitride deposition: A method of processing semiconductor wafers is provided, comprising loading a batch of semiconductor wafers into a processing chamber; depositing titanium nitride (TiN) onto the wafers in the processing chamber; and depositing silicon onto the wafers in the processing chamber, without removing the wafers from the processing chamber between said... Agent: Knobbe Martens Olson & Bear LLP

20080286982 - Plasma immersion ion implantation with highly uniform chamber seasoning process for a toroidal source reactor: A method is provided for performing plasma immersion ion implantation with a highly uniform seasoning film on the interior of a reactor chamber having a ceiling and a cylindrical side wall and a wafer support pedestal facing the ceiling. The method includes providing a gas distribution ring with plural gas... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20080286983 - Deposition of ta- or nb-doped high-k films: Methods and compositions for depositing high-k films are disclosed herein. In general, the disclosed methods utilize precursor compounds comprising Ta or Nb. More specifically, the disclosed precursor compounds utilize certain ligands coupled to Ta and/or Nb such as 1-methoxy-2-methyl-2-propanolate (mmp) to increase volatility. Furthermore, methods of depositing Ta or Nb... Agent: Air Liquide Intellectual Property

20080286984 - Silicon-rich low-hydrogen content silicon nitride film: In one embodiment, a method for forming a silicon nitride film is provided. The method includes providing a plasma-enhanced chemical vapor deposition (PECVD) reactor with a semiconductor substrate therein; flowing a gas mixture consisting of silane and nitrogen into the PECVD reactor; and forming a plasma in the PECVD reactor,... Agent: Macpherson Kwok Chen & Heid LLP

20080280379 - Method of manufacturing thin film transistor substrate and manufacturing system using the same: Provided is a method of manufacturing a thin film transistor substrate and a manufacturing system using the same, wherein the production of corrosive substances is reduced during the process of manufacturing the thin film transistor substrate. The method includes providing an etching unit with an insulation substrate on which a... Agent: H.c. Park & Associates, PLC

20080280380 - Fluid storage and dispensing system including dynamic fluid monitoring of fluid storage and dispensing vessel: A monitoring system (100) for monitoring fluid in a fluid supply vessel (22, 24, 26, 28, 108) during operation including dispensing of fluid from the fluid supply vessel. The monitoring system includes (i) one or more sensors (114, 126) for monitoring a characteristic of the fluid supply vessel or the... Agent: Intellectual Property / Technology Law

20080280381 - Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on... Agent: Lee & Morse, P.C.

20080280382 - Wafer-level test module for testing image sensor chips, the related test method and fabrication: A wafer-level test module is disclosed to include a base layer having multiple first apertures spaced from one another at a pitch corresponding to the pitch of the image sensor chips of an integrated circuit wafer, a cover layer having second apertures respectively axially aimed at the first apertures, and... Agent: Bacon & Thomas, PLLC

20080280383 - Method of real-time monitoring implantation: A method of real-time monitoring implantation includes plotting a calibration curve for monitoring implantation first. Next, a testing substrate covered a photoresist is provided and then implanted. Since photoresist surface roughness will be changed after implantation, surface roughness change could be quantitatively determined by monitoring scattering light. Finally, the detected... Agent: Rosenberg, Klein & Lee

20080280384 - Solid-state light emitting display and fabrication method thereof: A solid-state light emitting display and a fabrication method thereof are proposed. The light emitting display includes a metallic board formed with conductive circuits, and a plurality of luminous microcrystals disposed on a surface of the metallic board and electrically connected to the conductive circuits. The metallic board provides the... Agent: Rabin & Berdo, PC

20080280385 - Thin-film transistor, tft-array substrate, liquid-crystal display device and method of fabricating the same: A thin-film transistor includes a gate layer, a gate insulting layer, a semiconductor layer, a drain layer, a passivation layer (each of which being formed on or over an insulating substrate), and a conductive layer formed on the passivation layer. The conductive layer is connected to the gate layer or... Agent: Mcginn Intellectual Property Law Group, PLLC

20080280386 - Method for manufacturing semiconductor optical device: A method for manufacturing an laser diode includes: providing a wafer having thereon a semiconductor structure; depositing an SiO2 film; forming channels and a waveguide ridge between the channels in the wafer; forming an SiO2 film over the wafer; forming a resist pattern covering the SiO2 film in the channels... Agent: Leydig Voit & Mayer, Ltd

20080280387 - Layout design and fabrication of sda micro motor for low driving voltage and high lifetime application: Provided is a new design and fabrication of scratch drive actuator (SDA) micro rotary motor with low driving voltage and high lifetime characteristics. To substantially reduce the driving voltage from 30˜150 Vo-p to 12˜30 Vo-p ac amplitude, a silicon wafer with very low resistivity (<0.004 Ω-cm) was firstly adopted as... Agent: Bacon & Thomas, PLLC

20080280388 - Ccd type solid-state imaging device and method for manufacturing the same: A CCD type solid-state imaging device is provided and includes: photodiodes (PD) in a light receiving area of a semiconductor substrate; vertical charge transfer paths; a horizontal charge transfer path; channel stops including linear high density impurity regions for separating mutually adjoining sets from each other, each set including a... Agent: Birch Stewart Kolasch & Birch

20080280389 - Camera module and method for assembling same: A method for assembling a camera module includes following steps: providing a circuit board having a connecting region; disposing a liquid anisotropic conductive adhesive on the connecting region of the circuit board; placing an image sensor module, on the connecting region of the circuit board; thermal press-bonding the image sensor... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080280390 - Method of fabricating semiconductor memory device having self-aligned electrode, related device and electronic system having the same: A method of fabricating a semiconductor memory device having a self-aligned electrode is provided. An interlayer insulating layer having a contact hole is formed on a substrate. A phase change pattern partially filling the contact hole is formed. A bit line which includes a bit extension self-aligned to the phase... Agent: Marger Johnson & Mccollom, P.C.

20080280391 - Methods of manufacturing mos transistors with strained channel regions: In some methods of manufacturing transistors, a gate electrode and a gate insulation layer pattern are stacked on a substrate. Impurity regions are formed at portions of the substrate that are adjacent to the gate electrode by implanting Group III impurities into the portions of the substrate. A diffusion preventing... Agent: Myers Bigel Sibley & Sajovec

20080280392 - Convex die attachment method: A method for assembling a microelectronic device is provided comprising the step of adhering a die to a substrate using a convex die attachment process. The convex die attachment process generally comprises a) providing a die having an underfill material thereon, b) picking up and inverting the die, c) heating... Agent: Lord Corporation Patent & Legal Services

20080280393 - Methods for forming package structures: A method for forming a semiconductor structure includes forming a first connector over at least one pad of a first substrate, the first connector having at least one curved sidewall. An encapsulation layer is formed at least partially over the first connector so as to partially expose a top surface... Agent: Duane Morris LLP (tsmc)IPDepartment

20080280395 - Semiconducting device with stacked dice: Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the substrate. The first die includes active circuitry (e.g., a flash memory array or logic circuitry) on an upper surface of the first die. The... Agent: Intel Corporation C/o Intellevate, LLC

20080280396 - Stacked die package for peripheral and center device pad layout device: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor... Agent: Trask Britt, P.C./ Micron Technology

20080280394 - Systems and methods for post-circuitization assembly: A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to... Agent: Texas Instruments Incorporated

20080280397 - Method for manufacturing strip level substrate without warpage and method for manufacturing semiconductor package using the same: A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist... Agent: Ladas & Parry LLP

20080280398 - System and method for direct bonding of substrates: A method of forming a MEMS (Micro-Electro-Mechanical System), includes forming an ambient port through a MEMS cap which defines a cavity containing a plurality of MEMS actuators therein; and bonding a lid arrangement to the MEMS cap to hermetically seal the ambient port.... Agent: Hewlett Packard Company

20080280399 - Methods for forming co-planar wafer-scale chip packages: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed... Agent: F. Chau & Associates, LLC

20080280400 - Method for manufacturing semiconductor device: A field effect transistor having a T-shaped gate electrode is formed on a GaAs substrate, and the T-shaped gate electrode of the field effect transistor is coated with a SiO2 film. A lower electrode of a MIM capacitor is formed on the GaAs substrate. The active portion of the field... Agent: Leydig Voit & Mayer, Ltd

20080280401 - Increasing effective transistor witdth in memory arrays with dual bitlines: A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the... Agent: Cantor Colburn, LLP - IBM Arc Division

20080280402 - Manufacturing method of semiconductor device and electronic device: Silicide films with high quality are formed with treatment of laser light irradiation, so that miniaturization and higher performance is achieved in a field-effect transistor that is formed over an insulating substrate and has little variation in electric characteristics. An island-shaped semiconductor film including a pair of impurity regions and... Agent: Nixon Peabody, LLP

20080280403 - Transistor fabrication method: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A... Agent: Hitt Gaines, PC Lsi Corporation

20080280404 - Residue free patterned layer formation method applicable to cmos structures: A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over... Agent: Scully, Scott, Murphy & Presser, P.C.

20080280405 - Semiconductor device: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080280406 - Semiconductor device and its manufacturing method: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080280407 - Cmos device with dual polycide gates and method of manufacturing the same: A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well... Agent: Ladas & Parry LLP

20080280408 - Semiconductor device with improved overlay margin and method of manufacturing the same: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line... Agent: Frank Chau, Esq F. Chau & Associates, LLC

20080280409 - Memory arrays, semiconductor constructions and electronic systems; and methods of forming memory arrays, semiconductor constructions and electronic systems: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region... Agent: Wells St. John P.s.

20080280411 - Method for manufacturing phase change memory device using a patterning process: A phase change memory device is made by processes including forming a first interlayer dielectric on a semiconductor substrate that has junction regions. Then etching the first interlayer dielectric and thereby defining contact holes that expose the junction regions. A conductive layer is formed on the first interlayer dielectric to... Agent: Ladas & Parry LLP

20080280410 - Self aligned narrow storage elements for advanced memory device: A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface... Agent: Amin, Turocy & Calvin, LLP

20080280412 - Method of manufacturing silicon carbide semiconductor device: Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the inter-band scattering is prevented from... Agent: Rossi, Kimms & Mcdowell LLP.

20080280413 - Methods for forming a transistor: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080280414 - Systems and methods for fabricating vertical bipolar devices: Systems and methods for fabricating bipolar and/or biCMOS devices are described. A combination of bipolar fabrication steps and CMOS, and in particular, SOI fabrication steps may be used. In one embodiment, a collector region and/or a base region of a bipolar device may be formed using a bipolar mask, and... Agent: Fulbright & Jaworski L.L.P.

20080280415 - Method of manufacturing semiconductor memory device: A method of manufacturing a semiconductor memory device of the present invention consists of a step of forming a selection transistor and a separate selection transistor and a step of forming a variable resistance element and a capacitance element, characterized by forming the variable resistance element by sequentially laminating a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080280416 - Techniques for layer transfer processing: Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method... Agent: Ryan, Mason & Lewis, LLP

20080280417 - Method for manufacturing semiconductor device: An object is to provide a method for manufacturing, with high yield, a semiconductor device having a crystalline semiconductor layer even if a substrate with low upper temperature limit. A groove is formed in a part of a semiconductor substrate to form a semiconductor substrate that has a projecting portion,... Agent: Eric Robinson

20080280418 - Method for manufacturing the shallow trench isolation structure: A method for manufacturing a shallow trench isolation (STI) structure is provided. In the method, a substrate is initially provided. Then, a patterned pad layer and a patterned mask layer are successively formed in order on the substrate. After that, a portion of the substrate is removed by using the... Agent: Jianq Chyun Intellectual Property Office

20080280419 - Method for nanostructuring of the surface of a substrate: m

20080280420 - Method for manufacturing substrate of semiconductor device: A method for manufacturing a substrate of a semiconductor device is provided, which comprises a step of forming a fragile layer in a semiconductor substrate by irradiating the semiconductor substrate with ion species, a step of forming a bonding layer over the semiconductor substrate, a step of bonding the semiconductor... Agent: Eric Robinson

20080280421 - Wafer dividing method: A wafer dividing method that includes a modifying layer forming step in which a laser beam with a wavelength that can pass through the wafer is focused on the inside of the wafer from a rear surface side thereof, and applied along the street to form a modifying layer having... Agent: Greer, Burns & Crain

20080280422 - Ultra thin bumped wafer with under-film: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond... Agent: Quarles & Brady LLP

20080280423 - Chilled wafer dicing: A method and system for dicing a wafer is disclosed. One illustrative method includes forming a layer of frozen material above a plurality of integrated circuit die on a substrate and performing a cutting process to cut through the layer of frozen material and the substrate to singulate the plurality... Agent: Wells St. John P.s.

20080280424 - Manufacturing method of soi substrate and manufacturing method of semiconductor device: After the plurality of single-crystal semiconductor layers are provided adjacent to each other with a certain distance over a glass substrate which is a support substrate, heat treatment is performed on the glass substrate. The support substrate shrinks by this heat treatment, and the adjacent single-crystal semiconductor layers are in... Agent: Eric Robinson

20080280425 - Beam homogenizer, and laser irradiation method, laser irradiation apparatus, and laser annealing method of non-single crystalline semiconductor film using the same: A rectangular beam having the energy density distribution homogenized in its short-side direction is formed in a beam homogenizer wherein two light reflection surfaces are parallel-provided in a beam progression optical waveguide with a predetermined space so as to face each other at surfaces along the beam progression direction and... Agent: Eric Robinson

20080280426 - Gallium nitride-on-silicon interface: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080280427 - Low etch pit density (epd) semi-insulating gaas wafers: A method for manufacturing wafers using a low EPD crystal growth process and a wafer annealing process is provided that results in GaAs/InGaP wafers that provide higher device yields from the wafer.... Agent: Dla Piper US LLP

20080280428 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device including heating a semiconductor substrate, has forming a cap film on a surface of said semiconductor substrate; selectively removing said cap film at least from an upper surface of an edge of said semiconductor substrate, a bevel surface of the edge of said... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080280429 - Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method: A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (103) having a horizontal surface (107) and a vertical surface (105); (b) depositing a first metal layer (109) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon (111) over the horizontal and... Agent: Fortkort & Houston P.C.

20080280430 - Method of forming films in a trench: A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric... Agent: Townsend And Townsend And Crew, LLP

20080280431 - Method of fabricating flash memory device: The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching an insulating layer for... Agent: Townsend And Townsend And Crew, LLP

20080280432 - Barrier material and process for cu interconnect: A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include... Agent: Slater & Matsil, L.L.P.

20080280434 - Enhanced mechanical strength via contacts: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of... Agent: International Business Machines Corporation Dept. 18g

20080280433 - Method for manufacturing semiconductor device: A four-layer structured hard mask composed of a SiC film, a first SiO2 film, a SiC film, and a second SiO2 film is formed on a porous silica film as an interlayer insulating film. Then, the second SiO2 film is etched with a resist mask. Subsequently, the SiC film is... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080280435 - Producing a covered through substrate via using a temporary cap layer: The present invention relates to a method for producing a substrate with at least one covered via that electrically and preferably also thermally connects a first substrate side with an opposite second substrate side. The processing involves forming a trench on a the first substrate side remains and covering the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080280436 - Method for fabricating an inductor structure or a dual damascene structure: A method for fabricating an inductor structure or a dual damascene structure is disclosed. First, a dielectric layer is provided. Subsequently, a first etching process is performed on the dielectric layer so as to form a first opening in the dielectric layer. A polymer is also formed in the first... Agent: North America Intellectual Property Corporation

20080280437 - Substrate processing method and substrate processing apparatus: A CoWB film is formed as a cap metal on a Cu interconnection line formed on a substrate or wafer W, by repeating a plating step and a post-cleaning step a plurality of times. The plating step is arranged to apply electroless plating containing CoWB onto the Cu interconnection line.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080280438 - Methods for depositing tungsten layers employing atomic layer deposition techniques: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080280439 - Optimal concentration of platinum in a nickel film to form and stabilize nickel monosilicide in a microelectronic device: A method of forming a nickel monosilicide layer on silicon-containing features of an electronic device that includes depositing a nickel film over the silicon-containing features. The nickel film is co-deposited with a selected material. The selected material has an atomic percentage in a range of about 10% to 25%. A... Agent: Schwegman, Lundberg & Woessner / Atmel

20080280440 - Method for forming a pn diode and method of manufacturing phase change memory device using the same: Disclosed is a method of forming a PN diode and a method of manufacturing a phase change memory device using the same. Formation of a PN diode includes forming a first conductivity type region in a surface of a semiconductor substrate. A polysilicon layer doped with second conductivity type impurities... Agent: Ladas & Parry LLP

20080280441 - Method of forming isolation layer of flash memory device: An embodiment of the invention relates to a method of forming an isolation layer of a flash memory device. An isolation layer is formed using a PSZ-based material and a nitride film of liner form is deposited on a trench before the PSZ film is deposited. An oxide film can... Agent: Marshall, Gerstein & Borun LLP

20080280442 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. A substrate includes two different regions, each of which has a different pattern density. A polish target layer is formed over the substrate to cover the patterns in the regions and a planarization guide layer is formed along a top surface... Agent: Townsend And Townsend And Crew, LLP

20080280443 - Exposure mask and method of forming a contact hole of a semiconductor device employing the same: An exposure mask and a method of forming a contact hole of a semiconductor device using the same, in which micro patterns can be formed are disclosed herein. In an aspect, an exposure mask method includes a mask substrate, a light-shield pattern formed on the mask substrate, and a transparent... Agent: Marshall, Gerstein & Borun LLP

20080280444 - Method of forming micro pattern of semiconductor device: The present invention relates to a method of forming a micro pattern of a semiconductor device. In the method according to an aspect of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first... Agent: Townsend And Townsend And Crew, LLP

20080280445 - Manufacturing method of nitride semiconductor device and nitride semiconductor device: Provided is a manufacturing method of a nitride semiconductor device having a nitride semiconductor substrate (e.g. GaN substrate) in which dislocation concentrated regions align in stripe formation, the dislocation concentrated regions extending from a front surface to a back surface of the substrate, the manufacturing method being for stacking each... Agent: Mcdermott Will & Emery LLP

20080280446 - Method of producing a microscopic hole in a layer and integrated device with a microscopic hole in a layer: A microscopic hole is produced in a dielectric layer having a dielectric first material, a first surface and a second surface. In one embodiment, the tapered through-hole is etched from the second surface of the layer to the first surface of the layer. The tapered hole provides a first cross... Agent: Dicke, Billig & Czaja

20080280448 - Method for manufacturing gate oxide layer with different thicknesses: A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first... Agent: J C Patents, Inc.

20080280447 - Spin on glass (sog) etch improvement method: A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via... Agent: Texas Instruments Incorporated

20080280449 - Self-aligned dielectric cap: A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of the substrate so that little... Agent: Haynes And Boone, LLP

20080280450 - Method of two-step backside etching: The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the substrate. Then,... Agent: Rosenberg, Klein & Lee

20080280451 - Plasma processing method and plasma processing apparatus: A plasma processing apparatus includes: a film which is made of an insulative material and constructs a surface of a sample stage on which a sample is put; a disk-shaped member whose upper surface is joined with the film in a lower portion of the film and which is made... Agent: Mcdermott Will & Emery LLP

20080280452 - method for stripping photoresist: Disclosed is a method for stripping a photoresist comprising: (I) providing a photoresist pattern on a substrate where the substrate has at least a copper (Cu) wiring and a low-dielectric layer thereon, and selectively etching the low-dielectric layer by using the photoresist pattern as a mask; (II) contacting the substrate... Agent: Wenderoth, Lind & Ponack, L.L.P.

20080280453 - Apparatus and method for supporting, positioning and rotating a substrate in a processing chamber: Embodiments of the invention contemplate a method, apparatus and system that are used to support, position, and rotate a substrate during processing. Embodiments of the invention may also include a method of controlling the transfer of heat between a substrate and substrate support positioned in a processing chamber. The apparatus... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080280454 - Wafer recycling method using laser films stripping: A wafer recycling method using laser films stripping is proposed, in which the high energy density of laser is used to instantaneously vaporize and remove multilayer films of different materials on wafers. The process is simple, and it is not necessary to sore wafers in advance, and the selection of... Agent: Rosenberg, Klein & Lee

20080280455 - Atomic layer deposition systems and methods including metal beta-diketiminate compounds: The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one β-diketiminate ligand. Such systems and methods can be useful for depositing metal-containing layers on substrates.... Agent: Mueting, Raasch & Gebhardt, P.A.

20080280456 - Thermal methods for cleaning post-cmp wafers: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to... Agent: Carr & Ferrell LLP

20080280457 - Method of improving initiation layer for low-k dielectric film by digital liquid flow meter: A method for depositing a low dielectric constant film by flowing a oxidizing gas into a processing chamber, flowing an organosilicon compound from a bulk storage container through a digital liquid flow meter at an organosilicon flow rate to a vaporization injection valve, vaporizing the organosilicon compound and flowing the... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080280458 - Irradiating apparatus, semiconductor device manufacturing apparatus, semiconductor device manufacturing method, and display device manufacturing method: m

20080274567 - Method of forming integrated circuit having a magnetic tunnel junction device: A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the... Agent: Steven E. Dicke Dicke, Billig & Czaja, PLLC

20080274569 - Method for forming semiconductor ball grid array package: A method for forming a semiconductor package provides a ball grid array, BGA, formed on a package substrate. The apices of the solder balls of the BGA are all at the same height, even if the package substrate is non-planar. Different solder ball pad sizes are used and tailored to... Agent: Duane Morris LLP (tsmc)IPDepartment

20080274568 - Reticle and method of fabricating semiconductor device: Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080274570 - Inkjet head, method for producing inkjet head, inkjet recorder and inkjet coater: A method for producing an inkjet head for jetting an ink from a nozzle that is formed on a nozzle main body formed of a metal material, the method includes smoothening a surface of the nozzle main body, applying a silica sol solution to the nozzle main body so as... Agent: Mcginn Intellectual Property Law Group, PLLC

20080274571 - Semiconductor device, led print head and image-forming apparatus using same, and method of manufacturing semiconductor device: In a method of manufacturing a semiconductor thin film piece device, a plurality of semiconductor thin film pieces (14) are selected from among the semiconductor thin film pieces (14) formed on a first substrate (35), and bonded to a first set of predetermined area on a second substrate (12). Subsequently,... Agent: Panitch Schwarze Belisario & Nadel LLP

20080274572 - Method of making high efficiency uv vled on metal substrate: A method of fabricating ultraviolet (UV) vertical light-emitting diode (VLED) structures composed of AlInGaN or AlGaN with increased crystalline quality and a faster growth rate when compared to conventional AlInGaN or AlGaN LED structures is provided. This may be accomplished by forming a sacrificial GaN layer above a carrier substrate,... Agent: Patterson & Sheridan, L.L.P.

20080274573 - Method of fabricating linear cascade high-speed green light emitting diode: Green light emitting diodes (LED) of gallium arsenide (GaAs) are series-connected. The series connection has a small transmission attenuation and a wide bandwidth. The GaAs LED has a big forward bias and so neither extra driving current nor complex resonant-cavity epitaxy layer is needed. Hence, the present invention has a... Agent: Troxell Law Office PLLC

20080274574 - Laser liftoff structure and related methods: Light-emitting devices, and related components, systems, and methods associated therewith are provided.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20080274575 - Vertical semiconductor light-emitting device and method of manufacturing the same: Provided is a vertical semiconductor light-emitting device and a method of manufacturing the same. The method may include sequentially forming a lower clad layer, an active layer, and an upper clad layer on a substrate to form a semiconductor layer and forming first electrode layers on the upper clad layer.... Agent: Harness, Dickey & Pierce, P.L.C

20080274576 - Semiconductor device and manufacturing method thereof: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity... Agent: Miles & Stockbridge PC

20080274578 - Method of forming a pixel sensor cell for collecting electrons and holes: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel... Agent: Ibm Microelectronics Intellectual Property Law

20080274577 - Method of the application of a zinc sulfide buffer layer on a semiconductor substrate: A chemical bath deposition method of depositing on a semiconductor substrate a layer of zinc sulfide by dipping the semiconductor substrate into an aqueous solution of zinc sulfate and thiourea and ammonia.... Agent: Law Offices Of Hormann

20080274579 - Wafer level image sensor package with die receiving cavity and method of making the same: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die... Agent: Bacon & Thomas, PLLC

20080274580 - Method for manufacturing image sensor: A method for manufacturing an image sensor including forming a metal line layer on a semiconductor substrate, and then forming color filters on the metal line layer, and then forming seed microlenses spaced apart on the color filters, and then cleaning the surface of the seed microlenses, and then forming... Agent: Sherr & Vaughn, PLLC

20080274581 - Method for manufacturing image sensor: A method for manufacturing an image sensor that includes reducing the surface energy of the microlenses to prevent particles generated during a wafer sawing process from damaging the microlens or adhering to the microlens to cause a defective image.... Agent: Sherr & Vaughn, PLLC

20080274582 - Method of making silicon solar cells containing μc silicon layers: The invention relates to a method for producing solar cells comprising at least one p-i-n layer sequence containing micro-crystalline layers with the aid of a PECVD method. Said method is characterised in that all layers of the p-i-n layer sequence are deposited in a single-chamber process. The electrodes are interspaced... Agent: K.f. Ross P.C.

20080274583 - Through-wafer vias: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in... Agent: Schmeiser, Olsen & Watts

20080274584 - Method of microwave annealing for enhancing organic electronic devices: A method of microwave annealing for enhancing the properties of organic electronic devices is provided, including the steps of providing organic electronic devices and then microwave annealing the organic electronic devices. Because microwave annealing is non-contact and requires only a short time for annealing, and also because it anneals a... Agent: Reed Smith LLP

20080274585 - Spacer electrode small pin phase change memory ram and manufacturing method: A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080274586 - Semiconductor device, wafer and method of designing and manufacturing the same: A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that... Agent: Young & Thompson

20080274587 - Method of assembling electronic components of an electronic system, and system thus obtained: An electronic system comprising: an electronic system support substrate for the attachment of components of the electronic system, the electronic system support substrate including electric signal propagation paths for the propagation of electric signals between the system components; at least a first and a second electronic components, wherein at least... Agent: International Business Machines Corporation

20080274588 - Semiconductor device and method of fabricating the same, circuit board, and electronic instrument: A method of fabricating a semiconductor device, including: preparing a wiring board on which is mounted a first semiconductor chip having a plurality of first pads; electrically connecting each of the first pads to an interconnecting pattern of the first semiconductor chip by a wire; providing resin paste on the... Agent: Oliff & Berridge, PLC

20080274590 - Manufacturing method of semiconductor device: A manufacturing method of the semiconductor device including a step of forming solder balls on the circuit face of a mother chip, a step of making flip chip bonding of the daughter chip after the step of forming solder balls on the circuit face of the mother chip, and a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080274589 - Wafer-level flip-chip assembly methods: A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then... Agent: Slater & Matsil, L.L.P.

20080274591 - Carrier for stacked type semiconductor device and method of fabricating stacked type semiconductor devices: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas... Agent: Ingrassia Fisher & Lorenz, P.C.

20080274592 - Process and apparatus for wafer-level flip-chip assembly: A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on... Agent: Slater & Matsil, L.L.P.

20080274593 - Semiconductor device package with multi-chips and method of the same: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die... Agent: Bacon & Thomas, PLLC

20080274594 - Step height reduction between soi and epi for dso and bos integration: A semiconductor process and apparatus provides a planarized hybrid substrate (16) by removing a nitride mask layer (96) and using an oxide polish stop layer (92) when an epitaxial semiconductor layer (99) is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack (11)... Agent: Hamilton & Terrile, LLP

20080274595 - Dual substrate orientation or bulk on soi integrations using oxidation for silicon epitaxy spacer formation: A semiconductor process and apparatus provide a planarized hybrid substrate (15) by thermally oxidizing SOI sidewalls (90) in a trench opening (93) to form SOI sidewall oxide spacers (94) which are trimmed while etching through a buried oxide layer (80) to expose the underlying bulk substrate (70) for subsequent epitaxial... Agent: Hamilton & Terrile, LLP

20080274597 - Method and structure to reduce contact resistance on thin silicon-on-insulator device: A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080274596 - Semiconductor device and method of manufacturing the same: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080274598 - Doped wge to form dual metal gates: A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work... Agent: Texas Instruments Incorporated

20080274599 - Method of manufacturing a semiconductor device having a trench surrounding plural unit cells: A semiconductor device comprises a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET). The unit cell includes a first source region formed in a first base region, a second source region formed in the first base region and separated from the first source... Agent: Young & Thompson

20080274600 - Method to improve source/drain parasitics in vertical devices: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure,... Agent: Fortkort & Houston P.C.

20080274601 - Method of forming a transistor having multiple types of schottky junctions: A gate electrode is formed overlying a substrate. A first angled metal implant is performed at a first angle into the substrate followed by performing a second angled metal implant at a second angle. The first angled metal implant and the second angled metal implant form a first current electrode... Agent: Freescale Semiconductor, Inc. Law Department

20080274602 - Method of manufacturing dynamic random access memory: A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is... Agent: J C Patents, Inc.

20080274603 - Semiconductor package having through-hole via on saw streets formed with partial saw: A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer with many die having contact pads disposed on each die. The semiconductor wafer has saw street guides between each die. A trench is formed in the saw streets. The trench extends partially but not completely... Agent: Quarles & Brady LLP

20080274604 - Susceptor with backside area of constant emissivity: Methods and apparatus for providing constant emissivity of the backside of susceptors are provided. Provided is a susceptor comprising: a susceptor plate having a surface for supporting a wafer and a backside surface opposite the wafer supporting surface; a layer comprising an oxide, a nitride, an oxynitride, or combinations thereof... Agent: Diehl Servilla LLC

20080274605 - Method of manufacturing silicon nitride film, method of manufacturing semiconductor device, and semiconductor device: A method of manufacturing a silicon nitride film that forms a silicon nitride film on a surface of a substrate comprises sequentially repeating first through third steps. The first step includes feeding a first gas containing silicon and nitrogen to the surface of the substrate. The second step includes feeding... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080274606 - Method of manufacturing semiconductor device: Each of channel regions 2a and 3b is covered by a gate electrode 6 via a gate insulation film 5 and side wall spacers 9 from its top face to both side faces along an x-direction. In other words, there is no insulation material of an STI element isolation structure... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080274607 - Semiconductor device and fabrication process thereof: A method of fabricating a semiconductor device includes the steps of modifying a damaged layer containing carbon and formed at a semiconductor surface by exposing the damaged layer to oxygen radicals to form a modified layer, and removing the modified layer by a wet etching process, wherein the modifying step... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080274608 - Structure and method for enhancing resistance to fracture of bonding pads: The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within... Agent: Scully, Scott, Murphy & Presser, P.C.

20080274609 - Method and structure for low-k interlayer dielectric layer: An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overlying the first interlayer dielectric layer. A contact structure including metallization is... Agent: Townsend And Townsend And Crew, LLP

20080274611 - Method and process for forming a self-aligned silicide contact: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W... Agent: Scully, Scott, Murphy & Presser, P.C.

20080274610 - Methods of forming a semiconductor device including a diffusion barrier film: Methods of forming a semiconductor device that includes a diffusion barrier film are provided. The diffusion barrier film includes a metal nitride formed by using a MOCVD process and partially treated with a plasma treatment. Thus, a specific resistance of the diffusion barrier film can be decreased, and the diffusion... Agent: Myers Bigel Sibley & Sajovec

20080274612 - Shielded capacitor structure: A method and apparatus if provided for shielding a capacitor structure formed in a semiconductor device. In a capacitor formed in an integrated circuit, one or more shields are disposed around layers of conductive strips to shield the capacitor. The shields confine the electric fields between the limits of the... Agent: Johnson & Associates

20080274614 - fabricating method of metal line: A method of fabricating a metal line using a dual damascene process which enhances reliability of the semiconductor device. The method includes forming a lower metal line in a first inter metal dielectric layer; and then sequentially forming a first anti-etch layer, a second inter metal dielectric layer and a... Agent: Sherr & Vaughn, PLLC

20080274613 - Method for the protection of openings in a component during a machining process: The invention relates to a method for the protection of openings in a component, produced from an electrically-conducting material, in particular, from metal or a metal alloy, during a machining process against the ingress of material, whereby the openings are sealed with a filler material before the machining process, which... Agent: Siemens Corporation Intellectual Property Department

20080274615 - Atomic layer deposition methods, methods of forming dielectric materials, methods of forming capacitors, and methods of forming dram unit cells: Some embodiments include methods of forming metal-containing oxides. The methods may utilize ALD where a substrate surface is exposed to an organometallic composition while the substrate surface is at a temperature of at least 275° C. to form a metal-containing layer. The metal-containing layer may then be exposed to at... Agent: Wells St. John P.s.

20080274616 - Method for depositing titanium nitride films for semiconductor manufacturing: Embodiments of the invention describe TiN deposition methods suitable for high volume manufacturing of semiconductor devices on large patterned substrates (wafers). One embodiment describes a chemical vapor deposition (CVD) process using high gas flow rate of a tetrakis(ethylmethylamino) titanium (TEMAT) precursor vapor along with an inert carrier gas at a... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080274617 - Periodic plasma annealing in an ald-type process: Methods for performing periodic plasma annealing during atomic layer deposition are provided along with structures produced by such methods. The methods include contacting a substrate with a vapor-phase pulse of a metal source chemical and one or more plasma-excited reducing species for a period of time. Periodically, the substrate is... Agent: Knobbe, Martens, Olson & Bear LLP

20080274620 - Chemical mechanical polishing agent kit and chemical mechanical polishing method using the same: A chemical mechanical polishing method of the present invention comprises conducting polishing by the use of a chemical mechanical polishing aqueous dispersion (A) containing abrasive grains and then conducting polishing by the use of a chemical mechanical polishing aqueous composition (B) containing at least one organic compound having a heterocyclic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080274619 - Cmp compositions containing a soluble peroxometalate complex and methods of use thereof: The present invention provides a chemical-mechanical polishing (CMP) composition for polishing a ruthenium-containing substrate in the presence of hydrogen peroxide without forming a toxic level of ruthenium tetroxide during the polishing process. The composition comprises (a) a catalytic oxidant comprising a water-soluble peroxometalate complex, an oxidizable precursor of a peroxometalate... Agent: Steven Weseman Associate General Counsel, I.p.

20080274618 - Polishing composition and method for high selectivity polysilicon cmp: The present invention provides a polishing composition and a method for removing polysilicon in preference to silicon dioxide, silicate glasses and/or silicon nitride via chemical-mechanical polishing during semiconductor device fabrication. In a preferred embodiment, the polishing composition includes an aqueous dispersion of ceria abrasive particles, from about 0.005% to about... Agent: Rankin, Hill & Clark LLP

20080274621 - Iii-nitride semiconductor device with trench structure: A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being... Agent: Ostrolenk Faber Gerb & Soffen

20080274622 - Plasma processing, deposition and ald methods: A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least two regions that exhibit different plasma densities. The method includes exposing at least some of the surface to both of... Agent: Neal R. Rueger

20080274623 - Methods for fabricating a magnetic head reader using a chemical mechanical polishing (cmp) process for sensor stripe height patterning: Methods for fabricating TMR and CPP GMR magnetic heads using a chemical mechanical polishing (CMP) process with a patterned CMP conductive protective layer for sensor stripe height patterning. The method comprises defining a stripe height of a read sensor of a magnetic head reader. The method further comprises refill depositing... Agent: Duft Bornsen & Fishman, LLP

20080274624 - Method for depositing titanium nitride films for semiconductor manufacturing: Embodiments of the invention describe TiN deposition methods suitable for high volume manufacturing of semiconductor devices on large patterned substrates (wafers). One embodiment describes a chemical vapor deposition (CVD) process using high gas flow rate of a tetrakis(ethylmethylamino)titanium (TEMAT) precursor vapor along with an inert carrier gas at a low... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080274625 - Methods of forming electronic devices containing zr-sn-ti-o films: A dielectric film containing Zr—Sn—Ti—O and methods of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Films of Zr—Sn—Ti—O may be formed in a self-limiting growth process.... Agent: Schwegman, Lundberg & Woessner/micron

20080274626 - Method for depositing a high quality silicon dielectric film on a germanium substrate with high quality interface: In certain embodiments methods for depositing materials on substrates, and more particularly, methods for depositing dielectric layers, such as silicon oxides or silicon oxynitrides, on germanium substrates are provided. The methods involve depositing a barrier layer on the germanium substrate to prevent oxidation of the germanium substrate when forming a... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080274627 - Silicon-containing film, forming material, making method, and semiconductor device: Using a cyclic siloxane compound having a vinyl group directly attached to a silicon atom and a relatively bulky substituent group containing a primary carbon vicinal to the silicon, a dielectric film, especially a low-k interlayer dielectric film can be formed by the plasma-enhanced CVD process.... Agent: Westerman, Hattori, Daniels & Adrian, LLP