Semiconductor device manufacturing: process inventions 10/08

20080261332 - Method for manufacturing semiconductor device: The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a ferroelectric film on a first conductive film by a sol-gel method; forming a first conductive metal oxide film on the ferroelectric film; carrying out a first annealing on the first conductive metal oxide... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080261333 - Methods of forming a material film, methods of forming a capacitor, and methods of forming a semiconductor memory device using the same: A method of forming a material (e.g., ferroelectric) film, a method of manufacturing a capacitor, and a method of forming a semiconductor memory device using the method of forming the (e.g., ferroelectric) film are provided. Pursuant to an example embodiment of the present invention, a method of forming a ferroelectric... Agent: Harness, Dickey & Pierce, P.L.C

20080261331 - Mram and method of manufacturing the same: A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261334 - Method of processing semiconductor wafers: A method of processing semiconductor waters comprises forming a pattern of recesses in an exposed surface of each water in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is... Agent: Texas Instruments Incorporated

20080261335 - Endpoint detection for photomask etching: Apparatus and method for endpoint detection are provided for photomask etching. The apparatus provides a plasma etch chamber with a substrate support member. The substrate support member has at least two optical components disposed therein for use in endpoint detection. Enhanced process monitoring for photomask etching are achieved by the... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080261336 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080261337 - Low voltage electron source with self aligned gate apertures, fabrication method thereof, and luminous display using the electron source: A method of fabricating an electron source having a self-aligned gate aperture is disclosed. A substrate is deposited on a first conductive layer. Over the first conductive layer an emitter layer is deposited. The emitter layer includes one or a plurality of spaced-apart nano-structures and a solid surface with nano-structures... Agent: Dechert LLP

20080261338 - Method for manufacturing an electronics module comprising a component electrically connected to a conductor-pattern layer: Method for manufacturing an electronic module, which electronic module includes a component (6), which is connected electrically to a conductor-pattern layer (14). In the method contact openings (17) are made in the conductor layer (4), the mutual positions of which correspond to the mutual positions of the contact areas (7)... Agent: Baker & Daniels LLP

20080261339 - Packaging method to manufacture package for a high-power light emitting diode: A packaging method to manufacture a package for a high-power light emitting diode (LED) has steps of (a) obtaining a metal board, (b) treating the metal board, (c) molding a cell matrix with multiple reflective bases, (d) attaching LED chips onto the dissipating boards and bonding conductive wires in each... Agent: Patenttm.us

20080261340 - Surface-roughening method: The method is disclosed as applied to roughening the light-emitting surface of an LED wafer for reduction of the internal total reflection of the light generated. A masking film of silver is first deposited on the surface of a wafer to be diced into LED chips. Then the masking film... Agent: Woodcock Washburn LLP

20080261341 - Method for fabricating a light emitting diode chip: A method for fabricating substrate-free LED chips has a multilayer semiconductor structure at least 10 microns thick provided on a growth substrate. One or more arrays of parallel streets are etched into the multilayer semiconductor structure using a first pulsed laser beam. By scanning a second pulsed laser beam through... Agent: Goldeneye, Inc.

20080261342 - Chemical sensor using semiconducting metal oxide nanowires: Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration... Agent: Fish & Richardson, PC

20080261343 - Vacuum packaged single crystal silicon device: A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of... Agent: Honeywell International Inc. Patent Services Ab-2b

20080261344 - Vacuum packaged single crystal silicon device: A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of... Agent: Honeywell International Inc. Patent Services Ab-2b

20080261345 - Method for manufacturing a semiconductor pressure sensor: Method for manufacturing a semiconductor pressure sensor, wherein, in a silicon substrate, trenches are dug and delimit walls; a closing layer is epitaxially grown, that closes the trenches at the top and forms a suspended membrane; a heat treatment is performed so as to cause migration of the silicon of... Agent: Seed Intellectual Property Law Group PLLC

20080261346 - Semiconductor image device package with die receiving through-hole and method of the same: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080261347 - Method of manufacturing semiconductor film and method of manufacturing photovoltaic element: A method of manufacturing a semiconductor film capable of inhibiting the quality of a semiconductor film from destabilization is obtained. This method of manufacturing a semiconductor film includes steps of introducing source gas for a semiconductor, controlling the pressure of an atmosphere formed by the source gas to a prescribed... Agent: Ditthavong Mori & Steiner, P.C.

20080261348 - Method of manufacturing semiconductor film and method of manufacturing photovoltaic element: A method of manufacturing a semiconductor film capable of suppressing difficulty in temperature control of a catalytic wire is obtained. This method of manufacturing a semiconductor film includes steps of heating a catalytic wire to at least a prescribed temperature and forming a semiconductor film by introducing source gas for... Agent: Ditthavong Mori & Steiner, P.C.

20080261349 - Protective coating for planarization: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer... Agent: Knobbe Martens Olson & Bear LLP

20080261350 - Solder interconnection array with optimal mechanical integrity: A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array... Agent: Law Office Of Delio & Peterson, LLC.

20080261351 - Wafer sawing method: A wafer sawing method for sawing a wafer by using a cutting tool is provided. Sawing paths are formed on a surface of the wafer. In the wafer sawing method, a carrier on which strip-shaped adhesives or at least a fiducial mark is formed is firstly provided. The dimension of... Agent: J C Patents, Inc.

20080261352 - Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being... Agent: Harness, Dickey & Pierce, P.L.C

20080261353 - Underfill film having thermally conductive sheet: An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the... Agent: Law Offices Of Michael Dryja

20080261354 - Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator cmos devices: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs... Agent: Scully, Scott, Murphy & Presser, P.C.

20080261355 - Method of making a semiconductor device with a stressor: First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in the stressor layer that overlies the first transistor is modified. Stress in the stressor layer that overlies the second transistor... Agent: Freescale Semiconductor, Inc. Law Department

20080261356 - Method of forming thin film transistor: A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate and includes at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor... Agent: Jianq Chyun Intellectual Property Office

20080261357 - Method for fabrication of semiconductor device: After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion.... Agent: Miles & Stockbridge PC

20080261359 - Ldmos transistor device, integrated circuit, and fabrication method thereof: An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2′; 151) on top of a gate insulation layer region (3; 141), source (4) and drain (5, 7) regions, and a channel (6; 12) arranged beneath... Agent: Coats & Bennett/infineon Technologies

20080261358 - Manufacture of lateral semiconductor devices: A method of manufacturing a lateral semiconductor device comprising a semiconductor body (2) having top and bottom major surfaces (2a, 2b), the body including a drain drift region (6a) of a first conductivity type. The method includes the steps of forming a vertical access trench (20) in the semiconductor body... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080261360 - Methods of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is... Agent: F. Chau & Associates, LLC

20080261361 - Shallow trench isolation for soi structures combining sidewall spacer and bottom liner: A method for making a semiconductor device is provided which comprises (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion... Agent: Fortkort & Houston P.C.

20080261362 - Method of making a semiconductor device using a stressor: A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having... Agent: Freescale Semiconductor, Inc. Law Department

20080261363 - Dual gated finfet gain cell: A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device.... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080261364 - Method for forming stack capacitor: A method for forming a stack capacitor includes providing a substrate with a bottom layer, a BPSG layer, a USG layer and a top layer thereon; using the top layer as a hard mask and the substrate as a first etching stop layer to perform a dry etching process to... Agent: North America Intellectual Property Corporation

20080261366 - Non-volatile memory device having improved erase efficiency and method of manufacturing the same: A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment... Agent: Buchanan, Ingersoll & Rooney PC

20080261365 - Nonvolatile semiconductor memory device and manufacturing method thereof: A technology realizing decreases of capacitance between the adjoining floating gates and of the threshold voltage shift caused by interference between the adjoining memory cells in a nonvolatile semiconductor memory device with the advances of miniaturization in the period following the 90 nm generation. By having the floating gate 3... Agent: Miles & Stockbridge PC

20080261367 - Method for process integration of non-volatile memory cell transistors with transistors of another type: A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on... Agent: Freescale Semiconductor, Inc. Law Department

20080261368 - Work function adjustment with the implant of lanthanides: Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of... Agent: Texas Instruments Incorporated

20080261369 - Structure and method for mosfet with reduced extension resistance: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080261370 - Semiconductor device and method of fabricating the same: e

20080261371 - Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for soi bicmos with reduced buried oxide thickness for low-substrate bias operation: The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at... Agent: Scully, Scott, Murphy & Presser, P.C.

20080261372 - Method of manufacturing vibrating micromechanical structures: A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, a capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer... Agent: Honeywell International Inc. Patent Services Ab-2b

20080261373 - Method of fabricating semconductor device: A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080261375 - Method of forming a semiconductor device having a dummy feature: A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the edge of the active device region is coincident with at least a portion of the perimeter,... Agent: Freescale Semiconductor, Inc. Law Department

20080261374 - Separate layer formation in a semiconductor device: A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer is formed over the first conductive layer. A trench is formed in the semiconductor layer to separate the first... Agent: Freescale Semiconductor, Inc. Law Department

20080261376 - Method of manufacturing soi substrate: To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a... Agent: Eric Robinson

20080261377 - Method of forming a device wafer with recyclable support: A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and... Agent: Winston & Strawn LLP Patent Department

20080261378 - Method for growth of gan single crystal, method for preparation of gan substrate, process for producing gan-based element, and gan-based element: A GaN-based thin film (thick film) is grown using a metal buffer layer grown on a substrate. (a) A metal buffer layer (210) made of, for example, Cr or Cu is vapor-deposited on a sapphire substrate (120). (b) A substrate obtained by vapor-depositing the metal buffer layer (210) on the... Agent: Cowan Liebowitz & Latman P.c

20080261379 - Method for manufacturing soi substrate and semiconductor device: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is... Agent: Eric Robinson

20080261380 - Semiconductor layer structure and method of making the same: A method of forming a semiconductor structure includes providing a substrate and providing a detach region which is carried by the substrate. A device structure which includes a stack of crystalline semiconductor layers is provided, wherein the detach region is positioned between the device structure and substrate. The stack is... Agent: Schmeiser Olsen & Watts

20080261381 - Method for manufacturing bonded substrate: There is provided a method for manufacturing a bonded substrate in which an insulator substrate is used as a handle wafer and a donor wafer is bonded to a front surface of the insulator substrate, the method comprises at least that a sandblast treatment is performed with respect to a... Agent: Oliff & Berridge, PLC

20080261382 - Wafer dicing using a fiber mopa: Silicon wafer dicing apparatus includes a master oscillator power amplifier (MOPA) arrangement wherein the master oscillator includes a continuous wave (CW) laser the output of which modulated by an external modulator to provide optical pulses to be amplified in the power amplifier. In one example of the apparatus the power... Agent: Stallman & Pollock LLP

20080261383 - Semiconductor workpiece carriers and methods for processing semiconductor workpieces: Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier assembly includes (a) a support structure having an opening sized to receive at least a portion of a semiconductor workpiece, and (b) a replaceable carrier positioned at the opening. The replaceable... Agent: Perkins Coie LLP Patent-sea

20080261384 - Method of removing photoresist layer and method of fabricating semiconductor device using the same: A method of removing a photoresist layer is provided. An ion implantation process has been performed on the photoresist layer to transform a surface of the photoresist layer to a crust and a soft photoresist layer remains within the crust. The method includes performing a first removing step to remove... Agent: J C Patents, Inc.

20080261385 - Method for selective removal of a layer: A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method... Agent: Freescale Semiconductor, Inc. Law Department

20080261386 - Sample wafer fabrication method: A third channel region into which a high concentration N-type impurity is implanted, a fourth channel region into which a low concentration N-type impurity is implanted, a first channel region into which a high concentration P-type impurity is implanted, and a second channel region into which a low concentration P-type... Agent: Young & Thompson

20080261387 - Semiconductor device and method of manufacturing semiconductor device: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261388 - Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å... Agent: Kevin L. Beaman

20080261389 - Method of forming micro pattern of semiconductor device: A method of forming a micro pattern of a semiconductor device method includes forming an etch target layer over a substrate, a hard mask layer over the etch target layer, and first auxiliary patterns over the etch target layer. The first auxiliary patterns defining a plurality of structures that are... Agent: Townsend And Townsend And Crew, LLP

20080261390 - Method for forming bumps on under bump metallurgy: A method for forming metal bumps is provided. A bonding pad is first formed on the active surface of a chip and then a passivation layer is formed on the active surface of the chip and exposes the bonding pad. An under bump metallurgy is formed on the active surface... Agent: Lowe Hauptman Ham & Berner, LLP

20080261391 - Method of producing semiconductor device: A method of producing a semiconductor device includes the steps of: preparing a base member; laminating sequentially a barrier film formed of titanium nitride, a wiring portion film formed of tungsten, and a mask film formed of titanium nitride on the base member to form a multi-layer film; forming a... Agent: Kubotera & Associates, LLC

20080261392 - Conductive via formation: A method involves depositing a first electrically conductive material, using a deposition technique, into a via formed in a material, the via having a diameter at a surface of the material of less than about 10 μm and a depth of greater than about 50 μm, so as to form... Agent: Foley & Lardner LLP

20080261393 - Reducing wire erosion during damascene processing: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may... Agent: Greenblum & Bernstein, P.L.C

20080261394 - Method for fabricating semiconductor device with silicided gate: A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at... Agent: Slater & Matsil, L.L.P.

20080261395 - Semiconductor device, method for manufacturing semiconductor devices and mask systems used in the manufacturing of semiconductor devices: Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned... Agent: Slater & Matsil, L.L.P.

20080261396 - Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same: A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole,... Agent: Ladas & Parry LLP

20080261397 - Method for manufacturing semiconductor device: There is provided a method for manufacturing a semiconductor device, which includes the steps of: providing a semiconductor substrate including a gate, a source and a drain, wherein the gate includes a gate dielectric layer disposed on the semiconductor substrate; forming an etching barrier layer on the semiconductor substrate; and... Agent: Squire, Sanders & Dempsey L.L.P.

20080261398 - Semiconductor device having oxidized metal film and manufacture method of the same: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080261399 - Method for chemical mechanical polishing in a scan manner of a semiconductor device: The chemical mechanical polishing of a semiconductor device includes polishing a target layer to be polished through a chemical reaction by slurry and a mechanical process by a polishing pad. Then performing a post cleaning composed of cleaning, rinsing and drying of the surface of the polished target layer. The... Agent: Ladas & Parry LLP

20080261400 - Polishing composition, polishing method, and method for forming copper wiring for semiconductor integrated circuit: The present invention provides a polishing composition containing a neutralized carboxylic acid, an oxidizer and water, wherein a part of the carboxylic acid is an alicyclic resin acid (A) and the pH value is within a range of from 7.5 to 12. The alicyclic resin acid is preferably at least... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261401 - Chemical-mechanical polishing of sic surfaces using hydrogen peroxide or ozonated water solutions in combination with colloidal abrasive: A process is taught for producing a smooth, damage-free surface on a SiC wafer, suitable for subsequent epitaxial film growth or ion implantation and semiconductor device fabrication. The process uses certain oxygenated solutions in combination with a colloidal abrasive in order to remove material from the wafer surface in a... Agent: The Webb Law Firm, P.C.

20080261402 - Method of removing insulating layer on substrate: A method of removing an insulating layer on a substrate is described, including a first CMP process and a second CMP process performed in sequence, wherein the polishing slurry used in the first CMP process and that used in the second CMP process have substantially the same pH value that... Agent: Jianq Chyun Intellectual Property Office

20080261403 - Method for obtaining high-quality boundary for semiconductor devices fabricated on a partitioned substrate: One embodiment of the present invention provides a process for obtaining high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate. During operation, the process receives a trench-partitioned substrate wherein the substrate surface is partitioned into arrays of isolated deposition platforms which are separated by arrays of... Agent: Park, Vaughan & Fleming LLP

20080261404 - Method of making semiconductor device: A plasma processing method, which enables the etching controllability for a high-dielectric-constant insulating film to be improved. A substrate having a high-dielectric-constant gate insulating film and a hard mask formed thereon is subjected to etching processing using a plasma of a processing gas containing a noble gas and a reducing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261405 - Hydrogen ashing enhanced with water vapor and diluent gas: An oxygen-free hydrogen plasma ashing process particularly useful for low-k dielectric materials based on hydrogenated silicon oxycarbide materials. The main ashing step includes exposing a previously etched dielectric layer to a plasma of hydrogen and optional nitrogen, a larger amount of water vapor, and a yet larger amount of argon... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20080261406 - Etching method and semiconductor device fabrication method: An etching method capable of increasing the selectivity of a polysilicon film to a silicon oxide film and suppressing recess formation on a silicon base layer. That part of the polysilicon film of a wafer transferred into a processing vessel which is exposed through an opening is etched so as... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261408 - Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors: A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080261409 - Processing device and method for processing a substrate: A processing device for producing a layer system including at least one layer of an organic light emitting semiconductor material (OLED), comprises (1) a configuration of one or more treatment stations for processing the substrate in the treatment stations and (2) a first encapsulation module for providing an encapsulation element... Agent: Townsend And Townsend And Crew, LLP

20080261407 - Semiconductor device with hydrogen barrier and method therefor: A method of forming a semiconductor device comprises providing a portion of a semiconductor device structure, wherein the portion includes a region susceptible to hydrogen incorporation due to subsequent device processing. For example, the subsequent device processing can include one or more of (i) forming a layer over the region,... Agent: Freescale Semiconductor, Inc. Law Department

20080261410 - Method for treating base oxide to improve high-k material deposition: A method for forming a high-K material layer in a semiconductor device fabrication process including providing a silicon semiconductor substrate or thermally growing interfacial oxide layer comprising silicon dioxide over the silicon substrate; treating with an aqueous base solution or nitridation and depositing a high-K material layer.... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080261411 - Method for manufacturing soi substrate: The present invention provides a method for manufacturing an SOI substrate by which an oxygen ion is implanted from at least one of main surfaces of a single-crystal silicon substrate to form an oxygen-ion-implanted layer and then an oxide film-forming heat treatment that changes the formed oxygen-ion-implanted layer into a... Agent: Oliff & Berridge, PLC

20080261412 - Apparatus and method for atomic layer deposition: The embodiments provide apparatus and methods of depositing conformal thin film on interconnect structures by providing processes and systems using an atomic layer deposition (ALD). More specifically, each of the ALD systems includes a proximity head that has a small reaction volume right above an active process region of the... Agent: Martine Penilla & Gencarella, LLP

20080261413 - Pretreatment processes within a batch ald reactor: Embodiments of the invention provide methods for forming a hafnium material on a substrate within a processing chamber. In one embodiment, a method is provided which includes exposing the substrate within the processing chamber to a first oxidizing gas during a pretreatment process, exposing the substrate sequentially to a second... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080261332 - Method for manufacturing semiconductor device: The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a ferroelectric film on a first conductive film by a sol-gel method; forming a first conductive metal oxide film on the ferroelectric film; carrying out a first annealing on the first conductive metal oxide... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080261333 - Methods of forming a material film, methods of forming a capacitor, and methods of forming a semiconductor memory device using the same: A method of forming a material (e.g., ferroelectric) film, a method of manufacturing a capacitor, and a method of forming a semiconductor memory device using the method of forming the (e.g., ferroelectric) film are provided. Pursuant to an example embodiment of the present invention, a method of forming a ferroelectric... Agent: Harness, Dickey & Pierce, P.L.C

20080261331 - Mram and method of manufacturing the same: A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261334 - Method of processing semiconductor wafers: A method of processing semiconductor waters comprises forming a pattern of recesses in an exposed surface of each water in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is... Agent: Texas Instruments Incorporated

20080261335 - Endpoint detection for photomask etching: Apparatus and method for endpoint detection are provided for photomask etching. The apparatus provides a plasma etch chamber with a substrate support member. The substrate support member has at least two optical components disposed therein for use in endpoint detection. Enhanced process monitoring for photomask etching are achieved by the... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080261336 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080261337 - Low voltage electron source with self aligned gate apertures, fabrication method thereof, and luminous display using the electron source: A method of fabricating an electron source having a self-aligned gate aperture is disclosed. A substrate is deposited on a first conductive layer. Over the first conductive layer an emitter layer is deposited. The emitter layer includes one or a plurality of spaced-apart nano-structures and a solid surface with nano-structures... Agent: Dechert LLP

20080261338 - Method for manufacturing an electronics module comprising a component electrically connected to a conductor-pattern layer: Method for manufacturing an electronic module, which electronic module includes a component (6), which is connected electrically to a conductor-pattern layer (14). In the method contact openings (17) are made in the conductor layer (4), the mutual positions of which correspond to the mutual positions of the contact areas (7)... Agent: Baker & Daniels LLP

20080261339 - Packaging method to manufacture package for a high-power light emitting diode: A packaging method to manufacture a package for a high-power light emitting diode (LED) has steps of (a) obtaining a metal board, (b) treating the metal board, (c) molding a cell matrix with multiple reflective bases, (d) attaching LED chips onto the dissipating boards and bonding conductive wires in each... Agent: Patenttm.us

20080261340 - Surface-roughening method: The method is disclosed as applied to roughening the light-emitting surface of an LED wafer for reduction of the internal total reflection of the light generated. A masking film of silver is first deposited on the surface of a wafer to be diced into LED chips. Then the masking film... Agent: Woodcock Washburn LLP

20080261341 - Method for fabricating a light emitting diode chip: A method for fabricating substrate-free LED chips has a multilayer semiconductor structure at least 10 microns thick provided on a growth substrate. One or more arrays of parallel streets are etched into the multilayer semiconductor structure using a first pulsed laser beam. By scanning a second pulsed laser beam through... Agent: Goldeneye, Inc.

20080261342 - Chemical sensor using semiconducting metal oxide nanowires: Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration... Agent: Fish & Richardson, PC

20080261343 - Vacuum packaged single crystal silicon device: A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of... Agent: Honeywell International Inc. Patent Services Ab-2b

20080261344 - Vacuum packaged single crystal silicon device: A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of... Agent: Honeywell International Inc. Patent Services Ab-2b

20080261345 - Method for manufacturing a semiconductor pressure sensor: Method for manufacturing a semiconductor pressure sensor, wherein, in a silicon substrate, trenches are dug and delimit walls; a closing layer is epitaxially grown, that closes the trenches at the top and forms a suspended membrane; a heat treatment is performed so as to cause migration of the silicon of... Agent: Seed Intellectual Property Law Group PLLC

20080261346 - Semiconductor image device package with die receiving through-hole and method of the same: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080261347 - Method of manufacturing semiconductor film and method of manufacturing photovoltaic element: A method of manufacturing a semiconductor film capable of inhibiting the quality of a semiconductor film from destabilization is obtained. This method of manufacturing a semiconductor film includes steps of introducing source gas for a semiconductor, controlling the pressure of an atmosphere formed by the source gas to a prescribed... Agent: Ditthavong Mori & Steiner, P.C.

20080261348 - Method of manufacturing semiconductor film and method of manufacturing photovoltaic element: A method of manufacturing a semiconductor film capable of suppressing difficulty in temperature control of a catalytic wire is obtained. This method of manufacturing a semiconductor film includes steps of heating a catalytic wire to at least a prescribed temperature and forming a semiconductor film by introducing source gas for... Agent: Ditthavong Mori & Steiner, P.C.

20080261349 - Protective coating for planarization: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer... Agent: Knobbe Martens Olson & Bear LLP

20080261350 - Solder interconnection array with optimal mechanical integrity: A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array... Agent: Law Office Of Delio & Peterson, LLC.

20080261351 - Wafer sawing method: A wafer sawing method for sawing a wafer by using a cutting tool is provided. Sawing paths are formed on a surface of the wafer. In the wafer sawing method, a carrier on which strip-shaped adhesives or at least a fiducial mark is formed is firstly provided. The dimension of... Agent: J C Patents, Inc.

20080261352 - Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being... Agent: Harness, Dickey & Pierce, P.L.C

20080261353 - Underfill film having thermally conductive sheet: An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the... Agent: Law Offices Of Michael Dryja

20080261354 - Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator cmos devices: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs... Agent: Scully, Scott, Murphy & Presser, P.C.

20080261355 - Method of making a semiconductor device with a stressor: First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in the stressor layer that overlies the first transistor is modified. Stress in the stressor layer that overlies the second transistor... Agent: Freescale Semiconductor, Inc. Law Department

20080261356 - Method of forming thin film transistor: A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate and includes at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor... Agent: Jianq Chyun Intellectual Property Office

20080261357 - Method for fabrication of semiconductor device: After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion.... Agent: Miles & Stockbridge PC

20080261359 - Ldmos transistor device, integrated circuit, and fabrication method thereof: An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2′; 151) on top of a gate insulation layer region (3; 141), source (4) and drain (5, 7) regions, and a channel (6; 12) arranged beneath... Agent: Coats & Bennett/infineon Technologies

20080261358 - Manufacture of lateral semiconductor devices: A method of manufacturing a lateral semiconductor device comprising a semiconductor body (2) having top and bottom major surfaces (2a, 2b), the body including a drain drift region (6a) of a first conductivity type. The method includes the steps of forming a vertical access trench (20) in the semiconductor body... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080261360 - Methods of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is... Agent: F. Chau & Associates, LLC

20080261361 - Shallow trench isolation for soi structures combining sidewall spacer and bottom liner: A method for making a semiconductor device is provided which comprises (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion... Agent: Fortkort & Houston P.C.

20080261362 - Method of making a semiconductor device using a stressor: A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having... Agent: Freescale Semiconductor, Inc. Law Department

20080261363 - Dual gated finfet gain cell: A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device.... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080261364 - Method for forming stack capacitor: A method for forming a stack capacitor includes providing a substrate with a bottom layer, a BPSG layer, a USG layer and a top layer thereon; using the top layer as a hard mask and the substrate as a first etching stop layer to perform a dry etching process to... Agent: North America Intellectual Property Corporation

20080261366 - Non-volatile memory device having improved erase efficiency and method of manufacturing the same: A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment... Agent: Buchanan, Ingersoll & Rooney PC

20080261365 - Nonvolatile semiconductor memory device and manufacturing method thereof: A technology realizing decreases of capacitance between the adjoining floating gates and of the threshold voltage shift caused by interference between the adjoining memory cells in a nonvolatile semiconductor memory device with the advances of miniaturization in the period following the 90 nm generation. By having the floating gate 3... Agent: Miles & Stockbridge PC

20080261367 - Method for process integration of non-volatile memory cell transistors with transistors of another type: A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on... Agent: Freescale Semiconductor, Inc. Law Department

20080261368 - Work function adjustment with the implant of lanthanides: Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of... Agent: Texas Instruments Incorporated

20080261369 - Structure and method for mosfet with reduced extension resistance: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080261370 - Semiconductor device and method of fabricating the same: e

20080261371 - Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for soi bicmos with reduced buried oxide thickness for low-substrate bias operation: The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at... Agent: Scully, Scott, Murphy & Presser, P.C.

20080261372 - Method of manufacturing vibrating micromechanical structures: A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, a capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer... Agent: Honeywell International Inc. Patent Services Ab-2b

20080261373 - Method of fabricating semconductor device: A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080261375 - Method of forming a semiconductor device having a dummy feature: A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the edge of the active device region is coincident with at least a portion of the perimeter,... Agent: Freescale Semiconductor, Inc. Law Department

20080261374 - Separate layer formation in a semiconductor device: A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer is formed over the first conductive layer. A trench is formed in the semiconductor layer to separate the first... Agent: Freescale Semiconductor, Inc. Law Department

20080261376 - Method of manufacturing soi substrate: To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a... Agent: Eric Robinson

20080261377 - Method of forming a device wafer with recyclable support: A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and... Agent: Winston & Strawn LLP Patent Department

20080261378 - Method for growth of gan single crystal, method for preparation of gan substrate, process for producing gan-based element, and gan-based element: A GaN-based thin film (thick film) is grown using a metal buffer layer grown on a substrate. (a) A metal buffer layer (210) made of, for example, Cr or Cu is vapor-deposited on a sapphire substrate (120). (b) A substrate obtained by vapor-depositing the metal buffer layer (210) on the... Agent: Cowan Liebowitz & Latman P.c

20080261379 - Method for manufacturing soi substrate and semiconductor device: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is... Agent: Eric Robinson

20080261380 - Semiconductor layer structure and method of making the same: A method of forming a semiconductor structure includes providing a substrate and providing a detach region which is carried by the substrate. A device structure which includes a stack of crystalline semiconductor layers is provided, wherein the detach region is positioned between the device structure and substrate. The stack is... Agent: Schmeiser Olsen & Watts

20080261381 - Method for manufacturing bonded substrate: There is provided a method for manufacturing a bonded substrate in which an insulator substrate is used as a handle wafer and a donor wafer is bonded to a front surface of the insulator substrate, the method comprises at least that a sandblast treatment is performed with respect to a... Agent: Oliff & Berridge, PLC

20080261382 - Wafer dicing using a fiber mopa: Silicon wafer dicing apparatus includes a master oscillator power amplifier (MOPA) arrangement wherein the master oscillator includes a continuous wave (CW) laser the output of which modulated by an external modulator to provide optical pulses to be amplified in the power amplifier. In one example of the apparatus the power... Agent: Stallman & Pollock LLP

20080261383 - Semiconductor workpiece carriers and methods for processing semiconductor workpieces: Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier assembly includes (a) a support structure having an opening sized to receive at least a portion of a semiconductor workpiece, and (b) a replaceable carrier positioned at the opening. The replaceable... Agent: Perkins Coie LLP Patent-sea

20080261384 - Method of removing photoresist layer and method of fabricating semiconductor device using the same: A method of removing a photoresist layer is provided. An ion implantation process has been performed on the photoresist layer to transform a surface of the photoresist layer to a crust and a soft photoresist layer remains within the crust. The method includes performing a first removing step to remove... Agent: J C Patents, Inc.

20080261385 - Method for selective removal of a layer: A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method... Agent: Freescale Semiconductor, Inc. Law Department

20080261386 - Sample wafer fabrication method: A third channel region into which a high concentration N-type impurity is implanted, a fourth channel region into which a low concentration N-type impurity is implanted, a first channel region into which a high concentration P-type impurity is implanted, and a second channel region into which a low concentration P-type... Agent: Young & Thompson

20080261387 - Semiconductor device and method of manufacturing semiconductor device: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261388 - Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å... Agent: Kevin L. Beaman

20080261389 - Method of forming micro pattern of semiconductor device: A method of forming a micro pattern of a semiconductor device method includes forming an etch target layer over a substrate, a hard mask layer over the etch target layer, and first auxiliary patterns over the etch target layer. The first auxiliary patterns defining a plurality of structures that are... Agent: Townsend And Townsend And Crew, LLP

20080261390 - Method for forming bumps on under bump metallurgy: A method for forming metal bumps is provided. A bonding pad is first formed on the active surface of a chip and then a passivation layer is formed on the active surface of the chip and exposes the bonding pad. An under bump metallurgy is formed on the active surface... Agent: Lowe Hauptman Ham & Berner, LLP

20080261391 - Method of producing semiconductor device: A method of producing a semiconductor device includes the steps of: preparing a base member; laminating sequentially a barrier film formed of titanium nitride, a wiring portion film formed of tungsten, and a mask film formed of titanium nitride on the base member to form a multi-layer film; forming a... Agent: Kubotera & Associates, LLC

20080261392 - Conductive via formation: A method involves depositing a first electrically conductive material, using a deposition technique, into a via formed in a material, the via having a diameter at a surface of the material of less than about 10 μm and a depth of greater than about 50 μm, so as to form... Agent: Foley & Lardner LLP

20080261393 - Reducing wire erosion during damascene processing: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may... Agent: Greenblum & Bernstein, P.L.C

20080261394 - Method for fabricating semiconductor device with silicided gate: A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at... Agent: Slater & Matsil, L.L.P.

20080261395 - Semiconductor device, method for manufacturing semiconductor devices and mask systems used in the manufacturing of semiconductor devices: Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned... Agent: Slater & Matsil, L.L.P.

20080261396 - Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same: A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole,... Agent: Ladas & Parry LLP

20080261397 - Method for manufacturing semiconductor device: There is provided a method for manufacturing a semiconductor device, which includes the steps of: providing a semiconductor substrate including a gate, a source and a drain, wherein the gate includes a gate dielectric layer disposed on the semiconductor substrate; forming an etching barrier layer on the semiconductor substrate; and... Agent: Squire, Sanders & Dempsey L.L.P.

20080261398 - Semiconductor device having oxidized metal film and manufacture method of the same: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080261399 - Method for chemical mechanical polishing in a scan manner of a semiconductor device: The chemical mechanical polishing of a semiconductor device includes polishing a target layer to be polished through a chemical reaction by slurry and a mechanical process by a polishing pad. Then performing a post cleaning composed of cleaning, rinsing and drying of the surface of the polished target layer. The... Agent: Ladas & Parry LLP

20080261400 - Polishing composition, polishing method, and method for forming copper wiring for semiconductor integrated circuit: The present invention provides a polishing composition containing a neutralized carboxylic acid, an oxidizer and water, wherein a part of the carboxylic acid is an alicyclic resin acid (A) and the pH value is within a range of from 7.5 to 12. The alicyclic resin acid is preferably at least... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261401 - Chemical-mechanical polishing of sic surfaces using hydrogen peroxide or ozonated water solutions in combination with colloidal abrasive: A process is taught for producing a smooth, damage-free surface on a SiC wafer, suitable for subsequent epitaxial film growth or ion implantation and semiconductor device fabrication. The process uses certain oxygenated solutions in combination with a colloidal abrasive in order to remove material from the wafer surface in a... Agent: The Webb Law Firm, P.C.

20080261402 - Method of removing insulating layer on substrate: A method of removing an insulating layer on a substrate is described, including a first CMP process and a second CMP process performed in sequence, wherein the polishing slurry used in the first CMP process and that used in the second CMP process have substantially the same pH value that... Agent: Jianq Chyun Intellectual Property Office

20080261403 - Method for obtaining high-quality boundary for semiconductor devices fabricated on a partitioned substrate: One embodiment of the present invention provides a process for obtaining high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate. During operation, the process receives a trench-partitioned substrate wherein the substrate surface is partitioned into arrays of isolated deposition platforms which are separated by arrays of... Agent: Park, Vaughan & Fleming LLP

20080261404 - Method of making semiconductor device: A plasma processing method, which enables the etching controllability for a high-dielectric-constant insulating film to be improved. A substrate having a high-dielectric-constant gate insulating film and a hard mask formed thereon is subjected to etching processing using a plasma of a processing gas containing a noble gas and a reducing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261405 - Hydrogen ashing enhanced with water vapor and diluent gas: An oxygen-free hydrogen plasma ashing process particularly useful for low-k dielectric materials based on hydrogenated silicon oxycarbide materials. The main ashing step includes exposing a previously etched dielectric layer to a plasma of hydrogen and optional nitrogen, a larger amount of water vapor, and a yet larger amount of argon... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20080261406 - Etching method and semiconductor device fabrication method: An etching method capable of increasing the selectivity of a polysilicon film to a silicon oxide film and suppressing recess formation on a silicon base layer. That part of the polysilicon film of a wafer transferred into a processing vessel which is exposed through an opening is etched so as... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080261408 - Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors: A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080261409 - Processing device and method for processing a substrate: A processing device for producing a layer system including at least one layer of an organic light emitting semiconductor material (OLED), comprises (1) a configuration of one or more treatment stations for processing the substrate in the treatment stations and (2) a first encapsulation module for providing an encapsulation element... Agent: Townsend And Townsend And Crew, LLP

20080261407 - Semiconductor device with hydrogen barrier and method therefor: A method of forming a semiconductor device comprises providing a portion of a semiconductor device structure, wherein the portion includes a region susceptible to hydrogen incorporation due to subsequent device processing. For example, the subsequent device processing can include one or more of (i) forming a layer over the region,... Agent: Freescale Semiconductor, Inc. Law Department

20080261410 - Method for treating base oxide to improve high-k material deposition: A method for forming a high-K material layer in a semiconductor device fabrication process including providing a silicon semiconductor substrate or thermally growing interfacial oxide layer comprising silicon dioxide over the silicon substrate; treating with an aqueous base solution or nitridation and depositing a high-K material layer.... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080261411 - Method for manufacturing soi substrate: The present invention provides a method for manufacturing an SOI substrate by which an oxygen ion is implanted from at least one of main surfaces of a single-crystal silicon substrate to form an oxygen-ion-implanted layer and then an oxide film-forming heat treatment that changes the formed oxygen-ion-implanted layer into a... Agent: Oliff & Berridge, PLC

20080261412 - Apparatus and method for atomic layer deposition: The embodiments provide apparatus and methods of depositing conformal thin film on interconnect structures by providing processes and systems using an atomic layer deposition (ALD). More specifically, each of the ALD systems includes a proximity head that has a small reaction volume right above an active process region of the... Agent: Martine Penilla & Gencarella, LLP

20080261413 - Pretreatment processes within a batch ald reactor: Embodiments of the invention provide methods for forming a hafnium material on a substrate within a processing chamber. In one embodiment, a method is provided which includes exposing the substrate within the processing chamber to a first oxidizing gas during a pretreatment process, exposing the substrate sequentially to a second... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080254553 - In situ, ex situ and inline process monitoring, optimization and fabrication: Methods and systems for in situ process control, monitoring, optimization and fabrication of devices and components on semiconductor and related material substrates includes a light illumination system and electrical probe circuitry. The light illumination system may include a light source and detectors to measure optical properties of the in situ... Agent: Macpherson Kwok Chen & Heid LLP

20080254554 - Method for producing optical coupling element: A method for producing an optical coupling element of the present invention includes the steps of: determining the mounting position of a light-emitting element and a light-receiving element on the front surface of the header portion of each lead frame based on the current amplification factor of the light-receiving element... Agent: Birch Stewart Kolasch & Birch

20080254555 - Patterning method for light-emitting devices: m

20080254556 - Semiconductor light emitting device and method of manufacture: A light-emitting diode (“LED”) device has an LED chip attached to a substrate. The terminals of the LED chip are electrically coupled to leads of the LED device. Elastomeric encapsulant within a receptacle of the LED device surrounds the LED chip. A second encapsulant is disposed within an aperture of... Agent: Kathy Manke Avago Technologies Limited

20080254557 - Method for manufacturing lens for led package: A method for manufacturing a lens for a light emitting diode (LED) package is disclosed. The method for manufacturing a lens for an LED package includes: forming a dome lens on each of a plurality of LED packages placed on a fixing plate, the dome lens made of silicon; forming... Agent: Nath & Associates

20080254558 - Side-emitting led package and method of manufacturing the same: The invention relates to a side-emitting LED package and a manufacturing method thereof. The side-emitting LED package includes a substrate with an electrode formed thereon, and a light source disposed on the substrate and electrically connected to the electrode. The side-emitting LED package also includes a molded part having an... Agent: Mcdermott Will & Emery LLP

20080254559 - Method of fabricating liquid crystal display device: Provided is a method of fabricating a liquid crystal display device. The method includes fabricating a liquid crystal panel divided into transmission and non-transmission regions, and including an upper substrate and a lower substrate, which are spaced apart from and opposite to each other, and a liquid crystal layer filled... Agent: The Webb Law Firm, P.C.

20080254560 - Display device, method for manufacturing display device, and soi substrate: A manufacturing method is provided which achieves an SOI substrate with a large area and can improve productivity of manufacture of a display device using the SOI substrate. A plurality of single-crystalline semiconductor layers are bonded to a substrate having an insulating surface, and a circuit including a transistor is... Agent: Eric Robinson

20080254562 - Method of making a light emitting element: A method of making a light emitting element, the light emitting element with a semiconductor layer represented by: AlxInyGa1-x-yN (0≦X≦1, 0≦Y≦1, 0≦X+Y≦1), has the step of wet-etching a surface of the semiconductor layer by using an etching solution to have a roughened surface on the semiconductor layer. The wet-etching is... Agent: Mcginn Intellectual Property Law Group, PLLC

20080254563 - Method for manufacturing semiconductor optical device: A method for manufacturing a semiconductor optical device includes: forming a p-type cladding layer; forming a capping layer on the p-type cladding layer the capping layer being selectively etchable relative to the p-type cladding layer; forming a through film on the capping layer; forming a window structure by in implantation;... Agent: Leydig Voit & Mayer, Ltd

20080254564 - Method for manufacturing solid-state image sensor and solid-state image sensor: There is provide a divided exposure technology capable of restraining deterioration in the performance of a solid-state image sensor. A photoresist is formed over a semiconductor substrate and subjected to divided exposure. A dividing line for divided exposure is located at least over a region of a semiconductor substrate in... Agent: Miles & Stockbridge PC

20080254565 - Method for fabricating semiconductor image sensor: A semiconductor image sensor and a method for fabricating the same are described. The semiconductor image sensor includes a substrate having at least a photoactive region therein and an IR cutting layer over the photoactive region.... Agent: J C Patents, Inc.

20080254566 - Surface-emission semiconductor laser device: A surface-emitting semiconductor laser device includes a semi-insulating substrate, a layer structure with a bottom multilayer reflector, an n-type cladding layer, an active layer structure for emitting laser, a p-type cladding layer and a top multilayer reflector with a dielectric material, consecutively formed on the semi-insulating substrate, the active layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080254567 - Thick film conductive composition and processe for use in the manufacture of semiconductor device: The present invention is directed to a thick film conductive composition comprising: a) electrically conductive silver powder; b) ZnO powder; c) lead-free glass frits wherein based on total glass frits: Bi2O3: >5 mol %, B2O3: <15 mol %, BaO: <5 mol %, SrO: <5 mol %, Al2O3: <5 mol %;... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080254568 - Composition and method of forming a device: The present invention provides a method of forming a semiconducting device comprising an organic semiconducting material, which method comprises: heating a composition comprising the organic semiconducting material to a temperature at or above the melting point or glass transition temperature of the composition to form a melt; cooling the melt... Agent: Philips Intellectual Property & Standards

20080254561 - Method of fabricating vertical structure compound semiconductor devices: A method of fabricating a vertical structure opto-electronic device includes fabricating a plurality of vertical structure opto-electronic devices on a crystal substrate, and then removing the substrate using a laser lift-off process. The method then fabricates a metal support structure in place of the substrate. In one aspects the step... Agent: Ipsg, P.C.

20080254569 - Semiconductor device: One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more of a metal oxide including zinc-gallium, cadmium-gallium, cadmium-indium.... Agent: Hewlett Packard Company

20080254570 - Angle control of multi-cavity molded components for mems and nems group assembly: A method of making a mold includes forming spaced mold cavities in a mold body. The mold cavities include geometrically similar portions, but have respective depths below an initial reference surface that vary as a function of position along a particular direction. The mold cavities can be formed using anisotropic... Agent: Townsend And Townsend And Crew, LLP

20080254571 - System in package (sip) with dual laminate interposers: There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and... Agent: Fletcher Yoder (micron Technology, Inc.)

20080254572 - Vertical system integration: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use... Agent: Michael J. Ure

20080254573 - Integrated circuit thermal management method and apparatus: An apparatus, method, and system for providing thermal management for an integrated circuit includes a first metallic layer directly placed on a back surface of the integrated circuit. An integrated heat spreader with a substantially cap-like shape is placed over the integrated circuit, with an aperture of a ceiling wall... Agent: Schwabe, Williamson & Wyatt, P.C.

20080254574 - Semiconductor device and a manufacturing method of the same: By preparing a package substrate which has a plurality of lands of NSMD structure, and the output wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180° symmetry, and printing solder by a printing method to the lands... Agent: Miles & Stockbridge PC

20080254575 - Encapsulation method and apparatus: A method and apparatus for encapsulating items such as electronic devices. A mold material is dispensed onto the electronic device and the device is situated between first and second molds. One mold is moved towards the other so as to vary the size of a cavity defined by the first... Agent: Dicke, Billig & Czaja

20080254576 - Method of fabricating a self-aligning damascene memory structure: A method of forming a three-dimensional, non-volatile memory array utilizing damascene fabrication techniques is disclosed. A bottom set of conductors is formed and a set of first pillar shaped elements of heavily doped semiconductor material as formed thereon. A mold is formed of insulating material having pillar shaped openings self-aligned... Agent: Dugan & Dugan, PC

20080254577 - Sectional field effect devices and method of fabrication: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and... Agent: George Sai-halasz

20080254578 - Method for fabricating thin film transistors: A method for fabricating thin film transistors is disclosed. An amorphous silicon film is formed on a substrated and selectively irradiated with a laser beam for lateral growth to form a plurality of polysilicon regions. The whole surface of the substrate is then oxidized and irradiated with exicer laser annealing.... Agent: Joe Mckinney Muncy

20080254580 - Realization of self-positioned contacts by epitaxy: Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region of the substrate surface (for example, through epitaxial growth). The growth material is surrounded by an insulating material. The grown... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080254579 - Semiconductor device and fabrication thereof: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080254581 - Semiconductor device and method for manufacturing the same: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080254582 - Semiconductor integrated circuit device having single-element type non-volatile memory elements: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080254583 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device includes steps of forming a gate electrode on the surface of a region of a semiconductor substrate provided with a first element, forming an insulating film to cover the surface of the gate electrode and another region of the semiconductor substrate provided with... Agent: Mcdermott Will & Emery LLP

20080254584 - Method of manufacturing flash memory device: A method for manufacturing a flash memory device including providing a semiconductor substrate having a cell region and a periphery region; and then adjusting a threshold voltage of the cell region; and then forming a memory device on the cell region and forming a transistor on the periphery region; and... Agent: Sherr & Vaughn, PLLC

20080254585 - Method for fabricating semiconductor memory: A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation region; forming a gate electrode by forming a... Agent: Rabin & Berdo, PC

20080254586 - Soi semiconductor device with body contact and method thereof: A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor... Agent: Freescale Semiconductor, Inc. Law Department

20080254587 - Method for manufacturing semiconductor devices using self-aligned process to increase device packing density: A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon... Agent: Townsend And Townsend And Crew, LLP

20080254588 - Methods for forming transistors with high-k dielectric layers and transistors formed therefrom: A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such... Agent: Duane Morris LLPIPDepartment (tsmc)

20080254589 - Method for manufacturing collars of deep trench capacitors: A method for manufacturing collars of deep trench capacitors includes providing a substrate with a deep trench in which there is a trench capacitor in the bottom; forming an inner wall layer completely covering the deep trench and the substrate; forming a hard mask layer on the surface of the... Agent: North America Intellectual Property Corporation

20080254590 - Fabrication process for silicon-on-insulator field effect transistors using high temperature nitrogen annealing: Disclosed is a method of fabricating a silicon-on-insulator (SOI) device that enables high device densities and mitigates variances in carrier mobility and saturation drain current (Idsat). The fabrication method incorporates one or more high temperature nitrogen anneal processes. The high temperature nitrogen anneal nitridizes the interfaces between the n-well and... Agent: Honeywell International Inc. Patent Services

20080254591 - Method for making a thin-film element: A method for making a thin-film element includes epitaxially growing a first crystalline layer on a second crystalline layer of a support where the second crystalline layer is a material different from the first crystalline layer, the first crystalline layer having a thickness less than a critical thickness. A dielectric... Agent: Brinks Hofer Gilson & Lione

20080254592 - Method of forming isolation structure for semiconductor integrated circuit substrate: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of... Agent: Patentability Associates

20080254593 - Method for fabricating isolation layer in semiconductor device: A method of fabricating an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, depositing a high-density plasma (HDP) oxide layer partially filling the trench by supplying an HDP deposition source, etching an overhang generated while the HDP oxide layer is deposited using a fluorine-containing... Agent: Marshall, Gerstein & Borun LLP

20080254594 - Strained silicon cmos on hybrid crystal orientations: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080254595 - Method for manufacturing soi substrate: A silicon substrate 10 used for bonding is a single-crystal Si substrate in which an interstitial oxygen concentration measured by infrared absorption spectrophotometry is equal to or below 1×1018 cm−3. The interstitial oxygen concentration of the single-crystal silicon substrate is set to 1×1018 cm−3 or below since a degree of... Agent: Oliff & Berridge, PLC

20080254597 - Method for manufacturing soi substrate: A method for manufacturing an SOI substrate superior in film thickness uniformity and resistivity uniformity in a substrate surface of a silicon layer having a film thickness reduced by an etch-back method is provided. After B ions is implanted into a front surface of a single-crystal Si substrate 10 to... Agent: Oliff & Berridge, PLC

20080254596 - Method for transferring wafers: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer,... Agent: Thelen Reid Brown Raysman & Steiner LLP

20080254598 - Laser irradiation method, laser irradiation apparatus, and semiconductor device: An object of the present invention is obtaining a semiconductor film with uniform characteristics by improving irradiation variations of the semiconductor film. The irradiation variations are generated due to scanning while irradiating with a linear laser beam of the pulse emission. At a laser crystallization step of irradiating a semiconductor... Agent: Cook Alex Ltd

20080254599 - Thermal processing of silicon wafers: Apparatus and methods that minimize surface defect development in silicon wafers during thermal processing at relatively high temperatures at which silicon wafers are annealed and at less extreme temperature, or for other purposes. The apparatus and methods have utility to horizontally-disposed furnaces for silicon wafers and to vertically-oriented furnaces in... Agent: North Weber & Baugh LLP

20080254600 - Methods for forming interconnect structures: A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric... Agent: Duane Morris LLPIPDepartment (tsmc)

20080254601 - Methods for optimizing thin film formation with reactive gases: A method for producing a Group IV semiconductor thin film in a chamber is disclosed. The method includes positioning a substrate in the chamber, wherein the chamber further has a chamber pressure. The method further includes depositing a nanoparticle ink on the substrate, the nanoparticle ink including set of Group... Agent: Foley & Lardner LLP

20080254602 - Method of impurity introduction and: A method of introducing an impurity into a wafer surface is provided. The method comprises the steps of: low energy implantation of impurity into a surface of the wafer to generate an implanted dopant layer; and simultaneously removing an implanted surface of the implanted dopant layer to generate a doping... Agent: Townsend And Townsend And Crew, LLP

20080254603 - Method of fabricating semiconductor device: There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this... Agent: Fasse Patent Attorneys, P.A.

20080254604 - Method for fabricating a hybrid orientation substrate: A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second... Agent: North America Intellectual Property Corporation

20080254606 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the... Agent: Ladas & Parry LLP

20080254605 - Method of reducing the interfacial oxide thickness: One inventive aspect is related to a method of minimizing the final thickness of an interfacial oxide layer between a semiconductor material and a high dielectric constant material. The method comprises depositing a covering layer on the high dielectric constant material. The method further comprises removing adsorbed/absorbed water from the... Agent: Knobbe Martens Olson & Bear LLP

20080254607 - integration approach to form the core floating gate for flash memory using an amorphous carbon hard mask and arf lithography: Systems and methods are described that facilitate integrating ArF core patterning of floating gate structures in a flash memory device followed by KrF periphery gate patterning using a hard mask comprising a material such as amorphous carbon to facilitate core gate construction. The amorphous carbon hard mask can facilitate preparing... Agent: Amin, Turocy & Calvin, LLP

20080254608 - Method of forming contact structure and method of fabricating semiconductor device using the same: A method of forming a contact structure includes forming an isolation region defining active regions in a semiconductor substrate. Gate patterns extending to the isolation region while crossing the active regions are formed. A sacrificial layer is formed on the semiconductor substrate having the gate patterns. Sacrificial patterns remaining on... Agent: Marger Johnson & Mccollom, P.C.

20080254609 - Apparatus and method for electronic fuse with improved esd tolerance: Method of making an electronic fuse blow resistor structure. In one embodiment, the method includes forming an insulator film, depositing a conductor on the insulator film, and after the depositing, etching the conductor to form a plurality of spaced apart non-conductive regions and a plurality of spaced-apart conductive regions. In... Agent: Greenblum & Bernstein, P.L.C

20080254610 - Semiconductor device and process for manufacturing the same: The present invention relates to a semiconductor device in which electrodes formed on a semiconductor chip and electrodes formed on a wiring board are electrically connected via projecting elastic electrodes, and further relates to a mounting method of reducing a pressure applied to electrodes formed on a substrate or underlying... Agent: Mcdermott Will & Emery LLP

20080254611 - Interconnection designs and materials having improved strength and fatigue life: Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large... Agent: Marger Johnson & Mccollom, P.C. - Intel

20080254612 - Polycarbosilane buried etch stops in interconnect structures: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, O≦y≦0.3,... Agent: Scully, Scott, Murphy & Presser, P.C.

20080254613 - Methods for forming metal interconnect structure for thin film transistor applications: Methods for forming a metal interconnection structure in thin-film transistor applications are provided in the present invention. In one embodiment, the method may include providing a substrate into a processing chamber, supplying a first gas mixture into the chamber to deposit a metal layer on the substrate, and supplying a... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080254614 - Multilayered cap barrier in microelectronic interconnect structures: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures... Agent: Scully, Scott, Murphy & Presser, P.C.

20080254615 - Method for reducing dielectric overetch using a dielectric etch stop at a planar surface: A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch... Agent: Dugan & Dugan, PC

20080254616 - Semiconductor device and a method of manufacturing the same: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching... Agent: Miles & Stockbridge PC

20080254617 - Void-free contact plug: A semiconductor device manufacturing process for forming a contact plug includes sequentially depositing a titanium or tantalum contact layer (30), a titanium nitride barrier layer (40), and a tungsten seed layer (50) in a contact opening (24). The contact hole (24) is then filled up from a bottom surface of... Agent: Hamilton & Terrile, LLP

20080254618 - Method of manufacturing a semiconductor device: The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling... Agent: Morrison & Foerster LLP

20080254620 - Method for fabricating landing plug of semiconductor device: A method of fabricating a landing plug of a semiconductor device includes performing a double patterning process to separately form a landing plug contact hole for a storage node and a landing plug contact hole for a bit line, thereby facilitating forming a device having a half pitch of 30... Agent: Marshall, Gerstein & Borun LLP

20080254619 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device is provided. First, a semiconductor substrate and a dielectric layer positioned on the semiconductor substrate are prepared. Subsequently, the dielectric layer is etched to form a hole structure in the dielectric layer. Afterward, a degas process is performed. An ultraviolet (UV) treatment is... Agent: North America Intellectual Property Corporation

20080254621 - Wafer electroless plating system and associated methods: A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an... Agent: Martine Penilla & Gencarella, LLP

20080254622 - Cmos silicide metal gate integration: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height,... Agent: Scully, Scott, Murphy & Presser, P.C.

20080254623 - Methods for growing low-resistivity tungsten for high aspect ratio and small features: The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten... Agent: Beyer Weaver LLP

20080254624 - Metal cap for interconnect structures: A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer... Agent: International Business Machines Corporation Dept. 18g

20080254627 - Method for adjusting feature size and position: Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sidewalls. The critical dimension of the spacers is selected... Agent: Knobbe Martens Olson & Bear LLP

20080254625 - Method for cleaning a semiconductor structure and chemistry thereof: A method for removing a etch residue (e.g., polymer or particle) from a semiconductor structure and using a cleaning chemistry and the composition of the chemistry is described. By providing a semiconductor structure with etch residue on it, the semiconductor substrate is then placed in a chemistry to remove the... Agent: Freescale Semiconductor, Inc. Law Department

20080254626 - Processing apparatus: A processing apparatus for transferring a relief pattern on a mold to a resist on a substrate through a compression of the mold against the resist, includes a supplier for supplying the resist between the substrate and the mold, and a recovery unit for recovering the resist.... Agent: Morgan & Finnegan, L.L.P.

20080254629 - Composition and method used for chemical mechanical planarization of metals: Compositions for use in CMP processing and methods of CMP processing. The composition utilizes low levels of particulate material, in combination with at least one amino acid, at least one oxidizer, and water to remove a metal layer such as one containing copper to a stop layer with high selectivity.... Agent: Hayden Stone, PLLC

20080254628 - High throughput chemical mechanical polishing composition for metal film planarization: A chemical mechanical polishing process including a single copper removal CMP slurry formulation for planarization of a microelectronic device structure preferably having copper deposited thereon. The process includes the bulk removal of a copper layer using a first CMP slurry formulation having oxidizing agent, passivating agent, abrasive and solvent, and... Agent: Moore & Van Allen PLLC

20080254630 - Device and methodology for reducing effective dielectric constant in semiconductor devices: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features... Agent: Greenblum & Bernstein, P.L.C

20080254631 - Method for fabrication of semiconductor device: Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the... Agent: David R. Metzger Sonnenschein Nath & Rosenthal LLP

20080254632 - Method for forming a semiconductor structure having nanometer line-width: A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first... Agent: Bacon & Thomas, PLLC

20080254633 - Multiple exposure lithography method incorporating intermediate layer patterning: A method of patterning a semiconductor substrate includes creating a first set of patterned features in a first inorganic layer; creating a second set of patterned features in one of the first inorganic layer and a second inorganic layer; and transferring, into an organic underlayer, both the first and second... Agent: Cantor Colburn LLP - IBM Fishkill

20080254634 - Photoresist composition and method of manufacturing a thin-film transistor substrate using the same: m

20080254635 - Method for accelerated etching of silicon: A method for the plasma-free etching of silicon using the etching gas ClF3 or XeF2 and its use are provided. The silicon is provided having one or more areas to be etched as a layer on the substrate or as the substrate material itself. The silicon is converted into the... Agent: Kenyon & Kenyon LLP

20080254636 - Etching of silicon oxide film: An etching method includes preparing a target object such that a first oxide film made of silicon oxide containing at least one of B and P is formed on a substrate, a second oxide film made of silicon oxide containing neither of B and P is formed on the first... Agent: Smith, Gambrell & Russell

20080254637 - Methods for removing photoresist defects and a source gas for same: A method for removing at least one photoresist defect is disclosed. The photoresist defect is exposed to a plasma produced from a source gas including oxygen and a non-oxidizing gas in a plasma reactor, wherein the oxygen is present in the source gas at from 1% by volume to about... Agent: Trask Britt, P.C./ Micron Technology

20080254638 - Etch process with controlled critical dimension shrink: Methods to etch an opening in a substrate layer with reduced critical dimensions are described. A multi-layered mask including a lithographically patterned photoresist and an unpatterned organic antireflective coating (BARC) is formed over a substrate layer to be etched. The BARC layer is etched with a significant negative etch bias... Agent: Applied Materials/bstz Blakely Sokoloff Taylor & Zafman LLP

20080254639 - Method for etching organic hardmasks: A method of etching or removing an amorphous carbon organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an amorphous carbon organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0,... Agent: Law Office Of Delio & Peterson, LLC.

20080254640 - Method of removing material layer and remnant metal: A method of removing material layer is disclosed. First, a semiconductor substrate is fixed on a rotating platform, where a remnant material layer is included on the surface of the semiconductor substrate. Afterward, an etching process is carried out. In the etching process, the rotating platform is rotated, and an... Agent: North America Intellectual Property Corporation

20080254641 - Manufacturing method of semiconductor device and film deposition system: A dielectric film (91) made of CF is deposited on a substrate. A protective layer comprising an SiCN film (93) is formed on the dielectric film (91). A film (94) serving as a hardmask made of SiCO is deposited on the protective layer by a plasma containing active species of... Agent: Smith, Gambrell & Russell

20080254642 - Method of fabricating gate dielectric layer: A method for fabricating gate dielectric layer is provided. First, a sacrificial layer is formed on a substrate. Next, fluorine ions are implanted into the substrate. Then, the sacrificial layer is then removed. Finally, a dielectric layer is formed on the substrate.... Agent: J C Patents, Inc.

20080254643 - Structure to improve adhesion between top cvd low-k dielectric and dielectric capping layer: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion... Agent: Scully, Scott, Murphy & Presser, P.C.

20080254644 - Method of substrate treatment, computer-readable recording medium, substrate treating apparatus and substrate treating system: A disclosed substrate processing method in a single wafer substrate processing device including a first process position for introducing nitrogen atoms to a high-dielectric film and a second process position for performing heat treatment on the high-dielectric film includes: successively conveying plural substrates to be processed to the first process... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080254645 - Light irradiation apparatus, crystallization apparatus, crystallization method, and device: A light irradiation apparatus includes a light modulation element which has a step line of a phase step having a phase difference different from 180 degrees, and modulates a phase of incident light. An illumination optical system illuminates the modulation element with illumination light inclined in a direction perpendicular to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080248595 - Method for manufacturing semiconductor device and computer storage medium: A method for fabricating a semiconductor device includes the steps of forming a PbTiOx film having a predominantly (111) orientation on a lower electrode as a nucleation layer by an MOCVD process with a film thickness exceeding 2 nm, and forming a PZT film having a predominantly (111) orientation on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080248596 - Method of making a circuitized substrate having at least one capacitor therein: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser.... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20080248597 - Methods for determining a dose of an impurity implanted in a semiconductor substrate and an apparatus for same: Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a semiconductor substrate is directly measured, such as by utilizing a Faraday cup. A ratio of impurity-based ion species to non-impurity-based ion species in a... Agent: Trask Britt, P.C./ Micron Technology

20080248598 - Method and apparatus for determining characteristics of a stressed material using scatterometry: A method includes illuminating at least a portion of a first grid including a first plurality of stressed material regions formed at least partially in a semiconducting material. Light reflected from the illuminated portion of the first grid is measured to generate a first reflection profile. A characteristic of the... Agent: Williams, Morgan & Amerson

20080248599 - Rapid thermal anneal equipment and method using sichrome film: A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a... Agent: Texas Instruments Incorporated

20080248600 - Method and device for wafer backside alignment overlay accuracy: A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through... Agent: Haynes And Boone, LLP

20080248601 - Method of fusing trimming for semiconductor device: Deviation occurring in a particular region in a plane of a resistor group which constitutes a semiconductor integrated circuit is improved and a quick increase in yield is accomplished. Provided is a fuse trimming method for a semiconductor device in which circuit elements such as transistors and resistors are formed... Agent: Bruce L. Adams, Esq Adams & Wilks

20080248602 - Light emitting device processes: Light-emitting devices, and related components, processes, systems and methods are disclosed.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20080248603 - Nitride-based semiconductor element and method of preparing nitride-based semiconductor: A method of preparing a nitride semiconductor capable of forming a nitride-based semiconductor layer having a small number of dislocations as well as a small number of crystal defects resulting from desorption with excellent crystallinity on the upper surface of a substrate through a small number of growth steps is... Agent: Mcdermott Will & Emery LLP

20080248604 - Post-logic isolation of silicon regions for an integrated sensor: In producing an integrated sensor, regions of silicon between compensating electronics and a sensor are electrically isolated, while the sensor is delineating and released. The described process can be performed at the end of a fabrication process after electronics processing (i.e., CMOS processing) and compensating electronics are formed. In an... Agent: Delphi Technologies, Inc.

20080248605 - Method of forming a pressure switch thin film device: This invention provides a method of forming at least one pressure switch thin film device. The method includes providing a substrate and depositing a plurality of thin film device layers as a stack upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device... Agent: Hewlett Packard Company

20080248606 - Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed... Agent: Panitch Schwarze Belisario & Nadel LLP

20080248607 - Solid state image pickup device and its manufacture method: A solid state image pickup device is provided which includes: charge accumulation regions disposed in a semiconductor substrate in a matrix shape; a plurality of vertical transfer channels formed in the semiconductor substrate each in a close proximity to each column of the charge accumulation regions; vertical transfer electrodes formed... Agent: Birch Stewart Kolasch & Birch

20080248608 - Front side electrical contact for photodetector array and method of making same: A photodiode includes a semiconductor having front and backside surfaces and first and second active layers of opposite conductivity, separated by an intrinsic layer. A plurality of isolation trenches filled with conductive material extend into the first active layer, dividing the photodiode into a plurality of cells and forming a... Agent: Panitch Schwarze Belisario & Nadel LLP

20080248609 - Display device and method of fabricating the same: A constitution of the display device of the invention is shown in the following. The display device includes a pixel unit including TFTs of which the active layer contains an organic semiconductor material for forming channel portions in the opening portions in an insulating layer arranged to meet the gate... Agent: Nixon Peabody, LLP

20080248611 - Manufacturing method of semiconductor device: The quality and reliability of a semiconductor device can be improved by eliminating a warp of a chip and performing a chip-stack. A wiring substrate, the first semiconductor chip connected via the first gold bump on the wiring substrate, the second semiconductor chip stacked via the second gold bump on... Agent: Miles & Stockbridge PC

20080248610 - Thermal bonding process for chip packaging: The present invention provides a thermal bonding process for chip packaging. In accordance with an aspect of the invention, there is provided an approach to solve the problems caused by the different CTEs between the die and the substrate. It discloses an improved thermal bonding process for forming pillar-shaped interconnection,... Agent: Lawrence Y.d. Ho & Associates Pte Ltd

20080248612 - Asymmetric alignment of substrate interconnect to semiconductor die: An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect... Agent: Westman Champlin & Kelly, P.A.

20080248613 - Method of forming a micromechanical device with microfluidic lubricant channel: A micromechanical device assembly includes a micromechanical device enclosed within a processing region and a lubricant channel formed through an interior wall of the processing region and in fluid communication with the processing region. Lubricant is injected into the lubricant channel via capillary forces and held therein via surface tension... Agent: Patterson & Sheridan, L.L.P.

20080248614 - Wafer level package with good cte performance: The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die... Agent: Kusner & Jaffe Highland Place Suite 310

20080248615 - Cmos structure for body ties in ultra-thin soi (utsoi) substrates: The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in... Agent: Scully, Scott, Murphy & Presser, P.C.

20080248616 - Integration of strained ge into advanced cmos technology: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure... Agent: George Sai-halasz

20080248617 - Display substrate and method of manufacturing the same: A display substrate includes a base substrate, a first metal pattern, a gate insulating layer, a second metal pattern, a channel layer and a pixel electrode. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode of a switching element. The... Agent: Cantor Colburn, LLP

20080248618 - Atomic layer deposition of ceo2/al2o3 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric... Agent: Schwegman, Lundberg & Woessner/micron

20080248619 - Process for fabricating dynamic random access memory: A process for fabricating a dynamic random access memory is provided. In this fabrication process, the steps of forming the silicon layer, and performing the ion implantation process and the removing process are repeated at least twice and the oxidation process is performed once to form an oxidation spacer that... Agent: Jianq Chyun Intellectual Property Office

20080248620 - Gated semiconductor device and method of fabricating same: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate.... Agent: Slater & Matsil, L.L.P.

20080248621 - Integrated non-volatile memory and peripheral circuitry fabrication: Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer... Agent: Vierra Magen/sandisk Corporation

20080248622 - Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation: Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the... Agent: Vierra Magen/sandisk Corporation

20080248623 - Method for forming high-drain-voltage tolerance mosfet transistor in a cmos process flow with double well dose approach: A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of... Agent: Slater & Matsil, L.L.P.

20080248624 - Method of making integrated circuit (ic) including at least one storage cell: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080248625 - Methods for enhancing trench capacitance and trench capacitor: Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form... Agent: Hoffman Warnick LLC

20080248626 - Shallow trench isolation self-aligned to templated recrystallization boundary: A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization... Agent: Scully, Scott, Murphy & Presser, P.C.

20080248627 - Method of manufacturing integrated deep and shallow trench isolation structures: A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinting a first pattern into the... Agent: Texas Instruments Incorporated

20080248628 - Methods of forming integrated circuit devices having single crystal semiconductor fin structures that function as device active regions: Methods of forming integrated circuit devices include forming an electrically insulating layer having a semiconductor fin structure extending therethrough. This semiconductor fin structure may include at least one amorphous and/or polycrystalline semiconductor region therein. The at least one amorphous and/or polycrystalline semiconductor region within the semiconductor fin structure is then... Agent: Myers Bigel Sibley & Sajovec

20080248629 - Method for manufacturing semiconductor substrate: A method for manufacturing a semiconductor substrate is provided, which comprises a step of irradiating a single crystal semiconductor substrate with ions to form an embrittlement layer in the single crystal semiconductor substrate, a step of forming a silicon oxide film over the single crystal semiconductor substrate, a step of... Agent: Eric Robinson

20080248630 - Method of manufacturing bonded wafer: The present invention provides a method of manufacturing a bonded wafer. The method includes forming an oxygen ion implantation layer in an active layer wafer having a substrate resistivity of 1 to 100 mΩcm by implanting oxygen ions in the active layer wafer, bonding a base wafer and the active... Agent: Greenblum & Bernstein, P.L.C

20080248631 - Wafer and method of producing a substrate by transfer of a layer that includes foreign species: A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer... Agent: Winston & Strawn LLP Patent Department

20080248634 - Enhancement mode iii-nitride fet: A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device.... Agent: Ostrolenk Faber Gerb & Soffen

20080248633 - Method for manufacturing indium gallium aluminium nitride thin film on silicon substrate: The method for manufacturing the indium gallium aluminium nitride (InGaAlN) thin film on silicon substrate, which comprises the following steps: introducing magnesium metal for processing online region mask film, that is, or forming one magnesium mask film layer or metal transition layer; then forming one metal transition layer or magnesium... Agent: Park, Vaughan & Fleming LLP

20080248632 - Methods of fabricating multi-bit phase-change memory devices and devices formed thereby: Methods of forming integrated circuit devices include forming at least one non-volatile memory cell on a substrate. The memory cell includes a plurality of phase-changeable material regions therein that are electrically coupled in series. This plurality of phase-changeable material regions are collectively configured to support at least 2-bits of data... Agent: Myers Bigel Sibley & Sajovec

20080248635 - Polycrystalline sige junctions for advanced devices: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused... Agent: George Sai-halasz

20080248636 - Boron ion implantation using alternative fluorinated boron precursors, and formation of large boron hydrides for implanation: Methods of implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. A method of manufacturing a semiconductor device including implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. Also disclosed are a system for supplying a... Agent: Intellectual Property / Technology Law

20080248637 - Method of fabricating semiconductor device: In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A flash annealing process is performed on... Agent: Marshall, Gerstein & Borun LLP

20080248638 - Process for manufacturing voltage-controlled transistor: The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is... Agent: Jianq Chyun Intellectual Property Office

20080248639 - Method for forming electrode for group iii nitride based compound semiconductor and method for manufacturing p-type group iii nitride based compound semiconductor: An undoped GaN layer having a thickness of 3 μm is formed by MOVPE on a sapphire substrate with a buffer layer composed of aluminum nitride (AlN) therebetween. A GaN layer doped with 5×1019/cm3 of Mg and having a thickness of 100 nm is formed thereon. An ITO film having... Agent: Mcginn Intellectual Property Law Group, PLLC

20080248640 - Method for reducing polysilicon gate defects in semiconductor devices: Semiconductor devices and fabrication methods are provided, in which gate defects associated with photoresist stress after plasma trim/etch are substantially reduced. The method comprises forming a gate dielectric layer above a semiconductor body substrate; coating the gate dielectric layer with a photoresist coating; exposing and developing the photoresist coating; performing... Agent: Texas Instruments Incorporated

20080248641 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device according to this invention includes; forming a first region in which a first insulating film is formed on a semiconductor substrate surface and a second region on which the semiconductor substrate surface is exposed; cleaning the semiconductor substrate surface exposed in the second... Agent: Mcginn Intellectual Property Law Group, PLLC

20080248642 - Nanowire transistor and method for forming same: A method is provided for removing reentrant stringers in the fabrication of a nanowire transistor (NWT). The method provides a cylindrical nanostructure with an outside surface axis overlying a substrate surface. The nanostructure includes an insulated semiconductor core. A conductive film is conformally deposited overlying the nanostructure, to function as... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080248643 - Solder connector structure and method: Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080248644 - Method of fabricating a semiconductor device with a porous dielectric film: In the fabrication of a semiconductor device, an SiO2GeO2 film is formed on a substrate, then washed with water to dissolve the GeO2, leaving a porous SiO2 film. The SiO2GeO2 film may be deposited directly on the substrate, or an SiGe film may be deposited on the substrate and then... Agent: Volentine & Whitt PLLC

20080248645 - Method to create a metal pattern using a damascene-like process: A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive, insulative material. A conformed metal layer is formed over the dielectric layer and into the at least one trench and a photoresist layer is... Agent: Trask Britt, P.C./ Micron Technology

20080248646 - Method of fabricating a flash memory device: In a method of fabricating a flash memory device, an interlayer dielectric layer is formed on a semiconductor substrate. The interlayer dielectric layer is etched to form first contact holes through which junction regions of a cell region are exposed. First contact plugs are formed within the first contact holes.... Agent: Townsend And Townsend And Crew, LLP

20080248647 - Method of depositing materials on a non-planar surface: A method of depositing materials on a non-planar surface is disclosed. The method is effectuated by rotating non-planar substrates as they travel down a translational path of a processing chamber. As the non-planar substrates simultaneously rotate and translate down a processing chamber, the rotation exposes the whole or any desired... Agent: Haverstock & Owens LLP

20080248648 - Deposition precursors for semiconductor applications: This invention relates to organometallic compounds comprising at least one metal or metalloid and at least one substituted anionic 6 electron donor ligand having sufficient substitution (i) to impart decreased carbon concentration in a film or coating produced by decomposing said compound, (ii) to impart decreased resistivity in a film... Agent: Praxair, Inc. Law Department - M1 557

20080248649 - First inter-layer dielectric stack for non-volatile memory: A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer (72) with a substantially uniform thickness. After forming device components (32, 33) on a substrate (31), a gap fill dielectric layer of SATEOS (52) is deposited over an etch stop layer... Agent: Hamilton & Terrile, LLP

20080248650 - Etching apparatus and method for semiconductor device: Disclosed is an etching method for a semiconductor device. The protecting layer, such as the hydrocarbon layer or the hydrocarbon layer containing phosphorous, is formed on the photoresist layer by using the precursor gas containing no fluorine. Therefore, the etching process enabling the thin photoresist to have a high selectivity... Agent: Staas & Halsey LLP

20080248651 - Method for manufacturing semiconductor device and semiconductor device: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered... Agent: Young & Thompson

20080248652 - Semiconductor manufacturing apparatus and manufacturing method of semiconductor device: A semiconductor manufacturing apparatus includes a chamber, a gas supplier, a vacuum pump, an electrode, a conductive knitted wire mesh and a radio frequency power supply. The electrode is placed outside of the chamber and fixed to the chamber. The gas supplier supplies gas into the chamber. The vacuum pump... Agent: Young & Thompson

20080248653 - Etchant gas and a method for removing material from a late transition metal structure: An etchant gas and a method for removing at least a portion of a late transition metal structure are disclosed. The etchant gas includes PF3 and at least one oxidizing agent, such as at least one of oxygen, ozone, nitrous oxide, nitric oxide and hydrogen peroxide. The etchant gas provides... Agent: Trask Britt, P.C./ Micron Technology

20080248654 - Method of forming a micro pattern of a semiconductor device: A method of forming a micro pattern of a semiconductor device includes forming an etch target layer, a hard mask layer, a Bottom Anti-Reflective Coating (BARC) layer and a first photoresist pattern over a semiconductor substrate. An organic layer is formed on a surface of the first photoresist pattern. A... Agent: Townsend And Townsend And Crew, LLP

20080248655 - Development or removal of block copolymer or pmma-b-s-based resist using polar supercritical solvent: Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier... Agent: Hoffman Warnick LLC

20080248656 - Methods for stripping photoresist and/or cleaning metal regions: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.... Agent: Ingrassia Fisher & Lorenz, P.C.

20080248657 - Method and system for thermally processing a plurality of wafer-shaped objects: Process and system for processing wafer-shaped objects, such as semiconductor wafers is disclosed. In accordance with the present disclosure, a multiple of two wafers are processed in a thermal processing chamber. The thermal processing chamber is in communication with at least one heating device for heating the wafers. The wafers... Agent: Dority & Manning, P.A.

20080241968 - Manufacturing method, remanufacturing method and reshipping method for a semiconductor memory device: A manufacturing method, remanufacturing method and reshipping method for a semiconductor memory device capable of preventing the charge hold characteristic from deteriorating even if information data is repeatedly written and erased. The manufacturing method is for a semiconductor memory device having a plurality of memory cells in an FET structure... Agent: Studebaker & Brackett PC

20080241969 - In-line lithography and etch system: The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer sequences. The S-D creation procedures can be performed using S-D processing elements, the S-D evaluation procedures can be performed using S-D evaluation elements,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080241970 - Method and apparatus for performing a site-dependent dual damascene procedure: The present invention includes a method of performing a dual damascene procedure using Site-Dependent (S-D) procedures, the method including receiving a plurality of wafers and associated data by a S-D transfer subsystem coupled to a lithography-related subsystem, determining S-D wafer data for each wafer, establishing a first Dual Damascene processing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080241971 - Method and apparatus for performing a site-dependent dual patterning procedure: The present invention includes a method of performing a double-patterning (DP) processing sequence using a plurality of Site-Dependent (S-D) procedures, the method including receiving a first set of wafers by one or more subsystems in a processing system, creating one or more first patterned layers on a first set of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080241972 - Method of manufacturing a semiconductor device, pattern correction apparatus, and computer-readable recording medium: A method of manufacturing a semiconductor device includes measuring a first width of a first mask pattern formed in a photomask and a second width of a second mask pattern formed in the photomask, and deciding a temperature of heat treatment of a thickening material over a resist film based... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080241973 - Method of correcting a mask pattern and method of manufacturing a semiconductor device: The method of manufacturing a semiconductor device has deciding an amount of a correction of a mask pattern for a size of an active region of a semiconductor substrate, correcting the mask pattern on the basis of the decided amount of the correction, and exposing a resist film by using... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080241975 - Automated process control using optical metrology and photoresist parameters: To control a photolithography cluster using optical metrology, a structure is fabricated on a wafer using the photolithography cluster. A measured diffraction signal off the structure is obtained. The measured diffraction signal is compared to a simulated diffraction signal. The simulated diffraction signal is associated with one or more values... Agent: Morrison & Foerster LLP

20080241974 - Determining photoresist parameters using optical metrology: To generate a simulated diffraction signal, one or more values of one or more photoresist parameters, which characterize behavior of photoresist when the photoresist undergoes processing steps in a wafer application, are obtained. One or more values of one or more profile parameters are derived using the one or more... Agent: Morrison & Foerster LLP

20080241976 - Semiconductor device production process: A semiconductor device production process includes forming, on a prepared SOI wafer, semiconductor functional devices and substrate contacts. The substrate contacts connect to a support substrate of the SOI wafer. The semiconductor device production process also includes forming a pattern that connects the substrate contacts to external connection pads formed... Agent: Rabin & Berdo, PC

20080241977 - Semiconductor device with electrode pad having probe mark: A semiconductor device is formed by bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark formed... Agent: Mcdermott Will & Emery LLP

20080241978 - Light emitting device processes: Light-emitting devices, and related components, processes, systems and methods are disclosed.... Agent: Luminus Devices , Inc. C/o Wolf, Greenfield & Sacks , P.C.

20080241979 - Multi-directional light scattering led and manufacturing method thereof: A multidirectional light scattering LED and a manufacturing method thereof are disclosed. A metal oxide is irregular disposed over a second semiconductor layer and then is removed by etching. Part of the second semiconductor layer, part of a light-emitting layer or part of the first semiconductor layer is also removed... Agent: Rosenberg, Klein & Lee

20080241980 - Liquid crystal display: A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080241981 - Thin film semiconductor device and method for manufacturing same: A thin film semiconductor device is provided that includes a semiconductor thin film and a gate electrode. The semiconductor thin film has an active region turned into a polycrystalline region through irradiation with an energy beam. The gate electrode is provided to traverse the active region. In a channel part... Agent: Bell, Boyd & Lloyd, LLP

20080241983 - Method of manufacturing nitride semiconductor light-emitting device: Provided is a method of manufacturing a nitride semiconductor light-emitting device including the step of contacting a surfactant material with the surface of an n-type nitride semiconductor layer or the surface of a p-type nitride semiconductor layer before the growth of an active layer, or, with a grown crystal surface... Agent: Harness, Dickey & Pierce, P.L.C

20080241984 - Method for manufacturing semicondcutor sensor: A semiconductor sensor is disclosed that includes a substrate including at least a semiconductor layer. The substrate includes a weight arranging part in the vicinity of the center of the substrate, a flexible part around the weight arranging part, and supporting parts provided around the flexible part. The semiconductor sensor... Agent: Cooper & Dunham, LLP

20080241985 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to... Agent: Dickstein Shapiro LLP

20080241986 - Method for fabricating a silicon solar cell structure having amorphous silicon layers: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.... Agent: Alston & Bird LLP

20080241988 - Method for fabricating a silicon solar cell structure having a gallium doped p-silicon substrate: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.... Agent: Alston & Bird LLP

20080241987 - Method for fabricating a silicon solar cell structure having silicon nitride layers: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.... Agent: Alston & Bird LLP

20080241990 - Method for manufacturing organic thin film transistor substrate: A method for manufacturing an organic thin film transistor substrate comprising forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, defining a channel region on the gate insulating layer between a source electrode and a drain electrode, neutralizing the channel region, forming a... Agent: Macpherson Kwok Chen & Heid LLP

20080241989 - Oled patterning method: A method of patterning a substrate according to several steps, including: a) mechanically locating a first masking film over the substrate; and b) segmenting the first masking film into a first masking portion and one or more first opening portions in first locations. Next, mechanically locate a first removal film... Agent: David Novais Patent Legal Staff

20080241982 - Vertical gan-based led and method of manufacturing the same: Provided are a vertical GaN-based LED and a method of manufacturing the same. The vertical GaN-based LED includes an n-electrode. An AlGaN layer is formed under the n-electrode. An undoped GaN layer is formed under the AlGaN layer to provide a two-dimensional electron gas layer to a junction interface of... Agent: Mcdermott Will & Emery LLP

20080241991 - Gang flipping for flip-chip packaging: An improved method and apparatus for packaging integrated circuits are described. More particularly, a method and apparatus for use in securing a plurality of integrated circuit dice to a lead frame panel are described. Each integrated circuit die includes an active surface having a multiplicity of solder bumps. The lead... Agent: Beyer Law Group LLP

20080241992 - Method of assembling chips: A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is... Agent: Megica Corporation

20080241993 - Gang flipping for ic packaging: A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is... Agent: Beyer Law Group LLP

20080241994 - Print mask and method of manufacturing electronic components using the same: A print mask is used to form bumps on barrier metal layers of a wafer. The mask comprises a plurality of elongated perforations disposed in a linear arrangement such that paste can be applied to an object to be printed on via the perforations. Each of the perforations includes an... Agent: Hogan & Hartson L.L.P.

20080241995 - Adhesive sheet for both dicing and die bonding and semiconductor device manufacturing method using the adhesive sheet: An adhesive sheet for dicing and die bonding includes a base material and an adhesive layer releasably laminated on said base material, wherein said adhesive layer has a pressure sensitive adhering property at room temperature and a thermosetting property, the elastic modulus of the adhesive layer before thermosetting is 1.0×103... Agent: The Webb Law Firm, P.C.

20080241997 - Interposer and method for producing the same and electronic device: An interposer includes a substrate made of an inorganic material; a through wiring including conductors embedded in through holes; and an upper wiring and (or) a lower wiring. The through wiring, the upper wiring and the lower wiring are respectively formed on preliminary wiring patterns that are additionally simultaneously or... Agent: Drinker Biddle & Reath (dc)

20080241996 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device includes preparing a first semiconductor substrate having a first integrated circuit formed therein and including a plurality of first through substrate vias, and a second semiconductor substrate having a second integrated circuit formed therein and including a plurality of second through substrate vias,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080241998 - Method for fabricating a low cost integrated circuit (ic) package: A method for fabricating a low cost integrated circuit package (600) includes separating a processed silicon wafer into a plurality of individual die (601) and then positioning the die (603) on a secondary substrate in a face down position for allowing an increased die I/O connection area. The die is... Agent: Motorola, Inc

20080241999 - Semiconductor device and manufacturing method therefor: A semiconductor device is manufactured by sealing a semiconductor chip, which is mounted on a prescribed support such as a lead frame, support bars, and a substrate connected with electrical wiring, in a package. Herein, individual information containing management information representing manufacturing conditions of semiconductor chips and test information representing... Agent: Dickstein Shapiro LLP

20080242000 - Wafer-level-chip-scale package and method of fabrication: A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and... Agent: Volentine & Whitt PLLC

20080242002 - Apparatus and methods for cooling semiconductor integrated circuit package structures: The present invention relates generally to apparatus and methods for cooling semiconductor integrated circuit (IC) chip package structures. More specifically, the present invention relates to apparatus and methods for thermally coupling semiconductor chips to a heat conducting device (e.g., copper thermal hat or lid) using a compliant thermally conductive material... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080242001 - Lid attachment mechanism: Apparatus and methods for assembling semiconductor chips packages are provided. In one aspect, a method of manufacturing is provided that includes placing a first set of semiconductor chip package substrates in a first group of receptacles of a first processing station. Each of the first set of semiconductor chip package... Agent: Timothy M Honeycutt Attorney At Law

20080242003 - Integrated circuit devices with integral heat sinks: A method for forming integral heat sinks on back surfaces of integrated circuit devices at wafer level is described. A first metallic layer is deposited over the back surface of a wafer. A second metallic layer is deposited over the first metallic layer. Optionally, a third metallic layer is deposited... Agent: Beyer Law Group LLP

20080242004 - Inkjet printed wirebonds, encapsulant and shielding: A method of connecting a chip to a package in a semiconductor device includes printing an encapsulant to a predetermined thickness on at least a portion of the chip and package and printing a layer of conductive material on the encapsulant in a predetermined pattern between the chip and package.... Agent: Min, Hsieh & Hack, LLP

20080242005 - Method for manufacturing semiconductor device: In the present application, is disclosed a method of manufacturing a flexible semiconductor device having an excellent reliability and tolerance to the loading of external pressure. The method includes the steps of: forming a separation layer over a substrate having an insulating surface; forming an element layer including a semiconductor... Agent: Eric Robinson

20080242007 - Method for selectively etching portions of a layer of material based upon a density or size of semiconductor features located thereunder: The disclosure provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445) over a substrate (310), and then forming a layer of material (510) over the semiconductor features (405, 410, 415, 420, 425, 430,... Agent: Texas Instruments Incorporated

20080242006 - Methods of forming nand flash memory with fixed charge: A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may... Agent: Vierra Magen/sandisk Corporation

20080242008 - Method of making three dimensional nand memory: A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming... Agent: Foley And Lardner LLP Suite 500

20080242009 - Semiconductor memory devices and methods for fabricating the same: A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080242010 - At least penta-sided-channel type of finfet transistor: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five... Agent: Harness, Dickey & Pierce, P.L.C

20080242011 - Method of fabricating non-volatile memory device: A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on... Agent: Harness, Dickey & Pierce, P.L.C

20080242012 - High quality silicon oxynitride transition layer for high-k/metal gate transistors: A method for fabricating a high quality silicon oxynitride layer for a high-k/metal gate transistor comprises depositing a high-k dielectric layer on a substrate, depositing a barrier layer on the high-k dielectric layer, wherein the barrier layer includes at least one of nitrogen or oxygen, depositing a capping layer on... Agent: Intel Corporation C/o Intellevate, LLC

20080242013 - Semiconductor device and a method of manufacturing the same: A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080242014 - Methods for fabricating semiconductor substrates with silicon regions having differential crystallographic orientations: A method is provided for fabricating a differential semiconductor substrate. A first structure is provided which comprises a first semiconductor substrate including a first semiconductor region, and a first oxide layer overlying a surface of the first semiconductor substrate. The first semiconductor substrate has a first crystallographic orientation. A second... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080242015 - Methods of forming cmos integrated circuit devices having stressed nmos and pmos channel regions therein and circuits formed thereby: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may... Agent: Myers Bigel Sibley & Sajovec

20080242016 - Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods: Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080242017 - Method of manufacturing semiconductor mos transistor devices: A method of fabricating metal-oxide-semiconductor (MOS) transistor devices is disclosed. A semiconductor substrate is provided. A gate dielectric layer is formed. A gate electrode is stacked on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of... Agent: North America Intellectual Property Corporation

20080242019 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate. A gate dielectric layer is formed on the semiconductor substrate. A first conductive layer is formed on the gate dielectric layer, wherein the first conductive layer is an in-situ doped... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080242018 - Method of reducing channeling of ion implants using a sacrificial scattering layer: Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer over at least a portion a surface of the substrate, wherein the sacrificial scattering layer includes an amorphous material. The method further includes ion... Agent: Texas Instruments Incorporated

20080242020 - Method of manufacturing a mos transistor device: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate and a gate structure positioned on the semiconductor substrate are prepared first. A source region and a drain region are included in the semiconductor substrate on two opposite sides of the gate structure. Subsequently, a stressed... Agent: North America Intellectual Property Corporation

20080242021 - Method of fabricating a bottle trench and a bottle trench capacitor: A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent... Agent: Schmeiser, Olsen & Watts

20080242022 - Electronic device including discontinuous storage elements within a dielectric layer and process of forming the electronic device: An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the... Agent: Larson Newman Abel Polansky & White, LLP

20080242023 - Method for preparing a metal-oxide-semiconductor transistor: A method for preparing a Metal-Oxide-Semiconductor (MOS) transistor comprises the steps of forming a gate oxide layer on a substrate, forming a gate and a first dielectric layer on the gate oxide layer, forming a second dielectric layer on the sidewall of the gate, forming a third dielectric layer covering... Agent: Wpat, PC Intellectual Property Attorneys

20080242024 - Method of manufacturing semiconductor device: To provide a semiconductor device using a Fin-FET and having a contact configuration such that the GIDL is reduced while limiting an increase in contact resistance, source and drain regions of the Fin-FET are formed by solid-phase diffusion positively utilizing impurity implantation after forming of contact holes 13 and oozing-out... Agent: Sughrue Mion, PLLC

20080242025 - 3-dimensional flash memory device and method of fabricating the same: In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on... Agent: Marger Johnson & Mccollom, P.C.

20080242026 - Method of manufacturing a semiconductor memory device having a floating gate: A method of manufacturing a semiconductor memory device which includes forming a conductive layer for a floating gate above a semiconductor layer intervening a gate insulating film therebetween, then, forming, over the conductive layer, a first spacer comprising a first silicon oxide material and a second spacer adjacent with the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080242027 - Non-volatile memory integrated circuit: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines,... Agent: Bever Hoffman & Harms, LLP 2099 Gateway Place

20080242029 - Method and structure for making a top-side contact to a substrate: A method for forming a semiconductor structure includes the following steps. A starting semiconductor substrate having a top-side surface and a back-side surface is provided. A recess is formed in the starting semiconductor substrate through the top-side of the starting semiconductor substrate. A semiconductor material is formed in the recess.... Agent: Townsend And Townsend And Crew, LLP

20080242028 - Method of making three dimensional nand memory: A method of making a monolithic, three dimensional NAND string including a first memory cell located over a second memory cell, includes growing a semiconductor active region of second memory cell, and epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the... Agent: Foley And Lardner LLP Suite 500

20080242030 - Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer: A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region... Agent: Ladas & Parry LLP

20080242032 - Carbon-doped epitaxial sige: A method for forming carbon-doped epitaxial SiGe of a PMOS transistor by providing a semiconductor substrate having a PMOS transistor gate stack and recess etched active regions. The method includes forming carbon-doped epitaxial SiGe within the recess etched active regions. A PMOS transistor includes a semiconductor substrate, a PMOS transistor... Agent: Texas Instruments Incorporated

20080242031 - Method for fabricating p-channel field-effect transistor (fet): A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile.... Agent: J C Patents, Inc.

20080242033 - Self-aligned ldmos fabrication method integrated deep-sub-micron vlsi process, using a self-aligned lithography etches and implant process: An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define... Agent: Bever Hoffman & Harms, LLP 2099 Gateway Place

20080242034 - Method of making three dimensional nand memory: A method of making a monolithic, three dimensional NAND string, includes forming a semiconductor active region of a first memory cell over a semiconductor active region of a second memory cell. The semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross... Agent: Foley And Lardner LLP Suite 500

20080242035 - Manufacturing method of semiconductor device: The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type... Agent: Miles & Stockbridge PC

20080242036 - Semiconductor device and manufacturing method thereof: A method for manufacturing a semiconductor device, includes: a) forming a first semiconductor layer on a semiconductor substrate; b) forming a second semiconductor layer on the first semiconductor layer; c) sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer so as to... Agent: Harness, Dickey & Pierce, P.L.C

20080242037 - Semiconductor device having self-aligned epitaxial source and drain extensions: A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch... Agent: Intel Corporation C/o Intellevate, LLC

20080242038 - Methods of forming a multilayer capping film to minimize differential heating in anneal processes: Methods and associated structures of forming a microelectronic device are described. Those methods may include implanting the source/drain region, forming a multilayer cap on the source/drain region, annealing the source/drain region, and removing the multilayer cap.... Agent: Intel Corporation C/o Intellevate, LLC

20080242039 - Method of enhancing dopant activation without suffering additional dopant diffusion: A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080242040 - Method of forming a semiconductor structure: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature... Agent: Williams, Morgan & Amerson

20080242041 - Selective deposition of germanium spacers on nitride: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080242042 - Method for fabricating a capacitor in a semiconductor device: A method for fabricating a capacitor in a semiconductor device includes forming a sacrificial layer and a support layer on a substrate. A plurality of openings are formed by etching the support layer and the sacrificial layer. An electrode is formed in inner walls of the openings including sidewalls of... Agent: Townsend And Townsend And Crew, LLP

20080242043 - Method for checking alignment accuracy using overlay mark: A method for checking the alignment accuracy using an overlay mark is provided. The overlay mark includes an inner mark and an outer mark formed on a wafer. The outer mark is formed in a lower layer on the wafer when the lower layer is patterned. The inner mark is... Agent: J C Patents, Inc.

20080242044 - Method for fabricating nonvolatile memory device: A method for fabricating a nonvolatile memory device includes forming a gate insulation layer, a first gate conductive layer, a first sacrificial layer, and a second sacrificial layer over a substrate, etching the first and second sacrificial layers, the first gate conductive layer, the gate insulation layer, and the substrate... Agent: Marshall, Gerstein & Borun LLP

20080242045 - Method for fabricating trench dielectric layer in semiconductor device: A method for fabricating a trench dielectric layer in a semiconductor device is provided. A trench is formed in a semiconductor substrate and a liner nitride layer is then formed on an inner wall of the trench. A liner oxide layer formed on the liner nitride layer is nitrified in... Agent: Townsend And Townsend And Crew, LLP

20080242046 - Method on forming an isolation film or a semiconductor device: A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a... Agent: Marshall, Gerstein & Borun LLP

20080242047 - Method of forming isolation structure of semiconductor memory device: The present invention relates to a method of forming isolation layers of a semiconductor memory device. According to a method of forming isolation layers of a semiconductor memory device in accordance with an aspect of the present invention, a tunnel dielectric layer, a conductive layer for a floating gate, a... Agent: Townsend And Townsend And Crew, LLP

20080242048 - Method for manufacturing soi substrate: After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the... Agent: Hogan & Hartson L.L.P.

20080242049 - Method for generating a micromechanical structure: In a method for manufacturing a micromechanical structure, first a two-dimensional structure is formed in a substrate. The two-dimensional structure is deflected from the substrate plane by action of force and fixed in the deflected state.... Agent: Schoppe, Zimmerman , Stockeller & Zinkler C/o Keating & Bennett , LLP

20080242050 - Method for manufacturing semiconductor device: It is an object of the present invention to manufacture a semiconductor element and an integrated circuit that have high performance over a large-sized substrate with high throughput and high productivity. When single crystal semiconductor layers are transferred from a single crystal semiconductor substrate (a bond wafer), the single crystal... Agent: Eric Robinson

20080242051 - Method for manufacturing semiconductor device: When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor... Agent: Eric Robinson

20080242052 - Method of forming ultra thin chips of power devices: With a step-profiled chuck to support wafer back-side, the pre-fabricated devices are separated from each other and from the wafer periphery in one dicing operation with dicing depth slightly thicker than the wafer central portion. The separated thin semiconductor devices are then picked up and collected.... Agent: Chein-hwa S. Tsao

20080242054 - Dicing and drilling of wafers: Methods and apparatus to dicing and/or drilling of wafers are described. In one embodiment, an electromagnetic radiation beam (e.g., a relatively high intensity, ultra-short laser beam) may be used to dice and/or drill a wafer. Other embodiments are also described.... Agent: Caven & Aghevli C/o Intellevate, LLC

20080242053 - Integrated circuit system with a debris trapping system: An integrated circuit system including: providing an integrated circuit wafer having an integrated circuit side and a backside; mounting a protective adhesive on the integrated circuit side of the integrated circuit wafer; removing material from the backside of the integrated circuit wafer; and dicing the integrated circuit wafer through the... Agent: Law Offices Of Mikio Ishimaru

20080242056 - System and method for cutting using a variable astigmatic focal beam spot: A variable astigmatic focal beam spot is formed using lasers with an anamorphic beam delivery system. The variable astigmatic focal beam spot can be used for cutting applications, for example, to scribe semiconductor wafers such as light emitting diode (LED) wafers. The exemplary anamorphic beam delivery system comprises a series... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20080242055 - Wafer laser processing method and laser processing equipment: A wafer laser processing method for forming a groove in a wafer having a plurality of areas which are sectioned by streets formed in a lattice pattern on the front surface of a substrate, a device being formed in each of the plurality of areas, and an insulating film being... Agent: Greenblum & Bernstein, P.L.C

20080242058 - Adhesive composition, adhesive sheet and production process for semiconductor device: According to the present invention, provided are an adhesive composition which can achieve a high package reliability in a package in which a semiconductor chip being reduced in a thickness is mounted even when exposed to severe reflow conditions, an adhesive sheet having an adhesive layer comprising the above adhesive... Agent: The Webb Law Firm, P.C.

20080242057 - Semiconductor device with a thinned semiconductor chip and method for producing the thinned semiconductor chip: A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected... Agent: Dicke, Billig & Czaja

20080242059 - Methods of forming nickel silicide layers with low carbon content: A method for forming a nickel silicide layer on a MOS device with a low carbon content comprises providing a substrate within an ALD reactor and performing an ALD process cycle to form a nickel layer on the substrate, wherein the ALD process cycle comprises pulsing a nickel precursor into... Agent: Intel Corporation C/o Intellevate, LLC

20080242060 - Method for forming algan crystal layer: A method for preparing an AlGaN crystal layer with good surface flatness is provided. A surface layer of AlN is epitaxially formed on a c-plane sapphire single crystal base material by MOCVD method, and the resulting laminated body is then heated at a temperature of 1300° C. or higher so... Agent: Burr & Brown

20080242062 - Fabrication of diverse structures on a common substrate through the use of non-selective area growth techniques: Diverse semiconductor structures are fabricated on a single substrate or wafer by using a non-selective area growth technique involving deposition of material over the entire substrate. The fabricated structures are obtained by selective removal of portions of the deposited material layers. Single level and multi-level structures are possible.... Agent: Brosemer, Kolefas & Associates, LLC - (lucent)

20080242061 - Precursor gas mixture for depositing an epitaxial carbon-doped silicon film: A precursor gas mixture for depositing an epitaxial carbon-doped silicon film is described. The precursor gas mixture is comprised of a volume of a silicon precursor gas, a volume of acetylene gas and a volume of a carrier gas. A method of forming a semiconductor structure having an epitaxial carbon-doped... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080242063 - Solder composition doped with a barrier component and method of making same: A solder composition and a method of making the composition. The solder composition comprises a Sn-containing base material and a barrier component having a reactivity with Sn which is higher than a reactivity of Ni or Cu with Sn, the barrier component being present in the composition in an amount... Agent: Intel Corporation C/o Intellevate, LLC

20080242064 - Manufacturing method of semiconductor device: To provide a manufacturing method of a semiconductor device capable of performing a selective growth at a low temperature. A manufacturing method of a semiconductor device for placing in a processing chamber a substrate having at least a silicon surface and an insulating film surface on a surface; and allowing... Agent: Oliff & Berridge, PLC

20080242065 - Control of ion angular distribution function at wafer surface: A manufacturing method and apparatus for IC fabrication controls the ion angular distribution at the surface of a wafer with electrodes in a wafer support that produce electric fields parallel to the wafer surface without disturbing plasma parameters beyond the wafer surface. The ion angular distribution function (IADF) at the... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080242066 - Method of manufacturing semiconductor: A method of producing ultra shallow junctions (104) for PMOS transistors, which eliminates the need for pre-amorphization implants, is disclosed. The method utilizes dopant species, such as cluster ions, e.g., octadecaborane, B18H22. In accordance with the present invention, the pre-amorphizing step may be eliminated, greatly reducing cost per processed wafer.... Agent: Patent Administrator Katten Muchin Rosenman LLP

20080242068 - Method for manufacturing a semiconductor device: A semiconductor device fabrication method by which CMOS transistors with low-resistance metal gate electrodes each having a proper work function can be fabricated. A HfN layer in which nitrogen concentration in an nMOS transistor formation region differs from nitrogen concentration in a pMOS transistor formation region is formed. A MoN... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080242067 - Semiconductor substrate and method of manufacture thereof: A semiconductor substrate is disclosed, which comprises a lightly doped substrate that contains impurities at a low concentration, a heavily doped diffusion layer which is formed over a top of the lightly doped substrate and is higher in impurity concentration than the lightly doped substrate, and an epitaxial layer which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080242069 - Hybrid soi/bulk semiconductor transistors: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080242070 - Integration schemes for fabricating polysilicon gate mosfet and high-k dielectric metal gate mosfet: Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A... Agent: Scully, Scott, Murphy & Presser, P.C.

20080242071 - Method for passivating gate dielectric films: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric... Agent: Haynes And Boone, LLP

20080242072 - Plasma dry etch process for metal-containing gates: A method of manufacturing a semiconductor device. The method comprises forming a gate stack layer. The gate stack has an insulating layer on a substrate, a metal-containing layer on the insulating layer, a metal nitride barrier layer on the metal-containing layer, and a silicon-containing layer on the metal nitride barrier... Agent: Texas Instruments Incorporated

20080242073 - Method for fabricating a nonvolatile memory device: A method for fabricating a nonvolatile memory device includes forming a gate insulation layer and a gate conductive layer for forming a floating gate over a substrate. A portion of the gate conductive layer, the gate insulation layer, and the substrate is etched to form a trench. An isolation structure... Agent: Townsend And Townsend And Crew, LLP

20080242075 - Method for forming non-volatile memory devices: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are... Agent: Mills & Onello LLP

20080242074 - Method of forming gate pattern of flash memory device: A method of forming a gate pattern of a flash memory device may include forming a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, a metal electrode layer, and a hard mask film over a semiconductor substrate. The... Agent: Marshall, Gerstein & Borun LLP

20080242076 - Method of making semiconductor die stack having heightened contact for wire bond: A method of making a semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on... Agent: Vierra Magen/sandisk Corporation

20080242077 - Strained metal silicon nitride films and method of forming: A method for forming a strained metal nitride film and a semiconductor device containing the strained metal nitride film. The method includes exposing a substrate to a gas containing a metal precursor, exposing the substrate to a gas containing a silicon precursor, exposing the substrate to a gas containing a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080242078 - Process of filling deep vias for 3-d integration of substrates: A method for filling defect-free conductive material in deep vias or cavities in semiconductor wafers in 3-D integration structures is provided. The process may be performed in at least two steps for depositing the conductive material, including a first deposition step that partially fills the cavity with the conductive material... Agent: Knobbe, Martens, Olson & Bear LLP

20080242079 - In-situ formation of conductive filling material in through-silicon via: The formation of electronic assemblies including a die having through vias is described. In one embodiment, a method includes providing Si die including a first surface and a second surface opposite the first surface, and forming a via extending through the Si die from the first surface to the second... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20080242080 - Method for implementing diffusion barrier in 3d memory: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower... Agent: Eschweiler & Associates LLC

20080242081 - Polishing method, polishing apparatus, and method for manufacturing semiconductor device: A polishing method includes a first polishing step of halfway polishing a film to be polished formed on a substrate, and a second polishing step of further polishing the polished film, wherein a first film thickness profile showing an in-plane distribution of a film thickness of the polished film after... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080242082 - Method for fabricating back end of the line structures with liner and seed materials: A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has... Agent: Hoffman Warnick LLC

20080242083 - Method for manufacturing memory element: A first conductive layer is formed, a composition layer over the first conductive layer is formed by discharging a composition in which nanoparticles comprising a conductive material covered with an organic material are dispersed in a solvent, and the composition layer is dried. Subsequently, pretreatment is performed in which the... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080242084 - Method for planarizing an insulation layer in a semiconductor device capable of omitting a mask process and an etching process: In a method for planarizing an insulation layer in a semiconductor device, an insulation layer is formed over a semiconductor substrate having a cell region and a peripheral region. The cell region is higher than the peripheral region due to a capacitor formed in the cell region. A metal layer... Agent: Ladas & Parry LLP

20080242086 - Plasma processing method and plasma processing apparatus: A plasma processing method, for performing a plasma process on a target substrate by generating a plasma between an upper electrode and a lower electrode facing each other by means of applying a radio frequency power therebetween, includes applying a DC voltage of a positive or negative polarity to an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080242085 - Showerhead electrodes and showerhead electrode assemblies having low-particle performance for semiconductor material processing apparatuses: Showerhead electrodes for a semiconductor material processing apparatus are disclosed. An embodiment of the showerhead electrodes includes top and bottom electrodes bonded to each other. The top electrode includes one or more plenums. The bottom electrode includes a plasma-exposed bottom surface and a plurality of gas holes in fluid communication... Agent: Buchanan, Ingersoll & Rooney PC

20080242087 - Magnetron sputtering apparatus and method for manufacturing semiconductor device: A magnetron sputtering apparatus includes: a target provided in a sputtering chamber; a susceptor opposed to the target; a high-frequency power supply connected to the susceptor; a plate provided outside the sputtering chamber and coaxial with a central axis of the target; a rotary motion mechanism configured to rotate the... Agent: Pearne & Gordon LLP

20080242088 - Method of forming low resistivity copper film structures: A method for forming low (electrical) resistivity Cu film structures by depositing a metal nitride barrier film on a substrate, depositing a Ru film on the metal nitride barrier film, depositing a Cu seed layer on the Ru film, and depositing bulk Cu metal on the Cu seed layer. The... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080242090 - Metal-polishing liquid and polishing method: m

20080242089 - Method for distributed processing at copper cmp: A method of manufacturing a semiconductor device. A first thickness of a copper layer located over a semiconductor substrate is removed by chemical-mechanical polishing (CMP) on a first platen using a first polishing slurry. The copper layer is located over a barrier layer. A remaining thickness of the copper layer... Agent: Texas Instruments Incorporated

20080242091 - Metal-polishing liquid and polishing method: A metal-polishing liquid used for chemical and mechanical polishing of copper wiring in a semiconductor device, the metal-polishing liquid comprising: (a) a tetrazole compound having a substituent in the 5-position; (b) a tetrazole compound not substituted in the 5-position; (c) abrasive grains; and (d) an oxidizing agent.... Agent: Sughrue Mion, PLLC

20080242093 - Method for manufacturing semiconductor integrated circuit device: Cracks are generated in a resist film part used to form an opening part in a photoreceptor part, whereby etching is performed as far as the inter-layer insulating film in unintended portions. In order to prevent this, the resist pattern used as an etching mask is formed in a shape... Agent: Oliff & Berridge, PLC

20080242092 - Method of manufacturing spacer: A method of manufacturing an L-shaped spacer is described. First, a substrate is provided and a protruding structure is formed thereon. Next, a dielectric material is formed on the substrate and covers the stacked structure. Then, the dielectric material on the top of the protruding structure and on portions of... Agent: J C Patents, Inc.

20080242094 - Method of making a semiconductor structure utilizing spacer removal and semiconductor structure: A method for making a semiconductor structure (10) includes providing a wafer with a structure (16) having a sidewall, forming a sidewall spacer (22) adjacent to the sidewall, and forming a layer of material (28) over the wafer including over the sidewall spacer and over the structure having the sidewall.... Agent: Freescale Semiconductor, Inc. Law Department

20080242095 - Method for forming trench in semiconductor device: A method for fabricating a trench in a semiconductor device includes forming a mask pattern over a substrate, and etching the substrate to form a trench with a vertical profile, the etching performed at an etching rate of approximately 40 A/sec or less using an etching gas including a gas... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080242096 - Method for preparing bottle-shaped deep trenches: A method for preparing a bottle-shaped deep trench first forms a first mask with at least one opening on a substrate including a first epitaxy layer, an insulation layer on the first epitaxy layer and a second epitaxy layer on the insulation layer. A first etching process is performed to... Agent: Wpat, PC Intellectual Property Attorneys

20080242098 - Method for forming pattern in semiconductor device: A method for forming a pattern in a semiconductor device includes forming an etch target layer over a substrate, forming a hard mask pattern over the etch target layer, and etching the etch target layer using the hard mask pattern as an etch mask and a gas mixture including a... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080242097 - Selective deposition method: The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080242099 - Method for forming contact hole using dry and wet etching processes in semiconductor device: A method for forming a contact hole in a semiconductor device includes forming an insulation layer over a substrate, forming a hard mask pattern over the insulation layer, forming a first contact hole by partially etching the insulation layer, forming a spacer on sidewalls of the first contact hole, forming... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080242100 - Semiconductor device and fabrications thereof: A method for forming a semiconductor device is disclosed. A substrate comprising a structural layer thereon is provided. A hard mask layer is formed on the structural layer. A photoresist layer is formed on the hard mask layer. The photoresist layer is patterned to from a plurality of main photoresist... Agent: Quintero Law Office, PC

20080242102 - Chemistry for removal of photo resist, organic sacrifical fill material and etch polymer: Methods and associated structures of forming a microelectronic device are described. Those methods may include utilizing a cleaning mixture comprising a solvent such as ethylene glycol monopropyl ether, an inorganic base, an organic base, a copper corrosion inhibitor and a surfactant to clean at least one of a polymer residue,... Agent: Intel Corporation C/o Intellevate, LLC

20080242103 - Method of manufacturing semiconductor device and semiconductor manufacturing apparatus: A method of manufacturing a semiconductor device having a process for cleaning a semiconductor substrate after the semiconductor substrate is etched for patterning includes a first process of preparing the semiconductor substrate having a first temperature, a second process of setting the semiconductor substrate at a second temperature, a third... Agent: Junichi Mimura Oki America Inc.

20080242101 - Process control method in spin etching and spin etching apparatus: The present invention provides a process control method in spin etching capable of realizing uniformity in etching amount in etching treatment for even wafers each having various conditions, and achieving uniformity of thickness values among etched wafers. In the present invention, weight of a wafer before etching is measured in... Agent: Arent Fox LLP

20080242104 - Semiconductor device, method of manufacturing thereof and mask for dividing exposure: A method of manufacturing a semiconductor device has a first exposure to the photoresist by using a first mask having a first portion of a monitor pattern, a second exposure to the photoresist by using a second mask having a second portion of the monitor pattern so that a first... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080242105 - Semiconductor manufacturing apparatus, semiconductor wafer manufacturing method using this apparatus, and recording medium having program of this method recorded therein: Foreign particles are prevented from adhering to a semiconductor wafer in a semiconductor manufacturing apparatus including (a) a hot plate which heats a semiconductor wafer to increase its temperature and which has a suction/discharge hole through which a negative pressure is supplied to suck and hold said semiconductor wafer at... Agent: Rabin & Berdo, PC

20080242106 - Chemical mechanical polishing method and apparatus for reducing material re-deposition due to ph transitions: A CMP apparatus and process reduces material re-deposition due to pH transitions. The CMP process reduces the re-deposition of material by performing a water rinse between CMP stages. A CMP apparatus, which performs CMP process, may reduce re-deposition by including a water rinse between two CMP stages that utilize different... Agent: Texas Instruments Incorporated

20080242107 - Method for manufacturing a semiconductor device by using an ald technique: A method for manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon substrate, and forming a silicon nitride film on the silicon oxide film. The step of forming the silicon nitride film includes the steps of growing a first silicon layer having a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080242108 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080242109 - Method for growing a thin oxynitride film on a substrate: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber. The wet process gas and the nitriding gas form... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080242111 - Atomic layer deposition of strontium oxide via n-propyltetramethyl cyclopentadiendyl precursor: A method of depositing oxide materials on a substrate is provided. A deposition chamber holds the substrate, where the substrate is at a specified temperature, and the chamber has a chamber pressure and wall temperature. A precursor molecule containing a cation material atom is provided to the chamber, where the... Agent: Lumen Patent Firm, Inc.

20080242110 - Capping layer formation onto a dual damescene interconnect: A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080242113 - Film forming method of high-k dielectric film: A method for forming a high-K dielectric film on a silicon substrate includes the steps of processing a surface of the silicon substrate with a diluted hydrofluoric acid, conducting nucleation process of HfN, after the step of processing with the diluted hydrofluoric acid, by supplying a metal organic source containing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080242112 - Phase-separated dielectric structure fabrication process: A process for fabricating an electronic device including: depositing a layer comprising a semiconductor; liquid depositing a dielectric composition comprising a lower-k dielectric material, a higher-k dielectric material, and a liquid, wherein the lower-k dielectric material and the higher-k dielectric material are not phase separated prior to the liquid depositing;... Agent: Patent Documentation Center

20080242114 - Thermal anneal method for a high-k dielectric: A method of manufacturing a semiconductor device is provided. In one embodiment, the method provides for the formation, over a substrate, of a dielectric layer having a high dielectric constant. This dielectric layer may be exposed to a nitrogen plasma after which it may be annealed in a hydrogen containing... Agent: Texas Instruments Incorporated

20080242115 - Semiconductor device and method for manufacturing semiconductor device: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080242116 - Method for forming strained silicon nitride films and a device containing such films: A method for forming a strained SiN film and a semiconductor device containing the strained SiN film. The method includes exposing the substrate to a gas including a silicon precursor, exposing the substrate to a gas containing a nitrogen precursor activated by a plasma source at a first level of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080242117 - Apparatus to reduce wafer edge temperature and breakage of wafers: In some embodiments radiation incident on a wafer is provided to perform an annealing process, and the wafer is cooled at an edge portion to reduce temperature and stress on the wafer. Other embodiments are described and claimed.... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20080242118 - Methods for forming dense dielectric layer over porous dielectrics: Methods for forming a dense dielectric layer over the surface of an opening in a porous inter-layer dielectric having an ultra-low dielectric constant are disclosed. The disclosure provides methods for exposing the sidewall surface and the bottom surface of the opening to a plurality of substantially parallel ultra-violet (UV) radiation... Agent: Hoffman Warnick LLC