Semiconductor device manufacturing: process inventions 09/08

20080233661 - Methods and systems for lithography alignment: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.... Agent: Haynes And Boone, LLP

20080233662 - Advanced process control for semiconductor processing: An advanced process control (APC) method for semiconductor fabrication is provided. A first substrate and a second substrate are provided. The first substrate and the second substrate include a dielectric layer. A first etch process parameter for the first substrate is determined. A trench is etched in the dielectric layer... Agent: Haynes And Boone, LLP

20080233663 - Singulated bare die testing: There is testing of individual dice prior to their inclusion in a multi-chip package. A wafer is sawn into individual dice and the dice are placed onto a die tray. If the tray is not full, then dice can be added that originate from other wafers. Contacts perform diagnostic tests... Agent: Amin, Turocy & Calvin, LLP

20080233664 - Semiconductor integrated circuit production method and device: A semiconductor integrated circuit production method prepares an SOI layer thickness database that correlates measurement data of each SOI layer thickness with each SOI substrate identification data. The production method extracts the measurement data for each SOI substrate from the SOI layer thickness database, and carries out layer thickness adjustment... Agent: Rabin & Berdo, PC

20080233665 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device including: forming a semiconductor layer on a substrate with transistor and capacitor formation regions; forming first and second photo resist patterns at the transistor and capacitor formation regions, respectively, the second photo resist pattern having a thickness less than that of the first... Agent: Christie, Parker & Hale, LLP

20080233666 - Light emitting diode package with metal reflective layer and method of manufacturing the same: The invention relates to an LED package having a metal reflective layer for focusing and emitting light through a side of the package, and a manufacturing method of the same. The LED package includes a substrate with an electrode formed thereon, a light emitting diode chip disposed on the substrate,... Agent: Mcdermott Will & Emery LLP

20080233667 - Microdisplay packaging system: Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least... Agent: Buckley, Maschoff & Talwalkar LLC

20080233668 - Method for manufacturing semiconductor optical device: A method for manufacturing a semiconductor optical device includes: forming a laminated semiconductor structure of GaN-based materials on a semiconductor wafer, the laminated semiconductor structure forming a laser diode of GaN-based materials, including an active layer having a quantum well structure; cleaving the semiconductor wafer including the laminated semiconductor structure... Agent: Leydig Voit & Mayer, Ltd

20080233669 - Method for manufacturing light-emitting device: A full-color light-emitting device is achieved with plural kinds of light-emitting elements in each of which a stacked layer of a first material layer formed selectively with a droplet discharge apparatus and a second material layer formed by vapor-deposition method using the conductive-surface plate on which a layer containing an... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080233670 - Method for fabricating a p-i-n light emitting diode using cu-doped p-type zno: A method of fabricating a p-i-n type light emitting diode using p-type ZnO, and particularly, a technique for fabricating a p-type ZnO thin film doped with copper, a light emitting diode manufactured using the same, and its application to electrical and magnetic devices. The method of fabricating a p-i-n type... Agent: The Rafferty Patent Law Firm

20080233671 - Method of fabricating gan led: A light emitting diode (LED) is made. The LED had a LiAlO2 substrate and a GaN layer. Between them, there is a zinc oxide (ZnO) layer. Because GaN and ZnO have a similar. Wurtzite structure, GaN can easily grow on ZnO. By using the ZnO layer, the GaN layer is... Agent: Troxell Law Office PLLC Suite 1404

20080233672 - Method of integrating mems structures and cmos structures using oxide fusion bonding: A method to fabricate a device including a micro-electro-mechanical system structure and a monolithic integrated circuit comprises using a first wafer as a first substrate, fabricating the micro-electro-mechanical system structure on the first substrate, and forming a first oxide layer over the micro-electro-mechanical system structure. The method further comprises using... Agent: Fliesler Meyer LLP

20080233673 - Method for fabricating mems-resonator: The present invention is an etching mask used for fabricating of the MEMS resonator including an oscillator which both edges are fixed to a base substance and vibrates to a vibrating direction, and an electrode which is fixed to a base substance by vibration is impossible in parallel for the... Agent: Volentine & Whitt PLLC

20080233674 - Photo mask and method for fabricating image sensor using the same: A method for fabricating an image sensor includes forming an insulation layer over a substrate in a logic circuit region and a pixel region, forming a photoresist over the insulation layer, patterning the photoresist to form a photoresist pattern where the insulation layer in the pixel region is exposed and... Agent: Morgan Lewis & Bockius LLP

20080233675 - Method of fabricating nano-wire array: Provided is a method of fabricating a nano-wire array, including the steps of: depositing a nano-wire solution, which contains nano-wires, on a substrate; forming a first etch region in a stripe shape on the substrate and then patterning the nano-wires; forming drain and source electrode lines parallel to each other... Agent: Rabin & Berdo, PC

20080233676 - Integrated circuit device with embedded passive component by flip-chip connection and method for manfacturing the same: An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the... Agent: Troxell Law Office PLLC

20080233677 - Semiconductor device and method of manufacturing the same: Two semiconductor substrates are first bonded together by means of a metal bump, while respective one-side surfaces on which device patterns are formed are faced each other, and a resin is then filled into a gap between the respective one-side surfaces and thereafter each of the semiconductor substrates is polished... Agent: Kratz, Quintos & Hanson, LLP

20080233678 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device having a substrate on which conductor wiring is disposed, electrodes provided to the conductor wiring, a semiconductor element connected to the electrodes, and a sealing member that covers the semiconductor element, comprises; mounting a plurality of semiconductor elements on the substrate in the... Agent: GlobalIPCounselors, LLP

20080233679 - Semiconductor package with plated connection: A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of... Agent: Van Pelt, Yi & James LLP

20080233681 - Design of beol patterns to reduce the stresses on structures below chip bondpads: A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080233680 - Semiconductor die collet and method: Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the... Agent: Yingsheng Sam Tung Texas Instruments Incorporated

20080233682 - Methods of forming a cored metallic thermal interface material and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a core portion of a TIM, wherein the core portion comprises a high thermal conductivity and does not comprise indium, and forming an outer portion of the TIM on the core portion.... Agent: Intel Corporation C/o Intellevate, LLC

20080233684 - Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, at least two leads, and at least two bond wires. Each of the leads may have a reduced-thickness inner length adjacent terminals... Agent: Perkins Coie LLP Patent-sea

20080233683 - Pre-plated leadframe having enhanced encapsulation adhesion: A process for producing a pre-plated leadframe that has enhanced adhesion by molding compound is provided, wherein a base leadframe material is first plated with multiple layers of metallic material. Thereafter, the plated base leadframe material is covered with a mask, so as to expose selected surfaces thereof at unmasked... Agent: Ostrolenk Faber Gerb & Soffen

20080233685 - Method of manufacture of an apparatus for increasing stability of mos memory cells: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number... Agent: Glenn Patent Group

20080233686 - Esd protection for high voltage applications: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and... Agent: Haynes And Boone, LLP

20080233687 - Ultra shallow junction formation by epitaxial interface limited diffusion: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080233688 - Method of fabricating a bipolar transistor: A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080233689 - Method for manufacturing semiconductor device: The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide... Agent: Nixon Peabody, LLP

20080233692 - Method and system for forming a controllable gate oxide: Method and system for forming gate structure with controllable oxide. The method includes a step for providing a semiconductor substrate and defining a source region and a drain region within the semiconductor substrate. Furthermore, the method includes a step for defining a gate region positioned between the source region and... Agent: Townsend And Townsend And Crew, LLP

20080233691 - Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers: A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer... Agent: Schmeiser, Olsen & Watts

20080233690 - Method of selectively forming a silicon nitride layer: A method for selectively forming a dielectric layer. An embodiment comprises forming a dielectric layer, such as an oxide layer, on a semiconductor substrate, depositing a silicon layer on the dielectric layer, and treating the silicon layer with nitrogen, thereby converting the silicon layer into a silicon nitride layer. This... Agent: Slater & Matsil, L.L.P.

20080233693 - Complementary metal-oxide semiconductor (cmos) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same: A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer.... Agent: Myers Bigel Sibley & Sajovec

20080233694 - Transistor device and method of manufacture thereof: A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of... Agent: Slater & Matsil LLP

20080233695 - Integration method of inversion oxide (toxinv) thickness reduction in cmos flow without added pattern: A method of manufacturing a CMOS semiconductor comprising, forming shallow trench isolation regions in a workpiece, depositing a gate oxide layer on top of the workpiece, depositing a polysilicon layer on top of the gate oxide, performing VTN patterning, performing first series of adjusted implantations, performing post implantation cleaning, performing... Agent: Texas Instruments Incorporated

20080233696 - Semiconductor device and method for fabricating the same: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080233699 - Bulk finfet device: A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode... Agent: Schmeiser, Olsen & Watts

20080233697 - Multiple-gate mosfet device and associated manufacturing methods: One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The... Agent: Texas Instruments Incorporated

20080233698 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the semiconductor substrate and an insulator provided in the trench, a part... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080233700 - Methods of forming integrated circuitry: The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having... Agent: Wells St. John P.s.

20080233701 - Methods of forming integrated circuit devices including a depletion barrier layer at source/drain regions: Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite sides of the gate pattern and extending along a portion... Agent: Myers Bigel Sibley & Sajovec

20080233702 - Method of forming a recess in a semiconductor structure: One embodiment of the present invention relates to a method of processing a semiconductor device. During the method an amorphization implant is performed to amorphize a selected region of a semiconductor structure. The amorphized selected region is then removed by performing a recess etch that is selective thereto. Other methods... Agent: Texas Instruments Incorporated

20080233703 - Polysilicon conductivity improvement in a salicide process technology: An electronic device and method for forming same. The electronic device includes a source and drain region. Each region has an uppermost portion comprised of a first silicide where the first silicide is overlaid with a first dielectric layer. The electronic device further includes a gate region having an uppermost... Agent: Schwegman, Lundberg & Woessner / Atmel

20080233704 - Integrated resistor capacitor structure: A resistor capacitor structure and a method of fabrication. A resistor capacitor structure provides a capacitance between at least two nodes within a microelectronic circuit. A bottom plate of the resistor capacitor structure comprises a resistance layer, which in turn provides a resistance path between an additional node within the... Agent: Honeywell International Inc.

20080233705 - Method for selectively forming electric conductor and method for manufacturing semiconductor device: A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20080233706 - Manufacturing method of dynamic random access memory: A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the... Agent: Jianq Chyun Intellectual Property Office

20080233707 - Semiconductor device comprising capacitor and method of fabricating the same: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in... Agent: Mcdermott Will & Emery LLP

20080233708 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a semiconductor substrate; forming a first groove penetrating the first semiconductor layer and the second semiconductor layer by partially etching the first semiconductor layer and the second semiconductor layer; forming... Agent: Harness, Dickey & Pierce, P.L.C

20080233709 - Method for removing material from a semiconductor: A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time... Agent: Infineon Technologies North America Corp.

20080233710 - Methods for forming single dies with multi-layer interconnect structures and structures formed therefrom: A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not... Agent: Duane Morris LLPIPDepartment (tsmc)

20080233711 - Manufacturing method for devices: A manufacturing method for devices including a wafer supporting step of mounting an adhesive film to the lower surface of a wafer and attaching the wafer through the adhesive film to the upper surface of a dicing tape mounted on an annular frame, a laser processing step of applying a... Agent: Greer, Burns & Crain

20080233714 - Method for fabricating semiconductor device: An object of the present invention is to provide a method for fabricating a semiconductor device to fabricate a semiconductor device. To achieve such an object, the present invention relates to a method for fabricating a semiconductor device composed of a hetero-junction substrate formed of a semiconductor substrate, and a... Agent: Scully Scott Murphy & Presser, PC

20080233712 - Method of manufacturing device: A method of manufacturing a device includes the steps of forming dividing grooves with a predetermined depth along planned dividing lines of a wafer, then grinding the backside surface of the wafer to expose the dividing grooves on the back side and to divide the wafer into individual devices, mounting... Agent: Greer, Burns & Crain

20080233713 - Method of processing silicon wafer and method of manufacturing liquid ejecting head: A break pattern is formed on a silicon wafer using an anisotropic etching process. The break pattern includes a plurality of through holes, each of having a first plane perpendicular to a plane defined by the silicon wafer, a second plane opposite to the first plane, a third plane that... Agent: Workman Nydegger

20080233715 - Method and apparatus for the laser scribing of ultra lightweight semiconductor devices: A system for the laser scribing of semiconductor devices includes a laser light source operable to selectably deliver laser illumination at a first wavelength and at a second wavelength which is shorter than the first wavelength. The system further includes a support for a semiconductor device and an optical system... Agent: Gifford, Krass, Sprinkle,anderson & Citkowski, P.c

20080233716 - Method for fabricating semiconductor device: The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon... Agent: Rabin & Berdo, PC

20080233717 - Soi wafer and manufacturing method thereof: This wafer is an SOI wafer used for a process of manufacturing a semiconductor device, in which laser annealing is conducted for no more than 0.1 seconds at a maximum temperature of 1200° C. or more, which includes an active layer, a support layer of a monocrystaline silicon, and an... Agent: Greenblum & Bernstein, P.L.C

20080233718 - Method of semiconductor thin film crystallization and semiconductor device fabrication: A method of fabricating a semiconductor device includes providing a substrate, forming an amorphous silicon layer over the substrate, forming a patterned heat retaining layer over the amorphous silicon layer, doping the amorphous silicon layer to form a pair of doped regions in the amorphous silicon layer by using the... Agent: Akin Gump LLP - Silicon Valley

20080233719 - Method for manufacturing crystalline semiconductor film and method for manufacturing thin film transistor: The present invention relates to a method for manufacturing a polycrystalline semiconductor film that can be used for a semiconductor device. In the method, an amorphous semiconductor film is irradiated with a femtosecond laser to be crystallized. By laser irradiation using a femtosecond laser, when an amorphous semiconductor film over... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080233720 - Method of making a solar grade silicon wafer: A method of making a solar grade silicon wafer is disclosed. In at least some embodiments of this invention, the method includes the follow steps: providing a slurry including a liquid that essentially prevents the oxidation of silicon powder and a silicon powder that is essentially free of oxides; providing... Agent: Pitts And Brittian P C

20080233721 - Method for forming algan crystal layer: There is provided a method for preparing an AlGaN crystal layer having an excellent surface flatness. A buffer layer effective in stress relaxation is formed on a template substrate having a surface layer that is flat at a substantially atomic level and to which in-plane compressive stress is applied, and... Agent: Burr & Brown

20080233722 - Method of forming selective area compound semiconductor epitaxial layer: A method of forming a selective area semiconductor compound epitaxy layer is provided. The method includes the step of using two silicon-containing precursors as gas source for implementing a process of manufacturing the selective area semiconductor compound epitaxy layer, so as to form a semiconductor compound epitaxy layer on an... Agent: Jianq Chyun Intellectual Property Office

20080233723 - Plasma doping method and apparatus: There are provided a plasma doping method and an apparatus which have excellent reproducibility of the concentration of impurities implanted into the surfaces of samples. In a vacuum container, in a state where gas is ejected toward a substrate placed on a sample electrode through gas ejection holes provided in... Agent: Mcdermott Will & Emery LLP

20080233724 - Recycling of electrochemical-mechanical planarization (ecmp) slurries/electrolytes: A method, process and system for the recycling of electrochemical-mechanical planarization slurries/electrolytes as they are used in the back end of line of the semiconductor wafer manufacturing process is disclosed. The method, process and system includes with the removal of metal ions from slurries using ion exchange media and/or electrochemical... Agent: Greenblum & Bernstein, P.L.C

20080233726 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a gate conductive layer, a first mask layer, a second mask layer, and a third mask layer over a semiconductor substrate that includes a cell region and a peripheral region. The method also includes forming a second mask pattern and a... Agent: Marshall, Gerstein & Borun LLP

20080233725 - Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures: Semiconductor material strips are secured to substrates in such a way as to stress the semiconductor material. The strips of semiconductor material may be compressively stressed, subjected to tensile stress, or some strips may be compressively stressed while other strips are tensilely stressed. Stress may be induced by forming non-planarities... Agent: Trask Britt, P.C./ Micron Technology

20080233727 - Method of manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. More specifically, in the invention, a gate pattern is formed and then an interlayer insulating pattern burying the space between the gate patterns is formed to ensure the region into which a landing plug contact hole has to be opened, thereby... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080233728 - Semiconductor device and a method for manufacturing the same: Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080233729 - Method of forming micro pattern in semiconductor device: A method of forming a fine pattern in a semiconductor device includes forming an target layer, a hard mask layer and first sacrificial patterns on a semiconductor substrate; forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns; performing the first... Agent: Townsend And Townsend And Crew, LLP

20080233730 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes providing a substrate where a cell region and a peripheral region are defined, stacking a conductive layer, a hard mask layer, a metal-based hard mask layer, and an amorphous carbon (C) pattern over the substrate etching the metal-based hard mask layer using... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080233731 - Method of forming top electrode for capacitor and interconnection in integrated passive device (ipd): A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and... Agent: Quarles & Brady LLP

20080233732 - Method of placing wires: A method of placing wires for placing a shield wire with respect to a shield subject wire placed on a chip, a method includes setting a plurality of wire tracks on the chip, dividing the chip into at least a first area and a second area according to a division... Agent: Sughrue Mion, PLLC

20080233733 - Method of wire bonding over active area of a semiconductor circuit: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over... Agent: Megica Corporation

20080233734 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080233735 - Etching method for semiconductor element: An etching method for semiconductor element is provided. The etching method includes the following procedure. First, a to-be-etched substrate is provided. Then, a silicon-rich silicon oxide (SRO) layer is formed on the to-be-etched substrate. Afterwards, an anti-reflective layer is formed on the SRO layer. Then, a patterned photo resist layer... Agent: Rabin & Berdo, PC

20080233736 - Process for manufacturing semiconductor integrated circuit device: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080233737 - Method of fabricating intergrated circuit chip: A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and an external region by a die seal ring region. A number of circuit units are then formed in the... Agent: Jianq Chyun Intellectual Property Office

20080233738 - Methods for fabricating an integrated circuit: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080233739 - Method for fabricating conductive layer: A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution... Agent: Jianq Chyun Intellectual Property Office

20080233740 - Method for producing electrically conductive bushings through non-conductive or semiconductive substrates: The present invention relates to a method for producing electrical bushings through non-conductive or semiconductive substrates, which are particularly suitable for electrical applications. The method is characterized in that a semiconductor substrate or a non-conductive substrate (13) whose front side has an electrically conductive contact point (6) at least one... Agent: Duane Morris, LLPIPDepartment

20080233741 - Bulk-isolated pn diode and method of forming a bulk-isolated pn diode: A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a dielectric material over the doped region. The method may also include forming first and second holes in the dielectric material exposing the... Agent: Fletcher Yoder (micron Technology, Inc.)

20080233743 - Method and structure for self-aligned device contacts: Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080233742 - Method of depositing aluminum layer and method of forming contact of semiconductor device using the same: A contact hole is formed in an interlayer insulating layer disposed on a semiconductor substrate. The semiconductor substrate is loaded into a reaction chamber. A reaction gas including an aluminum precursor is injected into the reaction chamber. Reaction energy is supplied to the reaction chamber so as to allow thermal... Agent: Townsend And Townsend And Crew, LLP

20080233744 - Carbon nanotube switches for memory, rf communications and sensing applications, and methods of making the same: Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at... Agent: Hiscock & Barclay, LLP

20080233745 - Interconnect structures for semiconductor devices: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In... Agent: Slater & Matsil, L.L.P.

20080233748 - Etch depth determination for sgt technology: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test... Agent: Joshua D. Isenberg Jdi Patent

20080233746 - Method for manufacturing mos transistors utilizing a hybrid hard mask: A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing... Agent: North America Intellectual Property Corporation

20080233747 - Semiconductor device manufactured using an improved plasma etch process for a fully silicided gate flow process: In one aspect, there us provided a method of manufacturing a semiconductor device that comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the... Agent: Texas Instruments Incorporated

20080233750 - Method for forming fine patterns in semiconductor device: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080233749 - Methods and apparatuses for removing polysilicon from semiconductor workpieces: Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains... Agent: Perkins Coie LLP Patent-sea

20080233751 - Ic chip uniform delayering methods: Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at... Agent: Hoffman Warnick LLC

20080233752 - Method for manufacturing floating structure of microelectromechanical system: Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on... Agent: Ladas & Parry LLP

20080233753 - Method of manufacturing a semiconductor device and a semiconductor manufacturing equipment: A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080233754 - Substrate peripheral film-removing apparatus and substrate peripheral film-removing method: A substrate peripheral film-removing apparatus which is capable of removing a film from a substrate periphery without complicating the construction of the apparatus. A wafer chamber receives a wafer having an SiO2 film formed on a periphery thereof. In a beveled portion-receiving chamber, film-removing chemical processing is carried out on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080233755 - Method of removing metallic, inorganic and organic contaminants from chip passivation layer surfaces: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic... Agent: Harrington & Smith, PC

20080233756 - Particle-removing apparatus for a semiconductor device manufacturing apparatus and method of removing particles: In a semiconductor device manufacturing apparatus that processing a substrate by applying a voltage to a gas to create a plasma, positively charged particles are trapped or guided at the instant that the cathode voltage is stopped, by an electrode to which is imparted a negative voltage, so as to... Agent: Muirhead And Saturnelli, LLC

20080233757 - Plasma processing method: A plasma processing method for processing a target substrate uses a plasma processing apparatus which includes a vacuum evacuable processing vessel for accommodating the target substrate therein, a first electrode disposed in the processing vessel and connected to a first RF power supply for plasma generation and a second electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080233758 - Method for forming trench and method for fabricating semiconductor device using the same: A method for forming a trench includes providing a substrate, and forming the trench in the substrate using a gas containing chlorine (Cl2) gas as a main etch gas and SiFX gas as an additive gas, wherein a sidewall of the trench has a substantially vertical profile by virtue of... Agent: Lowe Hauptman Ham & Berner, LLP

20080233759 - High selectivity bpsg to teos etchant: Methods of selectively etching BPSG over TEOS are disclosed. In one embodiment, a TEOS layer may be used to prevent contamination of other components in a semiconductor device by the boron and phosphorous in a layer of BPSG deposited over the TEOS layer. An etchant of the present invention may... Agent: Trask Britt, P.C./ Micron Technology

20080233760 - Process for the treatment of substrate surfaces: The present invention relates in general terms to the treatment or processing of substrate surfaces. In particular, the invention relates to processes for modifying the surface of silicon wafers.... Agent: Griffin & Szipl, PC

20080233761 - Fabrication method of semiconductor integrated circuit device: An object of the present invention is to provide a fabrication method of a semiconductor integrated circuit device capable of improving the throughput, reducing the cost of a cleaning gas and prolonging the life of a process kit by automatically detecting the end point of cleaning in a chamber. A... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080233762 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a high dielectric insulating layer. An amorphous high dielectric insulating layer having a high density is formed by using a precursor which can be deposited through the atomic layer deposition method at a temperature above 400° C. A resulting insulating exhibits... Agent: Townsend And Townsend And Crew, LLP

20080233763 - Method of achieving uniform length of carbon nanotubes (cnts) and method of manufacturing field emission device (fed) using such cnts: In a method of achieving uniform lengths of Carbon NanoTubes (CNTs) and a method of manufacturing a Field Emission Device (FED) using such CNTs, an organic film is coated to cover CNTs formed on a predetermined material layer. The organic film is etched to a predetermined depth to remove projected... Agent: Robert E. Bushnell

20080233764 - Formation of gate insulation film: A method of forming a gate insulation film 4 comprising a hafnium silicate material with a SiO2 equivalent oxide thickness of 1.45 nm or less on a silicon substrate 1 is disclosed. The method includes the steps of: cleaning a surface of the silicon substrate 1 to establish thereon a... Agent: Smith, Gambrell & Russell

20080233765 - Method for enhancing adhesion between layers: A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080233766 - Ashing method and apparatus therefor: An ashing method of a target substrate is applied after plasma-etching a part of a low-k film by using a patterned resist film as a mask in a vacuum processing chamber. The method includes a process of removing the resist film in the vacuum processing chamber, and a pre-ashing process,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080227223 - Active matrix substrate and repairing method thereof: An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged... Agent: Jianq Chyun Intellectual Property Office

20080227224 - Method of manufacturing semiconductor device and control system: When a multi-layer structure is formed by forming the interconnect trenches or via holes having different patterns in a plurality of insulating films, an anti-reflective film and an upper resist film are stacked in this order over an insulating interlayer, and the anti-reflective film is etched through the upper resist... Agent: Mcginn Intellectual Property Law Group, PLLC

20080227225 - Method and apparatus for manufacturing a semiconductor device: The present invention relates to a method of manufacturing a semiconductor device wherein etching is performed on films on a wafer using a plasma treatment apparatus. In the manufacturing method according to the present invention, a change in the difference between the emission intensities of a first wavelength component and... Agent: Mcginn Intellectual Property Law Group, PLLC

20080227226 - Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device: A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080227227 - Dynamic temperature backside gas control for improved within-substrate process uniformity: A method and apparatus are provided to control the radial or non-radial temperature distribution across a substrate during processing to compensate for non-uniform effects, including radial and angular non-uniformities arising from system variations, or process variations, or both. The temperature is controlled, preferably dynamically, by flowing backside gas differently across... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080227228 - Measurement of overlay offset in semiconductor processing: A method of semiconductor manufacturing including forming an overlay offset measurement target including a first feature on a first layer and a second feature on a second layer. The first feature and the second feature have a first predetermined overlay offset. The target is irradiated. The reflectivity of the irradiated... Agent: Haynes And Boone, LLP

20080227229 - Method of fabrication mems integrated circuits: m

20080227230 - Quantum dot vertical cavity surface emitting laser and fabrication method of the same: A quantum dot vertical capacity surface emitting laser (QD-VCSEL) and a method of manufacturing the same are provided. The QD-VCSEL includes a substrate, a lower distributed brag reflector (DBR) mirror formed on the substrate, an electron transport layer (ETL) formed on the lower DBR mirror, an emitting layer (EML) formed... Agent: Buchanan, Ingersoll & Rooney PC

20080227231 - Thin film transistor liquid crystal display and manufacturing method thereof: A manufacturing method and the structure of a thin film transistor liquid crystal display (TFT-LCD) are disclosed. The TFT-LCD uses metal electrodes as a mask to thoroughly remove the unwanted semiconductor layer during the etching process for forming the source and drain electrodes. This manufacturing method can reduce the problems... Agent: Ladas & Parry

20080227232 - Method for manufacturing display device: An object is to provide a display device that can be manufactured by improvement of use efficiency of a material and simplification of a manufacturing process. A light absorbing layer is formed, an insulating layer is formed over the light absorbing layer, the light absorbing layer and the insulating layer... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080227233 - Method for manufacturing semiconductor optical device: A method for manufacturing a semiconductor optical device includes forming a BDR (Band Discontinuity Reduction) layer of a first conductivity type doped with an impurity, depositing a contact layer of the first conductivity type in contact with the BDR layer after forming the BDR layer, the contact layer being doped... Agent: Leydig Voit & Mayer, Ltd

20080227234 - Method of manufacturing a semiconductor device: A semiconductor device is manufactured in a silicon-on-insulator (SOI) wafer having an silicon active layer, a buried oxide layer, and a supporting substrate layer. Before the wafer is diced into chips along scribe lines, the silicon active layer is selectively etched to form trenches surrounding the scribe lines. The wafer... Agent: Rabin & Berdo, PC

20080227235 - Sensor component and method for producing a sensor component: A device for detecting a measured quantity has a sensor chip for detecting the measured quantity, a supply for providing a power supply, and an injection-molded enclosure for accommodating the sensor chip and the supply, the injection-molded enclosure including integrated conductive traces providing an electrical connection between the sensor chip... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080227236 - Substrate structures for integrated series connected photovoltaic arrays and process of manufacture of such arrays: This invention comprises manufacture of photovoltaic cells by deposition of thin film photovoltaic junctions on metal foil substrates. The photovoltaic junctions may be heat treated if appropriate following deposition in a continuous fashion without deterioration of the metal support structure. In a separate operation, an interconnection substrate structure is provided,... Agent: Daniel Luch

20080227237 - Method of assembling chips: A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is... Agent: Megica Corporation

20080227238 - Integrated circuit package system employing multi-package module techniques: An integrated circuit package system that includes: providing a first package including a first package first device and a first package second device both adjacent a first package substrate; and mounting and electrically interconnecting a second package over an electrical interconnect array formed on a substrate of the first package... Agent: Law Offices Of Mikio Ishimaru

20080227239 - Semiconductor-chip exfoliating device and semiconductor-device manufacturing method: A semiconductor-chip exfoliating device for exfoliating a semiconductor chip 1 from an adhesive sheet 6 is provided. The device includes a backup holder 28 for holding the adhesive sheet 6 so that semiconductor chips 1 turn upward, a pair of needle pins arranged on a backside of the holder 28... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080227240 - Semiconductor-chip exfoliating device and semiconductor-device manufacturing method: The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using a highly compressive... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080227241 - Method of fabricating semiconductor device: A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a <110> direction. These wafers are surface-bonded together so... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080227242 - Pixel structure of a thin film transistor liquid crystal display: A pixel structure of a thin film transistor liquid crystal display employs a design of three metal layers and includes an organic insulating layer between a data signal line and a common electrode for reducing a parasitic capacitance, while a passivation layer included between the common electrode and a pixel... Agent: Hdsl

20080227243 - Method of fabricating thin film transistor and array substrate for liquid crystal display device including the same: According to an embodiment, a method of fabricating a thin film transistor comprises forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor layer on the gate insulating layer, the semiconductor layer corresponding to the gate electrode; forming first and second... Agent: Birch Stewart Kolasch & Birch

20080227244 - Method of fabricating array substrate for liquid crystal display device: A method of fabricating an array substrate for a liquid crystal display device comprises forming a gate line, a data line that crosses the gate line and a thin film transistor connected to the gate line and the data line on a substrate, and forming an organic insulating material layer... Agent: Brinks Hofer Gilson & Lione

20080227245 - Thin film transistor array panel and a method for manufacturing the same: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on... Agent: Cantor Colburn, LLP

20080227246 - Method of sulfuration treatment for a strained inalas/ingaas metamorphic high electron mobility transistor: This invention relates to a method of sulfuration treatment for InAlAs/InGaAs metamorphic high electron mobility transistor (MHEMT), and the sulfuration treatment is applied to the InAlAs/InGaAs MHEMT for a passivation treatment for Gate, in order to increase initial voltage, lower the surface states and decrease surface leakage current, which makes... Agent: Nikolai & Mersereau, P.A.

20080227247 - Barrier dielectric stack for seam protection: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric... Agent: Scully, Scott, Murphy & Presser, P.C.

20080227248 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a manufacturing method are disclosed. The gates of the transistors are formed in the active region of the unit pixel, and a diffusion region for the photo diode is defined by an ion implantation of impurities to the semiconductor substrate. The patterns of the photoresist... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080227249 - Cmos image sensor white pixel performance: Methods and systems for forming a photodiode in a substrate, forming a source/drain region in the substrate and extending over at least a portion of the photodiode, and growing a thermal oxide layer over the photodiode by performing a rapid thermal anneal (RTA) process utilizing an oxidizing environment.... Agent: Haynes And Boone, LLP

20080227250 - Cmos device with dual-epi channels and self-aligned contacts: A CMOS device having dual-epi channels comprises a first epitaxial region formed on a substrate, a PMOS device formed on the first epitaxial region, a second epitaxial region formed on the substrate, wherein the second epitaxial region is formed from a different material than the first epitaxial region, an NMOS... Agent: Intel Corporation C/o Intellevate, LLC

20080227251 - Semiconductor integrated circuit device and process for manufacturing the same: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation... Agent: Miles & Stockbridge PC

20080227252 - Fabrication methods of thin film transistor substrates: Methods for manufacturing thin film transistor arrays utilizing three steps of lithography and one step of laser ablation while the lithography procedure is used four to five times in conventional processes are disclosed. The use of the disclosed methods assists in improving throughput and saving of manufacturing cost.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080227253 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device which includes a first gate wiring layer and a second gate wiring layer adjacent to each other; a first diffused layer provided on a side between the wiring layers; a second diffused layer provided on one side external to the side between the... Agent: Young & Thompson

20080227254 - Electronic device including channel regions lying at different elevations and processes of forming the same: An electronic device including a nonvolatile memory cell can include a substrate including a first portion and a second portion, wherein a first major surface within the first portion lies at an elevation lower than a second major surface within the second portion. The electronic device can also include a... Agent: Larson Newman Abel Polansky & White, LLP

20080227255 - Methods of forming vertical transistors: A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over the first pillar, forming... Agent: Wells St. John P.s.

20080227256 - Method of manufacturing silicon carbide semiconductor device: A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate... Agent: Young & Basile, P.C.

20080227257 - Methods for forming semiconductor devices: A method for forming a semiconductor device comprises providing a substrate. A N type region and a non-N type region are formed in the substrate. The substrate is wet etched to form a protruding portion in the N type region and a concave portion in the non-N type region. A... Agent: Quintero Law Office, PC

20080227258 - Methods of forming a semiconductor device: Methods of forming a semiconductor device include forming a mask layer on a semiconductor substrate. The mask layer has vertically and horizontally extending portions. The vertically extending portions have a thickness selected to provide a desired line width to an underlying structure to be formed using the mask layer and... Agent: Myers Bigel Sibley & Sajovec

20080227259 - Self-aligned process for nanotube/nanowire fets: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention... Agent: Scully, Scott, Murphy & Presser, P.C.

20080227260 - Method for fabricating semiconductor device with thin gate spacer: A method for fabricating a transistor. A substrate having a gate electrode thereon and insulated therefrom is provided. A first gate spacer with a first dielectric material is formed on the sidewalls of the gate electrode. A liner with a second dielectric material is formed on the upper surfaces of... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080227261 - Method for fabricating a transistor structure: The invention is distinguished by the fact that all junctions between differently doped regions have a sharp interface. In this case, by way of example, a first collector region 2.1 is suitable for a high-frequency transistor with high limiting frequencies fT and a second collector region 2.2 is suitable for... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080227262 - Vertically base-connected bipolar transistor: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.... Agent: Brooks, Cameron & Huebsch , PLLC

20080227263 - Semiconductor device and method for fabricating the same: A semiconductor device of the present invention includes a plurality of lower electrodes covering the entire surfaces of a plurality of trenches formed in a first interlayer insulating film, a capacitive insulating film covering the entire surfaces of the plurality of lower electrodes, and an upper electrode covering the surfaces... Agent: Mcdermott Will & Emery LLP

20080227264 - Vertical nanotube semiconductor device structures and methods of forming the same: Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080227265 - Methods for fabricating semiconductor devices: Methods of fabricating a gate-insulating layer of a dual-gate semiconductor device are disclosed. A disclosed method comprises sequentially forming a buffer oxide layer and a nitride layer on a semiconductor substrate having at least one high voltage device area and at least one low voltage device area; forming at least... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080227266 - Method of sti corner rounding using nitridation and high temperature thermal processing: One embodiment of the present invention relates to a method of forming an isolation structure with rounded corners in a semiconductor substrate, comprising forming an isolation trench within the semiconductor substrate, performing an oxidation blocking nitridation process on exposed surfaces of the trench, performing corner rounding by oxidizing the exposed... Agent: Texas Instruments Incorporated

20080227267 - Stop mechanism for trench reshaping process: An opening, such as a trench, on a semiconductor substrate is annealed to smooth edges and corners of the opening. The anneal causes reflow of the material forming the walls of the opening, thereby smoothing out the edges and corners of the opening. After a desired amount of reflow is... Agent: Knobbe Martens Olson & Bear LLP

20080227268 - Method of forming an isolation layer in a semiconductor memory device: A method of forming an isolation layer in a semiconductor memory device is disclosed. After a trench is formed in a semiconductor substrate, a plasma nitrification annealing process is performed before and preferably after a wall oxide layer is formed to prevent trap charges and degradation problems at the interface... Agent: Marshall, Gerstein & Borun LLP

20080227269 - Termination trench structure for mosgated device and process for its manufacture: A process for the fabrication of a MOSgated device that includes a plurality of spaced trenches in the termination region thereof.... Agent: Ostrolenk Faber Gerb & Soffen

20080227270 - Low temperature fusion bonding with high surface energy using a wet chemical treatment: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been... Agent: Scully, Scott, Murphy & Presser, P.C.

20080227271 - Method of manufacturing bonded wafer: The present invention provides a method of manufacturing a bonded wafer. The method includes ozone washing two silicon wafers to form an oxide film equal to or less than 2.2 nm in thickness on each surface of the two silicon wafers, and bonding the two silicon wafers through the oxide... Agent: Greenblum & Bernstein, P.L.C

20080227272 - Wafer dividing method: A method of dividing a wafer having a plurality of streets which are formed in a lattice pattern on the front surface and having devices which are formed in a plurality of areas sectioned by the plurality of streets into individual devices along the streets, the method comprising the steps... Agent: Smith, Gambrell & Russell

20080227273 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes: a) forming a first semiconductor layer on a semiconductor substrate; b) forming a second semiconductor layer on the first semiconductor layer; c) forming a first groove exposing a side of the first semiconductor layer by partially etching the first semiconductor layer and... Agent: Harness, Dickey & Pierce, P.L.C

20080227274 - Manufacturing method of display device: In crystallization of a silicon film by annealing using a linear-shaped laser beam having a width of the short axis of the beam is ununiform, the profile (intensity distribution) of the laser beam is evaluated and the results are fed back to a condition of oscillating the laser beam or... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080227275 - Method and device with durable contact on silicon carbide: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.... Agent: Hiscock & Barclay, LLP

20080227276 - Silicon substrate with reduced surface roughness: The present disclosure provides a method for fabricating a semiconductor device including providing a semiconductor substrate comprising a first surface and a second surface, wherein at least one imaging sensor is located adjacent the first surface, activating a dopant layer in the semiconductor substrate adjacent the second surface using a... Agent: Haynes And Boone, LLP

20080227277 - Method of manufacturing semiconductor element: A method of manufacturing a semiconductor element includes implanting ions of a dopant having a large diffusion coefficient into a semiconductor to provide a doped layer; and irradiating the doped layer with a plurality of pulsed laser beams supplied by a plurality of laser irradiation devices to activate the doped... Agent: Rabin & Berdo, PC

20080227278 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device including an NMOS transistor and a PMOS transistor is provided. The method includes: forming a silicon layer over a substrate through a gate insulating film; forming a first gate electrode and a second gate electrode by patterning the silicon layer, the first gate... Agent: Young & Thompson

20080227279 - Method of manufacturing semiconductor device: According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and a NMOS transistor, wherein the method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through... Agent: Young & Thompson Suite 500

20080227280 - Method of manufacturing semiconductor device: According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and an NMOS transistor, wherein the method facilitates obtaining a full silicide phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and... Agent: Young & Thompson

20080227281 - Method for fabricating semiconductor device with recess gate: A method for fabricating a semiconductor device includes forming a sacrificial layer having a stack structure of a first insulation layer, a first conductive layer and a second insulation layer over a substrate, forming a recess by etching the sacrificial layer and the substrate, forming a gate insulation layer over... Agent: Lowe Hauptman Ham & Berner, LLP

20080227282 - Method of manufacturing non-volatile memory: A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of... Agent: Jianq Chyun Intellectual Property Office

20080227283 - Self-aligned metal to form contacts to ge containing substrates and structure formed thereby: A method for forming gennano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop... Agent: Scully, Scott, Murphy & Presser, P.C.

20080227284 - Wire bonding method and related device for high-frequency applications: A wire bond circuit device has a circuit die in which substantially all of the input/output (I/O) pads are disposed along the outermost row of pads. A substrate onto which the die is disposed has wedges that are similarly arranged in rows, with the wedges used to carry I/O placed... Agent: Ryan, Mason & Lewis, LLP

20080227285 - Wirebond structure and method to connect to a microelectronic die: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20080227286 - Method for manufacturing an interconnection structure with cavities for an integrated circuit: w

20080227288 - Dual damascene process: A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080227287 - Method for dual damascene process: The present disclosure provides a method of dual damascene processing. The method includes providing a substrate having vias formed therein; forming an under-layer in the vias and on the substrate; applying a solvent washing process to the under-layer; forming a silicon contained layer on the under-layer; patterning the silicon contained... Agent: Haynes And Boone, LLP

20080227289 - Method of fabricating integrated circuitry: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b)... Agent: Wells St. John P.s.

20080227290 - Semiconductor device and method for fabricating the same: A method of fabricating a semiconductor device includes forming a barrier film over a semiconductor substrate and over a gate disposed on the substrate; forming a metal layer over the barrier film; selectively etching the metal layer and the barrier film to form a contact pattern between the gates; forming... Agent: Marshall, Gerstein & Borun LLP

20080227291 - Formation of composite tungsten films: Embodiments of the invention provide methods for depositing tungsten materials. In one embodiment, a method for forming a composite tungsten film is provided which includes positioning a substrate within a process chamber, forming a tungsten nucleation layer on the substrate by subsequently exposing the substrate to a tungsten precursor and... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080227292 - Method for manufacturing semiconductor device: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer, forming a semiconductor function element on the semiconductor wafer, drying the semiconductor wafer after forming the semiconductor function element by using an isopropyl alcohol vapor, heating the semiconductor wafer after drying the semiconductor wafer, and performing an RA... Agent: Volentine & Whitt PLLC

20080227293 - Integrated circuit fabrication: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature... Agent: Knobbe Martens Olson & Bear LLP

20080227294 - Method of making an interconnect structure: A method of making an interconnect structure includes providing a die (120) having an electrically conducting pad (140) and further includes using electrophoresis to place a plurality of nanostructures (150) on the electrically conducting pad.... Agent: Intel Corporation C/o Intellevate, LLC

20080227295 - Self-aligned contact frequency doubling technology for memory and logic device applications: Contact spatial-frequency doubling technology is invented to pattern a contact-hole array and a row/column (or multiple isolated rows/columns) of contact holes with their density increased to twice of the maximum density achievable during one exposure with a conventional lithographic technology. These contact frequency doubling processes can be used not only... Agent: Yijian Chen

20080227296 - Slurry compositions, methods of preparing slurry compositions, and methods of polishing an object using slurry compositions: A slurry composition includes an acidic aqueous solution and one or both of, an amphoteric surfactant and a glycol compound. Examples of the amphoteric surfactant include a betaine compound and an amino acid compound, and examples of the amino acid compound include lysine, proline and arginine. Examples of the glycol... Agent: Volentine & Whitt PLLC

20080227297 - Chemical mechanical polishing method and method for manufacturing semiconductor device: A chemically mechanically polishing method is provided, which includes slide-contacting a polishing film with a polishing pad while feeding a first chemical liquid and a second chemical liquid to the polishing pad. The first chemical liquid contains an electrolyte and bubbles having a diameter ranging from 10 nm to 1000... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080227298 - Semiconductor device manufacturing method: The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper layer is reduced by making separate layers respectively serve as a mask during forming... Agent: Young & Thompson

20080227299 - Tapered edge exposure for removal of material from a semiconductor wafer: A semiconductor wafer edge exposure process as described herein employs a photoresist exposure step that exposes photoresist material to radiation having a gradient intensity profile near the outer edge of the wafer. The gradient intensity profile creates a tapered outer edge in the developed photoresist material, which in turn creates... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080227300 - Method for manufacturing semiconductor device: A method of manufacturing a semiconductor device prevents a pattern bridge phenomenon generated by a proximity effect between patterns and a thickness lowering phenomenon of the pattern. As a result, a length of the major axis required in characteristics of the device is secured to improve an electric characteristic and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080227301 - Control of bevel etch film profile using plasma exclusion zone rings larger than the wafer diameter: A method of cleaning a bevel edge of a semiconductor substrate is provided. A semiconductor substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. The substrate has a dielectric layer overlying a top surface and a bevel edge of the substrate, the layer... Agent: Buchanan, Ingersoll & Rooney PC

20080227302 - Fibrous laminate interface for security coatings: an integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at... Agent: Honeywell International Inc.

20080227303 - Systems and methods for forming tantalum oxide layers and tantalum precursor compounds: A method of forming (and apparatus for forming) a tantalum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and a tantalum precursor compound that includes alkoxide ligands, for example.... Agent: Mueting, Raasch & Gebhardt, P.A.

20080220541 - Process for structuring a surface layer: A process for structuring a surface layer of an object includes applying bio-components to the surface of the object that carry away surface material. The bio-components are contained in at least one of a nutrient and osmotic protective medium. The at least one of a nutrient and osmotic protective medium... Agent: Panitch Schwarze Belisario & Nadel LLP

20080220542 - Low-fire ferroelectric material: A low-fire ferroelectric composition, includes a lead bismuth titanate compound having a formula represented by: (Bi2O2)x2+(Mm−1TimO3m−1)x2− wherein in represents a number 1 through 5, M represents a combination of bismuth and lead, and x represents a number of cations and anions present in the compound, and a eutectic mixture of... Agent: Cantor Colburn, LLP

20080220543 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080220544 - Method for utilizing heavily doped silicon feedstock to produce substrates for photovoltaic applications by dopant compensation during crystal growth: A method for using relatively low-cost silicon with low metal impurity concentration by adding a measured amount of dopant before and/or during silicon crystal growth so as to nearly balance, or compensate, the p-type and n-type dopants in the crystal, thereby controlling the net doping concentration within an acceptable range... Agent: Holland & Knight LLP Attn: Stefan V. Stein/ Ip Dept.

20080220545 - System and method for testing and providing an integrated circuit having multiple modules or submodules: In an integrated circuit having a plurality of modules and/or submodules that each perform a substantially same function, defective modules and/or submodules are determined by creating a test signature from an input test pattern. The output of each module and/or submodule is compared with the test signature and defective modules... Agent: Freescale Semiconductor, Inc. Law Department

20080220546 - Method for simulating deposition film shape and method for manufacturing electronic device: A deposition film shape simulation method for calculating a thickness of a thin-film formed by supplying deposition species on a substrate surface, includes: changing a parameter to be used in the calculation depending on the thickness of the deposited thin-film.... Agent: Pearne & Gordon LLP

20080220547 - Single-chip surface mounted led structure and a method for manufacturing the same: A single-chip surface mounted LED structure and a method for manufacturing the same, said LED structure mainly comprises an LED chip, a heat sink structure, two opposing electrodes, conducting wires and a supporting structure; said method comprises the steps of firstly cutting off a spare area other than said heat... Agent: Sinorica, Llc

20080220548 - Multi-chip surface mounted led structure and a method for manufacturing the same: A multi-chip surface mounted LED structure and a method for manufacturing the same, said LED structure comprises a plurality of equivalent lighting units, each lighting unit comprises an LED chip, a heat sink structure, two opposing electrodes, said plurality of equivalent lighting units are mutually connected by a supporting structure;... Agent: Sinorica, Llc

20080220549 - Sealed light emitting diode assemblies including annular gaskets and methods of making same: An optoelectronic device assembly includes a circuit board and an optoelectronic device disposed on the circuit board and electrically connected with the circuit board. An annular gasket is disposed on the circuit board and surrounds the optoelectronic device. A sealant is disposed over and seals at least a portion of... Agent: Fay Sharpe LLP

20080220551 - Display panels and fabrication methods thereof: A display panel including a pixel array region. The pixel array region includes a plurality of pixel cells disposed in a matrix configuration. Each pixel cell has an active device. A relative position of a first active device in a first pixel cell among the pixel cells is different from... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080220552 - Fabricating a spatial light modulator: A high contrast spatial light modulator for display and printing is fabricated by coupling a high active reflection area fill-ratio and non-diffractive micro-mirror array with a high electrostatic efficiency and low surface adhesion control substrate.... Agent: Fish & Richardson P.c.

20080220550 - Method of producing n-type group-13 nitride semiconductor, method of forming current confinement layer, method of producing surface emitting laser, method of changing resistance of nitride semiconductor and method of producing semiconductor laser: The object of the present invention is to provide a method of producing an n-type group-13 nitride semiconductor which enables resistance of the n-type group-13 nitride semiconductor to be changed, as well as, a method of producing a laser using the above method to produce a current confinement structure. There... Agent: Fitzpatrick Cella Harper & Scinto

20080220553 - Method of producing liquid crystal display device including forming an align mark in an insulating mother substrate: A method of producing a liquid crystal display in which elements can be precisely aligned includes: providing an insulating mother substrate; forming an align mark within the insulating mother substrate by irradiating laser light, which has a wavelength less than 355 nm and having an insulating mother substrate absorbance of... Agent: Frank Chau, Esq. F. Chau & Associates, Llc

20080220554 - Optical substrate, light emitting element, display device and manufacturing methods thereof: The present invention relates to an optical substrate comprising a transparent substrate a low refractive index layer, whose refractive index is lower than that of the transparent substrate, disposed over the transparent substrate, and a solgel film disposed over the low refractive index layer; a light emitting element having a... Agent: Scully Scott Murphy & Presser, Pc

20080220555 - Nitride semiconductor structures with interlayer structures and methods of fabricating nitride semiconductor structures with interlayer structures: A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080220556 - Method of manufacturing enhancement type semiconductor probe and information storage device having the semiconductor probe using the same: A method of manufacturing an enhancement type semiconductor probe and an information storage device having the enhancement type semiconductor probe are provided. The method involves using an anisotropic wet etching and a side-wall in which influence of process parameters upon the performance of a device is reduced to improve reliability... Agent: Sughrue Mion, Pllc

20080220557 - Sensor manufacture with data storage: A biometric sensing device includes a sensor manufacture for sensing a biometric stimulus. The sensor manufacture is also configured to persistently store data electronically, such as security data.... Agent: Fish & Richardson P.c.

20080220558 - Plasma spraying for semiconductor grade silicon: A plasma spray gun configured to spray semiconductor grade silicon to form semiconductor structures including p-n junctions includes silicon parts such as the cathode or anode or other parts facing the plasma or carrying the silicon powder having at least surface portions formed of high purity silicon. The semiconductor dopant... Agent: Law Offices Of Charles Guenzer

20080220559 - Solar cell, manufacturing method thereof and electrode material: There is presented a solar cell comprising a semiconductor substrate of one conductivity-type, a layer of the opposite conductivity-type provided on a surface side of the semiconductor substrate, a surface electrode formed thereon, and a backside electrode formed on a backside of the semiconductor substrate, wherein the semiconductor substrate is... Agent: Hogan & Hartson L.l.p.

20080220560 - Programmable resistance memory element and method for making same: A programmable resistance memory element. The active volume of memory material is made small by the presence of a small area of contact between the conductive material and the memory material. The area of contact is created by forming a region of conductive material and an intersecting sidewall layer of... Agent: Ovonyx, Inc

20080220561 - Melt-based patterning for electronic devices: The present invention provides methods and apparatus for melt-based patterning for electronic devices. It employs and provides processes and apparatus for fabricating an electronic device having a pattern formed on a surface by a deposition material. Further, the invention a process for fabricating semiconductors, organic light-emitting devices (OLEDs), field-effect transistors,... Agent: Louis Paul Herzberg

20080220562 - Structure and fabrication of self-aligned high-performance organic fets: A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor... Agent: Weyerhaeuser Company Intellectual Property Dept., Ch 1j27

20080220563 - Module having stacked chip scale semiconductor packages: Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the substrate side of the top chip scale package, the second package being electrically connected to the first package by wire... Agent: Law Offices Of Mikio Ishimaru

20080220565 - Design techniques for stacking identical memory dies: A semiconductor structure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a... Agent: Slater & Matsil, L.l.p.

20080220564 - Semiconductor module: A semiconductor module is disclosed. One embodiment provides a first semiconductor chip, a second semiconductor chip and a spacer. The first semiconductor chip has a depression at a first main surface. The spacer is applied to the first main surface and at least partly fills the depression. The second semiconductor... Agent: Dicke, Billig & Czaja

20080220566 - Substrate process for an embedded component: A substrate process for an embedded component is disclosed. A mold having a surface and protruding components protruded from the surface is provided. A first dielectric layer is formed on the surface and covers the protruding components. At least one electronic component having an active surface, a back surface, and... Agent: North America Intellectual Property Corporation

20080220568 - Manufacturing method of semiconductor device: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080220567 - Semiconductor component and production method: A semiconductor component is disclosed. In one embodiment, the semiconductor component includes a semiconductor chip, which is arranged on a substrate, and a housing, which at least partially surrounds the semiconductor chip. The substrate is at least partly provided with a layer of polymer foam.... Agent: Dicke, Billig & Czaja

20080220569 - Method for manufacturing a field effect transistor with auto-aligned grids: s

20080220570 - Semiconductor device and manufacturing method thereof: A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The THF of the present invention is characterized by its semiconductor layer where the thickness of the source region or the... Agent: Eric Robinson

20080220571 - High mobility power metal-oxide semiconductor field-effect transistors: High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110]... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20080220572 - Silicon rich barrier layers for integrated circuit devices: Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and... Agent: Dinsmore & Shohl LLP

20080220573 - Method for manufacturing semiconductor device: On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080220574 - Method of fabricating semiconductor device: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second... Agent: J C Patents, Inc.

20080220575 - Method of fabricating dynamic random access memory: A method of fabricating a dynamic random access memory is provided. A trench capacitor is formed in a substrate and an isolation structure is formed on the trench capacitor. A gate structure and a passing gate structure are formed on the substrate. The gate structure is on one side of... Agent: Jianq Chyun Intellectual Property Office

20080220576 - Manufacturing method of anti-punch-through semiconductor device: An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the... Agent: Jianq Chyun Intellectual Property Office

20080220577 - Scalable high density non-volatile memory cells in a contactless memory array: A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory... Agent: Leffert Jay & Polglaze, P.a. Attn: Kenneth W. Bolvin

20080220578 - Method of fabricating a non-volatile memory device: In a method of fabricating a non-volatile memory device, a semiconductor substrate includes an isolation layer formed in an isolation region, a tunnel insulating layer and a first conductive layer for a floating gate formed in an active region, and a dielectric layer, a second conductive layer for a control... Agent: Townsend And Townsend And Crew, LLP

20080220579 - Stress enhanced mos transistor and methods for its fabrication: According to a method for fabricating a stress enhanced MOS device having a channel region at a surface of a semiconductor substrate, first and second trenches are etched into the semiconductor substrate, the first trench having a first side surface, and the second trench having a second side surface. The... Agent: Ingrassia Fisher & Lorenz, P.c. (amd)

20080220580 - Semiconductor device and a method of manufacturing the same: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of... Agent: Miles & Stockbridge Pc

20080220581 - Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing... Agent: Scully, Scott, Murphy & Presser, P.c.

20080220582 - Semiconductor device and method of fabricating the same:

20080220583 - Semiconductor device structures for bipolar junction transistors and methods of fabricating such structures: Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080220585 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device comprises forming a silicon film, converting a surface of the silicon film into a hydrophilic surface, forming an insulating film over the silicon film, and polishing the insulating film formed over the silicon film.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080220584 - Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques: Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley... Agent: Myers Bigel Sibley & Sajovec

20080220586 - Methods for forming semiconductor structures with buried isolation collars and semiconductor structures formed by these methods: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080220587 - Dual stress sti: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080220588 - Strained si mosfet on tensile-strained sige-on-insulator (sgoi): A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer... Agent: Scully, Scott, Murphy & Presser, P.c.

20080220589 - Method for evaluation of bonded wafer: A bonded wafer formed by directly bonding a wafer for active layer and a wafer for support substrate without an insulating film and thinning the wafer for active layer is evaluated by a method comprising steps of removing native oxide from a surface of an active layer in the bonded... Agent: Sughrue Mion, Pllc

20080220590 - Thin wafer dicing using uv laser: In a method and system for dicing a wafer (220), an ultraviolet (UV) laser (210) is aligned with a street (222) on the wafer (220). A thickness of the wafer (220) is at most 400 times a wavelength of the UV laser (210). When energized, the UV laser (210) generates... Agent: Texas Instruments Incorporated

20080220591 - Method of manufacturing device: A method of manufacturing a device, including the steps of forming dividing grooves with a predetermined depth along planned dividing lines of a wafer, then grinding the back-side surface of the wafer to expose the dividing grooves on the back side, dividing the wafer into individual devices, attaching a UV-curable... Agent: Greer, Burns & Crain

20080220592 - Substrate processing apparatus, substrate processing method, and substrate planarization method: A substrate processing apparatus has a processing space provided with a holding stand for holding a substrate to be processed. A hydrogen catalyzing member is arranged in the processing space to face the substrate and for decomposing hydrogen molecules into hydrogen radicals H*. A gas feeding port is arranged in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080220593 - Nanoparticles: Method for producing a nanoparticle comprised of core, first shell and second shell semiconductor materials. Effecting conversion of a core precursor composition comprising separate first and second precursor species to the core material and then depositing said first and second shells. The conversion is effected in the presence of a... Agent: Goodwin Procter LLP Patent Administrator

20080220594 - Fabrication method of a mixed substrate and use of the substrate for producing circuits: The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive... Agent: Oliff & Berridge, Plc

20080220595 - Method for fabricating a hybrid orientation substrate: A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second... Agent: North America Intellectual Property Corporation

20080220596 - Delivery of low pressure dopant gas to a high voltage ion source: A system for delivery of low-pressure dopant gas to a high-voltage ion source in the doping of semiconductor substrates, in which undesired ionization of the gas is suppressed prior to entry into the high-voltage ion source, by modulating electron energy upstream of the high-voltage ion source so that electron acceleration... Agent: Intellectual Property / Technology Law

20080220597 - Photoresists and methods for use thereof: New photoresists are provided that can be applied and imaged with reduced undesired outgassing and/or as thick coating layers. Preferred resists of the invention are chemically-amplified positive-acting resists that contain photoactive and resin components.... Agent: Peter F. Corless Rohm And Haas Electronic Materials Llc

20080220598 - Method for dopant diffusion: A method for controlling dopant diffusion is disclosed. Using certain control parameters that are not used in the prior art, the method provides an unprecedented measure of control over the dopant diffusion process. The control parameters include, among others, the size of the diffusion windows in the diffusion mask and... Agent: Demont & Breyer, Llc

20080220599 - Method of fabricating short-gate-length electrodes for integrated iii-v compound semiconductor devices: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is... Agent: Bacon & Thomas, Pllc

20080220600 - Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the... Agent: Wells St. John P.s.

20080220602 - Method of manufacturing semiconductor device: The semiconductor manufacturing method comprises the step of forming a metal alloy film of an alloy of a metal of Ni or others and a noble metal over a semiconductor substrate containing a region where silicon is partially exposed; the step of selectively reacting the silicon in the region and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080220601 - Methods for forming nonvolatile memory elements with resistive-switching metal oxides: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in... Agent: G. Victor Treyz

20080220603 - Method of manufacturing semiconductor device: An embodiment of the present invention is a method of manufacturing a semiconductor device, for forming transistors of first and second conductivity types in first and second regions on a substrate respectively. The method includes: depositing a gate insulator and a sacrificial layer ranging from the first region to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080220604 - Air break for improved silicide formation with composite caps: Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080220605 - Method of manufacturing flash memory device: The present invention discloses a method of manufacturing a flash memory device comprising the steps of forming a first insulating layer and a first conductive layer on a semiconductor substrate; etching the first conductive layer, the first insulating layer and the semiconductor substrate to form a trench; forming an isolation... Agent: Marshall, Gerstein & Borun LLP

20080220606 - Self-aligned metal to form contacts to ge containing substrates and structure formed thereby: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop... Agent: Scully, Scott, Murphy & Presser, P.c.

20080220607 - Signal routing on redistribution layer: A method of routing signals within a semiconductor memory device includes providing a semiconductor wafer having a top surface with a center portion, an edge portion and wafer bond pads at the center portion. A redistribution layer is provided on the top surface of the semiconductor wafer. The method includes... Agent: Dicke, Billig & Czaja

20080220608 - Modified via bottom structure for reliability enhancement: The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the... Agent: Scully, Scott, Murphy & Presser, P.c.

20080220609 - Methods of forming mask patterns on semiconductor wafers that compensate for nonuniform center-to-edge etch rates during photolithographic processing: Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the... Agent: Myers Bigel Sibley & Sajovec

20080220610 - Silicon oxide polishing method utilizing colloidal silica: The inventive method comprises chemically-mechanically polishing a substrate with a polishing composition comprising a liquid carrier and sol-gel colloidal silica abrasive particles.... Agent: Steven Weseman Associate General Counsel, I.p.

20080220611 - Method of forming fine patterns of semiconductor devices using double patterning: A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns... Agent: Harness, Dickey & Pierce, P.L.C

20080220612 - Protection of polymer surfaces during micro-fabrication: A method of protecting a polymeric layer from contamination by a photoresist layer. The method includes: (a) forming a polymeric layer over a substrate; (b) forming a non-photoactive protection layer over the polymeric layer; (c) forming a photoresist layer over the protection layer; (d) exposing the photoresist layer to actinic... Agent: Schmeiser, Olsen & Watts

20080220613 - Protection of polymer surfaces during micro-fabrication: A method of protecting a polymeric layer from contamination by a photoresist layer. The method includes: (a) forming a polymeric layer over a substrate; (b) forming a non-photoactive protection layer over the polymeric layer; (c) forming a photoresist layer over the protection layer; (d) exposing the photoresist layer to actinic... Agent: Schmeiser, Olsen & Watts

20080220614 - Method for manufacturing image sensor device: The invention is directed to a method for manufacturing an image sensor device. The method comprises steps of forming a photodiode and a transistor on a substrate. A salicide block is formed over a photo-sensing region of the photodiode. An interconnects processes is performed several times to forming a plurality... Agent: Jianq Chyun Intellectual Property Office

20080220615 - Method for producing self-aligned mask, articles produced by same and composition for same: A method for forming a self-aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion... Agent: Scully, Scott, Murphy & Presser, P.c.

20080220616 - Process for manufacturing a semiconductor device: A process for manufacturing a semiconductor device, comprising: preparing a substrate in which a silicon-containing resist pattern is formed on a processed-material layer, dry-etching the processed-material layer using the silicon-containing resist pattern as a mask to form a processed-material layer pattern, ashing the silicon-containing resist pattern to leave a silicon-containing... Agent: Sughrue Mion, Pllc

20080220617 - Deep sti trench and soi undercut enabling sti oxide stressor: A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer (307) is provided which has a dielectric layer (305) disposed beneath it. A trench (319) is created which extends through the semiconductor layer and into the dielectric layer,... Agent: Fortkort & Houston P.c.

20080220618 - Zirconium silicon oxide films: Electronic apparatus, systems, and methods include structures having a dielectric layer containing zirconium silicon oxide film. The zirconium silicon oxide film may be disposed in an integrated circuit, as well as in a variety of other electronic devices. Additional apparatus, systems, and methods are disclosed.... Agent: Schwegman, Lundberg & Woessner/micron

20080220619 - Method for increasing mechanical strength of dielectric film by using sequential combination of two types of uv irradiation: A method for increasing mechanical strength of a dielectric film includes: providing an initial dielectric film containing porogen; irradiating the initial dielectric film with first UV light having a first wavelength which is substantially or nearly similar to a maximum light absorption wavelength of the porogen for removing the porogen;... Agent: Knobbe Martens Olson & Bear LLP

20080220620 - Method of manufacturing silicon carbide semiconductor device: A method of manufacturing a silicon carbide semiconductor device includes forming a trench for a MOS gate in an SiC substrate by dry etching. Thereafter, the substrate with the trench is heat treated. The heat treatment includes heating the substrate in an Ar gas atmosphere or in a mixed gas... Agent: Rossi, Kimms & Mcdowell LLP.

20080220621 - Substrate treatment apparatus and substrate treatment method: A substrate treatment apparatus that treats a substrate under treatment has an interface section, a substrate loading/unloading section, a reduced pressure atmosphere conveyance chamber, and an exposure treatment chamber. The interface section has a conveyance mechanism that can freely load and unload the substrate under treatment from another device into... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080220622 - Substrate processing pallet with cooling: A substrate processing pallet can cool a substrate. A substrate processing pallet can include a base member; an interface pad attachable to the base member, the interface pad having substantially the same coefficient of thermal expansion as the base member and adapted to facilitate cooling of the substrate; and a... Agent: Proskauer Rose LLP

20080213923 - Dna-based memory device and method of reading and writing same: The present invention is directed to a memory device having very high storage density capability. In general, the memory device includes an array of individual memory cells which store information that is assigned a value based on the molecular contents of the memory cell. In a preferred embodiment, the molecules... Agent: Dority & Manning, P.A.

20080213924 - Ferroelectric memory device and method of manufacturing the same: A method of manufacturing a ferroelectric memory device includes: forming a hydrogen barrier film which covers a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, wherein a thickness of an area of the hydrogen barrier film provided on the upper electrode is made greater than... Agent: Harness, Dickey & Pierce, P.L.C

20080213925 - Photometrically modulated delivery of reagents: A process system adapted for processing of or with a material therein. The process system includes: a sampling region for the material; an infrared photometric monitor constructed and arranged to transmit infrared radiation through the sampling region and to responsively generate an output signal correlative of the material in the... Agent: Intellectual Property / Technology Law

20080213926 - Method for evaluating a semiconductor substrate: A method for evaluating a semiconductor substrate is provided that can evaluate even a thin semiconductor substrate or a substrate with untreated surfaces, can evaluate a large quantity of semiconductor substrates for solar cells in a short time and can be used as in-line inspection in a production process of... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080213927 - Method for manufacturing an improved resistive structure: Provided, in one embodiment, is a method for manufacturing a resistive structure. This method, without limitation, includes forming a substrate, and forming a tantalum-aluminum-nitride resistive layer over the substrate. Moreover, a bulk resistivity of the tantalum-aluminum-nitride resistive layer may be adjusted by varying at least one deposition condition selected from... Agent: Texas Instruments Incorporated

20080213928 - Method for manufacturing semiconductor light emitting device: A method for manufacturing a semiconductor light emitting device can result in a device that includes a housing having a cavity, a light emitting element on a bottom face of the cavity, and a wavelength conversion layer provided within the cavity. The wavelength conversion layer can include particles of a... Agent: Cermak Kenealy & Vaidya, LLP

20080213930 - Dual panel-type organic electroluminescent display device and method of fabricating the same: A dual panel-type organic electroluminescent display device includes first and second substrates facing and spaced apart from each other, an array element layer disposed along an inner surface of the first substrate, the array element including a thin film transistor, a connection pattern disposed on the array element layer and... Agent: Morgan Lewis & Bockius LLP

20080213929 - Light emitting device: An objective is to increase the reliability of a light emitting device structured by combining TFTs and organic light emitting elements. A TFT (1201) and an organic light emitting element (1202) are formed on the same substrate (1203) as structuring elements of a light emitting device (1200). A first insulating... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080213931 - Light emitting device: A light emitting device includes a laminate of a lower electrode layer, an organic light-emitting layer, and an upper transparent electrode layer. In the light emitting device, an auxiliary electrode layer is formed of colloidal nano-sized particles of a conductive metal between the lower electrode layer and the organic light-emitting... Agent: Brinks Hofer Gilson & Lione

20080213932 - Method of improving the flatness of a microdisplay surface and method of manufacturing liquid crystal on silicon (lcos) display panel the same: A method of improving the flatness of a microdisplay surface is disclosed. A reflective mirror layer and a raised layer are formed in order on substrate. The raised layer may comprise a buffer layer and a stop layer, and pixel electrode areas are defined therefrom and gaps are consequently formed... Agent: North America Intellectual Property Corporation

20080213933 - Methods of fabricating a large area transducer array: Methods of fabricating a tiled transducer array are disclosed. Embodiments of the methods include fabricating a wafer comprising a plurality of transducers, dicing the wafer to form individual transducers, testing the individual transducers to identify a plurality of known good transducers, preparing a substrate having a front side and a... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20080213934 - Integrated device manufacturing process: A process for manufacturing an integrated device includes the steps of: providing a silicon substrate on which a silicon dioxide structure is arranged; and forming a trench having first and second essentially vertical walls relative to the substrate in the structure by means of anisotropic-type etching. A concavity having a... Agent: Hogan & Hartson LLP

20080213936 - Alignment mark forming method, alignment method, semiconductor device manufacturing method, and solid-state image capturing apparatus manufacturing method: An alignment mark forming method according to the present invention includes: an alignment mark forming step of using an impurity implantation region as an alignment target layer and using, as a mask, the same resist film used for forming the impurity implantation region to form an alignment mark that is... Agent: Edwards Angell Palmer & Dodge LLP

20080213935 - Manufacturing method of solid-state imaging device: Provided is a manufacturing method of a CCD solid-state imaging device having such an impurity concentration distribution with which shading is reduced and formation of a buried channel endowed with a large saturation signal charge amount is made possible. The manufacturing method includes: an oxide layer forming step of forming... Agent: Mcdermott Will & Emery LLP

20080213937 - Method of fabricating optical device caps: A wafer having a plurality of through holes is provided, and a glass wafer is disposed on the wafer. A plate having a plurality of concave cavities is disposed on the glass wafer, wherein the concave cavities corresponding to the through holes of the wafer so that a part of... Agent: North America Intellectual Property Corporation

20080213938 - Method for fabricating a cmos image sensor: A method for fabricating a CMOS image sensor is disclosed. First, a substrate having a sensor array region and a peripheral region is provided. A contact pad is formed on the substrate of the peripheral region, and a dielectric layer is disposed on the substrate for exposing the surface of... Agent: North America Intellectual Property Corporation

20080213939 - Solid-state imaging device and method for producing the same: In a solid-state imaging device, a light-shielding film 10a is formed of at least one of a high melting point metal film or a high melting point metal compound film. The surface of the light-shielding film 10a is constituted by an amorphous silicon film 13. Instead of the amorphous silicon... Agent: Mcdermott Will & Emery LLP

20080213940 - Methods of forming metal oxide layers, methods of forming gate structures using the same, and methods of forming capacitors using the same: Provided herein are methods of forming a metal oxide layer that include providing an organometallic compound and an oxidizing agent to the substrate to form the metal oxide layer on the substrate. The organometallic compound may have the general formula of M(NR1R2)3R3, wherein M is a metal; R1 and R2... Agent: Myers Bigel Sibley & Sajovec

20080213941 - Bump-on-lead flip chip interconnection: A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die... Agent: Quarles & Brady LLP

20080213942 - Method for fabricating semiconductor device and carrier applied therein: This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into... Agent: Edwards Angell Palmer & Dodge LLP

20080213944 - Structure combining an ic integrated substrate and a carrier, and method of manufacturing such structure: The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer... Agent: Madson & Austin

20080213943 - Thermosetting die bonding film: The thermosetting die bonding film of the invention is a thermosetting die bonding film used to produce a semiconductor device, which contains, as main components, 5 to 15% by weight of a thermoplastic resin component and 45 to 55% by weight of a thermosetting resin component, and has a melt... Agent: Knobbe Martens Olson & Bear LLP

20080213945 - Semiconductor device and fabrication process thereof: A semiconductor device includes a mount substrate and a semiconductor chip mounted upon the mount substrate via a metal bump, wherein metal bump includes an inner part joined to the semiconductor chip and an outer part covering the inner part, the outer part having an increased hardness as compared with... Agent: Kratz, Quintos & Hanson, LLP

20080213946 - Substrate based unmolded package: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the... Agent: Townsend And Townsend And Crew, LLP

20080213947 - Resin encapsulation molding method for semiconductor device: According to a resin encapsulation molding method for a semiconductor device, a resin-encapsulated substrate having a semiconductor device that is mounted on the substrate and that has a portion exposed is formed. With the method, a device-mounted substrate on which the semiconductor device is mounted is prepared and then the... Agent: Birch Stewart Kolasch & Birch

20080213948 - Dual wired integrated circuit chips: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side... Agent: Schmeiser, Olsen & Watts

20080213949 - Method for manufacturing array substrate: A method for manufacturing a substrate for a flat panel display device is disclosed. The present method uses photolithography with four masks to manufacture a TFT-LCD. After the third half-tone mask is used, the manufacturing of the TFTs and the defining of the pixel area of the substrate can be... Agent: Bacon & Thomas, PLLC

20080213950 - Array substrate for a liquid crystal display and method for fabricating thereof: An array substrate for a liquid crystal display device includes a substrate, a plurality of thin film transistors formed on the substrate, each thin film transistor includes a gate electrode, a first gate insulation layer, a second gate insulation layer, an active layer, an ohmic contact layer, a source electrode... Agent: Mckenna Long & Aldridge LLP

20080213951 - Method of fabricating pixel structure: A method of fabricating a pixel structure including the following procedures is provided. First, a substrate having an active device thereon is provided. A patterned passivation layer is formed on the substrate and the active device, and the patterned passivation layer exposes a portion of the active device. Then, a... Agent: Jianq Chyun Intellectual Property Office

20080213952 - Shallow trench isolation process and structure with minimized strained silicon consumption: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box... Agent: Amd-mke C/o Foley Lardner LLP

20080213953 - Method of manufacturing a semiconductor device: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the... Agent: Eric Robinson

20080213954 - Semiconductor device and manufacturing method thereof: A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further... Agent: Fish & Richardson P.C.

20080213955 - Schottky diode with minimal vertical current flow: A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second... Agent: Texas Instruments Incorporated

20080213956 - Field effect transistor device including an array of channel elements: The present invention relates to a semiconductor structure such as a field effect transistors (FETs) in which the channel region of each of the FETs is composed of an array of more than one electrically isolated channel. In accordance with the present invention, the distance between each of the channels... Agent: Scully, Scott, Murphy & Presser, P.C.

20080213957 - Integrated circuit with multi-length output transistor segments: A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the... Agent: The Law Offices Of Bradley J. Bereznak

20080213958 - Capacitor structure and fabricating method thereof: Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080213959 - Non-volatile memory (nvm) retention improvement utilizing protective electrical shield: An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material... Agent: Stallman & Pollock LLP

20080213960 - Method of producing a semiconductor device having a trench-stuffed layer: A semiconductor device includes a first conductivity type semiconductor substrate. A first conductivity type drift layer is formed on a surface of the first conductivity type semiconductor substrate, and a second conductivity type base region is produced in the first conductivity type drift layer. The second conductivity type base region... Agent: Young & Thompson

20080213961 - Process for manufacturing a tft device with source and drain regions having gradual dopant profile: Process for realizing TFT devices on a substrate which comprises the steps of: forming on the substrate, in cascade, an amorphous silicon layer and a heavily doped amorphous silicon layer, forming a photolithographic mask on the heavily doped amorphous silicon layer provided with an opening, removing the heavily doped amorphous... Agent: Seed Intellectual Property Law Group PLLC

20080213962 - Strained silicon with elastic edge relaxation: A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are... Agent: Hogan & Hartson L.L.P.

20080213963 - Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same: A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the... Agent: Martine Penilla & Gencarella, LLP

20080213964 - Field effect transistor with thin gate electrode and method of fabricating same: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the... Agent: Schmeiser, Olsen & Watts

20080213965 - Method for manufacturing dmos device: A method for manufacturing a semiconductor device is provided. The semiconductor device may be a drain extended metal-oxide-semiconductor (DMOS) device. The method includes: forming a gate insulating film on a semiconductor substrate having an active region; forming a gate on the gate insulating film; forming a low-concentration source region and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080213966 - Inductor embedded in substrate, manufacturing method thereof, micro device package, and manufacturing method of cap for micro device package: An inductor embedded in a substrate, including a substrate, a coil electrode formed by filling a metal in a spiral hole formed on the substrate, an insulation layer formed on the substrate, and an external connection pad formed on the insulation layer to be connected to the coil electrode. The... Agent: Sughrue Mion, PLLC

20080213967 - Trench capacitor and method for manufacturing the same: Method of manufacturing a trench capacitor includes providing a substrate having a memory array region and a logic region, performing a shallow trench isolation (STI) process for forming at least a STI in the substrate within each of the memory array regions and the logic regions, forming a patterned hard... Agent: North America Intellectual Property Corporation

20080213968 - Method for fabricating capacitor: A method for fabricating a capacitor includes firstly providing a substrate. A doped first dielectric layer and an undoped second dielectric layer are then formed on the substrate sequentially. Next, many trenches are formed in the first and the second dielectric layers. Afterwards, an ion implantation process is performed in... Agent: J C Patents, Inc.

20080213969 - Method of forming isolation layer in semiconductor device: The present invention is related to a method of forming an isolation layer in a semiconductor device and comprises the steps of forming a tunnel insulating layer and conductive layer patterns on an active area of a semiconductor substrate, the width of an upper portion of the conductive layer patterns... Agent: Marshall, Gerstein & Borun LLP

20080213970 - Process for the formation of dielectric isolation structures in semiconductor devices: A process for forming a dielectric isolation structure on a silicon substrate includes forming at least one trench in the substrate, performing a high-temperature treatment in an oxidizing environment to form a first liner layer of silicon dioxide on the walls and the bottom of the trench, and performing a... Agent: Christopher F. Regan, Esquire

20080213971 - Semiconductor device having dual-sti and manufacturing method thereof: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a... Agent: Mcmermott Will & Emery LLP

20080213972 - Processes for forming isolation structures for integrated circuit devices: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated... Agent: Patentability Associates

20080213973 - Method of fabricating a substrate for a planar, double-gated, transistor process: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate... Agent: Freescale Semiconductor, Inc. Law Department

20080213974 - Method of manufacturing bonded wafer: The present invention provides a method of manufacturing a bonded wafer. The method comprises an oxidation step in which an oxide film is formed on at least one surface of a base wafer, a bonding step in which the base wafer on which the oxide film has been formed is... Agent: Greenblum & Bernstein, P.L.C

20080213976 - Methods for fabricating semiconductor components and packaged semiconductor components: Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall... Agent: Perkins Coie LLP Patent-sea

20080213975 - Supply mechanism for the chuck of an integrated circuit dicing device: A system for dicing substrates to singulate integrated circuit units within in them includes a dicing machine (Z) which operates with a chuck table (4). A lifting assembly (Ax,Ay) deposits substrates to be singulated onto the chuck table (4) at substantially the same time as it removes previously singulated units... Agent: Dickstein Shapiro LLP

20080213977 - Vacuum expansion of integrated circuits at sort: A frame and vacuum expansion chuck are used in combination for stretching a tape carrying a plurality of singulated devices to facilitate removal of the devices with reduced risk of contact between a device being removed from the tape and an adjacent device on the tape. The combination includes a... Agent: Delphi Technologies, Inc.

20080213978 - Debris management for wafer singulation: The present invention discloses methods and apparatuses for substrate singulation. Embodiments of the present invention comprise cryogenic-assist scribing or cutting mechanism for debris reduction, preferably cryogenic-assist laser scribe or cutting; controlling mechanism for debris flow and redeposition during laser process; and integrated, dry debris removal scribing process with breaking mechanism.... Agent: Tue Nguyen

20080213979 - Method and apparatus for breaking semiconductor substrate, method for breaking solar cell and method for fabrication of solar cell module: A method and apparatus for breaking a semiconductor substrate along a predetermined area over which a split groove is formed. The breaking apparatus includes a table for placing a portion of the semiconductor substrate inside the predetermined area and a breaking blade being operable to move downward from a position... Agent: Ditthavong Mori & Steiner, P.C.

20080213980 - Process applied to semiconductor: A process applied to grinding, dicing, and/or stacking semiconductors is disclosed. One of its features is that after transparent material is stuck on its active surface, a semiconductor is ground from another surface thereof to become thinner, then take advantage of transparency of the transparent material to cut the transparent... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080213981 - Method of fabricating a silicon-on-insulator structure: In the field of sensor fabrication, it is known to form a silicon-on-insulator starting structure from which fabrication of the sensor based. The present invention provides a method of forming a silicon-on-insulator structure comprising a substrate having an insulating layer patterned thereon. A silicon oxide layer is then deposited over... Agent: Freescale Semiconductor, Inc. Law Department

20080213982 - Method of fabricating semiconductor wafer: Provided is a method of fabricating a semiconductor wafer. The method includes preparing a substrate wafer having a non-single-crystalline thin layer; disposing at least one single crystalline pattern adjacent to the non-single-crystalline thin layer on the substrate wafer; and forming a material layer contacting the single crystalline pattern on the... Agent: Myers Bigel Sibley & Sajovec

20080213983 - Method for manufacturing semiconductor device: Method for manufacturing a semiconductor device including a transistor having a grooved gate structure and a transistor having a planar gate structure on the same substrate, in which, even when the semiconductor device is configured as a dual gate structure in which a gate electrode structure is a poly-metal gate... Agent: Young & Thompson

20080213986 - Laser annealing method and laser annealing device: In order to promote an effect of laser annealing in respect of a semiconductor film, moisture is intentionally included in an atmosphere in irradiating laser beam to the semiconductor film by which a temperature holding layer comprising water vapor is formed on the surface of the semiconductor film in irradiating... Agent: Fish & Richardson P.C.

20080213984 - Manufacturing method of semiconductor device: A cap film is formed over semiconductor films formed over an insulating substrate; the semiconductor films are irradiated with a laser beam which is capable of completely melting the semiconductor film in a film-thickness direction to completely melt the semiconductor film. By controlling the laser beam, a crystalline semiconductor films... Agent: Nixon Peabody, LLP

20080213985 - Method of forming polycrystalline silicon thin film and method of manufacturing thin film transistor using the method: Provided is a method of forming a polycrystalline silicon thin film with improved electrical characteristics. The method includes forming an amorphous silicon thin film on a substrate, partially melting a portion of the amorphous silicon thin film by irradiating the portion of the amorphous silicon thin film with a laser... Agent: Macpherson Kwok Chen & Heid LLP

20080213987 - Method of fabricating a sige semiconductor structure: A method of fabricating an integrated circuit includes providing a substrate and creating base-windows in a layer. The method also includes forming a monocrystalline SiGe base layer in each of the base layers, and polycrystalline SiGe elsewhere. Additionally, the method also includes forming a monocrystalline silicon layer over selectively exposed... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080213989 - Silicon wafer for manufacturing soi wafer, soi wafer, and method for manufacturing soi wafer: A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080213988 - Substrate heating apparatus and semiconductor fabrication method: A substrate heating apparatus having a heating unit for heating a substrate placed in a process chamber which can be evacuated includes a suscepter which is installed between the heating unit and a substrate, and on which the substrate is mounted, and a heat receiving member which is installed to... Agent: Fitzpatrick Cella Harper & Scinto

20080213990 - Method for forming gate electrode in semiconductor device: A method for forming a gate electrode in a semiconductor device includes providing a substrate, forming a gate insulation layer over the substrate, forming first and second conductive layers over the gate insulation layer, forming a hard mask pattern over the second conductive layer, etching the second conductive layer using... Agent: Lowe Hauptman Ham & Berner, LLP

20080213991 - Method of forming plugs: The present invention is a method of forming plugs for engaging with a socket on a substrate having pads thereon. The method including the steps of forming an insulation layer on the substrate, patterning the insulation layer to form openings for exposing the pads by a wet etching, respectively, forming... Agent: Joe Mckinney Muncy

20080213992 - Semiconductor package having enhanced heat dissipation and method of fabricating the same: A semiconductor package comprising a semiconductor chip and a first heat spreader adhered to the upper surface of the semiconductor chip is provided. The first heat spreader comprises a flat metal plate and a plurality of metal balls adhered to the flat metal plate. A method of fabricating the semiconductor... Agent: Volentine & Whitt PLLC

20080213993 - Method and apparatus of stress relief in semiconductor structures: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar... Agent: F. Chau & Associates, LLP

20080213994 - Treating a liner layer to reduce surface oxides: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ... Agent: Trop Pruner & Hu, PC

20080213996 - Designs and methods for conductive bumps: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The... Agent: Fish & Richardson, PC

20080213998 - Method for manufacturing semiconductor device, semiconductor manufacturing apparatus and storage medium for executing the method: The semiconductor device manufacturing method includes forming an alloy film of copper and an additive metal along a wall surface of a recess portion of an interlayer insulating film in a surface of a substrate; forming a barrier layer made of a compound of the additive metal and a constituent... Agent: Pearne & Gordon LLP

20080213997 - Selective copper-silicon-nitride layer formation for an improved dielectric film/copper line interface: A process to form a copper-silicon-nitride layer on a copper surface on a semiconductor wafer is described. The process may include the step of exposing the wafer to a first plasma made from helium. The process may also include exposing the wafer to a second plasma made from a reducing... Agent: Townsend And Townsend And Crew LLP / Amat

20080213995 - Ultrasonic electropolishing of conductive material: In one embodiment, the present invention includes a method for forming a dielectric layer on a semiconductor wafer and patterning at least one opening in the dielectric layer, depositing a barrier layer over the dielectric layer, depositing a conductive layer over the barrier layer, and electropolishing the conductive layer while... Agent: Trop Pruner & Hu, PC

20080213999 - Compositions and methods for forming and depositing metal films on semiconductor substrates using supercritical solvents: Compositions and methods for depositing elemental metal M(0) films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing a metal precursor, an excess amount of neutral labile ligands, and... Agent: Buchanan, Ingersoll & Rooney PC

20080214000 - Polishing composition and polishing method using the same: The present invention relates to a polishing composition more suitable for application in polishing semiconductor devices. The polishing composition consists of a liquid component including water and water-soluble amine. The water-soluble amine includes at least one of triethylenetetramine (TETA) and tetraethylenepentamine (TEPA) and is dissolved in the water.... Agent: Vidas, Arrett & Steinkraus, P.A.

20080214001 - Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same: The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In some embodiments, the metal-containing compounds are homoleptic complexes that include unsymmetrical β-diketiminate ligands. In other embodiments, the metal-containing compounds are heteroleptic complexes including at least one β-diketiminate ligand.... Agent: Mueting, Raasch & Gebhardt, P.A.

20080214002 - Cleaning solution and manufacturing method for semiconductor device: A method of manufacturing a semiconductor device forms an interlayer insulating film on a nickel silicide layer formed on a substrate, and forms a through hole by performing dry etching using a resist pattern, formed on the interlayer insulating film, as a mask and then removing the resist pattern by... Agent: Young & Thompson

20080214003 - Methods for forming a ruthenium-based film on a substrate: Methods for forming a film on a substrate in a semiconductor manufacturing process A reaction chamber a substrate in the chamber are provided. A ruthenium based precursor, which includes ruthenium tetroxide dissolved in a mixture of at least two non-flammable fluorinated solvents, is provided and a ruthenium containing film is... Agent: Air Liquide Intellectual Property

20080214004 - Method for manufacturing a semiconductor device and semiconductor device: A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer... Agent: Dicke, Billig & Czaja

20080214005 - Chemical solution feeding apparatus and method for preparing slurry: An apparatus for feeding slurry to an external device. The apparatus includes a preparation tank for preparing the slurry. A circulation pipe is connected to the preparation tank to circulate the slurry. A feeding pipe is connected between the preparation tank and the external device to feed the external device... Agent: Kratz, Quintos & Hanson, LLP

20080214006 - Methods of using corrosion-inhibiting cleaning compositions for metal layers and patterns on semiconductor substrates: Provided herein are methods for using corrosion-inhibiting cleaning compositions for semiconductor wafer processing that include an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids. The quantity of the corrosion-inhibiting compound in the admixture is... Agent: Myers Bigel Sibley & Sajovec

20080214007 - Method for removing diamond like carbon residue from a deposition/etch chamber using a plasma clean: Provided is a method for removing diamond like carbon residue from a deposition chamber. This method, in one embodiment, may include subjecting a deposition chamber including diamond like carbon residue to a plasma clean in the presence of fluorine containing gas and oxygen containing gas. The method may further include... Agent: Texas Instruments Incorporated

20080214008 - Method of manufacturing semiconductor device: In a method of manufacturing a semiconductor device, a plurality of structures are formed on a substrate, and a coating film is formed over a whole surface of the substrate to cover the plurality of structures. A photoresist layer is formed to have an opening portion above a target structure... Agent: Young & Thompson

20080214009 - Methods of forming a recess structure and methods of manufacturing a semiconductor device having a recessed-gate structure: Methods of forming a recess structure having a gentle curvature are provided. Such methods include forming a hard mask on a substrate, forming a first preliminary recess on the substrate using the hard mask as an etching mask and forming a spacer on a sidewall of the first preliminary recess.... Agent: Myers Bigel Sibley & Sajovec

20080214010 - Semiconductor device fabrication method and pattern formation mold: According to the present invention, there is provided a semiconductor device fabrication method comprising, bringing a mold having a predetermined pattern into contact with at least a portion of an imprinting material formed on a substrate to be processed, and forming the pattern on the substrate to be processed by... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080214011 - Method for fabricating dual damascene structures: A method for fabricating a dual damascene structure includes providing a multi-layer photoresist stack comprising a first photoresist layer and a second photoresist layer, wherein each photoresist layer has a distinct dose-to-clear value, exposing said photoresist stack to one or more predetermined patterns of light, and developing said photo-resist layers... Agent: Frank Chau, Esq. F.chau & Associates, LLC

20080214012 - Apparatus and method for fabricating semiconductor devices and substrates: An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower... Agent: Harness, Dickey & Pierce, P.L.C

20080214013 - Method for removal of bulk metal contamination from iii-v semiconductor substrates: The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080214014 - Absorber layer candidates and techniques for application: The present invention generally provides an absorber layer using carbon based materials with increased and stabled thermal absorption coefficient and economical methods to produce such an absorber layer. One embodiment of the present invention provides a method for processing a substrate comprising depositing an absorber layer on a top surface... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080214015 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a semiconductor device includes providing a workpiece, and forming a dielectric material over the workpiece. Forming the dielectric material includes forming a first layer of a first material and forming a second layer of... Agent: Slater & Matsil LLP

20080214016 - Process for reactive ion etching a layer of diamond like carbon: Provided is a process for manufacturing a diamond like carbon layer. The process for manufacturing the diamond like carbon layer includes, without limitation, forming a layer of diamond like carbon over a substrate, and reactive ion etching the layer of diamond like carbon.... Agent: Texas Instruments Incorporated

20080214017 - Forming method and forming system for insulation film: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.... Agent: Crowell & Moring LLP Intellectual Property Group

20080214018 - Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same: A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the... Agent: Ladas & Parry LLP

20080214019 - Method of manufacturing oxide film and method of manufacturing semiconductor device: A method of manufacturing an oxide film includes jetting onto a substrate a high-pressure solution containing an oxygen source and having a pressure of 5 MPa, and forming an oxide film on the substrate using the jetted high-pressure solution.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080214020 - Manufacturing method of semiconductor device subjected to heat treatment by use of optical heating apparatus: An auxiliary heating process is performed to set the temperature of the outer peripheral portion of a semiconductor substrate higher than that of the central portion thereof by use of an auxiliary heating source which supplementally heats a region of an area smaller than the area of the main surface... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080214021 - Method of crystallizing semiconductor film and method of manufacturing semiconductor device: It is an object of the present invention to align the plane orientations of crystal grains of a semiconductor film crystallized by irradiation with a linear laser beam with a width of less than or equal to 5 μm. By performing irradiation with the linear laser beam condensed by an... Agent: Nixon Peabody, LLP