Semiconductor device manufacturing: process inventions 08/08

20080206895 - Magnetic random access memory and method of manufacturing the same: A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080206896 - Method for repairing liquid crystal display panel: Provided is a method for repairing a LCD panel. An opaque substance is disposed within a region on the thin film transistor panel of LCD panel corresponding to at least one pixel with the bright spot defect before forming a cell, or within a region on the LCD panel corresponding... Agent: Sheridan Ross Pc

20080206899 - Method of manufacturing semiconductor device using electrochemical deposition with electric current revised by reflectance of every substrate surface and semiconductor manufacturing apparatus: A method of manufacturing a semiconductor device includes measuring the reflectance at the surface of a semiconductor substrate provided with concave portions and deciding a deposition parameter that represents a deposition condition corresponding to the measured reflectance. Then, a metal film is formed on the semiconductor substrate under a condition... Agent: Mcginn Intellectual Property Law Group, Pllc

20080206898 - Pattern monitor mark and monitoring method suitable for micropattern: A method of forming a monitor mark includes forming an insulating film on a semiconductor substrate, and forming a first repetitive line pattern group and a second repetitive line pattern group by patterning the insulating film on the semiconductor substrate, such that the first repetitive line pattern group and the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080206897 - Selective depth optical processing: Methods for processing semiconductor materials and substrates with a focused or collimated light beam. Light may be directed on a sample to alter material properties at a depth below the surface. The focused light beam has a peak power density positioned at a selected depth, and absorption of light energy,... Agent: Macpherson Kwok Chen & Heid LLP

20080206900 - Pulsed-plasma system for etching semiconductor structures: A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short... Agent: Applied Materials/blakely

20080206901 - Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductor structures: A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination... Agent: Applied Materials/blakely

20080206903 - Adaptive threshold wafer testing device and method thereof: Techniques for testing a semiconductor wafer are disclosed. One technique includes measuring a parameter for each of the semiconductor dies in a region of the wafer and determining an adaptive threshold for the region based on the measured parameters. The parameter measured for each die in the region is then... Agent: Larson Newman Abel Polansky & White, LLP

20080206902 - Stress measurements during large-mismatch epitaxial processes: A substrate is disposed within a processing chamber. A nitrogen precursor and a group-III precursor are flowed into the processing chamber. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process at an elevated temperature within the processing chamber using the nitrogen precursor and the group-III precursor. Light... Agent: Townsend And Townsend And Crew LLP / Amat

20080206904 - Method of making pcb circuit modification from multiple to individual chip enable signals: A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the... Agent: Vierra Magen/sandisk Corporation

20080206906 - Method of manufacturing nitride semiconductor device including sic substrate and apparatus for manufacturing nitride semiconductor device: Excitation light is irradiated onto a GaN layer on a silicon carbide substrate constituting a layered product that is set on a stage. Then light is emitted from a defective part caused by a structural defect of the silicon carbide substrate out of the GaN layer. By using this light... Agent: Venable LLP

20080206905 - Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies: During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch... Agent: Williams, Morgan & Amerson

20080206907 - Method for fabricating semiconductor device to which test is performed at wafer level and apparatus for testing semiconductor device: A method for fabricating a semiconductor device includes placing a semiconductor wafer on a stage, the semiconductor wafer having a plurality of ball-shaped external connecting terminals projected from a surface, bringing a probe card close to the semiconductor wafer placed on the stage to bring a plurality of probe terminals... Agent: Sprinkle Ip Law Group

20080206908 - Semiconductor device test structures and methods: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive feature disposed between the stress line and the feed line. The test structure includes a temperature adjuster proximate at least... Agent: Slater & Matsil LLP

20080206909 - Composition of carbon nitride, thin film transistor with the composition of carbon nitride, display device with the thin film transistor, and manufacturing method thereof: Consequently, a composition including carbon nitride according to the present invention is formed at a deposition temperature that enables to include hydrogen in the composition at 30 to 45 atomic %, for example, at temperatures of 100° C. or less, preferably 50° C. or less, more preferably from 20° C.... Agent: Eric Robinson

20080206910 - Luminescent sheet covering for leds: A lighting apparatus comprising at least one light emitting diode is disposed on an interconnect board to emit ultraviolet or blue radiation. A polymeric layer including a luminophor is disposed about the lighting apparatus to convert at least a portion of the radiation emitted from the LED into visible light.... Agent: Fay Sharpe LLP

20080206912 - Array substrate, method of manufacturing the same and method of crystallizing silicon: An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in... Agent: Cantor Colburn, LLP

20080206911 - Method of manufacturing liquid crystal display: A method of manufacturing a liquid crystal display includes depositing a transparent conductive layer on a substrate, depositing a reflective conductive layer on the transparent conductive layer, forming a first photoresist film having a variable thickness on the reflective conductive layer, the variable thickness of the first photoresist film varying... Agent: Cantor Colburn, LLP

20080206913 - Cleaving edge-emitting lasers from a wafer cell: In one example embodiment, a process for cleaving a wafer cell includes several acts. First a wafer cell is affixed to an adhesive film. Next, the adhesive film is stretched substantially uniformly. Then, the adhesive film is further stretched in a direction that is substantially orthogonal to a predetermined reference... Agent: Workman Nydegger

20080206915 - Manufacturing method for display device: With an interconnected fabrication step using the prior art photolithography, major portions of resist, interconnected material, and process gas necessary during plasma processing are wasted. Furthermore, a pumping means such as a vacuum system is necessary. Therefore, the whole equipment is increased in size. Consequently, as the processed substrate is... Agent: Nixon Peabody, LLP

20080206914 - Patterning self-aligned transistors using back surface illumination: Fabrication methods for making thin film devices on transparent substrates are described. Gate, source, and drain electrodes of a transistor are formed on a transparent substrate. The widths of the drain electrode and source electrodes are greater than a width of the gate electrode. A dielectric layer is formed on... Agent: Hollingsworth & Funk, Llc Suite 125

20080206916 - Solar cell and method and apparatus for manufacturing solar cell: A thin solar cell is provided, a decreased amount of an Al paste used for the solar cell without occurrence of a problem of ball-up which is a defect in appearance. A method of manufacturing such a solar cell as well as a manufacturing apparatus used therefor are provided. This... Agent: Nixon & Vanderhye, Pc

20080206918 - Image sensor package and forming method of the same: An image sensor package comprises a substrate, a chip mounted over the substrate. A molding material is formed surrounding the chip to expose a micron lens area, wherein the molding material includes via structure passing there through. A protection layer is formed on the micro lens area to prevent the... Agent: Kusner & Jaffe Highland Place Suite 310

20080206917 - Production of a radiation detector: The invention relates to a method of producing a radiation detector comprising a photosensitive receiver (1; 30; 41) associated with a radiation converter (5) which is fixed by bonding to the photosensitive receiver (1; 30; 41). The method uses a film of adhesive (6; 61; 62) protected on each of... Agent: Lowe Hauptman & Berner, LLP

20080206919 - Method of manufacture of a microlens structure for opto-electric semiconductor device: A semiconductor device includes a semiconductor material substrate, an opto-electric component formed on the substrate, and a first transparent layer formed on an upper surface of the substrate over the component, the layer having a planar upper surface with a cavity formed therein. The first transparent layer has a selected... Agent: Stmicroelectronics, Inc.

20080206922 - Methods for fabricating multi-terminal phase change devices: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created... Agent: Patent Law Professionals

20080206921 - Methods of forming phase changeable layers including protruding portions in electrodes thereof: A method of forming a structure in a phase changeable memory cell can include forming a bottom electrode having an interlayer dielectric layer thereon, the bottom electrode having a recess therein that extends beyond a boundary between the bottom electrode and the interlayer dielectric. A phase changeable layer can be... Agent: Myers Bigel Sibley & Sajovec

20080206920 - Pcram device with switching glass layer: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method.... Agent: Dickstein Shapiro LLP

20080206923 - Oxide semiconductor target, method of forming the same, method of forming oxide semiconductor layer using the same and method of manufacturing semiconductor device using the same: Provided are a method of forming an oxide semiconductor layer and a method of manufacturing a semiconductor device using the method of forming an oxide semiconductor layer. The method may include mounting an oxide semiconductor target in a chamber; loading a substrate into the chamber; vacuuming the chamber; applying a... Agent: Harness, Dickey & Pierce, P.L.C

20080206924 - Method for fabtricating semiconductor device: According to the second aspect of the present invention, a method for fabricating a semiconductor device with a silicon carbide (SiC) film is comprised of a process to grow a silicon carbide film on a substrate; and a process to form a groove on said silicon carbide film so that... Agent: Rabin & Berdo, Pc

20080206925 - Methods and apparatus to improve frit-sealed glass package: A hermetically sealed package includes: a first plate including inside and outside surfaces; a second plate including inside and outside surfaces; frit material disposed on the inside surface of the second plate; and at least one dielectric layer disposed directly or indirectly on at least one of: (i) the inside... Agent: Corning Incorporated

20080206926 - Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080206927 - Electronic component structure and method of making: An external component, typically a surface mount passive, is attached to a semiconductor die. In some embodiments the passive is placed directly over exposed pads on the semiconductor die and attached using conductive tape or conductive epoxy. In some embodiments the passive is attached to the semiconductor die using non-conductive... Agent: Marsh, Fischmann & Breyfogle LLP

20080206928 - Soldering method and method of manufacturing semiconductor device including soldering method: A soldering method of soldering first and second members includes shooting a laser light to at least one part of an outer peripheral portion surrounding a soldering-target region of the first member thereby to form an oxide film, and bonding the second member with the soldering-target region through a solder.... Agent: Rossi, Kimms & Mcdowell LLP.

20080206929 - Printing device, production unit, and production method of electronic parts: A printing device, a production unit and a production method of electronic parts suitable for production of precise electronic parts are provided. A squeegee is attached to a rotating machine, and is autorotated and self-driven, and moreover, a printing pressure is generated in the squeegee, and resin is strongly filled,... Agent: Weiner & Burt, P.c.

20080206930 - Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece: Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece are disclosed. A method in accordance with one aspect includes placing a semiconductor workpiece and an encapsulant in a mold cavity and driving some of the encapsulant from the mold cavity to an overflow chamber. The method can further... Agent: Perkins Coie LLP Patent-sea

20080206932 - Data line layout in semiconductor memory device and method of forming the same: In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n<m, and M=m+1, and... Agent: Volentine & Whitt Pllc

20080206931 - Nonvolatile memory element and production method thereof and storage memory arrangement: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080206934 - Forming semiconductor fins using a sacrificial fin: A semiconductor device is made by steps of removing portions of a first capping layer, removing portions of a sacrificial layer, recessing sidewalls, and forming fin structures. The step of removing portions of the first capping layer forms a first capping structure that covers portions of the sacrificial layer. The... Agent: Freescale Semiconductor, Inc. Law Department

20080206935 - Method for fabricating thin film transistor using local oxidation and transparent thin film transistor: The method comprises the steps of forming a gate electrode on a substrate and forming a gate insulating layer thereon, forming a transparent metal oxide layer on the gate insulating layer, forming an oxidation barrier layer on the transparent metal oxide layer in such a manner that a portion of... Agent: Ked & Associates, LLP

20080206936 - Method of forming conducting nanowires: A method of preparing an array of conducting or semi-conducting nanowires may include forming a vicinal surface of stepped atomic terraces on a substrate, and depositing a fractional layer of dopant material to form nanostripes having a width less than the width of the atomic terraces. Diffusion of the atoms... Agent: Foley Hoag, LLP Patent Group, World Trade Center West

20080206933 - Semiconductor fin integration using a sacrificial fin: There is a method for forming a semiconductor device. Portions of a sacrificial layer are removed to expose a first seed layer region. The first seed layer region corresponds to a first semiconductor region, and a remaining portion of the sacrificial layer corresponds to a second semiconductor region. An epitaxial... Agent: Freescale Semiconductor, Inc. Law Department

20080206937 - Wrap-around gate field effect transistor: A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080206938 - Low temperature polysilicon thin film transistor display and method of fabricating the same: A display comprises a substrate, a polysilicon layer which is crystallized by a solid phase crystallization (SPC) method, a gate dielectric layer made of silicon oxy-nitride (SiON) and formed on the polysilicon layer, and a gate electrode formed on the gate dielectric layer (i.e. SiON).... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080206940 - Forming a semiconductor device having epitaxially grown source and drain regions: A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is... Agent: Freescale Semiconductor, Inc. Law Department

20080206939 - Semiconductor device with integrated resistive element and method of making: A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively... Agent: Freescale Semiconductor, Inc. Law Department

20080206941 - Method for manufacturing sic semiconductor device: A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base region; forming a channel region on the base region... Agent: Posz Law Group, Plc

20080206942 - Method for fabricating strained-silicon metal-oxide semiconductor transistors: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing... Agent: North America Intellectual Property Corporation

20080206943 - Method of forming strained cmos transistor: A method of fabricating CMOS transistor is disclosed. Initially, a semiconductor substrate having at least a first active area and a second active area is provided. A high-strained thin film is formed on the semiconductor substrate, the first active area, and the second active area. Thereafter, a mask is formed... Agent: North America Intellectual Property Corporation

20080206944 - Method for fabricating trench dmos transistors and schottky elements: A method uses simplified processes to complete the forming of the trench DMOS transistors and Schottky contacts. In the processes, only four masks, i.e. a trench pattern mask, a contact-hole pattern mask, a P+ contact pattern mask and a conductive-wire pattern mask, are applied to create desired trench DMOS transistors.... Agent: Bacon & Thomas, Pllc

20080206945 - Process for forming differential spaces in electronics device integrated on a semiconductor substrate: A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first... Agent: Seed Intellectual Property Law Group Pllc

20080206946 - Memory and method of fabricating the same: A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell... Agent: Mcdermott Will & Emery LLP

20080206947 - Method of manufacturing semiconductor device: A method of manufacturing the semiconductor device is provided, which provides a prevention for a “dug” of a silicon substrate caused by the etching in regions except a region for forming a film during a removal of the film with a chemical solution. A method of manufacturing a semiconductor device... Agent: Young & Thompson

20080206948 - Semiconductor device and method of fabricating the same: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080206949 - Apparatus for forming conductor, method for forming conductor, and method for manufacturing semiconductor device: A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical... Agent: Christensen, O'connor, Johnson, Kindness, Pllc

20080206950 - Methods of forming a plurality of capacitors: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive... Agent: Wells St. John P.s.

20080206951 - High performance field effect transistors on soi substrate with stress-inducing material as buried insulator and methods: The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not... Agent: Scully, Scott, Murphy & Presser, P.c.

20080206952 - Silicon substrate processing method: In a thin film forming step S1, a thin film, having carbon as a main component, is formed on at least one principal surface of a silicon substrate. In a thin film partial removal step S2, of the thin film, a thin film portion at a partial region on the... Agent: Drinker Biddle & Reath (dc)

20080206953 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device having a silicon-on-insulator region and a bulk region in a same semiconductor substrate, the method including: (a) forming a protection film on the semiconductor substrate in the bulk region; (b) exposing a surface of the semiconductor substrate in the silicon-on-insulator region from under... Agent: Harness, Dickey & Pierce, P.L.C

20080206955 - Method of forming an isolation film in a semiconductor device: A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a... Agent: Marshall, Gerstein & Borun LLP

20080206954 - Methods of reducing impurity concentration in isolating films in semiconductor devices: A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper... Agent: Myers Bigel Sibley & Sajovec

20080206956 - Semiconductor device fabrication method: A method for fabricating a semiconductor device, includes forming a silicon nitride film on a base body, forming a silicon film on said silicon nitride film, forming at least one groove extending from said silicon film to inside of said base body, forming by high-density plasma-enhanced chemical vapor deposition a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080206957 - Method of forming isolation layer of semiconductor memory device: The present invention relates to a method of forming an isolation layer of a semiconductor memory device. After a trench is formed by etching a semiconductor substrate, a liner insulating film is formed from a DCS-HTO material having a similar wet etch rate to that of a PSZ film that... Agent: Marshall, Gerstein & Borun LLP

20080206958 - Enhancement of electron and hole mobilities in <110> si under biaxial compressive strain: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress... Agent: Scully, Scott, Murphy & Presser, P.c.

20080206959 - Peeling method: A peeling method is provided which does not cause damage to a layer to be peeled, and the method enables not only peeling of the layer to be peeled having a small area but also peeling of the entire layer to be peeled having a large area at a high... Agent: Eric Robinson

20080206960 - Reworkable chip stack: A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within... Agent: Cantor Colburn LLP-ibm Yorktown

20080206961 - Semiconductor device and semiconductor substrate: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a... Agent: Mattingly, Stanger, Malur & Brundidge, P.c.

20080206963 - Cleaving process to fabricate multilayered substrates using low implantation doses: A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave... Agent: Townsend And Townsend And Crew, LLP

20080206962 - Method and structure for thick layer transfer using a linear accelerator: A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes... Agent: Townsend And Townsend And Crew, LLP

20080206964 - Carbon nanotube transistor process with transferred carbon nanotubes: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the... Agent: Aka Chan LLP

20080206965 - Strained silicon made by precipitating carbon from si(1-x-y)gexcy alloy: Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used... Agent: Cantor Colburn LLP-ibm Yorktown

20080206967 - Method for forming semiconductor device: A thin semiconductor film is crystallized in a high yield by being irradiated with laser light. An insulating film, a semiconductor film, an insulating film, and a semiconductor film are stacked in this order over a substrate. Laser light irradiation is performed from above the substrate to melt the semiconductor... Agent: Nixon Peabody, LLP

20080206966 - Quantum dots nucleation layer of lattice mismatched epitaxy: Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of... Agent: Mh2 Technology Law Group, LLP

20080206968 - Manufacturing method of semiconductor device: To create a laminated film of a silicon oxide film and a silicon nitride film, with large current driving force and large dielectric constant. A manufacturing method of a semiconductor device includes: forming an amorphous silicon film on the silicon oxide film; and forming a single crystal silicon film by... Agent: Oliff & Berridge, Plc

20080206969 - Laser optical apparatus: In a multi-cylindrical lens (a glass substrate having a multiplicity of cylindrical lenses formed thereon) used in a homogenizer, convex cylindrical lenses and concave cylindrical lenses are arranged alternately, and the boundaries between the cylindrical lenses have a smooth structure. This makes it possible to reduce scattering of beams that... Agent: Fish & Richardson P.c.

20080206970 - Production of polycrystalline silicon: Polysilicon is deposited onto a tube or other hollow body. The hollow body replaces the slim rod of a conventional Siemens-type reactor and may be heated internally with simple resistance elements. The hollow body diameter is selected to provide a surface area much larger than that of a silicon slim... Agent: Klarquist Sparkman, LLP

20080206971 - Divergent charged particle implantation for improved transistor symmetry: The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles (320) to a substrate (330), the beam of charged particles... Agent: Texas Instruments Incorporated

20080206972 - Doped nanoparticle-based semiconductor junction: A doped semiconductor junction for use in an electronic device and a method for making such junction is disclosed. The junction includes a first polycrystalline semiconductor layer doped with donors or acceptors over a substrate such that the first doped semiconductor layer has a first polarity, the first layer including... Agent: Patent Legal Staff

20080206973 - Process method to optimize fully silicided gate (fusi) thru pai implant: An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming oxide and nitride etch-stop layers over a top portion of the gates of the NMOS and PMOS transistors, forming a... Agent: Texas Instruments Incorporated

20080206974 - Fabrication of semiconductor device having composite contact: A method of fabricating a semiconductor device with a composite contact is provided. The fabrication includes forming the composite contact to a semiconductor layer in a semiconductor structure. The composite contact is formed by forming a DC conducting electrode attached to a semiconductor layer in a semiconductor structure and forming... Agent: Hoffman Warnick Llc

20080206975 - Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080206976 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080206977 - Methods of forming wiring to transistor and related transistor: Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including... Agent: Hoffman Warnick Llc

20080206978 - Electronic fuses in semiconductor integrated circuits: A structure fabrication method. The method includes providing a structure. The structure includes (a) a substrate layer, (b) a first fuse electrode in the substrate layer, and (c) a fuse dielectric layer on the substrate layer and the first fuse electrode. The method further includes (i) forming an opening in... Agent: Schmeiser, Olsen & Watts

20080206979 - Interconnections for flip-chip using lead-free solders and having reaction barrier layers: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally... Agent: David Aker

20080206980 - Method for manufacturing semiconductor device, and method and structure for implementing semiconductor device: A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the... Agent: Harness, Dickey & Pierce, P.L.C

20080206981 - Semiconductor device and manufacturing method therefor: In a manufacturing method for a semiconductor storage device, an interlayer insulating film, a first hard mask made of an insulative material for coating the interlayer insulating film and a second hard mask are formed on a substrate. The second hard mask is opened, and with use of the second... Agent: Harness, Dickey & Pierce, P.L.C

20080206982 - Interconnect structures with a metal nitride diffusion barrier containing ruthenium and method of forming: A method for forming an interconnect structure for copper metallization and an interconnect structure containing a metal nitride diffusion barrier are described. The method includes providing a substrate having a micro-feature opening formed within a dielectric material and forming a metal nitride diffusion barrier containing ruthenium, nitrogen, and a nitride-forming... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080206983 - Method of manufacturing photoelectric conversion device: The present invention is a method of manufacturing a photoelectric conversion device having a multilayered interconnection (wiring) structure disposed on a semiconductor substrate, including steps of forming a hole in a region of the interlayer insulation film corresponding to an electrode of the transistor; burying an electroconductive substance in the... Agent: Fitzpatrick Cella Harper & Scinto

20080206984 - Conductive via formation utilizing electroplating: A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor... Agent: Freescale Semiconductor, Inc. Law Department

20080206985 - Method of fabricating a semiconductor device: Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A... Agent: Harness, Dickey & Pierce, P.L.C

20080206986 - Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.c.

20080206987 - Process for tungsten nitride deposition by a temperature controlled lid assembly: Embodiments of the invention provide processes for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a method for forming a tungsten-containing material is provided which includes positioning a substrate within a processing chamber containing a lid plate, heating the lid plate to a temperature... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080206988 - Formation of fully silicided gate with oxide barrier on the source/drain silicide regions: A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide... Agent: Texas Instruments Incorporated

20080206989 - Method for producing vertical electrical contact connections in semiconductor wafers: The invention relates to a method for producing vertical electrical connections (micro-vias) in semiconductor wafers for the fabrication of semiconductor components. The method is characterized by the following steps: —application of a protective resist to the wafer front side—patterning of the protective resist on the wafer front side such that... Agent: Thelen Reid Brown Raysman & Steiner LLP

20080206990 - Methods for fabricating semiconductor components with conductive interconnects: A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20080206991 - Methods of forming transistor contacts and via openings: A method of forming contacts to a transistor comprises depositing a dielectric layer on a substrate having the transistor, etching a first opening in the dielectric layer that contacts a gate stack of the transistor, depositing a sacrificial material in the first opening, and etching a second and a third... Agent: Intel Corporation C/o Intellevate, Llc

20080206992 - Method for manufacturing high flatness silicon wafer: The present invention relates to a method for manufacturing a high flatness silicon wafer comprising (S21) slicing a silicon single crystal ingot to produce a wafer; (S22) chamfering an edge of the wafer sliced from the ingot; (S23) lapping the edge-chamfered wafer; (S24) etching the lapped wafer; (S25) grinding the... Agent: Greer, Burns & Crain

20080206993 - Using spectra to determine polishing endpoints: Methods of determining a polishing endpoint are described using spectra obtained during a polishing sequence. In particular, techniques for using only desired spectra, faster searching methods and more robust rate determination methods are described.... Agent: Fish & Richardson P.c.

20080206995 - Metal-polishing liquid and polishing method therewith: t

20080206994 - Using spectra to determine polishing endpoints: Prior to performing a CMP process for planarizing a metallization level of an advanced semiconductor device, an appropriate cap layer may be formed in order to delay the exposure of metal areas of reduced height level to the highly chemically reactive slurry material. Consequently, metal of increased height level may... Agent: J Mike Amerson, Williams, Morgan & Amerson, P.c.

20080206997 - Method for manufacturing insulating film and method for manufacturing semiconductor device: A method for manufacturing an insulating film, by which the insulating film can be formed of a non-photosensitive siloxane resin and formed into a desired shape by wet etching. A thin film is formed with a suspension in which a siloxane resin or a siloxane-based material is included in an... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080206999 - Method for wet etching while forming interconnect trench in insulating film: A wet etching method that includes forming an insulating film on a substrate, and irradiating laser light to the insulating film during wet etching of the insulating film using an etching solution.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080206998 - Semiconductor fabrication apparatuses to perform semiconductor etching and deposition processes and methods of forming semiconductor device using the same: A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and... Agent: Stanzione & Kim, LLP

20080206996 - Sidewall image transfer processes for forming multiple line-widths: A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting... Agent: Schmeiser, Olsen & Watts

20080207000 - Method of making high-aspect ratio contact hole: A substrate has thereon a conductive region to be partially exposed by the contact hole, a contact etch stop layer overlying the substrate and covering the conductive region, and an inter-layer dielectric (ILD) layer on the contact etch stop layer. A photoresist pattern is formed on the ILD layer. The... Agent: North America Intellectual Property Corporation

20080207001 - Pulsed etching cooling: In an apparatus and method of vapor etching, a sample (S) to be etched is located in a main chamber (107) from which the atmosphere inside is evacuated. Etching gas is input into the main chamber (107) for a first period of time. Thereafter, the etching gas is evacuated from... Agent: The Webb Law Firm, P.c.

20080207002 - Method of removing graphitic and/or fluorinated organic layers from the surface of a chip passivation layer having si-containing compounds: A method for removing undesirable contaminants from a chip passivation layer surface without creating SiO2 particles on the passivation layer, wherein the undesirable contaminants include graphitic layers and fluorinated layers. The use of N2 plasma with optimized plasma parameters can remove through etching both the graphitic and fluorinated organic layers.... Agent: Scully, Scott, Murphy & Presser, P.c.

20080207003 - Production method of semiconductor apparatus: In order to provide a production method of a semiconductor apparatus that can form a film, even in the case of forming a carbon film, on a semiconductor substrate while maintaining an improved optical transparency at a visible band and while maintaining a preferable adhesion property, the semiconductor apparatus production... Agent: Sughrue Mion, Pllc

20080207004 - Method of forming a semiconductor structure: A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of... Agent: Freescale Semiconductor, Inc. Law Department

20080207005 - Wafer cleaning after via-etching: When a semiconductor wafer bears porous dielectric materials it is still possible to perform post-via-etch cleaning of the wafer using aqueous cleaning fluids if, before and/or simultaneously with application of the aqueous cleaning fluid(s), a water-soluble organosilane or like passivation material is used to form a passivation layer on the... Agent: Freescale Semiconductor, Inc. Law Department

20080207006 - Process for fabricating an integrated circuit: The present disclosure is directed to a process for plasma treating a film comprising titanium, nitrogen and impurities on a substrate. The process comprises forming a plasma of nitrogen gas and hydrogen gas, the flow ratio of hydrogen gas to nitrogen gas ranging from about 0.01 to about 0.7. The... Agent: Texas Instruments Incorporated

20080207007 - Plasma enhanced cyclic chemical vapor deposition of silicon-containing films: The present invention is a process of plasma enhanced cyclic chemical vapor deposition of silicon nitride, silicon carbonitride, silicon oxynitride, silicon carboxynitride, and carbon doped silicon oxide from alkylaminosilanes having Si—H3, preferably of the formula (R1R2N)SiH3 wherein R1 and R2 are selected independently from C2 to C10 and a nitrogen... Agent: Air Products And Chemicals, Inc. Patent Department

20080207008 - Microwave hybrid and plasma rapid thermal processing of semiconductor wafers: Microwave energy is used as a radiation source for rapid thermal processing of semiconductor wafers. In one aspect, a hybrid material formed from a microwave modulator material is used to provide temperature uniformity across the wafer and to avoid cracking or breaking of wafers due to the development of thermal... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20080199974 - Method for functionalizing biosensor chips: A met4hod is disclosed for functionalizing biosensors. The biosensors are based on semiconductor chips mounted on a finished processed wafer. They are provided with sensor fields placed thereupon, which are arranged in any array, and, to be precise, for carrying out a functionalization, for example, with organic molecules such as... Agent: Harness, Dickey & Pierce, P.L.C

20080199976 - Method of manufacturing semiconductor device including ferroelectric capacitor: A semiconductor device manufacturing method has a step forming a transistor layer portion on a semiconductor substrate, and a step forming a ferroelectric capacitor portion including a lower electrode, a ferroelectric substance and an upper electrode above the transistor layer portion, wherein the step forming the ferroelectric capacitor portion includes... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080199975 - Methods of forming a metal oxide layer pattern having a decreased line width of a portion thereof and methods of manufacturing a semiconductor device using the same: Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually... Agent: Myers Bigel Sibley & Sajovec

20080199977 - Activated chemical process for enhancing material properties of dielectric films: A method for restoring a dielectric constant of a layer of a silicon-containing dielectric material having a first dielectric constant and at least one surface, wherein the first dielectric constant of the layer of silicon-containing dielectric material has increased to a second dielectric constant, the method comprising the steps of:... Agent: Air Products And Chemicals, Inc. Patent Department

20080199978 - System and method for film stress and curvature gradient mapping for screening problematic wafers: A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy... Agent: Slater & Matsil, L.L.P.

20080199979 - Semiconductor device and method for fabricating the same: Method of manufacturing a semiconductor device, including: preparing a TAB tape featuring an insulating tape having a device hole and a plurality of holes, a plurality of leads formed on a surface of the tape and extending at one end into the device hole and at the other end into... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080199980 - Method of manufacturing a semiconductor integrated circuit device: Measures are: obtaining an image of a region PCA within the surface of a wafer including a region OGA pressed by a pressing member, at the center of which a chip just after probe-tested is located, by an imaging means such as a camera; comparing an image of a normal... Agent: Miles & Stockbridge PC

20080199981 - Method for forming a fluid ejection device: A method of forming a fluid ejection device includes forming a pair of first glass layers and forming a second glass layer. Each first glass layer includes a first side and a second side with the second side defining a first fluid flow structure. The second glass layer includes a... Agent: Hewlett Packard Company

20080199982 - Fabrication process for package with light emitting device on a sub-mount: A method of fabricating a package with a light emitting device includes depositing a first metallization to form a conductive pad on which the light emitting device is to be mounted and to form one or more feed-through interconnections extending through a semiconductor material that supports the conductive pad. Subsequently,... Agent: Fish & Richardson P.C.

20080199983 - Method for manufacturing a semiconductor laser: A method of manufacturing semiconductor laser device including a GaN wafer includes forming a semiconductor layer on the GaN wafer and on which ridge portions are formed. Grooves are formed in the semiconductor layer such that each groove is disposed in line with the scribe marks, between each of the... Agent: Leydig Voit & Mayer, Ltd

20080199984 - Oled patterning method: A method of forming a patterned, light-emitting device that includes mechanically locating a first masking film over a substrate; forming first openings in first locations in the masking film; and depositing first light-emissive materials over the substrate through the first openings in the first masking film. Subsequent steps include mechanically... Agent: Frank Pincelli Patent Legal Staff

20080199985 - Leadframe enhancement and method of producing a multi-row semiconductor package: A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with... Agent: Sughrue Mion, PLLC

20080199987 - Manufacturing method of semiconductor device and manufacturing method of lead frame: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080199986 - Method and apparatus for manufacturing electronic integrated circuit chip: A method (and apparatus) of assembling a die on an electronic substrate, includes processing an assembly including a substrate and a die, and during the processing, introducing a pre-stress to the assembly during a cure process.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080199988 - Conductive pattern formation method: The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern. The pitch of the conductive pattern corresponds to the pitch of electrodes on a semiconductor chip.... Agent: Texas Instruments Incorporated

20080199989 - Method of manufacturing semiconductor device: Disclosed herein is a method of manufacturing a semiconductor device having a thyristor formed by joining a first p-type semiconductor layer, a first n-type semiconductor layer, a second p-type semiconductor layer, and a second n-type semiconductor layer in order, the method including the steps of: forming the second p-type semiconductor... Agent: Sonnenschein Nath & Rosenthal LLP

20080199990 - Semiconductor constructions, and methods of forming semiconductor constructions: The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown over the dielectric material and within the gap. Subsequently, a transistor is... Agent: David G. Latwesen, Ph.d. Wells St. John P.s.

20080199991 - Stacked semiconductor device and method of fabrication: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the... Agent: Volentine & Whitt PLLC

20080199992 - Display device, manufacturing method thereof, and television receiver: The present invention discloses a method for manufacturing a display device comprising the steps of forming a first film pattern using a photosensitive material over a substrate, forming a second film pattern in such a way that the first film pattern is exposed by being irradiated with a laser beam,... Agent: Nixon Peabody, LLP

20080199993 - Protective layer in device fabrication: An improved method for fabricating an HEMT device having active device layers deposited on a semiconductor substrate. In an embodiment, the improved method comprises the steps of depositing an AlN layer over the active device layers using a relatively low temperature vacuum process to form an amorphous layer protecting the... Agent: Patti, Hewitt & Arezina LLC

20080199994 - Method of producing semiconductor device and semiconductor device: A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20080199995 - Integrated hydrogen anneal and gate oxidation for improved gate oxide integrity: A method of forming a trench gate field effect transistor includes the following processing steps. Trenches are formed in a semiconductor substrate. The semiconductor substrate is annealed in an ambient including hydrogen gas. A dielectric layer lining at least the sidewalls of the trenches is formed. During the time between... Agent: Townsend And Townsend And Crew, LLP

20080199996 - Method for forming a split gate memory device: A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed... Agent: Freescale Semiconductor, Inc. Law Department

20080199997 - Methods of forming inter-poly dielectric (ipd) layers in power semiconductor devices: A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to... Agent: Townsend And Townsend And Crew, LLP

20080199998 - Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance: The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080199999 - Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial sige: A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and... Agent: Texas Instruments Incorporated

20080200000 - Method for manufacturing semiconductor device: After the formation of element isolation insulating films, an n-well, and a p-well on a Si substrate, the Si substrate is subjected to cleaning (step S1) as pretreatment. The surface of the Si substrate is thermally oxidized by rapid thermal oxidation (RTO) to form a silicon oxide film (step S2)... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080200001 - Method of producing a transistor: t

20080200002 - Plasma sputtering film deposition method and equipment: A method for generating metal ions by sputtering a metal target (56) by plasma, attracting the metal ions by bias power to a target object S which is to be processed and is mounted on a mounting table (20) in a processing vessel, and depositing a metal film (74) on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080200003 - Method for forming multi-layered binary oxide film for use in resistance random access memory: The invention relates to a method for forming a multi-layered binary oxide film for ReRAM. The method includes forming a lower electrode layer on a substrate; forming a metal layer on the lower electrode layer in a vacuum atmosphere; oxidizing the metal layer into a binary oxide film in a... Agent: The Webb Law Firm, P.C.

20080200004 - Method of fabricating semiconductor optical device: In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure is formed on a primary surface of a first III-V semiconductor region. After forming the insulating structures, a second III-V semiconductor region is grown on the first III-V semiconductor... Agent: Smith, Gambrell & Russell

20080200005 - Structure and method of fabricating a transistor having a trench gate: An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the... Agent: Knobbe Martens Olson & Bear LLP

20080200006 - Method for forming shallow trench isolation of semiconductor device: A method for forming a shallow trench isolation (STI) of a semiconductor device comprises forming a nitride film pattern over a semiconductor substrate having a defined lower structure, etching a predetermined thickness of the semiconductor substrate using the nitride film pattern as a mask to form a trench having a... Agent: Marshall, Gerstein & Borun LLP

20080200007 - Methods of forming semiconductor devices: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first... Agent: Mills & Onello LLP

20080200008 - Bonding interface quality by cold cleaning and hot bonding: The invention relates to improvements in a method for molecularly bonding first and second substrates together by placing them in surface to surface contact. The improvement includes, prior to placing the substrates in contact, cleaning the surface of one or both of the substrates in a manner to provide a... Agent: Winston & Strawn LLP Patent Department

20080200009 - Methods of forming stacked semiconductor devices with single-crystal semiconductor regions: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces... Agent: Myers Bigel Sibley & Sajovec

20080200011 - High-temperature, spin-on, bonding compositions for temporary wafer bonding using sliding approach: New compositions and methods of using those compositions as bonding compositions are provided. The compositions comprise a polymer dispersed or dissolved in a solvent system, and can be used to bond an active wafer to a carrier wafer or substrate to assist in protecting the active wafer and its active... Agent: Hovey Williams LLP

20080200010 - Method for manufacturing bonded wafer: A thickness of silicon oxide film of a wafer for active layer is controlled to be thinner than that of buried silicon oxide film. Consequently, uniformity in film thickness of the active layer of a bonded wafer is improved even if a variation in the in-plane thickness of the silicon... Agent: Greenblum & Bernstein, P.L.C

20080200012 - Wafer processing method and laser processing apparatus: In a wafer processing method for penetrating a wafer by use of a laser processing apparatus including a chuck table for holding the wafer, laser beam irradiation means for irradiating the wafer held on the chuck table with a laser beam, and imaging means for imaging the wafer held on... Agent: Smith, Gambrell & Russell

20080200013 - Gallium nitride materials and methods associated with the same: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the... Agent: Wolf Greenfield & Sacks, P.C.

20080200014 - Method of forming a vertical diode and method of manufacturing a semiconductor device using the same: A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer... Agent: Marger Johnson & Mccollom, P.C.

20080200015 - Multi-step plasma doping with improved dose control: A method of multi-step plasma doping a substrate includes igniting a plasma from a process gas. A first plasma condition is established for performing a first plasma doping step. The substrate is biased so that ions in the plasma having the first plasma condition impact a surface of the substrate... Agent: Rauschenbach Patent Law Group, LLC

20080200016 - Method of fabricating nonvolatile semiconductor memory device: A method of fabricating a nonvolatile semiconductor memory device includes the steps of: (a) forming a layered dielectric film on the semiconductor substrate; (b) forming a first conductive film on the layered dielectric film; (c) forming a first dielectric film on the first conductive film; (d) patterning the first dielectric... Agent: Mcdermott Will & Emery LLP

20080200017 - Method of producing semiconductor device: A method of producing a semiconductor device includes the steps of: introducing a p-type impurity corresponding to a conductive type of a channel area into a channel forming area; introducing fluorine into the channel forming area at a low acceleration voltage; and thermally processing a substrate to increase a threshold... Agent: Takuchi & Kubotera, LLP

20080200018 - Substrate processing apparatus, substrate processing method, and method of manufacturing semiconductor device: There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080200019 - Selective deposition of noble metal thin films: Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal... Agent: Knobbe Martens Olson & Bear LLP

20080200020 - Semiconductor device and method of fabricating a semiconductor device: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation.... Agent: Patent Administrator Katten Muchin Rosenman LLP

20080200021 - Split poly-sige/poly-si alloy gate stack: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of... Agent: John A. Jordan, Esq.

20080200022 - Post-seed deposition process: A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above... Agent: Foley & Lardner LLP

20080200023 - Method of fabricating micro connectors: A wafer is provided, and a first surface of the wafer is etched to form a plurality of through holes. A first surface conductive layer is formed on the first surface, and an internal conductive layer is formed to fill up each through hole. A first insulating layer is formed... Agent: North America Intellectual Property Corporation

20080200024 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device includes forming an interlayer insulating film over a semiconductor substrate. The interlayer insulating film is selectively etched to form a hole defining a storage node region. A lower electrode is formed in the hole. A support layer is formed over the lower electrode.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080200025 - Method of forming composite opening and method of dual damascene process using the same: A dual damascene process is provided. A dielectric layer is formed on a substrate and then a via opening is formed in the dielectric layer to expose a liner formed on the substrate. A gap fill (GF) layer is filled into the via opening and a resistant layer is formed... Agent: J C Patents, Inc.

20080200026 - Method of forming fine metal patterns for a semiconductor device using a damascene process: A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene... Agent: Lee & Morse, P.C.

20080200027 - Method of forming metal wire in semiconductor device: The present invention discloses a method of forming a metal wire in a semiconductor device and comprises the steps of forming a first insulating layer, a conductive layer and a capping layer on a semiconductor substrate, forming hard mask patterns on the capping layer, etching the capping layer and the... Agent: Marshall, Gerstein & Borun LLP

20080200028 - Methods of positioning and/or orienting nanostructures: Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures,... Agent: Nanosys Inc.

20080200029 - Method of fabricating microstructures: Provided is a method of fabricating a microstructure, and more specifically, a method of fabricating a structure of a Micro Electro Mechanical System (MEMS), which includes the step of applying and patterning a material for the sacrificial layer on a silicon substrate, and forming a post with the same material... Agent: Needle & Rosenberg, P.C.

20080200030 - Method for producing an electronic component: The invention relates to a method for producing an electronic component on a surface of a substrate with the electronic component having, seen at right angles to the surface of the substrate, at least two electrical functional layers which are arranged one above the other and such that they overlap... Agent: Carella, Byrne, Bain, Gilfillan, Cecchi, Stewart & Olstein

20080200031 - Method of fabricating gate electrode having polysilicon film and wiring metal film: A method of forming a gate electrode of a semiconductor device according to example embodiments that may include forming a polysilicon film on a semiconductor substrate. An interface control layer may be formed on the polysilicon film by repeating a unit cycle a plurality of times. The unit cycle may... Agent: Harness, Dickey & Pierce, P.L.C

20080200032 - Polishing method of semiconductor substrate: The present invention relates to a method of polishing a semiconductor substrate, comprising pressing a semiconductor substrate having a film to be polished that is held by a carrier onto a polishing cloth fixed on a revolving polishing table and supplying a polishing slurry to the space between the polishing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080200033 - Polishing compound, method for polishing surface to be polished, and process for producing semiconductor integrated circuit device: The present polishing compound comprising abrasive particles (A), an adjusting agent of removal rate (B) which is at least one selected from the group consisting of a benzotriazole, a 1H-tetrazole, a benzene sulfonic acid, phosphoric acid or organic phosphonic acid, an organic solvent (C) having a relative permittivity of from... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080200034 - Method to remove beol sacrificial materials and chemical residues by irradiation: A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that... Agent: Ibm Corporation, T.j. Watson Research Center

20080200035 - Method of forming contact hole of semiconductor device: A method of forming a contact hole of a semiconductor device is disclosed. At the time of a hard mask formation process for forming a contact hole of a semiconductor device, first patterns are formed using a photoresist pattern employing an exposure process. Spacers having a predetermined thickness are formed... Agent: Townsend And Townsend And Crew, LLP

20080200036 - Printable etching media for silicon dioxide and silicon nitride layers: The present invention relates to a novel printable etching medium having non-Newtonian flow behaviour for the etching of surfaces in the production of solar cells, and to the use thereof. The present invention furthermore also relates to etching and doping media which are suitable both for the etching of inorganic... Agent: Millen, White, Zelano & Branigan, P.C.

20080200037 - Method of thinning a wafer: A method of thinning wafer is disclosed. A wafer has an active surface and a back surface is provided. A plurality of protruding components may be disposed on the active surface. The wafer is placed in a mold and a polymeric material is formed in the mold to cover at... Agent: North America Intellectual Property Corporation

20080200038 - Heat processing method and apparatus for semiconductor process: A heat processing method for a semiconductor process includes placing a plurality of target substrates stacked at intervals in a vertical direction within a process field of a process container. Each of the target substrates includes a process object layer on its surface. Then, the method includes supplying an oxidizing... Agent: Smith, Gambrell & Russell

20080200039 - Nitridation process: The invention is directed to a nitridation process for a wafer. The nitridation process comprises steps of disposing the wafer on a top surface of a chuck in a nitridation process tool, wherein a plurality of concentric pipe coils is disposed close to the bottom surface of the chuck. Then,... Agent: J C Patents, Inc.

20080194045 - Ferroelectric register, and method for manufacturing capacitor of the same: The present invention discloses a ferroelectric register and a method for manufacturing a capacitor of the same. The ferroelectric register is configured to reduce probability of data storage failure due to a weak state capacitor, by connecting a plurality of capacitors in parallel in a ferroelectric capacitor unit for storing... Agent: Townsend And Townsend And Crew, LLP

20080194046 - Method for determining low-noise power spectral density for characterizing line edge roughness in semiconductor wafer processing: According to one exemplary embodiment, a method for determining a power spectral density of an edge of at least one patterned feature situated over a semiconductor wafer includes measuring the edge of the at least one patterned feature at a number of points on the edge. The method further includes... Agent: Farjami & Farjami LLP

20080194047 - Observation apparatus and method for manufacturing electronic device: A disclosed observation apparatus for observing a void generated in an underfill resin upon mounting a body to be mounted on a substrate via the underfill resin in flip-chip mounting includes: a mounting unit mounting the body to be mounted on the substrate; and an observation unit observing behavior of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080194049 - Method for making a light emitting device: A method for making a light emitting device includes: (a) preparing a chip-mounting board having a conductive surface; (b) mounting a plurality of vertical-feedthrough-LED chips on the conductive surface of the chip-mounting board; (c) forming a photoresist layer that cooperates with the chip-mounting board to enclose the vertical-feedthrough-LED chips; (d)... Agent: Davidson Berquist Jackson & Gowdey LLP

20080194048 - Method for manufacturing a light-emitting diode having high heat-dissipating efficiency: A method for manufacturing a light-emitting diode having a high heat-dissipating efficiency forms a thickened metal into a plurality of supports. The support has a first electrode and a second electrode thereon. The first electrode is formed with a trough. The chip that emits a visible light or an invisible... Agent: Hdsl

20080194050 - Semiconductor light-emitting element and light-emitting device: A semiconductor light-emitting element has a laminated section which has an active layer made of a semiconductor, and first and second clad layers each being disposed to sandwich the active layer and made of a semiconductor, a pair of first high-reflection layers each being disposed to sandwich the active layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080194051 - Die separation: Techniques for dicing wafer assemblies containing multiple metal device dies, such as vertical light-emitting diode (VLED), power device, laser diode, and vertical cavity surface emitting laser device dies, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of... Agent: Patterson & Sheridan, L.l.p.

20080194052 - Optical semiconductor device and method for fabricating the same: An optical semiconductor device includes: a first conductivity type first semiconductor region; a first conductivity type second semiconductor region formed on the first semiconductor region; a second conductivity type third semiconductor region formed on the second semiconductor region; a photodetector section formed of the second semiconductor region and the third... Agent: Mcdermott Will & Emery LLP

20080194053 - Methods for fabricating micro-electro-mechanical devices: A method for fabricating a micro-electro-mechanical device (such as a cMUT) is disclosed. The method combines a substrate, a middle spring layer and a top plate using wafer bonding technology or sacrificial technology. A cavity is formed on either the top of the substrate or the bottom of the middle... Agent: Lee & Hayes, Pllc

20080194054 - Led array package structure having silicon substrate and method of making the same: An LED array package structure having a silicon substrate is disclosed. The LED array package structure comprises a silicon substrate having a plurality of cup-structures thereon, a reflective layer disposed on the silicon substrate, a transparent insulation layer disposed on the reflective layer, a conductive layer disposed on the transparent... Agent: North America Intellectual Property Corporation

20080194055 - Solid-state imaging device and method for manufacturing the same: A solid-state imaging device comprises a housing in which a base and ribs forming a rectangular frame are formed in one piece by a resin; a plurality of metal lead pieces embedded in the housing, each of which has an internal terminal portion facing an internal space of the housing... Agent: Hamre, Schumann, Mueller & Larson, P.c.

20080194056 - Method of producing plurality of organic transistors using laser patterning: A method of producing a plurality of transistors each including a source/drain electrode pair comprising a conductor material and a channel comprising semiconductor material between the source and drain electrodes of said source/drain electrode pair; the method comprising (i) forming over a substrate at least a first layer of said... Agent: Sughrue Mion, Pllc

20080194058 - Method for manufacturing passive device and semiconductor package using thin metal piece: A method for manufacturing passive devices and semiconductor packages using a thin metal piece is provided. According to the method, an adhesive layer is formed on a dummy substrate; a thin metal piece is bonded on the adhesive layer; a masking material is attached to the thin metal piece, a... Agent: Gifford, Krass, Sprinkle,anderson & Citkowski, P.c

20080194057 - Method of making a current sensing chip resistor: A method of making a current sensing chip resistor is composed of a resistor manufacturing process which is constituted by a pre-process and a post-process. In addition, a thin-film process is used for the resistor manufacturing process, and the aluminum nitride substrate is used in the thin-film, in association with... Agent: Troxell Law Office Pllc

20080194059 - Method and apparatus for creating rfid devices: A process is disclosed for creating semiconductor devices such as RFID assemblies wherein an array of dies mounted to a substrate is spaced apart at a first pitch, and the substrate is removed after the positions of the dies in the array is fixed by a solidifiable substance. The solidifiable... Agent: Avery Dennison Corporation Patent Group

20080194060 - Semiconductor device and method of manufacturing the same: A semiconductor device manufacturing method capable of improving the semiconductor device manufacturing yield is disclosed. Semiconductor chips are mounted respectively over semiconductor device regions of a matrix wiring substrate having plural semiconductor device regions, followed by wire bonding, and thereafter sealing resin is formed at a time onto the semiconductor... Agent: Mattingly, Stanger, Malur & Brundidge, P.c.

20080194062 - Adhesive film for semiconductor, lead frame and semiconductor device using the same, and method of producing semiconductor device: An adhesive film for semiconductor, which comprises at least one resin layer, and, after bonded to a lead frame, has at 25° C. a 90°-peel strength of at least 5 N/m between the resin layer and the lead frame, and, after a lead frame is bonded to the adhesive film... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080194061 - Methods of forming packaged semiconductor light emitting devices having multiple optical elements by compression molding: Methods of packaging semiconductor light emitting devices include providing a substrate having the semiconductor light emitting device on a front face thereof. A first optical element is formed from a first material on the front face proximate the semiconductor light emitting device. A second optical element is formed from a... Agent: Myers Bigel Sibley & Sajovec, P.a.

20080194063 - Method for producing a metal article intended for at least partially coating with a substance: A method of producing a metal article intended for at least partially coating with a substance, which includes a metal solder, a plastic, a glass, or a ceramic. The metal article itself may include, in particular, connecting, supporting, or conducting components for an electronic component. The metal article has macroscopically... Agent: Edell , Shapiro & Finnan , Llc

20080194064 - Programming of laser fuse: A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response... Agent: Schmeiser, Olsen & Watts

20080194065 - Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same: An integrated circuit device includes a substrate. An epitaxial pattern is on the substrate and has a pair of impurity diffusion regions formed therein and a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate. Respective ones of the pair... Agent: Myers Bigel Sibley & Sajovec

20080194066 - Methods of forming non-volatile memory cells, and methods of forming nand cell unit string gates: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen.... Agent: Wells St. John P.s.

20080194067 - Fabrication of optical-quality facets vertical to a (001) orientation substrate by selective epitaxial growth: Methods for forming {110} type facets on a (001) oriented substrate of Group III-V compounds and Group IV semiconductors using selective epitaxial growth is provided. The methods include forming a dielectric film on a (100) substrate. The dielectric film can then be patterned to expose a portion of the substrate... Agent: Mh2 Technology Law Group, LLP

20080194068 - Method of manufacturing a 3-d channel field-effect transistor and an integrated circuit: A method of manufacturing an integrated circuit includes providing an auxiliary structure between a first section and a second section of a field-effect transistor. A portion of the auxiliary structure is removed, where a gap is formed between the first section and a remaining portion of the auxiliary structure. In... Agent: Edell, Shapiro & Finnan, Llc

20080194069 - Method of manufacturing a semiconductor device and semiconductor device obtained with such a method: The invention relates to a method of manufacturing a semiconductor device (1.0) with a dual gate field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080194070 - Metal-oxide-semiconductor transistor device, manufacturing method thereof, and method of improving drain current thereof: A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed, in which, an insulation region is formed to define the insulation region and an active region, wherein the active region is adjacent to the insulation region and electrically insulated by the insulation region. A selective epitaxial process is performed to... Agent: North America Intellectual Property Corporation

20080194071 - Method of forming non-volatile memory cell: A method of forming a non-volatile memory cell is provided. The method comprises: (a) providing a substrate; (b) forming a stacking structure on the substrate, the stacking structure at least comprising an oxide-nitride-oxide layer (ONO layer) and a polysilicon layer thereon; (c) patterning the stacking structure to form a plurality... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080194072 - Polysilicon gate formation by in-situ doping: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over... Agent: Slater & Matsil, L.l.p.

20080194074 - Annealing process of polysilizane layer and method of forming isolation layer of semiconductor device employing the same: A method of forming an isolation layer of a semiconductor device is provided. A wafer having a polysilizane (PSZ) layer formed is loaded into a chamber while a loading temperature is maintained in the chamber. An oxygen gas is supplied to the chamber. After the loading, a temperature within the... Agent: Townsend And Townsend And Crew, LLP

20080194073 - Selective etching using a hard mask and a method for forming an isolation structure of a memory device using the same: A disclosed selective etching method comprises mixing a polymer with carbon nanotubes, applying the mixture to an etching target layer to form a carbon nanotube-polymer composite layer, forming a hard mask by patterning the carbon nanotube-polymer composite layer, such that a part of the etching target layer is selectively exposed,... Agent: Marshall, Gerstein & Borun LLP

20080194075 - Process of manufacturing a shallow trench isolation and process of treating bottom surface of the shallow trench for avoiding bubble defects: The present invention discloses a process of manufacturing an STI for avoiding bubble defects, in which, after the shallow trench is formed by etching, substance containing carbon or oxygen on the bottom of the shallow trench is removed, and then the process is continued to accomplish the STI. Alternatively, the... Agent: North America Intellectual Property Corporation

20080194077 - Method of low temperature wafer bonding through au/ag diffusion: Two wafers are bonded. One wafer has a gold (Au) film on its surface; the other, a silver (Ag) film. The wafers are stuck together for a bonding process between the Au and the Ag films. Thus, an Au/Ag bonding layer is formed. The bonding layer has a high melting... Agent: Troxell Law Office Pllc

20080194076 - Process for wafer bonding: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer;... Agent: Haynes And Boone, LLP

20080194078 - Method for manufacturing semiconductor substrate: To obtain a semiconductor substrate having a high-quality Ge-based epitaxial film in a large area, a SiGe mixed crystal buffer layer and a Ge epitaxial film is grown on a main surface of a Si substrate 10. Although high-density defects are introduced in the Ge epitaxial film 11 from an... Agent: Oliff & Berridge, Plc

20080194079 - Method for forming median crack in substrate and apparatus for forming median crack in substrate: In the method for forming a median crack in a brittle substrate, the brittle substrate is irradiated with a laser beam along a laser-scribe line to be formed with median cracks on the brittle substrate so as to be heated to a temperature that is no higher than its melting... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080194080 - Method and product for dicing an optoelectronic semiconductor wafer: A method for dicing an optoelectronic semiconductor wafer has steps of preparing an optoelectronic semiconductor wafer, laser scribing, diamond saw dicing and forming optoelectronic semiconductor dies. A product for dicing an optoelectronic semiconductor wafer has a substrate and an epitaxial layer. The substrate has a first surface, a second surface... Agent: Jackson Walker, L.l.p.

20080194081 - Block-molded semiconductor device singulation methods and systems: The invention discloses methods and systems for singulation of block-molded arrays of semiconductor devices. Preferred embodiments include methods and associated systems for securing a block-molded array of semiconductor devices into a mounting ring with light-sensitive tape. Tape-deactivating is used to render exposed regions of the light-sensitive tape less tacky. The... Agent: Yisheng Tung Texas Instruments Incorporated

20080194082 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer... Agent: Harness, Dickey & Pierce, P.L.C

20080194083 - Methods of laterally forming single crystalline thin film regions from seed layers: In a method of manufacturing a semiconductor device, a string structure including a selection transistor and a memory cell on a substrate. An insulation layer pattern is formed on the substrate to cover the string structure. The insulation layer pattern includes at least one opening exposing a portion of the... Agent: Myers Bigel Sibley & Sajovec

20080194085 - Growth of textured gallium nitride thin films and nanowires on polycrystalline substrates: A synthesis route to grow textured thin film of gallium nitride on amorphous quartz substrates and on single crystalline substrates such as c-sapphire and polycrystalline substrates such as pyrolytic boron nitride (PBN), alumina and quartz using the dissolution of atomic nitrogen rather than molecular nitrogen to allow for growth at... Agent: David W. Carrithers Carrithers Law Office, Pllc

20080194084 - Method of fabrication of highly heat dissipative substrates: The invention relates to a method for fabricating a composite structure having heat dissipation properties greater than a bulk single crystal silicon structure having the same dimensions. The structure includes a support substrate, a top layer and an oxide layer between the support substrate and the top layer. The method... Agent: Winston & Strawn LLP Patent Department

20080194086 - Method of introducing impurity: e

20080194087 - Polysilicon gate formation by in-situ doping: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over... Agent: Slater & Matsil, L.l.p.

20080194088 - Vapor deposition methods for forming a metal-containing layer on a substrate: Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high... Agent: Mueting, Raasch & Gebhardt, P.a.

20080194089 - Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations: A method of forming a current mirror device for an integrated circuit includes configuring a reference current source; forming a first field effect transistor (FET) in series with the reference current source, the first FET of a first conductivity type formed on a first portion of a substrate having a... Agent: Cantor Colburn LLP-ibm Burlington

20080194090 - Method for manufacturing semiconductor device using a free radical assisted chemical vapor deposition nitirifying process: A method for manufacturing a semiconductor device for use in avoiding unwanted oxidation along exposed surfaces and for use in relieving etching damage is presented. The method includes step of forming sequentially a gate insulation layer, a polysilicon layer, a barrier layer, a metallic layer and a hard mask layer... Agent: Ladas & Parry LLP

20080194091 - Method for fabricating nitrided oxide layer: A method for fabricating a nitrided oxide layer. A plasma reactor including a pedestal for supporting a substrate is provided. A substrate having an oxide layer thereon is placed on the pedestal. Nitridation of the oxide layer is performed by exposing the substrate to decoupled nitrogen plasma, wherein a positive... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080194092 - Method of fabricating a mos device with non-sio2 gate dielectric: A polycrystalline silicon layer is deposited on a gate dielectric and then a portion thereof is re-oxidized so as to form a thin layer of oxide between the poly-Si layer and the underlying gate dielectric. Subsequently, the poly-Si layer is converted to a fully-silicided form so as to produce a... Agent: Freescale Semiconductor, Inc. Law Department

20080194093 - Method for fabricating a nonvolatile memory device: A method for forming a nonvolatile memory device includes forming a tunnel insulation layer and a first conductive layer over a substrate. A trench is formed by partially etching the first conductive layer, the tunnel insulation layer and the substrate, thereby forming a resultant structure. An insulation layer is formed... Agent: Townsend And Townsend And Crew, LLP

20080194094 - Tungsten-doped indium oxide structures and methods: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain tungsten and monolayers that contain indium are deposited onto a substrate and subsequently processed to form tungsten-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure.... Agent: Schwegman, Lundberg & Woessner, P.a.

20080194095 - Undercut-free blm process for pb-free and pb-reduced c4: A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned... Agent: Scully, Scott, Murphy & Presser, P.c.

20080194096 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprises: forming a copper interconnect in an insulating film overlying a substrate; and annealing the copper interconnect at a temperature of 300° C. or less. The copper interconnect has a minimum interconnect width of 0.1 μm or less and a maximum interconnect width... Agent: Young & Thompson

20080194097 - Method of reworking a semiconductor substrate and method of forming a pattern of a semiconductor device: A method of reworking a semiconductor substrate and a method of forming a pattern of semiconductor device using the same without damage to an organic anti-reflective coating (ARC) is provided. The method of reworking a semiconductor substrate includes forming a photoresist pattern on a substrate having the organic ARC formed... Agent: Harness, Dickey & Pierce, P.L.C

20080194098 - Flash memory device and method of manufacturing the same: A method of forming a semiconductor device includes forming a first conductive layer over a semiconductor substrate. A dielectric layer is formed over the first conductive layer. A mask pattern having a first opening is formed over the dielectric layer. The mask pattern is annealed to convert the first opening... Agent: Townsend And Townsend And Crew, LLP

20080194099 - Method for integrating liner formation in back end of line processing: A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and... Agent: Cantor Colburn LLP - Ibm Fishkill

20080194100 - Method for forming metal silicide layer: The invention provides a method for forming a metal silicide layer. The method comprises steps of providing a substrate and forming a nickel-noble metal layer over the substrate. A grain boundary sealing layer is formed on the nickel-noble metal layer and then an oxygen diffusion barrier layer is formed on... Agent: J C Patents, Inc.

20080194101 - Method of manufacturing a contact structure to avoid open issue: A method of manufacturing a contact structure to avoid open issue is provided. The method includes the steps of providing a substrate with a contact region, forming an insulating layer to cover the substrate, forming a contact hole in the insulating layer to expose the contact region, conformally depositing a... Agent: Ingrassia Fisher & Lorenz, P.c.

20080194102 - Semiconductor device and manufacturing method thereof: The barrier film (for instance, a second barrier film 6) disposed between the interconnection or the via plug and its overlying interlayer insulating film is made to have a layered structure made of a plurality of films containing silicon and carbon (preferably, silicon, carbon and nitrogen), with different carbon contents,... Agent: Sughrue Mion, Pllc

20080194104 - Apparatus for plasma chemical vapor deposition and method for fabricating semiconductor device by using the same: An apparatus for use in a plasma chemical vapor deposition (CVD) includes a chamber; a cooling gas inlet passing through an electrostatic chuck for supplying a cooling gas to the bottom surface of a wafer when the plasma CVD process is performed; and a clamping unit for clamping the wafer... Agent: Townsend And Townsend And Crew, LLP

20080194103 - Composition and methods for forming metal films on semiconductor substrates using supercritical solvents: Compositions and methods for forming metal films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing at least one metal precursor comprising at least one ligand, an excess amount... Agent: Buchanan, Ingersoll & Rooney Pc

20080194105 - Organometallic precursors for seed/barrier processes and methods thereof: Organometallic precursors and methods for deposition on a substrate in seed/barrier applications are herein disclosed. In some embodiments, the organometallic precursor is a ruthenium-containing, tantalum-containing precursor or combination thereof and may be deposited by atomic layer deposition, chemical vapor deposition and/or physical vapor deposition.... Agent: Intel/blakely

20080194106 - Method of forming a titanium aluminum nitride layer and method of manufacturing a phase-change memory device using the same: In a method of forming a titanium aluminum nitride layer, a first reactant is formed on a substrate by reacting a first source including titanium and a second source including nitrogen. A second reactant is formed by providing a third source including aluminum onto the substrate having the first reactant... Agent: Marger Johnson & Mccollom, P.c.

20080194107 - Method of manufacturing semiconductor device: The present invention aims to improve the controllability of dimensions at the time when a silicon substrate or a film formed on top of the silicon substrate is etched. For this purpose, a SiN film is formed so as to be in contact with the top of an element-forming surface... Agent: Mcginn Intellectual Property Law Group, Pllc

20080194109 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device includes the steps of: depositing on a main surface of a semiconductor substrate a layer to be processed; depositing a base layer on the layer to be processed; depositing a first intermediate layer and then a second intermediate layer on the base layer;... Agent: Mcdermott Will & Emery LLP

20080194108 - Methods of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device using double patterning. The method includes: forming a first material layer pattern having recesses in a first direction on an object layer and a second material layer pattern formed on the first material layer pattern; selectively etching the second material layer... Agent: Myers Bigel Sibley & Sajovec

20080194110 - Methods of fabricating a semiconductor device using a dilute aqueous solution of an ammonia and peroxide mixture: This invention provides methods of fabricating semiconductor devices, wherein an alloy layer is formed on a semiconductor substrate to form a substrate structure, which methods include using an aqueous solution diluted ammonia and peroxide mixture (APM) to perform cleaning and/or wet etching treatment steps on the substrate structure.... Agent: Mills & Onello LLP

20080194111 - Removal of process residues on the backside of a substrate: A substrate is processed in a process chamber comprising a substrate support having a receiving surface for receiving a substrate so that a front surface of the substrate is exposed within the chamber. An energized process gas is used to process the front surface of the substrate. A peripheral edge... Agent: Janah & Associates, P.c.

20080194112 - Method and system for plasma etching having improved across-wafer etch uniformity: A method for improving across-wafer etch uniformity of semiconductor devices in an etching chamber, wherein the method includes: introducing a first flow of gas mixtures from a central gas distribution plate manifold; introducing a second flow of gas mixtures from an auxiliary gas feed; and controlling process parameters including one... Agent: Cantor Colburn LLP - Ibm Fishkill

20080194113 - Methods and apparatus for semiconductor etching including an electro static chuck: There is provided a semiconductor etching apparatus which removes particles remaining on the upper surface of an electro static chuck (ESC) during an etching process, thereby preventing a chucking force from decreasing and minimizing a leak of helium. To prevent a failure of the etching process due to a wafer... Agent: Myers Bigel Sibley & Sajovec

20080194114 - Plasma etching method: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080194115 - Processing method and storage medium: A processing method includes a gas having a Si—CH3 bond supplied into a processing chamber after a target substrate to be processed is loaded into the processing chamber; and a silylation process performed on the target substrate. The internal pressure of the chamber by the supply of the gas having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080194116 - Treatment solution and method of applying a passivating layer: A treatment solution for a semiconductor wafer comprising water, a passivating reagent and a surfactant. The treatment solution is either mixed with a cleaning fluid, a rinsing fluid or a drying vapour, and is used in a cleaning apparatus employing a Marangoni dryer.... Agent: Freescale Semiconductor, Inc. Law Department

20080194117 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device, includes forming a porous organo-siloxane film containing a porogen component having carbon as a main component above a semiconductor substrate, forming an upper-side insulating film having at least one of film density and film composition different from that of the porous organo-siloxane film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080194118 - Trench filling method: According to this method, even when aluminum is embedded into trenches having a fine and complex pattern, embedding performance is high and trenches in a large substrate can filled. This method can be carried out at a low cost.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080188011 - Apparatus and method of temperature conrol during cleaving processes of thick film materials: An apparatus for temperature control of manufacture of thick film materials includes a stage comprising a planar surface for supporting a bulk material to be implanted and subsequently cleaved. The bulk material has a surface region, a side region, and a bottom region which provides a volume of material and... Agent: Townsend And Townsend And Crew, LLP

20080188013 - In-situ dose monitoring using optical emission spectroscopy: The present invention generally provides methods and apparatus for monitoring ion dosage during a plasma process. One embodiment of the present invention provides a method for processing a substrate comprising generating a correlation between the at least one attribute of the plasma and a dosage quantity.... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080188012 - Manufacturing method of display device: In crystallization of a silicon film by annealing with a linear-shaped laser beam having an ununiform width of the short axis of the beam, the profile (intensity distribution) of the laser beam is evaluated, and the result is fed back to an oscillating condition of the laser beam or an... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080188014 - Feed forward silicide control scheme based on spacer height controlling preclean time: Embodiments herein present a method for a feed forward suicide control scheme based on spacer height controlling pre-clean time. The method forms field effect transistor gates over a substrate and then forms spacers on the gates. Next, the method measures the spacers using an atomic force microscope to determine a... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080188015 - Testing and burn-in using a strip socket: A method and apparatus are provided for using a strip socket in testing or burn-in of semiconductor devices in a strip. In one example of the method, processing of semiconductor devices involves assembling the semiconductor devices into a strip, isolating a portion of each of the semiconductor devices of the... Agent: Haverstock & Owens LLP Attn: Thomas B. Haverstock

20080188016 - Die detection and reference die wafermap alignment: One embodiment of the present invention includes a method for aligning a wafermap with a semiconductor wafer. The method may comprise assigning a location code to each of a plurality of dies on the wafermap. Each of the plurality of dies on the wafermap can correspond to each of a... Agent: Texas Instruments Incorporated

20080188017 - Method of sorting dies using discrimination region: A method of sorting dies using a discrimination region includes preparing a wafer including a chip region in which a plurality of dies are disposed and an edge region in which at least one discrimination region is disposed; testing the dies to prepare a wafer map for defining the coordinates... Agent: Mills & Onello LLP

20080188018 - Method of manufacturing ink jet circuit board with heaters and electrodes constructed to reduce corrosion: An ink jet head circuit board is provided which has heaters to generate thermal energy for ink ejection as they are energized. This circuit board has the heaters formed with high precision to reduce their areas. It also has provisions to protect the electrode wires against corrosion and prevent a... Agent: Fitzpatrick Cella Harper & Scinto

20080188019 - Methods of forming electromagnetic radiation emitters and conduits, methods of forming imager systems, methods of forming nanofluidic channels, fluorimetry methods: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures... Agent: Wells St. John P.s.

20080188020 - Method of led packaging on transparent flexible film: A method of LED packaging on transparent on transparent flexible film by: depositing transparent ITO on a flexible transparent substrate to form a conducting layer, and then processing the conducting layer to form a circuit pattern, and then bonding LED chips to the circuit pattern, and then molding a lens... Agent: Pro-techtor International Services

20080188021 - Light emitting diode and method making the same: A light emitting diode and the method of the same are provided. The light emitting diode includes a light emitting structure and a metal reflective layer. The light emitting structure includes two semiconductor layers and an active layer. Oxide elements are added into the metal reflective layer to improve the... Agent: Snell & Wilmer L.L.P. (main)

20080188022 - Semiconductor display devices: In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate that the electrical... Agent: Fish & Richardson P.C.

20080188023 - Method of manufacturing display substrate, method of patterning inorganic layer and method of manufacturing display device using the same: A method of manufacturing a display substrate includes forming a plurality of thin film transistors (TFTs) on a first substrate in a matrix, forming a plurality of pixel electrodes connected to the TFTs, forming a connecting pad to receive a common voltage, forming an organic pattern on the connecting pad,... Agent: F. Chau & Associates, LLC

20080188024 - Method of fabricating micro mechanical moving member and metal interconnects thereof: A method of fabricating micro mechanical moving member and metal interconnects thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the... Agent: North America Intellectual Property Corporation

20080188026 - Method for manufacturing a semiconductor package structure having micro-electro-mechanical systems: The present invention relates to a method for manufacturing a semiconductor package structure having Micro-Electro-Mechanical Systems (MEMS). A plurality of Micro-Electro-Mechanical Systems is disposed on a plurality of substrate units of a substrate, and a plurality of cover units of a cover plate is used to seal the corresponding Micro-Electro-Mechanical... Agent: Volentine & Whitt PLLC

20080188025 - Semiconductor device manufacturing method: A movable structural body formed over a semiconductor substrate is covered with a sacrifice film. The sacrifice film is covered with a silicon oxide film. Further, through holes are defined in the silicon oxide film. The sacrifice film is removed through the through holes to form space between the movable... Agent: Rabin & Berdo, PC

20080188027 - Semiconductor device having impurity-doped resistor element: Resistor elements are formed by doping impurity into a single crystal film formed on a substrate such as a silicon-on-insulator substrate. A semiconductor device having such resistor elements is used as a detector for detecting an amount of airflow, for example. The impurity density in the single crystal silicon is... Agent: Posz Law Group, PLC

20080188028 - Photodiode and phototransistor: A phototransistor includes a first-conduction-type lower region, a second-conduction-type upper region disposed on the first region, a second-conduction-type electrode contact region of a high concentration disposed at a surface inside of the upper region and is connected to an electrode so as to transmit a signal, a first-conduction-type first shield... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20080188029 - Pinned photodiode structure and method of formation: An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack is provided. A photodiode with a shallow doping profile with respect to the top surface of... Agent: Dickstein Shapiro LLP

20080188030 - Image sensor chip package and method of fabricating the same: The present invention relates to an image sensor chip package and a method for fabricating the same. In one embodiment of an image sensor chip package, chip pads on a first surface of an image sensor chip are attached to electrode pads of a glass substrate with conductive material. In... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080188031 - Packaging method of a light-sensing semiconductor device and packaging structure thereof: The present invention discloses a packaging method of a light-sensing semiconductor device and a packaging structure thereof, wherein a matrix of spacer walls is formed on a light-sensing wafer, which has multiple light-sensing chips, and the adhesive is directly applied to between two neighboring spacer walls on the non-light-sensing regions.... Agent: Rosenberg, Klein & Lee

20080188032 - Novel nanoparticle containing siloxane polymers: A method of producing a polymer composition for semiconductor optoelectronics, comprising the steps of providing at least one type of disilane monomer which is homo- or copolymerized to form a (co)polymer and then combined with nanoparticles to provide a polymer composition. The nanoparticle containing composition has excellent properties with high... Agent: Kubovcik & Kubovcik

20080188033 - Multi-junction solar cells and methods and apparatuses for forming the same: Embodiments of the present invention generally relate to solar cells and methods and apparatuses for forming the same. More particularly, embodiments of the present invention relate to thin film multi-junction solar cells and methods and apparatuses for forming the same.... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080188034 - Assemblies displaying differential negative resistance, semiconductor constructions, and methods of forming assemblies displaying differential negative resistance: The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at least about 9. The invention also includes a semiconductor construction comprising a substrate, and a first layer over the substrate. The first layer comprises Ge and one or more of... Agent: Dickstein Shapiro LLP

20080188035 - System and method for sealing a mems device: A method for assembling a hermetically sealed package to contain a MEMS die and the hermetically sealed package are presented. The method includes selectively applying a glass mixture to a dome. The dome is heated to a first temperature sufficient to flow the glass mixture. The dome is pressed into... Agent: Honeywell International Inc. Patent Services Ab-2b

20080188036 - Method, system, program product for bonding two circuitry-including substrates and related stage: A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying... Agent: Hoffman Warnick LLC

20080188037 - Method of manufacturing semiconductor chip assembly with sacrificial metal-based core carrier: A method of making a semiconductor chip assembly is disclosed. The semiconductor chip assembly is made by attaching a semiconductor chip to a multi-layer build-up substrate with a metal-based core carrier. The build-up substrate layers provide routing functions while the metal-based core carrier provides critical mechanical support for the semiconductor... Agent: Troxell Law Office PLLC

20080188038 - Integrated circuit edge protection method and apparatus: An apparatus, method, and system for providing a mechanical divider adapted to shield at least a portion of an active surface of an integrated circuit from out-gassing from underfill material. The mechanical divider is attached to a mounting substrate. The underfill material is dispensed on the mounting substrate. The integrated... Agent: Schwabe, Williamson & Wyatt, P.C.

20080188039 - Method of fabricating chip package structure: A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to... Agent: Jianq Chyun Intellectual Property Office

20080188040 - Method of manufacturing semiconductor device: A solder 14 is formed, by a plating method, on a connecting surface 21A and a side surface 21B in a connecting pad 21 of a wiring board 11 which is opposed to a metal bump 13 formed on an electrode pad 31 of a semiconductor chip 12, and subsequently,... Agent: Rankin, Hill & Clark LLP

20080188041 - Lateral undercut of metal gate in soi device: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.... Agent: Intel/blakely

20080188042 - Method of manufacturing thin film transistor panel: Provided is a method of manufacturing a thin film transistor panel that may reduce manufacturing costs. The method includes forming gate wires including a gate line and a gate electrode on an insulating substrate and forming data wires including source and drain electrodes, the data wires being insulated from the... Agent: H.c. Park & Associates, PLC

20080188043 - Method of manufacturing a semiconductor device: After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both... Agent: Townsend And Townsend And Crew, LLP

20080188044 - Semiconductor devices with dual-metal gate structures and fabrication methods thereof: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080188045 - Methods for operating and fabricating a semiconductor device having a buried guard ring structure: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction... Agent: Zagorin O'brien Graham LLP

20080188046 - Method and apparatus for manufacturing a semiconductor: A method and apparatus for crystallizing a semiconductor that includes a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation, comprising amorphizing at least a portion of the second layer, applying a stress to the second layer and heating the second... Agent: Infineon Technologies North America Corp.

20080188047 - Electrostatic discharge protection device and method of fabricating the same: An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a... Agent: Lee & Morse, P.C.

20080188048 - Semiconductor device: The invention provides a semiconductor apparatus capable of achieving a device having a snap-back resisting pressure of about 5 to 10 V by a self-aligning process. The semiconductor apparatus includes two or more sub-gates placed next to a main gate at a predetermined interval, and low concentration layers placed continuously... Agent: Young & Thompson

20080188049 - Methods of manufacturing non-volatile memory devices including charge-trapping layers: Methods of manufacturing non-volatile memory devices are provided including sequentially forming a tunnel insulating layer, a charge-trapping layer, a blocking layer and a conductive layer on a substrate having a channel region. The conductive layer is patterned to form a word line structure, and the blocking layer and the charge-trapping... Agent: Myers Bigel Sibley & Sajovec

20080188050 - Semiconductor device and method for manufacturing the same: The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to... Agent: Nixon Peabody, LLP

20080188051 - Methods of forming one or more covered voids in a semiconductor substrate, methods of forming field effect transistors, methods of forming semiconductor-on-insulator substrates, methods of forming a span comprising silicon dioxide, methods of cooling semi: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures... Agent: Wells St. John P.s.

20080188052 - Split-gate thin film storage nvm cell with reduced load-up/trap-up effects: A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15,... Agent: Hamilton & Terrile, LLP

20080188054 - Fabricating resistors: Methods for fabricating polysilicon resistors or silicon diffused resistors and mask structures for use in said methods. In one example embodiment, a method of fabricating a resistor includes forming an insulating layer on a semiconductor substrate, forming a polysilicon pattern on the insulating layer, and implanting impurity on the polysilicon... Agent: Workman Nydegger

20080188053 - Method for forming fully silicided gate electrodes and unsilicided poly resistors: A method is disclosed for forming silicided gate electrodes and unsilicided poly resistors. After patterning a semiconductor material for the gate electrode and resistor structures, a first dielectric layer is used to protect a poly resistor that is not to be silicided, then a first silicidation is performed for partially... Agent: Duane Morris LLPIPDepartment (tsmc)

20080188055 - Metal-insulator-metal structure and method of forming the same: A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080188056 - Method for forming capacitor of semiconductor device: A method for forming a capacitor of a semiconductor device includes the steps of forming first and second sacrificial insulation layers over a semiconductor substrate divided into first and second regions. The second and first sacrificial insulation layers in the first region are etched to define in the first region... Agent: Ladas & Parry LLP

20080188057 - Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed... Agent: Mills & Onello LLP

20080188058 - Semiconductor device and manufacturing method thereof: The present invention provides a method for manufacturing a semiconductor device which includes at least supplying an adhesive for bonding an electronic component which has a plurality of bumps with a substrate which has a plurality of bonding pads corresponding to the bumps, to at least a portion of the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080188059 - Integrated sensor and circuitry and process therefor: A micromachined sensor and a process for fabrication and vertical integration of a sensor and circuitry at wafer-level. The process entails processing a first wafer to incompletely define a sensing structure in a first surface thereof, processing a second wafer to define circuitry on a surface thereof, bonding the first... Agent: Hartman & Hartman, P.C.

20080188060 - Process for fabricating a substrate of the silicon-on-insulator type with thin surface layer: A process for fabricating a silicon on insulator (SOI) substrate by forming a weakened zone within a semiconductor donor substrate to define a thick layer having a thickness of greater 150 nm and form a boundary between the thick layer and a remainder of the donor substrate, bonding the donor... Agent: Winston & Strawn LLP Patent Department

20080188061 - Method of protecting front surface structure of wafer and method of wafer dividing: A method of protecting front surface structure of a wafer and method of wafer dividing is provided. Initially, a wafer having a plurality of device disposed on a front surface thereof is provided. A protective layer is formed on the front surface of the wafer and a first bonding layer... Agent: North America Intellectual Property Corporation

20080188063 - Graded core/shell semiconductor nanorods and nanorod barcodes: Graded core/shell semiconductor nanorods and shaped nanorods are disclosed comprising Group II-VI, Group III-V and Group IV semiconductors and methods of making the same. Also disclosed are nanorod barcodes using core/shell nanorods where the core is a semiconductor or metal material, and with or without a shell. Methods of labeling... Agent: Townsend And Townsend And Crew, LLP

20080188062 - Method of forming microcrystalline silicon film: A method capable of making a semiconductor device in a plasma-assisted chemical vapor deposition (CVD) system including a chamber having a first electrode and a second electrode spaced apart from one another, the method comprising providing a substrate on the second electrode, the substrate including a surface being exposed to... Agent: Akin Gump LLP - Silicon Valley

20080188064 - Nanostructures and methods for manufacturing the same: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.... Agent: Foley And Lardner LLP Suite 500

20080188065 - Preparation method of a coating of gallium nitride: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080188066 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device includes: forming a dummy gate that defines a region in which a gate electrode should be formed on a semiconductor substrate; forming a surface film on the semiconductor substrate by directional sputtering vertical to a surface of the semiconductor substrate, the directional sputtering... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080188067 - Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer: A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer... Agent: Larson Newman Abel Polansky & White, LLP

20080188068 - Method of forming a semiconductor device having a removable sidewall spacer: A semiconductor device is formed using a semiconductor substrate. A gate dielectric is formed over the semiconductor substrate. A gate electrode layer is formed over the gate dielectric. A patterned masking layer is formed over the gate electrode layer. A first region of the gate electrode layer lies within an... Agent: Freescale Semiconductor, Inc. Law Department

20080188069 - Apparatus and method for semiconductor wafer bumping via injection molded solder: An improved apparatus and a method for semiconductor wafer bumping, that utilizes the injection molded solder process. The apparatus is designed for high volume manufacturing and includes equipment for filling patterned mold cavities formed on a first surface of a mold structure with solder, equipment for positioning and aligning a... Agent: Akc Patents

20080188070 - Apparatus and method for semiconductor wafer bumping via injection molded solder: An improved apparatus for positioning and aligning a patterned surface of a semiconductor structure directly opposite to solder filled patterned mold cavities of a mold structure includes a pattern based alignment too including means for identifying a mold training pattern image and a semiconductor training pattern image on a training... Agent: Akc Patents

20080188071 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin

20080188072 - Apparatus and method for semiconductor wafer bumping via injection molded solder: An improved apparatus for semiconductor wafer bumping utilizes the injection molded solder process and is designed for high volume manufacturing. The apparatus includes equipment for filling patterned mold cavities on a mold structure with solder, equipment for positioning and aligning a patterned surface of a semiconductor structure directly opposite to... Agent: Akc Patents

20080188073 - Methods of forming a span comprising silicon dioxide: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures... Agent: Wells St. John P.s.

20080188074 - Peeling-free porous capping material: A method for forming a cap layer for an interconnect structure is provided. The method includes providing a substrate; depositing a low-k dielectric layer comprising a first porogen over the substrate; depositing a low-k cap layer comprising a second porogen on the low-k dielectric layer; and curing the low-k dielectric... Agent: Slater & Matsil, L.L.P.

20080188075 - Semiconductor device and production method therefor: A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a second interconnection layer of gold provided as an uppermost interconnection layer on the interlevel insulation film; and a barrier layer provided between the first interconnection... Agent: Rabin & Berdo, PC

20080188076 - Method for fabricating semiconductor device: A trench is formed in an interlayer dielectric formed on a substrate, then a barrier seed film is formed to cover the interlayer dielectric and the inner walls of the trench, and copper is embedded in the trench by electrolytic plating using the barrier seed film as an electrode. The... Agent: Mcdermott Will & Emery LLP

20080188077 - Barrier film deposition over metal for reduction in metal dishing after cmp: A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to pattern the tungsten layer, upper topological regions of the protective barrier... Agent: Stmicroelectronics, Inc.

20080188078 - Manufacturing method of electronic element: A circumferential portion of an epitaxial wafer is removed to remove an anomalously grown elevated portion formed in a circumferential chamfer. An epitaxial layer in the circumferential portion is removed with a width q=t to 5t wherein t is the thickness of the epitaxial layer so that the surface of... Agent: Venable LLP

20080188079 - Metal-polishing composition and chemical mechanical polishing method by using the same: in Formula A, R1 represents an alkyl group having 1 to 3 carbon atoms; and R2 represents a hydrogen atom or an alkyl group having 1 to 4 carbon atoms, and in Formula B, R3, R4, and R5 each independently represent a hydrogen atom, or an alkyl, aryl, alkoxy, amino,... Agent: Sughrue Mion, PLLC

20080188080 - Mandrel/trim alignment in sit processing: Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080188082 - Pulsed ultra-high aspect ratio dielectric etch: A method for selectively etching an ultra high aspect ratio feature dielectric layer through a carbon based mask in an etch chamber is provided. A flow of an etch gas is provided, comprising a fluorocarbon containing molecule and an oxygen containing molecule to the etch chamber. A pulsed bias RF... Agent: Beyer Law Group LLP

20080188081 - Ultra-high aspect ratio dielectric etch: A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon... Agent: Beyer Law Group LLP

20080188083 - Method of forming fine patterns of semiconductor device using double patterning: A method of forming fine patterns of a semiconductor device includes double etching by changing a quantity of producing polymer by-products to etch a film with different thicknesses in regions having different pattern densities. In a first etching, reactive ion etching (RIE) is performed upon a buffer layer and a... Agent: Myers Bigel Sibley & Sajovec

20080188084 - Method for reducing and homogenizing the thickness of a semiconductor layer which lies on the surface of an electrically insulating material: To reduce and homogenize the thickness of a semiconductor layer which lies on the surface of an electrically insulating material, the surface of the semiconductor layer is exposed to the action of an etchant whose redox potential is adjusted as a function of the material and the desired final thickness... Agent: Brooks Kushman P.C.

20080188085 - Post-dry etching cleaning liquid composition and process for fabricating semiconductor device: A post-dry etching cleaning liquid composition for cleaning a substrate after dry etching is provided, the cleaning liquid composition containing at least one type of fluorine compound, glyoxylic acid, at least one type of organic acid salt, and water. With regard to the fluorine compound, ammonium fluoride may be used.... Agent: L. C. Begin & Associates, PLLC

20080188086 - Etching method, etching apparatus and storage medium: An etching method for forming a groove by etching a silicon layer of a substrate by using a mask which has a first region where an opening with a first opening width is formed and a second region where an opening with a second opening width larger than the first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080188088 - Forming method and structure of porous low-k layer, interconnect process and interconnect structure: A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with... Agent: J C Patents, Inc.

20080188087 - Internal balanced coil for inductively coupled high density plasma processing chamber: A coil is provided for use in a semiconductor processing system to generate a plasma with a magnetic field in a chamber. The coil comprises a first coil segment, a second coil segment and an internal balance capacitor. The first coils segment has a first end and a second end.... Agent: Townsend And Townsend And Crew LLP / Amat

20080188089 - Method for reducing top notching effects in pre-doped gate structures: A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces... Agent: Cantor Colburn LLP - IBM Fishkill

20080188090 - Internal balanced coil for inductively coupled high density plasma processing chamber: A coil is provided for use in a semiconductor processing system to generate a plasma with a magnetic field in a chamber. The coil comprises a first coil segment, a second coil segment and an internal balance capacitor. The first coils segment has a first end and a second end.... Agent: Townsend And Townsend And Crew LLP / Amat

20080188091 - Semiconductor device, method for fabricating thereof and method for increasing film stress: A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is... Agent: J.c. Patents

20080188092 - Electronic device array: A method of producing an array of electronic devices, the method including the steps of: forming one or more first conductive elements of a first electronic device on a substrate and one or more second conductive elements of a second electronic device on said substrate; and forming a layer of... Agent: Sughrue Mion, PLLC