Semiconductor device manufacturing: process inventions 07/08

20080182342 - Magnetic tunnel barriers and associated magnetic tunnel junctions with high tunneling magnetoresistance: Magnetic tunneling devices are formed from a first body centered cubic (bcc) magnetic layer and a second bcc magnetic layer. At least one spacer layer of bcc material between these magnetic layers exchange couples the first and second bcc magnetic layers. A tunnel barrier in proximity with the second magnetic... Agent: Daniel E. Johnson IBM Corporation, Almaden Research Center

20080182344 - Method and system for determining deformations on a substrate: A method and system determines deformations in a substrate in the manufacturing of semiconductor devices. At least one property of vertical deformations of the substrate is measured at a plurality of locations on the substrate. Afterward, an automatic computation of horizontal deformations is determined based on the measured properties of... Agent: Slater & Matsil LLP

20080182343 - Real-time parameter tuning using wafer temperature: The invention can provide a method of processing a wafer using a Real-Time Parameter Tuning (RTPT) procedure to receive an input message that can include a pass-through message, a real-time feedforward message, or a real-time optimization message, or any combination thereof. The RTPT procedures can use real-time wafer temperature data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080182345 - Substrate processing method and semiconductor manufacturing apparatus: a step of processing the substrate by flowing a cooling gas through the cooling-gas passage by means of a cooling device while heating the process chamber by the heating device, and placing the heating device and the cooling device under control of a control section depending upon a pressure value... Agent: Oliff & Berridge, PLC

20080182346 - Method for reducing etch-induced process uniformities by omitting deposition of an endpoint detection layer during patterning of stressed overlayers in a semiconductor device: During the patterning of respective contact etch stop layers having a different type of intrinsic stress, the deposition of an etch indicator layer between the first and the second contact etch stop layer may be omitted in order to avoid any undue effects of this layer during the subsequent processing.... Agent: Williams, Morgan & Amerson

20080182347 - Methods for monitoring ion implant process in bond and cleave, silicon-on-insulator (soi) wafer manufacturing: A method of in-line characterization of ion implant process, during the SOI bond and cleave manufacturing or engineered silicon layer fabrication. In one embodiment, the method includes the steps of illuminating the engineered donor wafer using a modulated light source; performing a non-contact SPV measurement on the silicon wafer; measuring... Agent: Kirkpatrick & Lockhart Preston Gates Ellis LLP (formerly Kirkpatrick & Lockhart Nicholson Graham)

20080182348 - Impurity introducing method, impurity introducing apparatus, and electronic device produced by using those: An impurity doping method, includes a step of doping an impurity into a surface of a solid state base body, a step of measuring an optical characteristic of an area into which the impurity is doped, a step of selecting annealing conditions based on a measurement result to meet the... Agent: Pearne & Gordon LLP

20080182349 - Method for manufacturing display device: A display device which can be manufactured with improved material use efficiency and through a simplified manufacturing process, and a manufacturing technique thereof. A light-absorbing layer is formed, an insulating layer is formed over the light-absorbing layer, the light-absorbing layer and the insulating layer are selectively irradiated with laser light... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080182352 - Array substrate for lcd device having double-layered metal structure and manufacturing method thereof: The present invention is an array substrate for use in a liquid crystal display device, which includes a gate electrode, a gate line and a gate pad on a substrate, wherein the gate electrode, the gate line and the gate pad have a double-layered structure consisting of a first metal... Agent: Mckenna Long & Aldridge LLP

20080182351 - Liquid crystal display device and manufacturing method thereof: The present invention relates to a liquid crystal display device that is used in display portions of electronics devices and a manufacturing method thereof, and intends to provide a liquid crystal display device that can obtain excellent display quality and a manufacturing method thereof. The method of manufacturing a liquid... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20080182350 - Method for fabricating a pixel structure of a liquid crystal display: A method for fabricating a pixel structure of a liquid crystal device is provided. The method comprises providing a substrate defining a thin film transistor (TFT) region and a display region thereon. An opaque conductive layer is formed on the TFT region, and a transparent pixel electrode is formed on... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080182353 - Method for fabricating light emitting diodes: The invention is method for fabricating light emitting diodes. A layered semiconductor structure is provided on a growth substrate. The method includes using a pulsed laser to form an interfacial layer between the layered semiconductor structure and the growth substrate for subsequent substrate detachment and to simultaneously form light extracting... Agent: William Propp, Esq. Goldeneye, Inc.

20080182354 - Methods of fabricating cmos image sensors: CMOS image sensors and related methods of fabricating CMOS image sensors are disclosed. Fabrication of a CMOS image sensor can include forming a first impurity region having a first conductivity type in a semiconductor substrate. A second impurity region having a second conductivity type is formed in the semiconductor substrate... Agent: Myers Bigel Sibley & Sajovec

20080182355 - Conducting layer in chip package module: A conducting layer in a chip package module includes one or a plurality of through hole penetrating the top of a base being disposed at the bottom of an insulating layer in the chip package module, and inner wall of the through hole being applied with insulation material so that... Agent: Townsend And Townsend And Crew, LLP

20080182356 - Thin film transistor, method of manufacturing the same, and flat panel display using the thin film transistor: A thin film transistor, a method of manufacturing the same, and a flat panel display including the thin film transistor. The thin film transistor includes a gate electrode, a source electrode and a drain electrode, a first conductive layer connected to the gate electrode, a second conductive layer connected to... Agent: Robert E. Bushnell

20080182357 - Method of forming a memory device with switching glass layer: A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device.... Agent: Dickstein Shapiro LLP

20080182358 - Process for atomic layer deposition: The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising at least first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing... Agent: Andrew J. Anderson Patent Legal Staff

20080182359 - Techniques for providing decoupling capacitance: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or... Agent: Ryan, Mason & Lewis, LLP

20080182360 - Fabrication method of semiconductor package: A fabrication method of a semiconductor package is applied to fabricate the package with the lead frame. The fabrication method includes: performing a surface treatment on a carrier; electroplating a plurality of metal-stacked layers on the surface of the carrier, wherein the top of the metal-stacked layer is a bonding... Agent: Rosenberg, Klein & Lee

20080182361 - Techniques for providing decoupling capacitance: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or... Agent: Ryan, Mason & Lewis, LLP

20080182362 - Method for precision assembly of integrated circuit chip packages: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the... Agent: Schmeiser, Olsen & Watts

20080182363 - Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer: A method for forming a microelectronic assembly is provided. A carrier substrate (30) is provided. A sacrificial layer (38) is formed over the carrier substrate. A polymeric layer (40), including a polymeric tape (42) and a polymeric layer adhesive (44), is formed over the sacrificial layer. The polymeric layer adhesive... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080182364 - Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same: Methods for assembling a die-down array integrated circuit (IC) device packages with enhanced thermal, electrical, and input/output properties are presented. The method includes coupling a first surface of a substrate to a first surface of a heat spreader, mounting a first surface of an IC die to the first surface... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080182365 - Die package with asymmetric leadframe connection: A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on... Agent: Vierra Magen/sandisk Corporation

20080182366 - Hybrid module and method of manufacturing the same: A hybrid module includes a silicon substrate having a plurality of part mounting openings formed therein, the plurality of part mounting openings composed of through holes, a plurality of mounted parts that are mounted in the part mounting openings such that input/output portion forming surfaces are substantially flush with a... Agent: Robert J. Depke Lewis T. Steadman

20080182367 - Embedded memory in a cmos circuit and methods of forming the same: In some aspects, a method of forming a memory circuit is provided that includes (1) forming a two-terminal memory element on a substrate between a gate layer and a first metal layer of the memory circuit; and (2) forming a CMOS transistor on the substrate, the CMOS transistor for programming... Agent: Dugan & Dugan, PC

20080182368 - Method for production of thin-film semiconductor device: Disclosed herein is a method for production of a thin-film semiconductor device which includes, a first step to form a gate electrode on a substrate, a second step to form a gate insulating film of silicon oxynitride on the substrate in such a way as to cover the gate electrode,... Agent: Rader Fishman & Grauer PLLC

20080182369 - T-gate forming method and metamorphic high electron mobility transistor fabricating method using the same: A method for forming a T-gate of a metamorphic high electron mobility transistor is provided. The method includes sequentially laminating a plurality of resist films on a substrate; forming a T-shaped pattern in the laminated resist films using electron beam lithography; forming a gate metal layer on the substrate where... Agent: Bacon & Thomas, PLLC

20080182371 - Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss: By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions.... Agent: Williams, Morgan & Amerson

20080182370 - Methods for fabricating low contact resistance cmos circuits: Methods for fabricating low contact resistance CMOS integrated circuits are provided. In accordance with an embodiment, a method for fabricating a CMOS integrated circuit including an NMOS transistor and a PMOS transistor disposed in and on a silicon-comprising substrate includes depositing a first silicide-forming metal on the NMOS and PMOS... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080182372 - Method of forming disposable spacers for improved stressed nitride film effectiveness: A method of forming a complementary metal oxide semiconductor (CMOS) device includes forming an oxide layer on sidewalls and a top surface of a patterned gate conductor, and on sidewalls of a gate insulating layer formed on a semiconductor substrate; forming a first carbon-based layer over the gate conductor, gate... Agent: Cantor Colburn LLP-ibm Yorktown

20080182373 - Method for integrally forming an electrical fuse device and a mos transistor: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080182374 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes... Agent: Hogan & Hartson L.L.P.

20080182375 - Split gate memory cell method: A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area... Agent: Freescale Semiconductor, Inc. Law Department

20080182376 - Method of fabricating super trench mosfet including buried source electrode: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the... Agent: Patentability Associates

20080182377 - Method of forming a multi-bit nonvolatile memory device: In making a multi-bit memory cell, a first insulating layer is formed over a semiconductor substrate. A second insulating layer is formed over the first insulating layer. A layer of gate material is formed over the second insulating layer and patterned to leave a gate portion. The second insulating layer... Agent: Freescale Semiconductor, Inc. Law Department

20080182378 - Method of producing an integrated circuit having a capacitor: A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.... Agent: Dicke, Billig & Czaja

20080182379 - Semiconductor wafer with low-k dielectric layer and process for fabrication thereof: To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet... Agent: Freescale Semiconductor, Inc. Law Department

20080182380 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, comprises: (a) forming a first semiconductor layer on a semiconductor substrate in a first region and forming a second semiconductor layer on the semiconductor substrate in a second region, a thickness of the first semiconductor layer being larger than a thickness of the... Agent: Harness, Dickey & Pierce, P.L.C

20080182381 - Manufacturing method of semiconductor device using sti technique: A first trench and a second trench having width wider than the first trench are simultaneously formed in a main surface area of a semiconductor substrate. The width of an opening portion of the first trench is made narrower by forming a first insulating film on the main surface of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080182382 - Methods of thin film process: A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first... Agent: Townsend And Townsend And Crew LLP / Amat

20080182383 - Method of removing an oxide and method of filling a trench using the same: A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and removing the second byproducts.... Agent: Lee & Morse, P.C.

20080182386 - Controlled cleaving process: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define... Agent: Townsend And Townsend And Crew, LLP

20080182384 - Fabrication method of nitride-based semiconductor device: A fabrication method of a nitride-based semiconductor device includes the steps of forming a stacked structure constituted of a nitride-based semiconductor on a support substrate, depositing a first bonding metal on the stacked structure, depositing a second bonding metal on a retention substrate, bonding the first bonding metal and the... Agent: Morrison & Foerster LLP

20080182385 - Method for producing semiconductor device: A method for producing a semiconductor device includes bonding a transfer layer disposed on a first substrate to a second substrate and detaching the transfer layer from the first substrate. In bonding the transfer layer disposed on the first substrate to the second substrate, the method further includes placing a... Agent: Harness, Dickey & Pierce, P.L.C

20080182387 - Method of fabricating a semiconductor device employing electroless plating: A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an... Agent: Schein & Cai LLP

20080182389 - Low threshold voltage semiconductor device with dual threshold voltage control means: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other... Agent: Scully, Scott, Murphy & Presser, P.C.

20080182388 - Production device and production method for conductive nano-wire: Specifically, there is provided an electrolytic apparatus for forming a molecular assembly, including two electrodes and an electrolytic cell holding an electrolyte and the two electrodes, wherein the gap between the two electrodes is from 1 nm to 100 μm, by allowing the electrolytic cell to hold an electrolyte containing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080182390 - Methods of filling a set of interstitial spaces of a nanoparticle thin film with a dielectric material: A method of forming a densified nanoparticle thin film is disclosed. The method includes positioning a substrate in a first chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a... Agent: Foley & Lardner LLP

20080182391 - Doped nanoparticle semiconductor charge transport layer: A method is disclosed for making a doped semiconductor transport layer for use in an electronic device comprising: growing in-situ doped semiconductor nanoparticles in a colloidal solution; depositing the in-situ doped semiconductor nanoparticles on a surface; and annealing the deposited in-situ doped semiconductor nanoparticles so that the organic ligands boil... Agent: Frank Pincelli Patent Legal Staff

20080182392 - Method for fabricating polysilicon layer with large and uniform grains: An exemplary method for fabricating a polysilicon layer (208) includes the following steps. A substrate (200) is provided, and a first amorphous silicon layer (203) is formed over the substrate. Portions of the first amorphous silicon layer are removed through a photolithograph process to form a plurality of crystallization seeds... Agent: Wei Te Chung Foxconn International, Inc.

20080182393 - Gallium nitride materials and methods associated with the same: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the... Agent: Wolf Greenfield & Sacks, P.C.

20080182394 - Dual gate ldmos device and method: An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080182395 - Method for forming pattern in semiconductor device: A method for fabricating a dual polysilicon gate includes providing a substrate, forming a gate oxide layer over the substrate, forming a polysilicon layer over the gate oxide layer, patterning the polysilicon layer in a condition of applying a relatively low first pressure or a relatively high first bias power,... Agent: Townsend And Townsend And Crew, LLP

20080182396 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080182397 - Selective epitaxy process control: Methods of selectively and epitaxially forming a silicon-containing material on a substrate surface contained within a process chamber are provided. In one or more embodiments, the pressure in the process chamber is reduced during deposition of material on the substrate and increased during etching of material from the substrate. According... Agent: Diehl Servilla LLC

20080182399 - Methods of forming pad structures and related methods of manufacturing recessed channel transistors that include such pad structures: Methods of forming pad structures are provided in which a first contact region and second contact regions are formed in an active region of a substrate. An insulating interlayer is formed on the substrate. The insulating interlayer has a first opening that exposes the first contact region and the second... Agent: Myers Bigel Sibley & Sajovec

20080182398 - Varied solder mask opening diameters within a ball grid array substrate: A packaging assembly, such as a ball grid array package, is formed to reduce the effects of warpage by varying the size of solder ball aperture openings in the solder mask layer so that smaller solder ball aperture openings are located on the carrier substrate areas where warpage is higher... Agent: Hamilton & Terrile, LLP

20080182401 - Fabrication method of a semiconductor device: A semiconductor device and a fabrication method thereof are provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the... Agent: Edwards Angell Palmer & Dodge LLP

20080182400 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device is featured by including: a step for forming a bump on an electrode pad by a bonding wire, the electrode pad being formed in an area corresponding to a semiconductor chip of a substrate; a step in which a via hole is formed... Agent: Rankin, Hill & Clark LLP

20080182402 - Sub-lithographic interconnect patterning using self-assembling polymers: The present invention is directed to the formation of sublithographic features in a semiconductor structure using self-assembling polymers. The self-assembling polymers are formed in openings in a hard mask, annealed and then etched, followed by etching of the underlying dielectric material. At least one sublithographic feature is formed according to... Agent: International Business Machines Corporation Dept. 18g

20080182403 - Uv curing of pecvd-deposited sacrificial polymer films for air-gap ild: Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately 1. The air gap may generally be formed by depositing a sacrificial material between the respective conductive elements, depositing a... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080182404 - Novel air gap integration scheme: Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080182405 - Self-aligned air-gap in interconnect structures: An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the... Agent: Slater & Matsil, L.L.P.

20080182406 - Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080182407 - Method of forming vias in a semiconductor device: A via is formed in contact with a conductive line, whereby the via is offset from the conductive line so that the via extends beyond the conductive line. In accordance with a specific embodiment, a portion of the via contacts a sidewall of the conductive line.... Agent: Larson Newman Abel Polansky & White, LLP

20080182408 - Methods of forming carbon nano-tube wires on a catalyst metal layer and related methods of wiring semiconductor devices using such carbon nano-tube wires: In a method of forming a carbon nano-tube, an oxidized metal layer is formed on a substrate. An insulation layer having an opening is formed on the oxidized metal layer to expose a surface of the oxidized metal layer through the opening. The oxidized metal layer exposed through the opening... Agent: Myers Bigel Sibley & Sajovec

20080182409 - Method of forming a metal layer over a patterned dielectric by electroless deposition using a selectively provided activation layer: By forming an activation/nucleation layer selectively at a bottom of an opening, efficient electroless deposition techniques may be used for forming contacts, vias and trenches of advanced semiconductor devices. By selectively providing the activation material, a self-aligned bottom-to-top fill behavior may be obtained.... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080182410 - Passivated stoichiometric metal nitride films: Methods for forming passivated stoichiometric metal nitride films are provided along with structures incorporating such films. The preferred methods include contacting a substrate with alternating and sequential pulses of a metal source chemical, one or more plasma-excited species of hydrogen and a nitrogen source chemical to form a stoichiometric metal... Agent: Knobbe, Martens, Olsen & Bear LLP

20080182411 - Plasma-enhanced ald of tantalum nitride films: Methods of controllably producing conductive tantalum nitride films are provided. The methods comprise contacting a substrate in a reaction space with alternating and sequential pulses of a tantalum source material, plasma-excited species of hydrogen and nitrogen source material. The plasma-excited species of hydrogen reduce the oxidation state of tantalum, thereby... Agent: Knobbe, Martens, Olsen & Bear LLP

20080182412 - Configurable bevel etcher: A device for cleaning a bevel edge of a semiconductor substrate. The device includes: a lower support having a cylindrical top portion; a lower plasma-exclusion-zone (PEZ) ring surrounding the outer edge of the top portion and adapted to support the substrate; an upper dielectric component opposing the lower support and... Agent: Buchanan, Ingersoll & Rooney PC

20080182413 - Selective chemistry for fixed abrasive cmp: Methods and compositions for planarizing a substrate surface with selective removal rates and low dishing are provided. One embodiment provides a method for selectively removing a dielectric disposed on a substrate having at least a first and a second dielectric material disposed thereon. The method generally includes positioning the substrate... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080182414 - Mass production method of semiconductor integrated circuit device and manufacturing method of electronic device: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the... Agent: Miles & Stockbridge PC

20080182415 - Semiconductor device and method for fabricating the same: A semiconductor device comprises a semiconductor substrate including a scribe lane, and a metal layer disposed over the semiconductor substrate. The metal layer is formed over the overlay vernier by a sputtering method. The overlay vernier comprises a bar type mother vernier formed in the scribe lane. The overlay vernier... Agent: Townsend And Townsend And Crew, LLP

20080182417 - Plasma process uniformity across a wafer by apportioning ground return path impedances among plural vhf sources: In a plasma reactor chamber a ceiling electrode and a workpiece support electrode, respective RF power sources of respective VHF frequencies f1 and f2 are coupled to either respective ones of the electrodes or to a common one of the electrodes, where f1 is sufficiently high to produce a center-high... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20080182416 - Plasma process uniformity across a wafer by apportioning power among plural vhf sources: A method is provided for processing a workpiece in a plasma reactor chamber having electrodes including at least a ceiling electrode and a workpiece support electrode. The method includes coupling respective RF power sources of respective VHF frequencies f1 and f2 to either (a) respective ones of the electrodes or... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20080182418 - Plasma process uniformity across a wafer by controlling a variable frequency coupled to a harmonic resonator: A method of processing a workpiece in a plasma reactor chamber includes coupling RF power via an electrode to plasma in the chamber, the RF power being of a variable frequency in a frequency range that includes a fundamental frequency f. The method also includes coupling the electrode to a... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20080182419 - Plasma processing method: The invention provides a method for subjecting laminated thin films disposed below a photoresist mask pattern to plasma processing, wherein the roughness on the side walls of the formed pattern is reduced, and the LER and LWR are reduced. When etching a material to be processed to form a gate... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080182420 - Ion beam treatment for the structural integrity of air-gap iii-nitride devices produced by the photoelectrochemical (pec) etching: A method for ensuring the structural integrity of III-nitride opto-electronic or opto-mechanical air-gap nano-structured devices, comprising (a) performing ion beam implantation in a region of the III-nitride opto-electronic and opto-mechanical air-gap nano-structured device, wherein the milling significantly locally modifies a material property in the region to provide the structural integrity;... Agent: Gates & Cooper LLP Howard Hughes Center

20080182421 - Substrate processing method and substrate processing apparatus: A substrate processing method that can selectively remove deposit produced through dry etching of silicon. A substrate has a silicon base material and a hard mask that is made of a silicon nitride film and/or a silicon oxide film and formed on the silicon base material, the hard mask having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080182422 - Methods of etching photoresist on substrates: Methods of etching a carbon-rich layer on organic photoresist overlying an inorganic layer can utilize a process gas including a fluorine-containing gas, an oxygen-containing gas, and a hydrocarbon gas, and one or more optional components to generate a plasma effective to etch the carbon-rich layer with low removal of the... Agent: Buchanan, Ingersoll & Rooney PC

20080182423 - Substrate processing apparatus and gas supply method: A substrate processing apparatus that can prevent formation of deposit in openings of a plurality of gas supply holes leading into a processing chamber. Each of the gas supply holes is configured to uniformly supply a processing gas, whose molecules are turned into clusters, into the processing chamber and to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080182424 - Method for selectively controlling lengths of nanowires: A method for selectively controlling lengths of nanowires in a substantially non-uniform array of nanowires includes establishing at least two different catalyzing nanoparticles on a substrate. A nanowire from each of the at least two different catalyzing nanoparticles is substantially simultaneously grown. At least one of the nanowires has a... Agent: Hewlett Packard Company

20080182425 - Bubbler apparatus and method for delivering vapor phase reagent to a deposition chamber: The apparatus further has a temperature sensor and a source chemical level sensor extending through a centrally located portion of the top wall member and generally vertically downwardly to a sump cavity centrally located on a bottom wall member. The dispensing apparatus may be used for dispensing of reagents such... Agent: Praxair, Inc. Law Department - M1 557

20080182426 - Method for growing nitride semiconductor: A method for growing a nitride semiconductor has a first step for forming a surface reformation layer on a sapphire substrate, a second step for raising a temperature of the sapphire substrate with the surface reformation layer formed thereon up to a growth temperature of the nitride semiconductor in an... Agent: Mcginn Intellectual Property Law Group, PLLC

20080182427 - Deposition method for transition-metal oxide based dielectric: The present invention relates to a method for depositing a dielectric material comprising a transition metal oxide. In an initial step, a substrate is provided. In a further step, a first precursor comprising a transition metal containing compound, and a second precursor predominantly comprising at least one of water vapor,... Agent: Eschweiler & Associates LLC

20080182428 - Electronic device including a layer of discontinuous storage elements and a process for forming the electronic device: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at... Agent: Larson Newman Abel Polansky & White, LLP

20080182429 - Semiconductor manufacturing system and method of manufacturing semiconductor device: A semiconductor manufacturing system, having a filter that is disposed in a clean room and removes an organic solvent containing siloxane from a gas supplied from the outside of said clean room; a first semiconductor manufacturing apparatus that is disposed in said clean room and uses light in an atmosphere... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080182430 - Multiple-time flash anneal process: A method of forming an integrated circuit is provided. The method includes performing a multiple-time flash anneal process to a wafer, wherein the multiple-time flash anneal process comprises preheating the wafer to a first preheat temperature; performing a first flash on the wafer with a first flash energy; preheating the... Agent: Slater & Matsil, L.L.P.

20080176343 - Method for smart dummy insertion to reduce run time and dummy count: A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and... Agent: Haynes And Boone, LLP

20080176344 - Feature dimension control in a manufacturing process: A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080176345 - Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes: Gate dielectric punch through and/or incomplete silicidation or metallization events that may occur during transistor formation are identified. The events are identified just after gate electrodes are formed in order to characterize the degree of faulty transistors for process control purposes and to scrap product if sufficiently defective so that... Agent: Texas Instruments Incorporated

20080176346 - Method for manufacturing pixel structure: A method for manufacturing a pixel structure includes providing a substrate having an active device thereon and forming a dielectric layer covering the active device. Then, an uneven first photoresist layer having an opening is formed over the active device. After an etching process is implemented to form a contact... Agent: Jianq Chyun Intellectual Property Office

20080176348 - Array substrate of liquid crystal display and fabrication method thereof: Provided is an array substrate of an LCD that includes a substrate, an active layer, a first insulating layer, and a gate electrode sequentially formed on the substrate. A source region and a drain region reside in predetermined regions of the active layer and each is doped with impurity ions.... Agent: Brinks Hofer Gilson & Lione

20080176347 - Method for manufacturing wiring, thin film transistor, light emitting device and liquid crystal display device, and droplet discharge apparatus for forming the same: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a... Agent: Nixon Peabody, LLP

20080176350 - Method and apparatus providing cmos imager device pixel with transistor having lower threshold voltage than other imager device transistors: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions... Agent: Dickstein Shapiro LLP

20080176349 - Tft, flat panel display device having the same, method of manufacturing tft, method of manufacturing flat panel display device, and method of manufacturing donor sheet: A flexible flat panel display where nanoparticles are used for the active layer of the TFTs and the substrate is flexible and can be manufactured at room temperature, a flat panel display device having the same, a method of manufacturing a TFT, a method of manufacturing a flat panel display... Agent: Robert E. Bushnell

20080176351 - Manufacturing method of display device: The present invention provides a manufacturing method of a display device which can prevent the reduction of a size of a pseudo single-crystalline region having strip-like crystals in forming such a pseudo single-crystalline silicon region on a substrate. A step for forming pseudo single crystals having strip-like crystals on a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080176352 - Semiconductor laser device: This semiconductor laser device has the same structure as the conventional broad-area type semiconductor laser device, except that both side regions of light emission areas of active and clad layers are two-dimensional-photonic-crystallized. The two-dimensional photonic crystal formed on both side regions of the light emission area is the crystal having... Agent: Rader Fishman & Grauer Pllc

20080176353 - Semiconductor light emitting element and method for manufacturing the same: A high-luminance light emitting element is manufactured by a method comprising: forming a light emitting layer on a first surface of a GaP substrate including the first surface and a second surface opposed to the first surface and having an area smaller than the first area, the light emitting layer... Agent: Hogan & Hartson L.l.p.

20080176355 - Diode energy converter for chemical kinetic electron energy transfer: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring... Agent: Orrick, Herrington & Sutcliffe LLP Suite 1600

20080176356 - Diode energy converter for chemical kinetic electron energy transfer: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring... Agent: Orrick, Herrington & Sutcliffe LLP Suite 1600

20080176354 - Method of uniform current distribution using current modified layer: An electric device has a p-n diode, where the p-n diode is covered with a current modified layer (CML). With a resistance distribution of the CML, a current is decreased toward all directions from a point on a bonding pad between the CML and the p-n diode. Hence, a current... Agent: Troxell Law Office Pllc Suite 1404

20080176357 - Method for making a photovoltaic cell based on thin-film silicon: The invention concerns a method for making a photovoltaic cell based on thin film silicon, which consists in providing a heterojunction by depositing on a support at least one first P— (or N—) doped amorphous silicon layer (13) and a second N— (or P—) doped amorphous silicon layer (14), in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080176358 - Fabrication method of multichip stacking structure: The present invention provides a fabrication method of a multi-chip stacking structure. The method includes steps of: stacking the first chips on the chip carrier in a step-like manner to form a first chip module; electrically connecting the first chip module to the chip carrier by a plurality of first... Agent: Edwards Angell Palmer & Dodge LLP

20080176359 - Method for manufacturing of electronics package: A method for manufacturing an electronics package is provided in which a carrier is provided, at least one electronic component is placed on the carrier and a base layer is then deposited on the electronic component(s). The base layer may include a dielectric layer binding the electronic component(s) to the... Agent: Alston & Bird LLP

20080176360 - Method for sawing a wafer and method for manufacturing a semiconductor package by using a multiple tape: A method for sawing a wafer includes the following steps. A wafer which has an active surface, a back surface and a plurality of longitudinal and transverse sawing lines is provided, wherein the sawing lines are located on the active surface so as to define a plurality of dies. A... Agent: Lowe Hauptman Ham & Berner, LLP

20080176361 - Manufacturing method of electronic device: A manufacturing method of manufacturing an electronic device, includes the steps of: applying a thermosetting adhesive on a surface of a base having a conductive pattern formed on a film; mounting a circuit chip on the base through the thermosetting adhesive; holding the base while pressing a circuit chip side... Agent: Greer, Burns & Crain

20080176362 - Stress free package and laminate-based isolator package: Various methods are described where the semiconductor die and the lead frame (or the BGA or LGA substrate) are spaced apart to reduce stress. In one scenario, an air gap is formed between the semiconductor die and the lead frame by depositing a perimeter (made, for example, using polymer) either... Agent: Gauthier & Connors, LLP

20080176364 - Method of manufacturing thin film transistor substrate: The present invention provides a method for manufacturing a thin film transistor substrate including forming gate wires on an insulation substrate, forming oxide active layer patterns on the gate wires, forming data wires on the oxide active layer patterns so that the data wires cross the gate wires, forming a... Agent: H.c. Park & Associates, Plc

20080176363 - Virtual body-contacted trigate: A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080176365 - Method of making double-gated self-aligned finfet having gates of different lengths: A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially... Agent: International Business Machines Corporation Dept. 18g

20080176366 - Method for fabricating aigan/gan-hemt using selective regrowth: A semiconductor body includes, on a substrate, a stack of buffer layer, UID-GaN layer overlying the buffer layer, and UID-AlGaN layer overlying the UID-GaN layer. On the surface of the UID-AlGaN layer, an insulation film is deposited and patterned. An n+-GaN layer is selectively regrown directly on a region of... Agent: Rabin & Berdo, Pc

20080176367 - Field effect transistor and fabrication thereof, semiconductor device and fabrication thereof, logic circuit including the semiconductor device, and semiconductor substrate: A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon layer. The FET may be formed as a gate electrode of a p-channel type field effect transistor,... Agent: Rader Fishman & Grauer Pllc

20080176368 - Semiconductor device: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080176369 - Method of manufacturing semiconductor device including insulated-gate field-effect transistors: A method of manufacturing a semiconductor device including MOS transistors is disclosed. N-type and p-type semiconductor films are formed respectively above first and second surface regions of a semiconductor substrate. First and second protective films are laminated on the semiconductor films. The second protective film is selectively etched to form... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080176370 - Method for fabricating semiconductor device: In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080176371 - Method of making a non-volatile memory device: A method forms a nonvolatile memory device using a semiconductor substrate. A charge storage layer is formed overlying the semiconductor substrate and a layer of gate material is formed overlying the charge storage layer to form a control gate electrode. A protective layer overlies the layer of gate material. Dopants... Agent: Freescale Semiconductor, Inc. Law Department

20080176372 - Method of manufacturing a mosfet structure: A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of... Agent: Fogg & Powers Llc

20080176374 - Methods of forming semiconductor devices using self-aligned metal shunts: A method of fabricating a semiconductor device using a self-aligned metal shunt process is disclosed. The method can include sequentially forming a lower conductive pattern and a sacrificial pattern on a semiconductor substrate. An interlayer dielectric layer is formed to cover the sacrificial pattern. The interlayer dielectric layer is patterned... Agent: Myers Bigel Sibley & Sajovec

20080176373 - Semiconductor device and manufacturing method for the same: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a... Agent: Foley And Lardner LLP Suite 500

20080176375 - Method for forming a dielectric layer: The present invention relates to a deposition of a dielectric layer. On a substrate having a structured area a crystallization seed layer for a dielectric layer is deposited via an atomic layer deposition technique employing a first and a second precursor on the structured area of the substrate. The first... Agent: Coats & Bennett/qimonda

20080176376 - Making method for product information: A product information marking method including a back side grinding step for grinding the back side of a wafer having a plurality of devices formed on the front side so as to be partitioned by a plurality of separation lines, thereby obtaining a desired thickness of the wafer. After performing... Agent: Greer, Burns & Crain

20080176377 - Method of manufacturing semiconductor device: (d) forming a conductor (11) on the epitaxial film (31) provided on the diffusion region (41) by processing a conductive film into a columnar form, wherein the step (c) includes (c1) forming the second insulating film (32 & 33) so that the thickness thereof is larger than that of a... Agent: Sughrue Mion, Pllc

20080176378 - Multiple-depth sti trenches in integrated circuit fabrication: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a... Agent: Leffert Jay & Polglaze, P.a.

20080176379 - Method for forming isolation structure in semiconductor device: A method for forming an isolation structure in a semiconductor device including a substrate having a first region and a second region, the second region having an isolation structure formed to a larger width than a plurality of isolation structures formed in the first region, is provided. The method includes... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080176380 - Method for manufacturing compound material wafers and corresponding compound material wafer: The invention relates to a method for manufacturing compound material wafers, in particular, silicon on insulator type wafers, by providing an initial donor substrate, forming an insulating layer over the initial donor substrate, forming a predetermined splitting area in the initial donor substrate, attaching the initial donor substrate onto a... Agent: Winston & Strawn LLP Patent Department

20080176382 - Process of forming and controlling rough interfaces: The invention provides a method for forming a semiconductor component with a rough buried interface. The method includes providing a first semiconductor substrate having a first surface of roughness R1. The method further includes thermally oxidizing the first surface of the first semiconductor substrate to form an oxide layer defining... Agent: Edwards Angell Palmer & Dodge LLP

20080176381 - Surface roughening process: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material... Agent: Edwards Angell Palmer & Dodge LLP

20080176383 - Manufacturing apparatus of semiconductor device and method for manufacturing semiconductor device: To provide a manufacturing apparatus of a semiconductor device, which does not use a stepper in a manufacturing process in the case where mass production of semiconductor devices is carried out by using a large-sized substrate. A thin film formed over a substrate having an insulating surface is selectively irradiated... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080176384 - Methods of forming impurity regions in semiconductor devices: Provided according to some embodiments of the present invention are methods of forming an impurity region in a semiconductor device. Such methods may include forming a pad oxide layer on a substrate; providing impurities to the substrate to form a preliminary impurity region in the substrate; performing a heat treatment... Agent: Myers Bigel Sibley & Sajovec

20080176385 - Method for manufacturing a semiconductor device: A method of manufacturing a semiconductor device, comprises; a) forming a SiGe layer on a substrate; b) forming a Si layer on the SiGe layer ; c) forming a groove that exposes the side surface of the SiGe layer by partly etching the Si layer and the SiGe layer; and... Agent: Oliff & Berridge, Plc

20080176386 - Method of producing gallium nitride (gan) independent substrate, method of producing gan crystal body, and method of producing gan substrate: A method of producing a separated GaN crystal body grown by vapor phase epitaxy on a substrate made of material different from GaN is provided. In this method, a nitride deposit is formed during the growth on a periphery of the substrate and GaN crystal body. The present method comprises... Agent: Mcdermott Will & Emery LLP

20080176387 - Plasma doping methods using multiple source gases: A plasma doping method includes providing a substrate including a layer to be doped inside a chamber, and supplying first and second source gases to the layer to achieve a desired doping concentration. The first source gas includes a component configured to increase a thickness of the layer, and the... Agent: Myers Bigel Sibley & Sajovec

20080176388 - Methods for removing photoresist from semiconductor structures having high-k dielectric material layers: Methods for removing photoresist from semiconductor structures are provided. In an exemplary embodiment, a method for removing photoresist from a semiconductor structure having a high-k dielectric material layer overlying a substrate comprises depositing a photoresist overlying the high-k dielectric material layer and patterning the photoresist. The temperature of the substrate... Agent: Ingrassia Fisher & Lorenz, P.c. (amd)

20080176389 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080176390 - Method of forming carbon-containing silicon nitride layer: A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia and at least one carbon-source precursor as reactant gases is provided.... Agent: Jianq Chyun Intellectual Property Office

20080176391 - Method for manufacturing semiconductor device: The present invention has an object of providing a method for manufacturing a semiconductor device which can prevent occurrence of pattern abnormality of an electrode and deterioration of an electronic property. The method for manufacturing the semiconductor device including a GaAs substrate with a portion made of GaAs includes: forming... Agent: Greenblum & Bernstein, P.L.C

20080176392 - Method of fabricating grayscale mask using smart cut® wafer bonding process: A method of fabricating a grayscale mask includes preparing a silicon wafer; depositing a layer of Si3N4 directly on the silicon wafer; implanting H+ ions into the silicon wafer to form a defect layer; depositing a first layer of SiOxNy directly on the Si3N4 layer; depositing a layer of SRO... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080176393 - Bumping electronic components using transfer substrates: A method for forming solder bumps on an electronic component. Providing a transfer substrate having a plurality of solder balls, disposing the transfer substrate on the surface of the electronic component, heating to reflow the solder balls onto the electronic component; and removing the sacrificial substrate. The transfer substrate may... Agent: Gerald E. Linden

20080176394 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. The method may include forming a metal interconnection on a substrate, forming a liner layer on the substrate including the metal interconnection, performing a plasma process to an entire surface of the substrate including the liner layer, and forming a dielectric... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080176395 - Copper interconnect systems: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least... Agent: Woodcock Washburn LLP

20080176396 - Manufacturing method of semiconductor device: An object of the invention is to avoid an inconvenience at a connection portion formed by filling a metal film in a connecting hole, which has been opened in an insulating film, via a barrier metal film having a titanium nitride film stacked over a titanium film. A manufacturing method... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080176397 - Methods to completely eliminate or significantly reduce defects in copper metallization in ic manufacturing: A method for the improved electroplating of copper onto a copper seed layer provides treating the surface of a copper seed layer with nitrogen or another anaerobic gas. In another aspect, a burnishing treatment is used to enhance the platability of the copper seed layer. According to another aspect, the... Agent: Duane Morris, LLP Ip Department

20080176398 - High throughput, low cost dual-mode patterning method for large area substrates: Methods of the present invention provide a high-throughput, low cost, patterning platform that is an alternative to conventional photolithography and direct laser ablation patterning techniques. The present processing methods are useful for making patterns of microsized and/or nanosized structures having accurately selected physical dimensions and spatial orientation that comprise active... Agent: Greenlee Winner And Sullivan P C

20080176399 - Metallic silicide forming method and method of manufacturing semiconductor device: A metallic silicide forms method of forming a metallic silicide layer on a semiconductor region containing silicon. The method includes the steps of: forming a first metal layer containing a first metal on the semiconductor region; forming a second metal layer containing a second metal on the semiconductor region to... Agent: Sonnenschein Nath & Rosenthal LLP

20080176400 - Iii-v compound semiconductor substrate manufacturing method: Affords a III-V compound semiconductor substrate manufacturing method that enables enhancement of the substrate PL intensity. In such a III-V compound semiconductor substrate manufacturing method, first, the surface 3a of a wafer 3 is polished (polishing step). Second, the surface 3a of the wafer 3 is cleaned (first cleaning step... Agent: Judge Patent Associates

20080176402 - Method for fabricating semiconductor device with recess gate: A method for fabricating a semiconductor device includes providing a substrate, forming a sacrificial oxide layer over the substrate, the sacrificial layer having a higher etch rate than the substrate, forming a hard mask pattern over the sacrificial oxide layer, wet-etching the sacrificial oxide layer using the hard mask pattern... Agent: Lowe Hauptman Ham & Berner, LLP

20080176401 - Method for forming contact hole: A method for forming a contact hole. The method comprises steps of performing a substrate having at least a dielectric layer formed thereon and then forming a patterned mask layer on the dielectric layer, wherein the patterned mask layer exposes a portion of the dielectric layer. The dielectric layer is... Agent: J C Patents, Inc.

20080176403 - Method of polishing a layer and method of manufacturing a semiconductor device using the same: In a method of chemically and mechanically polishing a layer, a substrate on which the layer having stepped portions is formed is prepared. The layer is primarily chemically and mechanically polished at a temperature of about 30° C. to about 80° C. to remove the stepped portions of the layer.... Agent: Mills & Onello LLP

20080176404 - Method for fabricating semiconductor device: The method for fabricating the semiconductor device comprises the step of forming an insulating film 14 having an opening 18; the step of forming an organic resist film 20a; the step of forming over the organic resist film 20a a mask film 20b having etching characteristics different from those of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080176405 - Method of cleaning a surface of a cobalt-containing material, method of forming an opening to a cobalt-containing material, semiconductor processing method of forming an integrated circuit comprising a copper-containing conductive line, and a cobalt-conta: The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material, semiconductor processing methods of forming an integrated circuit comprising a copper-containing conductive line, and cobalt-containing film cleaning solutions. In one implementation, a method of cleaning a surface of a... Agent: Wells St. John P.s.

20080176407 - Method of manufacturing semiconductor device: A semiconductor device manufacturing method includes: a step of implementing etching onto a film formed on a semiconductor wafer; and a removal step of supplying, after etching, a removing solution for removing deposition on the film to a semiconductor wafer in the state where the number of rotations thereof is... Agent: Mcginn Intellectual Property Law Group, Pllc

20080176406 - Methods for fabricating semiconductor structures: Methods for fabricating semiconductor structures are provided. A first layer may be deposited onto a substrate followed by the deposition of a second layer onto the first layer. A plurality of line structures may be etched in the second layer. A third layer, deposited onto the plurality of line structures... Agent: Fulbright & Jaworski L.l.p.

20080176409 - Etching method and etching equipment: The invention provides an etching method for realizing trench etching without causing any damages to the side walls of the trench while maintaining a high-etching rate. The plasma etching method relates to forming a groove or a hole by forming a silicon trench to a silicon substrate or a silicon... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080176408 - Method and apparatus for manufacturing semiconductor devices, control program and computer-readable storage medium: A method for manufacturing a semiconductor device includes mounting a target substrate on a mounting table in a processing chamber; performing a plasma etching process via a resist mask; and performing an ashing process for removing the resist mask in the same processing chamber. Further, a temperature control of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080176410 - Method for forming a coating with a liquid, and method for manufacturing a semiconductor device: A method of forming a liquid coating on a substrate that reduces the amount of consumption of the coating liquid and achieves a more even distribution of the thickness of the liquid coating film. The method may include supplying a solvent to a surface of a substrate, starting a supply... Agent: Orrick, Herrington & Sutcliffe, LLP Ip Prosecution Department

20080176411 - Techniques for providing decoupling capacitance: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or... Agent: Ryan, Mason & Lewis, LLP

20080176412 - Atomic layer deposition system including a plurality of exhaust tubes: An atomic layer deposition system includes a reaction chamber, a plurality of exhaust tubes communicated to the reaction chamber, a plurality of first vacuum gauges for monitoring the degree of vacuum of the respective exhaust tubes, a second vacuum gauge for monitoring the degree of vacuum of the reaction chamber,... Agent: Young & Thompson

20080176413 - Selective plasma processing method: A selective plasma processing method, within a processing chamber of a plasma processing apparatus, acts oxygen-containing plasma on a target object having silicon and a silicon nitride layer to selectively oxidize the silicon with respect to the silicon nitride layer and to form a silicon oxide film. Further, the ratio... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080176414 - Systems and methods for inducing crystallization of thin films using multiple optical paths: The present invention is directed to systems and methods for irradiating regions of a thin film sample(s) with laser beam pulses having different energy beam characteristics that are generated and delivered via different optical paths. An exemplary method includes generating laser beam pulses having energy beam characteristics, directing a first... Agent: Wilmerhale/columbia University

20080176415 - Wafer support pin for preventing slip dislocation during annealing of water and wafer annealing method using the same: A wafer support pin has a front end contacted with a wafer such that the front end is flat or rounded. Thus, gravitational stress is minimized during annealing the wafer, thereby minimizing slip dislocation. This wafer support pin is suitably used for annealing of a wafer, particularly high temperature rapid... Agent: Greer, Burns & Crain

20080171401 - Device for repairing conducting line and repairing method using same: An exemplary repairing method includes providing a substrate having a plurality of conducting lines; detecting a broken position of one of the conducting lines; switching on a nozzle; and forming a copper layer at the broken position on the substrate. The repairing method of the present invention employing a repairing... Agent: Wei Te Chung Foxconn International, Inc.

20080171402 - Method of fabricating a semiconductor multi-package module having inverted land grid array (lga) package stacked over ball grid array (bga) package: A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between... Agent: Law Offices Of Mikio Ishimaru

20080171403 - Novel compound and method of producing organic semiconductor device: A method of producing an organic semiconductor device is provided in which a layer composed of an organic semiconductor having excellent crystallinity and orientation in a low-temperature region can be formed, and the device can be produced in the air. The method includes forming a layer composed of an organic... Agent: Fitzpatrick Cella Harper & Scinto

20080171405 - Integrated circuit package system with leads having multiple sides exposed: An integrated circuit package system includes forming an integrated circuit stack having a bottom non-active side and a top non-active side; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack; and forming an encapsulation, having both a non-elevated portion... Agent: Law Offices Of Mikio Ishimaru

20080171404 - Method and device for mutual contacting of two wafers: A method and a device for the mutual contacting of two wafer-type component composite configurations made of multiple identical components which are implemented coherently, in particular a semiconductor wafer (12) with a functional component wafer (14), to produce electronic assemblies on the wafer level, in which the component composite configurations... Agent: Blakely Sokoloff Taylor & Zafman

20080171406 - Methods of forming integrated circuit devices using composite spacer structures: Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and... Agent: Vierra Magen/sandisk Corporation

20080171407 - Manufacturing method of fin-type field effect transistor: A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is... Agent: Pearne & Gordon LLP

20080171408 - Methods for forming dual fully silicided gates over fins of finfet devices: Methods for forming fully silicided gates over fins of FinFet devices are disclosed. The disclosure provides methods for patterning a gate stack over each fin from a polysilicon layer and a polysilicon germanium layer, and then removing the polysilicon germanium layer over one of the fins. The disclosure further includes... Agent: Hoffman Warnick LLC

20080171409 - Method for fabricating bottom-gate low-temperature polysilicon thin film transistor: The present invention discloses a method for fabricating a bottom-gate low-temperature polysilicon thin film transistor, wherein the bottom gate structure is used to form an amorphous silicon layer with varied thicknesses; the amorphous silicon layer in the step region on the border of the bottom gate structure is partially melted... Agent: Sinorica, LLC

20080171410 - Method for manufacturing crystalline semiconductor film and semiconductor device: There is provided a method for manufacturing a crystalline semiconductor film. An insulating film is formed over a substrate; an amorphous semiconductor film is formed over the insulating film; a cap film is formed over the amorphous semiconductor film; the amorphous semiconductor film is scanned and irradiated with a continuous... Agent: Nixon Peabody, LLP

20080171411 - Nonvolatile semiconductor memory element excellent in charge retention properties and process for producing the same: In a process for producing nonvolatile semiconductor memory element comprising a floating gate made of a hardly oxidizable material having a Gibbs' formation free energy for forming its oxide higher than that of Si in a range of from 0° C. to 1,200° C., and an insulator made of an... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080171412 - Fabrication methods for mos device and cmos device: Fabrication methods for a MOS device and a CMOS device are provided. A substrate is provided with a gate structure formed on the substrate, a lightly-doped drain (LDD) region formed near sides of the gate structure in the substrate and a spacer wall formed on sidewalls of the gate structure... Agent: J C Patents, Inc.

20080171413 - Method of reducing detrimental sti-induced stress in mosfet channels: A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20080171414 - Method of fabricating semiconductor devices having a gate silicide: A method of fabricating a semiconductor device according to an example embodiment may include forming an isolation layer defining an active region in a semiconductor substrate, forming a silicon pattern and a sacrificial pattern on the active region, the sacrificial pattern including a semiconductor material different from the silicon pattern,... Agent: Harness, Dickey & Pierce, P.L.C

20080171415 - Methods of forming nand memory with virtual channel: A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma... Agent: Vierra Magen/sandisk Corporation

20080171416 - Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and... Agent: Wagner, Murabito & Hao LLP Two North Market Street

20080171417 - Method and apparatus for reducing patterning effects on a substrate during radiation-based heating: Patterning effects on a substrate are reduced during radiation-based heating by filtering the radiation source or configuring the radiation source to produce radiation having different spectral characteristics. For the filtering, an optical filter may be used to truncate specific wavelengths of the radiation. The different configurations of the radiation source... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080171418 - Method to fabricate passive components using conductive polymer: A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080171419 - Method for forming soi device: A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die... Agent: Birch Stewart Kolasch & Birch

20080171420 - Structure and method to form improved isolation in a semiconductor device: A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched... Agent: Scully, Scott, Murphy & Presser, P.C.

20080171421 - Manufacturing method of semiconductor device with smoothing: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding... Agent: Morrison & Foerster LLP

20080171422 - Apparatus and methods for fabrication of thin film electronic devices and circuits: Methods and systems for forming layered electronic devices on a flexible, elongated substrate are described. The layered electronic devices include at least one electronically or optically active layer. Deposition of one more layers of the electronic devices occurs as the flexible substrate is moved through one or more deposition stations.... Agent: 3m Innovative Properties Company

20080171423 - Low-cost strained soi substrate for high-performance cmos technology: A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor... Agent: Scully, Scott, Murphy & Presser, P.C.

20080171424 - Epitaxial growth of gan and sic on silicon using nanowires and nanosize nucleus methodologies: A method of fabricating a continuous layer of a defect sensitive material on a silicon substrate includes preparing a silicon substrate; forming a nanostructure array directly on the silicon substrate; depositing a selective growth enhancing layer on the substrate; smoothing the selective growth enhancing layer; and growing a continuous layer... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080171425 - Methods of forming an epitaxial layer on a group iv semiconductor substrate: A method of forming an epitaxial layer in a chamber is disclosed. The method includes positioning a Group IV semiconductor substrate in the chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV nanoparticles and a solvent, wherein a porous compact is formed. The method... Agent: Foley & Lardner LLP

20080171426 - Uniaxial strain relaxation of biaxial-strained thin films using ion implantation: A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block structure. The strain in the uncovered region is relaxed by ion implantation, which induces... Agent: Scully, Scott, Murphy & Presser, P.C.

20080171427 - Eeprom memory cell with controlled geometrical features: A method of fabricating structures in an electronic device by forming and patterning a first film layer on a substrate into ridges with a photolithographic system. The ridges are formed from an image produced by a first simple geometry photomask where the first photomask has at least one first slot-like... Agent: Schneck & Schneck

20080171428 - Methods of forming spacer patterns using assist layer for high density semiconductor devices: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a... Agent: Vierra Magen/sandisk Corporation

20080171429 - Semiconductor device including a floating gate electrode having stacked structure: A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080171431 - Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and... Agent: Slater & Matsil, L.L.P.

20080171430 - Methods of forming through-substrate interconnects: In one embodiment of a method of forming at least one through-substrate interconnect, a semiconductor substrate having first surface and an opposing second surface is provided. At least one opening is formed in the semiconductor substrate to extend from the first surface to an intermediate depth within the semiconductor substrate.... Agent: Hewlett Packard Company

20080171432 - Circuit structure with low dielectric constant regions and method of forming same: A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality of gap openings is formed above the first... Agent: Ryan, Mason & Lewis, LLP

20080171433 - Damascene interconnection structure and dual damascene process thereof: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on... Agent: North America Intellectual Property Corporation

20080171434 - Method of fabricating dual damascene structure: A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole... Agent: J C Patents, Inc.

20080171435 - Vacuum processing apparatus, method for manufacturing semiconductor device, and system for manufacturing semiconductor device: A vacuum processing apparatus including at least three transfer chambers that have transfer robot arms for transferring a substrate, one or more processing chambers connected to each of the transfer chambers; one or more substrate mounts disposed in the interior thereof; a single common vacuum chamber in which the transfer... Agent: Buchanan, Ingersoll & Rooney PC

20080171436 - Methods of depositing a ruthenium film: Cyclical methods of depositing a ruthenium film on a substrate are provided. In one process, each cycle includes supplying a ruthenium organometallic compound gas to the reactor; purging the reactor; supplying a ruthenium tetroxide (RuO4) gas to the reactor; and purging the reactor. In another process, each cycle includes simultaneously... Agent: Knobbe Martens Olson & Bear LLP

20080171437 - Methods of forming titanium-containing materials: The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance, the invention can utilize alternating cycles of titanium tetrachloride and activated hydrogen to form... Agent: Wells St. John P.s.

20080171438 - Methods of uniformly removing silicon oxide, a method of removing a sacrifical oxide, and an intermediate semiconductor device structure: A method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein or more than one density or strain therein. The silicon oxide having at least one cavity or more than one density or strain is exposed to a gaseous... Agent: Trask Britt, P.C./ Micron Technology

20080171440 - Pre-polishing treatment solution for interconnect substrate, polishing method, and method and apparatus for manufacturing interconnect substrate: A pre-polishing treatment solution has a prominent corrosion inhibiting effect, and can be used in pre-polishing treatments for interconnect substrates. The pre-polishing treatment solution comprises a corrosion inhibitor dissolved in an organic solvent.... Agent: Wenderoth, Lind & Ponack, L.L.P.

20080171439 - Recycling of ion implantation monitor wafers: A wafer processing method. The method includes providing a semiconductor wafer. The semiconductor wafer includes (i) a semiconductor layer and (ii) a dopant layer on top of the semiconductor layer. The dopant layer comprises dopants. The method further includes removing the dopant layer from the semiconductor wafer. No chemical etching... Agent: Schmeiser, Olsen & Watts

20080171441 - Polishing compound and method for producing semiconductor integrated circuit device: A polishing compound for chemical mechanical polishing to polish a surface to be polished for a semiconductor integrated circuit device, which comprises abrasive particles (A) having an average primary particle size in a range of from 5 to 300 nm and an association ratio in the polishing compound in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080171442 - Metal interconnect structure and process for forming same: A process for forming an interconnect structure in a low-k dielectric layer includes etching to form trenches in the dielectric layer, removal of photoresist, and further etching to remove damaged portions of the dielectric layer in sidewalls of the trenches. An interconnect structure includes a low-k dielectric layer formed on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080171443 - Fabrication of hybrid substrate with defect trapping zone: A process for fabricating a hybrid substrate that has a defect trapping zone. The process includes the steps of forming or depositing a first insulator layer on a first substrate of semiconductor material; increasing roughness of the first insulator layer surface; depositing a second insulator layer on the roughened surface... Agent: Winston & Strawn LLP Patent Department

20080171444 - Apparatuses for adjusting electrode gap in capacitively-coupled rf plasma reactor: A plasma processing chamber includes a cantilever assembly configured to neutralize atmospheric load. The chamber includes a wall surrounding an interior region and having an opening formed therein. A cantilever assembly includes a substrate support for supporting a substrate within the chamber. The cantilever assembly extends through the opening such... Agent: Buchanan, Ingersoll & Rooney PC

20080171445 - Novel chemical vapor deposition process: A chemical vapor deposition (CVD) method includes placing a semiconductor wafer into a reaction chamber; introducing a precursor into the reaction chamber; activating the precursor to a high-energy state using a non-direct plasma energy source; and reacting the precursor to form a film on the semiconductor wafer.... Agent: Slater & Matsil, L.L.P.

20080171446 - Method of forming semiconductor device: A method for forming a semiconductor device is provided including processing a wafer having a target material; forming a first pattern over the target material; forming a protection layer over the first pattern; and forming a second pattern, over the target material and not over the protection layer, without an... Agent: Farjami & Farjami LLP

20080171447 - Method of forming semiconductor device with multiple level patterning: A method for forming a semiconductor device is provided including processing a wafer having a target material, forming a multilevel photoresist structure having a protection layer over the target material, and forming a multilevel recess in the target material with the multilevel photoresist structure.... Agent: Farjami & Farjami LLP

20080171448 - System and method for selectively etching an integrated circuit: A method is provided for selectively marking a region of integrated circuit (IC). The method provides an IC die with a first region located on a backside surface of a bulk silicon (Si) layer. A semi-transparent film is formed overlying the bulk Si layer, semi-transparent to light having a first... Agent: Gerald W. Maliszewski

20080171449 - Method for cleaning salicide: A method for cleaning suicide includes providing a substrate having at least an intergraded silicide and residues, sequentially performing an ammonia hydrogen peroxide (APM) mixture cleaning process and a vaporized hydrochloric acid-hydrogen peroxide mixture (HPM) cleaning process to remove the residues, and performing a sulfuric acid-hydrogen peroxide mixture (SPM) cleaning... Agent: North America Intellectual Property Corporation

20080166822 - Semiconductor manufacturing apparatus: A semiconductor manufacturing apparatus includes: an ion source and a beam line for introducing an ion beam into a target film which is formed over a wafer with an insulating film interposed therebetween; a flood gun for supplying the target film with electrons for neutralizing charges contained in the ion... Agent: Mcdermott Will & Emery LLP

20080166823 - Method for evaluating semiconductor wafer, apparatus for evaluating semiconductor wafer, and method for manufacturing semiconductor wafer: The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is... Agent: Oliff & Berridge, PLC

20080166824 - Simulating method of ion implantaion and method for manufacturing semiconductor device: There is provided a method for simulating ion implantation which includes the steps of calculating an integral value Φa/c by integrating concentration distribution of Ge in a test silicon substrate from the thickness of an amorphous layer to infinite, acquiring a form parameter of the Ge concentration distribution in a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080166825 - Image sensor and manufacturing method thereof: An image sensor includes: a light source that irradiates a light on an object; a lens body that converges a reflection of the light from the object; a plurality of IC chips that receive the reflection passed through the lens body; and a transparent member provided between the IC chips... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080166828 - Gallium-containing light-emitting semiconductor device and method of fabrication: An LED comprising a light-generating semiconductor region having an active layer sandwiched between two confining layers of opposite conductivity types. A cathode is arranged centrally on one of the opposite major surfaces of the semiconductor region from which is emitted the light. An array of discrete gold regions are formed... Agent: Woodcock Washburn LLP

20080166826 - Systems and methods for on-die light sensing with low leakage: Systems and methods are disclosed for fabricating a device by forming a photosensitive area on a wafer; forming a control circuit adjacent the photosensitive area; and coating the photosensitive area with one or more film layers to form an optical filter. The filter provides a reduced leakage of an undesired... Agent: Tran & Associates

20080166827 - Thin film transistor array panel and method for manufacturing the same: The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and... Agent: Macpherson Kwok Chen & Heid LLP

20080166829 - Forming method of liquid crystal layer using ink jet system: According to an embodiment, a fabrication method includes forming a gate line disposed along a first direction and a common line parallel to the gate line on a substrate, the gate and common lines spaced apart from each other, forming a gate insulating layer on the gate and common lines,... Agent: Birch Stewart Kolasch & Birch

20080166830 - Image sensor pixel having photodiode with multi-dopant implantation: An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N− region formed within a P-type region. The N− region is formed from an implant of arsenic and an implant of... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080166831 - Method for fabricating a sensor semiconductor device with sensor chip: A sensor semiconductor device and a method for fabricating the same are proposed. A sensor chip is mounted on a substrate, and a dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the substrate and the sensor chip. The dielectric... Agent: Law Offices Of Mikio Ishimaru

20080166832 - Adjustments of masks by re-flow: As a step in performing a process on a structure, a hole pattern is provided in a thin layer of organic resin masking material formed over the structure to provide a process mask. A processing step is then performed through the openings in the mask, and after a processing step... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20080166833 - Hybrid window layer for photovoltaic cells: A novel photovoltaic solar cell and method of making the same are disclosed. The solar cell includes: at least one absorber layer which could either be a lightly doped layer or an undoped layer, and at least a doped window-layers which comprise at least two sub-window-layers. The first sub-window-layer, which... Agent: Macmillan Sobanski & Todd, LLC

20080166834 - Thin film etching method: Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching... Agent: Harness, Dickey & Pierce, P.L.C

20080166835 - Method of bonding a solder ball and a base plate and method of manufacturing packaging structure of using the same: A method of bonding a solder ball and a base plate and a method of manufacturing a packaging structure using the same are provided. The method of bonding a solder ball and a base plate includes the following steps. First, a base plate including an electrode layer and a base... Agent: Bacon & Thomas, PLLC

20080166836 - Semiconductor package including connected upper and lower interconnections, and manufacturing method thereof: A semiconductor package includes a base plate, at least one semiconductor constructing body which is formed on one surface of the base plate and has a plurality of external connection electrodes formed on a semiconductor substrate, an insulating layer which is formed on one surface of the base plate around... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080166837 - Power mosfet wafer level chip-scale package: A power MOSFET wafer level chip-scale packaging method is disclosed. The method includes the steps of electroless plating a wafer backside and a plurality of contact pads on a wafer front side and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality... Agent: Schein & Cai LLP

20080166838 - Manufacturing methods of metal wire, electrode and tft array substrate: A method of forming a gate line and gate electrode and a method of manufacturing a TFT array substrate. The metal gate line and gate electrode can be formed by: providing a substrate, forming a photoresist layer on the substrate, a photoresist pattern being formed complementary with that of the... Agent: Hasse & Nesbitt LLC

20080166839 - Sub-lithographics opening for back contact or back gate: A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the... Agent: Texas Instruments Incorporated

20080166840 - Method for manufacturing semiconductor device: The invention is directed to a method for manufacturing a semiconductor. The method comprises steps of providing a substrate having a gate structure formed thereon and forming a source/drain extension region in the substrate adjacent to the gate structure. A spacer is formed on the sidewall of the gate structure... Agent: J C Patents, Inc.

20080166841 - Method of fabricating a strained silicon channel metal oxide semiconductor transistor: The present invention provides a method of fabricating strained silicon channel MOS transistor, comprising providing a substrate, forming at least a gate structure on the substrate, forming a mask layer on the gate structure, performing an etching process to form two recesses corresponding to the gate structure within the substrate,... Agent: North America Intellectual Property Corporation

20080166842 - Etching composition and method for manufacturing a capacitor using the same: An etching composition for preventing from leaning a capacitor contains hydrofluoric acid (HF), ammonium fluoride (NH4F), an alkyl ammonium fluoride (ReNH3F; where Re is a C1-C10 linear or branched alkyl radical), a surfactant, an alcohol compound, and water. The composition can effectively suppress the leaning phenomenon of capacitors during the... Agent: Marshall, Gerstein & Borun LLP

20080166843 - Isolation regions for semiconductor devices and their formation: A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas of the substrate for future isolation regions of the semiconductor device. Portions of the substrate are removed in the areas for future isolation regions,... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20080166844 - Method of forming a non-volatile memory cell using off-set spacers: A stack of two polysilicon layers is formed over a semiconductor body region. A DDD implant is performed to form a DDD source region in the semiconductor body region along a source side of the polysilicon stack but not along a drain side of the polysilicon stack. Off-set spacers are... Agent: Townsend And Townsend And Crew, LLP

20080166846 - Method of forming trench gate fets with reduced gate to drain charge: A method for forming a FET includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A well region of a second conductivity type is formed in the semiconductor region. Source regions of the first conductivity type are formed in the well region such... Agent: Townsend And Townsend And Crew, LLP

20080166845 - Method of manufacture for a semiconductor device: A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at... Agent: Townsend And Townsend And Crew, LLP

20080166847 - Method of forming source and drain of field-effect-transistor and structure thereof: Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET;... Agent: International Business Machines Corporation Dept. 18g

20080166848 - Method for reducing overlap capacitance in field effect transistors: A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain region, the drain region having a drain extension... Agent: Cantor Colburn LLP - IBM Fishkill

20080166849 - Ldmos device and method: An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells.... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080166850 - Local collector implant structure for heterojunction bipolar transistors and methodof forming the same: A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant structure is formed within an upper portion of the... Agent: Cantor Colburn LLP - IBM Fishkill

20080166851 - Metal-insulator-metal (mim) capacitor and method for fabricating the same: The present invention discloses a metal-insulator-metal (MIM) capacitor and a method for fabricating the MIM capacitor, comprising forming a bottom insulation layer, a capacitor electrode material layer, and a hard mask material layer on a semiconductor substrate having a metal wire thereon; forming a hard mask by etching the hard... Agent: Frank Chau, Esq. F. Chau & Associates, LLP

20080166852 - Semiconductor element, semiconductor device, and method for fabrication thereof: A nitride semiconductor growth layer is laid on a substrate having an engraved region provided with a depressed portion.... Agent: Morrison & Foerster LLP

20080166853 - Method for manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so... Agent: Ingrassia Fisher & Lorenz, P.C.

20080166855 - Process for high voltage superjunction termination: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is... Agent: Panitch Schwarze Belisario & Nadel LLP

20080166854 - Semiconductor devices including trench isolation structures and methods of forming the same: Trench isolation methods include forming a first trench and a second trench in a semiconductor substrate. The second trench has a larger width than the first trench. A tower isolation layer is formed on the semiconductor substrate using a first high density plasma deposition process. The lower isolation layer has... Agent: Myers Bigel Sibley & Sajovec

20080166856 - Methods of forming recessed access devices associated with semiconductor constructions: The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the... Agent: Wells St. John P.s.

20080166857 - Electrically conductive path forming below barrier oxide layer and integrated circuit: Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising:... Agent: Hoffman Warnick LLC

20080166859 - Integrated assist features for epitaxial growth: A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device,... Agent: Fortkort & Houston P.C.

20080166858 - Self-constrained anisotropic germanium nanostructure from electroplating: A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20080166860 - Semiconductor device and manufacturing method thereof, liquid crystal television system, and el television system: The present invention provides a method for a semiconductor device, which comprises the steps of forming a first conductive layer in contact with a semiconductor region, forming an insulating layer on the first conductive layer by one of droplet discharge and application, irradiating a portion of the insulating layer with... Agent: Nixon Peabody, LLP

20080166861 - Impurity introducing apparatus and impurity introducing method: It is an object to prevent functions expected originally from being unexhibited when impurities to be introduced into a solid sample are mixed with each other, and to implement plasma doping with high precision. In order to distinguish impurities which may be mixed from impurities which should not be mixed,... Agent: Mcdermott Will & Emery LLP

20080166862 - Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The... Agent: Schwegman, Lundberg & Woessner / Atmel

20080166863 - Semiconductor transistors with contact holes close to gates: A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric... Agent: Schmeiser, Olsen & Watts

20080166864 - Method for forming trench gate and method for manufacturing semiconductor device: A method for forming trench gates is provided with a step of forming gate trenches on a semiconductor substrate, and a step of forming an element isolation region on the semiconductor substrate on which the gate trenches are formed. A step of channel doping within the gate trenches is performed... Agent: Sughrue Mion, PLLC

20080166865 - Method of fabricating flash memory: A method of fabricating a flash memory is provided. The method includes forming a tunneling insulating film, a charge storage film, and a blocking insulating film on a semiconductor substrate; performing High Temperature (HT) anneal for the resultant semiconductor substrate; and performing Low Temperature (LT) wet vapor anneal for the... Agent: Hyun Jong Park Tuchman & Park LLC

20080166866 - Method for forming gate structure with local pulled-back conductive layer and its use: A method for forming a gate structure with a pulled-back conductive layer and the use of the method are provided. The method conducts a local, not global, pull-back process on the conductive layer of the gate structure at the position intended for contact window formation, wherein the pull-back process is... Agent: Holland & Knight LLP

20080166868 - Semiconductor device and method for fabricating the same: A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to... Agent: Mcdermott Will & Emery LLP

20080166867 - Semiconductor device, method of manufacturing the same, and method of manufacturing metal compound thin film: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first... Agent: Cantor Colburn, LLP

20080166869 - Method of depositing a sculptured copper seed layer: A method of applying a sculptured copper seed layer on a semiconductor feature surface using ion deposition sputtering. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the... Agent: Shirley L. Church, Esq.

20080166870 - Fabrication of interconnect structures: Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20080166871 - Polyhedral oligomeric silsesquioxane based imprint materials and imprint process using polyhedral oligomeric silsesquioxane based imprint materials: A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, wherein each of the one or more polymerizable group is bound to a different silicon atom of the... Agent: Schmeiser, Olsen & Watts

20080166872 - Method of producing semiconductor device: A method produces a semiconductor device having an interconnection structure disposed above a substrate, wherein the interconnection structure has an interconnection and an insulator layer including a low-permittivity layer. The method includes an etching step forming openings in the insulator layer to expose a surface of the interconnection by dry... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080166873 - Method of manufacturing semiconductor device: In a dual damascene process to form a fine interconnection structure, a semiconductor manufacturing method includes: forming a first film to be etched on an insulating layer on a semiconductor substrate; forming a first mask film with an opening on the first film; forming a second film to be etched... Agent: Young & Thompson

20080166874 - Formation of vertical devices by electroplating: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080166875 - Thermally contained/insulated phase change memory device and method (combined): A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the dielectric material layer, including a phase-change layer positioned between and in electrical contact... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080166876 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second... Agent: Blakely Sokoloff Taylor & Zafman

20080166877 - Method for manufacturing semiconductor device and polisher used in the method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, including depositing an interconnect material including Cu or Cu alloy over an insulating film, and polishing the interconnect material by CMP with a polishing liquid, wherein the oxidation-reduction potential (ORP) of the polishing liquid is controlled so as to be in the range... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080166878 - Silicon nanostructures and fabrication thereof: A method of fabricating silicon nanostructures includes preparing a silicon wafer as a substrate; forming an oxide layer hardmask directly on the silicon substrate; patterning and etching the oxide hardmask; wet etching the silicon wafer to remove oxide to reduce the size of the oxide hardmask and to form nanostructure... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080166879 - Methods of manufacturing semiconductor structures using rie process: A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic... Agent: Greenblum & Bernstein, P.L.C

20080166880 - Delivery device for deposition: A delivery device for thin-film material deposition has at least first, second, and third inlet ports for receiving a common supply for a first, a second and a third gaseous material, respectively. Each of the first, second, and third elongated emissive channels allow gaseous fluid communication with one of corresponding... Agent: Andrew J. Anderson Patent Legal Staff

20080166881 - Semiconductor device manufacturing apparatus and manufacturing method of semiconductor device: Stagnation of gas used for substrate processing in an exhaust trap is prevented, and localized precipitation of components in the gas used for substrate processing is reduced. The proposed apparatus includes a substrate processing chamber (cylindrical space 250), a gas supply tube 232 for supplying substrate processing gas to the... Agent: Oliff & Berridge, PLC

20080166883 - Hemi-spherical structure and method for fabricating the same: Hemi-spherical structure and method for fabricating the same. A device includes discrete pillar regions on a substrate, and a pattern layer on the discrete support structures and the substrate. The pattern layer has hemi-spherical film regions on the discrete support structures respectively, and planarized portions on the substrate between the... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080166882 - Substrate processing apparatus and producing method of semiconductor device: A substrate treating apparatus is provided with a treatment chamber, a holding member, a heating member, and supplying members for alternately supplying the treatment chamber with first and second reacting substances. The apparatus is provided for forming a thin film on a substrate by supplying the first reacting substance to... Agent: Birch Stewart Kolasch & Birch

20080166884 - Delivery device comprising gas diffuser for thin film deposition: A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at... Agent: Patent Legal Staff Eastman Kodak Company

20080166885 - Method and apparatus for semiconductor wafer planarization: Broadly speaking, the present invention provides a method and an apparatus for planarizing a semiconductor wafer (“wafer”). More specifically, the present invention provides for depositing a planarizing layer over the wafer, wherein the planarizing layer serves to fill recessed areas present on a surface of the wafer. A planar member... Agent: Martine Penilla & Gencarella, LLP

20080166886 - Substrate processing apparatus: There is provided a substrate processing apparatus, comprising: a processing chamber that houses a plurality of substrates in a state of being stacked; a heating member that heats the substrate and an atmosphere in the processing chamber; a first gas supply member that supplies a source gas that thermally-decomposes; a... Agent: Oliff & Berridge, PLC

20080166887 - Method of depositing thin film and method of manufacturing semiconductor using the same: Disclosed herein are a method of depositing a thin film and a method of manufacturing a semiconductor using the same, having high selectivity by increasing etching resistance while an extinction coefficient associated with anti-reflectivity is maintained low. The method of depositing a thin film according to the invention includes (a)... Agent: Cantor Colburn, LLP

20080166888 - Sti of a semiconductor device and fabrication method thereof: A method for filling silicon nitride materials into a trench includes providing a substrate having a plurality of trenches, performing a first deposition process to form a first silicon nitride layer in the trenches, and performing a second deposition process to form a second silicon nitride layer in the trenches.... Agent: North America Intellectual Property Corporation

20080166889 - Eda methodology for extending ghost feature beyond notched active to improve adjacent gate cd control using a two-print-two-etch approach: In accordance with various embodiments, semiconductor devices and methods of forming semiconductor devices having non-rectangular active regions are provided. An exemplary method includes using a first mask to form a plurality of first features over a non-rectangular shaped active region and at least one ghost feature, wherein the plurality of... Agent: Texas Instruments Incorporated

20080166891 - Heat treatment method for silicon wafer: The present invention provides a heat treatment method for a silicon wafer in which, with respect to a surface of the silicon wafer made flat at an atomic level by a high-temperature heat-treatment at 1,100° C. or more, a surface roughness of the wafer can be reduced compared with the... Agent: Foley And Lardner LLP Suite 500

20080166890 - High pressure hydrogen annealing for mosfet: The present invention relates to a high pressure hydrogen annealing method for MOSFET semiconductor device, and more particularly, to effectively remove a supersaturated hydrogen on a high-k insulating layer treated by a high pressure hydrogen annealing so that the reliability of a device is improved. In other words, in order... Agent: Nath & Associates

20080166892 - Mask for forming polysilicon and a method for fabricating thin film transistor using the same: A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction... Agent: F. Chau & Associates, LLC

20080166894 - method for improving heat transfer of a focus ring to a target substrate mounting device: A focus ring heat transfer method improves heat transfer of a focus ring arranged in an outer peripheral portion of a mounting surface of a mounting table adapted to mount a target substrate in a chamber. The method includes steps of: disposing a heat transfer sheet between the focus ring... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080166893 - Low temperature oxide formation: A method of forming a semiconductor structure includes oxidizing a gate stack at a temperature of at most 600° C. with a plasma prepared from a gas mixture. The gas mixture includes an oxygen-containing gas and ammonia, and the gate stack is on a semiconductor substrate. The gate stack contains... Agent: Evan Law Group, LLC

20080160643 - Magnetic random access memory cells having split subdigit lines having cladding layers thereon and methods of fabricating the same: Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with... Agent: Myers Bigel Sibley & Sajovec

20080160644 - Method and structure for improved alignment in mram integration: A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the... Agent: Cantor Colburn LLP-ibm Yorktown

20080160641 - Multi-state thermally assisted storage: A process for manufacturing a random access memory cell, that is capable of storing multiple information states in a single physical bit, is described. The basic structure combines a conventional MTJ with a reference stack that is magnetostatically coupled to the MTJ. The MTJ is read in the usual way... Agent: Saile Ackerman Llc

20080160642 - Semiconductor device: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, a conductive plug which is connected to an active region of a transistor formed on the semiconductor substrate, a metal silicide film which covers a bottom surface portion and side surface portion of the conductive plug,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080160645 - Semiconductor device and method of fabricating the same: After bottom electrode film is formed, a first ferroelectric film is formed thereon. Then, the first ferroelectric film is allowed to crystallize. Thereafter, a second ferroelectric film is formed on the first ferroelectric film. Next, a top electrode film is formed on the second ferroelectric film, and the second ferroelectric... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080160640 - Top contact alignment in semiconductor devices: According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20080160646 - Method, system, and computer program product for predicting thin film integrity, manufacturability, reliability, and performance in electronic designs: Disclosed is an improved method, system, and computer program product for predicting and improving the integrity, manufacturability, reliability, and performance of an electronic circuit feature based on the stresses or strains of design features of electronic designs. Some embodiments identify the design, the concurrent model(s), design feature physical or electrical... Agent: Bingham Mccutchen LLP

20080160647 - Thick oxide film for wafer backside prior to metalization loop: A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick oxide on the wafer backside so that at least pre-selected oxide thickness remains after back end of line processing is complete and performing the back end of... Agent: Texas Instruments Incorporated

20080160648 - Establishing correspondence and traceability between wafers and solar cells: The invention regards a method and a system for establishing correspondence between wafers and solar cells produced from said wafers. The method comprises for each wafer and each solar cell, providing an image of the wafer, providing an image of the cell, comparing the wafer image to the cell image,... Agent: Christian D. Abel

20080160649 - Method for manufacturing semiconductor device: When a design diagram of the semiconductor device by a conventional CAD tool is used, a pattern which can be formed with the ink-jet apparatus is limited; therefore, there is a possibility that some circuits of the desired semiconductor device cannot be formed as they are designed. A plurality of... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080160651 - Recessing trench to target depth using feed forward data: Recessing a trench using feed forward data is disclosed. In one embodiment, a method includes providing a region on a wafer including a trench area that includes a trench and a field area that is free of any trench, and a material applied over the region so as to fill... Agent: Hoffman Warnick Llc

20080160650 - System and method for controlling an electrochemical etch process: By evaluating a status signal on the basis of a fault detection classification mechanism in an electrochemical etch tool, a corresponding failure status of the tool may be obtained for each single substrate, thereby significantly reducing the risk of significant yield loss compared to conventional strategies. The fault detection and... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.c.

20080160652 - Two-step method for etching a fuse window on a semiconductor substrate: A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said fuse interconnect-wire, an intermediate dielectric layer and a passivation layer.... Agent: North America Intellectual Property Corporation

20080160653 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate that includes a cell region and a peripheral region. A first hard mask layer, a second hard mask layer, and an anti-reflective coating layer are formed over the etch target layer. A photosensitive pattern... Agent: Townsend And Townsend And Crew, LLP

20080160654 - Method of testing an integrity of a material layer in a semiconductor structure: A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.c.

20080160655 - Method of verifying line reliability and method of manufacturing semiconductor device: Provided are a method of verifying line reliability and a method of fabricating a semiconductor substrate to improve the line reliability. The semiconductor device fabricating method includes: forming an interlayer insulating layer having a via hole on a semiconductor substrate; forming a seed layer on the interlayer insulating layer; performing... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080160657 - method of manufacturing a semiconductor integrated circuit device and a method of manufacturing a thin film probe sheet for using the same: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming... Agent: Miles & Stockbridge Pc

20080160656 - Addressable hierarchical metal wire test methodology: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal... Agent: Mcginn Intellectual Property Law Group, Pllc

20080160658 - Mold structure for packaging led chips and method thereof: A mold structure for packaging LED chips includes a top mold and a bottom mold. The bottom mold is mated with the top mold. The bottom mold has a main flow channel, a plurality of receiving spaces formed beside the main flow channel, a plurality of secondary flow channels for... Agent: Rosenberg, Klein & Lee

20080160659 - Pressure transducer diaphragm and method of making same: A method of making a pressure transducer diaphragm. One or more trenches are etched in a first surface of a first substrate. The trench is rendered etch resistant. A cavity is then formed in a second opposite surface of the first substrate defining a diaphragm supported by a frame with... Agent: General Electric Co. Global Patent Operation

20080160660 - Method for fabricating a cmos image sensor: A method for fabricating a CMOS image sensor may include forming an isolation layer defining an active area on a semiconductor substrate, forming first and second gate electrodes in the transistor area of the semiconductor substrate, forming a photodiode area in the semiconductor substrate at a first side of the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080160661 - Method and structure for fabricating solar cells using a layer transfer process: A reusable silicon substrate device for use with layer transfer process. The device has a reusable substrate having a surface region, a cleave region, and a total thickness of material. The total thickness of material is at least N times greater than a first thickness of material to be removed.... Agent: Townsend And Townsend And Crew, LLP

20080160665 - Image sensor fabricating method: A method of fabricating an image sensor includes forming a first SiO2 layer on a color filter layer, patterning a photosensitive layer on first SiO2 layer, patterning the first SiO2 layer through a first etching process, forming a second SiO2 layer on the first SiO2 layer, and forming a micro-lens... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080160664 - Method for manufacturing image sensor: Provided is a method for manufacturing an image sensor. The method includes the following. A color filter layer is formed on a semiconductor substrate having a photodiode and a transistor formed thereon. A planarization layer is formed on the color filter layer. An LTO (Low Temperature Oxide) layer is formed... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080160663 - Method for manufacturing of cmos image sensor: The present invention relates to a method for manufacturing a CMOS image sensor. The method comprises stacking an interlayer dielectric layer including a plurality of photodiodes on a semiconductor substrate, forming a metal pad on the interlayer dielectric layer, depositing an anti-reflective coating film on the metal pad, depositing a... Agent: Workman Nydegger

20080160662 - Method of manufacturing cmos image sensor: A method of manufacturing a CMOS image sensor comprising forming a first insulating film on a silicon semiconductor substrate which includes a metal pad; selectively etching the first insulating film, so as to form a first insulating film pattern with a first opening which exposes the metal pad; forming a... Agent: Workman Nydegger

20080160667 - Fabricating method of image sensor: A fabricating method of an image sensor that can include steps of forming a first isolation area and a first alignment key in a semiconductor substrate using a first mask pattern as a mask; and then forming a first photodiode in the semiconductor substrate using a second mask pattern as... Agent: Sherr & Nourse, Pllc

20080160666 - Method of manufacturing cmos image sensor: A method for manufacturing the CMOS image sensor comprising forming an epitaxial layer provided with a plurality of photo diodes on a semiconductor substrate, coating a first photo resist on the epitaxial layer and performing a patterning process on the first photo resist using a predetermined reference value in order... Agent: Workman Nydegger

20080160668 - Photo-detector and related methods: An apparatus comprising at least one multilayer wafer which includes a device layer adjacent to a barrier layer, and the device layer includes at least two photoconductive regions separated by an etched channel extending through the device layer. In some instances the apparatus may be an accelerometer having two photodiodes... Agent: Snell & Wilmer L.l.p. (grumman)

20080160669 - Light-emitting component and process for its preparation: A light-emitting component comprising organic layers and having several layers between a base contact and a cover contact, the corresponding process for its preparation. At least one polymer layer and two molecular layers are arranged, so that when the cover contact is a cathode, the layer adjacent to the cover... Agent: Baker Botts L.l.p.

20080160670 - Physical alignment features on integrated circuit devices for accurate die-in-substrate embedding: A method of packaging an integrated circuit die including forming a mask window having a first aperture with a first set of alignment edges and forming an alignment feature on an uppermost surface of the integrated circuit die where the alignment feature has a second set of alignment edges. The... Agent: Schneck & Schneck

20080160671 - Ball-mounting method for coplanarity improvement in large package: A method of forming a packaging structure and the packages formed thereof are provided. The method includes providing a package having a top surface and placing solder balls on the top surface of the package. A coplanar surface is then placed against the solder balls, wherein the surface is non-adhesive.... Agent: Slater & Matsil, L.l.p.

20080160672 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device including a cell area and a peripheral area. The peripheral area includes a low voltage area and a high voltage area. The cell area can be manufactured as a chip in a first wafer, the low voltage area can be manufactured as a... Agent: Sherr & Nourse, Pllc

20080160673 - Assembly of thin die coreless package: In one embodiment, a method comprises coupling a coreless substrate panel to a pressure cover plate of a carrier, applying flux to the coreless substrate panel, placing at least one die on the coreless substrate panel, reflowing solder onto the coreless substrate panel, defluxing the coreless substrate panel, underfilling the... Agent: Caven & Aghevli C/o Intellevate, Llc

20080160674 - Method of making a semiconductor device having multiple die redistribution layer: A semiconductor device and methods of forming same are disclosed having multiple die redistribution layer. After fabrication of semiconductor die on a wafer and prior to singulation from the wafer, adjacent semiconductor die are paired together and a redistribution layer may be formed across the die pair. The redistribution layer... Agent: Vierra Magen/sandisk Corporation

20080160676 - Heat transfer structures: A switching element includes a bubble chamber, a heater and a heat conductor. The bubble chamber holds fluid. The bubble chamber includes a trench within a planar light circuit and includes a trench within an integrated circuit attached to the planar light circuit. The heater is located under the trench... Agent: Kathy Manke Avago Technologies Limited

20080160677 - Method of forming component package: There is provided a method of forming a component package. The method includes the steps of providing the die pad or heat sink, forming an isolation layer on the rear surface of the die pad or heat sink and encapsulating the die pad with encapsulating material in a mold cavity... Agent: Slater & Matsil LLP

20080160675 - Microelectronic package with thermal access: A method of forming a microelectronic package including the steps of providing a three-layer metal plate, having a first layer, a second layer and a third layer. A plurality of conductive elements is formed from the first layer of the metal plate. A dielectric sheet is attached to the first... Agent: Tessera Lerner David Et Al.

20080160678 - Method for fabricating semiconductor package: A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on the second circuit layer. At... Agent: Edwards Angell Palmer & Dodge LLP

20080160679 - Apparatus and methods for encapsulating microelectromechanical (mem) devices on a wafer scale: Apparatus and methods are provided for enabling wafer-scale encapsulation of microelectromechanical (MEM) devices (e.g., resonators, filters) to protect the MEMs from the ambient and to provide either a controlled ambient or a reduced pressure. In particular, methods for wafer-scale encapsulation of MEM devices are provided, which enable encapsulation of MEM... Agent: F. Chau & Associates, Llc

20080160681 - Manufacture including shield structure: The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated... Agent: Neifeld Ip Law, P.c.,

20080160680 - Methods of fabricating shield plates for reduced field coupling in nonvolatile memory: Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because... Agent: Vierra Magen/sandisk Corporation

20080160682 - Semiconductor device having fuse circuit on cell region and method of fabricating the same: A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is possible to reduce the... Agent: Marger Johnson & Mccollom, P.c.

20080160683 - Source/drain extensions in nmos devices: A method including implanting carbon and fluorine into a substrate in an area of the substrate between a source/drain region and a channel, the area designated for a source/drain extension; and a source/drain extension dopant following implanting carbon and fluorine, implanting phosphorous in the area. A method including disrupting a... Agent: Intel/blakely

20080160684 - Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby: Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, in which an active pattern is formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, a gate insulating layer is formed... Agent: Mills & Onello LLP

20080160685 - Semiconductor device with surge current protection and method of making the same: A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions... Agent: Morris Manning Martin LLP

20080160686 - Semiconductor device and method of manufacturing same: A semiconductor device includes a semiconductor substrate, a field effect transistor (FET), contact plugs, a resistive element (specific member) and interconnects. Contact plugs are connected to the FET. A resistive element is provided in the layer (lowermost layer of interconnect layer) that also includes the contact plug. The contact plug... Agent: Young & Thompson

20080160687 - Method and resulting structure for fabricating dram capacitor structure: A method for forming a capacitor structure for a dynamic random access memory device. The method includes forming a device layer overlying a semiconductor substrate, e.g., silicon wafer. The method includes forming a first interlayer dielectric overlying the device layer and forming a via structure within the first interlayer dielectric... Agent: Townsend And Townsend And Crew, LLP

20080160688 - Methods for fabricating an integrated circuit: Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit... Agent: Ingrassia Fisher & Lorenz, P.c. (amd)

20080160690 - Flash memory device and method for fabricating the same: A flash memory device including an isolation layer for defining active regions in a semiconductor substrate. The active region is a region in which flash memory cells are to be formed. The device also includes a gate stack is formed to come across the active region and the isolation layer,... Agent: Lowe Hauptman Ham & Berner, LLP

20080160689 - Three-dimensional control-gate architecture for single poly eprom memory devices fabricated in planar cmos technology: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080160691 - Fabricating method of semiconductor device: A method of fabricating a semiconductor device is provided. Spacers can be formed on adjacent gate structures and used as an ion implantation mask for forming source/drain regions. The spacers can include a nitride layer and an oxide layer. An etch stop layer can be provided between the gate structures,... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080160692 - Method for manufacturing flash memory device: Provided is a method for manufacturing a flash memory device that can improve uniformity. In one method, an oxide chemical mechanical polishing process is performed to remove a height difference of the interlayer insulating layer that is generated between the cell area and the peripheral area due to the gate... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080160693 - Methods of forming non-volatile memory device: A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.... Agent: Myers Bigel Sibley & Sajovec

20080160694 - Method for forming flash memory device: A method for forming a flash memory device comprising forming a plurality of cell gate patterns in a cell area of a semiconductor substrate, forming a peripheral gate pattern, which includes a peripheral gate insulating layer and a peripheral gate electrode that are sequentially stacked, in a peripheral area of... Agent: Workman Nydegger

20080160695 - Method of fabricating semiconductor device: A method of forming a floating gate of a flash memory device that can include steps of forming isolation layers in a semiconductor substrate to define active regions, forming a tunnel oxide layer over the active regions of the semiconductor substrate and forming a gate layer by depositing doped polysilicon... Agent: Sherr & Nourse, Pllc

20080160696 - Method for fabricating flash memory device: A method for fabricating a flash memory device, includes: preparing a substrate having an active region and an inactive region; forming a trench in the inactive region; forming a device isolation film in the trench; forming a well in the active region; forming a tunnel oxide film, a first polysilicon... Agent: Sherr & Nourse, Pllc

20080160697 - Metal-oxide-semiconductor transistor and method of manufacturing the same: The trench MOS transistor according to the present invention includes a drain region in a form of a trench filled with a semiconductor material. The trench has a bottom surface and side surfaces and extends vertically downward from the top surface of the covering layer into the buried layer, the... Agent: North America Intellectual Property Corporation

20080160698 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device includes forming an isolation structure using a pad insulation layer for device isolation. A hard mask pattern forming a plurality of recesses is formed over an upper portion of a substrate including the pad insulation layer. The pad insulation layer and the substrate... Agent: Townsend And Townsend And Crew, LLP

20080160699 - Method for fabricating semiconductor device having bulb-type recessed channel: A method for fabricating a semiconductor device having a bulb-type recessed channel including forming a mask layer on the semiconductor substrate to expose a region where a trench for a bulb-type recessed channel can be formed, forming the trench in the semiconductor substrate, implanting dopant ions in three-dimensional radial directions... Agent: Marshall, Gerstein & Borun LLP

20080160700 - Method for manufacturing semiconductor device having bulb-type recessed channel: A method for manufacturing a semiconductor device having a bulb-type recessed channel including: forming a trench that defines an active region including a channel region having a sidewall and a junction region in a semiconductor substrate; forming a device isolation layer that buries the trench, and forming a sidewall pattern... Agent: Marshall, Gerstein & Borun LLP

20080160701 - Method of fabricating trench gate type mosfet device: Disclosed is a method of fabricating a trench gate type metal oxide semiconductor field-effect transistor (MOSFET) device. According to an embodiment, a trench can be formed in a semiconductor substrate. A gate oxide layer can be formed on an inner wall of the trench. A first insulating layer can be... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080160702 - Method of manufacturing semiconductor device: A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of... Agent: Miles & Stockbridge Pc

20080160703 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. A first gate can be formed in a salicide region of a semiconductor substrate, and a second gate can be formed in a non-salicide region of the semiconductor substrate. A source and a drain can be formed at both sides of... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080160704 - Ion implantation method for high voltage device: A method of performing ion implantation method for a high-voltage device. The method includes defining a logic region and a high-voltage region in a semiconductor substrate, forming a first gate insulation layer on the semiconductor substrate in the logic region and a second gate insulation layer on the semiconductor substrate... Agent: Workman Nydegger

20080160705 - Gate etch process for a high-voltage fet: A method, in one embodiment, includes etching first and second dielectric regions in a substantially isotropic manner through first and second openings of a mask layer to create first and second trenches. The first and second dielectric regions are disposed on opposite sides of a mesa of semiconductor material, the... Agent: The Law Offices Of Bradley J. Bereznak

20080160706 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided, in which drift areas are deeply formed in a silicon substrate even when a drive-in process is performed at a relatively lower temperature for a relatively shorter processing time. Therefore, the defects caused by thermal bird's beaks and the horizontal diffusion... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080160707 - Method for fabricating sesmiconductor device: A method for fabricating a semiconductor device is provided. The method includes forming a trench having a predetermined depth in a substrate having an active area and an isolation area by selectively removing the isolation area, forming a well region in the active area of the substrate using the trench... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080160708 - Sidewall spacer pullback scheme: A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the... Agent: Texas Instruments Incorporated

20080160709 - Advanced activation approach for mos devices: A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the... Agent: Slater & Matsil, L.l.p.

20080160710 - Method of fabricating mosfet device: A method of fabricating a MOSFET device comprising forming a gate electrode pattern on a gate insulating layer on a semiconductor substrate, forming pre-source and pre-drain junction layers using a first ion implantation process on the substrate on each side of the gate electrode pattern, respectively, forming lightly doped drain... Agent: Workman Nydegger

20080160711 - Contactless flash memory array: A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on a substrate. An insulating layer is then deposited over the active regions, and a portion of the insulating layer is removed to form... Agent: Intel/blakely

20080160712 - Multiple-layer dielectric layer and method for fabricating capacitor including the same: A dielectric layer of a capacitor includes a first dielectric layer, a second dielectric layer formed over the first dielectric layer, the second dielectric layer having a dielectric constant lower than that of the first dielectric layer, and a third dielectric layer formed over the second dielectric layer, the third... Agent: Townsend And Townsend And Crew, LLP

20080160713 - Simultaneously forming high-speed and low-power memory devices on a single substrate: A method patterns a trench mask over both SOI regions and bulk silicon regions of a single substrate. Next, the SOI regions and the bulk silicon regions are simultaneously etched through the trench mask to form trenches in the SOI regions and the bulk silicon regions. In such processing the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080160714 - Method of forming semiconductor device: A method for forming a semiconductor device comprising forming an inter-layer dielectric (ILD) layer on a semiconductor substrate; forming a first trench and second trench in a cell area on the ILD layer, wherein the second trench has a width which is wider than the first trench; forming a first... Agent: Workman Nydegger

20080160715 - Method of forming a device isolation film of a semiconductor device: A method of forming a device isolation film for a semiconductor device comprising forming a trench on a silicon semiconductor substrate, rounding an upper corner of the trench using an in-situ plasma method, filling the trench by forming an insulating layer over the silicon semiconductor substrate, and forming a shallow... Agent: Workman Nydegger

20080160716 - Method for fabricating an isolation layer in a semiconductor device: A method for forming an isolation layer in a semiconductor device includes forming a trench inside a semiconductor substrate, forming a fluid insulating layer over the semiconductor substrate, thereby filling the trench with the fluid insulating layer, curing the semiconductor substrate by plasma oxidation to densify the fluid insulating layer,... Agent: Marshall, Gerstein & Borun LLP

20080160718 - Method for fabricating isolation layer in semiconductor device: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of... Agent: Blakely Sokoloff Taylor & Zafman

20080160717 - Method of forming trench in semiconductor device: Provided is a method of forming a trench in a semiconductor device capable of improving gap-fill performance. In one method of forming a trench in a semiconductor device, an oxide layer and a mask layer are sequentially formed on a substrate. The mask layer is selectively patterned to form a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080160719 - Methods of forming shallow trench isolation structures in semiconductor devices: Methods of forming a shallow trench isolation structures in semiconductor devices are disclosed. A disclosed method comprises forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate; forming a trench defining first and second active areas by etching the second oxide layer, the nitride... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080160720 - Method for forming trench isolation: A method for forming a trench isolation in a semiconductor device is provided. This is a novel method for rounding the top corners of trench isolations. The method ensures that rounded corner portions with a uniform shape are consistently formed regardless of the pattern densities of active areas. The method... Agent: Workman Nydegger

20080160721 - Method for fabricating isolation film in semiconductor device: A method for forming an isolation layer in a semiconductor device comprises forming a trench inside a semiconductor substrate, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills the trench, etching overhangs on sides of the trench by first cleaning with... Agent: Marshall, Gerstein & Borun LLP

20080160722 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. The method includes the steps of forming an insulating layer on a substrate, partially exposing the substrate by selectively etching the insulating layer, implanting ions into the exposed substrate using the etched insulating layer as an ion implantation mask, and removing... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080160723 - Method of fabricating silicon/dielectric multi-layer semiconductor structures using layer transfer technology and also a three-dimensional multi-layer semiconductor device and stacked layer type image sensor using the same method, and a method of manufact: Fabrication of a three-dimensional semiconductor structure is provided by the present disclosure. A buffer oxide film, a nitride film, and an ONO dielectric layer are formed on a handle wafer. A semiconductor layer and an oxide film are formed on a donor wafer, which is turned over and is then... Agent: Brinks Hofer Gilson & Lione

20080160724 - Method of dicing: Provided is a method of dicing a wafer where a plurality of semiconductor device regions is formed on a front side of the wafer, the semiconductor device regions being separated by scribe lanes, the method comprising dicing the wafer by irradiating a laser beam on a backside of the wafer... Agent: Marger Johnson & Mccollom, P.c.

20080160725 - Semiconductor die pick up apparatus and method thereof: According to example embodiments, an apparatus for picking up a semiconductor die includes an electromagnetic collet unit configured to selectively generate an attractive force between the electromagnetic collet unit and a magnetic wafer adhesive tape disposed on a surface of the semiconductor die. The apparatus further includes a transfer head... Agent: Marger Johnson & Mccollom, P.c.

20080160726 - Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics: A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a... Agent: Myers Bigel Sibley & Sajovec

20080160727 - Silicon-on-insulator chip with multiple crystal orientations: A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the... Agent: Steven H. Slater Slater & Matsil, L.l.p.

20080160728 - Method for introducing impurities and apparatus for introducing impurities: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous... Agent: Michael E. Fogarty, Esq. Mcdermott Will & Emery LLP

20080160729 - Technique for removing resist material after high dose implantation in a semiconductor device: Resist masks exposed to high-dose implantation processes may be efficiently removed on the basis of a combination of a plasma-based etch process and a wet chemical etch recipe, wherein both etch steps may include a highly selective etch chemistry in order to minimize substrate material loss and thus dopant loss... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.c.

20080160730 - Method of ion implantation and method of fabricating a semiconductor device: A method of fabricating a semiconductor device includes forming a mask pattern for exposing a region of a semiconductor substrate. Dopant ions are implanted into the exposed region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.... Agent: Townsend And Townsend And Crew, LLP

20080160731 - Method for fabricating cmos image sensor: A method for fabricating a Complementary Metal Oxide Semiconductor (CMOS) image sensor includes implanting first conductive type dopants into a semiconductor substrate and forming a photodiode region in a surface of the semiconductor substrate, performing spike annealing to the semiconductor substrate having the photodiode region formed thereon, to thereby suppress... Agent: Lowe Hauptman Ham & Berner, LLP

20080160732 - Method for the production of a buried stop zone in a semiconductor component and semiconductor component comprising a buried stop zone: According to one embodiment, a method for the production of a stop zone in a doped zone of a semiconductor body comprises irradiating the semiconductor body with particle radiation in order to produce defects in a crystal lattice of the semiconductor body. The semiconductor body is exposed to an environment... Agent: Coats & Bennett/infineon Technologies

20080160733 - Silicon/germanium oxide particle inks, inkjet printing and processes for doping semiconductor substrates: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The... Agent: Dardi & Associates, Pllc

20080160734 - Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same: Under one aspect, a method of making a nanotube switch includes: providing a substrate having a first conductive terminal; depositing a multilayer nanotube fabric over the first conductive terminal; and depositing a second conductive terminal over the multilayer nanotube fabric, the nanotube fabric having a thickness, density, and composition selected... Agent: Wilmerhale/boston

20080160735 - Forming polysilicon regions: Polysilicon regions are formed by performing a thermal treatment in a hydrogen ambient environment after patterning a polysilicon structure.... Agent: Edell, Shapiro & Finnan, Llc

20080160736 - Lanthanide series metal implant to control work function of metal gate electrodes: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a gate dielectric. A lanthaide series metal is implanted into the metal screen layer above the gate dielectric. The lanthaide metal is contained in the screen layer or... Agent: Texas Instruments Incorporated

20080160738 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a conductive material layer for forming a gate over a substrate including a cell region and a peripheral region, forming hard mask patterns over the conductive material layer, forming a mask pattern over the resultant structure in the cell region, exposing... Agent: Blakely Sokoloff Taylor & Zafman

20080160739 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device including a first region and a second region, wherein pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region includes providing a substrate including the first region and the... Agent: Blakely Sokoloff Taylor & Zafman

20080160737 - Method for forming metal pattern and method for forming gate electrode in semiconductor device using the same: A method for forming a metal pattern in a semiconductor device includes forming an etch stop layer over a semi-finished substrate including a metal layer, forming a hard mask over the etch stop layer, etching the hard mask to form a hard mask pattern exposing the etch stop layer, and... Agent: Blakely Sokoloff Taylor & Zafman

20080160740 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device comprises forming a SEG layer in a bottom of a storage node contact hole, and forming a spacer at a sidewall of a storage node contact hole and a bit line contact hole, thereby preventing expansion of the bottom of the bit line... Agent: Marshall, Gerstein & Borun LLP

20080160742 - Method for fabricating semiconductor device with recess gate: A method for fabricating a semiconductor device having a recess gate includes forming a first recess pattern by etching the substrate and a sidewall protection layer on sidewalls of the first recess pattern, forming a second recess pattern having a greater width than the first recess pattern by etching a... Agent: Lowe Hauptman Ham & Berner, LLP

20080160741 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprising forming a plurality of trench gate electrodes in a semiconductor substrate which protrude from the semiconductor substrate by a predetermined height; forming a polycrystal silicon film on the surface of the substrate; performing an anisotropic etching process on the polycrystal silicon film... Agent: Workman Nydegger

20080160743 - Composition for cleaning substrates and method of forming gate using the composition: Provided are a substrate cleaning composition including a fluoride compound, an inorganic acid, and deionized water, and a method of forming a gate using the same. The fluoride compound is one of HF, NH4F, and a combination thereof, and the inorganic acid is one of HNO3, HCl, HCIO4, H2SO4, or... Agent: Volentine & Whitt Pllc

20080160744 - Method for fabricating semiconductor device and improving thin film uniformity: A substrate including a memory cell region and a peripheral circuit region is provided. A first dielectric layer, a first conductive layer and a mask layer are formed on the substrate. Isolation structures are formed, and the isolation structures in the memory cell region are denser than that in the... Agent: Jianq Chyun Intellectual Property Office

20080160745 - Method for fabricating a dual poly gate in semiconductor device: A method for fabricating a dual poly gate in a semiconductor device is disclosed. The method comprises forming a gate insulating layer over a semiconductor substrate including a first region and a second region, forming a first conductive type polysilicon layer and a second conductive type polysilicon layer in the... Agent: Marshall, Gerstein & Borun LLP

20080160746 - Method for fabricating semiconductor device with gate stack structure: A method for fabricating a semiconductor device includes forming a first conductive layer over a substrate, forming an intermediate structure over the first conductive layer, the intermediate structure formed in a stack structure comprising at least a first metal layer and a nitrogen containing metal silicide layer, and forming a... Agent: Townsend And Townsend And Crew, LLP

20080160747 - Method of forming a gate of a semiconductor device: A method of forming a gate of a semiconductor device includes providing a semiconductor substrate over which a first conductive layer, a dielectric layer and a second conductive layer are formed. The second conductive layer is patterned to expose a part of the dielectric layer. A first protection layer is... Agent: Townsend And Townsend And Crew, LLP

20080160748 - Method of forming dielectric layer of flash memory device: The present invention relates to a method of forming a dielectric layer of a flash memory device. In a process of forming a dielectric layer of a flash memory device, the dielectric layer may include a first oxide layer, a high dielectric layer, and a second oxide layer is formed.... Agent: Marshall, Gerstein & Borun LLP

20080160749 - Semiconductor device and method of forming thereof: A semiconductor device and method of forming thereof. An embodiment comprises forming a spacer layer on a substrate, forming a via having walls and a bottom in the spacer layer, depositing a conformal first conductive layer on the spacer layer and on the walls and the bottom of the via,... Agent: Texas Instruments Incorporated

20080160750 - Method of manfacturing semiconcudtor device: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.... Agent: Young & Thompson

20080160751 - Microelectronic die including solder caps on bumping sites thereof and method of making same: A method of forming a microelectronic package, and a package formed according to the method. The method includes: providing a microelectronic substrate including bonding pads and solder bumps on respective ones of the bonding pads; providing a microelectronic die including bumping sites thereon; providing solder caps on the bumping sites;... Agent: Intel/blakely

20080160752 - Method for chip to package interconnect: A damascene method of forming a C4 element includes forming a last level metal layer on a substrate, forming a TV ILD layer on the last level metal layer, forming a lithographically patterned UBM adhesion layer including one of Ti, TiW, Cr and Cu, forming a mandrel layer over the... Agent: Mcginn Intellectual Property Law Group, Pllc

20080160753 - Method of forming metal wire in semiconductor device: A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, forming a metal layer on the... Agent: Marshall, Gerstein & Borun LLP

20080160754 - Method for fabricating a microelectronic conductor structure: A method for fabricating a microelectronic structure includes forming a via aperture through a dielectric layer located over a substrate having a conductor layer therein, to expose the conductor layer. The conductor layer typically comprises a copper containing material. The method also includes etching the conductor layer to form a... Agent: Scully, Scott, Murphy & Presser, P.c.

20080160755 - Method of forming interconnection of semiconductor device: Disclosed is a method of forming an interconnection of a semiconductor device. The method includes forming a lower interlayer insulating layer including a lower metal interconnection on a semiconductor substrate, forming an insulating layer and an upper interlayer insulating layer on the lower interlayer insulating layer, forming a damascene pattern... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080160756 - Method of manufacturing opening and via opening: A method of manufacturing an opening is described. First, a substrate including a conductive portion and a dielectric layer both formed thereon is provided. The conductive portion at least includes a conductive layer and a passivation layer from bottom-up, and the dielectric layer covers the conductive portion. A first dry... Agent: J C Patents, Inc.

20080160757 - Semiconductor device fabricating method: A semiconductor device fabricating method may include forming an insulating layer on a semiconductor substrate; forming a through hole with a first depth in the insulating layer and the semiconductor substrate; forming a metal layer thereon, thereby forming a through electrode in the through hole; and exposing the through electrode... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.c.

20080160758 - Method of manufacturing semiconductor device: Etching is performed on an insulating layer 23 and a conductive layer 32 with a photoresist 41 as the mask, to form an opening 51 in the conductive layer 32. After removing the photoresist 41, another insulating layer 24 is formed all over, which is etched back so as to... Agent: Sughrue Mion, Pllc

20080160759 - Method for fabricating landing plug contact in semiconductor device: A method for fabricating a semiconductor device includes forming an etch barrier layer over a semi-finished substrate that includes a plurality of patterns, forming an insulation layer over the etch barrier layer, planarizing the insulation layer, recessing a portion of the planarized insulation layer, forming a hard mask pattern over... Agent: Blakely Sokoloff Taylor & Zafman

20080160760 - Method of forming contact plug in semiconductor: A method of forming a contact plug in a semiconductor device includes the steps of forming a plurality of select lines and a plurality of word lines on a semiconductor substrate; forming a first etching stop layer on the select lines and the word lines; forming a second etching stop... Agent: Marshall, Gerstein & Borun LLP

20080160761 - Method of modifying a surface and a method of forming an area of a functional liquid on the modified surface: A method of modulating a surface includes: (a) forming a BCB layer on a surface of a target object; and (b) conducting a CF4 plasma exposure against a top surface of the BCB layer.... Agent: Oliff & Berridge, Plc

20080160762 - Method for the protection of metal layers against external contamination: In order to avoid the contamination of a seed layer, which is typically highly reactive with the external atmosphere, during the formation of interconnect structures in a semiconductor device, a protective layer is formed. The protective layer may be comprised of oxide formed in an oxidizing ambient prior to transporting... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.c.

20080160763 - Semiconductor device and method for forming pattern in the same: A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate, forming a second hard mask layer pattern over the first hard mask layer, forming a spacer on a sidewall of the second hard mask layer pattern, selectively etching... Agent: Marshall, Gerstein & Borun LLP

20080160764 - Method for improved planarization in semiconductor devices: A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric... Agent: Harrity Snyder, L.l.p.

20080160765 - Method for forming pattern in semiconductor device: A method for forming a semiconductor device includes forming an etch target layer, forming a sacrificial hard mask layer having a metal layer and a carbon-based material layer on the etch target layer, forming a photoresist pattern on the carbon-based material layer, etching the carbon-based material layer by the photoresist... Agent: Blakely Sokoloff Taylor & Zafman

20080160766 - Method for fabricating bulb-shaped recess pattern: A method for fabricating a bulb-shaped recess pattern includes: forming an etch barrier layer over a substrate; forming a hard mask pattern in which a first polymer is attached to sidewalls of the hard mask pattern over the etch barrier layer; sequentially etching the etch barrier layer and the substrate... Agent: Lowe Hauptman Ham & Berner, LLP

20080160767 - Semiconductor device and method for forming pattern in the same: A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate and a second hard mask layer over the first hard mask layer, selectively etching the second hard mask layer and the first hard mask layer by using a... Agent: Marshall, Gerstein & Borun LLP

20080160771 - Etching method using hard mask in semiconductor device: An etching method in a semiconductor device includes forming a nitride-based first hard mask layer over a target etch layer, forming a carbon-based second hard mask pattern over the first hard mask layer, etching the first hard mask layer using the second hard mask pattern as an etch barrier to... Agent: Blakely Sokoloff Taylor & Zafman

20080160774 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes providing a substrate having a first and a second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer to have different thicknesses over the first and the second regions, forming a hard... Agent: Blakely Sokoloff Taylor & Zafman

20080160769 - Method for fabricating semiconductor device with recess gate: A method for fabricating a semiconductor device includes forming a structure including a sacrificial layer and a hard mask over a substrate, performing a plasma treatment over the structure including the hard mask to form a protective layer over the hard mask, etching the sacrificial layer using the protective layer... Agent: Lowe Hauptman Ham & Berner, LLP

20080160772 - Method for forming fine pattern in semiconductor device: A method for forming a fine pattern in a semiconductor device is provided. In one aspect, the method can construct a fine pattern in semiconductor devices. The fine pattern has a critical dimension that overcomes the resolution limit of an exposure equipment.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080160770 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming an underlying layer over a semiconductor substrate; forming a hard mask layer over the underlying layer; forming first etch patterns over the hard mask layer; forming second etch patterns between the first photoresist patterns; etching the hard mask layer using the... Agent: Townsend And Townsend And Crew, LLP

20080160773 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device includes a step of preparing a semiconductor substrate in which an edge region and a cell formation region are defined. Next, an insulating layer is deposited on an entire surface of the semiconductor substrate. The insulating layer deposited on the edge region of... Agent: Workman Nydegger

20080160768 - Method of manufacturing gate dielectric layer: A method of manufacturing a gate dielectric layer is described. First, a substrate including a high voltage device region and a low voltage device region is provided. Plural isolation structures are formed in the substrate and protrude from the substrate. A high voltage gate dielectric layer is then formed on... Agent: J C Patents, Inc.

20080160777 - Cleaning method for processing chamber of semiconductor substrates and etching method for silicon substrates technical field: A cleaning method for a processing chamber of semiconductor substrates is provided which is capable of rapidly removing deposits and accretions generated inside the chamber of processing semiconductor substrates of a high-dielectric-constant oxide and of preventing any reaction product depositing. The cleaning method for a processing chamber of semiconductor substrates... Agent: Nixon & Vanderhye, Pc

20080160775 - Method and apparatus for processing a substrate using plasma: Methods and arrangements for controlling the electron loss to the upper electrode, including techniques and apparatus for biasing the upper electrode more negatively to allow charged species to be trapped within the plasma chamber for a longer period of time, thereby increasing the plasma density may be increased. The induced... Agent: Ipsg, P.c.

20080160778 - Method for forming pattern using hard mask: A method for forming a pattern in a semiconductor device includes forming an etch target layer, forming a hard mask over the etch target layer, the hard mask including a multiple-layer stack structure comprising a bottom layer, a transformed layer, and an upper layer, wherein the transformed layer is formed... Agent: Blakely Sokoloff Taylor & Zafman

20080160776 - Plasma-enhanced substrate processing method and apparatus: A method and apparatus for processing a substrate in a capacitively-coupled plasma processing system having a plasma processing chamber and at least an upper electrode and a lower electrode. The substrate is disposed on the lower electrode during plasma processing. The method includes providing at least a first RF signal,... Agent: Ipsg, P.c.

20080160779 - By-die-exposure for patterning of holes in edge die: In accordance with the invention, there are semiconductor devices and methods of making semiconductor devices and holes. The method of making a semiconductor device can comprise forming a photoresist layer over a surface of a wafer, wherein the wafer comprises an edge that has a substantially rounded profile, an array... Agent: Texas Instruments Incorporated

20080160780 - Method and apparatus for depositing charge and/or nanoparticles: A method of forming a charge pattern includes treating a stamp layer with a plasma, applying the treated stamp layer to a surface of a substrate to thereby form a charge pattern on the surface of the substrate, and separating the stamp layer from the surface of the substrate. In... Agent: Westman Champlin & Kelly, P.a.

20080160781 - Substrate processing method, substrate processing system, and computer-readable storage medium: In the present invention, a plurality of rounds of patterning are performed on a substrate. In a patterning system, the substrate on which a first round of patterning has been performed is transferred to a planarizing film forming unit, where a planarizing film is formed above the substrate. The substrate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080160782 - Method for forming insulating film: A method of forming an insulating film for enhancing the film and removing water and OH groups from the film efficiently. The method comprises steps of forming a second low dielectric constant insulating film having a thickness smaller than a desired thickness in a predetermined material gas atmosphere, carrying out... Agent: Harness, Dickey & Pierce, P.L.C

20080160783 - Method for manufacturing semiconductor device: A method for manufacturing semiconductor device according to the present invention comprises a first film forming step of forming, on a concave and convex portion formed by an element on a semiconductor substrate, an oxidation preventive layer which prevents permeation of moisture into the element; a second film forming step... Agent: Griffin & Szipl, Pc

20080160784 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device for minimizing stress applied to a gate oxide layer or a tunnel oxide layer includes the steps of providing a semiconductor substrate in which a semiconductor device including a word line is formed, forming a capping layer including a first insulating layer having... Agent: Lowe Hauptman Ham & Berner, LLP

20080160785 - Method of forming oxide layer in semiconductor device: A method of forming an oxide layer in a semiconductor device comprising the step of loading a semiconductor substrate in a chamber, optionally increasing a temperature of an interior of the chamber, performing the first oxidation process in the chamber under the atmosphere of ozone to form an oxide layer... Agent: Marshall, Gerstein & Borun LLP

20080160786 - Method for increasing film stress and method for forming high stress layer: A method for forming a high stress layer is provided. According to the method, a substrate is put into a reactor of a PECVD machine and a reaction gas is added into the reactor. Then, an assistant reaction gas which has the molecular weight greater than or equal to the... Agent: Jianq Chyun Intellectual Property Office

20080160787 - Method for manufacturing a thin-layer structure: A method for manufacturing a thin-layer structure is disclosed. In one embodiment a macroporous supporting structure substrate having a plurality of pores that do not pass through the entire thickness of the substrate layer, a sacrificial layer is applied on the surface of the pore walls and the pore bottoms... Agent: Dicke, Billig & Czaja

20080160789 - Laser patterning of encapsulated organic light emitting diodes: Disclosed herein are methods of laser patterning organic light emitting diodes by permanently changing the light emissivity of the diodes.... Agent: 3m Innovative Properties Company

20080160788 - Methods for producing smooth wafers: Methods for reducing the surface roughness of semiconductor wafers through a combination of rough polishing and thermally annealing the wafer.... Agent: Senniger Powers LLP