Semiconductor device manufacturing: process inventions 06/08

20080153179 - Magnetic random access memory device and method of forming the same: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate... Agent: Harness, Dickey & Pierce, P.L.C

20080153178 - Method for fabricating mram: A method of fabricating a magnetic random access memory (MRAM) is provided. A metal interconnection, a magnetic tunnel junction layer, and an interlayer dielectric layer are formed on a semiconductor substrate. A portion of the interlayer dielectric layer is selectively removed, leaving protruded regions. A metal layer is then formed... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080153180 - Integrated circuit wafer system with control strategy: An integrated circuit wafer system includes an integrated circuit wafer, measuring thicknesses of the integrated circuit wafer, calculating a change in temperature ramp rates and thickness offsets for subsequent processing based on the temperature ramp rates for prior processing and the resultant thicknesses, and calculating an average temperature and deposition... Agent: Law Offices Of Mikio Ishimaru

20080153181 - Substrate processing method, substrate processing system, and computer-readable recording medium recording program thereon: In the present invention, the position of a substrate on a thermal plate is detected when baking after exposure is performed in a first round of patterning. In a second round of patterning, the setting position of the substrate is adjusted based on a detection result of the position before... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080153182 - Method and system to measure and compensate for substrate warpage during thermal processing: A method of performing a thermal process using a bake plate of a track lithography tool. The bake plate includes a plurality of heater zones. The method includes providing a first drive signal to a first electrode in electrical communication with a process surface of the bake plate. The first... Agent: Townsend And Townsend And Crew, LLP

20080153183 - Floating gate process methodology: A method of deprocessing a semiconductor structure is provided. The method involves removing a silicide layer over a second poly layer, an interpoly dielectric layer, a first poly layer, an optionally an oxide layer on a substrate. The method may further involve at least one of removing a second poly... Agent: Amin, Turocy & Calvin, LLP

20080153185 - Copper process methodology: A method of deprocessing a semiconductor structure is provided. The method involves removing one or more interlevel dielectric layers and one or more metal components from a frontside of the semiconductor structure. By removing the interlevel dielectric layer and the metal component, the exposed portion of the semiconductor structure can... Agent: Amin, Turocy & Calvin, LLP

20080153186 - Evaluation method for crystal defect in silicon single crystal wafer: The present invention provides an evaluation method for a crystal defect in a silicon single crystal wafer based on an infrared laser scattering tomograph method, wherein at least, the silicon single crystal wafer is irradiated with a laser beam, and light that enters the silicon single crystal wafer is scattered... Agent: Oliff & Berridge, Plc

20080153184 - Method for manufacturing integrated circuits by guardbanding die regions: The invention provides a method for manufacturing an integrated circuit. The method, in one embodiment, includes inspecting a semiconductor wafer including a plurality of die for a defect, the inspecting providing an image of the semiconductor wafer including the defect. The method further includes identifying an area of the semiconductor... Agent: Texas Instruments Incorporated

20080153187 - Chip-probing and bumping solutions for stacked dies having through-silicon vias: A method of forming a semiconductor structure includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate; a plurality of through-silicon vias in the substrate; and a plurality of under bump metallurgies (UBMs)... Agent: Slater & Matsil, L.l.p.

20080153188 - Apparatus and method for forming semiconductor layer: Grooves forming a thin-film transistor (TFT) pattern are formed on the surface of a roller. A tank supplies ink including semiconductor materials to the roller. A squeegee embeds the ink supplied to the roller into the grooves formed on the surface thereof. The roller transfers the ink embedded in the... Agent: Birch Stewart Kolasch & Birch

20080153189 - Method for producing a radiation-emitting-and-receiving semiconductor chip: A method for producing an integrated semiconductor component comprising a first semiconductor layer construction for emitting radiation and a second semiconductor layer construction for receiving radiation, wherein a substrate is first provided and a first semiconductor layer sequence containing a radiation-generating region is deposited epitaxially on the substrate. A second... Agent: Cohen, Pontani, Lieberman & Pavane

20080153190 - Light emitting diode package with direct leadframe heat dissipation: A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension.... Agent: Kathy Manke Avago Technologies Limited

20080153191 - Iii-nitride light emitting devices grown on templates to reduce strain: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template... Agent: Patent Law Group LLP

20080153192 - Iii-nitride light emitting devices grown on templates to reduce strain: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template... Agent: Patent Law Group LLP

20080153193 - Methods for fabricating solid state image sensor devices having non-planar transistors: Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current.... Agent: Frank Chau, Esq. F. Chau & Associates, Llc

20080153194 - Method for manufacturing image sensor: A method for manufacturing an image sensor is provided. An interlayer insulating layer can be formed on a semiconductor substrate including a metal line, and a pad can be formed on the interlayer insulating layer. An insulating layer can be formed on the interlayer insulating layer and the pad, and... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080153195 - Semiconductor optical sensors: A method for forming an optical sensor. First, a structure which comprises a semiconductor substrate is provided. Then, a first electrode and a fourth electrode are formed at a first depth in the semiconductor substrate. Then, a second electrode and a fifth electrode are formed at a second depth in... Agent: Schmeiser, Olsen & Watts

20080153197 - Gate oxide film structure for a solid state image pick-up device: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide... Agent: Birch Stewart Kolasch & Birch

20080153196 - Image sensor device and method of manufacturing the same: A method of manufacturing image sensor devices, in which a dielectric protecting layer is formed on a photo-receiving region before a gate of a MOS is formed. Therefore, during the subsequent processes for forming the MOS component, damage to the surface of the photo-receiving region caused by plasma or etching... Agent: North America Intellectual Property Corporation

20080153198 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor according to an embodiment includes: forming an interlayer dielectric layer over a metal wiring on a semiconductor substrate; forming a capping layer on the interlayer dielectric layer; forming a hard mask layer on the capping layer; forming a contact hole by selectively... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080153199 - Method of field-controlled diffusion and devices formed thereby: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/−50... Agent: Jas Ip Consulting

20080153201 - Flip chip mounting method by no-flow underfill having level control function: In a flip chip mounting method by a no-flow underfill in which a resin 54 is pre-coated on a substrate 52, and, thereafter, a semiconductor 50 with bump is mounted on the substrate 52 to join the pad electrode 53 of the substrate 52 to a bump 51, the substrate... Agent: Paul A. Fattibene Fattibene & Fattibene

20080153200 - Stacked semiconductor components: A first semiconductor chip is formed using a first process technology. A plurality of through-vias are formed in the first semiconductor chip and the first semiconductor chip is thinned such that each through-via extends from the upper surface to the lower surface of the chip. A second semiconductor chip is... Agent: Slater & Matsil LLP

20080153202 - Flip chip mounting method by no-flow underfill: Solving Means In a flip chip mounting method by a no-flow underfill in which resin is pre-coated on a substrate 52, and, thereafter, a semiconductor 50 with bump is mounted on the substrate 52 to join a pad electrode 53 on the substrate 52 to the bump 51, a resin... Agent: Paul A. Fattibene Fattibene & Fattibene

20080153203 - Semiconductor device manufacturing method: In a method of manufacturing a semiconductor device, the method includes: a) preparing one type of an ASIC chip; b) preparing memory chips which are different from each other; c) preparing a common circuit substrate; d) preparing a pedestal terminal chip including wiring patterns having memory chip terminals and external... Agent: Rankin, Hill & Clark LLP

20080153207 - Breakable interconnects and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include placing an anisotropic conductive layer comprising at least one compliant conductive sphere on at least one interconnect structure disposed on a first substrate, applying pressure to contact the compliant conductive spheres to the at least one interconnect... Agent: Intel Corporation C/o Intellevate, Llc

20080153206 - Chip mounting with flowable layer: A circuit structure may be formed in a substrate having a face and an open trench, where one or more chips are to be mounted. At least one bridge may extend across an intermediate portion of the trench, and optionally, may divide the trench into sections. A conductive adhesive layer... Agent: Kolisch Hartwell, P.c.

20080153205 - Semiconductor device and a method for manufacturing the same: c

20080153204 - Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods: An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes one or more vias having conductive material formed therein... Agent: Trask Britt, P.c./ Micron Technology

20080153208 - Semiconductor package block mold and method: Semiconductor device packages and methods related to their manufacture are described in which improved block molds and block-molding methods alleviate warpage in semiconductor device manufacturing processes. Preferred embodiments of the invention are disclosed in which semiconductor device package manufacturing includes placing an array of chips mounted on a substrate within... Agent: Texas Instruments Incorporated

20080153209 - Thinned die integrated circuit package: A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat... Agent: Schwegman, Lundberg & Woessner, P.a.

20080153210 - Electronic assembly having an indium wetting layer on a thermally conductive body: Embodiments include electronic packages and methods for forming electronic packages. One method includes providing a die and a thermal interface material on the die. A metal body is adapted to fit over the die. A wetting layer of a material comprising indium is formed on the metal body. The thermal... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20080153211 - Insulated power semiconductor module with reduced partial discharge and manufacturing method: A method for assembling a power semiconductor module with reduced partial discharge behavior is described. The method comprises the steps of bonding an insulating substrate (2) onto a bottom plate (11); disposing a first conductive layer (4) on a portion of said insulating substrate (2), so that at least one... Agent: Buchanan, Ingersoll & Rooney Pc

20080153212 - Semiconductor device and manufacturing method thereof: A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode... Agent: Rossi, Kimms & Mcdowell LLP.

20080153213 - Integrated circuit device, and method of fabricating same: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, integrated circuit device includes memory portion having, for example, PD or... Agent: Neil Steinberg

20080153214 - Method of manufacturing driving-device for unit pixel of organic light emitting display: Provided is a method of manufacturing a driving-device for a unit pixel of an organic light emitting display having an improved manufacturing process in which the driving device can be manufactured with a smaller number of processes and in simpler processes. The method includes: forming an amorphous silicon layer including... Agent: Cantor Colburn, LLP

20080153215 - Leakage barrier for gan based hemt active device: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is... Agent: Patent Administrator Katten Muchin Rosenman LLP

20080153216 - Method for manufacturing silicon carbide semiconductor device: A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each... Agent: Posz Law Group, Plc

20080153217 - Dual layer stress liner for mosfets: A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080153219 - Method for manufacturing cmos image sensor: A method for manufacturing a CMOS image sensor is provided. A metal line can be formed over a semiconductor substrate including a transistor structure. Dangling bonding on the surface of the semiconductor substrate can be removed after forming the metal line by injecting a preset amount of hydrogen (H) atoms... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080153218 - Recessed active for increased weffective transistors: A method of manufacturing a semiconductor device having recessed active trenches by providing a substrate with STI and active regions, forming a first oxide layer on the substrate, forming an nitride layer on the first oxide layer, employing a photolithographic process to create at least one recessed active trench through... Agent: Texas Instruments Incorporated

20080153220 - Method for fabricating semiconductor devices using strained silicon bearing material: A method of manufacturing an integrated circuit on semiconductor substrates. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. The semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second... Agent: Townsend And Townsend And Crew, LLP

20080153221 - Use of a single mask during the formation of a transistor's drain extension and recessed strained epi regions: A method 300 for forming a transistor's drain extension 70 and recessed strained epi regions 150 with a single mask step 306. In an example embodiment, the method 300 may include forming a patterned photoresist layer 200 over a protection layer 190 in a NMOS region 50 and then etching... Agent: Texas Instruments Incorporated

20080153224 - Integrated circuit system with memory system: An integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a contact on the outer doped region, thinning the contact for forming a thinned contact, and forming a metal plug... Agent: Farjami & Farjami LLP

20080153222 - Methods for fabricating a split charge storage node semiconductor memory: Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode... Agent: Ingrassia Fisher & Lorenz, P.c.

20080153223 - Using thick spacer for bitline implant then remove: The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening... Agent: Eschweiler & Associates, Llc National City Bank Building

20080153225 - Non-volatile memory in cmos logic process: A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080153226 - Method of forming a flash nand memory cell array with charge storage elements positioned in trenches: NAND arrays of memory cells are described, as well as methods of forming and using them. Memory cell charge storage devices, such as conductive floating gates, are oriented vertically in trenches, with control gates positioned both in the trenches between charge storage elements and over a horizontal surface between the... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080153227 - Nand flash memory device and method of manufacturing the same: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory... Agent: Townsend And Townsend And Crew, LLP

20080153233 - Flash memory with recessed floating gate: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected... Agent: Knobbe Martens Olson & Bear LLP

20080153231 - Manufacturing method of non-volatile memory: A non-volatile memory having a plurality of memory units is provided. Each memory unit includes a first memory cell and a second memory cell. The first memory cell is disposed on the substrate. The second memory cell is disposed on one sidewall of the first memory cell and the substrate.... Agent: Jianq Chyun Intellectual Property Office

20080153232 - Manufacturing method of non-volatile memory: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate... Agent: Jianq Chyun Intellectual Property Office

20080153229 - Method for fabricating flash memory device: A flash memory device fabricating method can include forming a plurality of gate patterns over a semiconductor substrate, forming a first spacer over the semiconductor substrate and against sidewalls of each gate pattern and a second spacer over the first spacer, forming an impurity region in the semiconductor substrate and... Agent: Sherr & Nourse, Pllc

20080153230 - Method for fabricating flash memory device: The present invention relates to a method for fabricating flash memory devices. The method may include the steps of forming an oxide/nitride/oxide (ONO) layer over a semiconductor substrate and a gate electrode on the ONO layer. Next, source/drain impurity region may be formed in a surface of the semiconductor substrate... Agent: Workman Nydegger

20080153228 - Methods for fabricating a memory device including a dual bit memory cell: Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second... Agent: Ingrassia Fisher & Lorenz, P.c.

20080153234 - Flash memory device and method of manufacturing the same: A non-volatile memory device includes a semiconductor substrate having an active region defined by isolation films that extend along a first direction. A control gate line extends along in a second direction perpendicular to the first direction. First and second floating gates are formed on the active region and below... Agent: Townsend And Townsend And Crew, LLP

20080153235 - Insulated gate type semiconductor device and method for fabricating the same: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both... Agent: Miles & Stockbridge Pc

20080153236 - Flash memory devices and methods for fabricating the same: Flash memory devices and methods for fabricating the same are provided. A method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a P-type silicon substrate and implanting an impurity dopant into the substrate substantially between the first gate... Agent: Ingrassia Fisher & Lorenz, P.c.

20080153237 - Selective etch for patterning a semiconductor film deposited non-selectively: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A... Agent: Blakely Sokoloff Taylor & Zafman

20080153238 - Method for forming a most device with reduced transient enhanced diffusion: A method for forming a MOS device on a semiconductor substrate includes steps of: forming a gate structure on the semiconductor substrate; implanting ions into the semiconductor substrate for forming one or more lightly doped drain structures adjacent to the gate structure; thermally treating the semiconductor substrate at a first... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080153240 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate including a core device region and an input/output device region, each of which is formed with a gate dielectric layer and a gate on the gate dielectric layer; performing a first ion implantation in the... Agent: Squire, Sanders & Dempsey L.l.p.

20080153239 - Semiconductor process for butting contact and semiconductor circuit device having a butting contact: According to the present invention, a semiconductor process for butting contact comprises: providing a substrate on which are formed two adjacent transistor gates; implanting a full area between the two adjacent transistor gates by a tilt angle, to form a lightly doped region of a first conductivity type; forming a... Agent: Tung & Associates

20080153241 - Method for forming fully silicided gates: A method for forming a fully silicided gate is disclosed. A gate structure of a transistor device is provided on a substrate. A mask layer is spin-on coated over the substrate to cover the gate structure and source/drain regions of the transistor device. The mask layer is etched back to... Agent: North America Intellectual Property Corporation

20080153242 - Printed metal mask for uv, e-beam, ion-beam and x-ray patterning: A method of forming vias and pillars using printed masks is described. The printed masks are typically made from droplets that include suspended metal nanoparticles. The use of metal to the same metal nanoparticles in both the mask formation and the subsequent formation of conducting structures simplifies the fabrication process.... Agent: Patent Documentation Center

20080153243 - Blanket implant diode: Blanket implant diode which can be used for transient voltage suppression having a P+ substrate implanted with an N-type dopant blanket implant near a top surface of the substrate, creating a P− region. An oxide mask is layered adjacent to and above the P− region. The oxide mask is partially... Agent: Mckee, Voorhees & Sease, P.L.C

20080153244 - Method for manufacturing passive components: A method for manufacturing passive components is disclosed. First, a substrate is provided, and a connecting region, a capacitor region and an inductance region are defined in the substrate. The substrate includes a first metal layer and an insulating layer on the first metal layer. Subsequently, the insulating layer is... Agent: North America Intellectual Property Corporation

20080153245 - Semiconductor device and method of forming passive devices: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the... Agent: Quarles & Brady LLP

20080153246 - Tridimensional integrated resistor: A resistor formed in a semiconductor substrate of a first conductivity type comprising parallel trenches, the resistor being formed of a layer of the second conductivity type extending on two opposite walls and the bottom of at least one trench.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.c.

20080153247 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device comprises forming an interlayer insulating film including a storage node contact plug over a semiconductor substrate; forming an etching barrier film, a sacrificial insulating film, and a hard mask film over the storage node contact plug and the interlayer insulating film; forming a... Agent: Marshall, Gerstein & Borun LLP

20080153248 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device that reduces the overall number of masking processes while also preventing short-circuiting between electrodes. The method can include sequentially forming a first insulating film, a lower metal layer, a second insulating material, an upper metal layer, and a third insulating material over a... Agent: Sherr & Nourse, Pllc

20080153250 - Method and structures for indexing dice: A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing... Agent: Graybeal, Jackson, Haley LLP

20080153249 - Method for fabricating semiconductor wafer with enhanced alignment performance: A manufacturing method of a semiconductor wafer includes forming a plurality of alignment trenches in the wafer substrate. A dielectric layer is formed over the substrate filling the trenches. A planarization process is performed to remove the dielectric layer above the substrate. A photolithograph process is subsequently performed to selectively... Agent: J C Patents, Inc.

20080153251 - Method of fabricating a mixed substrate: A method for fabricating a mixed substrate that include insulating material layer portions buried in a substrate of semiconductor material. The method includes providing a support substrate made of semiconductor material and having a front face that includes open cavities; providing a layer of an insulating material upon the front... Agent: Winston & Strawn LLP Patent Department

20080153252 - Method and apparatus for providing void structures: The present invention relates to integrated circuits. In particular, but not exclusively, the invention relates to a method and apparatus for connecting elements of integrated circuits with interconnects having one or more voids formed between adjacent interconnects. Embodiments of the invention provide apparatus for connecting elements in an integrated circuit... Agent: Horizon Ip Pte Ltd

20080153253 - Chemical mechanical polishing process and method of fabricating semiconductor device using the same: A chemical mechanical polishing process and a method of fabricating a semiconductor device using the same are provided. The chemical mechanical polishing process includes applying a polishing activation solution with a reduced surface energy, wherein the polishing activation solution includes a surfactant; and polishing the object using the polishing activation... Agent: Harness, Dickey & Pierce, P.L.C

20080153254 - Semiconductor device and method for manufacturing semiconductor device: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type... Agent: Mcdermott Will & Emery LLP

20080153255 - Method of forming device isolation film of semiconductor device: A method of forming a device isolation film of a semiconductor device is provided. The method of forming a device isolation film of a semiconductor device according to an embodiment includes forming the device isolation film by ion-implanting insulation materials inside of a trench formed on a semiconductor substrate.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080153256 - Methods and systems for nitridation of sti liner oxide in semiconductor devices: The invention provides methods for forming isolation structures and STI trenches in a semiconductor device, which may be carried out in a variety of semiconductor manufacturing processes. One embodiment of the invention relates to a method of forming a semiconductor device having isolation structures. In this method, trench regions are... Agent: Texas Instruments Incorporated

20080153257 - Method for producing a semiconductor-on-insulator structure: The invention relates to a process of treating a structure for electronics or optoelectronics, wherein the structure that has a substrate, a dielectric layer having a thermal conductivity substantially higher than thermal conductivity of an oxide layer made of an oxide of a semiconductor material, an oxide layer made of... Agent: Winston & Strawn LLP Patent Department

20080153258 - Process and device for bonding wafers: The invention relates to a process and a device for bonding at least two substrates (1, 2), in particular semiconductor substrates or wafers, having the following features: a) a lower pressure plate (5) for holding the substrates (1, 2) and transferring pressure and, in particular, heat to the substrates (1,... Agent: Kusner & Jaffe Highland Place Suite 310

20080153259 - Soi wafer and method for producing it: An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the... Agent: Brooks Kushman P.c.

20080153261 - Method and device for producing semiconductor wafers of silicon: Semiconductor wafers of silicon are produced by pulling a single crystal from a melt contained in a crucible and slicing semiconductor wafers from the pulled single crystal, heat being delivered to a center of the growing single crystal at the boundary with the melt during the pulling of the single... Agent: Brooks Kushman P.c.

20080153260 - Semiconductor wafer sawing system and method: Semiconductor wafer sawing systems and methods are described in which a wafer may be secured in a sawing position having a surface exposed to incur sawing with at least a portion of the exposed wafer surface positioned below the center of gravity of the wafer such that prevailing force of... Agent: Texas Instruments Incorporated

20080153263 - Singulation method of semiconductor device: Provided is a singulation method of a semiconductor device that can perform a sawing process while protecting a pad. In the singulation method for forming a semiconductor device including a scribe lane region and a chip region, pads are formed in the chip region. Photoresist patterns exposing the scribe lane... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080153262 - Wafer system with partial cuts: A wafer system is provided including providing a wafer having a topside and a backside, forming a partial cut from the topside of the wafer within a wafer rim and thinning the wafer from the backside for exposing the partial cut at the backside within the wafer rim.... Agent: Law Offices Of Mikio Ishimaru

20080153264 - Wafer dividing method: A method of dividing a wafer having a plurality of devices, which are formed in a plurality of areas sectioned by streets formed in a lattice pattern on the front surface, and having test metal patterns which are formed on the streets, comprising the steps of: a laser beam application... Agent: Smith, Gambrell & Russell

20080153265 - Semiconductor device manufactured using an etch to separate wafer into dies and increase device space on a wafer: In one aspect, the method comprises etching a trench into a scribe street located between dies formed on a semiconductor wafer. The dies each have circuitry, and the etching is conducted to a depth within the semiconductor wafer that extends beyond a depth of the circuitry. The etch forms an... Agent: Texas Instruments Incorporated

20080153266 - Method to improve the selective epitaxial growth (seg) process: A method of producing a semiconductor device using a selective epitaxial growth (SEG) process is disclosed. In one aspect, the method comprises providing a semiconductor substrate, forming a pattern of an insulation material on the semiconductor substrate, thereby defining a covered and non covered surface, performing a cleaning processing of... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080153267 - Method for manufacturing a soi substrate associating silicon based areas and gaas based areas: m

20080153268 - Atmosheric pressure chemical vapor deposition: A process for coating a substrate at atmospheric pressure comprises the steps of vaporizing a controlled mass of semiconductor material at substantially atmospheric pressure within a heated inert gas stream, to create a fluid mixture having a temperature above the condensation temperature of the semiconductor material, directing the fluid mixture... Agent: Fraser Clemens Martin & Miller Llc

20080153269 - Thin oxide dummy tiling as charge protection: The present invention pertains to a system and method for implementing dummy tiles in forming a memory device. The system and method involves forming at least a portion of a memory core array upon a semiconductor substrate comprising, forming STI structures in the substrate, depositing an oxide layer over the... Agent: Eschweiler & Associates, Llc National City Bank Building

20080153270 - Method for tuning epitaxial growth by interfacial doping and structure including same: A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration... Agent: Scully, Scott, Murphy & Presser, P.c.

20080153272 - Method for manufacturing soi substrate: A hydrogen ion is implanted into a surface of a single-crystal Si substrate 10 via an oxide film 11 to form a uniform ion implantation layer 12 at a predetermined depth near a surface of the single-crystal Si Substrate 10. At this time, ion implantation is carried out under a... Agent: Oliff & Berridge, Plc

20080153271 - Safe handling of low energy, high dose arsenic, phosphorus, and boron implanted wafers: A method of preventing toxic gas formation after an implantation process is disclosed. Certain dopants, when implanted into films disposed on a substrate, may react when exposed to moisture to form a toxic gas and/or a flammable gas. By in-situ exposing the doped film to an oxygen containing compound, dopant... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080153273 - Method for manufacturing a semiconductor device having improved across chip implant uniformity: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, in one embodiment, includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In... Agent: Texas Instruments Incorporated

20080153274 - Deep bitline implant to avoid program disturb: A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing... Agent: Eschweiler & Associates, Llc National City Bank Building

20080153275 - Non-uniform ion implantation apparatus and method thereof: A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide... Agent: Townsend And Townsend And Crew, LLP

20080153276 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is capable of increasing the size of a landing plug without loss of an insulating film separating the landing plug, and may be advantageously used for reducing contact resistance by enlarging a landing plug contact hole without causing the loss of the insulating... Agent: Marshall, Gerstein & Borun LLP

20080153277 - Exposure mask and method for fabricating semiconductor device using the same: An exposure mask for recess gate includes a transparent substrate and a recess gate pattern. The recess gate pattern is disposed over the transparent substrate. The recess gate pattern includes a first portion having a first line width and a second portion having a second line width smaller than the... Agent: Marshall, Gerstein & Borun LLP

20080153278 - Doped single crystal silicon silicided efuse: An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080153279 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes the steps of: forming a primary storage node contact plug at an upper part of the exposed landing plug at a lower part of the storage node contact hole; and filling the storage node contact hole with a conductive film to form... Agent: Marshall, Gerstein & Borun LLP

20080153280 - Reactive sputter deposition of a transparent conductive film: Methods for sputter depositing a transparent conductive oxide (TCO) layer are provided in the present invention. The transparent conductive oxide layer may be utilized as a back reflector in a photovoltaic device. In one embodiment, the method includes providing a substrate in a processing chamber, forming a first portion of... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080153281 - Fabrication for electroplating thick metal pads: A method of electroplating includes forming a seed region to be electroplated on a first portion of a substrate, forming a ground plane on a second portion of a substrate, electrically isolating the ground plane from the seed region, electroplating the region, wherein electroplating includes causing the ground plane and... Agent: Marger Johnson & Mccollom/parc

20080153282 - Method for preparing a metal feature surface: Provided is a method for manufacturing an interconnect. The method for manufacturing the interconnect, in one embodiment, includes forming a first metal feature over or within a substrate, the first metal feature having an exposed surface. The method for manufacturing the interconnect may additionally include cleaning the exposed surface using... Agent: Texas Instruments Incorporated

20080153284 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device. In the method according to an embodiment a first electro-chemical plating process using a CuCl2 solution is performed to form a first copper buried layer on a seed layer. A second electro-chemical plating process using a CuSO4 solution is performed to... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080153283 - Soluble hard mask for interlayer dielectric patterning: Described herein are embodiments of a method that includes forming a hard mask over an interlayer dielectric layer, patterning said hard mask, etching said interlayer dielectric layer, and removing said hard mask during a post-etch clean with a wet etchant having a selectivity to etch said hard mask at a... Agent: Michael A. Bernadicou Blakely, Sokoloff, Taylor & Zafman LLP

20080153285 - Patterning metal layers: A process for fabricating an electronic device comprising the step of patterning a metallic electrode to the electronic device by laser ablation followed by electroless plating, wherein the process of fabricating the electronic device comprises at least one other laser patterning step over the area of the metallic electrode performed... Agent: Sughrue Mion, Pllc

20080153286 - Semiconductor chip and method of manufacturing semiconductor chip: A semiconductor chip includes a semiconductor substrate having a first principal surface, and having a device layer on the first principal surface in which a semiconductor device is formed, an electrode pad disposed on the first principal surface of the semiconductor substrate and electrically connected to the semiconductor device, a... Agent: Ladas & Parry LLP

20080153287 - Method for patterning a semiconductor device: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer; forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the... Agent: Sherr & Nourse, Pllc

20080153288 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes implanting metal ions on a residual interlayer dielectric film in a storage contact hole to metallize the residual dielectric film, thereby reducing a contact resistance to prevent failures of the semiconductor device.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080153289 - Method for manufacturing semiconductor devices and plug: A method for manufacturing a semiconductor device is disclosed. The method is suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent... Agent: Jianq Chyun Intellectual Property Office

20080153290 - Method of forming contact: A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate. The first stress... Agent: Jianq Chyun Intellectual Property Office

20080153291 - Method and apparatus for material deposition: Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to... Agent: Martine Penilla & Gencarella, LLP

20080153292 - Silicon carbide polishing method utilizing water-soluble oxidizers: The inventive method comprises chemically-mechanically polishing a substrate comprising at least one layer of silicon carbide with a polishing composition comprising a liquid carrier, an abrasive, and an oxidizing agent.... Agent: Steven Weseman Associate General Counsel, I.p.

20080153293 - Silicon carbide polishing method utilizing water-soluble oxidizers: The inventive method comprises chemically-mechanically polishing a substrate comprising at least one layer of silicon carbide with a polishing composition comprising a liquid carrier, an abrasive, and an oxidizing agent.... Agent: Steven Weseman Associate General Counsel, I.p.

20080153294 - Method for forming self aligned contacts for integrated circuit devices: A method for processing integrated circuit devices including forming self aligned contact regions. The method includes providing a partially completed semiconductor wafer, the wafer including one or more semiconductor chips, where each of the chips including a plurality of MOS gate structures. Each of the gate structures is formed on... Agent: Townsend And Townsend And Crew, LLP

20080153295 - Method of fabricating openings and contact holes: A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to... Agent: North America Intellectual Property Corporation

20080153297 - Fabricating method of a semiconductor device: Disclosed is a method of fabricating a semiconductor device, in which the process steps of a photoresist process for forming a metal line are simply reduced, and a process exerting an influence on the contact hole is minimized, so that the electrical characteristics of the semiconductor device can be improved.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080153296 - Method of formation of a damascene structure utilizing a protective film: Disclosed is a method for the formation of features in a damascene process. According to the method, vias are formed in a dielectric layer and then covered by a layer of high molecular weight polymer. The high molecular weight polymer covers the vias but does not enter the vias. A... Agent: International Business Machines Corporation Dept. 18g

20080153302 - Forming heaters for phase change memories: Rather than depositing a heater material into a pore, a heater material may be first blanket deposited. The heater material may then be covered by a mask, such that the mask and the heater material may be etched to form a stack. Then, the region between adjacent stacks that form... Agent: Trop Pruner & Hu, Pc

20080153298 - Memory device etch methods: A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms... Agent: Harrity Snyder, L.l.p.

20080153300 - Method for forming fine pattern of semiconductor device: A method for forming a fine pattern of a semiconductor device comprises the steps of: preparing a semiconductor substrate including an underlying layer, an insulating film, a bottom anti-reflection film, and a positive photoresist film sequentially; patterning the positive photoresist film to form a positive photoresist pattern; forming a negative... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080153299 - Semiconductor device and method for forming a pattern in the same with double exposure technology: A method for forming a pattern in a semiconductor device includes performing a double exposure process for a multifunctional hard mask layer over a semiconductor substrate using a line/space mask to form a multifunctional hard mask layer pattern having a first contact hole region. The multifunctional hard mask layer pattern... Agent: Marshall, Gerstein & Borun LLP

20080153301 - Set of masks, method of generating mask data and method for forming a pattern: A method of generating mask data, for a set of masks used to transfer a pattern for delineating a circuit pattern of a semiconductor integrated circuit, includes preparing design data having a design pattern corresponding to the pattern to be transferred on a semiconductor substrate; generating resized data by enlarging... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080153303 - Field effect transistor, compound semiconductor substrate and process for forming a recess therein: m

20080153304 - Method of producing a semiconductor device: In a method of producing a semiconductor device, semiconductor burrs (74) are removed by dry etching using an etching gas in which a lateral-direction etch rate (R2) is greater than a depth-direction etch rate (R1) (that is, R1/R2 is smaller than 1) in a section of a groove (72) in... Agent: Scully Scott Murphy & Presser, Pc

20080153306 - Dry photoresist stripping process and apparatus: A process for stripping photoresist from a substrate is provided. A processing system for implanting a dopant into a layer of a film stack, annealing the stripped film stack, and stripping the implanted film stack is also provided. When high dopant concentrations are implanted into a photoresist layer, a crust... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080153305 - Passivating metal etch structures: A method to passivate a freshly etched metal structure comprises providing a metal surface on a substrate that has been etched by a first particle beam, exposing the metal surface to a passivation gas, and exposing the freshly etched metal structures to a second particle beam in the presence of... Agent: Intel Corporation C/o Intellevate, Llc

20080153307 - Method of producing semiconductor device: A method of producing a semiconductor device that a semiconductor substrate having holes formed by a dry etching process is wet-etched and the residue resulting from the dry etching process is removed, comprising a chemical solution supply process of supplying a wet etching chemical solution to the front surface of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080153310 - Integrated circuit having ultralow-k dielectric layer: A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing,... Agent: Horizon Ip Pte Ltd

20080153308 - Substrate processing apparatus: A substrate processing apparatus comprising: a processing chamber which is to accommodate at least one substrate; a gas supply system which is to supply processing gas into the processing chamber; an exhaust system which is to exhaust atmosphere in the processing chamber; and at least one pair of electrodes which... Agent: Birch Stewart Kolasch & Birch

20080153309 - Substrate processing apparatus and semiconductor device producing method: Disclosed is a substrate processing apparatus, including: a processing chamber for processing a substrate; a substrate rotating mechanism for rotating the substrate; a gas supply unit for supplying gas to the substrate, at least two kinds of gases A and B being alternately supplied a plurality of times to form... Agent: Birch Stewart Kolasch & Birch

20080153311 - Method for depositing an amorphous carbon film with improved density and step coverage: A method for depositing an amorphous carbon layer on a substrate includes the steps of positioning a substrate in a chamber, introducing a hydrocarbon source into the processing chamber, introducing a heavy noble gas into the processing chamber, and generating a plasma in the processing chamber. The heavy noble gas... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080153312 - Methods for exposure for the purpose of thermal management for imprint lithography processes: The present invention is directed to a method that attenuates, if not avoids, heating of a substrate undergoing imprint lithography process and the deleterious effects associated therewith. To that end, the present invention includes a method of patterning a field of a substrate with a polymeric material that solidifies in... Agent: Molecular Imprints

20080153313 - Method for producing a semiconductor-on-insulator structure: The invention relates to a process of treating a structure for electronics or optoelectronics, wherein the structure that has a substrate, a first oxide layer, an intermediate layer, a second oxide layer made of an oxide of a semiconductor material, and a thin semiconductor layer made of the semiconductor material.... Agent: Winston & Strawn LLP Patent Department

20080153314 - Substrate processing apparatus, method of manufacturing semiconductor device, and heating apparatus: An object of the present invention is to improve substrate processing efficiency. A substrate processing apparatus has a reaction tube that processes a substrate inside, and a heating apparatus disposed so as to surround an external periphery of the reaction tube, so that at least a gas inlet tube is... Agent: Oliff & Berridge, Plc

20080153315 - Wafer processing method: In a wafer processing method of radiating a pulsed-laser beam to a wafer from a back surface of a silicon substrate to form via holes reaching respective bonding pads, a plurality of devices being formed on a surface of the silicon substrate, the bonding pads being formed on each of... Agent: Greer, Burns & Crain

20080145951 - High density spin torque three dimensional (3d) memory arrays addressed with microwave current: One embodiment of the present invention includes a three dimensional memory array having a plurality of memory elements coupled to form the array through a single top lead and a single bottom lead, each memory element including a magnetic free layer in which non-volatile data can be stored, wherein each... Agent: Law Offices Of Imam

20080145953 - Manufacturing method for ferroelectric memory device: A manufacturing method for a ferroelectric memory device including: forming a lower electrode; forming an electrode oxide film composed of an oxide of a constituent material of the lower electrode; forming a first ferroelectric layer on the lower electrode by reaction between organometallic source material gas and oxygen gas; forming... Agent: Harness, Dickey & Pierce, P.L.C

20080145954 - Manufacturing method for ferroelectric memory device: A manufacturing method for a ferroelectric memory device includes: forming a ferroelectric capacitor on a substrate, the ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode; forming a first hydrogen barrier film that covers the ferroelectric capacitor by a chemical vapor deposition method; forming a dielectric... Agent: Harness, Dickey & Pierce, P.L.C

20080145956 - Method for manufacturing magnetic sensor apparatus: A magnetic sensor apparatus includes a semiconductor substrate and a magnetic impedance device for detecting a magnetic field. The magnetic impedance device is disposed on the substrate. The magnetic sensor apparatus has minimum size and is made with low manufacturing cost. Here, the magnetic impedance device detects a magnetic field... Agent: Posz Law Group, Plc

20080145952 - Mgo-based tunnel spin injectors: A MgO tunnel barrier is sandwiched between semiconductor material on one side and a ferri- and/or ferromagnetic material on the other side to form a spintronic element. The semiconductor material may include GaAs, for example. The spintronic element may be used as a spin injection device by injecting charge carriers... Agent: Daniel E. Johnson Ibm Corporation, Almaden Research Center

20080145955 - Varactors and methods of manufacture and use: In an embodiment of the present invention is provided a method of manufacturing a varactor, comprising providing a substrate; positioning a bottom electrode on a surface of the substrate; placing a tunable dielectric material adjacent to and extending over the bottom electrode forming a step and in contact with a... Agent: James S. Finn Box #8 825

20080145957 - Wafer transferring robot in semiconductor device fabrication equipmentand method of detecting wafer warpage using the same: A wafer transferring robot in semiconductor device fabricating equipment and a method of detecting wafer warpage by using the wafer transferring robot are provided. In the realizing the wafer transferring robot to transfer a wafer, vacuum lines are formed to adsorb a plurality of regions of the wafer. Whether the... Agent: F. Chau & Associates, Llc

20080145958 - Monitoring of electrostatic discharge (esd) events during semiconductor manufacture using esd sensitive resistors: A monitor semiconductor chip that incorporates ESD sensitive resistors is subjected to the same steps in a semiconductor manufacturing process to which functional semiconductor chips are subjected. The ESD sensitive resistors are configured to experience non-volatile changes in resistance in response to ESD events, such that the resistors retain the... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20080145959 - Substrate with transparent electrodes and devices incorporating it: m

20080145960 - Super thin led package for the backlighting applications and fabrication method: First and second light emitting diode (LED) arrays, which each includes a corresponding number of LED dies, are disposed on a substrate proximately and substantially parallel to one another. Each pair of substantially paralleled LED dies of the first and second arrays is covered by substantially transparent optical encapsulant. The... Agent: Scott A. Mccollister, Esg. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20080145962 - Nitride light emitting device and manufacturing method thereof: A nitride LED having a laminated structure in which a substrate, a n-type cladding layer, an active layer, a p-type cladding layer, and a multi-ohmic contact layer are sequentially stacked, and a manufacturing method thereof, are provided. In the nitride LED, the multi-ohmic contact layer includes multiple layers of a... Agent: Buchanan, Ingersoll & Rooney Pc

20080145961 - Semiconductor light emitting device and manufacturing method thereof: A semiconductor light emitting device can have stable electric characteristics and can emit light with high intensity from a substrate surface. The device can include a transparent substrate and a semiconductor layer on the substrate. The semiconductor layer can include a first conductive type semiconductor layer, a luminescent layer, a... Agent: Cermak Kenealy & Vaidya, LLP

20080145963 - Method for fabricating pixel cell of cmos image sensor: The present invention provides a method for fabricating a pixel cell of CMOS image sensor, comprising: preparing a semiconductor substrate divided into region I and region II; forming an insulation layer on the surface of the semiconductor substrate in the region I and a gate dielectric layer on the surface... Agent: Squire, Sanders & Dempsey L.l.p.

20080145964 - Precision synthesis of quantum dot nanostructures for fluorescent and optoelectronic devices: Methods are disclosed generally directed to design and synthesis of quantum dot nanoparticles having improved uniformity and size. In a preferred embodiment, a release layer is deposited on a semiconductor wafer. A heterostructure is grown on the release layer using epitaxial deposition techniques. The heterostructure has at least one layer... Agent: Nutter Mcclennen & Fish LLP

20080145965 - Via wave guide with curved light concentrator for image sensing devices: A CMOS image sensor (CIS) device includes an array of pixels, each pixel including a sensing element (e.g., a photodiode) and access circuitry. To facilitate the passage of light to the photodiode, each pixel includes a via wave guide (VWG) defined in the metallization layer formed over the pixel's photodiode.... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080145966 - Method for fabrication of organic thin-film transistor: A method for fabricating organic thin-film transistors is disclosed. The method includes the steps of: providing a mold and a flexible substrate, wherein the mold comprises microstructures for defining source/drain electrode patterns on the substrate and at least an opening for feeding a solution material; forming an adhesive layer on... Agent: Wpat, Pc Intellectual Property Attorneys

20080145967 - Semiconductor package and manufacturing method thereof: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the... Agent: Rabin & Berdo, Pc

20080145968 - Manufacturing method for micro-sd flash memory card: A method for fabricating MicroSD devices includes forming a PCB panel having multiple PCBs arranged in parallel rows, with each PCB connected to its neighboring PCBs in each row by relatively narrow connecting bridge pieces, and separated from PCBs of adjacent rows by elongated stamped out blank slots. Passive components... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080145969 - Semiconductor package and method for manufacturing the same: A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a... Agent: Lowe Hauptman Ham & Berner, LLP

20080145971 - Semiconductor package, manufacturing method thereof and ic chip: A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bonding pads may... Agent: Harness, Dickey & Pierce, P.L.C

20080145970 - Stack structure and method of manufacturing the same: A stack structure is formed by stacking and bonding a plurality of substrates. The stack structure includes bonding films each of which is interposed in a bonding region between, adjacent glass substrates, and bonded to oxygen atoms in the glass of the substrate by anodic bonding.... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20080145972 - Paste printer and method of printing with paste: A paste printer allows an electrically-conductive pad formed on a board to be exposed in an opening of a masking member. A removal mechanism is allowed to act on the surface of the electrically-conductive pad within the opening. A rust film is removed from the surface of the electrically-conductive pad.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080145973 - Method of manufacturing wafer level chip size package: To widely improve an entire manufacturing efficiency by efficiently forming a thermal stress relaxing post, an insulating layer and a solder bump, a rewiring circuit (3) is formed on a wafer (1) by plating, a thermal stress relaxing post (4) made of a conductive material such as a solder or... Agent: Bacon & Thomas, Pllc

20080145974 - Seed layer for a heat spreader in a magnetic recording head: Magnetic recording heads and associated fabrication methods are disclosed. A heat spreader structure in a magnetic recording head includes a seed layer with a heat spreader layer formed on the seed layer. When the heat spreader layer (e.g., Aluminum Nitride) is grown on the seed layer (e.g., NiTa or Alumina),... Agent: Duft Bornsen & Fishman, LLP

20080145975 - Method for fabricating circuit board structure with embedded semiconductor chip: The invention provides a method for fabricating printed circuit board having an embedded semiconductor chip, including: providing a carrier board including a first and a second surface and at least one through hole penetrating the first and second surfaces; disposing a semiconductor chip in the through hole and including an... Agent: Schmeiser Olsen & Watts

20080145976 - Packaging of micro devices: A silicon wafer is used as a substrate (1). A thin layer of metal is deposited and etched to form device metallisation (3), including electrodes and bondpads. A passivation layer (4) of silicon nitride is patterned to open access points to the metal. A lower sacrificial layer (5) is formed... Agent: Jacobson Holman Pllc

20080145977 - Increasing the resistance of a high frequency input/output power delivery decoupling path: A conductive path, such as a copper patch, between decoupling capacitors and a high frequency integrated circuit, may be oxidized to improve the power delivery performance. Specifically, adding the resistance in the conductive path by oxidizing the conductive path increases the dampening of the peak impedance at a given peak... Agent: Trop Pruner & Hu, Pc

20080145978 - Deposition of silicon germanium nitrogen precursors for strain engineering: Methods for making a semiconductor device are disclosed herein. In general, the disclosed methods utilize compounds containing silicon, nitrogen, and germanium. Furthermore, the methods and compositions described are particularly applicable for formation of layers over gate structures or electrodes, which are often used in the manufacture of devices such as... Agent: Air Liquide Intellectual Property

20080145979 - Method for changing characteristic of thin film transistor by strain technology: A method for changing a characteristic of a thin film transistor (TFT) is provided. The method comprises the steps of (1) providing a substrate; (2) forming the TFT having a channel on the substrate; (3) providing a pressure source; and (4) causing the pressure source to form a strain on... Agent: Volpe And Koenig, P.c.

20080145980 - Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion: A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the... Agent: Cantor Colburn, LLP

20080145981 - Method of manufacturing thin film transistor having lightly doped drain regions: Provided is a method of manufacturing a thin film transistor, the method comprising: forming an amorphous silicon layer on a substrate; forming a polysilicon layer by crystallizing the amorphous silicon layer; forming a mask structure that masks a portion of the polysilicon; forming a source and a drain region and... Agent: Cantor Colburn, LLP

20080145982 - Isolation spacer for thin soi devices: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.... Agent: Haynes And Boone, LLP

20080145983 - Semiconductor device and process for fabricating the same: A semiconductor device comprising at least two thin film transistors on a substrate having an insulating surface thereon, provided that the thin film transistors are isolated by oxidizing the outer periphery of the active layer of each of the thin film transistors to the bottom to provide an oxide insulating... Agent: Eric Robinson

20080145984 - Dual metal silicides for lowering contact resistance: A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming... Agent: Slater & Matsil, L.l.p.

20080145985 - Embedded semiconductor memory devices and methods for fabricating the same: The invention discloses a method for fabricating an embedded semiconductor memory device, comprising: preparing a semiconductor substrate comprising a region IA and a region IB; forming gate dielectric layers and gate structures sequentially on the semiconductor substrate, with the gate dielectric layer in region IA being a charge trap region,... Agent: Squire, Sanders & Dempsey L.l.p.

20080145986 - Structure and method for improved stress and yield in pfets with embedded sige source/drain regions: The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep canyons at the interface between the active area... Agent: Scully, Scott, Murphy & Presser, P.c.

20080145987 - Manufacture of semiconductor device: A reflectance-controlling layer whose reflectance to irradiation of laser light becomes lower as a thickness thereof becomes thinner is formed on a semiconductor substrate having a first region and a second region. Thereafter, the reflectance-controlling layer on the first region is etched. Then, a laser light is irradiated to the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080145988 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. A nickel layer is deposited on a semiconductor substrate and plasma-processed. Rapid thermal processing is performed on the plasma-processed nickel layer to form a nickel silicide layer. The portion of the nickel layer that has not reacted with silicon is then... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080145989 - Semiconductor device having partially insulated field effect transistor (pifet) and method of fabricating the same: Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form... Agent: Marger Johnson & Mccollom, P.c.

20080145990 - Method and structure for fabricating mos devices with a salicided gate and source/drain combined with a non-silicide source drain regions: A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer... Agent: Townsend And Townsend And Crew, LLP

20080145991 - Slim spacer implementation to improve drive current: Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers... Agent: Texas Instruments Incorporated

20080145992 - Method of manufacturing a semiconductor device having reduced n/p or p/n junction crystal disorder: One aspect provides a method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder. In one aspect, this improvement is achieved by forming gate electrodes over a semiconductor substrate, amorphizing the semiconductor substrate that creates amorphous regions adjacent the gate electrodes to a depth in the... Agent: Texas Instruments Incorporated

20080145993 - Electrostatic discharge protection device and method of fabricating same: A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried... Agent: Schmeiser, Olsen & Watts

20080145994 - Method for isotropic doping of a non-planar surface exposed in a void: A method is described for isotropic or nearly isotropic shallow doping of a non-planar surface exposed in a void. The results of ion implantation, a common doping method, are inherently planar. Some fabrication methods and devices may require doping a surface of a non-planar feature exposed in a void, such... Agent: Dugan & Dugan, Pc

20080145995 - Methods for forming process test capacitors for testing embedded passives during embedment into a printed wiring board: Making process test capacitors simultaneously with circuit capacitors that are to be embedded into a printed wiring board and firing the test capacitors to result in fired-on-foil test capacitors for the purpose of using the test capacitors as test substitutes for the embedded circuit capacitors to predict whether capacitance, dissipation... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080145996 - Method for manufacturing dielectric thin film capacitor: A method for manufacturing a dielectric thin film capacitor without causing cracks in a protective layer which covers a capacitor portion is provided. The method for manufacturing the dielectric thin film capacitor includes a step of forming a tapered resist pattern on a capacitor structure and a dry etching step... Agent: Dickstein Shapiro LLP

20080145997 - Method of forming a metal-insulator-metal capacitor: A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080145999 - Method for manufacturing a semiconductor device: A method of a semiconductor device comprises: a) depositing a first semiconductor layer and a second semiconductor layer in a semiconductor substrate in series; b) forming a first groove penetrating the first and second semiconductor layers and placed adjacent to an element region by partly etching the first and second... Agent: Harness, Dickey & Pierce, P.L.C

20080145998 - Method of forming a low-k dual damascene interconnect structure: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a... Agent: Moser Ip Law Group / Applied Materials, Inc.

20080146000 - Method of forming isolation structure of flash memory device: A method of forming a semiconductor memory device includes providing a semiconductor substrate having a cell region and a peripheral region. A gate dielectric layer is formed over the semiconductor substrate in the peripheral region. An insulating layer is formed over the gate dielectric layer. An isolation trench is formed... Agent: Townsend And Townsend And Crew, LLP

20080146001 - Pre-sti nitride descum step for increased margin against sti seam voids: A method of forming a shallow trench isolation structure is provided, and includes forming a mask structure over active regions of a substrate, thereby defining a trench region therebetween. A descum is then performed to remove any particulate matter that may be in the trench region over the substrate. A... Agent: Texas Instruments Incorporated

20080146002 - Method of manufacturing semiconductor device having buried gate: A method of manufacturing a semiconductor device having buried gates may include forming a stacked structure of sequentially stacked first mask patterns and second mask patterns with equal widths to expose active regions and isolation regions of a semiconductor substrate. After forming reduced first mask patterns by decreasing the width... Agent: Harness, Dickey & Pierce, P.L.C

20080146003 - Method and device for separating silicon wafers: The invention relates to a method for separation of a silicon wafer (12a) from a vertical stack (10) of silicon wafers (12). The method is characterised in that it comprises attaching a movable transport device (2) to a surface of the silicon wafer (12a) in the stack (10), and horizontal... Agent: Birch Stewart Kolasch & Birch

20080146005 - Methods for creating a densified group iv semiconductor nanoparticle thin film: A method of forming a densified nanoparticle thin film in a chamber is disclosed. The method includes positioning a substrate in the chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink... Agent: Foley & Lardner LLP

20080146004 - Silicon carbide devices and method of making: A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.... Agent: General Electric Company Global Research

20080146006 - Crystal imprinting methods for fabricating substrates with thin active silicon layers: Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080146007 - Method to increase the compressive stress of pecvd dielectric films: A method for forming a compressive stress carbon-doped silicon nitride layer is provided. The method includes forming an initiation layer and a bulk layer thereon, wherein the bulk layer has a compressive stress of between about −0.1 GPa and about −10 GPa. The initiation layer is deposited from a gas... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080146008 - Ultra-thin high-quality germanium on silicon by low-temperature epitaxy and insulator-capped annealing: Exemplary embodiments provide semiconductor devices with a high-quality semiconductor material on a lattice mismatched substrate and methods for their manufacturing using low temperature growth techniques followed by an insulator-capped annealing process. The semiconductor material can have high-quality with a sufficiently low threading dislocation (TD) density, and can be effectively used... Agent: Mh2 Technology Law Group, LLP

20080146009 - Method for introducing impurities: At the time of switching over plasmas which are used in plasma irradiation for realization of amorphous and plasma doping, electric discharge is stopped, and an initial condition of a matching point of a high frequency power supply and a peripheral circuit is reset so as to adapt to plasma... Agent: Pearne & Gordon LLP

20080146010 - Semiconductor component comprising a semiconductor chip and method for producing the same: A semiconductor component (1) has a semiconductor chip (5) and a semiconductor component carrier (3) with external connection strips (12, 13, 15). The semiconductor chip (5) has a first electrode (6) and a control electrode (7) on its top side (8) and a second electrode (9) on its rear side... Agent: Banner & Witcoff, Ltd. Attorneys For Client 007052

20080146011 - Method of forming self-assembled monolayer on ito film: Disclosed is a method of modifying the surface of an ITO (Indium Tin Oxide; In2O3—SnO2) film using new organic material to increase the properties of the ITO film. A method of forming a self-assembled monolayer on an ITO film to increase the work function of an ITO film for use... Agent: Adam K. Sacharoff Much Shelist Freed Denenberg Ament&rubenstein,pc

20080146012 - Novel method to adjust work function by plasma assisted metal incorporated dielectric: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric on a substrate; introducing metal dopants into the gate dielectric; annealing the gate dielectric; and forming a gate electrode on the gate dielectric.... Agent: Haynes And Boone, LLP

20080146013 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0≦x<0.25), subjecting the first layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080146014 - Self aligned contact: A semiconductor device comprises one or more self aligned contacts. The device may include one or more gate structures adjacent a first doped region. The device may comprise a first dielectric overlaying the gate structure and a first layer comprising silicon and overlaying a top of each said gate structure,... Agent: Macpherson Kwok Chen & Heid LLP

20080146015 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080146018 - Chip structure and method for fabrication the same: A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first... Agent: Mou-shiung Lin

20080146016 - Method for forming a structure: Method for constructing a line or dotted structure on a support, especially for constructing strip-like electrically conducting contacts on a semiconductor component such as a solar cell, by applying an electrically conducting paste-like substance containing a solvent adhering to a support and subsequent hardening of the substance. After the substance... Agent: Dennison, Schultz & Macdonald

20080146017 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device comprises: (a) stacking a first semiconductor layer and a second semiconductor layer serially on a semiconductor substrate; (b) providing a protection film above the second semiconductor layer; (c) providing a first groove that penetrates the protection film, the second semiconductor layer, and the... Agent: Harness, Dickey & Pierce, P.L.C

20080146019 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080146020 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20080146021 - Method of fabricating metal interconnects and inter-metal dielectric layer thereof: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the... Agent: North America Intellectual Property Corporation

20080146022 - Methods of forming conductive interconnects: The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel salt.... Agent: Wells St. John P.s.

20080146023 - Method of forming metal wire in semiconductor device: A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the... Agent: Townsend And Townsend And Crew, LLP

20080146024 - Method for forming a metal structure: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in... Agent: North America Intellectual Property Corporation

20080146025 - Methods and systems for barrier layer surface passivation: This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and... Agent: Larry Williams

20080146026 - Method for manufacturing semiconductor device capable of reducing parasitic bit line capacitance: A semiconductor memory device is manufactured by: forming a hole by etching an interlayer insulation film formed over a semiconductor substrate; forming a barrier film over the interlayer insulation film including a surface of the hole; forming a first metal film over the barrier film so as to fill in... Agent: Ladas & Parry LLP

20080146027 - Method of forming wiring of a semiconductor memory device: A method of forming a wiring for a semiconductor memory device includes obtaining a semiconductor substrate, depositing at least one conductive layer on the semiconductor substrate under controlled conditions, such as substrate temperature and atmosphere temperature, to provide a conductive layer exhibiting a reduced surface roughness as compared to a... Agent: Lee & Morse, P.c.

20080146028 - Method of depositing copper using physical vapor deposition: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50° C. or less, with the deposition taking place at... Agent: Paul J. Winters

20080146029 - Method of forming an interconnect structure: A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and... Agent: Schmeiser, Olsen & Watts

20080146030 - System and method for direct etching: System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first word line and a second word line. The contact... Agent: Townsend And Townsend And Crew, LLP

20080146031 - Method for forming a semiconductor structure: A method for semiconductor structure formation includes: providing a substrate; forming a first lower mask layer on the substrate; forming a first patterned mask on the first lower mask layer; forming a second lower mask layer on the first lower mask layer and overlaying the first patterned mask; forming a... Agent: Birch Stewart Kolasch & Birch

20080146032 - Glue layer for hydrofluorocarbon etch: A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the... Agent: Beyer Law Group LLP

20080146033 - Gap-filling method of semiconductor device: A gap-filling method of a semiconductor device is realized without voids by providing the optimal deposition conditions based on DED conditions related to etching time, etching number and RF frequency. The method includes (a) depositing a first high-density plasma oxide film to fill some of a gap; (b) etching some... Agent: Sherr & Nourse, Pllc

20080146035 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a SiGe layer on a Si substrate, forming a dummy pattern to expose a surface of the Si substrate, and wet etching the SiGe layer while an etchant is contacted with, the dummy pattern.... Agent: Harness, Dickey & Pierce, P.L.C

20080146034 - Method for recess etching: Methods for recess etching are provided herein that advantageously improve lateral to vertical etch ratio requirements, thereby enabling deeper recess etching while maintaining relatively shallow vertical etch depths. Such enhanced lateral etch methods advantageously provide benefits for numerous applications where lateral to vertical etch depth ratios are constrained or where... Agent: Moser Ip Law Group / Applied Materials, Inc.

20080146036 - Semiconductor manufacturing process: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it.... Agent: North America Intellectual Property Corporation

20080146037 - Use of a porous dielectric material as an etch stop layer for non-porous dielectric films: Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided herein. The novel interconnect structures are capable... Agent: Scully, Scott, Murphy & Presser, P.c.

20080146038 - Solvent bath and drain: According to one aspect of the invention, a wafer processing apparatus is provided. The wafer processing apparatus may include a wafer support, a dispense head, and a solvent bath. The dispense head may be moveable between a position over the wafer support and a position over the solvent bath. When... Agent: Blakely Sokoloff Taylor & Zafman

20080146040 - Local plasma processing: A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being... Agent: Schmeiser, Olsen & Watts

20080146039 - Method to reduce plasma charge damage from high density plasma chemical vapor deposition (hdp-cvd) process: A method of processing wafers within a high density plasma chemical vapor deposition chamber comprises setting a plasma charge level within the chamber at a zero power level and, while the plasma charge level within the chamber is at the zero power level, moving a wafer into the chamber. Then,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080146041 - Semiconductor device manufacturing method and plasma oxidation method: A semiconductor device manufacturing method includes forming a gate insulating film on a semiconductor substrate; forming, on the gate insulating film, a multilayered structure including at least a polysilicon layer and a metal layer containing a refractory metal; forming a gate electrode by etching the multilayered structure; and performing a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080146042 - Method of growing electrical conductors: A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a reducing agent, thereby... Agent: Knobbe Martens Olson & Bear LLP

20080146043 - Method for manufacturing an isolation structure using an energy beam treatment: The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation... Agent: Texas Instruments Incorporated

20080138915 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming through a first material film a second material film above a semiconductor substrate; patterning the second material film to have a predetermined pattern; trimming a width of the second material film thus patterned... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080138917 - Method and apparatus for processing a wafer: m

20080138916 - Pattern shape evaluation method, program, and semiconductor device manufacturing method: A pattern shape evaluation method comprising detecting an edge of an evaluation target pattern from an image of the evaluation target pattern to output the edge as a first edge, detecting an edge of a reference pattern from an image of the reference pattern to output the edge as a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080138918 - Light emitting device with blue light led and phosphor components: A light emitting device containing a semiconductor light emitting component and a phosphor, the phosphor is capable of absorbing a part of light emitted by the light emitting component and emitting light of a wavelength different from that of the absorbed light, is provided. A straight line connecting a point... Agent: Birch Stewart Kolasch & Birch

20080138919 - Luminescent ceramic for a light emitting device: A semiconductor light emitting device comprising a light emitting layer disposed between an n-type region and a p-type region is combined with a ceramic layer which is disposed in a path of light emitted by the light emitting layer. The ceramic layer is composed of or includes a wavelength converting... Agent: Patent Law Group LLP

20080138920 - Display employing organic material: A display is disclosed. The display includes a plurality of pixels configured to emit light. The display also includes a plurality of pixel control circuits that are each configured to regulate emission of light from a pixel. The pixel control circuits each include one or more two-terminal switching devices that... Agent: Beyer Weaver LLP

20080138921 - Liquid crystal display apparatus and manufacturing method thereof: A liquid crystal apparatus includes a TFT array substrate which includes gate wirings having a gate electrode, source wirings having a source electrode, a thin film transistor having the gate electrode, a semiconductor layer, the source electrode, and a drain electrode, an interlayer insulating film provided above the thin film... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080138924 - Method of fabricating electric field sensor having electric field shield: A method of manufacturing an electric field sensor having an electric field shield. The method includes providing a substrate doped with a first impurity; forming a resistive tip having a resistance region doped with a low concentration of a second impurity at an apex of a protruding portion of the... Agent: Sughrue Mion, Pllc

20080138923 - Method of forming suspended structure: A method of forming a suspended structure is disclosed. Initially, a substrate is provided. A patterned first sacrificial layer and a patterned second sacrificial layer are formed on a front surface of the substrate. The second sacrificial layer has an opening exposing a part of the substrate and a part... Agent: North America Intellectual Property Corporation

20080138922 - Micro-electro mechanical device made from mono-crystalline silicon and method of manufacture therefore: The present invention is related to a method for manufacturing micro-electro-mechanical systems (MEMS) having movable and stationary suspended structures formed from mono-crystalline silicon wafer or chip, bonded to a substrate wafer with an polymer adhesive layer that serves as spacer and as a sacrificial layer which is undercut by dry... Agent: Chang-feng Wan

20080138925 - Drop generator: A method for making an electromechanical device including forming an electromechanical transducer that includes a deposited metallic diaphragm, and attaching the electromechanical transducer to a fluid channel substructure.... Agent: Fay Sharpe / Xerox - Rochester

20080138926 - Two epitaxial layers to reduce crosstalk in an image sensor: An image sensor includes a substrate of a first conductivity type having an image area with a plurality of photosensitive sites, wherein a portion of the charge generated in response to light is collected in the pixel; and a subcollector of a second conductivity spanning the image area that collects... Agent: Frank Pincelli Patent Legal Staff

20080138927 - Systems and methods for fabricating crystalline thin structures using meniscal growth techniques: Systems and methods that utilize semiconductor molecules to form crystalline thin-films by depositing the molecules into a substrate at a lateral growth front. Techniques embodied in corresponding ones of the disclosed systems and methods include a submersion technique in which a substrate is submerged in a precursor solution containing the... Agent: Downs Rachlin Martin Pllc

20080138928 - Semiconducting element, organic light emitting display including the same, and method of manufacturing the semiconducting element: A semiconductor element (semiconductor device) including a substrate having a patterned structure of an organic semiconductor material and a method of manufacturing the semiconductor element are disclosed. According to one embodiment, the method of manufacturing the semiconductor element provides a substrate having a patterned structure of an organic semiconductor material... Agent: Knobbe Martens Olson & Bear LLP

20080138930 - Method for making a keyhole opening during the manufacture of a memory cell: A keyhole opening is formed during one example of manufacturing a memory cell. An upper layer is formed on a base layer, the base layer having a bottom electrode. The upper layer includes a second layer formed over the base layer and a first layer formed over the second layer.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080138929 - Method for making a self-converged memory material element for memory cell: A self-converged memory material element is created during the manufacture of a memory Cell comprising a base layer, with a bottom electrode, and an upper layer having a third, planarization stop layer over the base layer, a second layer over the third layer, and the first layer over the second... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080138931 - Method for making a self-converged void and bottom electrode for memoery cell: A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080138932 - Semiconductor device and method of manufacturing semiconductor device: The present invention provides a semiconductor device that is inexpensive and can suppress signal transmission delay, and a manufacturing method thereof. The semiconductor device includes: a plurality of semiconductor chips; a semiconductor substrate that has, on the same surface thereof, a chip-to-chip interconnection for electrically connecting the plurality of semiconductor... Agent: Sonnenschein Nath & Rosenthal LLP

20080138933 - Method of making semiconductor device: A method of fabricating a semiconductor device is provided. The semiconductor device has four levels of semiconductor chips stacked on a die pad of a lead frame. Specifically, the first, second, third and fourth semiconductor chips are stacked in turn. The first semiconductor chip shifts from the second semiconductor chip,... Agent: Rabin & Berdo, Pc

20080138934 - Method of manufacturing multi-stack package: A method of manufacturing a multi-stack package that ensures easy application of a solder paste or a flux. The method includes forming a first package comprising a first substrate on which bumps are arranged and a second package comprising a second substrate on which electrode pads corresponding to the bumps... Agent: Marger Johnson & Mccollom, P.c.

20080138935 - Chip scale package structure and method for fabricating the same: A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant... Agent: Edwards Angell Palmer & Dodge LLP

20080138936 - Method for laminating substrate and apparatus using the method: A supporting substrate is laminated on a wafer in such a manner that the supporting substrate locked in peripheral edges with a plurality of locking claws is disposed in proximity to and facing to an adhering surface of a double-sided adhesive sheet on the workpiece, the supporting substrate is pressed... Agent: Cheng Law Group, Pllc

20080138937 - Semiconductor device and fabrication method thereof: A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a... Agent: Rader Fishman & Grauer Pllc

20080138938 - Die positioning for packaged integrated circuits: A method that locates a plurality of die for forming a plurality of packaged integrated circuits. A frame is placed over the support structure, wherein the frame includes a plurality of openings therein and each opening of the plurality of openings has at least two walls. Each die of a... Agent: Freescale Semiconductor, Inc. Law Department

20080138939 - Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon: Methods for formation epitaxial layers containing silicon and carbon doped with phosphorus are disclosed. The pressure is maintained equal to or above 100 torr during deposition. The methods result in the formation of a film including substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in... Agent: Diehl Servilla Llc

20080138940 - Method of manufacturing thin film transistor and method of manufacturing liquid crystal display device using the same: A method of manufacturing a thin film transistor includes: forming a gate insulating layer on a substrate having a gate electrode; forming a semiconductor layer of nanomaterial on the gate insulating layer; forming a source electrode and a drain electrode on the gate insulating layer; and applying a voltage to... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20080138941 - Method for fabricating soi device: A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer. A well region is ion implanted in the monocrystalline silicon... Agent: Ingrassia Fisher & Lorenz, P.c. (amd)

20080138942 - Thin film transistor array panel and method for manufacturing the same: The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a... Agent: Cantor Colburn, LLP

20080138943 - Semiconductor device, method of manufacturing the same, and method of designing the same: An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method... Agent: Eric Robinson

20080138944 - Manufacturing method of semiconductor device: In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor... Agent: Nixon Peabody, LLP

20080138945 - Method for fabricating trench mosfet: A method for fabricating a semiconductor device, such as a trench MOSFET device, is provided. The method includes: forming a hard mask on an upper surface of a semiconductor substrate; forming an opening in the hard mask to expose a portion of the semiconductor substrate; forming a trench in the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080138946 - High frequency mos transistor, method of forming the same, and method of manufacturing a semiconductor device including the same: In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower... Agent: Mills & Onello LLP

20080138947 - Method and resulting structure for dram cell and peripheral transistor: A method for fabricating DRAM cells, e.g., dynamic random access memory cells. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of NMOS transistor gate structures. Each of the NMOS gate structures includes an NMOS source region and an NMOS drain region and... Agent: Townsend And Townsend And Crew, LLP

20080138948 - Methods of etching into silicon oxide-containing material, methods of forming container capacitors, and methods of forming dram arrays: Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide-containing material may be utilized for fabrication of container capacitors, and such... Agent: Wells St. John P.s.

20080138950 - Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process: A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080138949 - Semiconductor device with amorphous silicon monos memory cell structure and method for manufacturing thereof: A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the... Agent: Townsend And Townsend And Crew, LLP

20080138951 - Method for fabricating nonvolatile memory device: A method for fabricating a nonvolatile memory device includes forming a tunneling insulation layer, a first conductive layer for forming a floating gate, and a hard mask over a substrate. A portion of the hard mask, the first conductive layer, the tunneling insulation layer, and the substrate is etched to... Agent: Townsend And Townsend And Crew, LLP

20080138953 - Methods of making power semiconductor devices with thick bottom oxide layer: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the... Agent: Townsend And Townsend And Crew, LLP

20080138952 - Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same: The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate... Agent: Ladas & Parry LLP

20080138954 - High voltage ldmos: A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor substrate between the drain region and the source region. A gate... Agent: Hiscock & Barclay, LLP

20080138955 - Formation of epitaxial layer containing silicon: Methods for formation of epitaxial layers containing silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the epitaxial layer involves exposing a substrate in a process... Agent: Diehl Servilla Llc

20080138956 - Manufacturing method of semiconductor device: A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second... Agent: Jianq Chyun Intellectual Property Office

20080138957 - Triple alignment substrate method and structure for packaging devices: A method for aligning multiple substrates. The method includes providing a handle substrate, providing a spacer substrate, and forming a plurality of first alignment marks on a first surface of the handle substrate. The method also includes forming a plurality of self-limiting alignment marks on a first surface of the... Agent: Townsend And Townsend And Crew, LLP

20080138958 - Method for manufacturing device isolation film of semiconductor device: A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap... Agent: Townsend And Townsend And Crew, LLP

20080138959 - Method for producing semiconductor wafer: The present invention is a method for producing a semiconductor wafer, comprising: at least epitaxially growing a Si1-XGeX layer (0<X≦1) on a surface of a silicon single crystal wafer to be a bond wafer; implanting at least one kind of a hydrogen ion or a rare gas ion through the... Agent: Oliff & Berridge, Plc

20080138960 - Method of manufacturing a stack-type semiconductor device: A method of manufacturing a stack-type semiconductor device, in which a first substrate and a second substrate are prepared so that the first substrate has a surface layer and the second substrate has an insulation layer. The first substrate and the second substrate are attached to each other to allow... Agent: F. Chau & Associates, Llc

20080138961 - Wafer bonding method of system in package: A method of bonding a wafer in a system in package is provided. A plating layer is formed on each of a first semiconductor substrate and a second semiconductor substrate. The plating layers are then bonded to each other to connect the semiconductor substrates.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080138962 - Manufacturing method of semiconductor device: Illumination devices (7a) and (7b) which irradiate light having a wavelength of 1.1 μm or less are arranged on a front surface and a rear surface of a cover (8) of a dicing device (1). After a wafer is placed on a dicing stage (3), when the wafer is diced... Agent: Miles & Stockbridge Pc

20080138963 - Method of manufacturing a semiconductor device: After crystallization of a semiconductor film is performed by irradiating first laser light (energy density of 400 to 500 mJ/cm2) in an atmosphere containing oxygen, an oxide film formed by irradiating the first laser light is removed. It is next performed to irradiate second laser light under an atmosphere that... Agent: Eric Robinson

20080138964 - Formation of epitaxial layer containing silicon and carbon: Methods for formation of epitaxial layers containing silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the epitaxial layer involves exposing a substrate in a process... Agent: Diehl Servilla Llc

20080138965 - Amorphous si/au eutectic wafer bonding structure: An amorphous Si (silicon)/Au (gold) eutectic wafer bonding structure is fabricated. An amorphous Si obtained through coating or growth contacts with Au for bonding. The bonding layer is a Si/Au eutectic layer. Si is prevented from being precipitated. The bonding structure has a fast reaction ratio and a uniformed reaction.... Agent: Troxell Law Office Pllc

20080138966 - Method of fabricating a densified nanoparticle thin film with a set of occluded pores: A method of fabricating a densified nanoparticle thin film with a set of occluded pores in a chamber is disclosed. The method includes positioning a substrate in the chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method... Agent: Foley & Lardner LLP

20080138967 - Plasma immersed ion implantation process: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, the method for implanting ions into a substrate by a plasma immersion ion implantation process includes providing a substrate into a processing chamber, supplying a gas mixture including a reacting gas... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080138968 - Plasma immersed ion implantation process using balanced etch-deposition process: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting ions into a substrate includes providing a substrate into a processing chamber, generating a plasma from a gas mixture including a reacting gas and a etching gas... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080138969 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080138970 - Gate structure and method for fabricating the same, and method for fabricating memory and cmos transistor layout: A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive... Agent: Jianq Chyun Intellectual Property Office

20080138971 - Manufacturing method of semiconductor device: The present invention provides a manufacturing method of a semiconductor device having a semiconductor nonvolatile memory element that is highly reliable and that can increase a variation of a threshold voltage. Further, the present invention provides a method for manufacturing a semiconductor device having a highly reliable semiconductor nonvolatile memory... Agent: Nixon Peabody, LLP

20080138972 - Method of removing photoresist and method of manufacturing a semiconductor device: A method of removing a photoresist may include permeating supercritical carbon dioxide into the photoresist on a substrate having a conductive structure including a metal. The photoresist permeating the supercritical carbon dioxide may be easily removable. The photoresist permeating the supercritical carbon dioxide may be removed using a photoresist cleaning... Agent: Harness, Dickey & Pierce, P.L.C

20080138973 - Microelectronic devices and methods for forming interconnects in microelectronic devices: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled... Agent: Perkins Coie LLP Patent-sea

20080138974 - Method of sputtering a nickel silicon alloy, especially useful for forming a solder bump barrier: A nickel silicon alloy barrier layer formed between a metal bonding pad on an integrated circuit and a tin-based solder ball, for example, a lead-free solder. The nickel silicon alloy contains at least 2 wt % silicon and preferably less than 20 wt %. An adhesion layer may be formed... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20080138975 - Method and system for fabricating semiconductor components with through interconnects and back side redistribution conductors: A method for fabricating semiconductor components includes the step of providing a semiconductor substrate having a circuit side, a back side, a plurality of integrated circuits on the circuit side, and a plurality of substrate contacts on the circuit side in electrical communication with the integrated circuits. The method also... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20080138976 - Semiconductor chip and production process therefor: A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface interconnection may be connected to... Agent: Rabin & Berdo, Pc

20080138977 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a plurality of wirings disposed in parallel to each other and an insulating layer covering the wirings so that a void is defined between the wirings. Each wiring includes a metal wiring layer having a first side and a second side opposed to the first side,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080138978 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Megica Corporation

20080138979 - Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma... Agent: Miles & Stockbridge Pc

20080138980 - Method for manufacturing a metal pattern of a semiconductor device: A method for manufacturing a metal pattern of a semiconductor device capable of preventing generation of a ring defect in a metal pattern by performing a stuffing process for making increasing the density of an anti-reflection-coating using O2 gas or N2 gas.... Agent: Sherr & Nourse, Pllc

20080138982 - Semiconductor device: A through-electrode that penetrates a semiconductor substrate and that is insulatively separated from the semiconductor substrate includes an inner through-electrode, a quadrangular ring-shaped semiconductor, and an outer peripheral through-electrode. The quadrangular ring-shaped semiconductor is formed around the inner through-electrode, and the outer peripheral through-electrode is formed around the quadrangular ring-shaped... Agent: Young & Thompson

20080138981 - System and method for manufacturing contact: System and method for manufacturing contact. According to an embodiment, the present invention provides a method for manufacturing integrated circuits. The method includes a step for providing a semiconductor substrate. The method also includes a step for defining a plurality of contact regions on the semiconductor substrate. The method further... Agent: Townsend And Townsend And Crew, LLP

20080138983 - Method of forming tensile stress films for nfet performance enhancement: A method of forming tensile stress films for NFET Performance enhancement, comprising the steps of: (a) providing a semiconductor substrate having a gate structure patterned thereon; (b) performing a deposition process to form a first dielectric film overlying the semiconductor substrate and covering the gate structure; (c) performing a curing... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080138984 - Organometallic precursor compounds: This invention relates to organometallic precursor compounds represented by the formula i-PrN═Ta(NR1R2)3 wherein R1 and R2 are the same or different and are alkyl having from 1 to 3 carbon atoms, provided that (i) when R1 is ethyl, then R2 is other than ethyl and (ii) when R2 is ethyl,... Agent: Praxair, Inc. Law Department - M1 557

20080138985 - Method for improved formation of nickel silicide contacts in semiconductor devices: A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over... Agent: Cantor Colburn LLP - Ibm Fishkill

20080138987 - Edge removal of silicon-on-insulator transfer wafer: A silicon-on-insulator transfer wafer having a front surface with a circumferential lip around a circular recess is polished. In one version, the circular recess on the front surface of the wafer is masked by filling the recess with spin-on-glass. The front surface of the wafer is exposed to an etchant... Agent: Townsend And Townsend And Crew LLP / Amat

20080138986 - Mask layer trim method using charged particle beam exposure: A method for forming a patterned target layer over a substrate uses a blanket target layer located over the substrate and a patterned mask layer located over the blanket target layer At least one mask layer pattern wit the patterned mask layer is treated with a charged particle beam to... Agent: Scully, Scott, Murphy & Presser, P.c.

20080138988 - Detection of clearance of polysilicon residue: During polishing of a substrate, polysilicon can be removed from a surface of the substrate. Detecting an endpoint during polishing of polysilicon can include polishing the substrate having a polysilicon residue on an area of oxide area and optically detecting clearance of the polysilicon residue.... Agent: Fish & Richardson P.c.

20080138989 - Method to recover patterned semiconductor wafers for rework: Disclosed are embodiments of a method of removing patterned circuit structures from the surface of a semiconductor wafer. The method embodiments comprise blasting the surface of the semiconductor wafer with particles so as to remove substantially all of the patterned circuit structures. The blasting process is followed by one or... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080138990 - Polishing composition and polishing method: The present invention provide a chemical-mechanical polishing composition for inhibiting dishing and erosion as well as rapidly polishing an insulating film and barrier film at the same time while maintaining the flatness of the substrate surface polished. The present chemical-mechanical polishing composition comprises methanesulfonic acid, an alkali metal ion, an... Agent: Sughrue Mion, Pllc

20080138991 - Method of manufacturing a transistor: A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure... Agent: Marger Johnson & Mccollom, P.c.

20080138992 - Wide area radio frequency plasma apparatus for processing multiple substrates: An antenna array for a radio frequency plasma process chamber including, an array of electrodes, an array of dielectric tubes concentrically disposed about each electrode tube to define a chamber configured to be at atmospheric pressure between an outer surface of each electrode tube and an inner surface of the... Agent: Cantor Colburn, LLP

20080138995 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080138993 - Plasma processing apparatus: A dry etching apparatus comprises: a vacuum chamber where a processing target is disposed on a bottom wall side of an internal space; a coil for generating plasma that is disposed above and outside the vacuum chamber and has conductors disposed so that a gap is formed in a plane... Agent: Wenderoth, Lind & Ponack L.l.p.

20080138994 - Substrate processing method and substrate processing apparatus: The present invention includes a step of generating mixed plasma by causing a mixed gas of hydrogen (H2) gas and oxygen (O2) or oxygen-containing gas supplied to a starting substrate to form a plasma discharge, and processing the starting substrate by the mixed plasma; and a step of generating hydrogen... Agent: Oliff & Berridge, Plc

20080138996 - Etching method and etching apparatus: The present invention is an etching method for performing an etching process in the presence of a plasma on an object to be processed in which a layer to be etched made of a tungsten-containing material is formed on a base layer made of a silicon-containing material in a process... Agent: Smith, Gambrell & Russell

20080138997 - Two step etching of a bottom anti-reflective coating layer in dual damascene application: Methods for removing a BARC layer from a feature are provided in the present invention. In one embodiment, the method includes providing a substrate having a feature filled with a BARC layer in an etching chamber, supplying a first gas mixture comprising NH3 gas into the chamber to etch a... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080138998 - Methods for manufacturing memory and logic devices using the same process without the need for additional masks: A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on... Agent: Baker & Mckenzie LLP Patent Department

20080138999 - Solar cell fabrication using extrusion mask: Large-area ICs (e.g., silicon wafer-based solar cells) are produced by positioning a mask between an extrusion head and the IC wafer during extrusion of a dopant bearing material or metal gridline material. The mask includes first and second peripheral portions that are positioned over corresponding peripheral areas of the wafer,... Agent: Bever, Hoffman & Harms, LLP

20080139000 - Radical processing of a sub-nanometer insulation film: A method of nitriding an insulation film, includes the steps of forming nitrogen radicals by high-frequency plasma, and causing nitridation in a surface of an insulation film containing therein oxygen, by supplying the nitrogen radicals to the surface of the insulation film.... Agent: Crowell & Moring LLP Intellectual Property Group

20080139001 - Method for processing polysilazane film: A method for processing a polysilazane film includes performing temperature increase of changing a process field of a reaction container, which accommodates a target substrate with a polysilazane coating film formed thereon, from a pre-heating temperature to a predetermined temperature, while setting the process field to be a first atmosphere... Agent: Smith, Gambrell & Russell

20080139002 - Liquid chemical supply apparatus for supplying liquid chemical onto substrate, and semiconductor device fabrication method using liquid chemical supply apparatus: A liquid chemical supply apparatus includes a storage unit, addition unit, and nozzle unit. The storage unit stores a liquid chemical. The addition unit adds, to the liquid chemical supplied from the storage unit, a modifier in an amount corresponding to the degree of deterioration of the liquid chemical. The... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080139003 - Barrier coating deposition for thin film devices using plasma enhanced chemical vapor deposition process: A method to produce barrier coatings (such as nitrides, oxides, carbides) for large area thin film devices such as solar panels or the like using a high frequency plasma enhanced chemical vapor deposition (PECVD) process is presented. The proposed process provides a uniform deposition of barrier coating(s) such as silicon... Agent: Weiss & Moy Pc

20080139004 - Light emission from silicon-based nanocrystals by sequential thermal annealing approaches: A method for enhancing photoluminescence includes providing a film disposed over a substrate, the film including at least one of a semiconductor and a dielectric material. A first annealing step is performed at a first temperature in a processing chamber or annealing furnace; and, thereafter, a second annealing step is... Agent: Goodwin Procter LLP Patent Administrator

20080131979 - Vapor-phase growth system and vapor-phase growth method: Affords a vapor-phase growth system and vapor-phase growth method that enable gas leakage reduction. A vapor-phase growth system (1) is provided with a flow channel (4), a flow channel (5) linked to the downstream end of the flow channel (4), and susceptor (17) for supporting a substrate 21 so that... Agent: Judge Patent Associates

20080131981 - Method for forming au-bump with clean surface: A method for fabricating and testing a semiconductor wafer includes sputtering a TiW layer on a passivation layer and on pads, next sputtering a seed layer, made of gold, on the TiW layer, next forming a photoresist layer on the seed layer, next electroplating gold bumps on the seed layer... Agent: North America Intellectual Property Corporation

20080131980 - Method of adjusting buried resistor resistance: Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based... Agent: Hoffman, Warnick & D'alessandro Llc

20080131982 - Method of trimming semiconductor elements with electrical resistance feedback: A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion... Agent: Dla Piper Us LLP

20080131983 - Method for forming post passivation au layer with clean surface: A method for fabricating and testing a wafer includes forming metal traces with metal pads, wherein forming the metal traces include forming a TiW layer on a passivation layer and on pads, next forming a seed layer on the TiW layer, next forming a photoresist layer on the seed layer,... Agent: North America Intellectual Property Corporation

20080131984 - Photon-based memory device: An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material formed therein for storing data as light received from and emitted to the pixel.... Agent: Dickstein Shapiro LLP

20080131985 - Method of manufacturing a thin film transistor array panel: A method for manufacturing a flexible display, includes forming a gate line including a plurality of gate electrodes with a first interval on a substrate having a coefficient of thermal expansion, sequentially depositing both a gate insulating layer covering the gate line and a semiconductor layer, etching the semiconductor layer... Agent: Cantor Colburn, LLP

20080131986 - Organic thin film transistor array and manufacturing method thereof: An organic thin film transistor array panel is provided, which includes: a substrate; a data line formed on the substrate and including a source electrode; a drain electrode formed on the substrate and separated from the data line; an organic semiconductor disposed on the source electrode and the drain electrode;... Agent: Patent Law Group LLP

20080131987 - Method for fabricating light-emitting device: A method for fabricating a light-emitting device includes: forming a first semiconductor layer on a substrate; foaming an active layer on the first semiconductor layer; forming a second semiconductor layer on the active layer, the second semiconductor layer having a conduction type opposite to that of the first semiconductor layer;... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080131988 - Nitride semiconductor light emitting device and method of manufacturing the same: A nitride semiconductor light emitting device and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device comprises an n-type nitride semiconductor layer formed on a substrate, an active layer formed on the n-type nitride semiconductor layer, a p-type nitride semiconductor layer formed on the active... Agent: Lowe Hauptman Ham & Berner, LLP

20080131989 - Method of producing acceleration sensor chip package: An acceleration sensor chip package includes an acceleration sensor chip; a sensor control chip; a re-wiring layer; an outer terminal; a sealing portion; and a substrate. The acceleration sensor chip includes a frame portion; a movable structure; a detection element; and an electrode pad electrically. The re-wiring layer has a... Agent: Takeuchi & Kubotera, LLP

20080131990 - Image sensor and method of manufacturing the same: An image sensor for minimizing a dark level defect is disclosed. The image sensor includes an isolation layer formed on a substrate. A field region and an active region are defined on the substrate by the isolation layer. A photodiode is formed in the image sensor in such a structure... Agent: F. Chau & Associates, Llc

20080131992 - Image sensor having integrated infrared-filtering optical device and related method: An image sensing device is disclosed having a die formed with an array of photosensing sites and a structure of optical material having infrared absorbing characteristics formed over the photosensing sites. An embodiment is disclosed in which the structure of optical material having infrared absorbing characteristics is formed as an... Agent: Ratnerprestia

20080131991 - Method of manufacturing cmos image sensor: A method of manufacturing a CMOS image sensor including a surface protection layer of an oxide-nitride-oxide (ONO) structure in order to minimize warping of the wafer by relieving thermal stresses of a silicon nitride layer, and to prevent blistering and popping by minimizing such thermal stresses.... Agent: Sherr & Nourse, Pllc

20080131993 - Low resistance thin film organic solar cell electrodes: A method which lower the series resistance of photosensitive devices includes providing a transparent film of a first electrically conductive material arranged on a transparent substrate; depositing and patterning a mask over the first electrically conductive material, such that openings in the mask have sloping sides which narrow approaching the... Agent: Kenyon & Kenyon LLP

20080131994 - Method for manufacturing phase change memory device which can stably form an interface between a lower electrode and a phase change layer: A phase change memory device is manufactured by forming a sacrificial layer and a hard mask layer on a lower electrode; performing a first etching these layers and forming on the lower electrode a first stack pattern having a first width less than a width of the lower electrode; performing... Agent: Ladas & Parry LLP

20080131995 - Memory device and mehtod of manufacturing the device by simulataneously conditioning transition metal oxide layers in a plurality of memory cells: Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers.... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080131996 - Reverse build-up process for fine bump pitch approach: A reverse build-up method for forming a package substrate includes forming bumps; forming an interconnect structure connected to the bumps; and forming ball grid array (BGA) balls on the interconnect structure. The BGA balls are electrically connected to the bumps through the interconnect structure. The step of forming the bumps... Agent: Slater & Matsil, L.l.p.

20080131997 - Integrated circuit package with chip-side signal connections: Embodiments of the present invention include an apparatus, method, and/or system for an integrated circuit package with signal connections on the chip-side of the package structure.... Agent: Schwabe, Williamson & Wyatt, P.c.

20080131999 - Method of die stacking using insulated wire bonds: A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate adhesive layer. After the intermediate layer is applied, the second semiconductor die may be stacked on top... Agent: Vierra Magen/sandisk Corporation

20080131998 - Method of fabricating a film-on-wire bond semiconductor device: A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate adhesive layer in which the wire bond loops from the first semiconductor die are embedded. After the... Agent: Vierra Magen/sandisk Corporation

20080132000 - Chip scale package and method for marking chip scale packages: A method for marking chip scale packages at the wafer level is provided. First, a positioning step is performed to determine the position of a plurality of semi-finished chip scale packages formed on a wafer. Each of the semi-finished chip scale package includes a plurality of terminals for making external... Agent: Lowe Hauptman Ham & Berner, LLP

20080132001 - Electronic part and method for manufacturing the same: A method for manufacturing an electronic part, including: cutting a wiring substrate, which contains a base substrate, a wiring pattern provided on a first surface of the base substrate, and a reinforcing member provided on a second surface of the base substrate, along a line intersecting with an outer circumference... Agent: Harness, Dickey & Pierce, P.L.C

20080132002 - Semiconductor package and production method thereof, and semiconductor device: A method of producing semiconductor packages includes the step of punching out a dam-bar and part of the region lateral to a lead of a scaling body formed by molding, the punching-out being effected by using a support block and a punch. The support block has an outer lateral surface... Agent: Mcdermott Will & Emery LLP

20080132003 - Semiconductor chip package and method for fabricating the same: Disclosed are a semiconductor chip package and a method for fabricating the same. The semiconductor chip package includes a semiconductor chip and a circuit board. The semiconductor chip is bonded to the circuit board by means of adhesive except for a metal-exposed region of the semiconductor chip. Anti-migration material is... Agent: Ladas & Parry LLP

20080132004 - Method and apparatus for applying external coating to grid array packages for increased reliability and performance: A method and apparatus are disclosed for selective removal of a conformal coating from the solder balls of grid array packages such that the benefits of the coating are realized. An ancillary benefit of the invention is improved process-ability of the grid array package by improving the mechanical containment of... Agent: Honeywell International Inc.

20080132005 - Electroplating method for a semiconductor device: An electroplating method calls for immersing a body to be plated in a plating solution containing tin and bismuth to form a tin-bismuth alloy skin layer on surfaces of the body. The plating is carried out such that a solid tin metal and a solid bismuth metal placed in the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080132006 - Packaged microelectronic devices and methods for packaging microelectronic devices: Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate,... Agent: Perkins Coie LLP Patent-sea

20080132007 - Hybrid integrated circuits and their methods of fabrication: The present invention provides architectures for hybrid integrated circuits and methods for producing these hybrid integrated circuits that contain both field programmable gate arrays and mask programmable gate arrays, a form of application specific integrated circuits. Methods for producing an integrated circuit that is field programmable as well as mask... Agent: Emil Chang Law Offices Of Emil Chang

20080132008 - method for fabricating landing polysilicon contact structures for semiconductor devices: A method for forming an integrated circuit device, e.g., memory, logic. The method includes providing a semiconductor substrate (e.g., silicon wafer) comprising a surface region and forming a polysilicon layer overlying the surface region. Preferably, the polysilicon layer is doped with an impurity to provide conductive characteristics. The method forms... Agent: Townsend And Townsend And Crew, LLP

20080132009 - Substrate, device, method of manufacturing device, method of manufacturing active matrix substrate, electro-optical apparatus and electronic apparatus: A substrate on which a pattern is formed by a discharged functional liquid, includes a coating region coated with the functional liquid, and banks formed to enclose the coating region, wherein a difference between a contact angle of the functional liquid with respect to the coating region and a contact... Agent: Oliff & Berridge, Plc

20080132010 - Thin film transistor substrate and manufacturing method for the same: A thin film transistor substrate is provided whose structure allows for the formation of (i) a thick gate insulating film, (ii) a high pressure resistance TFT having a LDD region of a GOLD structure, and (iii) a low voltage TFT having a thin gate insulating film, with less number of... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20080132011 - Semiconductor device and method of manufacturing same: A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on... Agent: Volentine & Whitt Pllc

20080132012 - Advanced cmos using super steep retrograde wells: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of... Agent: Texas Instruments Incorporated

20080132013 - Methods of forming semiconductor constructions: The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH2F2. The silicon-containing layer can contain an n-type doped region and a p-type doped region.... Agent: Wells St. John P.s.

20080132014 - Eeprom cell and eeprom device with high integration and low source resistance and method of manufacturing the same: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is... Agent: Mills & Onello LLP

20080132017 - Manufacturing method of non-volatile memory: A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates... Agent: Jianq Chyun Intellectual Property Office

20080132016 - Method of manufacturing a flash memory device: In a method of fabricating a flash memory device, a semiconductor substrate includes a tunnel insulating layer and a charge storage layer formed in an active region and a trench formed in an isolation region. A first insulating layer is formed to fill a part of the trench. A second... Agent: Townsend And Townsend And Crew, LLP

20080132015 - Sidewall memory with self-aligned asymmetrical source and drain configuration: A method of forming a semiconductor structure includes providing a semiconductor substrate and forming a memory cell at a surface of the semiconductor substrate. The step of forming the memory cell includes forming a gate dielectric on the semiconductor substrate and a control gate on the gate dielectric; forming a... Agent: Slater & Matsil, L.l.p.

20080132018 - Formation and treatment of epitaxial layer containing silicon and carbon: Methods and apparatus for formation and treatment of epitaxial layers containing silicon and carbon are disclosed. Treatment of the epitaxial layer converts interstitial carbon to substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET)... Agent: Diehl Servilla Llc

20080132019 - Short channel effect engineering in mos device using epitaxially carbon-doped silicon: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.... Agent: Slater & Matsil, L.l.p.

20080132021 - High performance fet devices and methods thereof: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to... Agent: George Sai-halasz

20080132020 - Method of forming silicon nano crystals and method of manufacturing memory devices having the same: Provided are methods of forming nano crystals and method of manufacturing a memory device suing the same. In an example embodiment, a method of forming nano crystals may include forming an amorphous film on a substrate and converting the amorphous film into an oxide film having the nano crystals by... Agent: Harness, Dickey & Pierce, P.L.C

20080132022 - Method of fabricating semiconductor device: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080132023 - Semiconductor process: A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate.... Agent: Jianq Chyun Intellectual Property Office

20080132024 - Method of manufacturing double diffused drains in semiconductor devices: A method of manufacturing double diffused drains in a semiconductor device. An embodiment comprises forming a gate dielectric layer on a substrate, and masking and patterning the gate dielectric layer. Once the gate dielectric layer has been patterned, a second dielectric layer, having a different depth than the gate dielectric... Agent: Slater & Matsil, L.l.p.

20080132025 - Ultra-thin soi vertical bipolar transistors with an inversion collector on thin-buried oxide (box) for low substrate-bias operation and methods thereof: The present invention provides a “collector-less” silcon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such... Agent: Scully, Scott, Murphy & Presser, P.c.

20080132026 - Optimum padset for wire bonding rf technologies with high-q inductors: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of... Agent: Scully, Scott, Murphy & Presser, P.c.

20080132027 - Planar vertical resistor and bond pad resistor and related method: Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending... Agent: Hoffman, Warnick & D'alessandro Llc

20080132028 - Method and structure for isolating substrate noise: An integrated circuit structure for isolating substrate noise and a method of forming the same are provided. In the preferred embodiment of the present invention, a semi-insulating region is formed using proton bombardment in a substrate between a first circuit region and a second circuit region. Two guard rings are... Agent: Steven H. Slater Slater & Matsil, L.l.p.

20080132029 - Trench widening without merging: A semiconductor fabrication method. First, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench includes a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the... Agent: Schmeiser, Olsen & Watts

20080132030 - Method of manufacturing semiconductor device: After sequentially forming an insulating layer and a capping dielectric layer having a higher density than the insulating layer, a chemical mechanical polishing (CMP) process is performed to prevent scratch from being formed on the surface of the insulating layer at the early stage of the CMP process. Thus, a... Agent: Marger Johnson & Mccollom, P.c.

20080132032 - Method for manufacturing silicon wafer: A method for manufacturing a silicon wafer is characterized by performing one or both of grinding and polishing to a thin discoid silicon wafer to give bowl-shaped warpage that is concave at a central part to a wafer surface. One main surface of the thin discoid silicon wafer is adsorbed... Agent: Brinks Hofer Gilson & Lione

20080132031 - Method of manufacturing a semiconductor heterostructure: A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which... Agent: Winston & Strawn LLP Patent Department

20080132033 - Method for manufacturing semiconductor device: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is... Agent: Eric Robinson

20080132034 - Laser dicing sheet and manufacturing method for chip body: Disclosed herein is a laser dicing sheet comprising a base material comprising a polyurethane acrylate film and a shape-restoring film; and an adhesive layer formed on a surface of said polyurethane acrylate film of the base material.... Agent: Hahn & Voight Pllc

20080132035 - Method of processing wafer: An undefill material is provided on the surface of a wafer in such a manner as to cover bumps, then the wafer is irradiated with a laser beam from the surface thereof and along planned cutting lines so as to remove an insulation layer and the underfill material present over... Agent: Greer, Burns & Crain

20080132037 - Device manufacturing method and dicing method: Prior to dicing, a volatile protective agent is applied to at least the face of the substrate in which the devices are fabricated. Then the devices are separated by dicing. After dicing, the surface of the volatile protective agent is cleaned, and then the volatile protective agent is evaporated.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080132036 - Method for subdividing wafer into leds: A method for forming chips on a wafer includes forming one or more spaces in a substrate to form and to space two or more chips from each other, forming a positive electrode and a negative electrode in each of the chips, cutting one or more cut-off portions through the... Agent: Charles E. Baxley, Esq.

20080132038 - Semiconductor device and manufacturing method of the same: The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to a pad... Agent: Morrison & Foerster LLP

20080132040 - Deposition technique for producing high quality compound semiconductor materials: Deposited layers are advantageously obtained by utilizing a specific hydride vapour phase epitaxy deposition procedure. In this procedure, a vertical growth cell structure with extended diffusion layer, a homogenising diaphragm, sidewall purging gases, anal independent gas and substrate heaters is used for the deposition of III-V and VI compound semiconductors.... Agent: Christie, Parker & Hale, LLP

20080132039 - Formation and treatment of epitaxial layer containing silicon and carbon: Methods for formation and treatment of epitaxial layers containing silicon and carbon are disclosed. Treatment converts interstitial carbon to substitutional carbon in the epitaxial layer, according to one or more embodiments. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor... Agent: Diehl Servilla Llc

20080132041 - Laser irradiation apparatus, laser irradiation method, and method for manufacturing a semiconductor device: A second laser light of a continuous wave oscillation is irradiated to a region melted by a first laser light of a pulsed oscillation having a harmonic. Specifically, the first laser light has a wavelength not longer than that of visible light (830 nm, preferably not more than 780 nm).... Agent: Eric Robinson

20080132042 - Process for cleaning chamber in chemical vapor deposition apparatus: A process for cleaning a chamber in a Chemical Vapor Deposition apparatus includes removing a polysilicon layer formed on the interior of the chamber after a doped polysilicon layer has been deposited on a wafer through Chemical Vapor Deposition, and depositing a doped polysilicon layer on the interior of the... Agent: Squire, Sanders & Dempsey L.l.p.

20080132043 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes the steps of forming an oxide film on a surface layer section of an entire surface of a semiconductor substrate, forming a window section by selectively removing the oxide film from an active surface side of the semiconductor substrate, the window section... Agent: Oliff & Berridge, Plc

20080132044 - Nitride semiconductor device manufacturing method: Affords a manufacturing method enabling nitride-based semiconductor devices containing epitaxial films excelling in flatness and crystallinity to be easily produced. Method of manufacturing nitride semiconductor devices that are formed onto a semiconductor substrate being a compound containing nitrogen, and a Group IIIA element for forming compounds with nitrogen, including steps... Agent: Judge Patent Associates

20080132045 - Laser-based photo-enhanced treatment of dielectric, semiconductor and conductive films: A metallic, semiconductor, dielectric or oxide layer, such as a thin gate oxide, is formed by supplying a wafer in a processing chamber with thermal energy to heat the wafer and light energy, such as laser light at a selected wavelength, to improve the quality of the resulting layer. The... Agent: Macpherson Kwok Chen & Heid LLP

20080132046 - Plasma doping with electronically controllable implant angle: A plasma doping apparatus includes a chamber and a plasma source that generates ions from a dopant gas. A platen is positioned in the chamber adjacent to the plasma source that supports a wafer for plasma doping. A deflection grid comprising a first and second deflection electrode is positioned in... Agent: Rauschenbach Patent Law Group, Llc

20080132047 - Method for doping impurities: A method for doping impurities into a device layer is provided. The method includes providing a carbonized dopant layer over a device layer, wherein the carbonized dopant layer comprises one or more dopant impurities, and heat treating the carbonized dopant layer to thermally diffuse the dopant impurities into the device... Agent: General Electric Company Global Research

20080132048 - Semiconductor component and method for producing the same: A method for producing a semiconductor component has the following step: the front side (101) of the semiconductor body (100) is irradiated with high-energy particles using the terminal electrode (40) as a mask, in order to produce recombination centres (80A, 80B) in the semiconductor body (100) for the recombination of... Agent: Coats & Bennett/infineon Technologies

20080132049 - Method for fabricating schottky barrier tunnel transistor: Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a... Agent: Rabin & Berdo, Pc

20080132050 - Deposition process for graded cobalt barrier layers: A method for forming a graded cobalt-containing barrier layer comprises forming a cobalt nitride layer on a semiconductor substrate in a reactor, wherein the semiconductor substrate includes a trench etched into a dielectric layer, forming a cobalt metal layer atop the cobalt nitride layer, and then annealing the cobalt nitride... Agent: Intel Corporation C/o Intellevate, Llc

20080132051 - Method for fabricating semiconductor device with bulb-shaped recess gate: A method for fabricating a semiconductor device includes forming a plurality of bulb-shaped recesses in a substrate, forming a gate insulation layer over the substrate including the bulb-shaped recesses, forming a patterned first conductive layer over sidewalls of a bulb pattern of the corresponding bulb-shaped recesses, and forming a patterned... Agent: Blakely Sokoloff Taylor & Zafman

20080132052 - Method of fabricating electronic device using nanowires: A method of fabricating an electronic device using nanowires, minimizing the number of E-beam processing steps and thus improving a yield, includes the steps of: forming electrodes on a substrate; depositing a plurality of nanowires on the substrate including the electrodes; capturing an image of the substrate including the nanowires... Agent: Rabin & Berdo, Pc

20080132053 - Method for preparing an intergrated circuits device having a reinforcement structure: An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad... Agent: Wpat, Pc Intellectual Property Attorneys

20080132054 - Method for producing metal/semiconductor contacts through a dielectric: A method of forming contacts between at least one metallic layer and at least one semiconductor substrate through at least one layer of dielectric in a semiconductor device. The semiconductor device includes, on at least one base face of the semiconductor substrate, the dielectric layer. The metallic layer is stacked... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080132055 - Hardmask for improved reliability of silicon based dielectrics: The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising... Agent: Scully, Scott, Murphy & Presser, P.c.

20080132056 - Integration of thin film resistors having different tcrs into single die: An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer (2) formed on a semiconductor substrate (1), a first thin film resistor (3) disposed on the first oxide layer (2), and a second oxide layer (14) disposed over the first... Agent: Texas Instruments Incorporated

20080132057 - Method of selectively forming a conductive barrier layer by ald: By providing a surface modification process prior to or during a self-limiting deposition process, the per se highly conformal deposition behavior may be selectively changed so as to obtain reliable coverage at specific surface areas, while significantly reducing or suppressing a deposition above unwanted surface areas, such as the bottom... Agent: Williams, Morgan & Amerson

20080132058 - Electrical programmable metal resistor: The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is provided that includes an interconnect structure comprising at least... Agent: Scully Scott Murphy & Presser, Pc

20080132059 - Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device: Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080132060 - Contact barrier layer deposition process: A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma physical vapor deposition process, wherein the layer of Ti has a thickness of between about 10 angstroms (Å) and about 1000 Å. A... Agent: Baker & Mckenzie LLP Patent Department

20080132061 - Contact barrier layer deposition process: A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma (IMP) physical vapor deposition process. The IMP process includes: generating gaseous ions, accelerating the gaseous ions towards a titanium target, sputtering the titanium... Agent: Baker & Mckenzie LLP Patent Department

20080132062 - Method of manufacturing semiconductor device: To obtain a copper film having satisfactory electrical characteristics with a simple structure, there is provided a method of manufacturing a semiconductor device including the step of forming on a semiconductor substrate a barrier metal film to be a seed film which functions as a cathode when a copper film... Agent: Young & Thompson

20080132063 - Fabrication method of semiconductor device: A method of fabricating a semiconductor device is provided. The method includes forming a refractory metal alloy layer over a silicon-containing conductive layer. The refractory metal alloy layer is constituted of a first refractory metal and a second refractory metal. Thereafter, a cap layer is formed on the refractory metal... Agent: Jianq Chyun Intellectual Property Office

20080132064 - Method for forming a self-aligned nitrogen-containing copper silicide capping layer in a microstructure device: By forming a copper/silicon/nitrogen alloy in a surface portion of a copper-containing region on the basis of a precursor layer, highly controllable and reliable process conditions may be established. The precursor layer may be formed on the basis of a liquid precursor solution, which may exhibit a substantially self-aligned and... Agent: J. Mark Amerson Williams, Morgan, Amerson, P.c.

20080132065 - Method for redirecting void diffusion away from vias in an integrated circuit design: A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of... Agent: Lsi Logic Corporation Corporate Legal Department

20080132066 - Integrated circuit having a top side wafer contact and a method of manufacture therefor: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the... Agent: Texas Instruments Incorporated

20080132068 - Damascene metal-insulator-metal (mim) device: The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the... Agent: Paul J. Winters

20080132067 - Method for fabricating a dual damascene structure: A method for fabricating a dual damascene structure contains providing a substrate having a conductive layer, an etching stop layer, a dielectric layer, and a photoresist layer thereon, performing an etching process to remove a portion of the dielectric layer through a via pattern of the photoresist layer for forming... Agent: North America Intellectual Property Corporation

20080132069 - Apparatus and method for forming a thin layer on semiconductor substrates: An apparatus and a method form a thin layer on each of multiple semiconductor substrates. A processing chamber of the apparatus includes a boat in which the semiconductor substrates are arranged in a vertical direction. A vaporizer vaporizes a liquid metal precursor into a metal precursor gas. A buffer receives... Agent: Volentine & Whitt Pllc

20080132070 - Fully and uniformly silicided gate structure and method for forming same: Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep... Agent: International Business Machines Corporation Dept. 18g

20080132071 - Composition and method for enhancing pot life of hydrogen peroxide-containing cmp slurries: A method for providing CMP slurries for copper CMP that have improved pot life by ameliorating hydrogen peroxide degradation in slurries. The method comprises a composition that has a transition metal content of less than about 5 parts per million (ppm), preferably less than about 2 ppm. Preferably the method... Agent: Steven Weseman Associate General Counsel, I.p.

20080132072 - Semiconductor substrate having a protection layer at the substrate back side: By forming a protection layer on the back side of a substrate prior to any process sequences, which may deposit material or material residues on the back side, the respective back side uniformity may be significantly enhanced, thereby also increasing process efficiency of subsequent back side critical processes, such as... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.c.

20080132074 - Method for fabricating semiconductor device with recess gate: A method for fabricating a semiconductor device includes forming a first recess in a substrate, forming a plasma oxide layer over the substrate including first recess, etching the plasma oxide layer to have a portion of the plasma oxide layer remain on sidewalls of the first recess, and forming a... Agent: Lowe Hauptman Ham & Berner, LLP

20080132073 - Oxide pattern forming method and patterning method of semiconductor device: An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining region where the boron ions are not implanted.... Agent: Marshall, Gerstein & Borun LLP

20080132076 - Method for avoiding polysilicon defect: A method for avoiding a polysilicon defect includes: forming a silicon oxide layer on a silicon substrate; forming a polysilicon plug in the silicon oxide layer, with the polysilicon plug going through the silicon oxide layer; forming on the silicon oxide layer a silicon nitride layer covering the polysilicon plug;... Agent: Squire, Sanders & Dempsey L.l.p.

20080132075 - Method of manufacturing semiconductor memory device: A method of manufacturing a semiconductor device is disclosed. In the method of manufacturing the semiconductor device, a first insulating layer is formed on a semiconductor substrate. A metal line layer and an etch-stop layer are formed over the first insulating layer. The etch-stop layer and the metal line layer... Agent: Marshall, Gerstein & Borun LLP

20080132077 - Method for manufacturing a fin field effect transistor: The objective of the present invention is to provide a manufacturing method of a fin field effect transistor easily and surely without a constriction on a bottom end portion of the fin, through a method that includes a process for removing damage caused by plasma etching by wet etching of... Agent: Masuvalley & Partners

20080132078 - Ashing method and ashing apparatus: An ashing device and ashing method that can positively remove resist from a wafer while preventing degradation of the film material properties of exposed porous Low-K film on the wafer. The ashing device of the present invention introduces a gas to a dielectric plasma generating chamber 14, excites said gas... Agent: Snell & Wilmer LLP (oc)

20080132079 - Film formation apparatus and method for using the same: A method for using a film formation apparatus for a semiconductor process includes a first cleaning process of removing by a first cleaning gas a by-product film from an inner surface of a reaction chamber of the film formation apparatus, while supplying the first cleaning gas into the reaction chamber,... Agent: Smith, Gambrell & Russell

20080132080 - Method of avoiding haze formation on surfaces of silicon-containing pecvd-deposited thin films: A method of PECVD deposition of silicon-containing films has been discovered and further developed. The method is particularly useful when the films are deposited on substrates having surface areas which are larger than 25,000 cm2. The method prevents the deposition of partially reacted silicon-containing species which form a powdery material... Agent: Shirley L. Church, Esq.

20080132081 - Thin iii-v semiconductor films with high electron mobility: A method of forming a thin III-V semiconductor film on a semiconductor substrate, where the lattice structure of the III-V film is different than the lattice structure of the substrate. The method includes epitaxially growing the III-V film on the substrate until the III-V film is greater than 3.0 μm... Agent: Intel Corporation C/o Intellevate, Llc

20080132082 - Precision printing electroplating through plating mask on a solar cell substrate: Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080132083 - Film formation apparatus for semiconductor process and method for using the same: A method is provided for using a film formation apparatus including a process container having an inner surface, which contains as a main component a material selected from the group consisting of quartz and silicon carbide. The method includes performing a film formation process to form a silicon nitride film... Agent: Smith, Gambrell & Russell

20080132084 - Method for manufacturing semiconductor device background: To improve a step coverage and a loading effect, without inviting a deterioration of throughput and an increase of cost, in a method for forming a thin film by alternately flowing a raw material and alcohol to a processing chamber. The method includes: loading a silicon wafer having a surface... Agent: Oliff & Berridge, Plc

20080132085 - Silicon rich dielectric antireflective coating: A light absorption layer for use in fabricating semiconductor devices is provided with a high Si concentration. For example, a semiconductor device comprises a substrate and an Si-rich dielectric light absorption layer, such as an SiON or SiOX layer having an Si concentration of at least 68%. A second dielectric... Agent: Knobbe Martens Olson & Bear LLP

20080132086 - Reducing nitrogen concentration with in-situ steam generation: In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas.... Agent: Macpherson Kwok Chen & Heid LLP

20080132087 - Post-deposition treatment to enhance properties of si-o-c low k films: A method for providing a dielectric film having enhanced adhesion and stability. The method includes a post deposition treatment that densifies the film in a reducing atmosphere to enhance stability if the film is to be cured ex-situ. The densification generally takes place in a reducing environment while heating the... Agent: Townsend And Townsend And Crew LLP / Amat

20080132088 - Method for surface modification: A method for surface modification is disclosed. The method includes the step of irradiating a material with ultrashort pulse laser light to form a modified region including an amorphous region and/or a strain region on a surface of the material.... Agent: Sonnenschein Nath & Rosenthal LLP

20080132089 - Methods for discretized processing and process sequence integration of regions of a substrate: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is... Agent: Martine Penilla Gencarella, LLP