Semiconductor device manufacturing: process inventions 05/08

20080124814 - Method for passivation of plasma etch defects in dram devices: A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can... Agent: George O. Saile

20080124815 - Method for post cap ild/imd repair with uv irradiation: The present invention provides a method for repairing a damaged insulating layer in a semiconductor device comprising pre-cleaning the damaged insulating layer of the semiconductor device, depositing a CNH polymeric cap material on said damaged insulating layer, wherein said polymeric cap material comprises between about 10 and about 90 atomic... Agent: Scully, Scott, Murphy & Presser, P.C.

20080124816 - Systems and methods for semiconductor structure processing using multiple laser beam spots: Methods and systems selectively irradiate structures on or within a semiconductor substrate using multiple laser beams. The structures may be laser-severable conductive links, and the purpose of the irradiation may be to sever selected links.... Agent: Stoel Rives LLP

20080124817 - Stress measurement and stress balance in films: Methods and systems are provided of fabricating a compound nitride semiconductor structure. A substrate is disposed within a processing chamber into which a group-III precursor and a nitrogen precursor are flowed. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process using the precursors. The substrate is transferred... Agent: Townsend And Townsend And Crew LLP / Amat

20080124818 - Method and system for reducing the variation in film thickness on a plurality of semiconductor wafers having multiple deposition paths in a semiconductor manufacturing process: A method and system for reducing the variation in film thickness on a plurality of semiconductor wafers having multiple deposition paths in a semiconductor manufacturing process is disclosed. A film of a varying input thickness is applied to semiconductor wafers moving through various film deposition paths. The deposition path of... Agent: International Business Machines Corporation Dept. 18g

20080124819 - Molecular containment film modeling tool: A system and method for modeling the effect of a molecular contaminant film on performance of an optical system is disclosed. A mass of material outgassed from materials of the optical system is correlated to spectrum of outgassed products. The spectrum of outgassed products is normalized, and an aggregate molecular... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20080124820 - Method and system for detecting existence of an undesirable particle during semiconductor fabrication: One exemplary embodiment is a method for detecting existence of an undesirable particle between a planar lithographic object, such as a semiconductor wafer or a lithographic mask, and a chuck during semiconductor fabrication. The exemplary method in this embodiment includes placing the planar lithographic object, such as the semiconductor wafer,... Agent: Farjami & Farjami LLP

20080124821 - Method for fabricating a pixel structur of organic electroluminescent display: A method for fabricating a pixel structure of an OELD includes the following steps. First, a first gate, a scan line and a second gate are formed on a substrate. Next, a gate insulation layer is formed on the substrate to cover the first gate, the scan line and the... Agent: J C Patents, Inc.

20080124822 - Thermosetting resin composition and photo-semiconductor encapsulant: A method of encapsulating a photo-semiconductor device using a thermosetting resin composition comprising (A) a silicone compound containing at least two epoxy groups per molecule and having a molecular weight of 500-2, 100, (B) an acid anhydride, and (C) an optional catalyst, which cures into a low-stressed product having improved... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080124824 - Method for forming electronic devices by using protecting layers: This invention discloses that photolithography can be made compatible with the production of electronic devices containing sensitive materials, if the sensitive materials are over-coated with an ultra-thin layer of non-reactive materials (e.g. inorganic oxides) before undergoing photolithographic patterning. This protecting layer isolates the sensitive materials from solvents and etching reactants... Agent: Hoffmann & Baron, LLP

20080124823 - Method of fabricating patterned layer using lift-off process: Method of fabricating patterned layers using lift-off processes is disclosed. A patterned stacked layer is formed on a substrate. The patterned stacked layer consists of a sacrificed layer and a photoresist layer, which covers and extends out of the sacrificed layer. Next, a film layer having a thickness smaller than... Agent: Jianq Chyun Intellectual Property Office

20080124825 - Manufacturing method of liquid crystal display device: A method for manufacturing a liquid crystal display that provides a wide viewing angle and in which its manufacturing processes are shortened and high reliability is provided. The method includes a process of forming a gate electrode metal layer, gate insulator, and a—Si layer and forming an island by patterning... Agent: Hayes Soloway P.C.

20080124826 - Method and system for improving critical dimension proximity control of patterns on a mask or wafer: A method for improving critical dimension uniformity of a substrate is provided. An equation based on a proximity trend of a pattern on a first substrate is determined. The equation is applied in a regression model to determine a parameter value of a second substrate. A recipe of an exposure... Agent: Haynes And Boone, LLP

20080124827 - Method and structure for manffacturing long-wavelength visible light-emitting diode using prestrained growth effect: A method and structure for manufacturing long-wavelength visible light-emitting diode (LED) using the prestrained growth effect comprises the following steps: Growing a strained low-indium-content InGaN layer on the N-type GaN layer, and then growing a high-indium-content InGaN/GaN single- or multiple-quantum-well light-emitting structure on the low-indium-content InGaN layer to enhance the... Agent: Rosenberg, Klein & Lee

20080124828 - Fabrication processes of a mems alloy probe: MEMS processes for fabrication of a MEMS alloy probe are revealed. Multiple layers of the MEMS alloy probe are formed on the substrate in sequences as a first surface layer, a first conductive layer, a core layer, a second conductive layer, and a second surface layer where the width of... Agent: Troxell Law Office PLLC

20080124829 - Method for forming pinned photodiode resistant to electrical leakage: A method is provided for reducing or eliminating leakage between a pinned photodiode and shallow trench isolation structure fabricated therewith while optimizing the sensitivity of the photodiode. An N+ region is implanted in a P-type substrate and a P-type well separates the N+ region from the shallow trench isolation (STI)... Agent: Mark J. Marcelli Duane Morris LLP

20080124830 - Method of manufacturing image sensor: A method of manufacturing a CMOS image sensor in which a photodiode region and a floating diffusion region can be formed without using a hard mask. Such a method can prevent misalignment between the photodiode region and a gate pattern region without using a hard maska and also prevent the... Agent: Sherr & Nourse, PLLC

20080124831 - High-throughput printing of semiconductor precursor layer from chalcogenide particles: Methods and devices are provided for high-throughput printing of semiconductor precursor layer from microflake particles. In one embodiment, the method comprises of transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that... Agent: Director Of Ip

20080124832 - Formation of ultra-thin films that are grafted to electrically-conducting or semi-conducting surfaces: in the formation, by electrochemical grafting, of a homogeneous organic film, preferably with a thickness of less than or equal to 10 nm, on an electrically conducting or semiconducting surface; and to the corresponding process for the formation of an ultrathin homogeneous organic film on an electrically conducting or semiconducting... Agent: Alston & Bird LLP

20080124833 - Method for filling holes with metal chalcogenide material: A metal chalcogenide material is deposited into holes within a substrate surface. The method comprises obtaining a hydrophilic substrate surface; obtaining a solution of a hydrazine-based precursor of a metal chalcogenide; applying the solution onto the substrate to fill the holes with said precursor; and thereafter annealing the precursor to... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20080124834 - Mounting method of semiconductor element and manufacturing method of semiconductor device: A mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb), the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080124835 - Hermetic seal and reliable bonding structures for 3d applications: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned... Agent: Scully, Scott, Murphy & Presser, P.C.

20080124836 - Packaging substrate and manufacturing method thereof: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one... Agent: Birch Stewart Kolasch & Birch

20080124837 - Method of mounting semiconductor chip to circuit substrate using solder bumps and dummy bumps: A semiconductor chip comprises a silicon substrate on which semiconductor elements are formed, pads, each of which is formed on the silicon substrate and electrically connected to at least one of the semiconductor elements, a first insulating layer having an opening over each one of the pads, a first wiring... Agent: Birch Stewart Kolasch & Birch

20080124839 - Adhesive composition, adhesive sheet and production process for semiconductor device: An adhesive composition is characterized by including an acrylic polymer, an epoxy thermosetting resin having an unsaturated hydrocarbon group and a thermosetting agent. The adhesive composition achieves high reliability in a package in which a semiconductor chip of reduced thickness is mounted even when exposed to severe reflow conditions. An... Agent: The Webb Law Firm, P.C.

20080124838 - Gold/silicon eutectic die bonding method: A direct gold/silicon eutectic die bonding method is disclosed. The method includes the steps of gold plating a die bonding pad, grinding a wafer to a desired thickness, dicing the wafer after the grinding step, picking a die, and attaching the die to the die bonding pad at a temperature... Agent: Schein & Cai LLP

20080124840 - Electrical insulating layer for metallic thermal interface material: Various semiconductor devices and method of manufacturing the same are provided. In one aspect, a method of manufacturing is provided that includes forming an insulating layer on a backside of a semiconductor chip and forming a metallic thermal interface material on the insulating layer. In another aspect, an integrated circuit... Agent: Timothy M Honeycutt Attorney At Law

20080124842 - Method and apparatus for linear die transfer: A method for assembling a semiconductor device including the steps of providing a penetrable substrate having an adhesive surface and a plurality of dies disposed on the adhesive surface; providing a strap lead substrate having a plurality of strap leads disposed thereon; dispensing a first plurality of strap leads from... Agent: Jeffer, Mangels, Butler & Marmaro, LLP

20080124841 - Reduction of damage to thermal interface material due to asymmetrical load: Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive.... Agent: Timothy M Honeycutt Attorney At Law

20080124843 - Resin for sealing semiconductor device, resin-sealed semiconductor device and the method of manufacturing the semiconductor device: A resin sealed semiconductor device includes a semiconductor chip having a main surface, a plurality of surface electrodes formed on the main surface of the chip, a plurality of projection electrodes formed the main surface, each projection electrode being connected to respective one surface electrodes, and a resin shield covering... Agent: Junichi Mimura Oki America Inc.

20080124844 - Method of manufacturing well pick-up structure of non-volatile memory: A method of manufacturing a well pick-up structure of a non-volatile memory is provided. A substrate including a first conductive type well, device isolation structures and dummy memory columns is provided. Each of the dummy memory columns includes a second conductive type source region and a second conductive type drain... Agent: Jianq Chyun Intellectual Property Office

20080124845 - Stacked structures and methods of fabricating stacked structures: A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor... Agent: Duane Morris LLPIPDepartment (tsmc)

20080124846 - Method of fabricating thin film transistor: A method of fabricating a thin film transistor is provided. A gate is formed on a substrate. Then, an insulating layer is formed on the substrate to cover the gate. A semiconductor layer is formed on the insulating layer above the gate. A source/drain is formed on the semiconductor layer.... Agent: J C Patents, Inc.

20080124847 - Reducing crystal defects from hybrid orientation technology during semiconductor manufacture: Aspects of the present disclosure are directed to reducing strain in at least a portion of a bulk silicon region formed in a silicon-on-insulator (SOI) wafer using a hybrid orientation technology (HOT) process. A trench is formed having a sidewall liner. The liner is recessed prior to oxidation of the... Agent: Banner & Witcoff, Ltd.

20080124848 - Electronics device, semiconductor device, and method for manufacturing the same: In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of... Agent: Eric Robinson

20080124849 - Fabricating method of semiconductor device: The embodiment relates to a fabricating method of a semiconductor device, the method comprising the steps of: forming a gate oxide film, a gate electrode, and a side spacer on a semiconductor substrate; forming a source/drain area by implanting ion on the semiconductor substrate; forming a carbon layer on the... Agent: Sherr & Nourse, PLLC

20080124850 - Method for manufacturing semiconductor device and heat treatment method: A heat treatment that is necessary in a step of forming a thin film element by laminating a semiconductor film or an insulating film over a glass substrate is performed without thermally-damaging the substrate. For the purpose, a light-absorbing layer that can absorb pulsed light over a particular portion of... Agent: Eric Robinson

20080124851 - Gan-based high electron mobility transistor and method for making the same: A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through the openings.... Agent: HowardIPLaw Group

20080124852 - Method of forming t- or gamma-shaped electrode: A method of forming a fine T- or gamma-shaped gate electrode is provided, which is performed by a lithography process using a multi-layered photoresist layer having various sensitivities, deposition of an insulating layer, and an etching process. The method includes: a first step of depositing a first insulating layer on... Agent: Blakely Sokoloff Taylor & Zafman

20080124853 - Vertical-channel junction field-effect transistors having buried gates and methods of making: Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown... Agent: Merchant & Gould PC

20080124854 - Method for fabricating a semiconductor device and a semiconductor device fabricated by the method: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a conductive compound containing layer over the gate insulation layer, etching the conductive compound containing layer and the gate insulation layer to form a gate structure, forming a metal layer over the resultant... Agent: Ladas & Parry LLP

20080124856 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, in which a stress film having a large stress can be formed with high accuracy over a transistor. The method comprises the steps of: depositing a tensile stress film over the whole surface of a substrate having formed thereon an n-MOSFET; removing by... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080124855 - Modulation of stress in esl sin film through uv curing to enhance both pmos and nmos transistor performance: An example embodiment of a method of forming a semiconductor device comprising the following. We form at least a first transistor over a first region of a substrate and forming at least a second transistor over a second region of the substrate. We form a stress layer over the first... Agent: HorizonIPPte Ltd

20080124857 - Cmos device with metal and silicide gate electrodes and a method for making it: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.... Agent: Intel/blakely

20080124858 - Selective stress relaxation by amorphizing implant in strained silicon on insulator integrated circuit: A semiconductor fabrication process includes forming an NMOS gate electrode overlying a biaxially strained NMOS active region and forming a PMOS gate electrode overlying a biaxially strained PMOS active region. Amorphous silicon is created in a PMOS source/drain region to reduce PMOS channel direction tensile stress. A PMOS source/drain implant... Agent: Freescale Semiconductor, Inc.

20080124859 - Methods of forming cmos integrated circuits using gate sidewall spacer reduction techniques: Methods of forming field effect transistors include methods of forming PMOS and NMOS transistors by forming first and second gate electrodes on a substrate and then forming an electrically insulating layer having etch-enhancing impurities therein, on the first and second gate electrodes. The electrically insulating layer may be formed as... Agent: Myers Bigel Sibley & Sajovec

20080124860 - Metal gated ultra short mosfet devices: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer... Agent: Innovation Interface, LLC

20080124861 - Electron mobility enhancement for mos devices with nitrided polysilicon re-oxidation: A semiconductor structure includes a PMOS device and an NMOS device. The PMOS device includes a first gate dielectric on a semiconductor substrate, a first gate electrode on the first gate dielectric, and a first gate spacer along sidewalls of the first gate electrode and the first gate dielectric. The... Agent: Slater & Matsil, L.L.P.

20080124862 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive... Agent: Mcdermott Will & Emery LLP

20080124863 - Trench memory: A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of... Agent: Charles N. J. Ruggiero Ohlant, Greeley, Ruggiero & Perle, L.L.P.

20080124864 - Method for decreasing pn junction leakage current of dynamic random access memory: A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), includes the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon substrate; etching the insulation oxide layer until... Agent: Squire, Sanders & Dempsey L.L.P.

20080124865 - Method for forming non-volatile memory with shield plate for limiting cross coupling between floating gates: A memory system is disclosed that includes a set of non-volatile storage elements. Each of the non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned... Agent: Vierra Magen/sandisk Corporation

20080124866 - Methods of fabricating semiconductor devices: Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first... Agent: Myers Bigel Sibley & Sajovec

20080124868 - Fin-type field effect transistor: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080124867 - Methods of forming vertical transistors: A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over the first pillar, forming... Agent: Wells St. John P.s.

20080124869 - Methods of manufacturing vertical channel semiconductor devices: Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart... Agent: Myers Bigel Sibley & Sajovec

20080124871 - Methods of fabricating semiconductor device including fin-fet: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the... Agent: Marger Johnson & Mccollom, P.C.

20080124870 - Trench gate fet with self-aligned features: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants.... Agent: Townsend And Townsend And Crew, LLP

20080124872 - Method of integrating triple gate oxide thickness: A method for forming TGO structures includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the substrate and then removed... Agent: William Stoffel

20080124873 - Method of fabricating semiconductor device having gate dielectrics with different thicknesses: A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing... Agent: Harness, Dickey & Pierce, P.L.C

20080124875 - Method for forming a strained channel in a semiconductor device: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080124874 - Methods of forming field effect transistors having silicon-germanium source and drain regions: Methods of forming field effect transistors include forming an insulated gate electrode on a non-SiGe semiconductor substrate and then selectively etching the semiconductor substrate to define source and drain region trenches on opposite sides of the insulated gate electrode. A step is performed to remove native oxide layers from sidewalls... Agent: Myers Bigel Sibley & Sajovec

20080124876 - Method for forming contact hole in semiconductor device: Methods for forming a contact hole in a semiconductor device are provided. An exposed portion of an isolation layer, which may be generated during a process of forming a borderless contact hole, can be covered with a material similar to that of the substrate.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080124877 - Methods for fabricating a stress enhanced mos circuit: Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel region in the semiconductor substrate so that the stressed dummy gate... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080124878 - Multi-component strain-inducing semiconductor regions: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion... Agent: Intel/blakely

20080124879 - Method for fabricating semiconductor device: Provided is a method for fabricating a semiconductor device. In the method, a gate oxide layer and a gate electrode is formed on a substrate, and a first dopant implanted into the substrate using the gate electrode as an ion implantation mask. An insulation layer is formed on the gate... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080124880 - Fet structure using disposable spacer and stress inducing layer: Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form S/D regions adjacent the disposable spacers. We remove the disposable spacers.... Agent: HorizonIPPte Ltd

20080124881 - Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for si-ge bipolar technology: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region;... Agent: Scully, Scott, Murphy & Presser, P.C.

20080124882 - Sige heterojunction bipolar transistor (hbt) and method of fabrication: A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first... Agent: Ibm Microelectronics Intellectual Property Law

20080124883 - Semiconductor structure and method of manufacture: A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first... Agent: Greenblum & Bernstein, P.L.C

20080124884 - Methods for fabricating a semiconductor device on an soi substrate: Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080124887 - Method for manufacturing semiconductor device: A method for manufacturing semiconductor devices containing capacitors, the method includes: forming a second inter-layer insulating film over a first inter-layer insulating film; forming holes in the second inter-layer insulating film; forming a first electroconductive film covering the inner faces of the holes to form storage electrodes; forming thereafter a... Agent: Sughrue Mion, PLLC

20080124885 - Method of fabricating capacitor and electrode thereof: A method of fabricating an electrode of a capacitor is provided. A substrate is provided and a dielectric layer is then formed thereon. After that, one multilayer mask is formed on the dielectric layer to expose a portion of the dielectric layer, wherein the multilayer mask consists of at least... Agent: Jianq Chyun Intellectual Property Office

20080124886 - Method of fabricating capacitor over bit line and bottom electrode thereof: A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first contacts is then... Agent: Jianq Chyun Intellectual Property Office

20080124888 - Semiconductor device isolation structures: Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a substrate that is spaced apart from a first integrated device region. An isolation region may be interposed between the first integrated... Agent: Schwegman, Lundberg & Woessner, P.A.

20080124889 - Process of forming an electronic device including a conductive structure extending through a buried insulating layer: A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming... Agent: Larson Newman Abel Polansky & White, LLP

20080124890 - Method for forming shallow trench isolation structure: A method for forming a shallow trench isolation structure is described. A trench is formed in a substrate, and then a liner layer is formed in the trench. A portion of the liner layer around the top corner of the trench is removed, and then the trench is filled with... Agent: Jianq Chyun Intellectual Property Office

20080124891 - Method for preventing wafer edge peeling in metal wiring process: A method for preventing wafer edge peeling in a metal wiring process. A buffer layer is formed between a diffusion barrier layer of a metal wiring substructure and a semiconductor substrate. The buffer layer is an insulating dielectric layer, preferably a silicon oxide layer, or a polysilicon layer. The silicon... Agent: Squire, Sanders & Dempsey L.L.P.

20080124892 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprises at least two processes. Under an atmosphere comprising hydrogen and oxygen, a sacrificial oxide film is formed on a silicon substrate that is provided with at least one nitride region. Then, the sacrificial oxide film and the nitride region are removed from... Agent: Sughrue Mion, PLLC

20080124893 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device including a planar type transistor and a fin type transistor, a substrate having a first region and a second region is partially to form an isolation trench defining an isolation region and an active region. An insulation layer liner is formed on... Agent: Volentine & Whitt PLLC

20080124894 - Method of forming isolation layer of semiconductor device: A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned... Agent: Townsend And Townsend And Crew, LLP

20080124895 - Wafer bonding method: The invention is directed to a wafer bonding method for bonding a first wafer with a second wafer, wherein the first wafer has a first top surface and the second wafer has a second top surface formed thereon and the first wafer bonds with the second wafer in a manner... Agent: Jianq Chyun Intellectual Property Office

20080124897 - Method of producing bonded wafer: A bonded wafer is produced by implanting ions of a light element into a wafer for active layer to a predetermined depth position to form an ion implanted layer, bonding the wafer for active layer to a wafer for support substrate directly or through an insulating film of not more... Agent: Sughrue Mion, PLLC

20080124896 - Silicon wafer thinning end point method: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080124898 - Wafer laser processing method and laser beam processing machine: A wafer laser processing method for forming deteriorated layers in the inside of a wafer having devices which are formed in a plurality of areas sectioned by a plurality of streets formed in a lattice pattern on the front surface along the streets by applying a laser beam along the... Agent: Smith, Gambrell & Russell

20080124899 - Method of improving a surface of a semiconductor substrate: The invention relates to a method of improving a surface of a semiconductor substrate which is at least partially made of silicon. Defects present in or on the semiconductor substrate can be really repaired to provide a semiconductor substrate with a high surface quality. This is achieved by a selective... Agent: Winston & Strawn LLP Patent Department

20080124900 - Method for introduction impurities and apparatus for introducing impurities: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous... Agent: Mcdermott Will & Emery LLP

20080124901 - Method for maintaining semiconductor manufacturing apparatus, semiconductor manufacturing apparatus, and method for manufacturing semiconductor: A method for maintaining semiconductor manufacturing apparatus, semiconductor manufacturing apparatus, and a method for manufacturing a semiconductor that allow a component to be reused and contamination to a wafer to be suppressed without a need for replacement of the component, are provided. The method for maintaining semiconductor manufacturing apparatus includes,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080124902 - Method of manufacturing a semiconductor device comprising a field stop zone at a specific depth: Some embodiments of the invention relate to manufacturing a semiconductor device with an implantation layer on a semiconductor substrate including a method of manufacturing such an implantation layer, wherein said implantation layer is formed in an implantation step at a predetermined depth of penetration, determined from a top surface of... Agent: Schwegman, Lundberg & Woessner, P.A.

20080124903 - Techniques for low-temperature ion implantation: Techniques for low-temperature ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a wafer support mechanism to hold a wafer during ion implantation and to facilitate movement of the wafer in at least one... Agent: Hunton & Williams LLP/varian Semiconductor, Equipment Associates, Inc.

20080124904 - Method for fabricating semiconductor device: Provided is a method for fabricating a semiconductor device. The method includes implanting ions into an n-channel metal oxide semiconductor (NMOS) region of a semiconductor substrate so as to form a channel. The implanting can be performed by implanting boron ions at an ion implanting energy of 20 keV to... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080124905 - Solid-state circuit assembly: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080124906 - Method for transferring self-assembled dummy pattern to substrate: A semiconductor device fabrication method is disclosed. The method includes obtaining an inverse layout of an original circuit layout, reducing the inverse layout in size, thereby obtaining a reduced layout, obtaining a dummy pattern layout having an outline identical to an outline of the reduced layout and a given line... Agent: Townsend And Townsend And Crew, LLP

20080124907 - Hafnium lanthanide oxynitride films: Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium... Agent: Schwegman, Lundberg & Woessner, P.A.

20080124908 - Hafnium tantalum oxynitride high-k dielectric and metal gates: Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may... Agent: Schwegman, Lundberg & Woessner, P.A.

20080124909 - Methods of cleaning a semiconductor device and methods of manufacturing a semiconductor device using the same: The present invention provides methods of cleaning a semiconductor device by removing contaminants, such as particles and/or etching by-products, from a structure of a semiconductor device using a first cleaning solution including a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and deionized (DI) water, and a second cleaning solution... Agent: Myers Bigel Sibley & Sajovec

20080124910 - Method of disposing and arranging dummy patterns: A method of disposing dummy patterns is described, which is used for increasing the pattern density of an aluminum pad layer. A substrate is provided, and an aluminum pad material layer is formed on the substrate. Then, the aluminum pad material layer is patterned to form the aluminum pad layer... Agent: Jianq Chyun Intellectual Property Office

20080124911 - Method of forming a pattern and method of manufacturing a capacitor using the same: In a method of forming a pattern and a method of manufacturing a capacitor using the same, a conductive layer is formed on a mold layer having an opening. A first buffer layer pattern including a polymer having a repeating unit of anthracene-methyl methacrylate and a repeating unit of alkoxyl-vinyl... Agent: Marger Johnson & Mccollom, P.C.

20080124912 - Semiconductor methods: A method includes the steps of: (a) forming a conductive layer within a dielectric layer formed over a substrate; (b) forming a material layer over the conductive layer and the dielectric layer; (c) forming an opening within the material layer by an etch process to expose a portion of the... Agent: Duane Morris LLPIPDepartment (tsmc)

20080124913 - Slurry compositions and cmp methods using the same: The exemplary embodiments of the present invention providing new slurry compositions suitable for use in processes involving the chemical mechanical polishing (CMP) of a polysilicon layer. The slurry compositions include one or more non-ionic polymeric surfactants that will selectively form a passivation layer on an exposed polysilicon surface in order... Agent: Harness, Dickey & Pierce, P.L.C

20080124918 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080124915 - Method for manufacturing semiconductor device: An insulation film having an open part in which a silicon part is exposed at a bottom surface is formed on a silicon substrate for forming a semiconductor device. Titanium is deposited to form a titanium film on the bottom surface and side wall surfaces of the contact hole. The... Agent: Oliff & Berridge, PLC

20080124914 - Method of fabricating flash memory device: A method of fabricating a flash memory device includes forming an insulating layer and a hard mask film pattern over a semiconductor substrate. A spacer is formed along surfaces of the hard mask film pattern and the insulating layer. Contact holes are formed in the insulating layer by a first... Agent: Townsend And Townsend And Crew, LLP

20080124917 - Method of manufacturing a semiconductor device having air gaps: In a method of manufacturing a semiconductor device having air gaps, an organic sacrificial layer pattern is formed on a semiconductor substrate, wherein the organic sacrificial layer pattern includes openings. Metal structures are formed in the openings. The organic sacrificial layer pattern is removed by a plasma ashing treatment using... Agent: Mills & Onello LLP

20080124916 - Method of manufacturing semiconductor device: A method manufacturing a semiconductor device is provided. Cost can be reduced and line reliability can be improved since a step for depositing a barrier metal is not required. An interlayer insulating layer, including a contact hole, can be formed on a semiconductor substrate. A seed layer, including a first... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080124919 - Cleaning processes in the formation of integrated circuit interconnect structures: A method for fabricating an integrated circuit includes providing a substrate, forming a low-k dielectric layer over the substrate, etching the low-k dielectric layer to form an opening in the low-k dielectric layer wherein an underlying metal is exposed through the opening, performing a remote plasma treatment to the substrate... Agent: Slater & Matsil, L.L.P.

20080124920 - Fabrication method for an integrated circuit structure: The present invention provides a fabrication method for an integrated circuit structure comprising the steps of forming a electrode layer stack (5, 6′, 7′, 8′) by sequentially depositing a polysilicon layer (5) on a gate dielectric layer (9); a contact layer (6′) composed of Ti on the polysilicon layer (5);... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080124923 - fabricating method of semiconductor device: Disclosed is a method of fabricating a semiconductor device, capable of improving the reliability of a semiconductor device. The method of fabricating the semiconductor device comprises forming a cobalt layer on an entire surface of a semiconductor substrate including a transistor structure, forming a cobalt nitride layer on the cobalt... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080124922 - Method for fabricating semiconductor device: A semiconductor device fabrication method by which the thermal stability of nickel silicide can be improved. Nickel (or a nickel alloy) is formed over a semiconductor substrate on which a gate region, a source region, and a drain region are formed. Dinickel silicide is formed by performing a first annealing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080124921 - Method forming ohmic contact layer and metal wiring in semiconductor device: A method of forming an ohmic contact layer including forming an insulation layer pattern on a substrate, the insulation pattern layer having an opening selectively exposing a silicon bearing layer, forming a metal layer on the exposed silicon bearing layer using an electrode-less plating process, and forming a metal silicide... Agent: Volentine & Whitt PLLC

20080124924 - Scheme for copper filling in vias and trenches: Embodiments of the present invention generally relate to methods and apparatuses using supercritical fluids and/or dense fluids to deposit a metal material on the surface of a substrate. In one embodiment, a metal material layer is deposited by applying a supercritical fluid, a dense fluid, or combinations thereof and a... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080124925 - Method for improved formation of cobalt silicide contacts in semiconductor devices: A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at a temperature of about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a cobalt layer over the wafer at a point in... Agent: Cantor Colburn LLP - IBM Fishkill

20080124926 - Methods for growing low-resistivity tungsten film: Improved methods for depositing low resistivity tungsten films are provided. The methods involve depositing a tungsten nucleation layer on a substrate and then depositing a tungsten bulk layer over the tungsten nucleation layer to form the tungsten film. The methods provide precise control of the nucleation layer thickness and improved... Agent: Beyer Weaver LLP

20080124927 - Semiconductor device including a discontinuous film and method for manufacturing the same: Disclosed is a semiconductor device comprising a semiconductor substrate, a first insulating film formed above the semiconductor substrate, Cu wiring buried in the first insulating film, a second insulating film formed above the Cu wiring, and a discontinuous film made of at least one metal selected from the group consisting... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080124928 - Method for decapsulating package: A method for decapsulating a package is provided. The method comprises steps of providing a package having a chip therein, wherein the chip has an active surface and a rear surface. Further, the package further comprises a heat sink, a plurality of solder bumps, a substrate, an underfill and a... Agent: Jianq Chyun Intellectual Property Office

20080124932 - Apparatus and method for surface treatment of substrate, and substrate processing apparatus and method: An surface treatment apparatus of a substrate can clean a substrate surface in the air without employing a vacuum apparatus, and can remove a natural oxide film or an organic material, such as BTA, from the substrate surface without resorting to plasma cleaning. The surface treatment apparatus includes: an inert... Agent: Wenderoth, Lind & Ponack, L.L.P.

20080124931 - Method for forming fine patterns of a semiconductor device using a double patterning process: A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming... Agent: Lee & Morse, P.C.

20080124930 - Methods of recycling a substrate including using a chemical mechanical polishing process: In a method of recycling a substrate having an edge portion on which a stepped portion is formed, the substrate is chemically mechanically polished using a first slurry composition including fumed silica to remove the stepped portion. The substrate is then chemically mechanically polished using a second slurry composition including... Agent: Myers Bigel Sibley & Sajovec

20080124929 - Process for regenerating layer transferred wafer and layer transferred wafer regenerated by the process: The process for regenerating a layer transferred wafer in which the layer transferred wafer 11b obtained as a by-product in manufacturing a bonded SOI wafer 10 by an ion implantation separation method so as to be reused for an SOI layer wafer 11 of the bonded SOI wafer 10, comprises:... Agent: Reed Smith, LLP Attn: Patent Records Department

20080124933 - Fabrication process of a semiconductor device: A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080124934 - Method of manufacturing a semiconductor device: In one embodiment, a preliminary insulation layer is formed over a cell region and a peripheral circuit region of a semiconductor substrate. The preliminary insulation layer covers a capacitor formed over the cell region. The preliminary insulation layer over the cell region has a first height higher than a second... Agent: Harness, Dickey & Pierce, P.L.C

20080124935 - Two-step process for manufacturing deep trench: A two-step process for manufacturing a deep trench in a semiconductor device that prevents shorts and leakages between neighboring capacitors due to over etching is disclosed. The process comprises conducting a first etching step to remove a portion of a substrate to form a trench with a first determined depth... Agent: Nixon Peabody LLP - Patent Group

20080124936 - Manufacturing method of capacitor electrode, manufacturing system of capacitor electrode, and storage medium: A method for manufacturing a capacitor electrode by removing a silicon oxide film on a surface of a substrate, including: transforming the silicon oxide film into a reaction product by supplying a gas containing a halogen element to chemically react with the silicon oxide film while controlling temperature of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080124937 - Selective etching method and apparatus: A dry etching method and apparatus are described. A workpiece supports silicon nitride and silicon dioxide. The workpiece is exposed to a plasma containing at least one of sulfur hexafluoride and nitrogen trifluoride and ammonia to selectively remove the silicon nitride in relation to the silicon dioxide. In one feature,... Agent: Pritzkau Patent Group, LLC

20080124938 - Chromium-free etching solution for si-substrates and uses therefor: The present invention relates to a novel etching solution suitable for characterizing defects on semiconductor surfaces, including silicon germanium surfaces, as well as a method for treating semiconductor surfaces with an etching solution as disclosed herein. This novel etching solution is chromium-free and enables a highly sufficient etch rate and... Agent: Winston & Strawn LLP Patent Department

20080124939 - Process of etching a titanium/tungsten surface and etchant used therein: An etchant which includes an aqueous solution of between about 30% and about 38% concentrated hydrogen peroxide, said percentages being by volume, based on the total volume of the solution; between about 3.5 ml and about 20 ml per liter of phosphoric acid; and an amount of potassium hydroxide to... Agent: Scully, Scott, Murphy & Presser, P.C.

20080124940 - Method of forming dielectric layer: A method of forming a dielectric layer is provided. A first dielectric layer is formed on a substrate having metal layers formed thereon. The first dielectric layer includes overhangs in the spaces between two neighboring metal layers and voids under the overhangs. The first dielectric layer is partially removed to... Agent: J C Patents, Inc.

20080124941 - Manufacturing method of semiconductor device and semiconductor device manufacturing apparatus: To provide a manufacturing method of a semiconductor device for forming a diffusion layer by diffusing phosphorus atoms on a surface of a silicon substrate on which resist is applied, including the step of forming a diffusion layer, with a temperature of the silicon substrate maintained lower than a deterioration... Agent: Oliff & Berridge, PLC

20080124942 - Method for forming thin film heads using a bi-layer anti-reflection coating for photolithographic applications and a device thereof: A bi-layer anti-reflective coating for use in photolithographic applications, and specifically, for use in ultraviolet photolithographic processes. The bi-layered anti-reflective coating is used to minimize pattern distortion due to reflections from neighboring features in the construction of microcircuits. The bi-layer anti-reflection coating features a first layer, an absorption layer, disposed... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080124943 - Manufacturing method of a semiconductor device, and substrate processing apparatus: An object of this invention is to make it possible to suppress early-stage oxidation of a substrate surface prior to oxidation processing, and to remove a natural oxidation film. For this reason, a method is provided comprising the steps of loading a substrate into a processing chamber, supplying a hydrogen-containing... Agent: Oliff & Berridge, PLC

20080124944 - Gas baffle and distributor for semiconductor processing chamber: Apparatus and methods for distributing gas in a semiconductor process chamber are provided. In an embodiment, a gas distributor for use in a gas processing chamber comprises a body. The body includes a baffle with a gas deflection surface to divert the flow of a gas from a first direction... Agent: Townsend And Townsend And Crew LLP / Amat

20080124945 - Production method for semiconductor device and substrate processing apparatus: Disclosed is a producing method of a semiconductor device comprising a first step of supplying a first reactant to a substrate to cause a ligand-exchange reaction between a ligand of the first reactant and a ligand as a reactive site existing on a surface of the substrate, a second step... Agent: Birch Stewart Kolasch & Birch

20080124946 - Organosilane compounds for modifying dielectrical properties of silicon oxide and silicon nitride films: The present invention discloses a process for depositing a carbon containing silicon oxide film, or a carbon containing silicon nitride film having enhanced etch resistance. The process comprises using a silicon containing precursor, a carbon containing precursor and a chemical modifier. The present invention also discloses a process for depositing... Agent: Air Products And Chemicals, Inc. Patent Department

20080124947 - Manufacturing apparatus for semiconductor device and manufacturing method of semiconductor device: A manufacturing apparatus for a semiconductor device that includes a bake chamber for a wafer with a coating film formed thereon to be baked at a predetermined temperature, a cooling chamber connected to the bake chamber, a first carrying unit for the baked wafer to be carried in the cooling... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080118995 - Method and composition for restoring dielectric properties of porous dielectric materials: The present invention provides a method for restoring the dielectric properties of a porous dielectric material. The method comprises providing a substrate comprising at least one layer of a porous dielectric material comprising a contaminant comprising at least one entrapped liquid having a surface tension, wherein the porous dielectric material... Agent: Air Products And Chemicals, Inc. Patent Department

20080118994 - Residue isolation process in tft lcd fabrication: A method is used to prevent unwanted electrical contacts between various electrically conducting surfaces and lines in a display panel due to an n+ a-Si residue and/or ITO debris. The method provides a clearing pattern including at least a cleared area in the passivation layer for preventing the residue or... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080118996 - Thin film transistor array substrate and method of producing the same: A method of producing a thin film transistor array substrate which includes an insulating substrate, a display pixel having a pixel electrode connected to a drain electrode, a gate wiring, and a source wiring perpendicular to the gate wiring, comprising forming a first thin metal multi-layer film an upper layer... Agent: Buchanan, Ingersoll & Rooney Pc

20080118997 - Vacuum holder for integrated circuit units: A support device for supporting a set of integrated circuit units (65), the device comprising: a support member having a metal surface, said surface having an array of recesses (27); a soft material layer, overlaying the recesses of the metal surface so as to protect the units (65) from damage... Agent: Dickstein Shapiro LLP

20080118998 - Method for enhancing lightness of p-type nitride group compound l.e.d.: A method for enhance lightness of p-type nitride group compound L.E.D. is disclosed. The present invention, firstly, the p-type GaN semiconductor layer is provided, then, the different thickness and coverage for titanium metal are coated on the p-type GaN semiconductor layer. Next, the activation process is carried out in the... Agent: Bacon & Thomas, Pllc

20080118999 - Method of fabricating a nitride semiconductor light emitting device: A method of fabricating a nitride semiconductor light emitting device includes the steps of: depositing on a substrate a first n-type nitride semiconductor layer, a light emitting layer, a p-type nitride semiconductor layer, and p-type nitride semiconductor tunnel junction layer containing an indium, in this order; depositing a nitride semiconductor... Agent: Morrison & Foerster LLP

20080119000 - Monolithic ic and mems microfabrication process: Monolithic IC/MEMS processes are disclosed in which high-stress silicon nitride is used as a mechanical material while amorphous silicon serves as a sacrificial layer. Electronic circuits and micro-electromechanical devices are built on separate areas of a single wafer. The sequence of IC and MEMS process steps is designed to prevent... Agent: Morrison Ulman Nupat, Llc

20080119001 - Substrate contact for a mems device: One embodiment of the present invention sets forth a substrate contact for a MEMS device die, where the substrate contact is formed through an electrically insulative layer in the device die that is positioned between a handle wafer layer and a MEMS device layer formed on the handle wafer layer.... Agent: Patterson & Sheridan, L.l.p.

20080119002 - Substrate contact for a mems device: One embodiment of the present invention sets forth a substrate contact for a MEMS device die, where the substrate contact is formed through an electrically insulative layer in the device die that is positioned between a handle wafer layer and a MEMS device layer formed on the handle wafer layer.... Agent: Patterson & Sheridan, L.l.p.

20080119003 - Substrate contact for a mems device: One embodiment of the present invention sets forth a substrate contact for a MEMS device die, where the substrate contact is formed through an electrically insulative layer in the device die that is positioned between a handle wafer layer and a MEMS device layer formed on the handle wafer layer.... Agent: Patterson & Sheridan, L.l.p.

20080119004 - Method of packaging a device having a keypad switch point: A packaged device has a semiconductor device that has a first major surface and a second major surface. An encapsulating layer is formed over the second major surface and around sides of the semiconductor device. The first major surface of the semiconductor device is left exposed. The semiconductor device has... Agent: Freescale Semiconductor, Inc. Law Department

20080119005 - Method for patterning mo layer in a photovoltaic device comprising cigs material using an etch process: A processing method described herein provides a method of patterning a MoSe2 and/or Mo material, for example a layer of such material(s) in a thin-film structure. According to one aspect, the invention relates to etch solutions that can effectively etch through Mo and/or MoSe2. According to another aspect, the invention... Agent: Applied Materials C/o Pillsbury Winthrop Shaw Pittman LLP

20080119006 - Method for manufacturing image sensor: Disclosed is a method for manufacturing an image sensor. The method includes forming a polysilicon layer on a semiconductor substrate having an active region, forming a sacrificial layer on the polysilicon layer, forming a photoresist pattern on the sacrificial layer, implanting conductive impurities onto the polysilicon layer using the photoresist... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080119010 - Manufacturing method of organic semiconductor device: A main object of the present invention is to provide a manufacturing method of an organic semiconductor device, wherein the method enabling an organic semiconductor layer to be patterned simply with high productivity and also enabling an organic semiconductor device having an organic semiconductor transistor to be produced with high... Agent: Ladas & Parry LLP

20080119011 - Method of film coating and device manufactured thereby: A method of forming a continuous layer of film, the method comprising providing a substrate having a surface, forming a first patterned layer of film on the surface, the first patterned layer of film including a plurality of first film units separated from each other, and forming a second patterned... Agent: Akin Gump LLP - Silicon Valley

20080119007 - Method of making a nonvolatile phase change memory cell having a reduced contact area: A method is described to form a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin,... Agent: Eschweiler & Associates Llc

20080119008 - Molecular device and manufacturing method for the same: A molecular device of the present invention is arranged so that a self-organizing monomolecular layer is formed on an oxide layer made of an oxide of a substrate by being chemically bonded with the surface of the oxide layer, and nano structures are formed on the monomolecular film. With this... Agent: Harness, Dickey & Pierce, P.L.C

20080119009 - Organic semiconductor material and semiconductor device: m

20080118993 - Method of manufacturing magnetic random access memory (mram): A magnetic random access memory (MRAM), and a method of manufacturing the same, includes a switching device and a magnetic tunneling junction (MTJ) cell connected to the switching device, wherein the MTJ cell includes a pinned film having a metal film and a magnetic film, the magnetic film enclosing the... Agent: Lee & Morse, P.c.

20080119012 - Mold array process for chip encapsulation and substrate strip utilized: A MAP (Mold Array Process) for chip encapsulation is disclosed in this invention. First, a substrate strip having a plurality of units is provided. A plurality of chips are disposed on the substrate strip and then an encapsulant is formed made by transfer molding to continuously encapsulate the chips on... Agent: Troxell Law Office Pllc

20080119014 - Method and apparatus for reducing stresses applied to bonded interconnects between substrates: A method (200) is provided for reducing stresses applied to one or more bonded interconnects (106) of a substrate (103) and a PCB (Printed Circuit Board) (104). The method comprises the steps of coupling (204) a compound (108) on a top surface of the substrate, wherein the compound has the... Agent: Motorola, Inc

20080119013 - Method of packaging a device using a dielectric layer: A method is for packaging a first device having a first major surface and a second major surface. An encapsulant is formed over a second major surface of the first device and around sides of the first device. This leaves the first major surface of the first device exposed. A... Agent: Freescale Semiconductor, Inc. Law Department

20080119015 - Method of packaging a semiconductor device and a prefabricated connector: A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein... Agent: Freescale Semiconductor, Inc. Law Department

20080119016 - Microcircuit fabrication and interconnection: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include... Agent: Schwabe, Williamson & Wyatt, P.c.

20080119017 - Method for manufacturing thin film transistor using differential photo-resist developing: An exemplary method for manufacturing a thin film transistor includes: forming at least two photo-resist layers on a substrate, a developing speed of an upper one of the photo-resist layers being less than that of each photo-resist layer below said upper one of the photo-resist layers; exposing and developing the... Agent: Wei Te Chung Foxconn International, Inc.

20080119018 - Image display unit and method for manufacturing the same: The present invention provides an image display unit and a method for manufacturing the same, in which the number of photolithographic processes can be reduced in the manufacture of an active substrate, and the manufacturing cost can be decreased. In a bottom gate type TFT substrate, a transparent conductive film... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20080119019 - Semiconductor devices having pfet with sige gate electrode and embedded sige source/drain regions and methods of making the same: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate... Agent: Slater & Matsil LLP

20080119020 - Methods of forming a field effect transistors, pluralities of field effect transistors, and dram circuitry comprising a plurality of individual memory cells: A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially... Agent: Wells St. John P.s.

20080119021 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080119022 - Method of making eeprom transistors: A first mask set is used to define parallel active area stripes while a second mask set with memory cell stripes is perpendicular to the first mask set. The second mask set features cell masks with spaced apart branches, one for a non-volatile memory cell. The branch for the non-volatile... Agent: Schneck & Schneck

20080119023 - Manufacturing method for semiconductor device to mitigate short channel effects: A method of manufacturing a plurality of MOS transistors includes forming gate structures in first and second regions on a substrate and forming mask portions only between adjacent drain sides of the respective gate structures only in the first region. Dopant of a first conductivity type that is the same... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080119024 - Method of manufacturing a semiconductor device: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order... Agent: Fish & Richardson P.c.

20080119025 - Method of making a strained semiconductor device: In a method of making a semiconductor device, a recess is formed in an upper surface of the semiconductor body of a first material. An embedded semiconductor region is formed in the recess. The embedded semiconductor region is formed from a second semiconductor material that is different than the first... Agent: Slater & Matsil LLP

20080119026 - Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080119027 - Vertically stacked field programmable nonvolatile memory and method of fabrication: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum... Agent: Dugan & Dugan, Pc

20080119028 - Soq substrate and method of manufacturing soq substrate: Hydrogen ions are implanted to a surface of a single crystal Si substrate 10 through an oxide film 11 to uniformly form an ion implanted layer 12 at a predetermined depth (average ion implantation depth L) from the surface of the single crystal Si substrate 10, and a bonding surface... Agent: Oliff & Berridge, Plc

20080119029 - Wafer scale thin film package: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by... Agent: John A. Jordan, Esq.

20080119030 - Method for manufacturing thin film semiconductor device: According to an embodiment of the present invention, there is provided an improved method for manufacturing a thin film semiconductor device. This method includes the step of depositing a silicon thin film including a crystalline structure on a substrate by plasma CVD in which a silane gas represented by the... Agent: Rader Fishman & Grauer Pllc

20080119031 - Stress enhanced mos transistor and methods for its fabrication: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate... Agent: Ingrassia Fisher & Lorenz, P.c. (amd)

20080119032 - Etching method and structure using a hard mask for strained silicon mos transistors: A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns... Agent: Townsend And Townsend And Crew, LLP

20080119033 - Method of integrating metal-containing films into semiconductor devices: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080119034 - Method of formation of coherent wavy nanostructures (variants): The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.... Agent: Darby & Darby P.c.

20080119037 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes: (a) forming a stress relaxation layer on a first surface having an electrode of a semiconductor substrate; (b) forming a wiring line so as to cover the electrode and the stress relaxation layer after step (a); (c) forming a solder resist layer... Agent: Harness, Dickey & Pierce, P.L.C

20080119035 - Wire and solder bond forming methods: Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only;... Agent: Hoffman, Warnick & D'alessandro Llc

20080119036 - Wire and solder bond forming methods: Methods of forming wire and solder bonds are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide... Agent: Hoffman, Warnick & D'alessandro Llc

20080119038 - Use of palladium in ic manufacturing with conductive polymer bump: An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising... Agent: Trask Britt, P.c./ Micron Technology

20080119039 - Memory card with connecting portions for connection to an adapter: Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a second conductive feature of the interconnect structure... Agent: Slater & Matsil LLP

20080119040 - Method for forming a dual damascene structure: A method for forming a dual damascene structure is provided. In one embodiment, a semiconductor substrate with a patterned protective layer formed thereover is provided. A conformal dielectric layer is formed over the protective layer. A patterned mask layer is formed over the dielectric layer. A portion of the dielectric... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080119041 - Method for fabricating closed vias in a printed circuit board: A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central... Agent: Motorola, Inc.

20080119042 - Systems and methods for back end of line processing of semiconductor circuits: A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the... Agent: Baker & Mckenzie LLP Patent Department

20080119043 - Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same: A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than the second opening. A first conductive material is formed over the semiconductor wafer to... Agent: Kevin D. Martin Micron Technology, Inc.

20080119044 - Systems and methods for back end of line processing of semiconductor circuits: A BEOL manufacturing process for forming a via on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and... Agent: Baker & Mckenzie LLP Patent Department

20080119045 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes (a) forming a conductive film on a first surface having an electrode of a semiconductor substrate having an integrated circuit formed therein, the electrode being electrically coupled to the integrated circuit, such that the electrode is covered, forming a plating resist layer... Agent: Harness, Dickey & Pierce, P.L.C

20080119046 - Method of making a contact on a backside of a die: A method of forming a semiconductor device includes forming active circuitry over a semiconductor substrate, wherein the semiconductor substrate has a first major surface and a second major surface and the first active circuitry is formed over the first major surface of the semiconductor substrate. A via is formed within... Agent: Freescale Semiconductor, Inc. Law Department

20080119047 - Schemes for forming barrier layers for copper in interconnect structures: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining... Agent: Slater & Matsil, L.l.p.

20080119048 - Lithography masks and methods of manufacture thereof: Lithography masks and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of manufacturing a lithography mask. The method includes providing a substrate, forming a first pattern in a first region of the substrate, and forming a second pattern in a second region of the substrate, the... Agent: Slater & Matsil LLP

20080119049 - Plasma etching method and apparatus: A plasma etching method and apparatus. In the plasma etching apparatus, pluralities of RF power supplies are respectively connected to upper and lower electrode via relevant matching networks to enable generation of various ion densities and ion energies of plasma by individually changing RF powers applied to the upper and... Agent: Stanzione & Kim, LLP

20080119050 - Semiconductor device manufacture method: An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating surface of the substrate and leave a portion of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080119051 - Method for selective cmp of polysilicon: A method of removing polysilicon in preference to silicon dioxide and/or silicon nitride by chemical mechanical polishing. The method removes polysilicon from a surface at a high removal rate while maintaining a high selectivity of polysilicon to silicon dioxide and/or a polysilicon to silicon nitride. The method is particularly suitable... Agent: Rankin, Hill & Clark LLP

20080119052 - Selective barrier metal polishing method: The polishing method uses a polishing solution for removing barrier materials in the presence of interconnect metals and dielectrics. The polishing solution comprises, by weight percent, 0.1 to 10 hydrogen peroxide, at least one pH adjusting agent selected from the group consisting of nitric acid, sulfuric acid, hydrochloric acid and... Agent: Rohm And Haas Electronic Materials Cmp Holdings, Inc.

20080119053 - Method of manufacturing sidewall spacers on a memory device, and device comprising same: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit... Agent: Wells St. John P.s.

20080119054 - Method of manufacturing semiconductor device: There is provided a dry etching method for forming wiring trenches in a first insulating layer and in a second insulating layer provided thereon. First, the second insulating layer is etched partway under first etching conditions using resist as a mask (first etching step). Next, the remnant of the second... Agent: Mcginn Intellectual Property Law Group, Pllc

20080119055 - Reducing twisting in ultra-high aspect ratio dielectric etch: An apparatus for etching a dielectric layer contained by a substrate is provided. An etch reactor comprises a top electrode and a bottom electrode. An etch gas source supplies an etch gas into the etch reactor. A first Radio Frequency (RF) source generates a first RF power with a first... Agent: Beyer Weaver LLP

20080119056 - Method for improved copper layer etching of wafers with c4 connection structures: A solution for wet etching a copper film within a ball limiting metallurgy (BLM) of a semiconductor device includes, in an exemplary embodiment, an ammonium persulfate etching agent, a potassium sulfate passivation agent for protecting a PbSn solder material, and a pH modifier for controlling the etch rate of the... Agent: Cantor Colburn LLP - Ibm Fishkill

20080119057 - Method of clustering sequential processing for a gate stack structure: A method of forming a gate dielectric comprising silicon and oxygen is provided. The gate dielectric may also include nitrogen or another high k material. In one aspect, forming the gate dielectric includes annealing a substrate in an oxidizing atmosphere to form a silicon oxide layer, depositing a silicon nitride... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080119058 - Method of improving initiation layer for low-k dielectric film by digital liquid flow meter: A method for depositing a low dielectric constant film by flowing a oxidizing gas into a processing chamber, flowing an organosilicon compound from a bulk storage container through a digital liquid flow meter at an organosilicon flow rate to a vaporization injection valve, vaporizing the organosilicon compound and flowing the... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080119059 - Low thermal budget chemical vapor deposition processing: Methods for low thermal budget silicon dioxide chemical vapor deposition in single-wafer chambers are provided. In semiconductor manufacturing, Si2H6-based oxide deposition is worthy of consideration as a viable alternative to higher temperature thermal CVD processes. A process of forming a film on a substrate is provided, the process comprising: placing... Agent: Karen M. Whitney Applied Materials, Inc.

20080119060 - Inspection systems and methods: Inspection systems and methods are disclosed. A preferred embodiment comprises an inspection system including a support for a reticle and a microscope including a lens system. The lens system includes at least one lens comprising at least one Fresnel element, wherein the at least one Fresnel element is non-circular.... Agent: Slater & Matsil LLP

20080113453 - Fabrication process of semiconductor device: A method for fabricating a semiconductor device includes the steps of forming a first ferroelectric film over a lower electrode, crystallizing the first ferroelectric film, forming a second ferroelectric film in an amorphous state over the first ferroelectric film so as to fill voids existing on a surface of the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080113454 - Processing systems and methods for semiconductor devices: Systems and methods for processing semiconductor devices are disclosed. A preferred embodiment comprises a processing method that includes providing a processing system including a first container and a second container fluidly coupled to the first container, the second container being adapted to receive and retain an overflow amount of a... Agent: Slater & Matsil LLP

20080113455 - Planar etching of dissimilar materials: A method of planar etching of dissimilar materials with a Focused Ion Beam (FIB) system such as the OptiFIB manufactured by Credence Systems. The method includes adjusting the selectivity between the two materials, which varies when the ratio of the assisting chemistry pressure to the ion dose rate changes. This... Agent: Deborah W. Wenocur

20080113456 - Process for protecting image sensor wafers from front surface damage and contamination: A method for protecting a semiconductor wafer fabricated for image sensing operation from contamination and/or physical damage to a front wafer surface during post-fabrication processing. The method includes applying a protective tape layer on the front surface of the semiconductor wafer in order to protect active light sensors fabricated thereon.... Agent: Scully, Scott, Murphy & Presser, P.c.

20080113457 - Method of chip manufacturing: A method of chip manufacturing, comprises of a design stage; a simulation stage; a foundry stage; a testing/packaging stage; a cutting stage; and a final coating stage. The present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips;... Agent: Birch Stewart Kolasch & Birch

20080113458 - Inspection method for protecting image sensor devices with front surface protection: A method for inspecting a semiconductor wafer fabricated for image sensing operation that has had a transparent protective tape layer applied to a front or active wafer surface. The method includes quantifying chip defects in the image sensor wafer that lie under the protective layer using automatic disposition equipment.... Agent: Scully, Scott, Murphy & Presser, P.c.

20080113459 - Method for dividing wafer, method for manufacturing silicon devices, and method for manufacturing liquid ejecting heads: A method for dividing a wafer into a plurality of chips is provided. The method includes providing recesses in a surface of the wafer at positions along boundaries between regions to become the individual chips, providing fragile portions having a predetermined width inside the wafer at positions along the boundaries... Agent: Workman Nydegger

20080113460 - Laser lift-off of sapphire from a nitride flip-chip: In a method for fabricating a flip-chip light emitting diode device, epitaxial layers are deposited on a sapphire growth substrate to produce an epitaxial wafer. A plurality of light emitting diode devices are fabricated on the epitaxial wafer. The epitaxial wafer is diced to generate a device die. The device... Agent: Fay Sharpe LLP

20080113461 - Method for manufacturing a lower substrate of a liquid crystal display device: A method for manufacturing a lower substrate of a liquid crystal display device is disclosed and more particularly, a method for manufacturing a color filter layer on a lower substrate is disclosed. This method is achieved by using a photosensitive insulating layer as a passivation layer or an overcoat of... Agent: Bacon & Thomas, Pllc

20080113462 - Method of manufacturing vertical light emitting device: Provided is a method of manufacturing a vertical light emitting device. The method of manufacturing the vertical light emitting device may include forming an emissive layer including a n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a substrate, forming a first trench dividing the emissive layer... Agent: Harness, Dickey & Pierce, P.L.C

20080113463 - Method of fabricating gan device with laser: A laser is used in fabricating a thin film gallium nitride (GaN) light emitting diode (LED). The laser has a wave length to be absorbed by GaN. The laser is used to define a GaN grain. And the laser is used to lift off a substrate after obtaining a bonding... Agent: Troxell Law Office Pllc

20080113464 - Asymmetric chalcogenide device: A semiconductor device with S-type negative differential resistance (e.g., phase change memory or threshold switch) may be formed with an asymmetric i-v curve. The asymmetric nature may be achieved by using a lower electrode formed of a semiconductor material such as doped amorphous or polycrystalline semiconductor. The resulting device may... Agent: Trop Pruner & Hu, Pc

20080113467 - Structure for and method of fabricating a high-speed cmos-compatible ge-on-insulator photodetector: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by... Agent: Scully, Scott, Murphy & Presser, P.c.

20080113468 - Electronic devices containing organic semi-conductors: The present invention relates to electronic devices comprising organic semiconductors whose content of halogens is less than 20 ppm. This increases the lifetime and the efficiency of the corresponding electronic devices, and these materials are thus better suited to use in organic electronic devices than materials with a higher halogen... Agent: Connolly Bove Lodge & Hutz, LLP

20080113465 - Angular rate sensor and method of manufacturing the same: An angular rate sensor 100 comprises a first structure 110 which includes a fixed portion 111 having an opening 114, a displacing portion 112 placed in the opening 114, and a connecting portion 113 adapted to connect the fixed portion 111 and the displacing portions 112; a second structure 130... Agent: Oliff & Berridge, Plc

20080113466 - Method of forming contact hole, method of manufacturing wiring board, method of manufacturing semiconductor device, and method of manufacturing electro-optical device: A method of forming a contact hole includes forming a first conductive layer patterned so as to serve as an electrode or a wiring on a substrate, forming an insulation layer on the substrate and the first conductive layer, inserting a cutting instrument into the insulation layer at an angle... Agent: Advantedge Law Group, Llc

20080113469 - Methods of fabricating a semiconductor device including a self-aligned cell diode: A method of fabricating a semiconductor device includes forming a conductive layer on a semiconductor substrate, forming an insulating layer on the conductive layer, forming a word line and isolation trenches by patterning the insulating layer and the conductive layer, forming an isolation layer that fills the isolation trenches, forming... Agent: Volentine & Whitt Pllc

20080113470 - Method of forming a wall structure in a microelectronic assembly: A method of forming a wall structure in a microelectronic assembly includes selectively depositing a flowable material on an upper surface of a first element in the microelectronic assembly, positioning a molding surface in contact with the deposited flowable material and controlling a distance between the upper surface of the... Agent: Tessera Lerner David Et Al.

20080113471 - Method of making multi-chip package with high-speed serial communications between semiconductor dice: A multi-chip package includes a package substrate. First and second semiconductor die are formed on the package substrate. The first and the second semiconductor die are configured to communicate with each other via a high-speed serial communications protocol.... Agent: Kathy Manke Avago Technologies Limited

20080113472 - Film and chip packaging process using the same: A film includes a removable base material, a resin layer and a plurality of arc elastomers. The resin layer is a partially-cured resin which is in a half-melting state with viscosity at a temperature higher than a first temperature and in a solid state without viscosity at a temperature lower... Agent: Reed Smith LLP

20080113473 - Method of manufacturing a thin-film transistor substrate: According to a method of manufacturing a thin-film transistor (TFT) substrate, a gate insulation layer, a semiconductor layer, an ohmic contact layer, and a data metal layer are sequentially formed on a substrate. A photoresist pattern is formed in a source electrode area and a drain electrode area. A data... Agent: F. Chau & Associates, Llc

20080113474 - Methods of forming semiconductor-on-insulating (soi) field effect transistors with body contacts: Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also... Agent: Myers Bigel Sibley & Sajovec

20080113475 - Thin film transistor array substrate and fabricating method thereof: A thin film transistor array substrate and a fabricating method are disclosed. A gate line and a data line cross each other and a thin film transistor (TFT) is provided at the intersection between the gate and data lines. A protective film covers the data line and the thin film... Agent: Brinks Hofer Gilson & Lione

20080113476 - Dual-plane complementary metal oxide semiconductor: Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface.... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080113477 - Fabricating method of complementary metal-oxide-semiconductor (cmos) image sensor: A complementary metal-oxide-semiconductor (CMOS) image sensor including a substrate, a p type well, a light emitting diode, a p type gate structure and a plurality of n type gate structures is provided. The substrate has a photo sensitive region and a transistor device region, and the p type well is... Agent: Jianq Chyun Intellectual Property Office

20080113478 - Recessed access device for a memory: Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess... Agent: Schwegman, Lundberg & Woessner, P.a.

20080113479 - Fabricating non-volatile memory with boost structures: A method for fabricating a non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or... Agent: Vierra Magen/sandisk Corporation

20080113480 - Method of manufacturing semiconductor device: A semiconductor substrate is covered with a resist mask and then an opening for exposing a whole upper surface of a polysilicon gate is formed by photo lithography and dry etching. Thereafter, nitrogen ions are implanted into the polysilicon gate through the opening. Implantation energy at this time is set... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080113481 - Capacitance dielectric layer, capacitor and forming method thereof: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits... Agent: J.c. Patents Suite 250

20080113482 - Method for enhancing field oxide: A CMOS device with polysilicon protection tiles is shown in FIG. 2. LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18, respectively. On the upper surface of the LOCOS regions 12.1, 12.2 are polysilicon tiles 14.1, 14.2, respectively. At the corner of the... Agent: Hiscock & Barclay, LLP

20080113484 - Method of manufacturing semiconductor device: When an isolation insulating film is formed, first, by thermal oxidation method, a silicon oxide film having a thickness of about 5 nm is formed. Next, a silicon nitride film having a thickness of about 3 nm to about 20 nm is formed. The silicon oxide film and the silicon... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080113483 - Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures: A method of forming staggered heights in a pattern layer of an intermediate semiconductor device structure. The method comprises providing an intermediate semiconductor device structure comprising a pattern layer and a first mask layer, forming first openings in the pattern layer, forming spacers adjacent to etched portions of the pattern... Agent: Trask Britt, P.c./ Micron Technology

20080113485 - Method of evaluating the uniformity of the thickness of the polysilicon gate layer: A method of evaluating the uniformity of the thickness of the polysilicon gate layer is provided. A substrate having a dense trenches area and a sparse trenches area is provided. A plurality of first trench isolation structures are formed in the sparse trenches area of the substrate and a plurality... Agent: Jianq Chyun Intellectual Property Office

20080113489 - Method for manufacturing semiconductor substrate: Hydrogen ions are implanted to a surface (main surface) of the single crystal Si substrate 10 at a dosage of 1.5×1017 atoms/cm2 or higher to form the hydrogen ion implanted layer (ion-implanted damage layer) 11. As a result of the hydrogen ion implantation, the hydrogen ion implanted boundary 12 is... Agent: Oliff & Berridge, Plc

20080113487 - Method of fabricating a semiconductor device: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080113488 - Method of fabricating a semiconductor device: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080113486 - Peeling apparatus and manufacturing apparatus of semiconductor device: An object is to eliminate electric discharge due to static electricity generated by peeling when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element. A substrate over which an element formation layer and a peeling layer are formed and a... Agent: Eric Robinson

20080113490 - Method for manufacturing semiconductor device: According to the present invention, there is provided a method for manufacturing a semiconductor device that includes preparing a first semiconductor substrate and a second semiconductor substrate, forming a first insulating film on a surface of the first semiconductor substrate, forming circuit elements on a first surface of the second... Agent: Young & Thompson

20080113491 - Euv pellicle with increased euv light transmittance: According to one exemplary embodiment, an extreme ultraviolet (EUV) pellicle for protecting a lithographic mask includes an aerogel film. The pellicle further includes a frame for mounting the aerogel film over the lithographic mask. The aerogel film causes the pellicle to have increased EUV light transmittance.... Agent: Farjami & Farjami LLP

20080113492 - Method for cutting protective tape of semiconductor wafer and apparatus for cutting the protective tape: A cutter blade movably in a radial direction of a wafer is pressed for biasing to an outer circumferential edge of the semiconductor wafer. Simultaneously, the pushing biasing force of the cutter blade is controlled constant with automatic regulation corresponding to a traveling speed variation of the cutter blade, so... Agent: Cheng Law Group, Pllc

20080113493 - Method, device and diffraction grating for separating semiconductor elements formed on a substrate by altering said diffraction grating: A method of separating semiconductor elements formed in a wafer of semiconductor material using a laser producing a primary laser beam, and an arrangement and diffraction grating used in the method. The at least one primary laser beam is split into a plurality of secondary laser beams using a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080113494 - Laser beam processing apparatus for processing semiconductor wafer in production of semiconductor devices, laser beam processing method executed therein, and such semiconductor wafer processed thereby: In a laser beam processing apparatus that processes a semiconductor wafer having a multi-layered wiring structure formed thereon, scribe lines defined thereon, and at least one alignment mark formed on any one of the scribe lines, a laser beam generator system generates a laser beam, and a movement system relatively... Agent: Young & Thompson

20080113495 - Method of construction of cte matching structure with wafer processing and resulting structure: A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern... Agent: Harrington & Smith, Pc

20080113496 - Method for heteroepitaxial growth of high-quality n-face gan, inn, and aln and their alloys by metal organic chemical vapor deposition: Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also... Agent: Gates & Cooper LLP Howard Hughes Center

20080113497 - Semiconductor device on gan substrate having surface bidirectionally inclined toward <1-100> and <11-20> directions relative to {0001} crystal planes: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1-100> direction lying in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080113498 - Variable resurf semiconductor device and method: Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20080113499 - Semiconductor device with mushroom electrode and manufacture method thereof: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080113500 - Method for fabricating semiconductor device including recess gate: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate having a field oxide layer, etching the substrate to form a recess by using the hard mask pattern, forming a first conductive layer over the recess and the hard mask pattern, planarizing the first... Agent: Lowe Hauptman Ham & Berner, LLP

20080113501 - Methods of forming semiconductor constructions: The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines... Agent: Wells St. John P.s.

20080113502 - Electronic device: An electronic device includes a first die that includes wires for bonding, a second die that includes an array of balls for bonding, and a substrate. The substrate includes bond sites for wires from the first die, and bond sites for the array of balls from the second die. The... Agent: Intel Corporation C/o Intellevate, Llc

20080113503 - Low fabrication cost, high performance, high reliability chip scale package: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is... Agent: Megica Corporation

20080113504 - Low fabrication cost, high performance, high reliability chip scale package: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is... Agent: Mou-shiung Lin

20080113505 - Method of forming a through-substrate via: A method for achieving a through-substrate via through a substrate having active circuitry on a first major surface begins by forming a hole into the substrate through the first major surface. The hole is lined with a conductive layer. A dielectric layer is deposited over the conductive layer. This deposition... Agent: Freescale Semiconductor, Inc. Law Department

20080113506 - Fabrication process of a semiconductor device: A method for fabricating a semiconductor device has forming an opening defined by an inner wall surface in an insulation film, covering said inner wall surface with a Cu—Mn alloy layer, depositing a first Cu layer over said Cu—Mn alloy layer without exposing said Cu—Mn alloy layer to the air,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080113507 - Poly filled substrate contact on soi structure: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080113508 - Method of fabricating metal interconnects using a sacrificial layer to protect seed layer prior to gap fill: Disclosed are embodiments of a method of forming metal interconnects using a sacrificial layer to protect a seed layer prior to metal gap fill. The sacrificial layer can prevent oxidation of the seed layer and perhaps oxygen migration to an underlying barrier layer. Other embodiments are described and claimed.... Agent: Intel Corporation C/o Intellevate, Llc

20080113509 - Polishing method and polishing device: Disclosed herein is a polishing method for polishing the end surface of a wafer by using a polishing tape, wherein the end surface of the wafer is polished in the condition where a polishing liquid containing an oxidizing agent is supplied to the end surface of the wafer.... Agent: Sonnenschein Nath & Rosenthal LLP

20080113510 - Semiconductor wafer fabricating method and semiconductor wafer mirror edge polishing method: There is provided a semiconductor wafer fabricating method comprising at least: a double-side polishing step of mirror-polishing a front surface and a back surface of a semiconductor wafer; and a mirror edge polishing step of mirror-polishing a chamfered part of the double-side-polished semiconductor wafer, wherein a protection film made of... Agent: Oliff & Berridge, Plc

20080113513 - Chemical mechanical planarization pad: A Chemical Mechanical Planarization (CMP) Pad. The CMP pad may be hydrophobic due to the incorporation of metal complexing agents. The CMP pad substantially retaining planarization characteristics throughout planarization applications. Shearing, hardness, wearing, water absorption and electrical characteristics of the CMP pad remain substantially constant during CMP applications.... Agent: Moore & Van Allen Pllc

20080113512 - Method of fabricating isolation layer of semiconductor device: A method of fabricating isolation layers of a semiconductor device is provided. The method includes depositing a pad oxide layer and a hard mask in sequence on a semiconductor substrate and patterning the pad oxide layer and the hard mask. Trenches may be formed by etching the substrate to a... Agent: Workman Nydegger

20080113511 - Method of forming fine patterns using double patterning process: A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of... Agent: Volentine & Whitt Pllc

20080113514 - Methods for the manufacture of notched trailing shields: Methods for improving within wafer and wafer to wafer yields during fabrication of notched trailing shield structures are disclosed. Ta/Rh CMP stop layers are deposited prior to planarization and notch formation to ensure a planar surface for trailing shield structures. These stop layers may be blanket deposited or patterened prior... Agent: D'arcy H. Lorimer

20080113515 - Methods of forming semiconductor devices: A method of forming a semiconductor device is provided. The method includes preparing a semiconductor substrate to include a cell region and a peripheral region and forming a first mask layer on the semiconductor substrate. First hard mask patterns that are configured to expose the first mask layer are formed... Agent: Myers Bigel Sibley & Sajovec

20080113516 - Selectivity control in a plasma processing system: A method in a plasma processing system for etching a feature through a given layer on a semiconductor substrate. The method includes placing the substrate in a plasma processing chamber of the plasma processing system. The method also includes flowing an etchant gas mixture into the plasma processing chamber, the... Agent: Ipsg, P.c.

20080113517 - Methods of fabricating semiconductor devices including selectively reacting reactant gases: A method of fabricating semiconductor devices with improved critical dimension (CD) uniformity is provided. The methods include forming photoresist patterns on an etching target layer, forming polymer layers on photoresist patterns on an etching target layer by selectively reacting a reactant gas with the photoresist patterns to provide different thicknesses... Agent: Myers Bigel Sibley & Sajovec

20080113518 - Wet etching method using ultraviolet light and method of manufacturing semiconductor device: A substrate supporting film to be etched is held on a rotating stage. Ultraviolet light having a wavelength of 200 nm or shorter radiated from first lamps irradiates the film in air, thereby removing an organic coatings from the film and making the surface of the film hydrophilic. A chemical... Agent: Leydig Voit & Mayer, Ltd

20080113519 - Method and apparatus for forming oxynitride film and nitride film, oxynitride film, nitride film, and substrate: Uniform oxynitride and nitride films can be formed by low-temperature and high-speed nitriding reaction not dependent on the nitriding time or nitriding temperature. A solid dielectric is provided on at least one of opposed surfaces of a pair of electrodes opposed to each other under a pressure of 300 (Torr)... Agent: Sughrue Mion, Pllc

20080113520 - Method of forming organic layer on semiconductor substrate: Disclosed relates to a method of coating or stacking an organic material to form an organic layer on a semiconductor substrate such as silicon, GaAs, etc. In the present invention, a polished semiconductor substrate is soaked in silanes, KOH, or a mixed solution of H2SO4 and H2O2. As a result,... Agent: Bruce E. Lilling Lilling & Lilling Pllc

20080113521 - Method of forming ultra-thin sin film by plasma cvd: A method of forming an ultra-thin SiN film includes: supplying a Si source gas into a reactor in which a substrate is placed on a susceptor; supplying an N source gas into the reactor at a flow rate which is at least 300 times that of the Si source gas;... Agent: Knobbe Martens Olson & Bear LLP

20080108153 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, includes forming a porous dielectric film above a substrate using a porous insulating material, forming an opening in the porous dielectric film, repairing film quality of the porous dielectric film on a surface of the opening by feeding a predetermined gas replacing a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080108154 - Apparatus and method for measuring chuck attachment force: An apparatus and method for measuring a chuck attachment force are provided. The apparatus is capable of measuring loads applied to a measurement substrate, while the measurement substrate is detached from a chuck, and precisely calculating necessary force through a process of comparing and analyzing values of the measured loads.... Agent: Ked & Associates, LLP

20080108156 - Method for fabricating led lamp and high-output led fabricated by using the method: A method for fabricating a light emitting diode lamp in a simplified procedure, and a high-output LED, that has a simple structure and can exhibit improvement in heat release property, fabricated by using the method which includes the steps of coating an insulating layer on a substrate and etching the... Agent: Cantor Colburn, LLP

20080108157 - Method for manufacturing a display device: There is provided a method for manufacturing a display device. The method includes the steps of: forming a bottom electrode for supplying a first charge, in individual pixels on a substrate; forming a pattern of a first light-emitting layer having a first-charge transport property above the bottom electrode in part... Agent: Sonnenschein Nath & Rosenthal LLP

20080108163 - Microelectromechanical system device and method for preparing the same for subsequent processing: A method for preparing a microelectomechanical system (MEMS) device for subsequent processing is disclosed. The method includes establishing an anti-stiction material on exposed surfaces of the MEMS device. The exposed surfaces include at least an interior surface of a chamber and an external surface of the MEMS device. The anti-stiction... Agent: Hewlett Packard Company

20080108164 - Sensor system and method: A sensor system and method for detecting the presence of one or more target substances reacting with one or more target recognition element types for producing an electrical charge detectable by a differential pair of field effect transistors that provide increased sensitivity by minimizing common mode effects on the differential... Agent: Morrison & Foerster LLP

20080108172 - Deterministic process for constructing nanodevices: A method is provided for constructing a nanodevice. The method includes: fabricating an electrode on a substrate; forming a nanogap across the electrode; dispersing a plurality of nanoobjects onto the substrate using electrophoresis; and pushing one of the nanoobjects onto the electrode using a tip of an atomic force microscope,... Agent: Harness, Dickey & Pierce, P.L.C

20080108173 - Organic light emission display and fabrication method of the same: An organic light emission display and a fabrication method thereof. According to one embodiment of the present invention, a fabrication method of an organic light emission display includes: forming a light emitting part on a first area of a substrate and a pad part on a second area of the... Agent: Christie, Parker & Hale, LLP

20080108155 - Method for evaluating dopant contamination of semiconductor wafer: The present invention provides a method for evaluating dopant contamination of a semiconductor wafer, wherein a resistivity of a bulk portion of the semiconductor wafer is measured by an eddy current method, a resistivity in a surface layer of the semiconductor wafer is measured by a surface photovoltage method, and... Agent: Oliff & Berridge, Plc

20080108158 - Light-emitting diode chip package body and packaging method thereof: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip... Agent: Rosenberg, Klein & Lee

20080108159 - Method for producing color-converting light-emitting device using electrophoresis: A method for producing a color-converting light-emitting device is provided that can prevent the deposition of elements caused by ion migration during an electrophoresis process used to deposit a phosphor layer on the light emitting device. An anode and a light-emitting device having a semiconductor light-emitting element are disposed in... Agent: Cermak Kenealy & Vaidya, LLP

20080108160 - Semiconductor light emitting device, its manufacturing method, semiconductor device and its manufacturing method: A semiconductor light emitting device made of nitride III-V compound semiconductors is includes an active layer made of a first nitride III-V compound semiconductor containing In and Ga, such as InGaN; an intermediate layer made of a second nitride III-V compound semiconductor containing In and Ga and different from the... Agent: Sonnenschein Nath & Rosenthal LLP

20080108161 - Method for manufacturing vertical light-emitting diode: A method for manufacturing a vertical light-emitting diode is described. In the method for manufacturing the vertical light-emitting diode, a sapphire substrate is provided. An illuminant epitaxial structure is formed on the sapphire substrate. Next, a first conductivity type electrode is formed on a surface of the illuminant epitaxial structure.... Agent: Daniel B. Schein, Ph.d., Esq., Inc.

20080108162 - Light-emitting device structure using nitride bulk single crystal layer: m

20080108165 - Anchors for microelectromechanical systems having an soi substrate, and method of fabricating same: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device having mechanical structures and anchors to secure the mechanical structures to the substrate. The anchors of the present invention are comprised... Agent: Kenyon & Kenyon LLP

20080108166 - Cmos image sensor providing uniform pixel exposure and method of fabricating same: An CMOS image sensor includes a photodiode region generating electrical charges in response to incident light-received thereat. In one example, the CMOS image sensor further includes first and second transfer gates adapted to prevent or substantially prevent the electrical charges from overflowing into a floating diffusion region or a storage... Agent: Volentine & Whitt Pllc

20080108167 - Solid state image pickup device and method of producing solid state image pickup dmce: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the... Agent: Robert J. Depke Lewis T. Steadman

20080108168 - Structure of image sensor module and method for manufacturing of wafer level package: An image sensor die comprises a substrate and an image sensor array formed over the substrate. Micro lens are disposed on the image sensor array. A protection layer is formed on the micro lens to prevent the micro lens from particle containment.... Agent: Kusner & Jaffe Highland Place Suite 310

20080108169 - Ultrathin module for semiconductor device and method of fabricating the same: An ultrathin module is provided for special types of semiconductor devices such as image sensor devices and micro-electro-mechanical system (MEMS) devices. In the module, a chip cover is directly attached to a semiconductor chip so as to protect a light-sensing area or mechanical elements of the chip. The chip cover... Agent: Volentine & Whitt Pllc

20080108170 - Cmos imager with cu wiring and method of eliminating high reflectivity interfaces therefrom: A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that... Agent: Scully, Scott, Murphy & Presser, P.c.

20080108171 - Release strategies for making transferable semiconductor structures, devices and device components: Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of... Agent: Greenlee Winner And Sullivan P C

20080108174 - Metal precursors for low temperature deposition and methods of forming a metal thin layer and manufacturing a phase-change memory device using the metal precursors: The present invention provides metal precursors for low temperature deposition. The metal precursors include a metal ring compound including at least one metal as one of a plurality of elements forming a ring. Methods of forming a metal thin layer and manufacturing a phase change memory device including use of... Agent: Myers Bigel Sibley & Sajovec

20080108175 - Method of forming a phase change layer and method of manufacturing a storage node having the phase change layer: A method of forming a phase change layer may include providing a bivalent first precursor having germanium (Ge), a second precursor having antimony (Sb), and a third precursor having tellurium (Te) onto a surface on which the phase change layer is to be formed. The phase change layer may be... Agent: Harness, Dickey & Pierce, P.L.C

20080108176 - Phase change memory and fabricating method thereof: A phase change memory including a phase change layer, a first electrode, and a porous dielectric layer formed with a plurality of pores. The porous dielectric layer is formed between the phase change layer and the first electrode. Therefore, the phase change layer may make contact with the first electrode... Agent: Rabin & Berdo, Pc

20080108177 - Semiconductor device: An exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more compounds of the formula AxBxOx, wherein each A is selected from the group of Cu, Ag, Sb, each B is selected from the group of Cu, Ag, Sb, Zn, Cd, Ga, In,... Agent: Hewlett Packard Company

20080108178 - Thermoplastic fluxing underfill method: A flip chip having solder bumps and an underfill that is thermoplastic and fluxing, as well as methods for making such a device. The resulting device is well suited for a simple one-step application to a printed circuit board, thereby simplifying flip chip manufacturing processes.... Agent: Senniger Powers LLP

20080108179 - Stackable molded packages and methods of making the same: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least... Agent: Freescale Semiconductor, Inc. Law Department

20080108180 - Nanoparticle filled underfill: The invention provides electronic articles and methods of making said articles. The electronic articles comprise an electronic component bonded and electrically connected to a substrate using an underfill adhesive comprising the reaction product of a thermosetting resin, curing catalyst, and surface-treated nanoparticles that are substantially spherical, non-agglomerated, amorphous, and solid.... Agent: 3m Innovative Properties Company

20080108181 - Method for attaching integrated circuit component to a substrate: An integrated circuit component is attached to a substrate by dispensing a controlled amount of photo-activatable anisotropic conductive adhesive (ACA) at a desired location on the substrate, exposing the dispensed ACA to an electromagnetic radiation source to initiate a chemical reaction in the ACA, aligning the component with the substrate... Agent: Heslin Rothenberg Farley & Mesiti Pc

20080108182 - Method for fabricating semiconductor package free of substrate: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the... Agent: Edwards Angell Palmer & Dodge LLP

20080108183 - Method for manufacturing dynamic random access memory: The present invention has an object to provide a method for manufacturing a dynamic random access memory capable of reducing a defect rate even if the memory has a large packing density. The method of the present invention is a method for manufacturing a dynamic random access memory having memory... Agent: Sughrue Mion, Pllc

20080108184 - Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers: A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising... Agent: Scully, Scott, Murphy & Presser, P.c.

20080108186 - Method of providing protection against charging damage in hybrid orientation transistors: In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction... Agent: International Business Machines Corporation Dept. 18g

20080108185 - Multilayer silicon over insulator device: An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multilayer SOI device has a first... Agent: Greenblum & Bernstein, P.L.C

20080108187 - Thin film transistor array panel and method for fabricating the same: The present invention relates to a TFT array panel and a fabricating method thereof. A gate insulating layer and a passivation layer are formed by printing organic insulating material in order to simplify the fabricating process. The inventive TFT panel includes an insulating substrate, and a gate wire formed on... Agent: F. Chau & Associates, Llc

20080108188 - T-gate forming method for high electron mobility transistor and gate structure thereof: A T-gate forming method for a high electron mobility transistor includes the steps of: coating a first, a second and a third resist, each having an electron beam sensitivity different from each other, on a semiconductor substrate; performing a first exposure process by using an electron beam on the semiconductor... Agent: Bacon & Thomas, Pllc

20080108190 - Sic mosfets and self-aligned fabrication methods thereof: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer.... Agent: General Electric Company Global Research

20080108189 - Transistor having field plate: A method for forming a transistor device having a field plate. The method includes forming a structure having a source, a drain, and a Tee gate. A photo-resist layer is formed on the structure with an opening therein only the one of two distal ends of the Tee gate. A... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20080108191 - Memory device with surface-channel peripheral transistors: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The... Agent: Texas Instruments Incorporated

20080108192 - Method for fabricating non-volatile memory cells: A method for fabricating non-volatile memory cells is provided. The method includes providing a substrate, forming a first dopant region in the substrate, forming a second dopant region in the first dopant region, growing a first isolation region over a first portion of the substrate, the first dopant region, and... Agent: Sawyer Law Group LLP

20080108193 - Cu annealing for improved data retention in flash memory devices: Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than... Agent: Mcdermott Will & Emery LLP

20080108194 - Memory device and manufacturing method thereof: A memory device comprising a substrate, a first insulation layer, a charge storage layer, a second insulation layer, a gate electrode layer and source/drain regions is provided. The forbidden gap of the substrate is larger than the forbidden gap of silicon. The first insulation layer is disposed over the substrate.... Agent: J.c. Patents

20080108195 - Fabrication process of memory cell: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region... Agent: Jianq Chyun Intellectual Property Office

20080108196 - High performance fet devices and methods thereof: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to... Agent: George Sai-halasz

20080108197 - Method of fabricating non-volatile flash memory device having at least two different channel concentrations: In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding... Agent: Lee & Morse, P.c.

20080108198 - Transistor structures and methods for making the same: Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, SnO2, or In2O3. A gate insulator layer comprising a substantially transparent material is... Agent: Klarquist Sparkman, LLP

20080108199 - Method of forming an integrated circuit including a transistor: A method of forming an integrated circuit including a transistor is disclosed. One embodiment provides an active zone formed in a semiconductor substrate. Trench insulator structures and cell insulator structures are adjacent to the active zone. A gate electrode is formed including a buried portion. The buried portion is formed... Agent: Dicke, Billig & Czaja

20080108200 - Process for self-aligned manufacture of integrated electronic devices: A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer.... Agent: Graybeal, Jackson, Haley LLP

20080108201 - Configurable integrated circuit capacitor array using via mask layers: A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in... Agent: Womble Carlyle Sandridge & Rice, Pllc

20080108202 - Precision high-frequency capacitor formed on semiconductor substrate: A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20080108203 - Multi-layer electrode and method of forming the same: An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive... Agent: Siemens Corporation Intellectual Property Department

20080108204 - Amorphization/templated recrystallization method for hybrid orientation substrates: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first... Agent: Scully, Scott, Murphy & Presser, P.c.

20080108205 - Semiconductor device and method for manufacturing the same: The present invention provides a semiconductor device formed over an insulating substrate, typically a semiconductor device having a structure in which mounting strength to a wiring board can be increased in an optical sensor, a solar battery, or a circuit using a TFT, and which can make it mount on... Agent: Eric Robinson

20080108206 - Method for manufacturing semiconductor device: A layer including a semiconductor film is formed over a glass substrate and is heated. A thermal expansion coefficient of the glass substrate is greater than 6×10−7/° C. and less than or equal to 38×10−7/° C. The heated layer including the semiconductor film is irradiated with a pulsed ultraviolet laser... Agent: Eric Robinson

20080108207 - Silicon semiconductor substrate and production method thereof: The present invention can provide a silicon semiconductor substrate used for and epitaxial wafer, in which uniform and high-level gettering ability is obtained irrespective of slicing positions from a silicon single crystal while generation of epitaxial defects can be suppressed, by doping carbon or carbon along with nitrogen during a... Agent: Clark & Brody

20080108208 - Techniques for forming shallow junctions: Techniques for forming shallow junctions are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for forming shallow junctions. The method may comprise generating an ion beam comprising molecular ions based on one or more materials selected from a group consisting of: digermane (Ge2H6), germanium... Agent: Hunton & Williams LLP/varian Semiconductor, Equipment Associates, Inc.

20080108209 - Method of forming pn junctions including a post-ion implant dynamic surface anneal process with minimum interface trap density at the gate insulator-silicon interface: A method of forming transistors on a wafer includes forming gates over gate insulators on a surface of the wafer and ion implanting dopant impurity atoms into the wafer to form source and drain regions aligned on opposite sides of each gate. The wafer is then annealed by pre-heating the... Agent: Law Office Of Robert M. Wallace

20080108210 - Low temperature process for depositing a high extinction coefficient non-peeling optical absorber for a scanning laser surface anneal of implanted dopants: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature,... Agent: Law Office Of Robert M. Wallace

20080108211 - Method for producing semiconductor device: A method for producing a semiconductor device which includes: a semiconductor base, a hetero semiconductor region made of a semiconductor material different in band gap from a semiconductor material for the semiconductor base, and so configured as to form a hetero junction in combination with the semiconductor base, a gate... Agent: Foley And Lardner LLP Suite 500

20080108212 - High voltage vertically oriented eeprom device: Apparatus and a method for adding non-volatile memory cells with trench-filled vertical gates to conventional MOSFET surface devices that have their drain and source regions horizontally positioned near the top surface of a substrate. A surface MOSFET device is used as a structural platform to which is added a vertical... Agent: Schneck & Schneck

20080108213 - Multi-layer nonvolatile memory devices and methods of fabricating the same: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The... Agent: Myers Bigel Sibley & Sajovec

20080108215 - Integrated circuit interconnect lines having reduced line resistance: The present invention provides integrated circuit fabrication methods and devices wherein shunted interconnect lines are formed. The shunted interconnect lines are formed in a dielectric stack comprising (1) a first dielectric layer having dense interconnect lines that form a first dielectric layer dense line subset and (2) a sequentially deposited... Agent: Applied Materials, Inc.

20080108216 - Method for forming contact in semiconductor device: A method for forming a contact in a semiconductor device includes opening a contact hole exposing a surface of a substrate, performing a first post treatment to form a rough portion at a bottom surface of the contact hole, and performing a second post treatment. The first post treatment includes... Agent: Townsend And Townsend And Crew, LLP

20080108214 - Threshold voltage targeting in carbon nanotube devices and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming at least one metal source/drain on a gate dielectric, wherein the at least one metal source/drain is adjacent to a channel region, wherein the channel region comprises at least one carbon nanotube.... Agent: Intel Corporation C/o Intellevate, Llc

20080108217 - Esd protection for passive integrated devices: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating... Agent: Ingrassia Fisher & Lorenz, P.c. (fs)

20080108218 - Low viscosity precursor compositions and methods for the deposition of conductive electronic features: A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low... Agent: Patent Administrator Cabot Corporation

20080108219 - Semiconductor interconnect and method of making same: An integrated circuit interconnect structure includes a conductive line, a first barrier layer disposed on a bottom surface of conductive line, a second barrier layer disposed on the top surface of the conductive line, and an interlevel dielectric surrounding the conductive line.... Agent: Slater & Matsil LLP

20080108220 - Interconnect structure with a barrier-redundancy feature: An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect... Agent: Scully, Scott, Murphy & Presser, P.c.

20080108221 - Microprobe tips and methods for making: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include... Agent: Microfabrica Inc. Att: Dennis R. Smalley

20080108222 - Method for forming pattern in semiconductor device: A method for forming a pattern in a semiconductor device includes forming an etch target layer comprising metal over a substrate. A hard mask pattern is formed over the etch target layer. The etch target layer is etched to form a pattern such that a line width of the etch... Agent: Townsend And Townsend And Crew, LLP

20080108223 - Integrated etch and supercritical co2 process and chamber design: A method and apparatus involve providing a substrate having a dielectric layer formed thereon, forming a photoresist mask over the dielectric layer, the photoresist mask defining an opening, etching the dielectric layer through the at least one opening in the photoresist mask, treating a portion of the photoresist mask with... Agent: Haynes And Boone, LLP

20080108224 - Patterning methods: A patterning method includes providing a substrate having an insulator layer established thereon. A silicon layer is established on the insulator layer. A mask is established on at least a portion of the silicon layer. Portions of the silicon layer and the insulator layer are removed to expose portions of... Agent: Hewlett Packard Company

20080108225 - Low temperature aerosol deposition of a plasma resistive layer: Embodiments of the present invention provide a method for low temperature aerosol deposition of a plasma resistive layer on semiconductor chamber components/parts. In one embodiment, the method for low temperature aerosol deposition includes forming an aerosol of fine particles in an aerosol generator, dispensing the aerosol from the aerosol generator... Agent: Patterson & Sheridan, LLP - - Appm/tx

20080108226 - Method of fabricating thin film transistor substrate and thin film transistor substrate produced using the same: A method of fabricating a thin film transistor substrate includes forming a gate wiring on an insulating substrate and forming a gate insulating layer on the gate wiring; performing a first hydrogen plasma treatment with respect to the gate insulating layer; forming a first active layer with a first thickness... Agent: Cantor Colburn, LLP

20080108227 - Method for producing single electron semiconductor element: The present invention provides a method for production of a single electron semiconductor element (SET) in which a quantum dot is selectively arranged in a nano gap between fine electrodes, whereby the product yield is significantly improved, leading to excellent practical applicability. The method for production of SET of the... Agent: Mcdermott Will & Emery LLP

20080108228 - Device having enhanced stress state and related methods: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device... Agent: Hoffman, Warnick & D'alessandro Llc

20080108229 - Manufacturing method of semiconductor device: In a manufacturing process of a semiconductor device, a manufacturing technique of a semiconductor device by which a lithography step that uses a photoresist is simplified is provided. A manufacturing cost is reduced and throughput is improved. An irradiation object is formed over a substrate by sequentially stacking a first... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080102538 - Apparatus and method for controlling relative particle concentrations in a plasma: An apparatus for controlling a plasma etching process includes plasma control structure that can vary a size of a plasma flow passage, vary a speed of plasma flowing through the plasma flow passage, vary plasma concentration flowing through the plasma flow passage, or a combination thereof.... Agent: Haynes And Boone, LLP

20080102539 - Wire-bonding method for wire-bonding apparatus: A wire-bonding method for a wire-bonding apparatus is provided. The wire-bonding apparatus includes at least a first wire-bonder and a second wire-bonder for respectively bonding at least several first chips in a first region and several second chips in a second region on a substrate simultaneously. The wire-bonding method includes... Agent: Bacon & Thomas, PLLC

20080102540 - Technique for forming a passivation layer without a terminal metal: By determining at least one surface characteristic of a passivation layer stack used for forming a bump structure, the situation after the deposition and patterning of a terminal metal layer stack may be “simulated,” thereby providing the potential for using well-established bump manufacturing techniques while nevertheless significantly reducing process complexity... Agent: Williams, Morgan & Amerson

20080102541 - Method for manufacturing light emitting diode chip and light emitting diode light source module: The present invention relates to a method for manufacturing a light emitting diode (LED) chip for a chip on board and a method for manufacturing an LED light source module in a chip on board fashion. The method of the present invention includes forming a plurality of LED chips on... Agent: F. Chau & Associates, LLC

20080102544 - Optical module producing method and apparatus: An optical module is produced by coating, with respect to a substrate having a substrate surface provided with terminal pads and landing pads a solder material on the terminal pads, mounting an optical element package having terminals and a flat top surface on the substrate using the landing pads so... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080102546 - Method of manufacturing semiconductor laser device including light shield plate: Provided is a method of manufacturing a semiconductor laser device having a light shield film comprising: forming a light emission structure by depositing a first clad layer, an active layer and a second clad layer on a substrate; depositing a light shield film and a protection film on the light... Agent: Harness, Dickey & Pierce, P.L.C

20080102549 - Method of manufacturing semiconductor light emitting device: Provided is a method of manufacturing semiconductor light emitting devices including: forming light emitting structures by sequentially depositing a first material layer, an active layer and a second material layer; forming the roughness pattern on a region of the bottom of a substrate except at least a cleaving region for... Agent: Harness, Dickey & Pierce, P.L.C

20080102552 - Wafer level method of locating focal plane of imager devices: A method is disclosed which includes providing an imager substrate comprised of at least one imager device, providing a transparent substrate, forming a plurality of standoff structures on one of the imager substrate and the transparent substrate, the standoff structures having a width, forming an adhesive material having an initial... Agent: Williams, Morgan & Amerson

20080102553 - Stabilizing an opened carbon hardmask: A process for passivating a carbon-based hard mask, for example, of hydrogenated amorphous carbon, overlying an oxide dielectric which is to be later etched according to the pattern of the hard mask. After the hard mask is photo lithographically etched, it is exposed to a plasma of a hydrogen-containing reducing... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20080102557 - Method of forming an isolation layer and method of manufacturing an image device using the same: A method of forming an isolation layer includes forming mask pattern structure on a substrate to partially expose the substrate, etching the substrate using the mask pattern as an etching mask to form a trench, forming an impurity diffusion region at an inner face of the trench, and filling the... Agent: Lee & Morse, P.C.

20080102556 - Method of manufacturing complementary metal oxide semiconductor image sensor: A method of manufacturing a CMOS image sensor manufacturing includes forming a plurality of metal pads over a semiconductor substrate; electrically connecting the metal pads to lower conductive film patterns of multi-layer metal wires using metal contacts; depositing an insulation film over the metal pads; patterning the insulation film to... Agent: Sherr & Nourse, PLLC

20080102558 - Closely spaced, high-aspect extruded gridlines: Closely spaced, high aspect-ratio gridline structures are formed on the surface of a substrate using two or more co-extrusion heads that co-extrude gridline material and sacrificial material such that the deposited gridline material is compressed between opposing portions of the sacrificial material. The co-extrusion heads include three-channel cavity structures that... Agent: Bever, Hoffman & Harms, LLP

20080102559 - Electronic devices: o

20080102542 - Wafer processing method: An inspection step for inspecting the cut state of a wafer that has been cut such as the state of the width of a cut groove, the state of a chip and the like is performed during cutting of a wafer held by another chuck table by making use of... Agent: Greer, Burns & Crain

20080102543 - Increasing an electrical resistance of a resistor by oxidation: A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor... Agent: Schmeiser, Olsen & Watts

20080102547 - Method of fabricating field emission array type light emitting unit: A method of fabricating a field emission array type light emitting unit that includes a rear substrate including a plurality of cathodes and a plurality of carbon nanotube emitters on a front side, a front substrate including a plurality of anodes and a phosphor layer on a rear side, wherein... Agent: Robert E. Bushnell

20080102545 - Method of forming light-emitting element: An object of the present invention is to provide a method of forming a light-emitting element at a lower cost than a conventional cost with suppressing the deterioration of the substrate due to thermal distortion in comparison with a conventional method of recycling a substrate and further having an effect... Agent: Morgan & Finnegan, L.L.P.

20080102548 - Liquid crystal display device: In a liquid crystal display device which performs image display by controlling a liquid crystal layer by a lateral electric field that is parallel with a substrate, the lateral electric field is formed by a black matrix and a pixel electrode. That is, a common electrode and a black matrix... Agent: Fish & Richardson P.C.

20080102550 - Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor: Provided is a thin film transistor that may be manufactured using Metal Induced Crystallization (MIC) and method for fabricating the same. Also provided is an active matrix flat panel display using the thin film transistor, which may be created by forming a crystallization inducing metal layer below a buffer layer... Agent: H.c. Park & Associates, PLC

20080102551 - Cmos image sensor and method of fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. The image sensor includes a blocking layer protecting a photodiode at a diode region. The blocking layer is formed to cover a top of the diode region and extended to an active region so as to cover... Agent: F. Chau & Associates, LLC

20080102555 - Color filter of image sensor, image sensor, and method for manufacturing the image sensor: A color filter of an image sensor, an image sensor and a method for manufacturing the image sensor are disclosed, wherein shapes of respective unit color cells closely form various color patterns, such as a red color pattern, a green color pattern and a blue color pattern, within each unit... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080102554 - Solid state image pickup device and method of producing solid state image pickup device: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the... Agent: Robert J. Depke Lewis T. Steadman

20080102560 - Method of forming phase change memory devices in a pulsed dc deposition chamber: A phase change memory including an ovonic threshold switch is formed using a pulsed direct current (DC) deposition chamber using pulsed DC. Pulsed DC is used to deposit a chalcogenide film. Pulsed DC may be also used to deposit a carbon film.... Agent: Seed Intellectual Property Law Group PLLC

20080102561 - Methods of manufacturing printed circuit board assembly: Methods of manufacturing printed circuit board assemblies include placing a semiconductor chip having a plurality of lead terminals on a board formed with a plurality of solder lands at its surface such that each of the plurality of lead terminals is in touch with a corresponding one of the solder... Agent: Schlumberger K.k.

20080102562 - Method of making multi-chip electronic package with reduced line skew: A method of making an electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20080102563 - Non-pull back pad package with an additional solder standoff: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which... Agent: Texas Instruments Incorporated

20080102564 - Method for cooling a semiconductor device: A semiconductor device comprises a semiconductor die, first and second electrically-conductive leads and first and second thermal elements. The die comprises first and second surfaces. The first lead is held in contact with the first surface of the die by a compressive force. The first thermal element is held in... Agent: Alston & Bird, LLP

20080102565 - Substrate with lossy material insert: In one embodiment, the present invention includes a semiconductor package with lossy material inserts. The lossy material inserts may reduce electronic noise such as package resonance. Other embodiments are described and claimed.... Agent: Trop Pruner & Hu, PC

20080102566 - Multiple layer and crystal plane orientation semiconductor substrate: A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer,... Agent: Schmeiser, Olsen & Watts

20080102567 - Method for making thin film transistor: A method for making a thin film transistor (TFT) is provided. A mask is first formed on the backside of a substrate, and is used to fabricate a gate, source, and drain of the transistor by backside exposure, such that the source and drain can be self-aligned with the gate... Agent: Jianq Chyun Intellectual Property Office

20080102568 - Soi bipolar transistors with reduced self heating: A method for constructing a bipolar transistor comprising a collector, a base and an emitter, all located over a substrate, the method including steps of: creating a collector layer over the substrate; etching a path through the collector layer to the substrate; and filling the path with a heat-conductive material.... Agent: Michael Buchenhorner, P.A.

20080102569 - Method of fabricating vertical body-contacted soi transistor: A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region... Agent: International Business Machines Corporation Dept. 18g

20080102570 - Fin field emission transistor apparatus and processes: A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree... Agent: Schwegman, Lundberg & Woessner, P.A.

20080102571 - Methods for fabricating a stress enhanced mos transistor: Methods are provided for fabricating a stress enhanced MOS transistor. One such method comprises the steps of depositing and patterning a layer of sacrificial material to form a dummy gate electrode and replacing the dummy gate electrode with a stressed gate electrode. After the stressed gate electrode has been formed... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080102572 - Manufacturing method of semiconductor device: The present invention provides a method of manufacturing a semiconductor device, which is simple in manufacturing process and easy to control formed positions of a tensile film and a compressive film and their thicknesses. An n-type MOSFET and a p-type MOSFET are formed on a semiconductor substrate, and the tensile... Agent: Rabin & Berdo, PC

20080102573 - Cmos device with raised source and drain regions: A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in... Agent: Slater & Matsil, L.L.P.

20080102574 - Manufacturing method of semiconductor device: A manufacturing method of a CMOS semiconductor device includes using, in an nMOS, spike RTA (first annealing) together with ultra-rapid rising/falling temperature annealing (second annealing) whose temperature increase/decrease rate is higher than that of the spike RTA, and applying the ultra-rapid rising/falling temperature annealing (second annealing) alone in a pMOS,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080102575 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming an insulating layer, a first conductive layer, a dielectric layer and a capping conductive layer over a semiconductor substrate in which a cell region is defined. The capping conductive layer and the dielectric layer is etched to form contact holes in... Agent: Townsend And Townsend And Crew, LLP

20080102576 - Semiconductor device and manufacturing method thereof: A p-type collector region of an IGBT and an n-type cathode region of a free wheel diode are alternately formed in a second main surface of a semiconductor substrate. A back electrode is formed on the second main surface so as to be in contact with both of the p-type... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080102578 - Manufacturing method for an integrated semiconductor structure: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure. The method comprises the steps of: forming a peripheral circuitry in a peripheral device region, said peripheral circuitry comprising a peripheral transistor at least partially formed in said semiconductor substrate and having a... Agent: Eschweiler & Associates LLC

20080102577 - Method for preparing a trench capacitor structure: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a buried bottom electrode on the lower outer surface of the trench. A dielectric layer is formed to cover an inner sidewall of the trench, and a plurality of deposition processes... Agent: Wpat, PC Intellectual Property Attorneys

20080102579 - Method of forming isolation layer of semiconductor device: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second... Agent: Townsend And Townsend And Crew, LLP

20080102580 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures... Agent: Jianq Chyun Intellectual Property Office

20080102581 - High-voltage vertical transistor with a multi-gradient drain doping profile: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer.... Agent: The Law Offices Of Bradley J. Bereznak

20080102582 - Manufacturing method of a super-junction semiconductor device: A manufacturing method for a super-junction semiconductor device is disclosed. The methods includes a first step of depositing, on a low-resistivity semiconductor substrate of one conductivity type, at least an epitaxial layer of the one conductivity type which is to become a drift layer; a second step of forming a... Agent: Rossi, Kimms & Mcdowell LLP.

20080102583 - Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to si, sige and strained silicon schemes: A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by... Agent: Lsi Corporation

20080102584 - Structure and method for improved heat conduction for semiconductor devices: A thermally conductive structure for a semiconductor integrated circuit and a method for making the structure. The structure comprises one or more vertical and/or horizontal thermally conductive elements disposed proximate a device for improving thermal conductivity from the device to a substrate of the integrated circuit. In one embodiment a... Agent: Hitt Gaines, PC Lsi Corporation

20080102585 - Method of manufacturing silicon carbide semiconductor device: A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate.... Agent: Posz Law Group, PLC

20080102586 - Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels: Integrated circuit field effect transistors are manufactured by forming a pre-active pattern on a surface of a substrate, while refraining from doping the pre-active pattern with phosphorus. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the... Agent: Myers Bigel Sibley & Sajovec

20080102587 - Method of manufacturing high voltage device: A method of manufacturing a high voltage device includes forming a junction region in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A portion of the insulating layer is etched so that the junction region is exposed. Arsenic is implanted into the exposed junction region to... Agent: Townsend And Townsend And Crew, LLP

20080102588 - Method for forming mos transistor: A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to... Agent: North America Intellectual Property Corporation

20080102590 - Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed... Agent: Williams, Morgan & Amerson

20080102589 - Method of manufacturing semiconductor device: A method for improved manufacturing stability of transistors having silicide layers is provided. A gate electrode 105 and a side wall insulating film that covers a side surface of the gate electrode are formed over the device-forming surface of a silicon substrate 101. A source/drain region 109 is formed in... Agent: Mcginn Intellectual Property Law Group, PLLC

20080102591 - Method of manufacturing silicon carbide semiconductor device: A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate.... Agent: Posz Law Group, PLC

20080102592 - Method for manufacturing bipolar transistor: A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity in the first well to form a third well; forming and... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080102593 - Method for fabricating a semiconductor structure: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions... Agent: Dicke, Billig & Czaja

20080102594 - Method for forming semiconductor memory capacitor without cell-to-cell bridges: A capacitor is formed by forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate. A metal storage node is formed on the surface of each of the storage node holes in the mold insulating layer. The mold insulating layer is removed by performing... Agent: Ladas & Parry LLP

20080102595 - Etching method for manufacturing semiconductor device: A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles... Agent: Marger Johnson & Mccollom, P.C.

20080102596 - Methods of forming semiconductor structures: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy... Agent: Wells St. John P.s.

20080102597 - Method for preparing a gate oxide layer: A method for preparing a gate oxide layer first forms a mask layer including at least one opening on a semiconductor substrate, and forms a trench in the semiconductor substrate below the opening, wherein the trench surrounds an active area. The opening is enlarged to expose a portion of the... Agent: Wpat, PC Intellectual Property Attorneys

20080102598 - Iii-nitride wafer fabrication: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.... Agent: Ostrolenk Faber Gerb & Soffen

20080102599 - Reduced leakage interconnect structure: An improved semiconductor device interconnect structure comprising a dielectric layer recessed with respect to the conductive interconnect features. This structure and method reduces embedded metallic residues from CMP scratches and metal cap applications and provides improved mechanical integrity at the capping layer/liner/dielectric interface.... Agent: International Business Machines Corporation Dept. 18g

20080102600 - Manufacturing method of high voltage semiconductor device: Disclosed is a semiconductor device, and more particularly, a manufacturing method of a high voltage semiconductor device. The method includes: forming a semiconductor substrate having a key area for an alignment key, a low voltage area for a low voltage device, and a high voltage area for a high voltage... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080102601 - Method for producing a semiconductor substrate: This invention relates to a method for producing a substrate by transferring a layer of a material from a donor substrate to a support substrate, and then by removing a part of the layer of material to form the thin layer. The step of removing a part of the layer... Agent: Winston & Strawn LLP Patent Department

20080102602 - Structure of strained silicon on insulator and method of manufacturing the same: Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO2 layer.... Agent: Buchanan, Ingersoll & Rooney PC

20080102603 - Method for producing direct bonded wafer and direct bonded wafer: A method for producing a direct bonded wafer comprising: forming a thermal oxide film or a CVD oxide film on a surface of at least one of a bond wafer and a base wafer, and bonding the wafer to the other wafer via the oxide film; subsequently thinning the bond... Agent: Oliff & Berridge, PLC

20080102604 - Electrical die contact structure and fabrication method: A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top... Agent: Beyer Weaver LLP

20080102605 - Method and apparatus for forming a silicon wafer: A furnace for growing a ribbon crystal has a channel for growing a ribbon crystal at a given rate in a given direction, and a separating mechanism for separating a portion from the growing ribbon crystal. At least a part of the separating mechanism moves at about the given rate... Agent: Bromberg & Sunstein LLP

20080102606 - Wafer dividing method and apparatus: In the case of cutting streets on the rear surface of a wafer by laser beam irradiation, even if the wafer is variously doped or thermally-treated, the streets of a wafer front surface can accurately be detected and cut. Infrared light is emitted from an infrared light source to the... Agent: Greer, Burns & Crain

20080102607 - Iii-v compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same: A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer... Agent: Freescale Semiconductor, Inc. Law Department

20080102609 - Method for producing a wired circuit board: A method for producing a wired circuit board includes the steps of preparing a wired circuit board including an insulating layer and a conductive pattern having a wire covered with the insulating layer and a terminal portion exposed from the insulating layer, and forming a semiconductive layer on a surface... Agent: Akerman Senterfitt

20080102608 - Producing method of wired circuit board: A producing method of a wired circuit board includes the step of preparing a wired circuit board including an insulating layer and a conductive pattern having a wire covered with the insulating layer and a terminal portion exposed from the insulating layer; and the step of forming a semiconductive layer... Agent: Akerman Senterfitt

20080102610 - Method of controlling stress in gallium nitride films deposited on substrates: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial... Agent: Gates & Cooper LLP Howard Hughes Center

20080102611 - Method for fabricating a polysilicon layer having large and uniform grains: An exemplary method for fabricating a polysilicon layer includes the following steps. A substrate (10) is provided and an amorphous silicon layer (12) is formed over the substrate. An excimer laser generator (13) for generating a pulse excimer laser beams collectively having the shape of a generally rectangular shaft is... Agent: Wei Te Chung Foxconn International, Inc.

20080102612 - Silicided polysilicon spacer for enhanced contact area: An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact... Agent: Law Office Of Delio & Peterson, LLC.

20080102613 - Controlled composition using plasma-enhanced atomic layer deposition: Metallic-compound films are formed by plasma-enhanced atomic layer deposition (PEALD). According to preferred methods, film or thin film composition is controlled by selecting plasma parameters to tune the oxidation state of a metal (or plurality of metals) in the film. In some embodiments, plasma parameters are selected to achieve metal-rich... Agent: Knobbe, Martens, Olsen & Bear LLP

20080102614 - Method for forming semiconductor device: A method for forming a semiconductor device is provided. More specifically, a method for forming a bulb-shaped portion of a bulb-shaped recess gate is provided to overcome an etching process margin reduction caused by a spacer oxide film formed on sidewalls of a recess and thickly laminated to a lower... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080102615 - Method of forming semiconductor device: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride... Agent: Marger Johnson & Mccollom, P.C.

20080102616 - Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate... Agent: Frommer Lawrence & Haug

20080102617 - Method of fabricating flash memory device: A method of fabricating a flash memory device is disclosed herein. The method of fabricating a flash memory device includes the steps of forming a gate insulating film, a first conductive film and a nitride film over a semiconductor substrate in which a cell region and a peri region are... Agent: Marshall, Gerstein & Borun LLP

20080102619 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes providing a semiconductor substrate in which a floating gate pattern is formed. A dielectric layer, a conductive layer for a control gate, a tungsten silicide layer, a first silicon oxynitride layer, a hard mask layer, a second silicon oxynitride layer and an... Agent: Townsend And Townsend And Crew, LLP

20080102618 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is provided. A first spacer is formed over a semiconductor substrate including an isolation layer that defines an active region. A part of the first spacer is removed to expose part of the active region. The exposed active region is etched to form... Agent: Townsend And Townsend And Crew, LLP

20080102620 - Solder ball mounting method and solder ball mounting substrate manufacturing method: A solder resist having first opening portions on positions corresponding to electrodes and a second opening portion on a mask providing position is formed on the substrate. A flux mask whose thickness is substantially same as the solder resist is arranged in the second opening portion and then a flux... Agent: Rankin, Hill & Clark LLP

20080102622 - Method of forming metal line in semiconductor device: A method of forming a metal line in a semiconductor device, including the steps of forming a metal line in a semiconductor device in which dummy patterns are formed on a dummy region by using non-metal material when a metal line is formed through a damascene process to prevent a... Agent: Marshall, Gerstein & Borun LLP

20080102621 - Methods of fabricating a barrier layer with varying composition for copper metallization: Various embodiments provide improved processes and systems that produce a barrier layer with decreasing nitrogen concentration with the increase of film thickness. A barrier layer with decreasing nitrogen concentration with film thickness allows the end of barrier layer with high nitrogen concentration to have good adhesion with a dielectric layer... Agent: Martine Penilla & Gencarella, LLP

20080102623 - Semiconductor device manufacturing method: To provide a semiconductor device manufacturing method in which, when a silicon nitride film is formed as an anti-oxidation film on bit wires formed from tungsten film, formation of tungsten nitride film, which is a cause of increased wire resistance, is suppressed, so that yields are improved compared with related... Agent: Sughrue Mion, PLLC

20080102624 - Method of fabricating semiconductor device with recess gate: A method of fabricating a semiconductor device includes forming a hard mask pattern over a substrate, wherein the hard mask pattern exposes a recess region, performing a first etching process on the exposed recess region to form a first recess having sidewalls and to form passivation layers on the sidewalls... Agent: Lowe Hauptman Ham & Berner, LLP

20080102625 - Method for producing a layer arrangement: The invention relates to a method for producing a layer arrangement. An electrically conductive layer is formed and patterned. A sacrificial layer formed on at least part of the patterned electrically conductive layer. An electrically insulating layer is formed on the electrically conductive and sacrificial layers and is patterned in... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080102626 - Method of forming copper wiring in semiconductor device: A semiconductor package includes method of forming a copper wiring may comprise forming an interlayer insulation film provided with a damascene pattern for wiring over a semiconductor substrate; depositing a barrier metal film over a surface of the damascene pattern and the interlayer insulation film; depositing a copper film over... Agent: Ladas & Parry LLP

20080102627 - Semiconductor scheme for reduced circuit area in a simplified process: An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080102628 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming, on a substrate having a recessed portion on a surface, a plating film which is at least buried in the recessed portion and has a higher impurity concentration in an upper portion than in a lower portion, thermally treating the plating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080102629 - Systems and methods of forming tantalum silicide layers: A method of forming (and apparatus for forming) tantalum silicide layers (including tantalum silicon nitride layers), which are typically useful as diffusion barrier layers, on a substrate by using a vapor deposition process with a tantalum halide precursor compound, a silicon precursor compound, and an optional nitrogen precursor compound.... Agent: Mueting, Raasch & Gebhardt, P.A.

20080102630 - Method of manufacturing semiconductor device: In a method of manufacturing a semiconductor device, an insulating film with a concave portion is formed on a semiconductor wafer. A barrier layer is formed on the insulating film to cover a surface of the insulating film such that the barrier layer has a uniform crystal orientation over a... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser, P.C.

20080102631 - Chemical dissolution of barrier and adhesion layers: A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until... Agent: Intel Corporation C/o Intellevate, LLC

20080102632 - Deposition process for iodine-doped ruthenium barrier layers: An iodine-doped ruthenium barrier layer for use with copper interconnects within integrated circuits is formed using novel, iodine-containing ruthenium precursors in an ALD or CVD process. Ruthenium precursors that may be used include ruthenium containing carbonyls, arenes, cyclopentadienyls, and certain other ruthenium containing compounds. The ruthenium precursors include iodine to... Agent: Intel Corporation C/o Intellevate, LLC

20080102633 - Method for manufacturing semiconductor device and semiconductor device: A method for manufacturing a semiconductor device includes: a first step for successively staking on a semiconductor substrate a first semiconductor layer, a second semiconductor layer and a third semiconductor layer; a second step for forming on the semiconductor substrate a first groove passing through the third semiconductor layer, the... Agent: Advantedge Law Group, LLC

20080102634 - Sacrificial cmp etch stop layer: A chemical mechanical polishing (CMP) stop layer is implemented in a semiconductor fabrication process. The CMP stop layer, among other things, mitigates erosion of sidewall spacers during semiconductor fabrication and adverse effects associated therewith.... Agent: Texas Instruments Incorporated

20080102635 - Chemical-mechanical polishing method: A chemical-mechanical polishing process for forming a conductive interconnect includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface... Agent: North America Intellectual Property Corporation

20080102636 - Method for manufacturing semiconductor device: A method of manufacturing a semiconductor device in which a source contact plug and a drain contact plug are formed. The method includes the steps of etching part of the semiconductor substrate to form a step, thus forming an overlay vernier, and forming a hard mask on the step so... Agent: Townsend And Townsend And Crew, LLP

20080102637 - Method and semiconductor structure for reliability characterization: According to one exemplary embodiment, a method for characterizing a reliability of a semiconductor structure includes forming a recess in a first dielectric layer in the semiconductor structure; filling the recess with a sacrificial material; removing the sacrificial material thereby causing an intentional defect with known characteristics to aid in... Agent: Farjami & Farjami LLP

20080102639 - Method for fabricating semiconductor device with recess gate: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a... Agent: Lowe Hauptman Ham & Berner, LLP

20080102638 - Etch depth control for dual damascene fabrication process: The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading... Agent: Patterson & Sheridan, LLP

20080102640 - Etching oxide with high selectivity to titanium nitride: A substrate comprising an oxide layer covering a nitride layer, is etched in a process zone of a substrate processing chamber. A process gas comprising H2 gas is introduced into the process zone, and the process gas is energized to etch through the oxide layer to at least partially expose... Agent: Janah & Associates, P.C.

20080102641 - Grayscale reticle for precise control of photoresist exposure: A method of fabricating a grayscale reticle includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080102642 - Method of seasoning idle silicon nitride etcher and method of activating: A method of seasoning an idle silicon nitride etcher is described. A buffer material having stronger adhesion to an internal wall of the chamber of the silicon nitride etcher than silicon nitride is etched in the chamber, so as to form a buffer layer on the internal wall of the... Agent: Jianq Chyun Intellectual Property Office

20080102644 - Methods for removing photoresist from a semiconductor substrate: Methods for removing photoresist from a semiconductor substrate are provided. In accordance with an exemplary embodiment of the invention, a method for removing a photoresist from a semiconductor substrate comprises the steps of exposing the semiconductor substrate and the photoresist to a first plasma formed from oxygen, forming an oxide... Agent: Ingrassia Fisher & Lorenz, P.C.

20080102643 - Patterning method: A patterning method is provided. The method includes the steps of firstly forming an underlying layer, a silicon rich organic layer, and a photoresist layer on the material layer in succession. The photoresist layer is patterned, and the silicon rich organic layer is etched using the photoresist layer as a... Agent: Jianq Chyun Intellectual Property Office

20080102645 - Plasma for resist removal and facet control of underlying features: A substrate comprising a resist layer overlying a dielectric feature, is processed in a substrate processing chamber comprising an antenna, and first and second process electrodes. A process gas comprising CO2 is introduced into the chamber. The process gas is energized to form a plasma by applying a source voltage... Agent: Janah & Associates, P.C.

20080102646 - Integrated method and apparatus for efficient removal of halogen residues from etched substrates: A method and apparatus for removing volatile residues from a substrate are provided. In one embodiment, a method for volatile residues from a substrate includes providing a processing system having a load lock chamber and at least one processing chamber coupled to a transfer chamber, treating a substrate in the... Agent: Patterson & Sheridan, LLP

20080102647 - Post-lithography misalignment correction with shadow effect for multiple patterning: Misalignment created during a multiple-patterning process is a serious challenge for critical dimension (CD) control and layout design in continuing integrated-circuit device scaling. A number of post-lithography misalignment correction technologies based on the shadow effect are invented for multi-pattering lithographic applications. When applied to transfer patterns from a top layer... Agent: Yijian Chen

20080102648 - Method and system for making photo-resist patterns: A method of forming a resist pattern in a semiconductor device layer includes forming a buffer layer on a semiconductor device layer and forming a resist layer on the buffer layer. A decomposing agent is released into a portion of the buffer layer by a portion of the resist layer... Agent: Haynes And Boone, LLP

20080102649 - Underlayer coating forming composition for lythography containing compound having protected carboxyl group: m

20080102650 - Method of fabricating a nitrided silicon oxide gate dielectric layer: A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater... Agent: Schmeiser, Olsen & Watts