Semiconductor device manufacturing: process inventions 04/08

20080096290 - Magnetic tunnel junction memory and method with etch-stop layer: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080096292 - Method for measuring interface traps in thin gate oxide mosfets: A method for measuring interface traps in a MOSFET, comprising measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in... Agent: Texas Instruments Incorporated

20080096294 - Integrated circuit structure, display module, and inspection method thereof: An integrated circuit structure has an IC chip, at least a functional bump, and at least a dummy bump positioned on a joint surface of the IC chip. A terminal surface of the dummy bump is different in appearance from a terminal surface of the functional bump, which improves an... Agent: North America Intellectual Property Corporation

20080096295 - Method of manufacturing a semiconductor integrated circuit device: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving... Agent: Miles & Stockbridge PC

20080096297 - Electrical contacts for a semiconductor light emitting apparatus: A process for forming electrical contacts for a semiconductor light emitting apparatus is disclosed. The light emitting apparatus has a first layer of first conductivity type, an active layer for generating light overlying the first layer, and a second layer of second conductivity type overlying the active layer. The process... Agent: Patent Law Group LLP

20080096301 - Micro electro mechanical system: Embodiments of a micro electro mechanical system are disclosed.... Agent: Hewlett Packard Company

20080096306 - Semiconductor device and method for forming the same: A memory device includes an insulating layer formed over a substrate, a gate formed over the insulating layer, and charge storage elements disposed over the insulating layer. The charge storage elements are separated from each other and are electrically insulated, and each of the charge storage elements is capable of... Agent: Lee & Morse, P.C.

20080096291 - Method for forming semiconductor device and method for forming photovoltaic device: A method for forming a semiconductor device including a semiconductor layer, formed of a silicon-based deposited film containing crystals by plasma-enhanced CVD, includes the steps of applying a bias voltage between a high-frequency electrode and a substrate with the high-frequency electrode being negative when the semiconductor layer is formed; detecting... Agent: Fitzpatrick Cella Harper & Scinto

20080096293 - Method and apparatus for evaluation and improvement of mechanical and thermal properties of cnt/cnf arrays: A method and apparatus for the evaluation and improvement of the mechanical and thermal properties of carbon-nanotube (CNT) and carbon nanofiber (CNF) arrays grown on a substrate is disclosed. The Young's modulus of a CNT/CNF material is measured by applying an axial compressive force on the CNT/CNF array and measuring... Agent: Glenn Patent Group

20080096296 - Ink-jet printhead and manufacturing method thereof: An ink-jet printhead and a manufacturing method thereof include a substrate on which a space portion is formed, a passage plate installed on the substrate in which an ink chamber is formed to store ink, a nozzle plate installed at a top surface of the passage plate in which a... Agent: Staas & Halsey LLP

20080096298 - Self-forming microlenses for vcsel arrays: A Vertical Cavity Surface Emitting Laser (VCSEL) assembly including a VCSEL structure having a light-emitting region located on its surface, a relatively wettable region of a surface modifier coating formed over the light emitting region, and a microlens formed on the relatively wettable region. A relatively non-wettable region of the... Agent: Bever, Hoffman & Harms, LLP

20080096299 - Liquid crystal display device and fabricating method thereof: A method for fabricating a liquid crystal display (LCD) device comprises forming an active pattern and a data line on a substrate, the active pattern including a source, a drain, and a channel regions; a first insulation film on a portion of the substrate; forming a gate electrode in a... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20080096300 - Manufacturing method of liquid crystal display panel: A liquid crystal display panel and a manufacturing method thereof are provided. The liquid crystal display panel comprises a color filter substrate and a thin film transistor array substrate arranged in parallel and a liquid crystal layer between the substrates. In addition, several spacers are disposed on a black matrix... Agent: Jianq Chyun Intellectual Property Office

20080096302 - Photodiode with ultra-shallow junction for high quantum efficiency cmos image sensor and method of formation: A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface latter has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019... Agent: Dickstein Shapiro LLP

20080096303 - Fabrication method of image sensing device: An image sensing device includes a substrate with a photo sensing and a transistor regions, a photo diode, a transistor, a dielectric layer, a metal interconnect, a metal conductive line, a conformal passivation layer, a color filter, a lens planar layer, and a microlens. The photo diode is in the... Agent: Jianq Chyun Intellectual Property Office

20080096304 - Photodiode array and method for making thereof: Disclosed is a photodiode array comprising a semiconductor substrate; a plurality of photodiodes formed on the semiconductor substrate; and crystal fused regions losing crystallinity by fusing a semiconductor material of the photodiodes between the plurality of photodiodes.... Agent: Drinker Biddle & Reath (dc)

20080096305 - Method for forming deposited film and photovoltaic element: A method for forming a deposited film containing microcrystalline silicon on a moving substrate by plasma-enhanced CVD includes forming a deposited film containing microcrystalline silicon on a moving substrate by plasma-enhanced CVD under conditions such that when a deposited film having a thickness of 300 nm or more is formed... Agent: Fitzpatrick Cella Harper & Scinto

20080096307 - Method and apparatus for controlling composition profile of copper indium gallium chalcogenide layers: The present invention relates to method and apparatus for preparing thin films of semiconductor films for radiation detector and photovoltaic applications. In one aspect, the present invention is directed to a method of forming a Cu(In,Ga)(S,Se)2 layer with substantially uniform Ga distribution. In a particular aspect, the method includes depositing... Agent: Pillsbury Winthrop Shaw Pittman LLP

20080096308 - Methods for coupling diamond structures to photonic devices: Various embodiments of the present invention are directed to methods for coupling semiconductor-based photonic devices to diamond. In one embodiment of the present invention, a method for coupling a photonic device with a diamond structure comprises embedding the diamond structure in a first substrate, where the first substrate comprises a... Agent: Hewlett Packard Company

20080096309 - Semiconductor-on-diamond devices and associated methods: Semiconductor-on-diamond devices and methods for making such devices are provided. One such method may include depositing a semiconductor layer on a semiconductor substrate, depositing an adynamic diamond layer on the semiconductor layer opposite the semiconductor substrate, and coupling a support substrate to the adynamic diamond layer opposite the semiconductor layer... Agent: Thorpe North & Western, LLP.

20080096311 - Apparatus and method for connecting components: An apparatus for connecting at least two components contains a lower die and an upper die. The lower die has the components which are to be connected, with the first component supporting the at least second component with an at least partial overlap relative to the first component. The lower... Agent: Coats & Bennett/infineon Technologies

20080096310 - Embedded capacitors for reducing package cracking: A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure... Agent: Intel/blakely

20080096312 - Low profile ball grid array (bga) package with exposed die and method of making same: Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080096313 - Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates: A projection system, a spatial light modulator, and a method for forming a MEMS device is disclosed. The spatial light modulator can have two substrates bonded together with one of the substrates comprising a micromirror array. The two substrates can be bonded at the wafer level after depositing a getter... Agent: Texas Instruments Incorporated

20080096314 - Ball grid array package and method thereof: A ball grid array package includes a substrate, a chip, a plurality of pads, a solder mask, a plurality of partitioning walls, and a plurality of solder balls. The substrate has an upper surface and a lower surface opposite to the upper surface. The chip is disposed on the upper... Agent: Reed Smith LLP

20080096315 - Stacked chip package and method for forming the same: Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire... Agent: Marger Johnson & Mccollom, P.C.

20080096316 - Stacked die in die bga package: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20080096317 - Method for producing portable memory devices: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test... Agent: Technology & Innovation Law Group, PC

20080096318 - Method of connecting carrier tapes and tcp mounting apparatus used therefor: A method of connecting carrier tapes in the TCP mounting apparatus is provided, which makes it surer to form an interconnection between the end portion of a current carrier tape and the beginning portion of a new carrier tape, and which is easy to be carried out. The end portion... Agent: Young & Thompson

20080096319 - Sawn power package and method of fabricating same: In one embodiment of the invention, a lead-frame is designed for use in IC packages such as those conforming to the TO 220 standard or other standards for power packages. The device areas of the lead-frame are arranged in columns, and each column is molded so as to expose a... Agent: Beyer Weaver LLP

20080096320 - High density chip packages, methods of forming, and systems including same: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.... Agent: Schwegman, Lundberg & Woessner, P.A.

20080096321 - Semiconductor chip package manufacturing method and structure thereof: A semiconductor chip package manufacturing method and a structure thereof are provided. The manufacturing method includes: providing a base having an image sensor chip and an encapsulant, in which the image sensor chip has pads and an active area; placing a transparent insulator on the active area; forming an insulation... Agent: Volentine & Whitt PLLC

20080096322 - Manufacturing method of semiconductor chip: The present invention provides a method of manufacturing a semiconductor chip formed with an adhesive film at a back surface thereof, comprising the steps of applying a die bond material onto a dummy wafer by a spin coat method to form a coating film, bonding a back surface of a... Agent: Rabin & Berdo, PC

20080096323 - Integrated circuit die/package interconnect: A system may include a plurality of pliant conductive elements, a first end of one of the plurality of pliant conductive elements to be electrically coupled to a first electrical contact of an integrated circuit substrate and a second end of the one of the plurality of pliant conductive elements... Agent: Buckley, Maschoff & Talwalkar LLC

20080096325 - Chip packaging process: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a... Agent: Jianq Chyun Intellectual Property Office

20080096324 - Electronic assemblies having a low processing temperature: Embodiments relate to electronic assemblies and methods for forming electronic assemblies. One method includes providing a die and a copper heat spreader that are to be coupled to one another through a thermal interface material. A layer of tin is formed on the copper heat spreader. The heat spreader and... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20080096326 - Method for making advanced smart cards with integrated electronics using isotropic thermoset adhesive materials with high quality exterior surfaces: Advanced Smart Cards and similar form factors (e.g. documents, tags) having high quality external surfaces of Polyvinylchloride (PVC), Polycarbonate (PC), synthetic paper or other suitable material can be made with highly sophisticated electronic components (e.g. Integrated Circuit chips, batteries, microprocessors, Light Emitting Diodes, Liquid Crystal Displays, polymer dome switches, and... Agent: John R Lane Frommer Lawrence & Haug

20080096327 - Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo,... Agent: Saile Ackerman LLC

20080096328 - Nonvolatile memory devices and methods of forming the same: A memory device includes a substrate having a cell region, a low voltage region and a high voltage region. A ground selection transistor, a string selection transistor and a cell transistor are in the cell region, a low voltage transistor is in the low voltage region, and a high voltage... Agent: Myers Bigel Sibley & Sajovec

20080096329 - Method of manufacturing thin film device, electro-optic device, and electronic instrument: A method of manufacturing a thin film device includes: manufacturing a multi-layered structure in which a transfer layer including a thin film device is transferred to a first surface of the transfer-target substrate; and adhering a second surface of the transfer-target substrate, to which the transfer layer was transferred, to... Agent: Harness, Dickey & Pierce, P.L.C

20080096330 - High-performance cmos soi devices on hybrid crystal-oriented substrates: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing... Agent: Scully, Scott, Murphy & Presser, P.C.

20080096331 - Method for fabricating high compressive stress film and strained-silicon transistors: A method for fabricating strained silicon transistors is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region formed thereon. Next, a precursor, silane, and ammonia are injected, in which the precursor is reacted with silane and... Agent: North America Intellectual Property Corporation

20080096332 - Method of manufacturing a thin-film transistor substrate: A gate insulating layer, an active layer and a data metal film are sequentially formed on a substrate. A first photoresist pattern having a relatively small thickness in a channel forming area with respect to a thickness of the photoresist pattern not in the channel forming area is formed on... Agent: Cantor Colburn, LLP

20080096333 - Method of manufacturing a thin film transistor substrate and stripping composition: A method of manufacturing a thin film transistor substrate includes forming a transistor thin layer pattern, forming a protecting layer, forming a photoresist film, forming a pixel electrode and a conductive layer that are separated from each other, stripping a photoresist pattern to remove the conductive layer using a stripping... Agent: Cantor Colburn, LLP

20080096334 - Semiconductor device manufacturing method and semiconductor device using the same: Including a process for forming a fin 12a having a first height and a fin 12b having a second height lower than the first height, a process for forming a silicon oxide film on the upper and side faces of each of the fins 12a and 12b, a process for... Agent: Rabin & Berdo, PC

20080096335 - Sic metal semiconductor field-effect transistors and methods for producing same: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication... Agent: HowardIPLaw Group

20080096336 - Method of forming integrated circuit devices having n-mosfet and p-mosfet transistors with elevated and silicided source/drain structures: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both... Agent: Slater & Matsil, L.L.P.

20080096337 - Disposable semiconductor device spacer with high selectivity to oxide: The invention provides, in one aspect, a method of forming a semiconductor device. The method includes forming a gate dielectric layer and a gate electrode layer over a substrate. A portion of the gate dielectric layer and gate electrode layer is etched to form a plurality of gate electrodes. A... Agent: Texas Instruments Incorporated

20080096338 - Methods and devices employing metal layers in gates to introduce channel strain: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed... Agent: Texas Instruments Incorporated

20080096339 - Cmos devices with hybrid channel orientations and method for fabricating the same: The present invention relates to a method of fabricating a semiconductor substrate that includes forming at least first and second device regions, wherein the first device region includes a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region includes... Agent: Scully, Scott, Murphy & Presser, P.C.

20080096340 - Method of fabricating a nonvolatile memory device: A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a charge blocking layer on the charge trapping layer by supplying sequentially a metal source gas and an oxidizing gas onto... Agent: Lee & Morse, P.C.

20080096341 - Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas: A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the center of the top surface of a second contact drain plug. A first electrode is formed... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080096342 - Cmos circuits including a passive element having a low end resistance: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end... Agent: Scully, Scott, Murphy & Presser, P.C.

20080096343 - Fabricating method of cmos: A method of forming a metal-oxide-semiconductor (MOS) device is provided. The method includes the following steps. First, a conductive type MOS transistor is formed on a substrate. Then, a first etching stop layer is formed over the substrate to cover conformably the conductive type MOS transistor. Thereafter, a stress layer... Agent: Jianq Chyun Intellectual Property Office

20080096344 - Method for manufacturing a resistor random access memory with a self-aligned air gap insulator: A method for manufacturing a resistor random access memory with a self-aligned air gap insulator. A high density plasma deposition on the stack of post-patterned layers produces a hard mask that is substantially near the center and overlying the cap layer of the stack of post-patterned layers. The high density... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080096345 - Nanoelectrochemical cell: A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080096346 - Method for preparing a trench capacitor structure: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric... Agent: Wpat, PC Intellectual Property Attorneys

20080096347 - Methods of forming electronic devices including electrodes with insulating spacers thereon: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the... Agent: Myers Bigel Sibley & Sajovec

20080096348 - Contacts for semiconductor devices: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.... Agent: Harrity Snyder, L.L.P.

20080096351 - Memory device and method of manufacturing the same: A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the... Agent: Harness, Dickey & Pierce, P.L.C

20080096349 - Method of fabricating a nonvolatile memory device: A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a first charge blocking layer on the charge trapping layer by supplying a metal source gas and a first oxidizing gas... Agent: Lee & Morse, P.C.

20080096350 - Nonvolatile memory device and fabrication method: Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region.... Agent: Volentine & Whitt PLLC

20080096352 - Method of forming a semiconductor memory device and semiconductor memory device: Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill... Agent: Slater & Matsil LLP

20080096353 - Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same: A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on... Agent: Townsend And Townsend And Crew, LLP

20080096354 - Vertical mos transistor with embedded gate and its fabrication process: According to the invention, a transistor of vertical MOS type is produced in which an insulating assembly (28) formed above the drain (26) comprises insulating zones (42, 44) either side of the drain; cavities extend under the insulating assembly, either side of the channel (69); the gate (77a, 77b) is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080096355 - Transistor structure of memory device and method for fabricating the same: A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed... Agent: Townsend And Townsend And Crew, LLP

20080096356 - Substrate having silicon germanium material and stressed silicon nitride layer: A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the... Agent: Applied Materials C/o Pillsbury Winthrop Shaw Pittman LLP

20080096357 - Method for manufacturing a memory device: A method for manufacturing a memory device that includes using a gap-filling material that inhibits charge coupling between memory devices. A semiconductor material is provided that has an active region and an isolation region. A charge trapping structure is formed over the active region and a layer of semiconductor material... Agent: Farjami & Farjami LLP

20080096358 - Method of fabricating semiconductor device having reduced contact resistance: Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After gate spacers are formed on sidewalls of the gate... Agent: F. Chau & Associates, LLC

20080096359 - Method of determining angle misalignment in beam line ion implanters: A method includes directing an ion beam at a plurality of differing incident angles with respect to a target surface of a substrate to implant ions into a plurality of portions of the substrate, wherein each one of the plurality of differing incident angles is associated with a different one... Agent: Varian Semiconductor Equipment Assc., Inc.

20080096360 - Semiconductor wafer suitable for forming a semiconductor junction diode device and method of forming same: A method is provided of making a semiconductor wafer for a semiconductor junction diode device having a target forward voltage drop and a target reverse breakdown voltage. The method begins by doping a semiconductor substrate of a first conductivity type through the back surface with a first dopant of the... Agent: Mayer & Williams PC

20080096361 - Structure for realizing integrated circuit having schottky diode and method of fabricating the same: An integrated circuit structure in which a plurality of Schottky diodes and a capacitor are integrally formed. The integrated circuit structure includes a substrate including an N-type semiconductor doped with N-type impurities and a P-type semiconductor doped with P-type impurities; a first conductive layer laminated on the substrate so that... Agent: Sughrue Mion, PLLC

20080096362 - Plasma display panel and manufacturing method of the same: A plasma display panel includes a sealing member that encloses a gas filled space, a first substrate and a second substrate that sandwich the gas filled space and the sealing member, a first insulator layer that is sandwiched between the first substrate and the sealing member, and a second insulator... Agent: Staas & Halsey LLP

20080096363 - High dielectric constant materials: An integrated circuit can be formed with a high-k dielectric layer. A first titanium oxide layer is deposited over a substrate using a first ALD process. A first metal oxide layer is also deposited over the substrate using a second ALD process. A second titanium oxide layer is deposited over... Agent: Slater & Matsil, L.L.P.

20080096364 - Conformal liner for gap-filling: Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition,... Agent: Mcdermott Will & Emery LLP

20080096365 - Permanent wafer bonding using metal alloy preform discs: A method for fabricating semiconductor devices at the wafer level, and devices fabricated using the method, are described. Wafer-level bonding using a relatively thick layer of electrically conducting bond medium was used to achieve void-free permanent wafer level bonding. The bond medium can be introduced to the pre-bonded wafers by... Agent: Koppel, Patrick & Heybl

20080096366 - Method for forming conductive layer and substrate having the same, and method for manufacturing semiconductor device: A separation layer is formed over a substrate having a depressed portion, using a silane coupling agent; a conductive layer and an insulating layer that covers the conductive layer are formed in the depressed portion over the separation layer; and a sticky member is attached to the insulating layer, then... Agent: Eric Robinson

20080096367 - Method for laser dicing of a substrate: The invention relates to a method for dicing a substrate with a laser apparatus, comprising the steps of delivering a laser beam (15) from said laser apparatus to said substrate to dice said substrate (1) in at least two dies. A first assist gas is supplied at the substrate during... Agent: Philips Intellectual Property & Standards

20080096368 - Wafer processing method: A water processing method for providing a gettering sink effect to a wafer having a plurality of streets which are formed in a lattice pattern on the front surface of a substrate and devices which are formed in a plurality of areas sectioned by the plurality of streets, comprising the... Agent: Smith, Gambrell & Russell

20080096369 - Apparatus and method for high-throughput chemical vapor deposition: The invention relates to a device for depositing at least one especially thin layer onto at least one substrate (9). Said device comprises a process chamber (1, 20, 11, 11′, 40, 21), housed in a reactor housing (2) and comprising a movable susceptor (20) which carries the at least one... Agent: Sonnenschein Nath & Rosenthal LLP

20080096370 - Method of manufacturing dual orientation wafers: Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080096371 - Process for producing p-doped and epitaxially coated semiconductor wafers from silicon: The Czochralski method is used for producing p−-doped and epitaxially coated semiconductor wafers from silicon, wherein a silicon single crystal is pulled, and during the pulling is doped with boron, hydrogen and nitrogen, and the single crystal thus obtained is processed to form p−-doped semiconductor wafers which are epitaxially coated.... Agent: Brooks Kushman P.C.

20080096372 - Patterning of doped poly-silicon gates: A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g.... Agent: Knobbe Martens Olson & Bear LLP

20080096373 - Fabrication of ccd image sensors using single layer polysilicon: A method for fabricating CCD imaging structures having single layer polysilicon gates and employing conventional photolithographic techniques and equipment is disclosed. The comprises the steps of providing a silicon substrate; growing a dielectric layer substantially overlying the silicon substrate; depositing a first layer of polysilicon substantially overlaying the dielectric layer;... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20080096374 - Selective removal of rare earth based high-k materials in a semiconductor device: A method is disclosed for the selective removal of rare earth based high-k materials such as rare earth scandate high-k materials (e.g. DyScO3) over silicon or silicon dioxide. As an example Dy and Sc comprising high-k materials are used as a high-k material in gate stacks of a semiconductor device.... Agent: Knobbe Martens Olson & Bear LLP

20080096378 - Contact structure and method of forming the same: In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first... Agent: Harness, Dickey & Pierce, P.L.C

20080096375 - Method for making memory cell device: A memory cell device, including a memory material element switchable between electrical property states by the application of energy, includes depositing an electrical conductor layer, depositing dielectric material layers and etching to create a first electrode and voids. A memory material is applied into a void to create a memory... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080096377 - Semiconductor device and method for forming the same: In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.... Agent: Marger Johnson & Mccollom, P.C.

20080096376 - Transparent zinc oxide electrode having a graded oxygen content: A method of reactively sputtering from a metallic zinc target a transparent conductive oxide electrode of zinc oxide from a metallic zine in a silicon photo diode device and the resultant product, such as a solar cell. The electrode in deposited on a transparent substrate in at least two steps.... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20080096379 - Flip chip metallization method and devices: Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wettable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in... Agent: Thorpe North & Western, LLP.

20080096380 - Low-k interconnect structures with reduced rc delay: A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier... Agent: Slater & Matsil, L.L.P.

20080096381 - Atomic layer deposition process for iridium barrier layers: An iridium barrier and adhesion layer for use with copper interconnects within integrated circuits is formed using an atomic layer deposition (ALD) process. The ALD process uses an organometallic iridium precursor and at least one co-reactant.... Agent: Intel Corporation C/o Intellevate, LLC

20080096382 - Method for producing an integrated circuit including a connection contact on a semiconductor body: A method for producing an integrated circuit is disclosed. One embodiment includes application of a barrier layer on the surface of the semiconductor body and in the trench, which barrier layer completely fills the trench and is at least partly deposited by using a CVD method. A metallization layer is... Agent: Dicke, Billig & Czaja

20080096383 - Method of manufacturing a semiconductor device with multiple dielectrics: A method of manufacturing a semiconductor device with at least a first dielectric material and a second dielectric material is disclosed. In one aspect, the method comprises providing a first dielectric material on a substrate. The method further comprises providing a patterned sacrificial layer covering the first dielectric material in... Agent: Knobbe Martens Olson & Bear LLP

20080096384 - Method of forming damascene filament wires: A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask.... Agent: Schmeiser, Olsen & Watts

20080096385 - Slurry composition for forming tungsten pattern and method for manufacturing semiconductor device using the same: A method for manufacturing a semiconductor device with a slurry composition for forming a tungsten pattern. The method comprises: forming a trench in an insulating film formed on a substrate; depositing a tungsten film over the insulating film including the trench; first polishing a tungsten film with a first slurry... Agent: Townsend And Townsend And Crew, LLP

20080096386 - Method of forming a phase-changeable layer and method of manufacturing a semiconductor memory device using the same: A phase-changeable layer and a method of forming the same are disclosed. In the method, a first hydrogen gas is introduced into a reaction chamber into which a substrate is loaded at a first flow rate to form first plasma. A primary cyclic CVD process is carried out using precursors... Agent: Marger Johnson & Mccollom, P.C.

20080096387 - Method for removing photoresist layer and method of forming opening: A method for removing a photoresist layer is provided. The method is suitable for a dielectric layer, wherein the dielectric layer has a patterned photoresist layer formed thereon and a metal silicide layer disposed thereunder and there is an etching stop layer disposed between the dielectric layer and the metal... Agent: Jianq Chyun Intellectual Property Office

20080096388 - Planarization method using hybrid oxide and polysilicon cmp: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of... Agent: Harrity Snyder, L.L.P.

20080096389 - Copper damascene chemical mechanical polishing (cmp) for thin film head writer fabrication: In one method and embodiment of the present invention, at least one coil layer is formed in a write head, using a two-slurry step of copper damascene chemical mechanical polishing method with a first slurry step removing the undesirable copper that is on top of the tantalum barrier layer and... Agent: Law Offices Of Imam

20080096390 - Halide anions for metal removal rate control: The inventive chemical-mechanical polishing composition comprises a liquid carrier, hydrogen peroxide, benzotriazole, and a halogen anion. The inventive method comprises chemically-mechanically polishing a substrate with the polishing composition.... Agent: Steven Weseman Associate General Counsel, I.p.

20080096391 - Method of fabricating semiconductor device having fine contact holes: A method for fabricating a semiconductor device having fine contact holes is exemplary disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer... Agent: Marger Johnson & Mccollom, P.C.

20080096392 - Ashing system: An ashing system capable of restraining etching and damage of an oxide film or a nitride film on a semiconductor substrate and ashing a resist uniformly at a very high rate is to be provided. The ashing system includes a reaction tube, a coil and a high frequency power source... Agent: Oliff & Berridge, PLC

20080096393 - Apparatus and method of etching a semiconductor substrate: An apparatus for etching a semiconductor substrate may include a bath, a reaction preventing layer, and a nozzle. The bath may receive a chemical solution. Grooves may be formed at the inner wall of the bath. The reaction preventing layer may be formed on the inner wall and in the... Agent: Harness, Dickey & Pierce, P.L.C

20080096394 - Gate dielectric layers and methods of fabricating gate dielectric layers: A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and... Agent: Duane Morris LLPIPDepartment (tsmc)

20080096395 - Producing method of semiconductor device: Disclosed is a producing method of a semiconductor device comprising: film thinning a silicon oxide film by heating the silicon oxide film formed after a surface of a silicon substrate is etched by chemical liquid, and one of thermal oxidizing by heating the thinned silicon oxide film to oxidize the... Agent: Birch Stewart Kolasch & Birch

20080096396 - Methods of forming low hydrogen concentration charge-trapping layer structures for non-volatile memory: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping... Agent: Akin Gump LLP - Silicon Valley

20080090307 - Bottom electrode for mram device and method to fabricate it: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a layer of ruthenium near the silicon nitride surface. The ruthenium is a good electrical conductor and it responds differently from Ta and TaN to certain etchants. Adhesion to SiN is enhanced... Agent: Stephen B. Ackerman

20080090310 - Substrate processing apparatus and substrate processing termination detection method: A substrate processing apparatus capable of completely removing an oxide layer that can cause defects in electronic devices, without lowering throughput of the apparatus. A process ship of the substrate processing apparatus includes a process module in which COR processing is performed on a wafer and another process module in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080090312 - Lithography alignment system and method using ndse-based feedback control: A contact lithography alignment system and method use nanoscale displacement sensing and estimation (nDSE) to maintain an alignment and compensate for a disturbance of one or more objects during contact lithography. A method of maintaining an alignment includes establishing an initial alignment of one or more objects and employing nDSE-based... Agent: Hewlett Packard Company

20080090313 - Manufacturing device of semiconductor package and manufacturing method of semiconductor package: A manufacturing device of a semiconductor package includes: a holding element for holding a substrate; a bonding element for holding the package and bonding a first metal bump of the package to a second metal bump of the substrate; a monitoring element for irradiating an infrared light toward the substrate... Agent: Posz Law Group, PLC

20080090314 - Semiconductor device and manufacturing method of the same: It is in offering the technology which can solve the problem actualized in connection with the narrowing of a pitch of a bump electrode. Concretely, even if it is a case where the contact position of the probe needle to a bump electrode shifts, in the needle contact of the... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080090315 - Method for manufacturing semiconductor optical device: After a metal cap layer is laminated on a semiconductor laminated structure, a waveguide ridge is formed, the waveguide ridge is coated with an SiO2 film, and a resist is applied; then, a resist pattern is formed, the resist pattern exposing the surface of the SiO2 film on the top... Agent: Leydig Voit & Mayer, Ltd

20080090318 - Method and apparatus for forming a photodiode: Embodiments of the invention provide a method and an apparatus for forming a photodiode. One embodiment provides a thin dielectric layer sandwiched between two metallic plates (electrodes), one or both of which are periodically patterned in one or two dimensions. The effect of the pattern is to couple incident light... Agent: Hewlett Packard Company

20080090320 - Self sealed mems device: An in-situ package comprises a hermetic enclosure (or “shell”) that may be formed by deposition of a material to form a cap structure. The cap structure may be left open at one end to allow introduction of an etchant to remove sacrificial material used in MEMS device fabrication. After removal,... Agent: Intel Corporation C/o Intellevate, LLC

20080090321 - Isolation method for low dark current imager: A method for forming the passivation layer for silicon-isolation interface between photosensitive regions of an image sensor, the method includes providing a substrate having a plurality of spaced apart photosensitive regions that collect charge in response to incident light; etching trenches in the substrate between the photosensitive regions; forming a... Agent: Pamela R. Crocker Patent Legal Staff

20080090323 - Image sensor and method of fabricating the same: An image sensor is provided. The image sensor includes a plurality of photodiode doped regions in a substrate, a passivation layer above the substrate, a dielectric layer between the passivation layer and the substrate, and a plurality of color filters in the dielectric layer being corresponding to the photodiode doped... Agent: Jianq Chyun Intellectual Property Office

20080090324 - Forming sublithographic heaters for phase change memories: A phase change memory with a heater with sublithographic dimensions may be achieved, in some embodiments, with lower thermal budget. The phase change memory may use a controlled etching process to reduce the lateral dimension of the heater.... Agent: Trop Pruner & Hu, PC

20080090325 - Method for producing organic field-effect transistors: p

20080090308 - Semiconductor device alignment mark having a plane pattern and semiconductor device: An alignment mark for a semiconductor device is provided. The alignment mark defines a plane pattern and includes a conductive layer embedded in a recessed section provided in an insulation layer, and an oxidation barrier layer provided on the conductive layer, wherein an area occupancy ratio of the recessed section... Agent: Harness, Dickey & Pierce, P.L.C

20080090309 - Controlled annealing method: A method for rapid thermal annealing is disclosed. As the substrate is inserted into an annealing chamber, it begins to heat due to the heat radiating from chamber components that were heated when a previous substrate was annealed. Thus, the leading edge of the substrate may be at an elevated... Agent: Patterson & Sheridan, LLP

20080090311 - Dipping detecting device for fabricating a semiconductor device: A dipping detecting device used in the fabrication of semiconductor devices. The dipping detecting device includes a gripper used as a conductive first electrode and configured to pick up a semiconductor device in order to dip the semiconductor device into a dipping solution. A conductor used as a second electrode... Agent: Volentine & Whitt PLLC

20080090316 - Method for manufacture of optically pumped, surface-emitting semiconductor laser device: A method for manufacturing an optically pumped surface-emitting semiconductor laser device, wherein a surface-emitting semiconductor laser layer sequence having a quantum confinement structure is applied onto a common substrate. The surface-emitting semiconductor laser layer sequence outside an intended laser region is removed and a region is exposed. An edge-emitting semiconductor... Agent: Schiff Hardin, LLP Patent Department

20080090317 - Nanotip diode electroluminescence device: A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080090319 - Infrared photodiodes and sensor arrays with improved passivation layers and methods of manufacture: InSb infrared photodiodes and sensor arrays with improved passivation layers and methods for making same are disclosed. In the method, a passivation layer of AlInSb is deposited on an n-type InSb substrate using molecular beam epitaxy before photodiode detector regions are formed in the n-type substrate. Then, a suitable P+... Agent: Intellectual Property & Licensing Raytheon Company

20080090322 - Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using soi wafers: The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made my producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing the dicing process to yield an individual chip. A thin-layered circuit may transmit... Agent: Second Sight Medical Products, Inc.

20080090327 - Method for producing znte system compound semiconductor single crystal, znte system compound semiconductor single crystal, and semiconductor device: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first... Agent: Birch Stewart Kolasch & Birch

20080090328 - Method for producing znte system compound semiconductor single crystal, znte system compound semiconductor single crystal, and semiconductor device: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first... Agent: Birch Stewart Kolasch & Birch

20080090326 - Method of surface treating a phase change layer and method of manufacturing a phase change memory device using the same: A method of surface treating a phase change layer may include, before forming the phase change layer, forming a coating layer on a surface of a bottom layer on which the phase change layer is to be formed, wherein the coating layer has a chemical structure for contributing to the... Agent: Harness, Dickey & Pierce, P.L.C

20080090330 - Semiconductor device including a plurality of circuit element chips and a manufacturing method thereof: A semiconductor device includes a first circuit element chip including a first surface on which a plurality of first electrodes are arranged, and a second circuit element chip including a first surface on which a plurality of second electrodes are arranged. The second circuit element chip is mounted on the... Agent: Volentine & Whitt PLLC

20080090329 - Stacked modules and method: The present invention stacks integrated circuits into modules that conserve board surface area. In a precursor assembly devised as a component for a stacked circuit module in accordance with a preferred embodiment of the present invention, one or more stiffeners are disposed at least partially between a flex circuit and... Agent: Fish & Richardson P.C.

20080090331 - Semiconductor device manufacturing method and manufacturing apparatus: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the... Agent: Harness, Dickey & Pierce, P.L.C

20080090334 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is described. The method comprises: providing a mold; coating a glue on a surface of the mold; providing at least one semiconductor chip, wherein the semiconductor chip includes a first side and a second side on opposite sides, and the first side of... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080090333 - Microelectronic packages fabricated at the wafer level and methods therefor: A method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with... Agent: Tessera Lerner David Et Al.

20080090332 - Process for fabricating electronic components using liquid injection molding: A process for fabricating an electronic component includes a liquid injection molding method for overmolding a semiconductor device. The liquid injection molding method includes: i) placing the semiconductor device in an open mold, ii) closing the mold to form a mold cavity, iii) heating the mold cavity, iv) injection molding... Agent: Dow Corning Corporation Co1232

20080090335 - Circuit module and manufacturing method thereof: A circuit module includes an electronic component, a ceramic multilayer substrate and a resin wiring substrate. The ceramic multilayer substrate is provided with a wiring layer disposed on top thereof and a cavity in which the electronic component is mounted, wherein a space between the electronic component and the cavity... Agent: Bacon & Thomas, PLLC

20080090336 - Method for fabricating heat dissipating package structure: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; an encapsulant formed on the chip carrier and for encapsulating the chip, with a non-active surface of the chip being exposed from the encapsulant; and a heat spreader having a... Agent: Edwards Angell Palmer & Dodge LLP

20080090337 - Electrically actuated switch: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at... Agent: Hewlett Packard Company

20080090338 - Flexible substrate with electronic devices and traces: A method of manufacturing an electronic device (10) provides a substrate (20) that has a plastic material and has a metallic coating on one surface. A portion of the metallic coating is etched to form a patterned metallic coating. A particulate material (16) is embedded in at least one surface... Agent: David A. Novais Patent Legal Staff

20080090339 - Method for forming inter-poly dielectric in shielded gate field effect transistor: A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer... Agent: Townsend And Townsend And Crew, LLP

20080090340 - Method for selective laser crystallization and display panel fabricated by using the same: A display panel comprises a substrate having a displaying region (such as active organic light emitting region) and a circuit driving region; and a polysilicon layer formed on the substrate and having a first polysilicon portion and a second polysilicon portion respectively corresponding to the displaying region and circuit driving... Agent: Bacon & Thomas, PLLC

20080090341 - Method for manufacturing display device, and etching apparatus: A tube is arranged to be in contact with an insulating layer in an opening formation region, and a treatment agent (etching gas or etchant) is discharged to the insulating layer through the tube. With the discharged treatment agent (etching gas or etchant), the insulating layer is selectively removed to... Agent: Nixon Peabody, LLP

20080090342 - Method of manufacturing a thin film transistor substrate: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a gate insulating film and an active layer on a substrate, forming a data metal layer including a first, second, and third metal layers on the active layer, forming a first photoresist pattern on the data metal layer,... Agent: Cantor Colburn, LLP

20080090343 - Method for manufacturing thin film transistor array panel: A method of manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a semiconductor layer, and a conductive layer on the gate line; forming a photosensitive film on the conductive layer; forming a first photosensitive film pattern including... Agent: Cantor Colburn, LLP

20080090344 - Semiconductor device and manufacturing method thereof: It is an object of the invention that, in semiconductor device, in order to promote the tendency of miniaturization of each display pixel pitch, which will be resulted in with the tendency toward the higher precision (increase of pixel number) and further miniaturizations, a plurality of elements is formed within... Agent: Eric Robinson

20080090345 - Method for fabrication of devices in a multi-layer structure: A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer... Agent: HowardIPLaw Group

20080090346 - Reliable high-voltage junction field effect transistor and method of manufacturing therefor: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a... Agent: Texas Instruments Incorporated

20080090347 - Lateral power mosfet with high breakdown voltage and low on-resistance: A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and... Agent: Slater & Matsil, L.L.P.

20080090348 - Gate-assisted silicon-on-insulator on bulk wafer and its application to floating body cell memory and transistors: Embodiments of methods and apparatus for a gate-assisted silicon-on-insulator on bulk wafer and its application to floating body cells are generally described herein. Other embodiments may be described and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20080090349 - Different embedded strain layers in pmos and nmos transistors and a method of forming the same: By omitting a growth mask or by omitting lithographical patterning processes for forming growth masks, a significant reduction in process complexity may be obtained for the formation of different strained semiconductor materials in different transistor types. Moreover, the formation of individually positioned semiconductor materials in different transistors may be accomplished... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080090351 - Fabricating non-volatile memory with dual voltage select gate structure: A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an... Agent: Vierra Magen/sandisk Corporation

20080090352 - Nonvolatile memory device and method of manufacturing the same: A method of manufacturing a nonvolatile memory device includes forming a plurality of device isolation regions in a semiconductor substrate, forming a tunneling insulation layer on the semiconductor substrate, forming a first preliminary polysilicon layer in communication with the tunneling insulation layer and the device isolation regions, forming a preliminary... Agent: Lee & Morse, P.C.

20080090350 - Strained semiconductor device and method of making same: In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric, floating gate, insulating region, and control... Agent: Slater & Matsil LLP

20080090354 - Method of manufacturing a non-volatile memory device: A method of manufacturing a non-volatile memory device, includes forming a tunnel isolation layer comprising an oxynitride on a substrate by a simultaneous oxidation and nitridation treatment in which an oxidation process and a nitridation process are simultaneously performed using a processing gas including oxygen and nitrogen. The method further... Agent: F. Chau & Associates, LLC

20080090353 - Method of manufacturing non-volatile memory device: A method of manufacturing a non-volatie memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density the lower dielectric layer, and forming a... Agent: F. Chau & Associates, LLC

20080090355 - Manufacturing method of flash memory: A method for manufacturing flash memory is provided. A tunneling dielectric layer, a conductive layer and a patterned mask layer that exposes a portion of the conductive layer are formed on a substrate. An oxide layer is formed on the exposed conductive layer so that the conductive layer is partitioned... Agent: Jianq Chyun Intellectual Property Office

20080090356 - Method of manufacturing integrated circuit device including recessed channel transistor: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching... Agent: Marger Johnson & Mccollom, P.C.

20080090357 - Shallow source mosfet: A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top... Agent: Van Pelt, Yi & James LLP

20080090358 - Method of fabricating semiconductor integrated circuit device: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080090359 - Semiconductor device having a p-mos transistor with source-drain extension counter-doping: A method for forming a semiconductor device is provided. The method includes forming a n-type well region. The method further includes forming a gate corresponding to the semiconductor device on top of the n-type well region. The method further includes forming a source-drain extension region on each side of the... Agent: Freescale Semiconductor, Inc. Law Department

20080090360 - Methods for fabricating multiple finger transistors: Methods are provided for the fabrication of multiple finger transistors. A method comprises forming a layer of gate-forming material overlying a semiconductor substrate and forming a layer of dummy gate material overlying the layer of gate-forming material. The layer of dummy gate material is etched to form a dummy gate... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080090361 - Corner dominated trigate field effect transistor: Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080090362 - Methods of fabricating field effect transistors having multiple stacked channels: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate... Agent: Myers Bigel Sibley & Sajovec

20080090363 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device forms an N− diffusion layer to be a source/drain region of a grooved transistor simultaneously with an N− diffusion layer of a channel region directly under a gate electrode of an antifuse element. The formation of the N− diffusion layer directly under the... Agent: Sughrue Mion, PLLC

20080090364 - Semiconductor device and its manufacture method: Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080090365 - Electrically erasable programmable read only memory (eeprom) cell: Semiconductor structures are adapted to form an electrically erasable programmable read only memory (EEPROM) cell having a long retention life, and/or a reduced programming voltage, and/or a reduced semiconductor real estate, and/or a reduced number of semiconductor fabrication steps.... Agent: Daly, Crowley, Mofford & Durkee, LLP

20080090366 - Hybrid soi-bulk semiconductor transistors: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080090367 - Field effect transistor with thin gate electrode and method of fabricating same: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the... Agent: Schmeiser, Olsen & Watts

20080090368 - Method for forming offset spacers for semiconductor device arrangements: Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the... Agent: Mcdermott, Will & Emery

20080090369 - Method of manufacturing semiconductor device: The method of manufacturing the semiconductor device comprises forming a transistor including a gate electrode and a source/drain diffused layer over a semiconductor substrate, forming a nickel platinum film over the semiconductor substrate, covering the gate electrode and the source/drain diffused layer, making a first thermal processing to react the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080090370 - Post-silicide spacer removal: A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080090371 - Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same: A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with... Agent: Dickstein Shapiro LLP

20080090372 - Method of manufacturing coil: A method of manufacturing a coil for a micro-actuator. The method of manufacturing a coil for a micro-actuator includes preparing a substrate, forming a plurality of trenches for forming a coil on the substrate, covering portions on the substrate with a masking layer except for the plurality of trenches, electroplating... Agent: Sughrue Mion, PLLC

20080090373 - Fabrication method of trench capacitor: A method of fabricating trench capacitors is provided. A plurality of trenches is formed in the substrate by performing a patterning process with a patterned mask layer on a substrate. A bottom electrode is formed in the substrate of the surface of the trench. A portion of the patterned mask... Agent: Jianq Chyun Intellectual Property Office

20080090374 - Methods of forming capacitors: A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with... Agent: Matthew W. Miller

20080090375 - Method for manufacturing a semiconductor device including a stacked capacitor: A process for forming a capacitor in a semiconductor device includes the step of forming a two-layer capacitor insulation film including a silicon oxynitride film and a tantalum oxide film. The step for forming the silicon oxynitride film is performed at a first substrate temperature, and the step of forming... Agent: Young & Thompson

20080090376 - Method of fabricating semiconductor device: A semiconductor device including a composite structure and a contact is provided. The composite structure includes a bottom electrode, an insulating layer, and an upper electrode from bottom to top. The contact electrically connects the upper electrode and the bottom electrode. The composite structure is used as a resistor, and... Agent: Jianq Chyun Intellectual Property Office

20080090377 - Laser scribe on front side of a semiconductor wafer: Disclosed are a semiconductor wafer (10) having a front side laser scribe (22) and the methods for manufacturing the same. The methods of the invention include the formation of a scribe foundation (12) on the front side of the semiconductor wafer (10) designed to accept laser scribing (22), and laser... Agent: Texas Instruments Incorporated

20080090378 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device includes forming a trench in a semiconductor substrate by a reactive ion etching (RIE) method, the trench having an inner surface, treating the trench with diluted hydrofluoric acid, treating the interior of the trench by a hydrofluoric acid vapor phase cleaning (HFVPC) method,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080090379 - Nitridation of sti fill oxide to prevent the loss of sti fill oxide during manufacturing process: A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080090380 - Temporary wafer bonding method for semiconductor processing: A method for temporary wafer bonding employs an addition reaction curable adhesive composition. The adhesive composition may include (A) a polyorganosiloxane containing an average of at least two silicon-bonded unsaturated organic groups per molecule, (B) an organosilicon compound containing an average of at least two silicon-bonded hydrogen atoms per molecule... Agent: Dow Corning Corporation Co1232

20080090381 - Laser processing method for gallium arsenide wafer: A laser processing method for a gallium arsenide wafer of radiating a laser beam along streets formed in lattice on a surface of a gallium arsenide substrate, and cutting-off the gallium arsenide wafer along the streets includes a wafer supporting step for sticking a rear surface of the gallium arsenide... Agent: Greer, Burns & Crain

20080090382 - Substrate dividing method: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within... Agent: Drinker Biddle & Reath (dc)

20080090383 - Method for manufacturing sic semiconductor device: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity ion in the SiC layer; forming a carbon layer on the SiC layer; heating the... Agent: Posz Law Group, PLC

20080090384 - Manufacturing method for simox substrate: A manufacturing method for a SIMOX substrate for obtaining a SIMOX substrate by subjecting a silicon substrate having oxygen ions implanted thereinto by heat treatment at 1300 to 1350° C. in an atmosphere of a gas mixture of argon and oxygen, the method includes: performing a pre-heat-treatment to the silicon... Agent: Kolisch Hartwell, P.C.

20080090385 - Composite material including nanocrystals and methods of making: Temperature-sensing compositions can include an inorganic material, such as a semiconductor nanocrystal. The nanocrystal can be a dependable and accurate indicator of temperature. The intensity of emission of the nanocrystal varies with temperature and can be highly sensitive to surface temperature. The nanocrystals can be processed with a binder to... Agent: Steptoe & Johnson LLP

20080090386 - Method for producing znte system compound semiconductor single crystal, znte system compound semiconductor single crystal, and semiconductor device: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first... Agent: Birch Stewart Kolasch & Birch

20080090388 - Method of fabricating semiconductor device and method for fabricating electronic device: A method for fabricating a semiconductor device, comprising: forming a semiconductor film on a substrate; and recrystallizing the semiconductor film using as a heat source flame of a gas burner that uses hydrogen and oxygen gas mixture as a fuel.... Agent: Oliff & Berridge, PLC

20080090387 - Method of making semiconductor element: A method of making a semiconductor element is provided. The method includes a step of forming a GaN layer doped with a p-type impurity on a substrate and a step of subjecting the GaN layer to activation process to form a p-type semiconductor layer. The activation process is performed with... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080090389 - Manufacturing method of semiconductor device and substrate processing apparatus: To provide a manufacturing method of a semiconductor device, comprising: loading a substrate, with a silicon surface exposed at a part of the substrate, into a processing chamber; heating an inside of said processing chamber; performing pre-processing of supplying at least silane-based gas, halogen-based gas, and hydrogen gas into said... Agent: Oliff & Berridge, PLC

20080090390 - Method for producing znte system compound semiconductor single crystal, znte system compound semiconductor single crystal, and semiconductor device: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first... Agent: Birch Stewart Kolasch & Birch

20080090391 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device from a semiconductor wafer having a first major surface, a recess provided inside a periphery on opposite side of the first major surface and surrounded by the periphery, and a second major surface provided at bottom of the recess is provided. The method... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080090392 - Technique for improved damage control in a plasma doping (plad) ion implantation: A technique for improved damage control in plasma doping (PLAD) ion implantation is disclosed. According to a particular exemplary embodiment, the technique may be realized as a method for improved damage control in plasma doping (PLAD) ion implantation. The method may comprise placing a wafer on a platen in a... Agent: Hunton & Williams LLP/varian Semiconductor, Equipment Associates, Inc.

20080090393 - Ultra shallow junction with rapid thermal anneal: Embodiments of the invention generally provide a method for forming an ultra shallow junction in a semiconductor device. In one embodiment, the method includes providing a silicon containing layer disposed on a substrate, implanting carbon and an elemental dopant into the silicon containing layer on the substrate, and annealing the... Agent: Patterson & Sheridan, LLP

20080090394 - Temperature synthesis of hexagonal zns nanocrystals as well as derivatives with different transition metal dopants using the said method: A method to fabricate semiconductor nanocrystals which comprises dissolving a metal source in a first solvent that contains at least one functional —OH group to form a mixture and heating the mixture to form a solution 1 and dissolving a X source in a second solvent which contains at least... Agent: Ratnerprestia

20080090395 - Method for producing p-type group iii nitride semiconductor and method for producing electrode for p-type group iii nitride semiconductor: The present invention provides a p-type group III nitride semiconductor production method which is excellent in terms of reliability and reproducibility. A photoresist mask is formed on a surface of an n−-GaN layer. Subsequently, an Mg film is formed so as to cover the n−-GaN layer and the photoresist mask,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080090396 - Light exposure apparatus and method for making semiconductor device formed using the same: An object of the present invention is to reduce variation in light exposure on an irradiation surface through a mask when the surface is exposed to laser light emitted from a laser source, whereby improving the throughput in light exposure of a substrate. Light exposure is performed using a solid-state... Agent: Nixon Peabody, LLP

20080090397 - Nonplanar transistors with metal gate electrodes: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of... Agent: Intel/blakely

20080090399 - Electrode for implantable device: An electrode includes a titanium substrate with a surface including an implanted layer of titanium oxy-nitride compounds.... Agent: Schwegman, Lundberg & Woessner, P.A.

20080090401 - Independently addressable interdigitated nanowires: An apparatus has multiple sets of independently addressable interdigitated nanowires. Nanowires of a set are in electrical communication with other nanowires of the same set and are electrically isolated from nanowires of other sets.... Agent: Hewlett Packard Company

20080090398 - Method for manufacturing a structure in a semiconductor device and a structure in a semiconductor device: The invention is concerned with a method for manufacturing a local wiring in a semiconductor device, comprising the manufacturing of at least two electrically conducting structures essentially in the same horizontal level in a layered stack on a substrate, the at least two electrically conducting structures being separated by a... Agent: Slater & Matsil LLP

20080090400 - Self-aligned in-contact phase change memory device: A memory cell and a method of making the same. An insulating material is deposited on a substrate. A via is produced in the substrate and a conductive lower block is disposed within the via. A step spacer comprised of insulating material is disposed in the via above the conductive... Agent: Ido Tuchman

20080090403 - Apparatus and method forming a contact to silicide and a contact to a contact: An apparatus and method for forming a contact to silicide through an active diffusion region, a contact to a contact through an active diffusion region, and a contact to a polysilicon structure through a shallow trench isolation region to create a conductive connection with a circuit node of interest. In... Agent: Sughrue Mion, PLLC

20080090402 - Densifying surface of porous dielectric layer using gas cluster ion beam: A method of fabricating and a structure of an integrated circuit (IC) incorporating a porous dielectric layer are disclosed. A metal line is formed in the porous dielectric layer. A gas cluster ion beam process is applied to the porous dielectric layer so that an upper portion of the dielectric... Agent: Hoffman, Warnick & D'alessandro LLC

20080090404 - Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes,... Agent: Macpherson Kwok Chen & Heid LLP

20080090405 - Composite solder tim for electronic package:

20080090406 - Via attached to a bond pad utilizing a tapered interconnect: Various embodiments include a method of forming an interconnect comprising forming at least two vias in a substrate, forming a conductive pad on a surface of the substrate, forming at least one tapered conductive segment on the surface of the substrate coupled to the conductive pad, wherein only a first... Agent: Schwegman, Lundberg & Woessner, P.A.

20080090407 - Terminal pad structures and methods of fabricating same: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.... Agent: Schmeiser, Olsen & Watts

20080090408 - Methods for controlling the profile of a trench of a semiconductor structure: Methods for controlling the profile of a trench of a semiconductor structure comprise the step of depositing a photoresist within a via and overlying a second dielectric layer. An image layer is deposited overlying the photoresist and is patterned to form a first trench having a first width and a... Agent: Ingrassia Fisher & Lorenz, P.C.

20080090409 - Method for manufacturing a semiconductor device including interconnections having a smaller width: A method for manufacturing a semiconductor device includes the steps of forming an interconnection layer including a top tungsten layer, forming a mask pattern on the tungsten layer, nitriding a portion of the tungsten layer in a plasma nitriding process to form a tungsten nitride layer, etching the tungsten nitride... Agent: Sughrue Mion, PLLC

20080090410 - Semiconductor device having oxidized metal film and manufacture method of the same: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080090411 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device is disclosed. The method includes the steps of forming a first insulating film having a contact plug on an upper portion of a semiconductor substrate; forming a second insulating film on an upper portion of the first insulating film and the contact plug;... Agent: Marshall, Gerstein & Borun LLP

20080090412 - Pre-silicide spacer removal: A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080090413 - Wafer via formation: A method of electrically conductive via formation in a fully processed wafer involves defining at least one trench area on a backside of the fully processed wafer, forming at least one trench within the trench area to an overall depth that will allow for a via formed within the trench... Agent: Morgan & Finnegan, L.L.P.

20080090414 - Manufacture of electroless cobalt deposition compositions for microelectronics applications: A method of preparing an aqueous electroless deposition composition for electrolessly depositing Co or a Co alloy onto a substrate in manufacture of microelectronic devices by treating water or an aqueous electroless deposition composition with a deoxygenating treatment to reduce the oxygen concentration.... Agent: Senniger Powers LLP

20080090415 - Substrate processing apparatus, method of manufacturing a semiconductor device, and method of forming a thin film on metal surface: There is provided a substrate processing apparatus equipped with a metallic component, with at least a part of its metallic surface exposed to an inside of a processing chamber and subjected to baking treatment at a pressure less than atmospheric pressure. As a result of this baking treatment, a film... Agent: Oliff & Berridge, PLC

20080090418 - Method for forming fine patterns of a semiconductor device using double patterning: A method for forming fine patterns of a semiconductor device is disclosed. The method includes forming an etch film on a substrate, forming a protection film on the etch film, forming a hard mask layer on the protection film, and forming a plurality of first mask patterns characterized by a... Agent: Volentine & Whitt PLLC

20080090416 - Methods of etching polysilicon and methods of forming pluralities of capacitors: A method of etching polysilicon includes exposing a substrate comprising polysilicon to a solution comprising water, HF, and at least one of a conductive metal nitride, Pt, and Au under conditions effective to etch polysilicon from the substrate. In one embodiment, a substrate first region comprising polysilicon and a substrate... Agent: Wells St. John P.s.

20080090417 - Upper electrode backing member with particle reducing features: Components of a plasma processing apparatus includes a backing member with gas passages attached to an upper electrode with gas passages. To compensate for the differences in coefficient of thermal expansion between the metallic backing member and upper electrode, the gas passages are positioned and sized such that they are... Agent: Buchanan, Ingersoll & Rooney PC

20080090419 - Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first... Agent: Volentine & Whitt PLLC

20080090420 - Method for manufacturing a semiconductor device: A method of manufacturing a semiconductor device according to the invention is an effective technique for ensuring a sufficient process margin and enabling the formation of a fine pattern in a peripheral circuit region. The method includes forming an anti-reflective layer with a varying thickness in a peripheral circuit region... Agent: Marshall, Gerstein & Borun LLP

20080090422 - Etching method: An etching method is described, including a first etching step that uses a first etching gas including a first fluorinated hydrocarbon compound, and a second etching step that uses a second etching gas including a second fluorinated hydrocarbon compound. The hydrogen content in the first fluorinated hydrocarbon compound is lower... Agent: Jianq Chyun Intellectual Property Office

20080090421 - Forming a sacrificial layer in order to realise a suspended element: The invention relates to a method of realization of a sacrificial layer, including the steps of: lithography of a resin deposited on a substrate in order to supply a lithographed resist pattern on a substrate zone, the zone having a given size and a given form, the pattern occupying a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080090423 - Gas switching during an etch process to modulate the characteristics of the etch: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while... Agent: Texas Instruments Incorporated

20080090424 - Method of forming an oxinitride layer: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first... Agent: Mills & Onello LLP

20080090425 - Two-step post nitridation annealing for lower eot plasma nitrided gate dielectrics: A method of forming a dielectric film that includes nitrogen. The method includes incorporating nitrogen into a dielectric film using a plasma nitridation process to form a silicon oxynitride film. The silicon oxynitride film is annealed first in an inert or reducing ambient at a temperature ranging between about 700°... Agent: Patent Counsel Applied Materials, Inc.

20080085568 - Method for repairing bonded metallic structures: A method of repairing a bonded metallic structure having a first metallic member bonded to a second metallic member is provided. The method includes the steps of: A) forming a hole in at least one of the first metallic member and second metallic member, wherein said hole is sufficiently configured... Agent: General Motors Corporation Legal Staff

20080085570 - Distinguishing between dopant and line width variation components: A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is... Agent: Williams, Morgan & Amerson

20080085569 - Method of using electrical test structure for semiconductor trench depth monitor: Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be... Agent: Texas Instruments Incorporated

20080085567 - Tunneling magnetoresistive element, semiconductor junction element, magnetic memory and semiconductor light emitting element: A pin junction element includes a ferromagnetic p-type semiconductor layer and a n-type semiconductor layer which are connected via an insulating layer, and which shows a tunneling magnetic resistance according to the magnetization of the ferromagnetic p-type semiconductor layer and the magnetization of the ferromagnetic n-type semiconductor layer. In this... Agent: Harness, Dickey & Pierce, P.L.C

20080085571 - Die bonder and die bonding method thereof: A die bonder and a die bonding method thereof are provided. The die bonder includes a wafer platform, an arranging platform, a conveyer, at least one first pick-up device and a second pick-up device. The wafer platform is for placing a wafer with several dies. The conveyer is for carrying... Agent: Birch Stewart Kolasch & Birch

20080085572 - Semiconductor packaging method by using large panel size: The present invention discloses a semiconductor packaging method, comprises steps of back lapping a processed silicon wafer to a desired thickness. Then, the dice are separated from the processed and lapped wafer into a single die. Then, the dice are picked and placed on a tool, an active surface of... Agent: Kusner & Jaffe Highland Place Suite 310

20080085573 - Underfill dispense at substrate aperture: Disclosed are methods for dispensing underfill material in an IC assembly having a die mounted on a substrate with a gap therebetween. One or more aperture is provided in the substrate for receiving underfill material into the gap. Underfill material is dispensed into the gap through the one or more... Agent: Texas Instruments Incorporated

20080085574 - Antifuse one time programmable memory array and method of manufacture: A method for making a one time programmable (OTP) memory array includes providing a wafer comprising a buried insulator layer and a semiconductor layer over the buried insulator layer and forming a plurality of bit lines in the semiconductor layer. Each of the plurality of bit lines comprise a portion... Agent: Freescale Semiconductor, Inc. Law Department

20080085575 - Dual work-function single gate stack: Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080085576 - Manufacturing method for semiconductor device: Disclosed is a manufacturing method for a semiconductor device capable of uniformly and stably silicidating an entire gate. The method includes: forming a gate oxide layer and a polysilicon pattern on a substrate; forming a spacer on a sidewall of the gate oxide layer and the polysilicon pattern; forming a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080085577 - Method of manufacturing complementary metal oxide semiconductor transistor: A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate,... Agent: North America Intellectual Property Corporation

20080085578 - Method of manufacturing semiconductor integrated circuit: A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs constituting the logic part and the... Agent: Sonnenschein Nath & Rosenthal LLP

20080085579 - Semiconductor structure with high-voltage sustaining capability and fabrication method of the same: A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080085580 - Methods for uniform doping of non-planar transistor structures: Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric... Agent: Intel/blakely

20080085581 - Methods of forming a semiconductor device that allow patterns in different regions that have different pitches to be connected: Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second... Agent: Myers Bigel Sibley & Sajovec

20080085582 - Hand-type nonvolatile memory device and method of forming the same: Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed... Agent: Myers Bigel Sibley & Sajovec

20080085583 - Method of manufacturing a non-volatile memory device: A method of manufacturing a non-volatile memory device includes forming a tunnel isolation layer forming a tunnel isolation layer on a substrate, forming a conductive pattern on the tunnel isolation layer, forming a lower silicon oxide layer on the conductive pattern, treating a surface portion of the lower silicon oxide... Agent: Lee & Morse, P.c.

20080085584 - Oxidation/heat treatment methods of manufacturing non-volatile memory devices: Methods of manufacturing non-volatile memory devices are disclosed which may at least partially cure etch damage and may at least partially remove defect sites in gate structures of the devices caused during manufacturing of the devices. An exemplary method of manufacturing a non-volatile memory device includes forming a gate structure... Agent: Myers Bigel Sibley & Sajovec

20080085585 - Structure and method for creation of a transistor: The invention is directed to an improved transistor that reduces dopant cross-diffusion and improves chip density. A first embodiment of the invention comprises gate electrode material partially removed at a junction of a first gate electrode region comprised of gate material doped with first ions for a first device and... Agent: International Business Machines Corporation Dept. 18g

20080085586 - Semiconductor device: A semiconductor device manufactured by forming a plurality of first trenches in each of which a trench gate is formed, in an epitaxial layer of a first conductivity type; implanting an impurity of a second conductivity type into a part beneath each of the first trenches to form a first... Agent: Mcginn Intellectual Property Law Group, Pllc

20080085587 - Epitaxial silicon growth: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric... Agent: Brooks, Cameron & Huebsch , Pllc

20080085588 - Method of arranging dies in a wafer for easy inkless partial wafer process: In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle pattern (602) that is configured by arranging the dies in an array having m rows and n columns, where the m rows start in... Agent: Texas Instruments Incorporated

20080085589 - Fabrication of strained silicon film via implantation at elevated substrate temperatures: A strained-silicon film is disclosed. A silicon-germanium film is made by ion implantation of germanium into an epitaxial silicon layer, preferably at a temperature in the range of 200 C to 400 C. The wafer is annealed in situ or optionally after implantation. A silicon film is applied to the... Agent: Lsi Corporation

20080085590 - Method of making fusi gate and resulting structure: Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stack height, removing the second polysilicon layer... Agent: Slater & Matsil, L.l.p.

20080085592 - Method for manufacturing semiconductor device: A predetermined pattern containing a plurality of gate patterns, in the process of formation thereof, is classified into fine gate patterns and the other patterns (S102), and a hard mask film is formed on a process target film (S106). Next, a first resist film having a fine first pattern is... Agent: Young & Thompson

20080085591 - Novel gate structure with low resistance for high power semiconductor devices: In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the... Agent: Macpherson Kwok Chen & Heid LLP

20080085593 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080085594 - Silver-containing nanoparticles with replacement stabilizer: A process including: providing a composition comprising silver-containing nanoparticles and molecules of an initial stabilizer on the surface of the silver-containing nanoparticles; and mixing a replacement stabilizer comprising a carboxylic acid with the composition to replace at least a portion of the initial stabilizer with the replacement stabilizer, resulting in... Agent: Patent Documentation Center Xerox Corporation

20080085595 - Method of providing solder bumps on a substrate using localized heating: A method of providing electrically conductive bumps on electrode pads of a microelectronic substrate. The method includes: providing a microelectronic substrate including electrode pads exhibiting an electrode pad pattern; providing solder portions onto respective ones of the electrode pads according to the electrode pad pattern; reflowing the solder portions to... Agent: Blakely Sokoloff Taylor & Zafman

20080085596 - Post passivation interconnection schemes on top of ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080085597 - Post passivation interconnection schemes on top of ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080085599 - Alignment mark, use of a hard mask material, and method: In a method to produce an alignment mark, an oxide layer and sacrificial layer are processed to comprise recesses. The recesses are filled with a filler material. During filling the recesses, a layer of filler material is formed on the sacrificial layer. The layer of filler material is removed by... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080085601 - Method of forming fine contact hole and method of fabricating semiconductor device using block copolymers: A method of forming a contact hole includes forming a plurality of lower patterns on a substrate. An insulation layer is formed on the lower patterns. A self-assemble induction layer is formed on the insulation layer. A recess is formed in the self-assemble induction layer in alignment with the lower... Agent: F. Chau & Associates, Llc

20080085600 - Method of forming lithographic and sub-lithographic dimensioned structures: A method of forming lithographic and sub-lithographic dimensioned structures. The method includes forming a mandrel layer on a top surface of an underlying layer and then forming a masking layer on a top surface of the mandrel layer; patterning the masking layer into a pattern of islands; transferring the pattern... Agent: Schmeiser, Olsen & Watts

20080085598 - Method of patterning contact holes: A method forms a blocking mask first and then patterns a contact hole mask over the blocking mask to provide a method of patterning contact holes in a substrate. This method first forms a blocking layer on the substrate and then patterns the blocking layer to have first openings to... Agent: Frederick W. Gibb, Iii Gibb & Rahman, Llc

20080085602 - Slurry composition for a chemical mechanical polishing process and method of manufacturing a semiconductor device using the slurry composition: A slurry composition for a chemical mechanical polishing process and a method of manufacturing a semiconductor memory device using the slurry composition are provided. The slurry composition may include about 0.001 percent by weight to about 5 percent by weight of a ceria abrasive, about 0.001 percent by weight to... Agent: Harness, Dickey & Pierce, P.L.C

20080085603 - Gate etch process for a high-voltage fet: A method, in one embodiment, includes etching first and second dielectric regions in a substantially isotropic manner through first and second openings of a mask layer to create first and second trenches. The first and second dielectric regions are disposed on opposite sides of a mesa of semiconductor material, the... Agent: The Law Offices Of Bradley J. Bereznak

20080085604 - Plasma treatment method and plasma etching method: The present invention develops a process for plasma treatment using a gas having no greenhouse effect in order to realize global environmental preservation and sophistication of plasma process performance and provides a process for plasma etching with high accuracy which process can depress damage to devices. The process for plasma... Agent: Sughrue Mion, Pllc

20080085605 - Dry etching method of insulating film: It is an object to provide a high-precision method for forming deep holes of elliptic pattern, which can improve hole directionality on the short diameter side, the hole directionality being possibly deteriorated as a result of excessive polymer deposition in the initial etching stage. The insulating film dry etching method... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080085606 - Method for fabricating a structure for a semiconductor component, and semiconductor component: In one aspect, the invention provides a fabrication method. Before the fabrication of the structure, a mask layer, for example a hard mask, is applied to a layer. The mask layer has at least two layers composed of materials that can be etched selectively with respect to one another. In... Agent: Slater & Matsil, L.l.p.

20080085608 - Method for manufacturing semiconductor device: In the process of forming a predetermined pattern in a process target film, a stacked hard mask film having a first film, a second film and a third film stacked in this order is formed on the process target film (S100), fine line patterns are formed in the third film... Agent: Young & Thompson

20080085607 - Method for modulating stresses of a contact etch stop layer: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected... Agent: Slater & Matsil, L.l.p.

20080085609 - Method for protecting high-topography regions during patterning of low-topography regions: A method for protecting at least one high-topography region on a substrate having both the at least one high-topography region and the at least one low-topography region is provided. The method comprises patterning a thick photo-resist layer having a first thickness, such that the thick photo-resist layer is formed on... Agent: Freescale Semiconductor, Inc. Law Department

20080085610 - Ald of metal silicate films: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a silicon source chemical, metal source chemical, and an oxidizing agent, wherein the metal source chemical is the next reactant provided after the silicon source chemical. Methods according... Agent: Knobbe, Martens, Olsen & Bear LLP

20080085611 - Deposition and densification process for titanium nitride barrier layers: In one embodiment, a method for forming a titanium nitride barrier material on a substrate is provided which includes depositing a titanium nitride layer on the substrate by a metal-organic chemical vapor deposition (MOCVD) process, and thereafter, densifying the titanium nitride layer by exposing the substrate to a plasma process.... Agent: Patterson & Sheridan, LLP

20080085612 - Method to deposit conformal low temperature sio2: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern... Agent: Micron Technology, Inc.

20080081380 - Method for leakage reduction in fabrication of high-density fram arrays: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and... Agent: Texas Instruments Incorporated

20080081382 - Method for reducing layout-dependent variations in semiconductor devices: A method for forming an integrated circuit includes providing a semiconductor substrate, forming a re-implantation blocking layer over the semiconductor substrate, forming a mask over the re-implantation blocking layer, patterning the mask to form an opening, wherein a portion of the re-implantation blocking layer is exposed through the opening, performing... Agent: Slater & Matsil, L.L.P.

20080081383 - Offset correction techniques for positioning substrates: A method for calculating a process center for a chuck in a processing chamber is provided. The method includes generating pre-processing and post-processing measurement data points, which is perform by measuring thickness of a film substrate at a set of orientations and a set of distances from a geometric center... Agent: Ipsg, P.C.

20080081386 - Through-die metal vias with a dispersed phase of graphitic structures of carbon for reduced thermal expansion and increased electrical conductance: A method, apparatus and various material-architectures in an electrically conductive through die via formed of a composite material with a continuous phase of matrix metal and a dispersed phase of graphitic structures of carbon, wherein bulk material properties of the composite material differ from similar bulk material properties of the... Agent: Intel Corporation C/o Intellevate, LLC

20080081387 - Manufacturing method of liquid discharge head and orifice plate: There is disclosed a manufacturing method in which depths of individual liquid chambers can be set to be small. The manufacturing method is a manufacturing method of a liquid discharge head having a liquid chamber which communicates with a discharge port for discharging a liquid, and includes: etching a first... Agent: Fitzpatrick Cella Harper & Scinto

20080081388 - Composite nanostructure apparatus and method: A metal is deposited onto a surface electrochemically using a deposition solution including a metal salt. In making a composite nanostructure, the solution further includes an enhancer that promotes electrochemical deposition of the metal on the nanostructure. In a method of forming catalyzing nanoparticles, the metal preferentially deposits on a... Agent: Hewlett Packard Company

20080081391 - Mems device with roughened surface and method of producing the same: A method of producing a MEMS device provides a MEMS apparatus having released structure. The MEMS apparatus is formed at least in part from an SOI wafer having a first layer, a second layer spaced from the first layer, and an insulator layer between the first layer and second layer.... Agent: Bromberg & Sunstein LLP

20080081392 - Method for the compensation of deviations occurring as a result of manufacture in the manufacture of micromechanical elements and their use: The invention relates to a method for the compensation of deviations occurring as a result of manufacture in the manufacture of micromechanical elements and their use which should be deflected at a resonant frequency. It is therefore the object of the invention to compensate deviations which occur due to manufacture... Agent: Barnes & Thornburg LLP

20080081394 - Manufacturing method of solid-state imaging device: A manufacturing method of a solid-state imaging device includes: forming a first and second insulating films having different properties on a silicon substrate such that they cover sides of gate electrodes formed on the silicon substrate; subjecting the second insulating film to selective etching, and forming sidewalls on the sides... Agent: Sonnenschein Nath & Rosenthal LLP

20080081381 - Method for fabricating semiconductor devices: A semiconductor device fabrication method that improves the efficiency of semiconductor device production. A plurality of wafer substrates are set and a process for fabricating semiconductor devices each having a ferroelectric capacitor is begun. After ferroelectric layers are formed over the plurality of wafer substrates, the ferroelectric layers formed are... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080081385 - Methods and systems for inspection of wafers and reticles using designer intent data: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the... Agent: Baker & Mckenzie LLP

20080081384 - Semiconductor device fabrication method and semiconductor device fabrication system: A semiconductor device fabrication method is disclosed. The method comprises an insulating film forming step of forming an insulating film on a semiconductor substrate; a trench forming step of forming a trench for device isolation in a predetermined part of the semiconductor substrate; a trench filling step of forming a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080081389 - Organic multicolor emission and display device and method for manufacturing same: A transparent first substrate and a second substrate of an organic multicolor emission and display device are positioned opposite to each other with a predetermined clearance and sealed with a gap material that performs desiccating a surrounding atmosphere. The gap material advantageously has different void fractions between in an inner... Agent: Rossi, Kimms & Mcdowell LLP.

20080081390 - Nitride-based light emitting heterostructure: An improved nitride-based light emitting heterostructure is provided. The nitride-based light emitting heterostructure includes an electron supply layer and a hole supply layer with a light generating structure disposed there between. The light generating structure includes a set of barrier layers, each of which has a graded composition and a... Agent: Hoffman Warnick & D'alessandro, LLC

20080081393 - Image sensors for reducing dark current and methods of fabricating the same: An image sensor includes a semiconductor substrate of a first conductivity type, a photodiode of a second conductivity type located in the substrate, a hole accumulated device (HAD) region of the first conductivity type located over the photodiode, a thin surface diffusion region formed on the surface of the HAD... Agent: Volentine & Whitt PLLC

20080081395 - Wafer level package structure of optical-electronic device and method for making the same: A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a... Agent: Rabin & Berdo, PC

20080081396 - Method of fabricating image sensor having inner lens: A method of fabricating an image sensor according to example embodiments may include forming a photodiode in a photoelectric conversion region of a substrate and forming an etch stop layer on the substrate. The etch stop layer may be patterned to form an inner lens on the photoelectric conversion region... Agent: Harness, Dickey & Pierce, P.L.C

20080081397 - Process for preparing a semiconductor structure for mounting: A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to... Agent: Patent Law Group LLP

20080081398 - Cap wafer for wafer bonded packaging and method for manufacturing the same: The present invention relates to semiconductor device manufacturing techniques, and specifically to a field of device packaging techniques at wafer level. More specifically, it relates to a cap wafer for wafer bonding application that is bonded to top part of a device wafer. The method of the present invention excludes... Agent: The Webb Law Firm, P.C.

20080081399 - Manufacturing method of semiconductor apparatus: A manufacturing method of a semiconductor apparatus, comprising the steps of: forming a plurality of leads corresponding to a plurality of semiconductor apparatuses on an electrically conductive sheet; disposing a plurality of semiconductor elements in predetermined positions of the electrically conductive sheet; connecting between a bonding pad of a semiconductor... Agent: SocalIPLaw Group LLP

20080081400 - Device transfer method and display apparatus: A device transfer method and a display apparatus are provided. A device transfer method and a display apparatus are provided by or in which, in transferring devices arranged on a substrate onto another substrate, it is possible to easily strip the substrate after the transfer of the devices, to lower... Agent: Bell, Boyd & Lloyd, LLP

20080081401 - Semiconductor device and manufacturing method thereof: The present invention provides a method for manufacturing a semiconductor device, which is capable of suppressing an overflow of a sealing resin and obtaining good sealing quality, simply and at low cost. Further, the present invention provides a semiconductor device that suppresses an overflow of a sealing resin and has... Agent: Rabin & Berdo, PC

20080081402 - Method for fabricating mos-fet: e

20080081403 - Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations: By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20080081405 - Method for fabricating a semiconductor device with a finfet: A method for fabricating a semiconductor device includes forming a device isolation structure in a substrate to define active regions, forming a hard mask pattern to open a region defining an active region pattern and to cover the device isolation structure, forming the active region pattern by selectively recessing the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080081404 - Recessed sti for wide transistors: A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic... Agent: Texas Instruments Incorporated

20080081406 - Method of fabricating semiconductor device having dual stress liner: A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the... Agent: F. Chau & Associates, LLC

20080081407 - Protective coating for mark preservation: A polymer coating material is disposed at a surface of a semiconductor substrate, superimposing a readable mark formed thereupon. A perimeter of the coating material is configured to correspond approximately with a perimeter of the mark, and a thickness of the coating material is configured to be relatively conformal with... Agent: Intel/blakely

20080081408 - Method for manufacturing semiconductor device: A semiconductor device manufacturing method including forming a dummy capacitor in a fuse region to avoid a step height between plate electrodes in a cell region and in a fuse region, is disclosed herein. The method can be used so that only an insulating film at a target thickness may... Agent: Marshall, Gerstein & Borun LLP

20080081409 - Method of manufacturing memory device: A method of manufacturing a memory device that improves electrical characteristics of an MIM capacitor using a zirconium oxide film (ZrO2) as a dielectric film includes: forming a lower metal electrode on a semiconductor substrate; forming a two or more-layered dielectric film including zirconium oxide films on the lower metal... Agent: F. Chau & Associates, LLC

20080081410 - Multi-bit memory technology (mmt) and cells: m

20080081412 - Method of forming hardmask pattern of semiconductor device: A method of forming a hardmask pattern over a semiconductor device semiconductor device includes forming a first hardmask layer over a semiconductor substrate. First and second structures are formed over the first hardmask layer, the first and second structures formed of the same material, the first and second structures defining... Agent: Townsend And Townsend And Crew, LLP

20080081415 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device. According to a method of manufacturing a flash memory device, since it comprises the steps of providing a semiconductor substrate including a cell region and a peripheral circuit region, forming a first oxide film and a nitride film subsequently over the semiconductor... Agent: Marshall, Gerstein & Borun LLP

20080081411 - Methods of manufacturing non-volatile memory devices: In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as... Agent: Myers Bigel Sibley & Sajovec

20080081414 - Nonvolatile memory device and method for fabricating the same: A method for fabricating a nonvolatile memory device comprises providing a substrate, forming an insulating layer and a conductive layer on the substrate, forming an electrical connection path out of a portion of the conductive layer, through which the conductive layer is electrically connected to the substrate, and gate patterning... Agent: Volentine & Whitt PLLC

20080081413 - Semiconductor memory devices and methods for forming the same: A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged... Agent: Myers Bigel Sibley & Sajovec

20080081416 - Methods of forming flash memory device: The present disclosure relates to methods of forming a flash memory device. A plurality of cells, a plurality of select transistors, and a transistor are formed over a semiconductor substrate including a cell region and a peripheral region. An insulating layer is formed on the entire surface. Metal contact holes... Agent: Marshall, Gerstein & Borun LLP

20080081417 - Method of manufacturing flash memory device: Disclosed herein is a method of fabricating a flash memory device. The method includes providing a semiconductor substrate that includes an active region and a field region. A tunnel insulating layer and a first conductive layer are formed in the active region, and an isolation structure is formed in the... Agent: Marshall, Gerstein & Borun LLP

20080081418 - Method of forming non-volatile memory device: A method of fabricating a non-volatile memory device, wherein a gate insulating layer, a first conductive layer, a tunneling layer, a trap nitride layer, a blocking oxide layer, and a capping layer are sequentially formed over a semiconductor substrate of a peripheral region. A contact region of the capping layer... Agent: Marshall, Gerstein & Borun LLP

20080081419 - Providing local boosting control implant for non-volatile memory: A substrate of a non-volatile storage system includes selected regions in which additional ions are deeply implanted during the fabrication process. NAND strings are formed over the selected regions such that end word lines of the NAND strings are over the deeply implanted ions. The presence of the deeply implanted... Agent: Vierra Magen/sandisk Corporation

20080081420 - Method for fabricating fin transistor: A method for fabricating a fin transistor includes patterning a first pad layer provided over a substrate using an isolation mask, etching the substrate using the isolation mask and the first pad layer to form trenches, filling the trenches with an insulating material to form isolation structures, etching the isolation... Agent: Townsend And Townsend And Crew, LLP

20080081421 - Dual polysilicon gate of semiconductor device with multi-plane channel and fabrication method thereof: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled... Agent: Townsend And Townsend And Crew, LLP

20080081422 - Method of manufacturing semiconductor apparatus: A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside... Agent: Mcginn Intellectual Property Law Group, PLLC

20080081423 - Processes and packaging for high voltage integrated circuits, electronic devices, and circuits: The present invention includes processes and packaging for high voltage integrated circuits (ICs), high voltage electronic devices and high voltage electronic circuits which operate over a wide range of voltages, e.g., from tens of volts to tens of thousands of volts. The inventive processes and packaging are particularly suitable for... Agent: Morriss Obryant Compagni, P.C.

20080081424 - Method of production of a semiconductor memory device and semiconductor memory device: A layer of electrically conductive material is applied above a carrier surface. Gate electrodes are formed above a first area of the carrier surface from the electrically conductive material. An implantation of a dopant that is provided for source/drain regions is performed in the first area. The implant is annealed,... Agent: Slater & Matsil LLP

20080081425 - Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors: Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors, wherein a collector semiconductor region is created, an etch stop layer is created on a connection region, an opening is introduced into this etch stop layer, semiconductor material, which is formed as a single crystal at least in the collector semiconductor... Agent: Mg-ip Law, PLLC

20080081426 - Semiconductor device having mos varactor and methods for fabricating the same: A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and... Agent: Volentine & Whitt PLLC

20080081427 - Method of forming a micromechanical system containing a microfluidic lubricant channel: Embodiments of the present invention generally relate to a electromechanical device that has an improved usable lifetime due to the presence of one or more channels that contain and deliver a lubricant material that can reduce the likelihood of stiction occurring between the various moving parts of the device. Embodiments... Agent: Patterson & Sheridan, L.L.P.

20080081428 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device, wherein a first insulating layer is formed over a semiconductor substrate. First insulating layer is etched to form a resistor hole. A first conductive layer is formed to fill the resistor hole and is planarized to form a resistor. A second insulating... Agent: Marshall, Gerstein & Borun LLP

20080081429 - Method for fabricating capacitor in semiconductor device: A method for fabricating capacitor in a semiconductor device includes forming an sacrificial layer and over a substrate, forming a mask pattern over the sacrificial layer, etching the sacrificial layer in two steps with differentiated top and bottom power levels using the mask pattern as an etch mask to form... Agent: Blakely Sokoloff Taylor & Zafman

20080081430 - Method for fabricating capacitor in semiconductor device: A method for forming a capacitor in a semiconductor device is disclosed. The method includes forming a storage node electrode on a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the storage node electrode, depositing a plate electrode on the dielectric layer, thereby forming by-product impurities,... Agent: Marshall, Gerstein & Borun LLP

20080081431 - Method for fabricating a capacitor: A method for fabricating a capacitor includes forming an isolation layer over a substrate. The isolation layer forms a plurality of open regions. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage... Agent: Townsend And Townsend And Crew, LLP

20080081433 - Method for forming a shallow trench isolation structure: A method for forming a shallow trench isolation structure, comprising the steps of: sequentially forming a pad oxide layer and an etch barrier layer on a semiconductor substrate, and sequentially defining the etch barrier layer, the pad oxide layer, and the substrate to form a trench; forming a liner oxide... Agent: Squire, Sanders & Dempsey L.L.P.

20080081432 - Semiconductor device with trench gate type transistor and method of manufacturing the same: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which... Agent: F. Chau & Associates, LLC

20080081434 - Method for forming isolation structure in semiconductor device: A method for forming an isolation structure in a semiconductor device includes preparing a semi-finished substrate including a trench. An oxide layer is formed over sidewalls of the trench. A multiple layer structure of liner layers is formed over the oxide layer. An insulation layer is formed over the multiple... Agent: Blakely Sokoloff Taylor & Zafman

20080081435 - Method for fabricating semiconductor element: According to this invention, a method for fabricating a semiconductor element comprises the steps of: providing a semiconductor wafer; forming an oxide layer on the semiconductor wafer; carrying out a high-temperature thermal treatment to the semiconductor wafer at least once, wherein the high-temperature thermal treatment comprises a final high-temperature treatment,... Agent: Rabin & Berdo, PC

20080081436 - Mos transistor on an soi substrate with a body contact and a gate insulating film with variable thickness: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080081437 - Active device array substrate and cutting method thereof: A structure of the active device array substrate and the cutting method thereof are provided. The leads laid on the surface of the active device array substrate to electrically connect the bond pads and the short rings have high transmittance for the laser light. After the large-scale active device array... Agent: Jianq Chyun Intellectual Property Office

20080081438 - Logical grouping of wafers in semiconductor processing: Embodiments of logical groups of wafers in semiconductor processing are presented herein.... Agent: Lee & Hayes, PLLC

20080081439 - Method of manufacturing semiconductor nanowires: A method is shown for manufacturing silicon semiconductor nanowires on graphite cloth conducting substrates. The nanowires are grown on the substrate by first depositing a thin gold film on the graphite cloth using RF sputtering. The substrate structure is then exposed to dilute silane, resulting in a uniform coating of... Agent: Whitaker, Chalk, Swindle & Sawyer, LLP

20080081440 - Method of forming a semiconductor device having trench charge compensation regions: In one embodiment, a method of forming a semiconductor device with trench charge compensation structures includes exposing the trench sidewalls to a reduced temperature hydrogen desorption process to enhance the formation of monocrystalline semiconductor layers.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20080081442 - Methods of forming a pattern and methods of manufacturing a memory device using the same: In a method of forming a pattern, a sacrificial layer pattern and a stop layer pattern for preventing or reducing an epitaxial growth may be formed on a substrate. The sacrificial layer pattern may have a first hole therethrough, and the first hole partially exposes a top surface of the... Agent: Harness, Dickey & Pierce, P.L.C

20080081441 - Methods of forming semiconductor structures and systems for forming semiconductor structures: A method and system for forming a semiconductor structure includes forming at least one material layer over a substrate. At least one portion of the material layer is etched with at least one first precursor, thereby defining at least one material pattern. Charges attached to the material pattern are removed... Agent: Duane Morris LLPIPDepartment (tsmc)

20080081443 - Method for fabricating semiconductor: According to the present invention, a method for fabricating a semiconductor device using a Silicon-On-Sapphire (SOS) wafer comprises a process for preparing a sapphire substrate, a process for forming a silicon (Si) layer on the sapphire substrate, a process for implanting silicon ions in the silicon layer, and a process... Agent: Rabin & Berdo, PC

20080081444 - Method for forming silicide layer on a silicon surface and its use: A method for forming a silicide layer on a silicon surface is provided. First, inert gas ions are implanted into the silicon surface. Then, a metal layer is formed on the surface and subsequently converted into the suicide layer. Thereby the resistance of the silicide can be reduced and the... Agent: Nixon Peabody LLP - Patent Group

20080081446 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a first pattern over a substrate, forming an oxide-based layer over the first pattern, forming a hard mask layer over the oxide-based layer, etching the hard mask layer at a first substrate temperature, and etching the oxide-based layer to form a... Agent: Blakely Sokoloff Taylor & Zafman

20080081445 - Method of forming a high-k film on a semiconductor device: According to the present invention, high-k film can be etched to provide a desired geometry without damaging the silicon underlying material. A silicon oxide film 52 is formed on a silicon substrate 50 by thermal oxidation, and a high dielectric constant insulating film 54 comprising HfSiOx is formed thereon. Thereafter,... Agent: Young & Thompson

20080081448 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming an insulation layer, a first electrode layer, a second electrode layer, and a hard mask over a substrate, etching the second electrode layer to form second electrodes with recessed sidewalls, forming a passivation layer over a resultant surface profile provided after... Agent: Blakely Sokoloff Taylor & Zafman

20080081449 - Method for fabricating semiconductor device including recess gate: A method for fabricating a semiconductor device includes etching a substrate to form a first trench pattern, forming spacers over sidewalls of the first trench pattern, etching a bottom portion of the first trench pattern using the spacers as a barrier to form a second trench pattern, performing an isotropic... Agent: Blakely Sokoloff Taylor & Zafman

20080081447 - Method for manufacturing recess gate in a semiconductor device: A method for manufacturing a recess gate in a semiconductor device includes forming a device isolation structure on a substrate to define an active region, forming a hard mask pattern over the substrate to selectively expose at least a portion of the active region, forming a recess pattern in the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080081450 - Method of manufacturing a flash memory device: In a method of manufacturing an SONOS type flash memory device, a first oxide layer and a buffer poly layer are formed over a surface of a semiconductor except for a memory cell region of a cell region. A second oxide layer, a nitride layer and a third oxide layer... Agent: Townsend And Townsend And Crew, LLP

20080081451 - Method of manufacturing flash memory device: A method of manufacturing a non-volatile memory device includes forming a conductive layer to form a gate on a semiconductor substrate; forming a hard mask over the conductive layer; patterning the hard mask and the conductive layer of a cell region to form the gate; partially recessing the hard mask... Agent: Townsend And Townsend And Crew, LLP

20080081452 - Method of forming tungsten polymetal gate having low resistance: A tungsten polymetal gate is made by forming a gate insulation layer and a polysilicon layer on a semiconductor substrate; depositing a barrier layer on the polysilicon layer; depositing a tungsten nucleation layer on the barrier layer through an ALD process; depositing a tungsten layer on the tungsten nucleation layer... Agent: Ladas & Parry LLP

20080081453 - Method of forming metal wire of semiconductor device: A method of forming a metal line of a semiconductor device includes the steps of forming an insulating layer and a glue layer on a semiconductor substrate, removing a portion of the glue layer and the insulating layer to form trenches, forming a metal layer over the semiconductor substrate including... Agent: Marshall, Gerstein & Borun LLP

20080081454 - Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance: When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even an adjacent fuse due... Agent: Young & Thompson

20080081455 - Methods of forming a single layer substrate for high capacity memory cards: Methods of forming a semiconductor package including a single-sided substrate are disclosed. In a first embodiment of the present invention, a substrate may include a conductive layer on a top surface of the substrate, i.e., on the same side of the substrate as where the die are mounted. In a... Agent: Vierra Magen/sandisk Corporation

20080081456 - Chip-on-board package having flip chip assembly structure and manufacturing method thereof: A chip-on-board (COB) package has a flip chip assembly structure and is used for an integrated circuit (IC) card. The COB package has conductive patterns as contact terminals on an outer surface of a non-conductive film, and an IC chip on an inner surface of the film. The film has... Agent: Marger Johnson & Mccollom, P.C.

20080081457 - Integrated circuit chips with fine-line metal and over-passivation metal: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node... Agent: John Chen

20080081458 - Integrated circuit chips with fine-line metal and over-passivation metal: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node... Agent: John Chen

20080081459 - Dual layer dielectric stack for microelectronics having thick metal lines: Embodiments of the invention include apparatuses and methods relating to dual layer dielectric stacks for thick metal lines of microelectronic devices. In one embodiment, the dual layer dielectric stack includes a first dielectric layer that is planar and mechanically strong and the second dielectric layer can be patterned by photolithography... Agent: Intel Corporation C/o Intellevate, LLC

20080081460 - Method of manufaturing a semiconductor device: In a method of manufacturing a semiconductor device, a preliminary insulating layer is formed on a substrate. A photoresist pattern is formed on the preliminary insulating layer. A central portion of the preliminary insulating layer is partially etched using the photoresist pattern as an etch mask to form a preliminary... Agent: Mills & Onello LLP

20080081462 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a plurality of memory cells and transistors over a substrate, forming a first stopping layer having tensile stress over the plurality of memory cells and transistors, forming a first insulation layer over the substrate and the first stopping layer, and forming... Agent: Lowe Hauptman Ham & Berner, LLP

20080081463 - Method for fabricating storage node contact in semiconductor device: A method for forming a storage node contact in a semiconductor device includes forming a first insulation layer over a substrate including a landing plug, forming bit lines over the first insulation layer, each bit line including a bit line tungsten layer and a bit line hard mask, forming a... Agent: Blakely Sokoloff Taylor & Zafman

20080081461 - Method of forming pad patterns using self-align double patterning method, pad pattern layout formed using the same, and method of forming contact holes using self-align double patterning method: A self-align patterning method for forming patterns includes forming a first layer on a substrate, forming a plurality of first hard mask patterns on the first layer, forming a sacrificial layer on top surfaces and sidewalls of the first hard mask patterns, thereby forming a gap between respective facing portions... Agent: Lee & Morse, P.C.

20080081465 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced... Agent: Marshall, Gerstein & Borun LLP

20080081464 - Method of integrated substrated processing using a hot filament hydrogen radical souce: A method of integrated processing is provided for a substrate in the substrate processing tool. The substrate contains an etch feature in a dielectric film and an exposed metal interconnect pattern formed underneath the etch feature. The integrated process includes pretreating exposed surfaces of the etch feature and the exposed... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080081466 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, includes forming an opening in a first film, embedding an alignment mark material for alignment with an upper layer in the opening, forming a second film on the first film in which the alignment mark material is embedded, irradiating the second film formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080081467 - Method for manufacturing semiconductor device: A first insulating film, a second insulating film, a first resist pattern is formed on a semiconductor substrate, the second insulating film is etched to form a second-insulating-film pattern, a third insulating film is deposited over the second-insulating-film pattern to form a third-insulating-film pattern, the first insulating film is etched... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080081468 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes the steps of: forming recesses (a via hole and wiring grooves) in a insulation film; forming a seal layer on inside surfaces of the recesses by using a gas based on a silane having an alkyl group as a precursor; applying EB-cure... Agent: Sonnenschein Nath & Rosenthal LLP

20080081469 - Method for forming contact plug in a semiconductor device: A method for forming a contact plug in a semiconductor device includes providing a substrate having an insulation layer. A hard mask pattern is formed over the insulation layer. The insulation layer is etched using the hard mask pattern to form a contact hole. A plug material is formed over... Agent: Townsend And Townsend And Crew, LLP

20080081470 - Method for forming strained silicon nitride films and a device containing such films: A method for forming a strained SiN film and a semiconductor device containing the strained SiN film. The method includes exposing the substrate to a gas including a silicon precursor. The substrate is exposed to a gas including a first nitrogen precursor configured to react with the silicon precursor with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080081472 - Manufacturing method of semiconductor device: A first structure is formed, having a contact plug formed on the bottom of a first opening in an interlayer insulating film, a second opening formed through the interlayer insulating film to reach a semiconductor substrate, and a third opening formed through the interlayer insulating film to reach a polymetal... Agent: Young & Thompson

20080081471 - Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniques: By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080081474 - Integration of a variable thickness copper seed layer in copper metallization: A method for forming a variable thickness Cu seed layer on a substrate for a subsequent Cu electrochemical plating process, where the Cu seed layer thickness profile improves uniformity of the electroplated Cu layer compared to when using a constant thickness Cu seed layer. The method includes depositing a Ru... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080081473 - Method for integrated substrate processing in copper metallization: A method of copper metallization includes providing a patterned substrate containing a via and a trench, and performing an integrated process on the patterned substrate. The integrated process includes depositing a first metal-containing layer over the patterned substrate, removing by sputter etching the first metal-containing layer from the bottom of... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080081475 - Method for forming pattern in semiconductor device: A method for forming a pattern in a semiconductor device includes forming an etch target layer and a hard mask layer, forming a mask pattern over the hard mask layer, etching the hard mask layer using the mask pattern as an etch mask, removing polymers generated while etching the hard... Agent: Blakely Sokoloff Taylor & Zafman

20080081476 - Methods of forming integrated circuit devices having tensile and compressive stress layers therein and devices formed thereby: Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal... Agent: Myers Bigel Sibley & Sajovec

20080081477 - Method for forming a semiconductor device having a cylindrical hole in a dielectric film: Anisotropic dry etching uses a hard mask as an etching mask and a mixture of fluorocarbon, oxygen and rare gas as an etching gas, and effects etching of a dielectric film and deposition of deposits on the hard mask for suppressing reduction of the thickness of the hard mask. A... Agent: Mcginn Intellectual Property Law Group, PLLC

20080081478 - Method for planarization of wafer and method for formation of isolation structure in top metal layer: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower... Agent: Squire, Sanders & Dempsey L.L.P.

20080081479 - Method for fabricating fine pattern in semiconductor device: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist pattern over an etch target layer, forming a first hard mask layer over a substrate structure, planarizing the first hard mask layer to form a first hard mask pattern and expose the first photoresist... Agent: Blakely Sokoloff Taylor & Zafman

20080081480 - Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device: By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080081481 - Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device: By providing a silicon cap layer on a compressive silicon nitride layer, the diffusion of nitrogen into sensitive resist material may be efficiently reduced, while the silicon may be converted into a highly compressive silicon dioxide in a later manufacturing stage. Consequently, yield loss due to contact failures during the... Agent: J. Mike Amerson Williams, Morgan & Amerson, P. C.

20080081483 - Pulsed plasma etching method and apparatus: A plasma etching method includes preparing in a reaction chamber a semiconductor substrate on which a material layer to be etched is provided; and injecting an etching gas into the reaction chamber, the etching gas being ionized through an RF (Radio Frequency) power source to generate a plasma, wherein the... Agent: Squire, Sanders & Dempsey L.L.P.

20080081482 - Selective-redeposition structures for calibrating a plasma process: Calibration wafers and methods for calibrating a plasma process performed in a plasma processing apparatus, such as an ionized physical vapor deposition apparatus. The calibration wafer includes one or more selective-redeposition structures for calibrating a plasma process. The selective-redeposition structures receive a controllable and/or measurable amount of redeposited material during... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080081484 - Method for fabricating recess pattern in semiconductor device: A method for fabricating a recess pattern in a semiconductor device includes defining an active region on a substrate, forming a first mask pattern over the active region in a line type structure, forming a second mask pattern comprising an open region over the active region, the open region exposing... Agent: Lowe Hauptman Ham & Berner, LLP

20080081485 - Post-ion implant cleaning on silicon on insulator substrate preparation: A combination of a dry oxidizing, wet etching, and wet cleaning processes are used to remove particle defects from a wafer after ion implantation, as part of a wafer bonding process to fabricate a SOI wafer. The particle defects on the topside and the backside of the wafer are oxidized,... Agent: Applied Materials/blakely

20080081486 - Field effect transistor having a stressed dielectric layer based on an enhanced device topography: By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or... Agent: Williams, Morgan & Amerson

20080081487 - Method for fabricating semiconductor element: According to this invention, a method for fabricating a semiconductor element comprises the steps of providing a semiconductor wafer; forming an oxide layer on the semiconductor wafer; loading the semiconductor wafer in a furnace; carrying out a high-temperature thermal treatment to the semiconductor wafer at least once, wherein the high-temperature... Agent: Rabin & Berdo, PC