Semiconductor device manufacturing: process inventions 03/08

20080070325 - Double-masking technique for increasing fabrication yield in superconducting electronics: A new technique is presented for improving the microfabrication yield of Josephson junctions in superconducting integrated circuits. This is based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material,... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080070328 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming a film to be processed having a first film thickness on a semiconductor substrate; forming a region, within the film to be processed, having a second film thickness thinner than the first film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080070329 - Removing dry film resist residues using hydrolyzable membranes: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the... Agent: Intel/blakely

20080070331 - Method for manufacturing a strongly refractive microlens for a light emitting diode with condensation silicone: A method for manufacturing a strongly refractive microlens for an LED with condensation silicone has steps of: forming a mixture of composite nanoparticles and PMMA microspheres, forming a mixture of condensation silicone and photonic crystals and injecting the condensation silicone and photonic crystals onto an LED to form a strongly... Agent: Patenttm.us

20080070340 - Image sensor using thin-film soi: Systems and methods related to an image sensor of one or more embodiments include subjecting a donor semiconductor wafer to an ion implantation process to create an exfoliation layer of semiconductor film on the donor semiconductor wafer, forming an anodic bond between the exfoliation layer and an insulator substrate by... Agent: Corning Incorporated

20080070342 - Methods of manufacturing image sensors: Example embodiments may provide methods of manufacturing an image sensor. Example methods of manufacturing an image sensor may include forming a photoelectric converter in a semiconductor substrate, forming an interlayer insulating film covering a surface of the semiconductor substrate, forming metal wires and an inter-metal insulating film filling between the... Agent: Harness, Dickey & Pierce, P.L.C

20080070343 - Methods for forming an organic thin film using solvent effects, organic thin film formed by the method, and organic electronic device comprising organic thin film: Disclosed is a method for forming an organic thin film using a good solvent and a non-solvent to promote crystallization of an organic material. The method may enable the formation of a dense, uniform, highly ordered organic thin film by a wet process in a simple and an economical manner.... Agent: Harness, Dickey & Pierce, P.L.C

20080070326 - Method for manufacturing semiconductor device: It is an aspect of the embodiments discussed herein to provide a method manufacturing a semiconductor device, including forming a bottom electrode film above a semiconductor substrate, forming an insulating film on the bottom electrode film, forming a top electrode on the insulating film, forming a capacitor insulating film by... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080070327 - Plasma processing method and plasma processing apparatus: In a plasma processing method, a correlation between substrate type data and optical data is obtained by using a multivariate analysis; substrate type data is obtained from optical data based on the correlation when initiating a plasma processing; and a substrate type is determined by using the obtained substrate type... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080070330 - Fabrication method of semiconductor integrated circuit device: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080070332 - Method of fabricating display substrate and method of fabricating display panel using the same: Disclosed is a method of fabricating a display substrate. A black matrix and a color filter layer are formed on a base substrate, and then a transparent electrode and a photoresist layer pattern are sequentially formed. The transparent electrode is patterned using the photoresist layer pattern as a mask to... Agent: H.c. Park & Associates, PLC

20080070333 - Optical semiconductor device and method of manufacturing thereof: A method of manufacturing an optical semiconductor device (16) sealed in a transparent or semitransparent cured silicone body (50) by placing an unsealed optical semiconductor device (16) into a mold (23, 34) and subjecting a transparent or semitransparent curable silicone composition (50) that fills the spaces between the mold and... Agent: Howard & Howard Attorneys, P.C.

20080070334 - Led including photonic crystal structure: A photonic crystal light emitting diode (“PXLED”) is provided. The PXLED includes a periodic structure, such as a lattice of holes, formed in the semiconductor layers of an LED. The parameters of the periodic structure are such that the energy of the photons, emitted by the PXLED, lies close to... Agent: Patent Law Group LLP

20080070335 - Method of fabricating a semiconductor device: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080070336 - Semiconductor layer formed by selective deposition and method for depositing semiconductor layer: In a method for fabricating a nitride-based semiconductor laser which forms, by a selective deposition, a current narrowing structure and a structure confining a light in a horizontal direction in parallel to a substrate, when the nitride-based semiconductor is selectively deposited by a metal organic chemical vapor deposition, silicon generated... Agent: Sughrue Mion, PLLC

20080070337 - Light emitting element and method of making same: A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (AlXInYGa(1-X-Y))2O3 where 0≦x≦1, 0≦y≦1 and 0≦x+y≦1. The pn-junction has first conductivity type substrate, and GaN system compound semiconductor thin film of second conductivity type opposite... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20080070339 - Method for one-way coupling an input signal to an integrated circuit: A method for one-way coupling an input signal to an integrated circuit on a semiconductor chip with the integrated circuit electrically isolated from the input signal comprises forming a MOS isolation coupler on the semiconductor chip by a CMOS process. The MOS isolation coupler comprises an inductor coil for generating... Agent: Wolf Greenfield & Sacks, P.C.

20080070338 - Micro-electromechanical system (mems) based current & magnetic field sensor having capacitive sense components: A micro-electromechanical system (MEMS) based current & magnetic field sensor includes a MEMS-based magnetic field sensing component having a capacitive magneto-MEMS component, a compensator and an output component for sensing magnetic fields and for providing, in response thereto, an indication of the current present in a respective conductor to be... Agent: General Electric Company Global Research

20080070341 - Photoelectric conversion device, and process for its fabrication: In a photoelectric conversion device comprising a photoelectric-conversion section and a peripheral circuit section where signals sent from the photoelectric-conversion section are processed, the both sections being provided on the same semiconductor substrate, a semiconductor compound layer of a high-melting point metal is provided on the source and drain and... Agent: Fitzpatrick Cella Harper & Scinto

20080070344 - Prams having a plurality of active regions located vertically in sequence and methods of forming the same: There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one... Agent: Mills & Onello LLP

20080070345 - Structure of high performance combo chip and processing method: A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the... Agent: Megica Corporation

20080070346 - Structure of high performance combo chip and processing method: A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the... Agent: Megica Corporation

20080070347 - Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device: There is provided a semiconductor device manufacturing method which prevents cracking of an overcoat during polishing process, and a semiconductor wafer and a semiconductor device which have an overcoat free from cracking. A plurality of divided overcoats 10 are formed on each chip 3 in a chip region 2 and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080070348 - Method for fabricating resin-molded semiconductor device having posts with bumps: A semiconductor apparatus includes a semiconductor device to be mounted on a circuit board; a plurality of conductive posts electrically connected to the semiconductor device; and a plurality of conductive bumps each provided on an outer end of each of the conductive posts, so that the plurality of conductive bump... Agent: Rabin & Berdo, PC

20080070349 - Formation of holes in substrates using dewetting coatings: Methods and systems for forming holes in a substrate using dewetting coating are described herein.... Agent: Schwabe, Williamson & Wyatt, P.C.

20080070350 - Semiconductor device and method of forming a semiconductor device: A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one. example, a region of the second conductivity type is provided at the second end of... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080070351 - Manufacturing method of display device: In a display device manufacturing method including a step of forming a semiconductor film above a substrate and a step of implanting an impurity to each of a first semiconductor film in a first region of the substrate, a second semiconductor film in a second region outside the first region,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080070352 - Method of manufacturing a semiconductor device: An impurity of one conductivity type is ionized and accelerated by electric field before being implanted into a semiconductor layer to form a high concentration impurity region near its surface. Then the semiconductor layer is irradiated with continuous wave laser light for melting and crystallization or recrystallization, through which a... Agent: Eric Robinson

20080070353 - Lithographic apparatus and device manufacturing method: The present invention relates to a lithographic apparatus including an illumination system configured to condition a radiation beam; a support constructed to support a first and a second patterning device, each patterning device being capable of imparting the radiation beam with a pattern in its cross-section to form a patterned... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080070354 - Site-specific nanoparticle self-assembly: Disclosed herein are methods of self-assembling nanoparticles on specific sites of a substrate. The method generally includes introducing a p-type dopant species to at least a portion of an n-type substrate or introducing an n-type dopant species to at least a portion of a p-type substrate, wherein the dopant species... Agent: Cantor Colburn, LLP

20080070355 - Aspect ratio trapping for mixed signal applications: Structures and methods for their formation include a substrate comprising a first semiconductor material, with a second semiconductor material disposed thereover, the first semiconductor material being lattice mismatched to the second semiconductor material. Defects are reduced by using an aspect ratio trapping approach.... Agent: Goodwin Procter LLP Patent Administrator

20080070356 - Trench replacement gate process for transistors having elevated source and drain regions: The method for forming a semiconductor device arrangement with raised source/drains includes depositing a raised source/drain layer on a substrate, followed by a sacrificial layer on the raised source/drain layer. A trench is formed in the sacrificial layer and the raised source/drain layer, and sidewall spacers are formed within the... Agent: Mcdermott Will & Emery LLP

20080070357 - Structure and method to optimize strain in cmosfets: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N... Agent: Scully, Scott, Murphy & Presser, P.C.

20080070358 - Semiconductor device: Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across... Agent: Mcdermott Will & Emery LLP

20080070359 - Semiconductor device including mos field effect transistor having offset spacers of gate sidewall films on either side of gate electrode and method of manufacturing the same: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film... Agent: Foley And Lardner LLP Suite 500

20080070360 - Method and structure for forming silicide contacts on embedded silicon germanium regions of cmos devices: A method of forming silicide contacts for a complementary metal oxide semiconductor (CMOS) device includes selectively forming a protective layer over faceted surfaces of an embedded SiGe (eSiGe) region of a substrate, the eSiGe region comprising a compressive stress inducing layer in a PFET portion of the CMOS device, wherein... Agent: Cantor Colburn LLP - IBM Fishkill

20080070361 - Method of manufacturing a capacitor and method of manufacturing a dynamic random access memory device using the same: In a method of manufacturing a capacitor and a method of manufacturing a dynamic random access memory device, an insulating layer covering an upper portion of a conductive layer may be provided with an ozone gas so as to change the property of the upper portion of the insulating layer.... Agent: Harness, Dickey & Pierce, P.L.C

20080070362 - Method of manufacturing a non-volatile nand memory semiconductor integrated circuit: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080070363 - Method of making an array of non-volatile memory cells with floating gates formed of spacers in substrate trenches: In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements are positioned along sidewalls of substrate trenches, preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes... Agent: Davis Wright Tremaine LLP

20080070364 - Vertical memory device and method: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the... Agent: Kacvinsky LLC C/o Intellevate

20080070365 - Shielded gate fet with self-aligned features: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants.... Agent: Townsend And Townsend And Crew, LLP

20080070366 - Multi-gate device with high k dielectric for channel top surface: A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the... Agent: Greenblum & Bernstein, P.L.C

20080070368 - Method of manufacturing a non-volatile memory device: In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be... Agent: Harness, Dickey & Pierce, P.L.C

20080070367 - Methods to create dual-gate dielectrics in transistors using high-k dielectric: A method including forming a gate dielectric film on a surface of a substrate; selectively increasing a physical thickness of a gate dielectric including the gate dielectric film in a first area designated for devices to be operated within a first voltage range; forming a first device in the first... Agent: Intel/blakely

20080070369 - Mos transistor device structure combining si-trench and field plate structures for high voltage device: A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field;... Agent: North America Intellectual Property Corporation

20080070371 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate, a gate electrode, a pair of first impurity regions, a pair of second impurity regions and at least one dummy pattern. The gate electrode is positioned above the substrate. The first impurity regions are positioned in the substrate and near both sides of the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080070370 - Silicide formation with a pre-amorphous implant: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal... Agent: Slater & Matsil, L.L.P.

20080070372 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, an insulating layer pattern defining at least one opening partially exposing a semiconductor substrate is formed on a semiconductor substrate including a single crystalline material. An amorphous thin layer is formed on the insulating layer pattern to fill up the opening. The... Agent: Marger Johnson & Mccollom, P.C.

20080070373 - Manufacturing method of a memory device: A method of manufacturing a memory device. The memory device comprises a trench in a substrate, a capacitor at the low portion of the trench, a collar dielectric layer overlying the capacitor and covering a portion of the sidewall of the trench, and a conductive layer filling a portion of... Agent: Quintero Law Office, PC

20080070374 - Method for forming trench capacitor and memory cell: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used... Agent: North America Intellectual Property Corporation

20080070375 - Method for fabricating a storage electrode of a semiconductor device: A method for fabricating a storage electrode of a semiconductor device includes forming an interlayer dielectric film including a storage node contact on a semiconductor substrate, forming an etching blocking layer on the interlayer dielectric film, forming a mold insulating layer on the etching blocking layer, the mold insulating layer... Agent: Marshall, Gerstein & Borun LLP

20080070376 - Method of wafer-to-wafer bonding: Methods of wafer-to-wafer bonding are disclosed. These methods use a force-transposing substrate providing redistribution of the applied force to the local bonding areas across the wafer. Certain versions of the Present Invention also provide a compliant force-distributing member along with applying bonding material to bonding areas in selectable locations. A... Agent: Fitch Even Tabin And Flannery

20080070377 - Method of producing bonded wafer: A method of producing a bonded wafer, comprising: performing bonding of a first semiconductor wafer and a second semiconductor wafer without interposing an insulation film in between; and performing thinning of the second semiconductor wafer, wherein surface portions at least including bonded surfaces of the first semiconductor wafer and the... Agent: Kolisch Hartwell, P.C.

20080070378 - Dual laser separation of bonded wafers: A system for dicing a bonded wafer includes a plurality of substrates having at least a first substrate bonded to at least a second substrate. A first laser is configured to emit a first laser beam at a first predetermined wavelength such that the first laser beam creates a modified... Agent: Hewlett Packard Company

20080070379 - Method of fabricating semiconductor device: The present invention provides a method of manufacturing a semiconductor device capable of preventing a cut portion from becoming chipped when dicing. The method of manufacturing a semiconductor device includes preparing a semiconductor wafer having an upper surface (first surface) including a plurality of device regions and partition regions for... Agent: Volentine & Whitt PLLC

20080070380 - Production method of compound semiconductor device wafer: An object of the present invention is to provide a method for producing a compound semiconductor device wafer, which method enables cleaving of a wafer with precision and at remarkably high yield, attains high process speed, and improves productivity. The inventive method for producing a compound semiconductor device wafer, the... Agent: Sughrue Mion, PLLC

20080070381 - Semiconductor wafer, method of manufacturing the same, and method of manufacturing a semiconductor device: In a semiconductor wafer including a plurality of element forming regions formed on a front surface of a semiconductor substrate, a scribe line groove is formed along a periphery of the each of the element forming regions, and stoppers are located at an intersection of the scribe line groove, so... Agent: Mcginn Intellectual Property Law Group, PLLC

20080070382 - Fixing apparatus for semiconductor wafer: A wafer fixing apparatus is disclosed including a dicing stage structured to fix a semiconductor wafer. A die attach film is disposed on the dicing stage to attach the semiconductor wafer to the dicing stage. The die attach film attaches the semiconductor wafer to the dicing stage due to the... Agent: Marger Johnson & Mccollom, P.C.

20080070383 - Rectifying contact to an n-type oxide material or a substantially insulating oxide material: A rectifying contact to an n-type oxide material and/or a substantially insulating oxide material includes a p-type oxide material. The p-type oxide material includes a copper species and a metal species, each of which are present in an amount ranging from about 10 atomic % to about 90 atomic %... Agent: Hewlett Packard Company

20080070384 - Formation of strain-inducing films using hydrogenated amorphous silicon: A method to form a strain-inducing epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is a three-component epitaxial film comprising atoms from a parent film, charge-neutral lattice-substitution atoms and charge-carrier dopant impurity atoms. In another embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch cycle... Agent: Intel/blakely

20080070385 - Water-barrier performance of an encapsulating film: A method and apparatus for depositing a material layer onto a substrate is described. The method includes delivering a mixture of precursors for the material layer into a process chamber and depositing the material layer on the substrate at low temperature. The material layer can be used as an encapsulating... Agent: Patterson & Sheridan, LLP

20080070386 - Device for irradiating a laser beam: A device for irradiating a laser beam onto an amorphous silicon thin film formed on a substrate. The device includes: a stage mounting the substrate; a laser oscillator for generating a laser beam; a projection lens for focusing and guiding the laser beam onto the thin film; a reflector for... Agent: Macpherson Kwok Chen & Heid LLP

20080070387 - Semiconductor device manufacturing method: A technique is provided which enables formation of nitride semiconductor layers with excellent flatness and excellent crystallinity on a gallium nitride substrate (GaN substrate), while improving the producibility of the semiconductor device using the GaN substrate. A gallium nitride substrate is prepared which has an upper surface having an off-angle... Agent: Leydig Voit & Mayer, Ltd

20080070388 - Compound semiconductor device epitaxial growth substrate, semiconductor device, and manufacturing method thereof: A compound semiconductor device epitaxial growth substrate, wherein a semiconductor substrate, a substrate protective layer made of a material that is different from the material of the substrate, a middle layer for making separation of the semiconductor substrate and a compound semiconductor device layer possible, and a compound semiconductor device... Agent: Nixon & Vanderhye, PC

20080070389 - Apparatus and method for doping: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a... Agent: Fish & Richardson P.C.

20080070390 - Method and apparatus for semiconductor device and semiconductor memory device: A method comprises providing a first conductive region, arranging a second conductive region adjacent to and insulated from the first conductive region by a dielectric region, arranging a third region adjacent to and insulated from the second conductive region, and adjusting mechanical stress to at least one of the first... Agent: Harness, Dickey & Pierce P.L.C

20080070391 - Anti-halo compensation: An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type in the substrate. By implanting... Agent: Greenblum & Bernstein, P.L.C

20080070392 - Controlling diffusion in doped semiconductor regions: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first... Agent: Schwegman, Lundberg & Woessner/micron

20080070393 - Method for manufacturing semiconductor device: In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes that use a photoresist and simplifying the process is provided, which improves throughput. An etching mask for forming a pattern of a layer to be processed such as a conductive layer or... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080070394 - Mos transistor in an active region: After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon nitride is removed, thereby a contact hole... Agent: Mcdermott Will & Emery LLP

20080070395 - Semiconductor devices and methods with bilayer dielectrics: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k... Agent: Haynes And Boone, LLP

20080070396 - Group ii element alloys for protecting metal interconnects: A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and method to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the... Agent: Intel/blakely

20080070397 - Methods for selective placement of dislocation arrays: Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.... Agent: Goodwin Procter LLP Patent Administrator

20080070398 - Method for fabricating semiconductor device having metal fuse: Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an... Agent: Marshall, Gerstein & Borun LLP

20080070399 - Process for forming low defect density heterojunctions: A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux... Agent: Ketan S. Vakil, Esq. Snell & Wilmer L.L.P.

20080070400 - Semiconductor device and manufacturing method thereof: When forming a silicon nitride film to protect and insulate a surface on which a silicon substrate has been ground or polishing, by use of a mixed gas containing SiH4, N2, and NH3 as a reaction gas, a film is formed by a single-frequency parallel-plate plasma CVD method. Thereby, even... Agent: Mcginn Intellectual Property Law Group, PLLC

20080070401 - Memory device and method for manufacturing the same: A memory device and a method for fabricating the same provide a device capable of increasing or maximizing the performance of a microstructure device. The device includes: a plurality of word lines formed with a gap therebetween and extending in parallel with each other in a first direction of extension;... Agent: Mills & Onello LLP

20080070402 - Method of forming contact hole pattern in semiconductor integrated circuit device: A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080070403 - Method and arrangement for contacting terminals: In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact... Agent: Maginot, Moore & Beck Chase Tower

20080070404 - Methods of manufacturing semiconductor devices and structures thereof: Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The... Agent: Slater & Matsil LLP

20080070405 - Methods of forming metal wiring layers for semiconductor devices: A method of forming a conductive plug for an integrated circuit device may include forming an insulating layer on an integrated circuit substrate with the insulating layer having a surface opposite the substrate and a recess therein. A titanium (Ti) layer may be formed on sidewalls of the recess and... Agent: Myers Bigel Sibley & Sajovec

20080070407 - Method for forming a conductive pattern in a semiconductor device: A method for forming a conductive pattern in a semiconductor device includes providing an insulation layer including a trench, forming a conductive material over the insulation layer to fill in the trench, polishing the conductive material to expose the insulation layer, and cleaning the resultant structure using a cleaning solution.... Agent: Townsend And Townsend And Crew, LLP

20080070406 - Pattern forming method and semiconductor device manufacturing method using the same: A resist film is formed on a substrate. A conductive layer is formed on the resist film. The resist film is exposed to an electron beam. The conductive layer is removed by a remover whose temperature is equal to or higher than 30° C. and equal to or lower than... Agent: Young & Thompson

20080070408 - Method for adjusting sizes and shapes of plug openings: The invention is directed to a method for adjusting sizes and shapes of plug openings for border plug openings overlapping with trenches respectively, wherein the border plug openings are separated from each other with a distance equal to or smaller than a specific distance. The method comprises performing an adjusting... Agent: J.c. Patents, Inc.

20080070409 - Method of fabricating interconnections of microelectronic device using dual damascene process: Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate,... Agent: Myers Bigel Sibley & Sajovec

20080070410 - Method for manufacturing capacitor using system in package: A method for manufacturing a capacitor is provided. The method includes: forming a first hole, depositing a barrier metal on an inner wall of the first hole to form a first electrode. The method further includes forming a second hole and bottom electrode-hole aligned with the first hole, forming a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080070411 - Methods for uniformly etching films on a semiconductor wafer: A chemical mixture etches chemically different materials, layers, or films on the surface of a semiconductor wafer or other workpiece at approximately the same rate. The different layers may include, for example, a first material, having a first chemical composition, encapsulated within or sandwiched between one or more materials having... Agent: Perkins Coie LLP/semitool

20080070412 - Polishing compound for semiconductor integrated circuit device, polishing method and method for producing semiconductor integrated circuit device: To provide a polishing technique with which in production of a semiconductor integrated circuit device, when a plane to be polished is polished, an appropriate polishing rate ratio of a polysilicon film to another material can be obtained, whereby high level planarization of a plane to be polished including a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080070413 - Fabrication methods of a patterned sapphire substrate and a light-emitting diode: A fabricating method for patterned sapphire substrate is provided. The fabricating method includes the following processes. First, a sapphire substrate is provided, and a mask layer is formed on the sapphire substrate, wherein the mask layer with appropriate pattern exposes a part of the sapphire substrate. Then, a wet etching... Agent: Jianq Chyun Intellectual Property Office

20080070414 - Method for designing mask and method for manufacturing semiconductor device employing thereof: A bias correction level can be defined with an improved efficiency when a transfer pattern of a hole is formed, so that the hole can be stably formed as originally designed. When a hole pattern is formed over a substrate, correction reference holes 103 existing in a region 113, which... Agent: Young & Thompson

20080070415 - Method for burying resist and method for manufacturing semiconductor device: A resist film is applied to an entire surface and subjected to patterning substantially in the same form as an opening to bury the resist film inside the opening. When a positive resist is used, a photomask having a light-shielding portion with an area smaller than the opening is used... Agent: Leydig Voit & Mayer, Ltd

20080070416 - Phase shift mask including a substrate with recess: A phase shift mask includes a quartz substrate having a main surface partially dug, and a Cr film deposited on the main surface. The dug portion includes an undercut provided such that the Cr film partially serves as an eaves, and the Cr film has a π opening exposing a... Agent: Mcdermott Will & Emery LLP

20080070417 - Method of etching semiconductor device and method of fabricating semiconductor device using the same: A method of fabricating a semiconductor device which prevents a pitting phenomenon from occurring on a gate insulating layer is provided. The method of fabricating of a semiconductor device according to the present invention comprises: depositing a first gate material including at least a gate insulating layer and a first... Agent: Mills & Onello LLP

20080070418 - Substrate processing apparatus and substrate processing method: A substrate processing apparatus has a cup part for receiving processing liquid which is applied from a processing liquid applying part and is splashed from a substrate, and the cup part is formed of electrical insulation material. Hydrophilic treatment is performed on an outer annular surface of the cup part... Agent: Ostrolenk Faber Gerb & Soffen

20080070419 - Process of manufacturing a semiconductor device: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the... Agent: Kratz, Quintos & Hanson, LLP

20080070420 - Method of fabricating image sensor: A method of fabricating an image sensor is disclosed, by which etch damage and stress causing dislocation can be reduced in a manner of forming a liner oxide layer and performing thermal hardening simultaneously. A method of fabricating an image sensor according to embodiments may include etching a trench in... Agent: Sherr & Nourse, PLLC

20080070421 - Bi-layer capping of low-k dielectric films: A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A... Agent: Patterson & Sheridan, LLP

20080070423 - Buried seed one-shot interlevel crystallization: A method is provided for crystallizing a semiconductor film using a buried seed one-shot interlevel crystallization process. The method forms a first semiconductor film having a crystallographic structure, overlying a transparent substrate. An insulator layer is formed overlying the first semiconductor film, and an opening is formed in the insulator... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080070422 - Serial irradiation of a substrate by multiple radiation sources: A method for configuring J electromagnetic radiation sources (J≧2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2; J≦I) thereon. Pj denotes a same source-specific normally incident energy flux on... Agent: Schmeiser, Olsen & Watts

20080064124 - Semiconductor device and manufacturing method thereof: An IrOX film of a thickness of 50 nm is formed on a PZT film by a sputtering method. The value of x is less than 2. Namely, an unsaturated iridium oxide film is formed. By performing RTA, the PZT film is completely crystallized. Thereafter, an IrOY film of a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080064125 - Extendable connector and network: Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are separated by a first proximate distance and applied in an... Agent: Crawford Maunu PLLC

20080064128 - Annealing apparatus, annealing method, and method of manufacturing a semiconductor device: The present invention provides an annealing apparatus including a heating unit, a storage unit, a calculating unit, and a control unit. The heating unit anneals a target wafer. The storage unit stores reference data which a shape parameter of a reference element, an annealing temperature, and an electrical characteristic of... Agent: Sughrue Mion, PLLC

20080064126 - In-situ wafer temperature measurement and control: Broadly speaking, the embodiments of the present invention fill the need by providing in-situ wafer temperature measuring method and apparatus. The in-situ substrate temperature measuring method and apparatus provide instant wafer temperature information to allow for continuous monitoring of the etching process. The method and apparatus also allow for instant... Agent: Martine Penilla & Gencarella, LLP

20080064127 - Method and system for yield and productivity improvements in semiconductor processing: A semiconductor processing method includes processing a first substrate while detecting at least one first processing parameter value in a first apparatus. The first processing parameter is analyzed, thereby yielding at least one first predicted parameter value. The first predicted parameter value is compared with a first pre-defined parameter value,... Agent: Duane Morris LLPIPDepartment (tsmc)

20080064129 - Method of manufacturing a display substrate: A method of manufacturing a display substrate comprises forming a thin-film transistor (TFT) on a silicon wafer, transferring the TFT from the silicon wafer onto a base substrate using a stamp unit and forming a pixel electrode electrically connected to the TFT.... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080064131 - Light emitting apparatus and method for the same: A light emitting apparatus includes a patterned conductive layer, a light emitting device on the patterned conductive layer, and a first light diffusion layer. The light emitting device and the patterned conductive layer are embedded in the first light diffusion layer. A method of forming such a light emitting apparatus... Agent: Snell & Wilmer L.L.P. (main)

20080064135 - Method of manufacturing image sensor: Embodiments relate to a method of manufacturing an image sensor which may include forming a gate pattern including a tunnel oxide film, an oxide-nitride-oxide (ONO) film, a floating gate and a control gate over a semiconductor substrate. An oxide film and a nitride film may be formed over the semiconductor... Agent: Sherr & Nourse, PLLC

20080064130 - Nitride-based light-emitting device and method of manufacturing the same: A nitride-based light-emitting device capable of suppressing reduction of the light output characteristic as well as reduction of the manufacturing yield is provided. This nitride-based light-emitting device comprises a conductive substrate at least containing a single type of metal and a single type of inorganic material having a lower linear... Agent: Mcdermott Will & Emery LLP

20080064132 - Method of fabricating vertical devices using a metal support film: A vertical topology device includes a conductive adhesion structure having a first surface and a second surface, a conductive thick film support formed on the first surface, and a semiconductive device having an upper electrical contact and located over the conductive adhesion layer. Electrical current can flow between the conductive... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20080064133 - Nitride semiconductor light emitting diode and method of manufacturing the same: A flip chip-type nitride semiconductor light emitting diode includes a light transmittance substrate, an n-type nitride semiconductor layer, an active layer, a p-type nitride semiconductor layer and a mesh-type DBR reflecting layer. The mesh-type DBR reflecting layer has a plurality of open regions. The mesh-type DBR reflecting layer is composed... Agent: Lowe Hauptman Ham & Berner, LLP

20080064134 - Methods of making combinational structures for electro-luminscent displays: A picture element for an electro-luminescent display comprises a substrate, a first intermediate structure disposed above a first area of the substrate, at least one first color type electro-luminescent device disposed above the first intermediate structure, a second intermediate structure disposed above a second area of the substrate, and at... Agent: Duane Morris, LLPIPDepartment

20080064136 - Supercritical fluid-assisted deposition of materials on semiconductor substrates: Supercritical fluid-assisted deposition of materials on substrates, such as semiconductor substrates for integrated circuit device manufacture. The deposition is effected using a supercritical fluid-based composition containing the precursor(s) of the material to be deposited on the substrate surface. Such approach permits use of precursors that otherwise would be wholly unsuitable... Agent: Moore & Van Allen PLLC

20080064137 - Method of protecting integrated circuits: The present application relates to the manufacture of Wafer Level Chip Scale Packages (WLCSPs), which are a type of CSP in which the traditional wire bonding arrangements are dispensed with in favour of making direct contact by means of conductive bumps (typically solder balls) to the integrated circuitry. WLCSPs differ... Agent: Wolf Greenfield & Sacks, P.C.

20080064138 - Perimeter matrix ball grid array circuit package with a populated center: A ball grid array (BGA) integrated circuit package which has an outer two-dimensional array of solder balls and a center two-dimensional array of solder balls located on a bottom surface of a package substrate. The solder balls are typically reflowed to mount the package to a printed circuit board. Mounted... Agent: Blakely Sokoloff Taylor & Zafman

20080064139 - Reliable printed wiring board assembly employing packages with solder joints and related assembly technique: An exemplary assembly comprises a printed wiring board having a first surface, and a package including a plurality of solder joints, such as solder balls, on one surface of the package. An anchor via is defined through the first surface of the printed wiring board, and conductive material situated in... Agent: Kyocera Wireless Corp.

20080064140 - Semiconductor device having curved leads offset from the center of bonding pads: A semiconductor device including: a substrate on which a plurality of leads are formed; and a semiconductor chip mounted on the substrate in such a manner that a surface of the semiconductor chip having a plurality of electrodes faces the substrate. Each of the leads includes a first portion that... Agent: Oliff & Berridge, PLC

20080064141 - Manufacturing method of semiconductor device, adhesive sheet used therein, and semiconductor device obtained thereby: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic... Agent: Knobbe Martens Olson & Bear LLP

20080064142 - Method for fabricating a wafer level package having through wafer vias for external package connectivity: According to an exemplary embodiment, a method for fabricating a wafer level package includes forming a polymer layer on a device wafer, where the device wafer includes at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected... Agent: Michael Farjami, Esq. Farjami & Farjami LLP

20080064144 - Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound... Agent: Schwegman, Lundberg & Woessner, P.A.

20080064143 - Microelectronic devices and methods: A microelectronic device is made of a semiconductor substrate, a heat generating component in a layer thereof, and a body within the remaining semiconductor substrate. The body is made of materials which have a high thermal inertia and/or thermal conductivity. When high thermal conductivity materials are used, the body acts... Agent: F. Chau & Associates, LLC

20080064145 - Die attach paddle for mounting integrated circuit die: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper... Agent: Schneck & Schneck

20080064146 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, the method includes: moving a nozzle around a semiconductor chip bonded to a wiring substrate by face-down bonding; and continuously supplying underfill material through the nozzle, thereby filling the underfill material between the wiring substrate and the semiconductor chip, wherein an outline of... Agent: Harness, Dickey & Pierce, P.L.C

20080064147 - Method for fabricating a metal-insulator-metal (mim) capacitor having capacitor dielectric layer formed by atomic layer deposition (ald): In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at... Agent: Young & Thompson

20080064148 - Semiconductor device and manufacturing process thereof: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is... Agent: Buchanan, Ingersoll & Rooney PC

20080064149 - Strained-channel fin field effect transistor (fet) with a uniform channel thickness and separate gates: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20080064150 - Manufacturing method of thin film transistor array substrate: A thin film transistor array substrate and a manufacturing method thereof are provided. Wherein, scan lines and data lines are disposed on a substrate to define a plurality of pixel regions. Thin film transistors are disposed in the pixel regions correspondingly and driven by the scan lines and the data... Agent: Jianq Chyun Intellectual Property Office

20080064152 - Liquid crystal display device having drive circuit and fabricating method thereof: A fabricating method of an array substrate for a liquid crystal display device including forming a polycrystalline silicon film on a substrate having a display region and a peripheral region, the polycrystalline silicon film having grains of square shape, forming a first active layer in the display region and a... Agent: Birch Stewart Kolasch & Birch

20080064151 - Thin film transistor and method of manufacturing the same: A method of manufacturing a thin film transistor includes: forming an amorphous silicon layer and a blocking layer; forming a photoresist layer having first and second photoresist patterns spaced apart from each other on the blocking layer; etching the blocking layer using the first photoresist pattern as a mask to... Agent: H.c. Park & Associates, PLC

20080064153 - Fully salicided (fuca) mosfet structure: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop... Agent: Saile Ackerman LLC

20080064154 - Process flow for metal gate access device: Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an access device following formation of the periphery transistor gates. Access devices and systems... Agent: Trask Britt, P.C./ Micron Technology

20080064155 - Method for producing a multi-stage recess in a layer structure and a field effect transistor with a multi-recessed gate: The method for forming a multi-stage recess in a layer structure comprises forming a photo-resist film atop a layer structure; a first step (49, 70) of etching the layer structure through an opening of the photo-resist film used as a mask, for forming a first stage of the recess; a... Agent: Philips Intellectual Property & Standards

20080064156 - Semiconductor device and method of manufacturing the same: In an nMOSFET, a gate electrode is formed by a silicide layer comprised of NiSi. In a surface layer of a Ge substrate on both sides of the gate electrode, NiGe layers which are germanide layers comprised of NiGe are formed. On junction interfaces between the NiGe layers and the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080064157 - Low noise and high performance lsi device, layout and manufacturing method: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be... Agent: Mills & Onello LLP

20080064158 - Method for fabricating non-volatile memory: A method for fabrication a memory having a memory area and a peripheral area includes forming a first gate insulating layer with a first thickness over a substrate of a first region in the peripheral area and a second insulating layer with a second thickness over the substrate of the... Agent: J C Patents, Inc.

20080064159 - Semiconductor device: Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across... Agent: Mcdermott Will & Emery LLP

20080064160 - Cmos devices incorporating hybrid orientation technology (hot) with embedded connectors: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations).... Agent: Scully Scott Murphy & Presser, PC

20080064161 - Memory cell having bar-shaped storage node contact plugs and methods of fabricating same: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. A plurality of parallel bit line patterns are placed on the bit line interlayer insulating layer. Each of the bit line patterns has a bit line and a bit line canning layer... Agent: Marger Johnson & Mccollom, P.C.

20080064162 - Vertical soi transistor memory cell and method of forming the same: The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node... Agent: Scully, Scott, Murphy & Presser, P.C.

20080064163 - Method and structure for integrating mim capacitors within dual damascene processing techniques: A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer... Agent: Cantor Colburn LLP - IBM Fishkill

20080064164 - Method of manufacturing nonvolatile memory device: A method of manufacturing a nonvolatile memory device is disclosed. The method includes the steps of forming a tunnel oxide layer, a first conductive layer for a floating gate, and a hard mask layer over a semiconductor substrate, etching a portion of the hard mask layer, the first conductive layer,... Agent: Marshall, Gerstein & Borun LLP

20080064165 - Dual storage node memory devices and methods for fabricating the same: Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes... Agent: Ingrassia Fisher & Lorenz, P.C.

20080064167 - Semiconductor device with a bulb-type recess gate: When a recess of a bulb-type recess gate is formed, the recess formed in a device isolation region is formed to be separated from an edge of an active region. This structure thereby prevents damage of a semiconductor substrate of the edge of the active region and a defect during... Agent: Townsend And Townsend And Crew, LLP

20080064168 - Method for forming a shielded gate trench fet with the shield and gate electrodes being connected together: A method of forming a field effect transistor includes the following steps. A trench is formed in a semiconductor region, and a shield dielectric layer lining lower sidewalls and a bottom surface of the trench is formed. A shield electrode is formed in a lower portion of the trench, and... Agent: Townsend And Townsend And Crew, LLP

20080064166 - Semiconductor devices and methods of manufacture thereof: A method of manufacturing a semiconductor device comprising source and drain regions (13, 14, 14a) of a first conductivity type, and a channelaccommodating region (15) of a second, opposite conductivity type which separates the source and drain regions. The device comprises a gate (11, 42) which extends adjacent to the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080064169 - Method for manufacturing semiconductor device, and semiconductor device: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistors' characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the... Agent: Oliff & Berridge, PLC

20080064170 - Transistor for memory device and method for manufacturing the same: Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a groove formed in the active region.... Agent: Ladas & Parry LLP

20080064171 - Method of forming a thin layer and method of manufacturing a semiconductor device: In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An... Agent: Harness, Dickey & Pierce, P.L.C

20080064172 - Stressed semiconductor device structures having granular semiconductor material: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the... Agent: International Business Machines Corporation Dept. 18g

20080064173 - Semiconductor device, cmos device and fabricating methods of the same: A method for fabricating a semiconductor device is described. A transistor is formed on a substrate, including a gate structure on the substrate, a spacer on the sidewall of the gate structure and S/D regions in the substrate beside the gate structure. A liner layer is formed over the substrate... Agent: Jianq Chyun Intellectual Property Office

20080064174 - Method for manufacturing an integrated circuit with fully depleted and partially depleted transistors: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080064175 - Low stress sacrificial cap layer: A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300,... Agent: Texas Instruments Incorporated

20080064176 - Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and... Agent: North America Intellectual Property Corporation

20080064177 - Bipolar device having improved capacitance: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9... Agent: Hitt Gaines, PC Lsi Corporation

20080064178 - Deep trench capacitor through soi substrate and methods of forming: Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the... Agent: Hoffman, Warnick & D'alessandro LLC

20080064179 - Low leakage mim capacitor: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. Attn: Timothy B. Clise

20080064180 - Method for passivating inductively coupled surface currents in a semiconductor device: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch... Agent: Lsi Corporation

20080064181 - Semiconductor device and method of fabricating the same: A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The... Agent: Paul J. Winters

20080064182 - Process for high temperature layer transfer: The invention concerns a method for transferring a thin layer from a donor wafer onto a receiving wafer by implanting at least one atomic species into the donor wafer to form a weakened zone therein, with the weakened zone being including microcavities or platelets therein, and the thin layer being... Agent: Winston & Strawn LLP Patent Department

20080064183 - Method of forming a multi-layer semiconductor structure incorporating a processing handle member: A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of... Agent: Daly, Crowley, Mofford & Durkee, LLP

20080064184 - Method, apparatus for holding and treatment of a substrate: Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which... Agent: Schwegman, Lundberg & Woessner / Infineon

20080064185 - Semiconductor wafer front side protection: There is provided a method for making a wafer comprising the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second... Agent: Driggs, Hogg, Daugherty & Del Zoppo Co., L.p.a.

20080064186 - Manufacturing method of semiconductor element: A semiconductor wafer includes plural element regions and a dicing region provided to partition off these element regions. The element region and the dicing region have a laminated film containing a low dielectric constant insulating film. In dicing the semiconductor wafer, a laser beam whose peak energy Y (W) and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080064187 - Production method for stacked device: A production method for obtaining a stacked device from a wafer is provided. The wafer has: a device forming region formed on a surface having plural devices formed thereon, the devices having surfaces and thicknesses; a peripheral extra region surrounding the device forming region; and plural metal electrodes embedded in... Agent: Brinks Hofer Gilson & Lione

20080064188 - Wafer processing method and wafer processing apparatus: A wafer processing apparatus (10) has a grinder (80) for grinding the back surface (22) of a wafer (20) on whose front surface (21) a circuit pattern (C) has been formed, and a die attachment paste applicator (30) for applying die attachment paste on the entire back surface of the... Agent: Christie, Parker & Hale, LLP

20080064189 - Crack stop for low k dielectrics: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC... Agent: Scully, Scott, Murphy & Presser, P.C.

20080064190 - Manufacturing method of semiconductor device and semiconductor manufacturing device: A manufacturing method of a semiconductor device, comprises; a process of heat-treating a semiconductor substrate under the ordinary pressure and in an oxidizing atmosphere; and a process of heat-treating the semiconductor substrate under the ordinary pressure and in an inert atmosphere, wherein heat-treating time or heat-treating temperature in heat treatment... Agent: Harness, Dickey & Pierce, P.L.C

20080064191 - Modulation of stress in stress film through ion implantation and its application in stress memorization technique: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the... Agent: HorizonIPPte Ltd

20080064192 - Method for forming semiconductor device: Embodiments relate to a method for forming a semiconductor device in which a first oxide layer may be deposited over a surface of a semiconductor substrate including high-voltage (HV) and low-voltage (LV) wells, the first oxide layer having a predetermined thickness corresponding to a high-voltage (HV) area of the well.... Agent: Sherr & Nourse, PLLC

20080064193 - Method for manufacturing semiconductor device using krf light source: A semiconductor device manufacturing method using a KrF light source is disclosed. Embodiments relate to a method for manufacturing a semiconductor device including forming an oxide film over a semiconductor substrate. A gate conductor may be formed over the oxide film. An antireflective film may be formed over the gate... Agent: Sherr & Nourse, PLLC

20080064194 - Method for fabricating flash memory device: A method for fabricating a flash memory device includes providing a semi-finished substrate including a first polysilicon layer electrically isolated by an isolation structure. Recesses are formed in the isolation structure to partially expose sidewalls of the first polysilicon layer. A second polysilicon layer is formed over the exposed first... Agent: Townsend And Townsend And Crew, LLP

20080064195 - Method for manufacturing gate of non volatile memory device: A method for manufacturing the gate of the non-volatile memory device is characterized in in-situ etching a tungsten silicide film, polycrystalline silicon films, an ONO film, and a silicon oxide film with one step using one etchant having a lower etch selectivity on the silicon and oxide films in order... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080064196 - Semiconductor device and method of manufacturing same: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the... Agent: Leydig Voit & Mayer, Ltd

20080064197 - Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and soi mos devices by gate stress engineering with sige and/or si:c: Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20080064198 - Chalcogenide semiconductor memory device with insulating dielectric: A semiconductor chalcogenide containing memory device may be formed with a dielectric in close juxtaposition to a chalcogenide alloy. Because the dielectric includes material interface regions, the thermal conductivity of the dielectric is reduced. As one result, heat transfer may be reduced, reducing the programming current required to program the... Agent: Trop Pruner & Hu, PC

20080064199 - Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during... Agent: Myers Bigel Sibley & Sajovec

20080064200 - Method to manufacture a phase change memory: Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting... Agent: Timothy N. Trop Trop, Pruner & Hu, P.C.

20080064201 - Flip chip packaging method that protects the sensing area of an image sensor from contamination: A flip chip packaging method that protects a sensing area of an image sensor from contamination primarily comprises: a transmitting substrate having a surface with a predetermined area forming a metal layer thereon which includes a circuit and at least one enclosure encircling said predetermined area; providing an image sensor... Agent: Chen Wen Ching

20080064202 - Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases: The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality... Agent: Young & Thompson

20080064203 - Method for fabricating a contact hole: A method for fabricating a contact hole is provided. A semiconductor substrate having thereon a conductive region is prepared. A dielectric layer is deposited on the semiconductor substrate and the conductive region. An etching resistive layer is coated on the dielectric layer. A silicon-containing hard mask bottom anti-reflection coating (SHB)... Agent: North America Intellectual Property Corporation

20080064204 - Method of forming a metal line of a semiconductor device: A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating the lower sidewalls of the contact holes and partially filling the contact holes. A second conductive layer is... Agent: Marshall, Gerstein & Borun LLP

20080064205 - Silicon-alloy based barrier layers for integrated circuit metal interconnects: A method for forming a silicon alloy based barrier layer comprises providing a substrate having a dielectric layer including a trench, placing the substrate in a reactor, and carrying out a process cycle, wherein the process cycle comprises introducing a silicon containing precursor into the reactor, introducing a metal containing... Agent: Intel Corporation C/o Intellevate, LLC

20080064206 - Method of manufacturing a semiconductor memory device: Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating... Agent: Marger Johnson & Mccollom, P.C.

20080064207 - Semiconductor device power interconnect striping: A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive path required between a power source and a semiconductor... Agent: Intel/blakely

20080064208 - System and method for increasing the strength of a bond made by a small diameter wire in ball bonding: A system and method is disclosed for increasing the strength of a bond made by a small diameter wire in ball bonding. In one embodiment of the invention a structure for receiving a ball bond comprises substrate material that has portions that form a substrate cavity and a wire bond... Agent: Stmicroelectronics, Inc.

20080064209 - Systems and methods for forming metal-containing layers using vapor deposition processes: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more homoleptic and/or heteroleptic precursor compounds that include, for example, guanidinate, phosphoguanidinate, isoureate, thioisoureate,... Agent: Mueting, Raasch & Gebhardt, P.A.

20080064210 - Systems and methods of forming refractory metal nitride layers using organic amines: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on a substrate by using an atomic layer deposition process (a vapor deposition process that includes a plurality of deposition cycles) with a refractory metal precursor compound,... Agent: Mueting, Raasch & Gebhardt, P.A.

20080064211 - Polishing compound for copper wirings and method for polishing surface of semiconductor integrated circuit: To provide a technique for realizing high-precision surface planarization when copper is used as a wiring metal. A polishing compound is used which comprises water; a peroxide oxidizer; a surface protective agent for copper; at least one first chelating agent selected from the group consisting of tartaric acid, malonic acid,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080064212 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, has applying perhydro polysilazane to a substrate; and immersing at least the surface of said substrate to which perhydro polysilazane is applied in a mixture containing water heated to 120 degrees C. or higher to which ultrasound is applied, thereby modifying the perhydro... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080064213 - Method for forming a fine pattern of a semiconductor device: A method for forming a fine pattern of a semiconductor device includes forming a photoresist pattern over a semiconductor substrate including an underlying layer. A cross-linking layer is formed on the sidewall of the photoresist pattern. The photoresist pattern is then removed to form a fine pattern comprising the cross-linking... Agent: Townsend And Townsend And Crew, LLP

20080064215 - Method of fabricating a semiconductor package: In one aspect, a method of manufacturing a semiconductor package includes providing a semiconductor substrate which includes a plurality of semiconductor chips and a scribe lane defined between the semiconductor chips, forming a trench within the scribe lane, filling the trench with a photolytic polymer, grinding a back side of... Agent: Volentine & Whitt PLLC

20080064214 - Semiconductor processing including etched layer passivation using self-assembled monolayer: In the fabrication of an integrated circuit where a porous silicon oxide layer is formed over a surface of a semiconductor substrate to electrically isolate two conductive metal layers, a via through the porous silicon oxide layer has an opening etched through the porous silicon oxide layer, a self-assembled monolayer... Agent: Beyer Weaver LLP

20080064218 - Manufacturing method for preventing image sensor from undercut: Embodiments relate to an image sensor, and in particular to a manufacturing method of an image sensor for preventing an undercut phenomenon in an etching process so that the salicidation of a pixel area can be prevented. Embodiments relate to a manufacturing method of an image sensor for preventing an... Agent: Sherr & Nourse, PLLC

20080064216 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device includes providing a substrate having an insulating layer, a first mask layer over the insulating layer, a second mask layer over the first mask layer, a first photoresist pattern over the second mask layer, the first photoresist pattern having a first pitch.... Agent: Townsend And Townsend And Crew, LLP

20080064219 - Method of removing photoresist: A method of removing a photoresist in a semiconductor manufacturing process including at least one of the following steps: sequentially depositing an oxide film and a metal film over a semiconductor substrate. Depositing an anti-reflection film and a photoresist over the metal film. Patterning the photoresist to form a photoresist... Agent: Sherr & Nourse, PLLC

20080064217 - Methods of forming semiconductor devices using di-block polymer layers: A method of forming a semiconductor device is provided. An interlayer dielectric is formed on a substrate. A di-block polymer layer that includes a plurality of first polymer blocks and a plurality of second polymer blocks is formed on the interlayer dielectric. The di-block polymer layer is divided into a... Agent: Myers Bigel Sibley & Sajovec

20080064220 - Method and system for dry etching a hafnium containing material: A method and system for etching a hafnium containing material using a boron tri-chloride (BCl3) based process chemistry is described. A substrate having a hafnium containing layer, such as a layer of hafnium dioxide (HfO2) is subjected a dry etching process comprising BCl3 and an additive gas including: an oxygen-containing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080064221 - Method for fabricating semiconductor device including plug: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, etching the insulation layer using a hard mask pattern to form a contact hole, filling the contact hole with a conductive layer, etching the conductive layer to form a plug in the contact hole, removing... Agent: Townsend And Townsend And Crew, LLP

20080064222 - Alkaline etching solution for semiconductor wafers and alkaline etching method: Alkaline etching solutions capable of improving a surface roughness even with a relatively low alkaline concentration, contain bromate or both bromate and nitrate. An alkaline etching method using the solution produces silicon wafers with improved surface roughness.... Agent: Brooks Kushman P.C.

20080064223 - Etching liquid, etching method, and method of manufacturing electronic component: An etching liquid used for selectively etching silicon nitride, the etching liquid includes: water; a first liquid that can be mixed with the water to produce a mixture liquid having a boiling point of 150° C. or more; and a second liquid capable of producing protons (H+). Alternatively, an etching... Agent: Pearne & Gordon LLP

20080064224 - Device comprising an ohmic via contact, and method of fabricating thereof: Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a conductive barrier layer over the metal layer, depositing an insulating layer over the conductive barrier layer, creating an opening in the insulating layer to expose the... Agent: Texas Instruments Incorporated

20080064225 - Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also... Agent: Patterson & Sheridan, LLP

20080064226 - Method of processing a substrate, heating apparatus, and method of forming a pattern: A method of processing a substrate, comprising forming a chemically amplified resist film on a substrate, irradiating energy beams to the chemically amplified resist film to form a latent image therein, carrying out heat treatment with respect to the chemically amplified resist film, heating treatment being carried out in a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080064227 - Apparatus for chemical vapor deposition and method for cleaning injector included in the apparatus: An apparatus for chemical vapor deposition includes a reaction chamber providing a predetermined sealed space, a reaction gas supply unit for supplying a first reaction gas into the reaction chamber and a reaction gas supply line formed by operatively connecting the reaction gas supply unit and the reaction chamber. The... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080057599 - Fabrication method of semiconductor device: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an... Agent: Miles & Stockbridge PC

20080057600 - Mounting circuit and method for producing semiconductor-chip-mounting circuit: A method according to the present invention for producing a semiconductor-chip-mounting circuit 1 includes mainly three steps. In a first step, contacts 2 each in the form of a conical helix are formed by solder-plating the surface of connecting terminals 12 on a mounting circuit 10. In a second step,... Agent: Beyer Weaver LLP

20080057601 - Method for manufacturing a white led: A method for manufacturing a white LED is disclosed. The method for manufacturing a white LED comprises a die bonding step in which a blue chip is mounted on a lead frame; a wire bonding step in which the blue chip and lead frame both mounted on the lead frame... Agent: Ladas & Parry

20080057605 - Method for manufacturing semiconductor device and method for manufacturing display device: An object is to provide a method for manufacturing a highly-reliable semiconductor device with an improved material use efficiency and with a simplified manufacturing process. The method includes the steps of forming a conductive layer over a substrate, forming a light-transmitting layer over the conductive layer, and selectively removing the... Agent: Eric Robinson

20080057604 - Method of fabricating display device: To improve the use efficiency of materials and provide a technique of fabricating a display device by a simple process. The method includes the steps of providing a mask on a conductive layer, forming an insulating film over the conductive layer provided with the mask, removing the mask to form... Agent: Nixon Peabody, LLP

20080057608 - Manufacturing method of group iii nitride substrate, group iii nitride substrate, group iii nitride substrate with epitaxial layer, manufacturing method of group iii nitride substrate with epitaxial layer, and manufacturing method of group iii nitride dev: A manufacturing method of a group III nitride substrate by which a group III nitride substrate being excellent in flatness can be obtained includes the steps of adhering a plurality of the stripe type group III nitride substrates to an abrading holder so that a stripe structure direction is perpendicular... Agent: Mcdermott Will & Emery LLP

20080057610 - Method of forming a mask structure and method of forming a minute pattern using the same: In the method of forming a mask structure, a first mask is formed on a substrate where the first mask includes a first mask pattern having a plurality of mask pattern portions having openings therebetween and a second mask pattern having a corner portion of which an inner side wall... Agent: Myers Bigel Sibley & Sajovec

20080057611 - Method of manufacturing a thin-film thermo-electric generator: A method of manufacturing a thin-film thermoelectric generator comprises the steps of: coating of a carrier film with a first semiconductor of a first conductor type, structuring of the first semiconductor, coating of the carrier film with a second semiconductor of a second conductor type and structuring of the second... Agent: Duane Morris, LLPIPDepartment

20080057612 - Method for adding an implant at the shallow trench isolation corner in a semiconductor substrate: A method for fabricating corner implants in the shallow trench isolation regions of an image sensor includes the steps of forming a photoresist layer on a first hard mask layer overlying an etch-stop layer on a semiconductor substrate. The photoresist mask is patterned to create an opening and the portion... Agent: F-p, Patent Legal Staff Eastman Kodak Company

20080057613 - Cmos image sensor and method for manufacturing the same: A method for manufacturing a CMOS image sensor may include at least one of the following steps: Forming a salicide blocking layer on an entire surface of a semiconductor substrate having a photodiode area and a transistor. Forming a photoresist pattern inclined at an angle less 90° (e.g. between approximately... Agent: Sherr & Nourse, PLLC

20080057615 - Manufacturing method of photoelectric conversion device: A noise generated by a constitution of widening an incident aperture of light of a photoelectric conversion element is reduced. In a manufacturing method of a photoelectric conversion device, first electroconductor arranged in a first hole arranged in the first interlayer insulation layer electrically connects a first semiconductor region to... Agent: Fitzpatrick Cella Harper & Scinto

20080057598 - Method for forming ferroelectric capacitor and method for fabricating semiconductor device: A ferroelectric capacitor formation method that enables stable FeRAM mass production. When a ferroelectric capacitor of an FeRAM is formed, a ferroelectric layer is formed over a lower electrode layer by a sputtering method by keeping a stage at a temperature lower than or equal to 35° C. To crystallize... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080057602 - Fabrication system and manufacturing method of light-emitting device: The present invention provides a vapor deposition method and a vapor deposition system of film formation systems by which EL materials can be used more efficiently and EL materials having superior uniformity with high throughput rate are formed. According to the present invention, inside a film formation chamber, an evaporation... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080057603 - Light emitting diode and method of making the same: A light emitting diode (LED) and a method of making the same are disclosed. The present invention is featured in that the LED comprises a transparent heat-conductive glue, a reflective layer, and a carrier, etc, wherein the transparent heat-conductive glue is used to adhere the epitaxial structure and the carrier... Agent: Glenn Patent Group

20080057606 - Liquid crystal display: There is provided a liquid crystal display device in which the wiring resistivity of signal lines is reduced. The liquid crystal display device includes substrates disposed in opposition to each other with a liquid crystal interposed therebetween, a thin film transistor to be driven by a scanning signal supplied from... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20080057607 - Liquid crystal display: There is provided a liquid crystal display device in which the wiring resistivity of signal lines is reduced. The liquid crystal display device includes substrates disposed in opposition to each other with a liquid crystal interposed therebetween, a thin film transistor to be driven by a scanning signal supplied from... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20080057609 - Organic light-emitting device with improved layer structure: An organic light emitting device having a cathode, an anode and an organic layer structure disposed between the cathode and the anode, the organic layer structure comprising a hole injection layer doped with a p-type dopant, a hole transport layer, an emissive layer and an electron transport layer doped with... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080057614 - Color image sensor device and fabrication method thereof: A color image sensor device and fabrication method thereof. A passivation layer and a first planarization layer are sequentially formed on a substrate. A plurality of color filter elements are disposed over the first planarization layer corresponding to the sensor pixel array. A second planarization layer and a third planarization... Agent: Birch Stewart Kolasch & Birch

20080057616 - Bandgap grading in thin-film devices via solid group iiia particles: Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment, a method is provided for bandgap grading in a thin-film device using such particles. The method may be comprised of providing a bandgap grading material comprising of an alloy having: a) a IIIA material... Agent: Nanosolar, Inc.

20080057617 - Method of thin lightshield process for solid-state image sensors: An image sensor includes a substrate having photosensitive areas; an insulator spanning at least a portion of the substrate; and a first and second layer of a multi-layer metallization structure, wherein the first layer forms light shield regions over selected portions of the photosensitive area as well forming circuit interconnections... Agent: Eastman Kodak Company

20080057618 - Method for manufacturing semiconductor device: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost. A method for manufacturing a semiconductor device includes the following steps:... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080057622 - Map type semiconductor package: A MAP (Mold-Array-Process) type semiconductor package mainly includes a chip carrier, at least a chip, and an encapsulant. The chip is disposed on the carrier and is electrically connected to the chip carrier. The encapsulant completely covers the upper surface of the chip carrier and encapsulates the chip. Therein, the... Agent: Troxell Law Office PLLC

20080057619 - Microcontainer for hermetically encapsulating reactive materials: A microcontainer device for micro-electro-mechanical systems such as atomic clocks is provided. The microcontainer device includes a substrate and a cavity in the substrate defined by a sidewall having an upper edge. The cavity is configured to hold a reactive material such as rubidium or cesium. A lid having a... Agent: Honeywell International Inc.

20080057621 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures... Agent: Perkins Coie LLP Patent-sea

20080057620 - Redistribution layers for microfeature workpieces, and associated systems and methods: Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a preformed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the... Agent: Perkins Coie LLP Patent-sea

20080057623 - Thin embedded active ic circuit integration techniques for flexible and rigid circuits: A flexible electronic circuit member formed of a plurality of dielectric layers includes a plurality of thinned semiconductor chips embedded within the circuit member for increased levels of integration and component density. The thinned semiconductor chips may include various integrated circuits thereon. They may be formed on various substrates and... Agent: HowardIPLaw Group

20080057624 - Stack type semiconductor package utilizing solder coated stacking protrusions and method for manufacturing the same: The stack type semiconductor package module includes a lower semiconductor package having a main substrate, a chip mounted on the main substrate and electrically connected to the main substrate through a wire. An epoxy molding compound (EMC) is provided on the main substrate to cover the chip and the wire.... Agent: Ladas & Parry LLP

20080057625 - Method and apparatus for making semiconductor packages: A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively;... Agent: Vedder Price Kaufman & Kammholz

20080057626 - Method of manufacturing a semiconductor device: For molding semiconductor chips on a wiring substrate matrix with a sealing resin, the wiring substrate matrix is placed on a lower die cavity block of a lower die, and, thereafter, an upper die is brought down, whereby an outer peripheral portion of a cavity of the upper die comes... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080057627 - Method of manufacturing a combined multilayer circuit board having embedded chips: A method has acts of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by steps of... Agent: Hershkovitz & Associates

20080057628 - Modified chip attach process: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the... Agent: Schwegman, Lundberg & Woessner, P.A.

20080057629 - Integrated circuit cooling and insulating device and method: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a... Agent: Attn: David C. Peterson Schwegman, Lundberg, Woessner & Kluth, P.A.

20080057630 - Flexible core for enhancement of package interconnect reliablity: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected... Agent: Intel/blakely

20080057632 - Method for manufacturing semiconductor device: The present invention offers a method for forming an opening portion by a simple process without using a photomask or a resist. Further, the present invention proposes a method for manufacturing a semiconductor device at low cost. A plurality of light absorbing layers is formed over a substrate, an interlayer... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080057631 - Thin film transistor, method of fabricating active layer thereof, and liquid crystal display: A manufacturing method of an active layer of a thin film transistor is provided. The method includes following steps. First a substrate is provided, and a semiconductor precursor solution is then prepared through a liquid process. Thereafter, the semiconductor precursor solution is provided on the substrate to form a semiconductor... Agent: Jianq Chyun Intellectual Property Office

20080057633 - Method for manufacturing thin film transistor array: The present invention relates to a method of manufacturing a thin film transistor array panel and apparatus and more particularly to an apparatus containing an in-situ fluorine generation chamber.... Agent: F. Chau & Associates, LLC

20080057634 - Method for forming semiconductor device: A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric... Agent: Marshall, Gerstein & Borun LLP

20080057635 - Asymmetric transistor: According to one exemplary embodiment, an asymmetric transistor includes a channel region having a drain-side channel portion and a source-side channel portion. The asymmetric transistor can be an asymmetric MOSFET. The source-side channel portion can comprise silicon, for example. The drain-side channel portion can comprise germanium, for example. The asymmetric... Agent: Farjami & Farjami LLP

20080057637 - Method for manufacturing semiconductor device: A method is provided for manufacturing a semiconductor device. The method may be capable of simplifying the formation of wells by reducing the number of process steps. In the method for manufacturing a semiconductor device including a high voltage device and a low voltage device, a P-well is formed simultaneously... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080057636 - Strained semiconductor device and method of making same: A method of making a semiconductor device is disclosed. A first heavily doped region of a first conductivity type is implanted in a first portion of the semiconductor body and a first upper surface anneal is performed. After performing the first upper surface anneal, a second heavily doped region of... Agent: Slater & Matsil LLP

20080057638 - Method of manufacturing a flash memory device: A method of manufacturing a flash memory device includes etching portions of a tunnel oxide layer, a first polysilicon layer, a hard mask layer and a semiconductor substrate all of which are laminated over a semiconductor substrate to form trenches. The trenches are filled with an insulating layer thereby forming... Agent: Townsend And Townsend And Crew, LLP

20080057640 - Method for fabricating first electrode of capacitor: A method for fabricating a first electrode of a capacitor is described. A substrate comprising an insulating layer formed thereon is provided. The insulating layer has an opening. A silicon layer is formed on the insulating layer. The silicon layer is transformed to a hemispherical grain layer. An etching process... Agent: J C Patents, Inc.

20080057639 - Semiconductor constructions, and methods of forming semiconductor constructions and flash memory cells: Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the... Agent: Wells St. John P.s.

20080057641 - Semiconductor device with capacitors and its manufacture method: An interlayer insulating film (22) is formed on a semiconductor substrate. A conductive plug (25) is embedded in a via hole formed through the interlayer insulating film. An oxygen barrier conductive film (33) is formed on the interlayer insulating film and being inclusive of an area of the conductive plug... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080057642 - Semiconductor device having polycide wiring layer, and manufacturing method of the same: A semiconductor device is provided with a semiconductor substrate comprising element isolation regions and an element region surrounded by the element isolation regions, a first polysilicon layer formed in the element region of the semiconductor substrate, an element-isolating insulation film formed in the element isolation region of the semiconductor substrate,... Agent: Foley And Lardner LLP Suite 500

20080057645 - Fabricating method of mosfet with thick gate dielectric layer: The fabricating method of a thick gate dielectric layer transistor is disclosed. A substrate including a first and a second regions and isolation structures is provided. A pad layer and a masking layer are formed on the substrate between the isolation structures. After the masking layer and the pad layer... Agent: J C Patents, Inc.

20080057643 - Memory and method of reducing floating gate coupling: Reduction in floating gate to floating gate coupling in non-volatile memories is accomplished with a conductor interposed between floating gates of adjacent memory cells, the conductor connected to a common source/drain region between adjacent cells, and spaced apart from the floating gates and control gates of adjacent memory cells to... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20080057644 - Semiconductor devices having a convex active region and methods of forming the same: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of... Agent: Myers Bigel Sibley & Sajovec

20080057646 - Nonvolatile memory device and methods of fabricating and driving the same: Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection gates on the lateral faces of the nitride layer; depositing... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080057647 - Structure and method of fabricating high-density, trench-based non-volatile random access sonos memory cells for soc applications: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to... Agent: Scully, Scott, Murphy & Presser, P.C.

20080057648 - Direct tunneling semiconductor memory device and fabrication process thereof: A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both sidewall surfaces and a top surface of a floating gate electrode formed on the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080057649 - Recessed-gate thin-film transistor with self-aligned lightly doped drain: A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080057650 - Semiconductor device: In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si... Agent: Miles & Stockbridge PC

20080057651 - Method of manufacturing non-volatile memory: A method of manufacturing a non-volatile memory including the following steps is provided. First, a dielectric layer, a first conductive layer and a patterned mask layer are sequentially formed on a substrate. A portion of the first conductive layer is removed using the patterned mask layer as a mask to... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080057652 - Ion implantation method of semiconductor device: Embodiments relate to an ion implantation method wherein a semiconductor substrate is divided into a core region, a high voltage region, and an I/O region. The core region and the I/O region are divided into a PMOS transistor region for forming PMOS transistors and an NMOS transistor region for forming... Agent: Sherr & Nourse, PLLC

20080057653 - Method and structure for improving device performance variation in dual stress liner technology: A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By... Agent: Scully Scott Murphy & Presser, PC

20080057654 - Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same: The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine,... Agent: Texas Instruments Incorporated

20080057655 - Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel: A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to... Agent: Jianq Chyun Intellectual Property Office

20080057656 - Method of manufacturing semiconductor device: A method is provided for forming a lightly-doped drain (LDD) area of a transistor by means of a single implant process. The method includes implanting a dopant under a process condition of an ;implantation energy of 10 KeV or less and a dose of 1.5×1014 to 3.0×1014 ions/cm2. The method... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080057657 - Method for fabrication of semiconductor device: A method of fabricating a semiconductor device is provided. The method includes: stacking a gate insulation layer and a polysilicon layer on a semiconductor substrate; forming a photoresist layer on the polysilicon layer; forming a gate stack by etching the gate insulation layer and the polysilicon layer; performing a first... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080057659 - Hafnium aluminium oxynitride high-k dielectric and metal gates: Electronic apparatus and methods of forming the electronic apparatus include a hafnium aluminum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium aluminum oxynitride film may be structured as one or more monolayers. The hafnium aluminum oxynitride film may be formed using atomic layer... Agent: Schwegman, Lundberg & Woessner, P.A.

20080057658 - Method for fabricating a thick copper line and copper inductor resulting therefrom: A method of forming one or more inductors on a substrate is disclosed. The method includes forming a first dielectric material over the substrate, forming a trench in the first dielectric material, and substantially filling the trench with copper to form the one or more inductors. The first dielectric material... Agent: Schneck & Schneck

20080057660 - Step-gate for a semiconductor device: A semiconductor device using a recessed step gate. An embodiment comprises a recessed region in a portion of the substrate, a transistor with one source/drain region located within the recessed region and one source/drain region located out of the recessed region, a storage device connected to the source/drain located out... Agent: Slater & Matsil, L.L.P.

20080057661 - Fabricating method of semiconductor device: A fabricating method of a semiconductor device includes: forming a first metal layer on a substrate and patterning the first metal layer to form a bottom metal line and a bottom electrode of a capacitor; forming an interlayer insulating layer on the resulting structure; forming a via hole in the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080057662 - Stud capacitor device and fabrication method: The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the substrate and the recess, depositing a filler layer so... Agent: Knobbe Martens Olson & Bear LLP

20080057663 - Low leakage mim capacitor: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. Attn: Timothy B. Clise

20080057664 - Low leakage mim capacitor: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer... Agent: Schwegman, Lundberg & Woessner/micron

20080057665 - Strained semiconductor device and method of making same: To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can... Agent: Slater & Matsil LLP

20080057666 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes providing a semiconductor substrate with gate structures. A sacrificial insulating layer is formed between the gate structures at a height lower than that of the gate structures such that a portion of each gate structure is exposed above the sacrificial insulating layer.... Agent: Townsend And Townsend And Crew, LLP

20080057668 - Method for fabricating semiconductor device: According to the present invention, a method for fabricating a semiconductor device includes: providing a semiconductor substrate; forming a STI region on the semiconductor substrate; forming a channel region on the semiconductor substrate; implanting impurities into the STI region; and performing a thermal treatment to diffuse impurities to a side... Agent: Volentine & Whitt PLLC

20080057669 - Method of forming element isolation film and nonvolatile semiconductor memory: An element isolation film is formed by filling an oxide in a trench formed in an element isolation region of a semiconductor substrate to thereby form an insulation film for element isolation. A method of forming the element isolation film includes a first step of depositing a material in a... Agent: Rabin & Berdo, PC

20080057667 - Test structure and method for detecting via contact shorting in shallow trench isolation regions: A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI... Agent: Cantor Colburn LLP - IBM Fishkill

20080057670 - Semiconductor device and method of fabricating the same: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A... Agent: F. Chau & Associates, LLC

20080057671 - Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080057672 - Shallow trench isolation structures and a method for forming shallow trench isolation structures: A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is... Agent: Hitt Gaines, PC Lsi Corporation

20080057673 - Semiconductor structure and method of making same: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate... Agent: Greenblum & Bernstein, P.L.C

20080057674 - Method for manufacturing sip semiconductor device: A method for manufacturing an SIP semiconductor device is provided. In this method, a first Organic Solderability Preservative (OSP) is coated over an upper surface of a semiconductor device including a plurality of elements and a first through electrode. An electrochemical plate (ECP) process is then performed on the semiconductor... Agent: Sherr & Nourse, PLLC

20080057675 - Method and device for controlled cleaving process: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of... Agent: Townsend And Townsend And Crew, LLP

20080057676 - Bonded wafer and method for producing bonded wafer: A bonded wafer is produced by directly bonding a silicon wafer for active layer and a silicon wafer for support substrate without an insulating film and thinning the silicon wafer for active layer to a given thickness, in which a silicon wafer cut out from an ingot at a cutting... Agent: Sughrue Mion, PLLC

20080057677 - Chip location identification: Chip location identification using dummy solder bead(s) is disclosed. A structure may include an integrated circuit (IC) chip including a plurality of solder beads for electrically coupling the IC chip to other structure, and a chip location identifier including at least one dummy solder bead on the IC chip, the... Agent: Hoffman, Warnick & D'alessandro LLC

20080057678 - Semiconductor on glass insulator made using improved hydrogen reduction process: Methods and apparatus for producing a semiconductor on glass (SiOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; reducing a concentration of hydrogen at least at the implantation surface of the donor... Agent: Corning Incorporated

20080057679 - Method of scribing stuck mother substrate and method of dividing stuck mother substrate: There is provided a method of scribing a stuck mother substrate for obtaining a plurality of stuck substrates formed by sticking a first square substrate and a second square substrate together so that one side of opposing two sides of the square substrates is aligned and the other side is... Agent: Workman Nydegger

20080057680 - Wafer laser processing method: carrying out a second laser processing step of carrying out laser processing along streets formed in the other half area of the wafer by carrying out a laser beam application step for applying a laser beam along the streets by positioning the outermost street on the other side in the... Agent: Smith, Gambrell & Russell

20080057681 - Dynamic surface annealing of implanted dopants with low temperature hdpcvd process for depositing a high extinction coefficient optical absorber layer: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature,... Agent: Law Office Of Robert M. Wallace

20080057682 - Manufacturing method of an integrated circuit formed on a semiconductor substrate: An embodiment of a method for manufacturing an integrated circuit formed on a semiconductor substrate comprising the steps of: forming at least one shielding structure on said semiconductor substrate, forming a protective layer at least on portions of the semiconductor substrate that surround said shielding structure, carrying out a ionic... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20080057684 - Method for fabricating low-defect-density changed orientation si: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention... Agent: Scully, Scott, Murphy & Presser, P.C.

20080057683 - Method for junction formation in a semiconductor device and the semiconductor device made thereof: Devices and methods for junction formation in manufacturing a semiconductor device are disclosed. The devices have shallow junction depths far removed from end-of range defects. The method comprises forming an amorphous region in a crystalline semiconductor such as silicon down to a first depth, followed by implantation of a substitutional... Agent: Knobbe Martens Olson & Bear LLP

20080057685 - Method for forming doped metal-semiconductor compound regions: A method for forming doped metal-semiconductor compound regions in a substrate is disclosed. In one aspect, a method for forming silicide regions in a substrate comprises partially regrowing an upper amorphous region on top of a crystalline part of the substrate, after having doped the upper amorphous region, to form... Agent: Knobbe Martens Olson & Bear LLP

20080057686 - Continuous dopant addition: A continuous dopant coater with improved control of the coating environment and methods and systems relating to the coater. Embodiments of the dopant coater may include a containment chamber and a coating chamber and the use of an inerting media to control the environment within and around the coater.... Agent: Intellectual Property Group Fredrikson & Byron, P.A.

20080057687 - Selective area deposition and devices formed therefrom: Patterned thin film layers (12) are applied to a substrate (10) surface by masking selective areas of a substrate surface, e.g., with a printed pattern (11) of a material such as an oil, and vapor-depositing thin film material. The masking material is subsequently removed.... Agent: Ngimatco. Microcoating Technologies, Inc.

20080057688 - Method of forming bit line of semiconductor memory device: A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which... Agent: Townsend And Townsend And Crew, LLP

20080057689 - Method of fabricating semiconductor integrated circuit device: Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer... Agent: Mills & Onello LLP

20080057690 - Tantalum silicon oxynitride high-k dielectrics and metal gates: Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using atomic layer... Agent: Schwegman, Lundberg & Woessner, P.A.

20080057693 - Electrical conductivity bridge in a conductive multilayer article: A method comprises providing a first electrically-conductive circuit-path (22), and separately providing a second electrically-conductive circuit-path (24). A portion of the first circuit-path is positioned proximally adjacent a portion of the second circuit-path at a first predetermined electrical bond location (26). A first, electrically-insulating barrier layer (28) is interposed between... Agent: Kimberly-clark Worldwide, Inc. Catherine E. Wolf

20080057694 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, in forming plugs, an alignment error margin between wirings and lower plugs is increased by using a conductive pad and thus avoids an increase of a contact resistance caused by an alignment error and improves reliability.... Agent: Marshall, Gerstein & Borun LLP

20080057691 - Methods and systems for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum: Methods of forming a conductive via in a substrate include contacting the substrate with a wave of conductive liquid material, such as molten solder, and drawing the liquid material into the aperture with a vacuum. The wave may be formed by flowing the liquid material out from an outlet in... Agent: Trask Britt

20080057692 - Single spacer process for multiplying pitch by a factor greater than two and related intermediate ic structures: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over... Agent: Knobbe Martens Olson & Bear LLP

20080057695 - Semiconductor and method for manufacturing the same: A semiconductor device includes a substrate formed with a predetermined trench, a plurality of devices fixed into the trench, an etch stop layer on an entire surface of the substrate including the devices while selectively exposing the devices, an interlayer dielectric layer on the etch stop layer, in which the... Agent: Sherr & Nourse, PLLC

20080057696 - Method of forming crack arrest features in embedded device build-up package and package thereof: A method of forming an embedded device build-up package (10) includes forming a first plurality of features (22) over a packaging substrate (12,16,18), wherein the first plurality of features (22) comprises a first feature and a second feature, forming at least a first crack arrest feature (28) in a first... Agent: Freescale Semiconductor, Inc. Law Department

20080057698 - Method of manufacturing semiconductor device: Provided are: a method of manufacturing semiconductor device which has multilayer interconnection in a damascene structure and a conductive barrier film such as CoWP film, and which has more excellent electric characteristics than a conventional one. To this end, when a via hole reaching a lower wiring is formed, a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080057697 - Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stress and structures formed thereby: Methods of forming interconnect structures include forming a first metal wiring pattern on a first dielectric layer and forming a capping layer (e.g., SiCN layer) on the first copper wiring pattern. An adhesion layer is deposited on the capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a... Agent: Myers Bigel Sibley & Sajovec

20080057699 - Method for manufacturing semiconductor device: Provided is a method for manufacturing a semiconductor device. In the method, an insulating layer is formed on a substrate. A via hole and a trench are formed in the insulating layer. A TiN layer may be formed in the via hole and the trench by physical vapor deposition (PVD).... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080057700 - Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device using the same: Disclosed are an apparatus and a method for manufacturing a semiconductor device. The apparatus comprises a transfer chamber for transferring a substrate, a first process chamber connected to the transfer chamber configured to form a TiSiN layer on the substrate, a second process chamber connected to the transfer chamber configured... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080057702 - Mehtod of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming an inter-layer insulating film on a silicon substrate, drying etching the inter-layer insulating film with an etching gas containing halogen using a mask of an organic material, forming a contact hole at a predetermined position on the inter-layer insulating film, separating... Agent: Pearne & Gordon LLP

20080057701 - Method for prevention of resist poisoning in integrated circuit fabrication: A method of manufacturing an integrated circuit comprising fabricating a dual damascene interconnect. Fabricating the interconnect including forming a via opening in a surface of an inter-layer dielectric (ILD) located over a semiconductor substrate. Fabricating the interconnect also includes depositing a sacrificial fill material over the surface and in the... Agent: Texas Instruments Incorporated

20080057703 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin Room 301/302, No. 47

20080057704 - Semiconductor device with a barrier film: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080057705 - Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics: By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer... Agent: Williams, Morgan & Amerson

20080057706 - Method for forming cyclinder type storage node for preventing creation of watermarks: A cylinder type storage node is made by, inter alia: forming a sacrificial oxide layer containing organic material over a semiconductor substrate; defining holes for storage nodes by etching the sacrificial oxide layer; forming storage nodes on surfaces of the holes; and removing the sacrificial oxide layer through wet etching... Agent: Ladas & Parry LLP

20080057707 - Method for forming contacts of semiconductor device: A method for forming contacts of a semiconductor device is provided. A diffusion barrier layer, an interlayer insulating layer, and a capping layer are sequentially formed on a lower metal wiring layer. A hard mask layer is formed on the capping layer. A photoresist layer is formed and patterned to... Agent: Sherr & Nourse, PLLC

20080057708 - Method for filling a trench in a semiconductor product: Method for filling a trench in a semiconductor product is disclosed. A first material is deposited onto a semiconductor product having a surface in which at least one trench is formed. A first layer is formed within the trench and on the surface of the semiconductor product outside the trench.... Agent: Slater & Matsil LLP

20080057709 - Method and apparatus for workpiece surface modification for selective material deposition: Methods and apparatus are provided for selective modification of the surface of a workpiece. In some embodiments, using a workpiece-surface-influencing device that preferentially contacts the top surface of the workpiece, chemical modification of the top surface is achieved on desired field areas of the workpiece without affecting the surfaces of... Agent: Knobbe Martens Olson & Bear LLP

20080057710 - Mosfets comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that... Agent: Scully, Scott, Murphy & Presser, P.C.

20080057711 - Reduction of punch-thru defects in damascene processing: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric... Agent: Texas Instruments Incorporated

20080057712 - Method for achieving uniform etch depth using ion implantation and a timed etch: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to... Agent: Bever, Hoffman & Harms, LLP

20080057713 - Silicon carbide polishing method utilizing water-soluble oxidizers: The inventive method comprises chemically-mechanically polishing a substrate comprising at least one layer of silicon carbide with a polishing composition comprising a liquid carrier, an abrasive, and an oxidizing agent.... Agent: Steven Weseman Associate General Counsel, I.p.

20080057714 - Polished semiconductor wafer and process for producing it: A polished semiconductor wafer has a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer.... Agent: Brooks Kushman P.C.

20080057715 - Cmp system utilizing halogen adduct: The invention provides a chemical-mechanical polishing system for polishing a substrate comprising (a) a polishing component selected from an abrasive, a polishing pad, or both an abrasive and a polishing pad, (b) an aqueous carrier, and (c) the halogen adduct resulting from the reaction of (1) an oxidizing agent selected... Agent: Steven Weseman Associate General Counsel, I.p.

20080057716 - Metal-polishing composition and chemical-mechanical polishing method: A metal-polishing composition includes colloidal silica particles, which has a ratio of minor axis/major axis of 0.2 to 0.8 and a surface at least partially covered with aluminum atoms, comprises in an amount of 50% or more with respect to total abrasives. The metal-polishing composition preferably includes an oxidizing agent,... Agent: Sughrue Mion, PLLC

20080057718 - Method for manufacturing semiconductor device: A technique for increasing productivity by simplified steps in a manufacturing process of TFTs, electronic circuits using TFTs, and semiconductor devices formed of TFTs is provided. A method for manufacturing a semiconductor device includes forming a light absorbing layer, forming a light-transmitting layer on the light absorbing layer emitting a... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080057719 - Method and apparatus for fabricating or altering microstructures using local chemical alterations: A method and apparatus for fabricating or altering a microstructure use means for heating to facilitate a local chemical reaction that forms or alters the submicrostructure.... Agent: Moser, Patterson & Sheridan, LLP

20080057717 - Semiconductor device manufacturing method: A semiconductor device manufacturing method that includes depositing a first insulating film on a semiconductor substrate, etching a part of the first insulating film, and performing UV irradiation to the first insulating film.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080057720 - Method for patterning contact etch stop layers by using a planarization process: By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.... Agent: Williams, Morgan & Amerson

20080057721 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer and the substrate using the first... Agent: Sherr & Nourse, PLLC

20080057722 - Fabricating method of semiconductor device: A fuse region and a wiring region are defined on a base to form a fuse in the fuse region of the base. A first insulation film is formed on the base and the fuse. After a first contact opening is formed in the first insulation film in the wiring... Agent: Rabin & Berdo, PC

20080057723 - Image sensor and method for manufacturing the same: A method for manufacturing an image sensor according to embodiments includes forming a transistor over a substrate. A protective layer including boron (B) may be formed, covering the transistor formed over the substrate. The protective layer including the boron may be annealed to move foreign substances including the boron to... Agent: Sherr & Nourse, PLLC

20080057724 - Selective etch chemistries for forming high aspect ratio features and associated structures: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where... Agent: Knobbe Martens Olson & Bear LLP

20080057725 - Method of manufacturing semiconductor device: Disclosed herein a method of manufacturing a semiconductor device, the method including: forming a plurality of layers over a semiconductor substrate having a lower structure including a transistor; forming a photoresist layer over the plurality of layers and patterning the photoresist layer in a contact hole shape; and etching the... Agent: Sherr & Nourse, PLLC

20080057726 - Apparatus and method for fabricating semiconductor device and removing by-products: An apparatus and a method for fabricating a semiconductor device are provided. The method can efficiently remove by-products from a foreline connected to a process chamber. The apparatus includes a remote plasma source, which generates a plasma gas. The plasma gas is guided to the foreline, so as to remove... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080057727 - Method of manufacturing a semiconductor device: Method of manufacturing a semiconductor device including arranging a substrate having a stacked film containing a first insulating film and a second insulating film formed thereon in an etching equipment, etching the first and second insulating film in the etching equipment, the first insulating film comprised of a nitrogen-containing film,... Agent: Young & Thompson

20080057729 - Etch methods to form anisotropic features for high aspect ratio applications: Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively... Agent: Patterson & Sheridan, LLP

20080057728 - Process for fabricating semiconductor device: In a semiconductor device manufacturing method, an etching mask (75b) having a predetermined opening pattern is formed on an etching target film (74) disposed on a target object. Then, an etching process is performed on the etching target film (74) through the opening pattern of the etching mask (75b) within... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080057730 - Method for using a modified post-etch clean rinsing agent: The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from... Agent: Texas Instruments Incorporated

20080057731 - Method for forming finely-structured parts, finely-structured parts formed thereby, and product using such finely-structured part: In a formation method for forming a fine structure in a workpiece (30) containing an etching control component, using an isotropic etching process, a mask (32, 34) having an opening (36) is applied to the workpiece, and the workpiece is etched with an etching solution (38) to thereby form a... Agent: Young & Thompson

20080057732 - Method for manufacturing silicon substrate, method for manufacturing droplet discharging head, and method for manufacturing droplet discharging apparatus: A method for manufacturing a silicon substrate comprises: forming a silicon nitride film on a patterning area on a surface of a silicon base material; forming a silicon oxide film on an area excluding the patterning area on the surface of the silicon base material after forming the silicon nitride... Agent: Workman Nydegger

20080057733 - Method of fabricating a semiconductor integrated circuit device: Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic... Agent: Marger Johnson & Mccollom, P.C.

20080057734 - Apparatus for fabricating a semiconductor device and method of fabricating a semiconductor device using the same: An apparatus for fabricating layers on a semiconductor device comprises a first chamber in which a pad oxide layer and a pad nitride layer are successively formed, and a second chamber in which a pad insulating layer is formed and heated.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080057736 - Method for improving adhesion force between thin films: Methods for improving an adhesive force between thin films of a semiconductor device. In one example embodiment, a method for improving an adhesive force between an HDP-CVD (High Density Plasma-Chemical Vapor Deposition) thin film and a nitride film includes forming a HDP-CVD thin film according to an HDP-CVD method in... Agent: Workman Nydegger

20080057735 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device, wherein an interlayer insulating layer, a lower barrier metal layer, a metal layer having a low resisvitity value, an upper barrier metal layer, a first oxynitride layer, a hard mask layer formed at low temperature, a second oxynitride layer, and an organic Bottom... Agent: Marshall, Gerstein & Borun LLP

20080057737 - System and method for forming a gate dielectric: A method of forming a dielectric stack on a pre-treated surface. The method comprises pre-cleaning a semiconductor wafer to remove native oxide, such as by applying hydrofluoric acid to form an HF-last surface, pre-treating the HF-last surface with ozonated deionized water, forming a dielectric stack on the pre-treated surface and... Agent: Patterson & Sheridan, LLP

20080057738 - Atomic layer deposition apparatus and method for manufacturing semiconductor device using the same: An apparatus for atomic layer deposition (ALD) and methods for manufacturing a semiconductor device using the same. In one example embodiment, an ALD apparatus includes a heater, a plasma device, a distance control unit, and a controller. The heater is configured to have a semiconductor substrate mounted thereon. The plasma... Agent: Workman Nydegger

20080057739 - Defect control in gate dielectrics: A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second... Agent: Texas Instruments Incorporated

20080057740 - Dopant activation in doped semiconductor substrates: Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate... Agent: Townsend And Townsend And Crew LLP / Amat