Semiconductor device manufacturing: process inventions 03/08

20080070325 - Double-masking technique for increasing fabrication yield in superconducting electronics: A new technique is presented for improving the microfabrication yield of Josephson junctions in superconducting integrated circuits. This is based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material,... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080070328 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming a film to be processed having a first film thickness on a semiconductor substrate; forming a region, within the film to be processed, having a second film thickness thinner than the first film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080070329 - Removing dry film resist residues using hydrolyzable membranes: A technique to remove dry film resist residues during solder bump formation. A resist assembly is formed on a metal pad on a substrate. The resist assembly includes a solder resist (SR) layer, a poly-electrolyte multi-layer (PEMU), and a dry film resist (DFR). A SR opening is formed in the... Agent: Intel/blakely

20080070331 - Method for manufacturing a strongly refractive microlens for a light emitting diode with condensation silicone: A method for manufacturing a strongly refractive microlens for an LED with condensation silicone has steps of: forming a mixture of composite nanoparticles and PMMA microspheres, forming a mixture of condensation silicone and photonic crystals and injecting the condensation silicone and photonic crystals onto an LED to form a strongly... Agent: Patenttm.us

20080070340 - Image sensor using thin-film soi: Systems and methods related to an image sensor of one or more embodiments include subjecting a donor semiconductor wafer to an ion implantation process to create an exfoliation layer of semiconductor film on the donor semiconductor wafer, forming an anodic bond between the exfoliation layer and an insulator substrate by... Agent: Corning Incorporated

20080070342 - Methods of manufacturing image sensors: Example embodiments may provide methods of manufacturing an image sensor. Example methods of manufacturing an image sensor may include forming a photoelectric converter in a semiconductor substrate, forming an interlayer insulating film covering a surface of the semiconductor substrate, forming metal wires and an inter-metal insulating film filling between the... Agent: Harness, Dickey & Pierce, P.L.C

20080070343 - Methods for forming an organic thin film using solvent effects, organic thin film formed by the method, and organic electronic device comprising organic thin film: Disclosed is a method for forming an organic thin film using a good solvent and a non-solvent to promote crystallization of an organic material. The method may enable the formation of a dense, uniform, highly ordered organic thin film by a wet process in a simple and an economical manner.... Agent: Harness, Dickey & Pierce, P.L.C

20080070326 - Method for manufacturing semiconductor device: It is an aspect of the embodiments discussed herein to provide a method manufacturing a semiconductor device, including forming a bottom electrode film above a semiconductor substrate, forming an insulating film on the bottom electrode film, forming a top electrode on the insulating film, forming a capacitor insulating film by... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080070327 - Plasma processing method and plasma processing apparatus: In a plasma processing method, a correlation between substrate type data and optical data is obtained by using a multivariate analysis; substrate type data is obtained from optical data based on the correlation when initiating a plasma processing; and a substrate type is determined by using the obtained substrate type... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080070330 - Fabrication method of semiconductor integrated circuit device: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080070332 - Method of fabricating display substrate and method of fabricating display panel using the same: Disclosed is a method of fabricating a display substrate. A black matrix and a color filter layer are formed on a base substrate, and then a transparent electrode and a photoresist layer pattern are sequentially formed. The transparent electrode is patterned using the photoresist layer pattern as a mask to... Agent: H.c. Park & Associates, PLC

20080070333 - Optical semiconductor device and method of manufacturing thereof: A method of manufacturing an optical semiconductor device (16) sealed in a transparent or semitransparent cured silicone body (50) by placing an unsealed optical semiconductor device (16) into a mold (23, 34) and subjecting a transparent or semitransparent curable silicone composition (50) that fills the spaces between the mold and... Agent: Howard & Howard Attorneys, P.C.

20080070334 - Led including photonic crystal structure: A photonic crystal light emitting diode (“PXLED”) is provided. The PXLED includes a periodic structure, such as a lattice of holes, formed in the semiconductor layers of an LED. The parameters of the periodic structure are such that the energy of the photons, emitted by the PXLED, lies close to... Agent: Patent Law Group LLP

20080070335 - Method of fabricating a semiconductor device: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080070336 - Semiconductor layer formed by selective deposition and method for depositing semiconductor layer: In a method for fabricating a nitride-based semiconductor laser which forms, by a selective deposition, a current narrowing structure and a structure confining a light in a horizontal direction in parallel to a substrate, when the nitride-based semiconductor is selectively deposited by a metal organic chemical vapor deposition, silicon generated... Agent: Sughrue Mion, PLLC

20080070337 - Light emitting element and method of making same: A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (AlXInYGa(1-X-Y))2O3 where 0≦x≦1, 0≦y≦1 and 0≦x+y≦1. The pn-junction has first conductivity type substrate, and GaN system compound semiconductor thin film of second conductivity type opposite... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20080070339 - Method for one-way coupling an input signal to an integrated circuit: A method for one-way coupling an input signal to an integrated circuit on a semiconductor chip with the integrated circuit electrically isolated from the input signal comprises forming a MOS isolation coupler on the semiconductor chip by a CMOS process. The MOS isolation coupler comprises an inductor coil for generating... Agent: Wolf Greenfield & Sacks, P.C.

20080070338 - Micro-electromechanical system (mems) based current & magnetic field sensor having capacitive sense components: A micro-electromechanical system (MEMS) based current & magnetic field sensor includes a MEMS-based magnetic field sensing component having a capacitive magneto-MEMS component, a compensator and an output component for sensing magnetic fields and for providing, in response thereto, an indication of the current present in a respective conductor to be... Agent: General Electric Company Global Research

20080070341 - Photoelectric conversion device, and process for its fabrication: In a photoelectric conversion device comprising a photoelectric-conversion section and a peripheral circuit section where signals sent from the photoelectric-conversion section are processed, the both sections being provided on the same semiconductor substrate, a semiconductor compound layer of a high-melting point metal is provided on the source and drain and... Agent: Fitzpatrick Cella Harper & Scinto

20080070344 - Prams having a plurality of active regions located vertically in sequence and methods of forming the same: There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one... Agent: Mills & Onello LLP

20080070345 - Structure of high performance combo chip and processing method: A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the... Agent: Megica Corporation

20080070346 - Structure of high performance combo chip and processing method: A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the... Agent: Megica Corporation

20080070347 - Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device: There is provided a semiconductor device manufacturing method which prevents cracking of an overcoat during polishing process, and a semiconductor wafer and a semiconductor device which have an overcoat free from cracking. A plurality of divided overcoats 10 are formed on each chip 3 in a chip region 2 and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080070348 - Method for fabricating resin-molded semiconductor device having posts with bumps: A semiconductor apparatus includes a semiconductor device to be mounted on a circuit board; a plurality of conductive posts electrically connected to the semiconductor device; and a plurality of conductive bumps each provided on an outer end of each of the conductive posts, so that the plurality of conductive bump... Agent: Rabin & Berdo, PC

20080070349 - Formation of holes in substrates using dewetting coatings: Methods and systems for forming holes in a substrate using dewetting coating are described herein.... Agent: Schwabe, Williamson & Wyatt, P.C.

20080070350 - Semiconductor device and method of forming a semiconductor device: A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one. example, a region of the second conductivity type is provided at the second end of... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080070351 - Manufacturing method of display device: In a display device manufacturing method including a step of forming a semiconductor film above a substrate and a step of implanting an impurity to each of a first semiconductor film in a first region of the substrate, a second semiconductor film in a second region outside the first region,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080070352 - Method of manufacturing a semiconductor device: An impurity of one conductivity type is ionized and accelerated by electric field before being implanted into a semiconductor layer to form a high concentration impurity region near its surface. Then the semiconductor layer is irradiated with continuous wave laser light for melting and crystallization or recrystallization, through which a... Agent: Eric Robinson

20080070353 - Lithographic apparatus and device manufacturing method: The present invention relates to a lithographic apparatus including an illumination system configured to condition a radiation beam; a support constructed to support a first and a second patterning device, each patterning device being capable of imparting the radiation beam with a pattern in its cross-section to form a patterned... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080070354 - Site-specific nanoparticle self-assembly: Disclosed herein are methods of self-assembling nanoparticles on specific sites of a substrate. The method generally includes introducing a p-type dopant species to at least a portion of an n-type substrate or introducing an n-type dopant species to at least a portion of a p-type substrate, wherein the dopant species... Agent: Cantor Colburn, LLP

20080070355 - Aspect ratio trapping for mixed signal applications: Structures and methods for their formation include a substrate comprising a first semiconductor material, with a second semiconductor material disposed thereover, the first semiconductor material being lattice mismatched to the second semiconductor material. Defects are reduced by using an aspect ratio trapping approach.... Agent: Goodwin Procter LLP Patent Administrator

20080070356 - Trench replacement gate process for transistors having elevated source and drain regions: The method for forming a semiconductor device arrangement with raised source/drains includes depositing a raised source/drain layer on a substrate, followed by a sacrificial layer on the raised source/drain layer. A trench is formed in the sacrificial layer and the raised source/drain layer, and sidewall spacers are formed within the... Agent: Mcdermott Will & Emery LLP

20080070357 - Structure and method to optimize strain in cmosfets: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N... Agent: Scully, Scott, Murphy & Presser, P.C.

20080070358 - Semiconductor device: Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across... Agent: Mcdermott Will & Emery LLP

20080070359 - Semiconductor device including mos field effect transistor having offset spacers of gate sidewall films on either side of gate electrode and method of manufacturing the same: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film... Agent: Foley And Lardner LLP Suite 500

20080070360 - Method and structure for forming silicide contacts on embedded silicon germanium regions of cmos devices: A method of forming silicide contacts for a complementary metal oxide semiconductor (CMOS) device includes selectively forming a protective layer over faceted surfaces of an embedded SiGe (eSiGe) region of a substrate, the eSiGe region comprising a compressive stress inducing layer in a PFET portion of the CMOS device, wherein... Agent: Cantor Colburn LLP - IBM Fishkill

20080070361 - Method of manufacturing a capacitor and method of manufacturing a dynamic random access memory device using the same: In a method of manufacturing a capacitor and a method of manufacturing a dynamic random access memory device, an insulating layer covering an upper portion of a conductive layer may be provided with an ozone gas so as to change the property of the upper portion of the insulating layer.... Agent: Harness, Dickey & Pierce, P.L.C

20080070362 - Method of manufacturing a non-volatile nand memory semiconductor integrated circuit: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080070363 - Method of making an array of non-volatile memory cells with floating gates formed of spacers in substrate trenches: In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements are positioned along sidewalls of substrate trenches, preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes... Agent: Davis Wright Tremaine LLP

20080070364 - Vertical memory device and method: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the... Agent: Kacvinsky LLC C/o Intellevate

20080070365 - Shielded gate fet with self-aligned features: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants.... Agent: Townsend And Townsend And Crew, LLP

20080070366 - Multi-gate device with high k dielectric for channel top surface: A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the... Agent: Greenblum & Bernstein, P.L.C

20080070368 - Method of manufacturing a non-volatile memory device: In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be... Agent: Harness, Dickey & Pierce, P.L.C

20080070367 - Methods to create dual-gate dielectrics in transistors using high-k dielectric: A method including forming a gate dielectric film on a surface of a substrate; selectively increasing a physical thickness of a gate dielectric including the gate dielectric film in a first area designated for devices to be operated within a first voltage range; forming a first device in the first... Agent: Intel/blakely

20080070369 - Mos transistor device structure combining si-trench and field plate structures for high voltage device: A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field;... Agent: North America Intellectual Property Corporation

20080070371 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a substrate, a gate electrode, a pair of first impurity regions, a pair of second impurity regions and at least one dummy pattern. The gate electrode is positioned above the substrate. The first impurity regions are positioned in the substrate and near both sides of the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080070370 - Silicide formation with a pre-amorphous implant: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal... Agent: Slater & Matsil, L.L.P.

20080070372 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, an insulating layer pattern defining at least one opening partially exposing a semiconductor substrate is formed on a semiconductor substrate including a single crystalline material. An amorphous thin layer is formed on the insulating layer pattern to fill up the opening. The... Agent: Marger Johnson & Mccollom, P.C.

20080070373 - Manufacturing method of a memory device: A method of manufacturing a memory device. The memory device comprises a trench in a substrate, a capacitor at the low portion of the trench, a collar dielectric layer overlying the capacitor and covering a portion of the sidewall of the trench, and a conductive layer filling a portion of... Agent: Quintero Law Office, PC

20080070374 - Method for forming trench capacitor and memory cell: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used... Agent: North America Intellectual Property Corporation

20080070375 - Method for fabricating a storage electrode of a semiconductor device: A method for fabricating a storage electrode of a semiconductor device includes forming an interlayer dielectric film including a storage node contact on a semiconductor substrate, forming an etching blocking layer on the interlayer dielectric film, forming a mold insulating layer on the etching blocking layer, the mold insulating layer... Agent: Marshall, Gerstein & Borun LLP

20080070376 - Method of wafer-to-wafer bonding: Methods of wafer-to-wafer bonding are disclosed. These methods use a force-transposing substrate providing redistribution of the applied force to the local bonding areas across the wafer. Certain versions of the Present Invention also provide a compliant force-distributing member along with applying bonding material to bonding areas in selectable locations. A... Agent: Fitch Even Tabin And Flannery

20080070377 - Method of producing bonded wafer: A method of producing a bonded wafer, comprising: performing bonding of a first semiconductor wafer and a second semiconductor wafer without interposing an insulation film in between; and performing thinning of the second semiconductor wafer, wherein surface portions at least including bonded surfaces of the first semiconductor wafer and the... Agent: Kolisch Hartwell, P.C.

20080070378 - Dual laser separation of bonded wafers: A system for dicing a bonded wafer includes a plurality of substrates having at least a first substrate bonded to at least a second substrate. A first laser is configured to emit a first laser beam at a first predetermined wavelength such that the first laser beam creates a modified... Agent: Hewlett Packard Company

20080070379 - Method of fabricating semiconductor device: The present invention provides a method of manufacturing a semiconductor device capable of preventing a cut portion from becoming chipped when dicing. The method of manufacturing a semiconductor device includes preparing a semiconductor wafer having an upper surface (first surface) including a plurality of device regions and partition regions for... Agent: Volentine & Whitt PLLC

20080070380 - Production method of compound semiconductor device wafer: An object of the present invention is to provide a method for producing a compound semiconductor device wafer, which method enables cleaving of a wafer with precision and at remarkably high yield, attains high process speed, and improves productivity. The inventive method for producing a compound semiconductor device wafer, the... Agent: Sughrue Mion, PLLC

20080070381 - Semiconductor wafer, method of manufacturing the same, and method of manufacturing a semiconductor device: In a semiconductor wafer including a plurality of element forming regions formed on a front surface of a semiconductor substrate, a scribe line groove is formed along a periphery of the each of the element forming regions, and stoppers are located at an intersection of the scribe line groove, so... Agent: Mcginn Intellectual Property Law Group, PLLC

20080070382 - Fixing apparatus for semiconductor wafer: A wafer fixing apparatus is disclosed including a dicing stage structured to fix a semiconductor wafer. A die attach film is disposed on the dicing stage to attach the semiconductor wafer to the dicing stage. The die attach film attaches the semiconductor wafer to the dicing stage due to the... Agent: Marger Johnson & Mccollom, P.C.

20080070383 - Rectifying contact to an n-type oxide material or a substantially insulating oxide material: A rectifying contact to an n-type oxide material and/or a substantially insulating oxide material includes a p-type oxide material. The p-type oxide material includes a copper species and a metal species, each of which are present in an amount ranging from about 10 atomic % to about 90 atomic %... Agent: Hewlett Packard Company

20080070384 - Formation of strain-inducing films using hydrogenated amorphous silicon: A method to form a strain-inducing epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is a three-component epitaxial film comprising atoms from a parent film, charge-neutral lattice-substitution atoms and charge-carrier dopant impurity atoms. In another embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch cycle... Agent: Intel/blakely

20080070385 - Water-barrier performance of an encapsulating film: A method and apparatus for depositing a material layer onto a substrate is described. The method includes delivering a mixture of precursors for the material layer into a process chamber and depositing the material layer on the substrate at low temperature. The material layer can be used as an encapsulating... Agent: Patterson & Sheridan, LLP

20080070386 - Device for irradiating a laser beam: A device for irradiating a laser beam onto an amorphous silicon thin film formed on a substrate. The device includes: a stage mounting the substrate; a laser oscillator for generating a laser beam; a projection lens for focusing and guiding the laser beam onto the thin film; a reflector for... Agent: Macpherson Kwok Chen & Heid LLP

20080070387 - Semiconductor device manufacturing method: A technique is provided which enables formation of nitride semiconductor layers with excellent flatness and excellent crystallinity on a gallium nitride substrate (GaN substrate), while improving the producibility of the semiconductor device using the GaN substrate. A gallium nitride substrate is prepared which has an upper surface having an off-angle... Agent: Leydig Voit & Mayer, Ltd

20080070388 - Compound semiconductor device epitaxial growth substrate, semiconductor device, and manufacturing method thereof: A compound semiconductor device epitaxial growth substrate, wherein a semiconductor substrate, a substrate protective layer made of a material that is different from the material of the substrate, a middle layer for making separation of the semiconductor substrate and a compound semiconductor device layer possible, and a compound semiconductor device... Agent: Nixon & Vanderhye, PC

20080070389 - Apparatus and method for doping: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a... Agent: Fish & Richardson P.C.

20080070390 - Method and apparatus for semiconductor device and semiconductor memory device: A method comprises providing a first conductive region, arranging a second conductive region adjacent to and insulated from the first conductive region by a dielectric region, arranging a third region adjacent to and insulated from the second conductive region, and adjusting mechanical stress to at least one of the first... Agent: Harness, Dickey & Pierce P.L.C

20080070391 - Anti-halo compensation: An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type in the substrate. By implanting... Agent: Greenblum & Bernstein, P.L.C

20080070392 - Controlling diffusion in doped semiconductor regions: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first... Agent: Schwegman, Lundberg & Woessner/micron

20080070393 - Method for manufacturing semiconductor device: In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes that use a photoresist and simplifying the process is provided, which improves throughput. An etching mask for forming a pattern of a layer to be processed such as a conductive layer or... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080070394 - Mos transistor in an active region: After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon nitride is removed, thereby a contact hole... Agent: Mcdermott Will & Emery LLP

20080070395 - Semiconductor devices and methods with bilayer dielectrics: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k... Agent: Haynes And Boone, LLP

20080070396 - Group ii element alloys for protecting metal interconnects: A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and method to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the... Agent: Intel/blakely

20080070397 - Methods for selective placement of dislocation arrays: Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.... Agent: Goodwin Procter LLP Patent Administrator

20080070398 - Method for fabricating semiconductor device having metal fuse: Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an... Agent: Marshall, Gerstein & Borun LLP

20080070399 - Process for forming low defect density heterojunctions: A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux... Agent: Ketan S. Vakil, Esq. Snell & Wilmer L.L.P.

20080070400 - Semiconductor device and manufacturing method thereof: When forming a silicon nitride film to protect and insulate a surface on which a silicon substrate has been ground or polishing, by use of a mixed gas containing SiH4, N2, and NH3 as a reaction gas, a film is formed by a single-frequency parallel-plate plasma CVD method. Thereby, even... Agent: Mcginn Intellectual Property Law Group, PLLC

20080070401 - Memory device and method for manufacturing the same: A memory device and a method for fabricating the same provide a device capable of increasing or maximizing the performance of a microstructure device. The device includes: a plurality of word lines formed with a gap therebetween and extending in parallel with each other in a first direction of extension;... Agent: Mills & Onello LLP

20080070402 - Method of forming contact hole pattern in semiconductor integrated circuit device: A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080070403 - Method and arrangement for contacting terminals: In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact... Agent: Maginot, Moore & Beck Chase Tower

20080070404 - Methods of manufacturing semiconductor devices and structures thereof: Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The... Agent: Slater & Matsil LLP

20080070405 - Methods of forming metal wiring layers for semiconductor devices: A method of forming a conductive plug for an integrated circuit device may include forming an insulating layer on an integrated circuit substrate with the insulating layer having a surface opposite the substrate and a recess therein. A titanium (Ti) layer may be formed on sidewalls of the recess and... Agent: Myers Bigel Sibley & Sajovec

20080070407 - Method for forming a conductive pattern in a semiconductor device: A method for forming a conductive pattern in a semiconductor device includes providing an insulation layer including a trench, forming a conductive material over the insulation layer to fill in the trench, polishing the conductive material to expose the insulation layer, and cleaning the resultant structure using a cleaning solution.... Agent: Townsend And Townsend And Crew, LLP

20080070406 - Pattern forming method and semiconductor device manufacturing method using the same: A resist film is formed on a substrate. A conductive layer is formed on the resist film. The resist film is exposed to an electron beam. The conductive layer is removed by a remover whose temperature is equal to or higher than 30° C. and equal to or lower than... Agent: Young & Thompson

20080070408 - Method for adjusting sizes and shapes of plug openings: The invention is directed to a method for adjusting sizes and shapes of plug openings for border plug openings overlapping with trenches respectively, wherein the border plug openings are separated from each other with a distance equal to or smaller than a specific distance. The method comprises performing an adjusting... Agent: J.c. Patents, Inc.

20080070409 - Method of fabricating interconnections of microelectronic device using dual damascene process: Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate,... Agent: Myers Bigel Sibley & Sajovec

20080070410 - Method for manufacturing capacitor using system in package: A method for manufacturing a capacitor is provided. The method includes: forming a first hole, depositing a barrier metal on an inner wall of the first hole to form a first electrode. The method further includes forming a second hole and bottom electrode-hole aligned with the first hole, forming a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080070411 - Methods for uniformly etching films on a semiconductor wafer: A chemical mixture etches chemically different materials, layers, or films on the surface of a semiconductor wafer or other workpiece at approximately the same rate. The different layers may include, for example, a first material, having a first chemical composition, encapsulated within or sandwiched between one or more materials having... Agent: Perkins Coie LLP/semitool

20080070412 - Polishing compound for semiconductor integrated circuit device, polishing method and method for producing semiconductor integrated circuit device: To provide a polishing technique with which in production of a semiconductor integrated circuit device, when a plane to be polished is polished, an appropriate polishing rate ratio of a polysilicon film to another material can be obtained, whereby high level planarization of a plane to be polished including a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080070413 - Fabrication methods of a patterned sapphire substrate and a light-emitting diode: A fabricating method for patterned sapphire substrate is provided. The fabricating method includes the following processes. First, a sapphire substrate is provided, and a mask layer is formed on the sapphire substrate, wherein the mask layer with appropriate pattern exposes a part of the sapphire substrate. Then, a wet etching... Agent: Jianq Chyun Intellectual Property Office

20080070414 - Method for designing mask and method for manufacturing semiconductor device employing thereof: A bias correction level can be defined with an improved efficiency when a transfer pattern of a hole is formed, so that the hole can be stably formed as originally designed. When a hole pattern is formed over a substrate, correction reference holes 103 existing in a region 113, which... Agent: Young & Thompson

20080070415 - Method for burying resist and method for manufacturing semiconductor device: A resist film is applied to an entire surface and subjected to patterning substantially in the same form as an opening to bury the resist film inside the opening. When a positive resist is used, a photomask having a light-shielding portion with an area smaller than the opening is used... Agent: Leydig Voit & Mayer, Ltd

20080070416 - Phase shift mask including a substrate with recess: A phase shift mask includes a quartz substrate having a main surface partially dug, and a Cr film deposited on the main surface. The dug portion includes an undercut provided such that the Cr film partially serves as an eaves, and the Cr film has a π opening exposing a... Agent: Mcdermott Will & Emery LLP

20080070417 - Method of etching semiconductor device and method of fabricating semiconductor device using the same: A method of fabricating a semiconductor device which prevents a pitting phenomenon from occurring on a gate insulating layer is provided. The method of fabricating of a semiconductor device according to the present invention comprises: depositing a first gate material including at least a gate insulating layer and a first... Agent: Mills & Onello LLP

20080070418 - Substrate processing apparatus and substrate processing method: A substrate processing apparatus has a cup part for receiving processing liquid which is applied from a processing liquid applying part and is splashed from a substrate, and the cup part is formed of electrical insulation material. Hydrophilic treatment is performed on an outer annular surface of the cup part... Agent: Ostrolenk Faber Gerb & Soffen

20080070419 - Process of manufacturing a semiconductor device: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the... Agent: Kratz, Quintos & Hanson, LLP

20080070420 - Method of fabricating image sensor: A method of fabricating an image sensor is disclosed, by which etch damage and stress causing dislocation can be reduced in a manner of forming a liner oxide layer and performing thermal hardening simultaneously. A method of fabricating an image sensor according to embodiments may include etching a trench in... Agent: Sherr & Nourse, PLLC

20080070421 - Bi-layer capping of low-k dielectric films: A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A... Agent: Patterson & Sheridan, LLP

20080070423 - Buried seed one-shot interlevel crystallization: A method is provided for crystallizing a semiconductor film using a buried seed one-shot interlevel crystallization process. The method forms a first semiconductor film having a crystallographic structure, overlying a transparent substrate. An insulator layer is formed overlying the first semiconductor film, and an opening is formed in the insulator... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080070422 - Serial irradiation of a substrate by multiple radiation sources: A method for configuring J electromagnetic radiation sources (J≧2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2; J≦I) thereon. Pj denotes a same source-specific normally incident energy flux on... Agent: Schmeiser, Olsen & Watts

20080064124 - Semiconductor device and manufacturing method thereof: An IrOX film of a thickness of 50 nm is formed on a PZT film by a sputtering method. The value of x is less than 2. Namely, an unsaturated iridium oxide film is formed. By performing RTA, the PZT film is completely crystallized. Thereafter, an IrOY film of a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080064125 - Extendable connector and network: Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are separated by a first proximate distance and applied in an... Agent: Crawford Maunu PLLC

20080064128 - Annealing apparatus, annealing method, and method of manufacturing a semiconductor device: The present invention provides an annealing apparatus including a heating unit, a storage unit, a calculating unit, and a control unit. The heating unit anneals a target wafer. The storage unit stores reference data which a shape parameter of a reference element, an annealing temperature, and an electrical characteristic of... Agent: Sughrue Mion, PLLC

20080064126 - In-situ wafer temperature measurement and control: Broadly speaking, the embodiments of the present invention fill the need by providing in-situ wafer temperature measuring method and apparatus. The in-situ substrate temperature measuring method and apparatus provide instant wafer temperature information to allow for continuous monitoring of the etching process. The method and apparatus also allow for instant... Agent: Martine Penilla & Gencarella, LLP

20080064127 - Method and system for yield and productivity improvements in semiconductor processing: A semiconductor processing method includes processing a first substrate while detecting at least one first processing parameter value in a first apparatus. The first processing parameter is analyzed, thereby yielding at least one first predicted parameter value. The first predicted parameter value is compared with a first pre-defined parameter value,... Agent: Duane Morris LLPIPDepartment (tsmc)

20080064129 - Method of manufacturing a display substrate: A method of manufacturing a display substrate comprises forming a thin-film transistor (TFT) on a silicon wafer, transferring the TFT from the silicon wafer onto a base substrate using a stamp unit and forming a pixel electrode electrically connected to the TFT.... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080064131 - Light emitting apparatus and method for the same: A light emitting apparatus includes a patterned conductive layer, a light emitting device on the patterned conductive layer, and a first light diffusion layer. The light emitting device and the patterned conductive layer are embedded in the first light diffusion layer. A method of forming such a light emitting apparatus... Agent: Snell & Wilmer L.L.P. (main)

20080064135 - Method of manufacturing image sensor: Embodiments relate to a method of manufacturing an image sensor which may include forming a gate pattern including a tunnel oxide film, an oxide-nitride-oxide (ONO) film, a floating gate and a control gate over a semiconductor substrate. An oxide film and a nitride film may be formed over the semiconductor... Agent: Sherr & Nourse, PLLC

20080064130 - Nitride-based light-emitting device and method of manufacturing the same: A nitride-based light-emitting device capable of suppressing reduction of the light output characteristic as well as reduction of the manufacturing yield is provided. This nitride-based light-emitting device comprises a conductive substrate at least containing a single type of metal and a single type of inorganic material having a lower linear... Agent: Mcdermott Will & Emery LLP

20080064132 - Method of fabricating vertical devices using a metal support film: A vertical topology device includes a conductive adhesion structure having a first surface and a second surface, a conductive thick film support formed on the first surface, and a semiconductive device having an upper electrical contact and located over the conductive adhesion layer. Electrical current can flow between the conductive... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20080064133 - Nitride semiconductor light emitting diode and method of manufacturing the same: A flip chip-type nitride semiconductor light emitting diode includes a light transmittance substrate, an n-type nitride semiconductor layer, an active layer, a p-type nitride semiconductor layer and a mesh-type DBR reflecting layer. The mesh-type DBR reflecting layer has a plurality of open regions. The mesh-type DBR reflecting layer is composed... Agent: Lowe Hauptman Ham & Berner, LLP

20080064134 - Methods of making combinational structures for electro-luminscent displays: A picture element for an electro-luminescent display comprises a substrate, a first intermediate structure disposed above a first area of the substrate, at least one first color type electro-luminescent device disposed above the first intermediate structure, a second intermediate structure disposed above a second area of the substrate, and at... Agent: Duane Morris, LLPIPDepartment

20080064136 - Supercritical fluid-assisted deposition of materials on semiconductor substrates: Supercritical fluid-assisted deposition of materials on substrates, such as semiconductor substrates for integrated circuit device manufacture. The deposition is effected using a supercritical fluid-based composition containing the precursor(s) of the material to be deposited on the substrate surface. Such approach permits use of precursors that otherwise would be wholly unsuitable... Agent: Moore & Van Allen PLLC

20080064137 - Method of protecting integrated circuits: The present application relates to the manufacture of Wafer Level Chip Scale Packages (WLCSPs), which are a type of CSP in which the traditional wire bonding arrangements are dispensed with in favour of making direct contact by means of conductive bumps (typically solder balls) to the integrated circuitry. WLCSPs differ... Agent: Wolf Greenfield & Sacks, P.C.

20080064138 - Perimeter matrix ball grid array circuit package with a populated center: A ball grid array (BGA) integrated circuit package which has an outer two-dimensional array of solder balls and a center two-dimensional array of solder balls located on a bottom surface of a package substrate. The solder balls are typically reflowed to mount the package to a printed circuit board. Mounted... Agent: Blakely Sokoloff Taylor & Zafman

20080064139 - Reliable printed wiring board assembly employing packages with solder joints and related assembly technique: An exemplary assembly comprises a printed wiring board having a first surface, and a package including a plurality of solder joints, such as solder balls, on one surface of the package. An anchor via is defined through the first surface of the printed wiring board, and conductive material situated in... Agent: Kyocera Wireless Corp.

20080064140 - Semiconductor device having curved leads offset from the center of bonding pads: A semiconductor device including: a substrate on which a plurality of leads are formed; and a semiconductor chip mounted on the substrate in such a manner that a surface of the semiconductor chip having a plurality of electrodes faces the substrate. Each of the leads includes a first portion that... Agent: Oliff & Berridge, PLC

20080064141 - Manufacturing method of semiconductor device, adhesive sheet used therein, and semiconductor device obtained thereby: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic... Agent: Knobbe Martens Olson & Bear LLP

20080064142 - Method for fabricating a wafer level package having through wafer vias for external package connectivity: According to an exemplary embodiment, a method for fabricating a wafer level package includes forming a polymer layer on a device wafer, where the device wafer includes at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected... Agent: Michael Farjami, Esq. Farjami & Farjami LLP

20080064144 - Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound... Agent: Schwegman, Lundberg & Woessner, P.A.

20080064143 - Microelectronic devices and methods: A microelectronic device is made of a semiconductor substrate, a heat generating component in a layer thereof, and a body within the remaining semiconductor substrate. The body is made of materials which have a high thermal inertia and/or thermal conductivity. When high thermal conductivity materials are used, the body acts... Agent: F. Chau & Associates, LLC

20080064145 - Die attach paddle for mounting integrated circuit die: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper... Agent: Schneck & Schneck

20080064146 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, the method includes: moving a nozzle around a semiconductor chip bonded to a wiring substrate by face-down bonding; and continuously supplying underfill material through the nozzle, thereby filling the underfill material between the wiring substrate and the semiconductor chip, wherein an outline of... Agent: Harness, Dickey & Pierce, P.L.C

20080064147 - Method for fabricating a metal-insulator-metal (mim) capacitor having capacitor dielectric layer formed by atomic layer deposition (ald): In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at... Agent: Young & Thompson

20080064148 - Semiconductor device and manufacturing process thereof: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is... Agent: Buchanan, Ingersoll & Rooney PC

20080064149 - Strained-channel fin field effect transistor (fet) with a uniform channel thickness and separate gates: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first... Agent: Mcginn Intellectual Property Law Group, PLLC

20080064150 - Manufacturing method of thin film transistor array substrate: A thin film transistor array substrate and a manufacturing method thereof are provided. Wherein, scan lines and data lines are disposed on a substrate to define a plurality of pixel regions. Thin film transistors are disposed in the pixel regions correspondingly and driven by the scan lines and the data... Agent: Jianq Chyun Intellectual Property Office

20080064152 - Liquid crystal display device having drive circuit and fabricating method thereof: A fabricating method of an array substrate for a liquid crystal display device including forming a polycrystalline silicon film on a substrate having a display region and a peripheral region, the polycrystalline silicon film having grains of square shape, forming a first active layer in the display region and a... Agent: Birch Stewart Kolasch & Birch

20080064151 - Thin film transistor and method of manufacturing the same: A method of manufacturing a thin film transistor includes: forming an amorphous silicon layer and a blocking layer; forming a photoresist layer having first and second photoresist patterns spaced apart from each other on the blocking layer; etching the blocking layer using the first photoresist pattern as a mask to... Agent: H.c. Park & Associates, PLC

20080064153 - Fully salicided (fuca) mosfet structure: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop... Agent: Saile Ackerman LLC

20080064154 - Process flow for metal gate access device: Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an access device following formation of the periphery transistor gates. Access devices and systems... Agent: Trask Britt, P.C./ Micron Technology

20080064155 - Method for producing a multi-stage recess in a layer structure and a field effect transistor with a multi-recessed gate: The method for forming a multi-stage recess in a layer structure comprises forming a photo-resist film atop a layer structure; a first step (49, 70) of etching the layer structure through an opening of the photo-resist film used as a mask, for forming a first stage of the recess; a... Agent: Philips Intellectual Property & Standards

20080064156 - Semiconductor device and method of manufacturing the same: In an nMOSFET, a gate electrode is formed by a silicide layer comprised of NiSi. In a surface layer of a Ge substrate on both sides of the gate electrode, NiGe layers which are germanide layers comprised of NiGe are formed. On junction interfaces between the NiGe layers and the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080064157 - Low noise and high performance lsi device, layout and manufacturing method: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be... Agent: Mills & Onello LLP

20080064158 - Method for fabricating non-volatile memory: A method for fabrication a memory having a memory area and a peripheral area includes forming a first gate insulating layer with a first thickness over a substrate of a first region in the peripheral area and a second insulating layer with a second thickness over the substrate of the... Agent: J C Patents, Inc.

20080064159 - Semiconductor device: Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across... Agent: Mcdermott Will & Emery LLP

20080064160 - Cmos devices incorporating hybrid orientation technology (hot) with embedded connectors: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations).... Agent: Scully Scott Murphy & Presser, PC

20080064161 - Memory cell having bar-shaped storage node contact plugs and methods of fabricating same: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. A plurality of parallel bit line patterns are placed on the bit line interlayer insulating layer. Each of the bit line patterns has a bit line and a bit line canning layer... Agent: Marger Johnson & Mccollom, P.C.

20080064162 - Vertical soi transistor memory cell and method of forming the same: The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node... Agent: Scully, Scott, Murphy & Presser, P.C.

20080064163 - Method and structure for integrating mim capacitors within dual damascene processing techniques: A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer... Agent: Cantor Colburn LLP - IBM Fishkill

20080064164 - Method of manufacturing nonvolatile memory device: A method of manufacturing a nonvolatile memory device is disclosed. The method includes the steps of forming a tunnel oxide layer, a first conductive layer for a floating gate, and a hard mask layer over a semiconductor substrate, etching a portion of the hard mask layer, the first conductive layer,... Agent: Marshall, Gerstein & Borun LLP

20080064165 - Dual storage node memory devices and methods for fabricating the same: Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes... Agent: Ingrassia Fisher & Lorenz, P.C.

20080064167 - Semiconductor device with a bulb-type recess gate: When a recess of a bulb-type recess gate is formed, the recess formed in a device isolation region is formed to be separated from an edge of an active region. This structure thereby prevents damage of a semiconductor substrate of the edge of the active region and a defect during... Agent: Townsend And Townsend And Crew, LLP

20080064168 - Method for forming a shielded gate trench fet with the shield and gate electrodes being connected together: A method of forming a field effect transistor includes the following steps. A trench is formed in a semiconductor region, and a shield dielectric layer lining lower sidewalls and a bottom surface of the trench is formed. A shield electrode is formed in a lower portion of the trench, and... Agent: Townsend And Townsend And Crew, LLP

20080064166 - Semiconductor devices and methods of manufacture thereof: A method of manufacturing a semiconductor device comprising source and drain regions (13, 14, 14a) of a first conductivity type, and a channelaccommodating region (15) of a second, opposite conductivity type which separates the source and drain regions. The device comprises a gate (11, 42) which extends adjacent to the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080064169 - Method for manufacturing semiconductor device, and semiconductor device: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistors' characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the... Agent: Oliff & Berridge, PLC

20080064170 - Transistor for memory device and method for manufacturing the same: Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a groove formed in the active region.... Agent: Ladas & Parry LLP

20080064171 - Method of forming a thin layer and method of manufacturing a semiconductor device: In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An... Agent: Harness, Dickey & Pierce, P.L.C

20080064172 - Stressed semiconductor device structures having granular semiconductor material: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the... Agent: International Business Machines Corporation Dept. 18g

20080064173 - Semiconductor device, cmos device and fabricating methods of the same: A method for fabricating a semiconductor device is described. A transistor is formed on a substrate, including a gate structure on the substrate, a spacer on the sidewall of the gate structure and S/D regions in the substrate beside the gate structure. A liner layer is formed over the substrate... Agent: Jianq Chyun Intellectual Property Office

20080064174 - Method for manufacturing an integrated circuit with fully depleted and partially depleted transistors: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080064175 - Low stress sacrificial cap layer: A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300,... Agent: Texas Instruments Incorporated

20080064176 - Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and... Agent: North America Intellectual Property Corporation

20080064177 - Bipolar device having improved capacitance: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9... Agent: Hitt Gaines, PC Lsi Corporation

20080064178 - Deep trench capacitor through soi substrate and methods of forming: Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the... Agent: Hoffman, Warnick & D'alessandro LLC

20080064179 - Low leakage mim capacitor: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. Attn: Timothy B. Clise

20080064180 - Method for passivating inductively coupled surface currents in a semiconductor device: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch... Agent: Lsi Corporation

20080064181 - Semiconductor device and method of fabricating the same: A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The... Agent: Paul J. Winters

20080064182 - Process for high temperature layer transfer: The invention concerns a method for transferring a thin layer from a donor wafer onto a receiving wafer by implanting at least one atomic species into the donor wafer to form a weakened zone therein, with the weakened zone being including microcavities or platelets therein, and the thin layer being... Agent: Winston & Strawn LLP Patent Department

20080064183 - Method of forming a multi-layer semiconductor structure incorporating a processing handle member: A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of... Agent: Daly, Crowley, Mofford & Durkee, LLP

20080064184 - Method, apparatus for holding and treatment of a substrate: Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which... Agent: Schwegman, Lundberg & Woessner / Infineon

20080064185 - Semiconductor wafer front side protection: There is provided a method for making a wafer comprising the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second... Agent: Driggs, Hogg, Daugherty & Del Zoppo Co., L.p.a.

20080064186 - Manufacturing method of semiconductor element: A semiconductor wafer includes plural element regions and a dicing region provided to partition off these element regions. The element region and the dicing region have a laminated film containing a low dielectric constant insulating film. In dicing the semiconductor wafer, a laser beam whose peak energy Y (W) and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080064187 - Production method for stacked device: A production method for obtaining a stacked device from a wafer is provided. The wafer has: a device forming region formed on a surface having plural devices formed thereon, the devices having surfaces and thicknesses; a peripheral extra region surrounding the device forming region; and plural metal electrodes embedded in... Agent: Brinks Hofer Gilson & Lione

20080064188 - Wafer processing method and wafer processing apparatus: A wafer processing apparatus (10) has a grinder (80) for grinding the back surface (22) of a wafer (20) on whose front surface (21) a circuit pattern (C) has been formed, and a die attachment paste applicator (30) for applying die attachment paste on the entire back surface of the... Agent: Christie, Parker & Hale, LLP

20080064189 - Crack stop for low k dielectrics: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC... Agent: Scully, Scott, Murphy & Presser, P.C.

20080064190 - Manufacturing method of semiconductor device and semiconductor manufacturing device: A manufacturing method of a semiconductor device, comprises; a process of heat-treating a semiconductor substrate under the ordinary pressure and in an oxidizing atmosphere; and a process of heat-treating the semiconductor substrate under the ordinary pressure and in an inert atmosphere, wherein heat-treating time or heat-treating temperature in heat treatment... Agent: Harness, Dickey & Pierce, P.L.C

20080064191 - Modulation of stress in stress film through ion implantation and its application in stress memorization technique: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the... Agent: HorizonIPPte Ltd

20080064192 - Method for forming semiconductor device: Embodiments relate to a method for forming a semiconductor device in which a first oxide layer may be deposited over a surface of a semiconductor substrate including high-voltage (HV) and low-voltage (LV) wells, the first oxide layer having a predetermined thickness corresponding to a high-voltage (HV) area of the well.... Agent: Sherr & Nourse, PLLC

20080064193 - Method for manufacturing semiconductor device using krf light source: A semiconductor device manufacturing method using a KrF light source is disclosed. Embodiments relate to a method for manufacturing a semiconductor device including forming an oxide film over a semiconductor substrate. A gate conductor may be formed over the oxide film. An antireflective film may be formed over the gate... Agent: Sherr & Nourse, PLLC

20080064194 - Method for fabricating flash memory device: A method for fabricating a flash memory device includes providing a semi-finished substrate including a first polysilicon layer electrically isolated by an isolation structure. Recesses are formed in the isolation structure to partially expose sidewalls of the first polysilicon layer. A second polysilicon layer is formed over the exposed first... Agent: Townsend And Townsend And Crew, LLP

20080064195 - Method for manufacturing gate of non volatile memory device: A method for manufacturing the gate of the non-volatile memory device is characterized in in-situ etching a tungsten silicide film, polycrystalline silicon films, an ONO film, and a silicon oxide film with one step using one etchant having a lower etch selectivity on the silicon and oxide films in order... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080064196 - Semiconductor device and method of manufacturing same: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the... Agent: Leydig Voit & Mayer, Ltd

20080064197 - Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and soi mos devices by gate stress engineering with sige and/or si:c: Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20080064198 - Chalcogenide semiconductor memory device with insulating dielectric: A semiconductor chalcogenide containing memory device may be formed with a dielectric in close juxtaposition to a chalcogenide alloy. Because the dielectric includes material interface regions, the thermal conductivity of the dielectric is reduced. As one result, heat transfer may be reduced, reducing the programming current required to program the... Agent: Trop Pruner & Hu, PC

20080064199 - Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during... Agent: Myers Bigel Sibley & Sajovec

20080064200 - Method to manufacture a phase change memory: Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting... Agent: Timothy N. Trop Trop, Pruner & Hu, P.C.

20080064201 - Flip chip packaging method that protects the sensing area of an image sensor from contamination: A flip chip packaging method that protects a sensing area of an image sensor from contamination primarily comprises: a transmitting substrate having a surface with a predetermined area forming a metal layer thereon which includes a circuit and at least one enclosure encircling said predetermined area; providing an image sensor... Agent: Chen Wen Ching

20080064202 - Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases: