Semiconductor device manufacturing: process inventions 02/08

20080050845 - Microelectromechanical systems encapsulation process: An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450 C is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation.... Agent: Courtney Staniford & Gregory LLP

20080050848 - Charged particle beam irradiation method and semiconductor device manufacturing method: A charged particle beam irradiation method includes setting an observation region on a sample, the sample including an object pattern to be observed, and the observation region including the object pattern, setting an irradiation region on the sample, the irradiation region being to be irradiated with a charged particle beam,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080050850 - Method for manufacturing semiconductor laser element: A method for manufacturing a semiconductor laser element includes forming a semiconductor laminated structure, having an active layer, on a substrate; etching the semiconductor laminated structure to form a mesa; cleaning the side of the mesa at a temperature lower thank a critical temperature at which an oxide layer forms... Agent: Leydig Voit & Mayer, Ltd

20080050851 - Method for manufacturing display device: A light-absorbing layer is selectively formed over an insulating surface, an insulating layer is formed over the insulating surface and the light-absorbing layer, the insulating surface, the light-absorbing layer, and the insulating layer are irradiated with laser light to selectively remove only the insulating layer above the light-absorbing layer in... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080050852 - Manufacturing of flexible display device panel: A manufacturing method of a display panel for an LCD includes forming a gate line on a flexible insulation substrate, depositing a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer and forming a data line and a drain electrode on the semiconductor... Agent: Macpherson Kwok Chen & Heid LLP

20080050856 - Method for manufacturing silicon device: A method for manufacturing a silicon device includes steps of: forming a silicon layer 4a that indicates a second conductivity type on a first surface S1a of a silicon substrate 2a that indicates a first conductivity type; and exposing, after the step, a third surface S3a of the silicon layer... Agent: Drinker Biddle & Reath (dc)

20080050844 - Surface reconstruction method for silicon carbide substrate: A surface reconstruction method for a silicon carbide substrate (1) includes a silicon film forming step of forming a silicon film (2) on a surface of the silicon carbide substrate (1) and a heat treatment step of heat-treating the silicon carbide substrate (1) and the silicon film (2) without providing... Agent: Fish & Richardson P.C.

20080050846 - Liquid crystal display panel device having compensation cell gap, method of fabricating the same and method of using the same: A liquid crystal display panel device includes a liquid crystal display panel, a sealing material disposed along a first outer perimeter of the liquid crystal display panel, a barrier wall disposed along a second outer perimeter of the liquid crystal display panel, and a liquid crystal material disposed within the... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20080050847 - Single ic-chip design on wafer with an embedded sensor utilizing rf capabilities to enable real-time data transmission: An apparatus and method for real-time monitoring process conditions of a semiconductor wafer processing operation. A semiconductor wafer subject to processing in a wafer processing tool is embedded with one or more sensor devices. In response to receipt of wireless electromagnetic signals, the embedded sensor devices are activated for generating... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050849 - Method to eliminate arsenic contamination in trench capacitors: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050853 - Method of fabricating display substrate: In a method of fabricating a display substrate, a photoresist layer pattern is formed on a substrate where a thin film transistor (TFT) is formed, and a transparent conductive layer is formed on the photoresist layer pattern. Then, the transparent conductive layer is patterned by a lift-off method to form... Agent: H.c. Park & Associates, PLC

20080050854 - Semiconductor light emitting element and method for manufacturing the same: A high-luminance light emitting element is manufactured by a method comprising: forming a light emitting layer on a first surface of a GaP substrate including the first surface and a second surface opposed to the first surface and having an area smaller than the first area, the light emitting layer... Agent: Hogan & Hartson L.L.P.

20080050855 - Nitride semiconductor laser device and a method for improving its performance: The present invention relates to a nitride semiconductor laser device provided with a window layer on a light-emitting end face of the resonator which comprises an active layer of nitride semiconductor between the n-type nitride semiconductor layers and the p-type nitride semiconductor layers, in which at least the radiation-emitting end... Agent: Smith Patent Office

20080050857 - Group iii nitride coatings and methods: The invention provides a composition that is a dispersion made from a Group III nitride, a solvent system, and a dispersant. The dispersion can be used to prepare Group III nitride thin films on a wide range of substrates, for example, glass, silicon, silicon dioxide, silicon nitride, silicon carbide, aluminum... Agent: Schwegman, Lundberg & Woessner, P.A.

20080050858 - Method for producing semiconductor device: A method for producing a semiconductor device includes the steps of forming a predetermined device in a device layer grown on a semiconductor substrate with a sacrificial layer provided therebetween; and removing the sacrificial layer by etching to separate the semiconductor substrate from the device layer while a supporting substrate... Agent: Robert J. Depke Lewis T. Steadman

20080050859 - Methods for a multiple die integrated circuit package: Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one... Agent: Vierra Magen/sandisk Corporation

20080050862 - Method of manufacturing a single chip semiconductor integrated circuit device including a mask rom in a short time: In a state of a first semiconductor integrated circuit device on which a first semiconductor integrated circuit board including a first mask ROM and a programmable ROM are mounted, an ultimate program determined by using the programmable ROM is stored in a second ROM of a second semiconductor integrated circuit... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080050860 - Adhesion by plasma conditioning of semiconductor chip: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits,... Agent: Texas Instruments Incorporated

20080050861 - Microelectromechanical systems encapsulation process with anti-stiction coating: An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450° C. is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation.... Agent: Courtney Staniford & Gregory LLP

20080050863 - Semiconductor structure including multiple stressed layers: A semiconductor structure and methods for fabricating the semiconductor structure include a gate electrode located over a channel region within a semiconductor substrate and a spacer layer adjacent the gate electrode. The spacer layer extends vertically above the gate electrode. The semiconductor structure also includes a first stressed layer having... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050864 - Method of manufacturing semiconductor device having impurity region under isolation region: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming... Agent: Mcdermott Will & Emery LLP

20080050865 - Non-planar transistor having germanium channel region and method of manufacturing the same: Provided is a non-planar transistor with a multi-gate structure that includes a germanium channel region, and a method of manufacturing the same. The non-planar transistor includes a silicon body and a channel region that covers exposed surfaces of the silicon body. The channel region is formed of a germanium layer... Agent: Mills & Onello LLP

20080050866 - Semiconductor structures integrating damascene-body finfet's and planar devices on a common substrate and methods for forming such semiconductor structures: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080050867 - Array substrate of liquid crystal display device and manufacturing method thereof: There is provided an array substrate of an LCD device including a plurality of gate lines aligned on the substrate, a plurality of data lines crossing the gate lines to form a plurality of pixel regions, a thin film transistor located at the intersection of the gate lines and the... Agent: Mckenna Long & Aldridge LLP

20080050868 - Method to enhance device performance with selective stress relief: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second... Agent: HorizonIPPte Ltd

20080050869 - Dual stress liner device and method: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper.... Agent: Banner & Witcoff, Ltd.

20080050870 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes the steps of: a) forming an insulating film on a semiconductor substrate; b) forming a first conductive film of a material which does not contain nitrogen on the insulating film; and c) forming a second conductive film of a material containing nitrogen... Agent: Mcdermott Will & Emery LLP

20080050872 - Fabrication of a high speed rram having narrow pulse width programming capabilities: A method of selecting a cathode material and a resistance material for use in a RRAM includes determining the work function of a group of potential resistance materials; determining the work function of a group of potential cathode materials; and selecting a suitable material for the resistance material from the... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080050871 - Methods for removing material from one layer of a semiconductor device structure while protecting another material layer and corresponding semiconductor device structures: Methods for removing material from one layer of a semiconductor device structure, such as an etch stop layer beneath a capacitor container, without substantially removing material from an overlying layer that includes the same material, such as a protective or reinforcing lattice over the capacitor container, include employing process parameters... Agent: Trask Britt, P.C./ Micron Technology

20080050873 - Semiconductor structures with body contacts and fabrication methods thereof: A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080050874 - Metal-insulator-metal capacitor and method of manufacturing the same: A metal-insulator-metal capacitor includes a first electrode in a first wiring level, a second electrode above the first wiring level and extending into a first portion of the first electrode that surrounds the second electrode, and a dielectric film separating the first electrode from the second electrode.... Agent: Volentine & Whitt PLLC

20080050875 - Methods of fabricating embedded flash memory devices: A method of fabricating a compound device includes forming a first gate insulating pattern on a semiconductor substrate including a first region and a second region, forming a second gate insulating layer on the first gate insulating pattern, and after forming the second gate insulating layer, forming a well in... Agent: Lee & Morse, P.C.

20080050876 - Method for fabricating silicon carbide vertical mosfet devices: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a... Agent: General Electric Company Global Research

20080050877 - Superjunction trench device and method: Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second (74-1, 74-2, 74-3, etc.) spaced-apart regions of first (70) and... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080050878 - Method for preparing a memory structure: A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporating the first etching mask... Agent: Oliff & Berridge, PLC

20080050879 - Methods of forming metal-containing gate structures: A method of forming a metal-containing gate includes forming a high-k dielectric layer over a substrate. A process using an oxygen-containing solution is provided to process the high-k dielectric layer. A metal-containing layer is formed over the high-k dielectric layer. The high-k dielectric layer and metal-containing layer are patterned, thereby... Agent: Duane Morris LLPIPDepartment (tsmc)

20080050880 - Structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050881 - Heterojunction tunneling field effect transistors, and methods for fabricating the same: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050882 - System and method for mitigating oxide growth in a gate dielectric: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer... Agent: Texas Instruments Incorporated

20080050883 - Hetrojunction bipolar transistor (hbt) with periodic multilayer base: A method and resulting electronic device utilizing a periodic multi-layer (ML) and/or superlattice (SL) structures in the base of a SiGe heterojunction bipolar transistor (HBT) is disclosed. The SL is a special case of an ML, in which layers that are chemically different from adjacent neighbors are successively repeated. The... Agent: Schneck & Schneck

20080050884 - Process for manufacturing semiconductor device: A dielectric body is formed by an ALD film deposition process comprising a gas flow sequence where a purging step after supplying a source and a reactant gases is a two-stage purging of vacuum purging and gas purging and the step of supplying a reactant gas is further divided. The... Agent: Sughrue Mion, PLLC

20080050886 - Method of producing semiconductor device: d

20080050885 - System and method for fabricating a fin field effect transistor: There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching... Agent: Fletcher Yoder (micron Technology, Inc.)

20080050887 - Method for fabricating sige-on-insulator (sgoi) and ge-on-insulator (goi) substrates: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050888 - Laser separation of thin laminated glass substrates for flexible display applications: A method of separating a sheet of coated brittle material comprises the steps of providing a sheet of layered brittle material comprising a brittle layer and a coating material adhered to a surface of the brittle layer and applying a laser along a separation line in the sheet, thereby cutting... Agent: Corning Incorporated

20080050889 - Hotwall reactor and method for reducing particle formation in gan mocvd: Systems and methods to suppress the formation of parasitic particles during the deposition of a III-V nitride film with, e.g., metal-organic chemical vapor deposition (MOCVD) are described. In accordance with certain aspects of the invention, a hotwall reactor design and methods associated therewith, with wall temperatures similar to process temperatures,... Agent: Townsend And Townsend And Crew LLP / Amat

20080050890 - Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates: A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080050891 - Coplanar silicon-on-insulator (soi) regions of different crystal orientations and methods of making the same: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI... Agent: Ibm Corporation, Intellectual Property Law

20080050892 - Method of manufacturing a thin film structure, method of manufacturing a storage node using the same, method of manufacturing a phase change random access memory using the same and a thin film structure, a storage node and a phase change random access mem: Provided are a method of manufacturing a thin film structure, a method of manufacturing a storage node having the same, a method of manufacturing a phase-change random access memory device having the same and a thin film structure, storage node and phase-change random access memory device formed using the same.... Agent: Harness, Dickey & Pierce, P.L.C

20080050893 - Manufacturing method of display device: A method of manufacturing a display device to improve the quality of a polycrystal silicon upon dehydrogenating and polycrystallizing an amorphous silicon at the outside of a display region of a substrate, by forming a plurality of pixels having TFT devices using an amorphous silicon in the display region of... Agent: Reed Smith LLP

20080050894 - Preparation method of a coating of gallium nitride: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080050895 - Method for manufacturing semiconductor device: In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes using a photoresist and simplifying the process is provided, and the throughput is improved. An etching mask for forming a pattern of a layer to be processed such as a conductive layer... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080050896 - Fabricating method of silicon layer with high resistance: A silicon layer with high resistance is provided. The silicon layer with high resistance is positioned on a substrate. Also, the silicon layer with high resistance includes a plurality of silicon material layers, and an interface layer between every two of the silicon material layers, wherein, the silicon material layers... Agent: Jianq Chyun Intellectual Property Office

20080050897 - Method for doping a fin-based semiconductor device: A method for doping a multi-gate device is disclosed. In one aspect, the method comprises patterning a fin in a substrate, depositing a gate stack, and doping the fin. The process of doping the fin is done by depositing a blocking mask material at least on the top surface of... Agent: Knobbe Martens Olson & Bear LLP

20080050898 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, disposing a gate dielectric material over the workpiece, and disposing a gate material over the gate dielectric material. Cl or F is introduced to the gate... Agent: Slater & Matsil, L.L.P.

20080050899 - Method for manufacturing a semiconductor device having a polymetal gate electrode structure: A process for manufacturing a semiconductor device having a polymetal structure includes patterning a bottom electrode layer by using a sacrificial layer pattern oxidizing the side surface of the patterned bottom electrode layer, forming a sidewall oxide film on both the patterned bottom electrode layer and the sacrificial layer pattern,... Agent: Young & Thompson

20080050900 - Methods for pitch reduction formation: Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elements and peripheral circuitry and results in a reduction in pitch.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080050902 - Method for forming an independent bottom gate connection for buried interconnection including bottom gate of a planar double gate mosfet: A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first (251), second and third (252) openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate;... Agent: Fortkort & Houston P.C.

20080050901 - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements... Agent: Perkins Coie LLP Patent-sea

20080050903 - Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof: Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width... Agent: Ibm Corporation Department 417

20080050904 - Methods for attaching microfeature dies to external devices: Methods for attaching microfeature dies to external devices are disclosed. The external devices can include other microfeature dies, support members or other suitable devices. A particular method includes attaching the solder to the at least one of the microfeature die in the support member by changing a phase of the... Agent: Perkins Coie LLP Patent-sea

20080050906 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin Room 301/302, No. 47

20080050905 - Method of manufacturing semiconductor device: A semiconductor device is fabricated by making first and second UBM films on an external terminal, the first under bump metal film having no wettability to a bump electrode and the second UBM film having wettability to the bump electrode; placing the bump electrode on the second UBM film; patterning... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080050907 - Semiconductor component with plastic housing, and process for producing the same: A semiconductor component includes a plastic housing including: plastic outer surfaces; lower outer contact surfaces arranged on an underside of the housing; upper outer contact surfaces arranged on a top side of the housing that is opposite the underside; and outer interconnects electrically connecting the lower outer contact surfaces to... Agent: Edell , Shapiro & Finnan , LLC

20080050908 - Semiconductor device and method of manufacture thereof: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080050909 - Top layers of metal for high performance ic's: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin Room 301/302

20080050910 - Method for producing smooth, dense optical films: The invention is directed to preparing optical elements having a thin, smooth, dense coating or film thereon, and a method for making such coating or film. The coated element has a surface roughness of <1.0 nm rms. The coating materials include hafnium oxide or a mixture of hafnium oxide and... Agent: Corning Incorporated

20080050911 - Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods: Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining... Agent: Perkins Coie LLP Patent-sea

20080050912 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080050913 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20080050914 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device according to the present invention includes: a step for forming a wiring layer on a semiconductor substrate; a step for patterning the wiring layer; and a step for covering the wiring layer with a protective insulating film. Moreover, after the step for forming... Agent: Rabin & Berdo, PC

20080050915 - Method for manufacturing semiconductor device: In the method for manufacturing a semiconductor device relating to the present invention, first, a metal film is formed onto a substrate in the state where a silicide forming region is exposed onto the surface of substrate. Next, thermal processes at pressure higher than atmosphere are conducted to the substrate... Agent: Mcdermott Will & Emery LLP

20080050916 - Methods and apparatus for depositing tantalum metal films to surfaces and substrates: Methods and an apparatus are disclosed for depositing tantalum metal films in next-generation solvent fluids on substrates and/or deposition surfaces useful, e.g., as metal seed layers. Deposition involves low valence oxidation state metal precursors soluble in liquid and/or compressible solvent fluids at liquid, near-critical, or supercritical conditions for the mixed... Agent: Battelle Memorial Institute Attn:IPServices, K1-53

20080050917 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device improves the cleaning efficiency by increasing a cleaning time and temperature, including a copper Chemical Mechanical Planarization process for a semiconductor wafer with a copper line. The method includes a main Cu CMP process to chemically and mechanically polish a surface of the... Agent: Sherr & Nourse, PLLC

20080050918 - Method for producing a device comprising a structure equipped with one or more microwires or nanowires based on a si and ge compound by germanium condensation: b) lateral thermal oxidation of the sides of the second Si1-yGey-based semiconductor zone so as to reduce the second zone in at least one direction parallel to the main plane of the support and to form one or more Si1-zGez-based semiconductor wire(s) (with 0<y<1 and y<z).... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080050919 - High aspect ratio via etch: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three... Agent: Knobbe Martens Olson & Bear LLP

20080050920 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first insulating film on a semiconductor substrate; forming a mask with an opening of a predetermined pattern in the first insulating film; performing anisotropic etching on the semiconductor substrate with the mask... Agent: Sughrue Mion, PLLC

20080050921 - Method for manufacturing semiconductor device: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property.... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080050922 - Chamber recovery after opening barrier over copper: A chamber dry cleaning process particularly useful after a dielectric plasma etch process which exposes an underlying copper metallization. After the dielectric etch process, the production wafer is removed from the chamber and a cleaning gas is excited into a plasma to clean the chamber walls and recover the dielectric... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20080050923 - Low-k damage avoidance during bevel etch processing: A method for etching a bevel edge of a substrate is provided. A patterned photoresist mask is formed over the etch layer. The bevel edge is cleaned comprising providing a cleaning gas comprising at least one of a CO2, CO, CxHy, H2, NH3, CxHyFz and a combination thereof, forming a... Agent: Beyer Weaver LLP

20080050924 - Substrate carrying apparatus and substrate carrying method: The substrate processing apparatus, adapted to provide a process, such as etching, to a wafer, comprises the processing vessel, the ambient atmospheric carrying chamber, and the functional module, such as an orienter 4. With the process to be provided, matters having potential to generate corrosive gases or the like due... Agent: Smith, Gambrell & Russell

20080050925 - Photoresist processing methods: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form... Agent: Wells St. John P.s.

20080050926 - Dry etching method: In dry etching an insulating film containing silicon and carbon and formed on a wafer, plasma is generated from a mixed gas of a first molecule gas containing carbon and fluorine and a second molecule gas containing nitrogen. At this time, an RF bias of 2 MHz or lower is... Agent: Mcdermott Will & Emery LLP

20080050927 - Variable temperature and dose atomic layer deposition: A variable temperature and/or reactant dose atomic layer deposition (VTD-ALD) process modulates ALD reactor conditions (e.g., temperature, flow rates, etc.) during growth of a film (e.g., metallic) on a wafer to produce different film properties a different film depths.... Agent: Intel/blakely

20080050930 - Method of forming insulating film and method of manufacturing semiconductor device: A method of forming an insulating film according to one embodiment of the present invention, which is a method of forming an insulating film for use in a semiconductor device, performs thermal oxidation of a tantalum nitride film at a temperature range of 200 to 400 degrees centigrade by a... Agent: Young & Thompson

20080050928 - Semiconductor constructions, and methods of forming dielectric materials: Some embodiments include methods of forming dielectric materials associated with semiconductor constructions. A semiconductor substrate surface having two different compositions may be exposed to a first silanol, then to organoaluminum to form a monolayer, and finally to a second silanol to form a dielectric material containing aluminum from the organoaluminum... Agent: Wells St. John P.s.

20080050929 - Method of and apparatus for low-temperature epitaxy on a plurality of semiconductor substrates: wherein the semiconductor substrates are moved or stored during the cleaning step and during transport from the first reactor into the second reactor in an interruption-free manner in a reducing gas atmosphere as long as the substrate temperature is above a critical temperature Tc which is dependent on the substrate... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080050931 - Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080050932 - Overall defect reduction for pecvd films: The present invention generally provides an apparatus and method for reducing defects on films deposited on semiconductor substrates. One embodiment of the present invention provides a method for depositing a film on a substrate. The method comprises treating the substrate with a first plasma configured to reduce pre-existing defects on... Agent: Patterson & Sheridan, LLP

20080050933 - Insulator film, manufacturing method of multilayer wiring device and multilayer wiring device: In a method for manufacturing a semiconductor device, including forming an insulator film including a material having Si—CH3 bond and Si—OH bond, and irradiating the insulator film with ultraviolet rays, the rate of decrease of C concentration by X-ray photoelectron spectroscopy is not more than 30%, and the rate of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080044931 - Packaging substrate and method of manufacturing the same: A packaging substrate and a method of manufacturing the same are provided. The method includes following steps. First, a first substrate including at least one defected packaging unit and several first packaging units is provided. The defected packaging unit and the first packaging units are arranged in an array on... Agent: Birch Stewart Kolasch & Birch

20080044933 - Method for forming matching table of inner pads and outer pads and method for matching inner pads with outer pads using the same: A method for forming a matching table of inner pads and outer pads includes the steps of: obtaining a pitch Pi and a space Si between two neighboring inner pads; computing Wim=m×Pi−Si; obtaining a pitch Po and a space So between two neighboring outer pads; computing Won=n×Po−So; computing Rn=Won+(So×C); comparing... Agent: Bacon & Thomas, PLLC

20080044934 - Methods of forming semiconductor light emitting device packages by liquid injection molding and molded semiconductor light emitting device strips: Semiconductor light emitting device packaging methods include fabricating a substrate configured to mount a semiconductor light emitting device thereon. The substrate may include a cavity configured to mount the semiconductor light emitting device therein. The semiconductor light emitting device is mounted on the substrate and electrically connected to a contact... Agent: Myers Bigel Sibley & Sajovec

20080044937 - Method of forming surface irregularities and method of manufacturing gallium nitride-based light emitting diode: A method of forming surface irregularities comprises preparing a GaN substrate; forming a mask on a surface of the GaN substrate, the mask defining a surface-irregularity formation region; and wet-etching portions of the surface of the GaN substrate by using the mask as an etching mask. The wet-etching of the... Agent: Mcdermott Will & Emery LLP

20080044938 - Technique for low-temperature ion implantation: A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter. The apparatus may also comprise a cooling... Agent: Varian Semiconductor Equipment Assc., Inc.

20080044941 - Fabricating cmos image sensor: A fabrication method of a CMOS image sensor provides forms micro lenses over a substrate by etching a plurality of holes in a wiring layer over a pixel area. An oxide layer is deposited to form a surface with a semi-circular cross section over the holes. The oxide layer may... Agent: Sherr & Nourse, PLLC

20080044942 - Method of fabricating cmos image sensor: A method of manufacturing a complimentary metal oxide semiconductor (CMOS) image sensor. The method includes a step of performing a silicide process relative to a plug for transferring electrons generated from a photodiode. The silicide of the plug blocks light irradiated through the plug, so that the performance of the... Agent: Sherr & Nourse, PLLC

20080044930 - Transplanted magnetic random access memory (mram) devices on thermally-sensitive substrates using laser transfer and method of making the same: A method of forming a magnetic memory device (and a resulting structure) on a low-temperature substrate, includes forming the memory device on a transparent substrate coated with a decomposable material layer subject to rapid heating resulting in a predetermined high pressure, and transferring the memory device to the low-temperature substrate.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080044932 - Carbon precursors for use during silicon epitaxial film formation: The present invention provides systems and methods of forming an epitaxial film on a substrate. After heating in a process chamber, the substrate is exposed to a silicon source and at least one of SiH2(CH3)2, SiH(CH3)3, Si(CH3)4, 1,3-disilabutane, and C2H2, at a temperature of greater than about 250 degrees Celsius... Agent: Dugan & Dugan, PC

20080044935 - Method for manufacturing contact structure of pixel electrode of liquid crystal display device: A method for manufacturing a pixel electrode contact structure of a thin-film transistors liquid crystal display is disclosed. First, a transparent substrate having a first insulating layer thereon is provided. Afterward, a first metal layer and a second metal layer are sequentially formed on the substrate and then be patterned... Agent: Bacon & Thomas, PLLC

20080044936 - Semiconductor laser module, optical amplifier, and method of manufacturing the semiconductor laser module: A semiconductor laser module has a semiconductor laser device; a package for housing the semiconductor laser device; a PBC fixed in the package for polarization-synthesizing two laser beams output from the semiconductor laser device; a depolarizing element fixed in the package for depolarizing a synthesizing light output from the PBC;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080044939 - Low power silicon thermal sensors and microfluidic devices based on the use of porous sealed air cavity technology or microchannel technology: This invention provides a miniaturized silicon thermal flow sensor with improved characteristics, based on the use of two series of integrated thermocouples (6, 7) on each side of a heater (4), all integrated on a porous silicon membrane (2) on top of a cavity (3). Porous silicon (2) with the... Agent: Marshall, Gerstein & Borun LLP

20080044940 - Laminating system: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it... Agent: Nixon Peabody

20080044943 - Manufacture of silicon-based devices having disordered sulfur-doped surface layers: The present invention provides methods of fabricating a radiation-absorbing semiconductor wafer by irradiating at least one surface location of a silicon substrate, e.g., an n-doped crystalline silicon, by a plurality of temporally short laser pulses, e.g., femtosecond pulses, while exposing that location to a substance, e.g., SF6, having an electron-donating... Agent: Nutter Mcclennen & Fish LLP

20080044944 - Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080044945 - Filling paste structure and process for wl-csp: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate.... Agent: Kusner & Jaffe Highland Place Suite 310

20080044946 - Semiconductor die package using leadframe and clip and method of manufacturing: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used... Agent: Townsend And Townsend And Crew, LLP

20080044947 - A method to provide substrate-ground coupling for semiconductor integrated circuit dice constructed from soi and related materials in stacked-die packages: An apparatus and a method for packaging semiconductor devices. Disclosed are multi-die packaging apparatuses and techniques, especially useful for integrated circuit dice involving insulative substrates, such as silicon-on-insulator (SOI), where grounding of a base layer is not reasonably practical. Disclosed is a means for effectively grounding all layers of an... Agent: Schneck & Schneck

20080044948 - Manufacturing method for resin sealed semiconductor device: The present invention relates to a leadless, resin sealed semiconductor device structure and manufacturing method. In the semiconductor device according to the present invention, one side of a thin plate made of copper or the like is subjected to half etching, and a plurality of die pad portions (3) and... Agent: Bruce L. Adams, Esq.

20080044949 - High performance reworkable heatsink and packaging structure with solder release layer and method of making: A method of making and a high performance reworkable heatsink and packaging structure with solder release layer are provided. A heatsink structure includes a heatsink base frame. A selected one of a heatpipe or a vapor chamber, and a plurality of parallel fins are soldered to the heatsink base frame.... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080044950 - Multi-layer fin wiring interposer fabrication process: An interposer having multi-layer fine wiring structure which comprises an insulating layer made of photosensitive polyimide which is photosensitive organic material and a wiring layer portion made of metal, such as copper, silver, gold, aluminum, palladium, indium, titanium, tantalum, and niobium, functions as wiring in an integrated circuit chip, wherein... Agent: Rader Fishman & Grauer PLLC

20080044951 - Semiconductor package and method of manufacturing the same: A semiconductor package may include a substrate having external contact terminals. A semiconductor chip having bonding pads may be formed on the substrate. Conductive bumps may connect the external contact terminals of the substrate to the bonding pads of the semiconductor chip. An underfill may be interposed between the substrate... Agent: Harness, Dickey & Pierce, P.L.C

20080044952 - Selective removal of gold from a lead frame: A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions... Agent: Texas Instruments Incorporated

20080044953 - Method for forming an array substrate: Disclosed is a method for manufacturing an array substrate utilizing a laser ablation process. With the laser ablation process, a photoresist layer is removed along with the transparent conductive layer therefrom, while maintaining other portions of the transparent conductive layer. Moreover, the laser ablation process of the invention does not... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080044954 - Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby: A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact.... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080044955 - Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply: An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise... Agent: Mh2 Technology Law Group, LLP

20080044956 - Apparatus for etching substrate and method of fabricating thin-glass substrate: An apparatus for etching a substrate includes (a) a nozzle system including at least one nozzle through which acid solution containing at least hydrofluoric acid is sprayed onto the substrate, (b) a mover which moves at least one of the nozzle system and the substrate relative to the other in... Agent: Scully Scott Murphy & Presser, PC

20080044958 - Method of fabricating complementary metal-oxide semiconductor (cmos) thin film transistor (tft): A method of fabricating a Complementary Metal-Oxide Semiconductor (CMOS) Thin Film Transistor (TFT) using a reduced number of masks includes: forming a buffer layer on the entire surface of a substrate; forming polysilicon and photoresist layers on the entire surface of the substrate having the buffer layer; exposing and developing... Agent: Robert E. Bushnell

20080044957 - Work function control of metals: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the... Agent: Texas Instruments Incorporated

20080044959 - Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures: A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080044960 - Semiconductor on insulator vertical transistor fabrication and doping process: A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into... Agent: Law Office Of Robert M. Wallace

20080044961 - Thin film transistor array panel: The present invention provides a thin film transistor array panel comprising: an insulating substrate; a first signal line formed on the insulating substrate and extending in a first direction; a second signal line formed on the insulating substrate, extending in a second direction, and intersecting the first signal line; a... Agent: Cantor Colburn, LLP

20080044962 - Electro-optical device and thin film transistor and method for forming the same: A semiconductor device having a pair of impurity doped second semiconductor layers, formed on a first semiconductor layer having a channel formation region therein, an outer edge of the first semiconductor film being at least partly coextensive with an outer edge of the impurity doped second semiconductor layers. The semiconductor... Agent: Eric Robinson

20080044963 - Tft substrate for liquid crystal display apparatus and method of manufacturing the same: There are provided a TFT substrate for an LCD apparatus and a method of manufacturing the same. A substrate (10), a diffusion barrier layer (11) and a copper alloy layer (12) are formed on the TET substrate, consecutively. The copper alloy includes a material from about 0.5 at % to... Agent: Cantor Colburn, LLP

20080044964 - Printed dopant layers: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080044965 - Method of manufacturing thin film transistor array panel: A method of manufacturing a thin film transistor array panel includes forming an amorphous silicon film on an insulating substrate; forming a sacrificial film having an embossed surface on the amorphous silicon film; contacting a metal plate with the sacrificial film and performing heat-treatment for crystallizing the amorphous silicon film... Agent: Cantor Colburn, LLP

20080044966 - Enhancement of electron and hole mobilities in <110> si under biaxial compressive strain: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress... Agent: Scully, Scott, Murphy & Presser, P.C.

20080044967 - Integrated circuit system having strained transistor: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer on the wafer, protecting a portion of the stress formation layer, and irradiating the wafer for modification of a stress value of an unprotected portion of the stress formation layer.... Agent: Law Offices Of Mikio Ishimaru

20080044968 - Method for improving transistor performance through reducing the salicide interface resistance: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon... Agent: Intel/blakely

20080044969 - Turn-on-efficient bipolar structures with deep n-well for on-chip esd protection: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the... Agent: Berkeley Law & Technology Group, LLP

20080044970 - Memory structure and method for preparing the same: A memory structure comprises a semiconductor substrate, an active are positioned in the semiconductor substrate, a plurality of doped regions positioned in the semiconductor substrate, a first conductive plug connecting a bit line and one of the doped regions and a second conductive plug connecting a capacitor and another one... Agent: Oliff & Berridge, PLC

20080044971 - Method for fabricating a semiconductor device having a capacitor: A method for fabricating a semiconductor device is disclosed. The method includes forming an etch stop layer on a substrate, forming a mold layer on the substrate, and forming an opening exposing the substrate by patterning the mold layer and the etch stop layer, wherein the opening includes a lower... Agent: Volentine & Whitt PLLC

20080044972 - Methods of forming nonvolatile memories with shaped floating gates: In a nonvolatile memory using floating gates to store charge, individual floating gates are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may also alternate in the word line direction. L-shaped floating gates are formed by etching conductive portions using etch masks of different... Agent: Winston & Strawn, LLP

20080044973 - Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose cmos technology: A method and corresponding structure for shielding a floating gate tunneling element. The method comprises disposing a floating gate over a gate oxide using standard CMOS processing in two active areas defined by first and second doped well regions formed in a substrate surrounded by field oxide, and forming a... Agent: Nixon Peabody, LLP

20080044974 - Embedded stressed nitride liners for cmos performance improvement: The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying... Agent: Scully, Scott, Murphy & Presser, P.C.

20080044975 - Thin-film transistor, method for manufacturing thin-film transistor, and display using thin-film transistors: The present invention provides a thin-film transistor offering a higher electron (or hole) mobility, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. The present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080044976 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin Science-based Industrial Park

20080044977 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080044978 - Isolation structures for integrated circuits and modular methods of forming the same: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20080044979 - Integrated circuitry, electromagnetic radiation interaction components, transistor devices and semiconductor construction; and methods of forming integrated circuitry, electromagnetic radiation interaction components, transistor devices and semiconductor: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The... Agent: Wells St. John P.s.

20080044980 - Method of forming a semiconductor device: A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric... Agent: Slater & Matsil LLP

20080044981 - Trench isolation methods, methods of forming gate structures using the trench isolation methods and methods of fabricating non-volatile memory devices using the trench isolation methods: Methods of fabricating semiconductor devices including forming a mask pattern on a semiconductor substrate are provided. The mask pattern defines a first opening that at least partially exposes the semiconductor substrate and includes a pad oxide layer and a nitride layer pattern on the pad oxide layer pattern. The nitride... Agent: Myers Bigel Sibley & Sajovec

20080044982 - Thin film transistor array panel for a display device and a method of manufacturing the same: A method of manufacturing a thin film transistor array panel includes forming gate lines including gate electrodes on an insulation substrate; forming a gate insulating layer, semiconductor layer, and etch stop layer on the gate lines; etching and patterning the etch stop and semiconductor layers at the same time using... Agent: F. Chau & Associates, LLC

20080044983 - Element formation substrate, method of manufacturing the same, and semiconductor device: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080044984 - Methods of avoiding wafer breakage during manufacture of backside illuminated image sensors: A process for forming backside illuminated devices is disclosed. Specifically, the process reduces processing damage to wafers caused by poor bond quality at the wafer edge ring. In one embodiment, a wafer edge trimming step is implemented prior to bonding the wafer to the substrate. A pre-grind blade is used... Agent: Duane Morris LLPIPDepartment (tsmc)

20080044985 - Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods: Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods are disclosed herein. One embodiment, for example, is directed to a method for processing a microfeature workpiece releasably attached to a first support member. The workpiece includes a microelectronic substrate, a plurality of... Agent: Perkins Coie LLP Patent-sea

20080044986 - Method for improved dielectric performance: A method of decreasing the density of dielectric interface traps in an integrated circuit device. In accordance with the teachings of the present invention, the method includes providing a semiconductor substrate, processing the semiconductor substrate to form an integrated circuit device, such as a field effect transistor including forming a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080044987 - Enhancement of electron and hole mobilities in <110> si under biaxial compressive strain: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress... Agent: Scully, Scott, Murphy & Presser, P.C.

20080044988 - Method for producing an integrated circuit having semiconductor zones with a steep doping profile: An integrated circuit and method, producing semiconductor zones with a steep doping profile is disclosed. In one embodiment, dopants are implanted in a region corresponding to the semiconductor zone to be formed and which has at least one topology process. During the subsequent laser irradiation for activating the dopants in... Agent: Dicke, Billig & Czaja

20080044989 - Photomask and its method of manufacture: An embodiment of a photomask for forming gate lines and a method of manufacturing semiconductor devices using the photomask is disclosed. The photomask includes a photomask substrate, gate line mask patterns that define gate lines that cross at least one active region on a semiconductor substrate, and that are arranged... Agent: Marger Johnson & Mccollom, P.C.

20080044990 - Method for fabricating a semiconductor device comprising surface cleaning: A method for fabricating a semiconductor device including surface cleaning includes forming a gate stack on a semiconductor substrate, cleaning contaminants present on the surface of the semiconductor substrate exposed through a contact hole using an etchant including a fluorine (F)-containing species dispersed in an alcohol, and filling a contact... Agent: Marshall, Gerstein & Borun LLP

20080044991 - Semiconductor device and method of fabricating the same: A semiconductor device including silicide layers with different thicknesses corresponding to diffusion layer junction depths, and a method of fabricating the same are provided. According to one aspect, there is provided a semiconductor device comprising a first semiconductor element device and a second semiconductor element device, wherein the first semiconductor... Agent: Foley And Lardner LLP Suite 500

20080044992 - Method for fabricating a recess gate in a semiconductor device: A method for fabricating a recess gate in a semiconductor device is provided. The method includes selectively etching an active region of a substrate to form a recess pattern, performing a post treatment on the recess pattern using a plasma, and forming a gate pattern in the recess pattern.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080044993 - Semiconductor device and method of manufacturing the same: Disclosed herein are a method of manufacturing a semiconductor device, which can prevent a stepped gate from leaning and increase the channel length of the device, thus contributing to an increase in the degree of integration of the device, as well as a semiconductor device manufactured thereby. The method comprises... Agent: Ladas & Parry LLP

20080044994 - Semiconductor device capable of threshold voltage adjustment by applying an external voltage: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region... Agent: Ladas & Parry LLP

20080044995 - Trilayer resist organic layer etch: A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the... Agent: Beyer Weaver LLP

20080044996 - Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a—Si layer, an extrinsic a—Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel... Agent: Cantor Colburn, LLP

20080044997 - Semiconductor device and method for manufacturing same: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer... Agent: Muirhead And Saturnelli, LLC

20080044998 - Method of fabricating metal interconnection of semiconductor device: A method of fabricating a metal interconnection of a semiconductor device is provided. According to an embodiment, spacers are formed at sidewalls of a first via hole in a first interlayer dielectric layer. Then, a second interlayer dielectric layer is deposited on the via hole having the spacers. A second... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080044999 - Method for an improved air gap interconnect structure: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one... Agent: Intel/blakely

20080045000 - Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction.... Agent: Harness, Dickey & Pierce, P.L.C

20080045003 - Method of wire bonding over active area of a semiconductor circuit: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over... Agent: Megica Corporation

20080045001 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080045002 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080045004 - Post passivation interconnection schemes on top of ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin Room 301/302, No. 47

20080045005 - Pattern formation method and method for forming semiconductor device: A pattern formation method includes the steps of forming a flowable film made of a material with flowability; forming at least one of a concave portion and a convex portion provided on a pressing face of a pressing member onto the flowable film by pressing the pressing member against the... Agent: Mcdermott Will & Emery LLP

20080045006 - Semiconductor device: An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole... Agent: Mcdermott Will & Emery LLP

20080045007 - Top layers of metal for integrated circuits: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses... Agent: Megica Corporation

20080045008 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin Room 301/302, No. 47

20080045009 - Method and apparatus for simultaneously removing multiple conductive materials from microelectronic substrates: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include... Agent: Perkins Coie LLP Patent-sea

20080045010 - Reducing silicon attack and improving resistivity of tungsten nitride film: The present invention provides improved methods of depositing tungsten-containing films on substrates, particularly on silicon substrates. The methods involve depositing an interfacial or “flash” layer of tungsten on the silicon prior to deposition of tungsten nitride. The tungsten flash layer is typically deposited by a CVD reaction of a tungsten... Agent: Beyer Weaver LLP

20080045011 - Trilayer resist scheme for gate etching applications: A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20080045012 - Electroprocessing profile control: Embodiments of the present invention provide methods of electroprocessing a substrate. One embodiment of the present invention provides a method comprises pressing a substrate against a polishing pad with a force less than about two pounds per square inch, the substrate contacting a first electrode of the polishing pad, applying... Agent: Patterson & Sheridan, LLP

20080045013 - Iridium encased metal interconnects for integrated circuit applications: An iridium encased copper interconnect comprises an iridium liner formed within a trench in a dielectric layer, wherein the iridium liner is formed directly on the dielectric layer, a copper interconnect formed on the iridium liner, and an iridium capping layer formed on the copper interconnect. The