Semiconductor device manufacturing: process inventions 02/08

20080050845 - Microelectromechanical systems encapsulation process: An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450 C is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation.... Agent: Courtney Staniford & Gregory LLP

20080050848 - Charged particle beam irradiation method and semiconductor device manufacturing method: A charged particle beam irradiation method includes setting an observation region on a sample, the sample including an object pattern to be observed, and the observation region including the object pattern, setting an irradiation region on the sample, the irradiation region being to be irradiated with a charged particle beam,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080050850 - Method for manufacturing semiconductor laser element: A method for manufacturing a semiconductor laser element includes forming a semiconductor laminated structure, having an active layer, on a substrate; etching the semiconductor laminated structure to form a mesa; cleaning the side of the mesa at a temperature lower thank a critical temperature at which an oxide layer forms... Agent: Leydig Voit & Mayer, Ltd

20080050851 - Method for manufacturing display device: A light-absorbing layer is selectively formed over an insulating surface, an insulating layer is formed over the insulating surface and the light-absorbing layer, the insulating surface, the light-absorbing layer, and the insulating layer are irradiated with laser light to selectively remove only the insulating layer above the light-absorbing layer in... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080050852 - Manufacturing of flexible display device panel: A manufacturing method of a display panel for an LCD includes forming a gate line on a flexible insulation substrate, depositing a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer and forming a data line and a drain electrode on the semiconductor... Agent: Macpherson Kwok Chen & Heid LLP

20080050856 - Method for manufacturing silicon device: A method for manufacturing a silicon device includes steps of: forming a silicon layer 4a that indicates a second conductivity type on a first surface S1a of a silicon substrate 2a that indicates a first conductivity type; and exposing, after the step, a third surface S3a of the silicon layer... Agent: Drinker Biddle & Reath (dc)

20080050844 - Surface reconstruction method for silicon carbide substrate: A surface reconstruction method for a silicon carbide substrate (1) includes a silicon film forming step of forming a silicon film (2) on a surface of the silicon carbide substrate (1) and a heat treatment step of heat-treating the silicon carbide substrate (1) and the silicon film (2) without providing... Agent: Fish & Richardson P.C.

20080050846 - Liquid crystal display panel device having compensation cell gap, method of fabricating the same and method of using the same: A liquid crystal display panel device includes a liquid crystal display panel, a sealing material disposed along a first outer perimeter of the liquid crystal display panel, a barrier wall disposed along a second outer perimeter of the liquid crystal display panel, and a liquid crystal material disposed within the... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20080050847 - Single ic-chip design on wafer with an embedded sensor utilizing rf capabilities to enable real-time data transmission: An apparatus and method for real-time monitoring process conditions of a semiconductor wafer processing operation. A semiconductor wafer subject to processing in a wafer processing tool is embedded with one or more sensor devices. In response to receipt of wireless electromagnetic signals, the embedded sensor devices are activated for generating... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050849 - Method to eliminate arsenic contamination in trench capacitors: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050853 - Method of fabricating display substrate: In a method of fabricating a display substrate, a photoresist layer pattern is formed on a substrate where a thin film transistor (TFT) is formed, and a transparent conductive layer is formed on the photoresist layer pattern. Then, the transparent conductive layer is patterned by a lift-off method to form... Agent: H.c. Park & Associates, PLC

20080050854 - Semiconductor light emitting element and method for manufacturing the same: A high-luminance light emitting element is manufactured by a method comprising: forming a light emitting layer on a first surface of a GaP substrate including the first surface and a second surface opposed to the first surface and having an area smaller than the first area, the light emitting layer... Agent: Hogan & Hartson L.L.P.

20080050855 - Nitride semiconductor laser device and a method for improving its performance: The present invention relates to a nitride semiconductor laser device provided with a window layer on a light-emitting end face of the resonator which comprises an active layer of nitride semiconductor between the n-type nitride semiconductor layers and the p-type nitride semiconductor layers, in which at least the radiation-emitting end... Agent: Smith Patent Office

20080050857 - Group iii nitride coatings and methods: The invention provides a composition that is a dispersion made from a Group III nitride, a solvent system, and a dispersant. The dispersion can be used to prepare Group III nitride thin films on a wide range of substrates, for example, glass, silicon, silicon dioxide, silicon nitride, silicon carbide, aluminum... Agent: Schwegman, Lundberg & Woessner, P.A.

20080050858 - Method for producing semiconductor device: A method for producing a semiconductor device includes the steps of forming a predetermined device in a device layer grown on a semiconductor substrate with a sacrificial layer provided therebetween; and removing the sacrificial layer by etching to separate the semiconductor substrate from the device layer while a supporting substrate... Agent: Robert J. Depke Lewis T. Steadman

20080050859 - Methods for a multiple die integrated circuit package: Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one... Agent: Vierra Magen/sandisk Corporation

20080050862 - Method of manufacturing a single chip semiconductor integrated circuit device including a mask rom in a short time: In a state of a first semiconductor integrated circuit device on which a first semiconductor integrated circuit board including a first mask ROM and a programmable ROM are mounted, an ultimate program determined by using the programmable ROM is stored in a second ROM of a second semiconductor integrated circuit... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080050860 - Adhesion by plasma conditioning of semiconductor chip: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits,... Agent: Texas Instruments Incorporated

20080050861 - Microelectromechanical systems encapsulation process with anti-stiction coating: An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450° C. is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation.... Agent: Courtney Staniford & Gregory LLP

20080050863 - Semiconductor structure including multiple stressed layers: A semiconductor structure and methods for fabricating the semiconductor structure include a gate electrode located over a channel region within a semiconductor substrate and a spacer layer adjacent the gate electrode. The spacer layer extends vertically above the gate electrode. The semiconductor structure also includes a first stressed layer having... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050864 - Method of manufacturing semiconductor device having impurity region under isolation region: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming... Agent: Mcdermott Will & Emery LLP

20080050865 - Non-planar transistor having germanium channel region and method of manufacturing the same: Provided is a non-planar transistor with a multi-gate structure that includes a germanium channel region, and a method of manufacturing the same. The non-planar transistor includes a silicon body and a channel region that covers exposed surfaces of the silicon body. The channel region is formed of a germanium layer... Agent: Mills & Onello LLP

20080050866 - Semiconductor structures integrating damascene-body finfet's and planar devices on a common substrate and methods for forming such semiconductor structures: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080050867 - Array substrate of liquid crystal display device and manufacturing method thereof: There is provided an array substrate of an LCD device including a plurality of gate lines aligned on the substrate, a plurality of data lines crossing the gate lines to form a plurality of pixel regions, a thin film transistor located at the intersection of the gate lines and the... Agent: Mckenna Long & Aldridge LLP

20080050868 - Method to enhance device performance with selective stress relief: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second... Agent: HorizonIPPte Ltd

20080050869 - Dual stress liner device and method: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper.... Agent: Banner & Witcoff, Ltd.

20080050870 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes the steps of: a) forming an insulating film on a semiconductor substrate; b) forming a first conductive film of a material which does not contain nitrogen on the insulating film; and c) forming a second conductive film of a material containing nitrogen... Agent: Mcdermott Will & Emery LLP

20080050872 - Fabrication of a high speed rram having narrow pulse width programming capabilities: A method of selecting a cathode material and a resistance material for use in a RRAM includes determining the work function of a group of potential resistance materials; determining the work function of a group of potential cathode materials; and selecting a suitable material for the resistance material from the... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080050871 - Methods for removing material from one layer of a semiconductor device structure while protecting another material layer and corresponding semiconductor device structures: Methods for removing material from one layer of a semiconductor device structure, such as an etch stop layer beneath a capacitor container, without substantially removing material from an overlying layer that includes the same material, such as a protective or reinforcing lattice over the capacitor container, include employing process parameters... Agent: Trask Britt, P.C./ Micron Technology

20080050873 - Semiconductor structures with body contacts and fabrication methods thereof: A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080050874 - Metal-insulator-metal capacitor and method of manufacturing the same: A metal-insulator-metal capacitor includes a first electrode in a first wiring level, a second electrode above the first wiring level and extending into a first portion of the first electrode that surrounds the second electrode, and a dielectric film separating the first electrode from the second electrode.... Agent: Volentine & Whitt PLLC

20080050875 - Methods of fabricating embedded flash memory devices: A method of fabricating a compound device includes forming a first gate insulating pattern on a semiconductor substrate including a first region and a second region, forming a second gate insulating layer on the first gate insulating pattern, and after forming the second gate insulating layer, forming a well in... Agent: Lee & Morse, P.C.

20080050876 - Method for fabricating silicon carbide vertical mosfet devices: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a... Agent: General Electric Company Global Research

20080050877 - Superjunction trench device and method: Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second (74-1, 74-2, 74-3, etc.) spaced-apart regions of first (70) and... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080050878 - Method for preparing a memory structure: A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporating the first etching mask... Agent: Oliff & Berridge, PLC

20080050879 - Methods of forming metal-containing gate structures: A method of forming a metal-containing gate includes forming a high-k dielectric layer over a substrate. A process using an oxygen-containing solution is provided to process the high-k dielectric layer. A metal-containing layer is formed over the high-k dielectric layer. The high-k dielectric layer and metal-containing layer are patterned, thereby... Agent: Duane Morris LLPIPDepartment (tsmc)

20080050880 - Structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050881 - Heterojunction tunneling field effect transistors, and methods for fabricating the same: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050882 - System and method for mitigating oxide growth in a gate dielectric: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer... Agent: Texas Instruments Incorporated

20080050883 - Hetrojunction bipolar transistor (hbt) with periodic multilayer base: A method and resulting electronic device utilizing a periodic multi-layer (ML) and/or superlattice (SL) structures in the base of a SiGe heterojunction bipolar transistor (HBT) is disclosed. The SL is a special case of an ML, in which layers that are chemically different from adjacent neighbors are successively repeated. The... Agent: Schneck & Schneck

20080050884 - Process for manufacturing semiconductor device: A dielectric body is formed by an ALD film deposition process comprising a gas flow sequence where a purging step after supplying a source and a reactant gases is a two-stage purging of vacuum purging and gas purging and the step of supplying a reactant gas is further divided. The... Agent: Sughrue Mion, PLLC

20080050886 - Method of producing semiconductor device: d

20080050885 - System and method for fabricating a fin field effect transistor: There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching... Agent: Fletcher Yoder (micron Technology, Inc.)

20080050887 - Method for fabricating sige-on-insulator (sgoi) and ge-on-insulator (goi) substrates: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the... Agent: Scully, Scott, Murphy & Presser, P.C.

20080050888 - Laser separation of thin laminated glass substrates for flexible display applications: A method of separating a sheet of coated brittle material comprises the steps of providing a sheet of layered brittle material comprising a brittle layer and a coating material adhered to a surface of the brittle layer and applying a laser along a separation line in the sheet, thereby cutting... Agent: Corning Incorporated

20080050889 - Hotwall reactor and method for reducing particle formation in gan mocvd: Systems and methods to suppress the formation of parasitic particles during the deposition of a III-V nitride film with, e.g., metal-organic chemical vapor deposition (MOCVD) are described. In accordance with certain aspects of the invention, a hotwall reactor design and methods associated therewith, with wall temperatures similar to process temperatures,... Agent: Townsend And Townsend And Crew LLP / Amat

20080050890 - Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates: A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080050891 - Coplanar silicon-on-insulator (soi) regions of different crystal orientations and methods of making the same: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI... Agent: Ibm Corporation, Intellectual Property Law

20080050892 - Method of manufacturing a thin film structure, method of manufacturing a storage node using the same, method of manufacturing a phase change random access memory using the same and a thin film structure, a storage node and a phase change random access mem: Provided are a method of manufacturing a thin film structure, a method of manufacturing a storage node having the same, a method of manufacturing a phase-change random access memory device having the same and a thin film structure, storage node and phase-change random access memory device formed using the same.... Agent: Harness, Dickey & Pierce, P.L.C

20080050893 - Manufacturing method of display device: A method of manufacturing a display device to improve the quality of a polycrystal silicon upon dehydrogenating and polycrystallizing an amorphous silicon at the outside of a display region of a substrate, by forming a plurality of pixels having TFT devices using an amorphous silicon in the display region of... Agent: Reed Smith LLP

20080050894 - Preparation method of a coating of gallium nitride: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080050895 - Method for manufacturing semiconductor device: In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes using a photoresist and simplifying the process is provided, and the throughput is improved. An etching mask for forming a pattern of a layer to be processed such as a conductive layer... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080050896 - Fabricating method of silicon layer with high resistance: A silicon layer with high resistance is provided. The silicon layer with high resistance is positioned on a substrate. Also, the silicon layer with high resistance includes a plurality of silicon material layers, and an interface layer between every two of the silicon material layers, wherein, the silicon material layers... Agent: Jianq Chyun Intellectual Property Office

20080050897 - Method for doping a fin-based semiconductor device: A method for doping a multi-gate device is disclosed. In one aspect, the method comprises patterning a fin in a substrate, depositing a gate stack, and doping the fin. The process of doping the fin is done by depositing a blocking mask material at least on the top surface of... Agent: Knobbe Martens Olson & Bear LLP

20080050898 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, disposing a gate dielectric material over the workpiece, and disposing a gate material over the gate dielectric material. Cl or F is introduced to the gate... Agent: Slater & Matsil, L.L.P.

20080050899 - Method for manufacturing a semiconductor device having a polymetal gate electrode structure: A process for manufacturing a semiconductor device having a polymetal structure includes patterning a bottom electrode layer by using a sacrificial layer pattern oxidizing the side surface of the patterned bottom electrode layer, forming a sidewall oxide film on both the patterned bottom electrode layer and the sacrificial layer pattern,... Agent: Young & Thompson

20080050900 - Methods for pitch reduction formation: Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elements and peripheral circuitry and results in a reduction in pitch.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080050902 - Method for forming an independent bottom gate connection for buried interconnection including bottom gate of a planar double gate mosfet: A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first (251), second and third (252) openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate;... Agent: Fortkort & Houston P.C.

20080050901 - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements... Agent: Perkins Coie LLP Patent-sea

20080050903 - Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof: Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width... Agent: Ibm Corporation Department 417

20080050904 - Methods for attaching microfeature dies to external devices: Methods for attaching microfeature dies to external devices are disclosed. The external devices can include other microfeature dies, support members or other suitable devices. A particular method includes attaching the solder to the at least one of the microfeature die in the support member by changing a phase of the... Agent: Perkins Coie LLP Patent-sea

20080050906 - Low fabrication cost, fine pitch and high reliability solder bump: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin Room 301/302, No. 47

20080050905 - Method of manufacturing semiconductor device: A semiconductor device is fabricated by making first and second UBM films on an external terminal, the first under bump metal film having no wettability to a bump electrode and the second UBM film having wettability to the bump electrode; placing the bump electrode on the second UBM film; patterning... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080050907 - Semiconductor component with plastic housing, and process for producing the same: A semiconductor component includes a plastic housing including: plastic outer surfaces; lower outer contact surfaces arranged on an underside of the housing; upper outer contact surfaces arranged on a top side of the housing that is opposite the underside; and outer interconnects electrically connecting the lower outer contact surfaces to... Agent: Edell , Shapiro & Finnan , LLC

20080050908 - Semiconductor device and method of manufacture thereof: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080050909 - Top layers of metal for high performance ic's: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about... Agent: Mou-shiung Lin Room 301/302

20080050910 - Method for producing smooth, dense optical films: The invention is directed to preparing optical elements having a thin, smooth, dense coating or film thereon, and a method for making such coating or film. The coated element has a surface roughness of <1.0 nm rms. The coating materials include hafnium oxide or a mixture of hafnium oxide and... Agent: Corning Incorporated

20080050911 - Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods: Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining... Agent: Perkins Coie LLP Patent-sea

20080050912 - Chip structure and process for forming the same: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric... Agent: Mou-shiung Lin

20080050913 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20080050914 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device according to the present invention includes: a step for forming a wiring layer on a semiconductor substrate; a step for patterning the wiring layer; and a step for covering the wiring layer with a protective insulating film. Moreover, after the step for forming... Agent: Rabin & Berdo, PC

20080050915 - Method for manufacturing semiconductor device: In the method for manufacturing a semiconductor device relating to the present invention, first, a metal film is formed onto a substrate in the state where a silicide forming region is exposed onto the surface of substrate. Next, thermal processes at pressure higher than atmosphere are conducted to the substrate... Agent: Mcdermott Will & Emery LLP

20080050916 - Methods and apparatus for depositing tantalum metal films to surfaces and substrates: Methods and an apparatus are disclosed for depositing tantalum metal films in next-generation solvent fluids on substrates and/or deposition surfaces useful, e.g., as metal seed layers. Deposition involves low valence oxidation state metal precursors soluble in liquid and/or compressible solvent fluids at liquid, near-critical, or supercritical conditions for the mixed... Agent: Battelle Memorial Institute Attn:IPServices, K1-53

20080050917 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device improves the cleaning efficiency by increasing a cleaning time and temperature, including a copper Chemical Mechanical Planarization process for a semiconductor wafer with a copper line. The method includes a main Cu CMP process to chemically and mechanically polish a surface of the... Agent: Sherr & Nourse, PLLC

20080050918 - Method for producing a device comprising a structure equipped with one or more microwires or nanowires based on a si and ge compound by germanium condensation: b) lateral thermal oxidation of the sides of the second Si1-yGey-based semiconductor zone so as to reduce the second zone in at least one direction parallel to the main plane of the support and to form one or more Si1-zGez-based semiconductor wire(s) (with 0<y<1 and y<z).... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080050919 - High aspect ratio via etch: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three... Agent: Knobbe Martens Olson & Bear LLP

20080050920 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first insulating film on a semiconductor substrate; forming a mask with an opening of a predetermined pattern in the first insulating film; performing anisotropic etching on the semiconductor substrate with the mask... Agent: Sughrue Mion, PLLC

20080050921 - Method for manufacturing semiconductor device: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property.... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080050922 - Chamber recovery after opening barrier over copper: A chamber dry cleaning process particularly useful after a dielectric plasma etch process which exposes an underlying copper metallization. After the dielectric etch process, the production wafer is removed from the chamber and a cleaning gas is excited into a plasma to clean the chamber walls and recover the dielectric... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20080050923 - Low-k damage avoidance during bevel etch processing: A method for etching a bevel edge of a substrate is provided. A patterned photoresist mask is formed over the etch layer. The bevel edge is cleaned comprising providing a cleaning gas comprising at least one of a CO2, CO, CxHy, H2, NH3, CxHyFz and a combination thereof, forming a... Agent: Beyer Weaver LLP

20080050924 - Substrate carrying apparatus and substrate carrying method: The substrate processing apparatus, adapted to provide a process, such as etching, to a wafer, comprises the processing vessel, the ambient atmospheric carrying chamber, and the functional module, such as an orienter 4. With the process to be provided, matters having potential to generate corrosive gases or the like due... Agent: Smith, Gambrell & Russell

20080050925 - Photoresist processing methods: A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form... Agent: Wells St. John P.s.

20080050926 - Dry etching method: In dry etching an insulating film containing silicon and carbon and formed on a wafer, plasma is generated from a mixed gas of a first molecule gas containing carbon and fluorine and a second molecule gas containing nitrogen. At this time, an RF bias of 2 MHz or lower is... Agent: Mcdermott Will & Emery LLP

20080050927 - Variable temperature and dose atomic layer deposition: A variable temperature and/or reactant dose atomic layer deposition (VTD-ALD) process modulates ALD reactor conditions (e.g., temperature, flow rates, etc.) during growth of a film (e.g., metallic) on a wafer to produce different film properties a different film depths.... Agent: Intel/blakely

20080050930 - Method of forming insulating film and method of manufacturing semiconductor device: A method of forming an insulating film according to one embodiment of the present invention, which is a method of forming an insulating film for use in a semiconductor device, performs thermal oxidation of a tantalum nitride film at a temperature range of 200 to 400 degrees centigrade by a... Agent: Young & Thompson

20080050928 - Semiconductor constructions, and methods of forming dielectric materials: Some embodiments include methods of forming dielectric materials associated with semiconductor constructions. A semiconductor substrate surface having two different compositions may be exposed to a first silanol, then to organoaluminum to form a monolayer, and finally to a second silanol to form a dielectric material containing aluminum from the organoaluminum... Agent: Wells St. John P.s.

20080050929 - Method of and apparatus for low-temperature epitaxy on a plurality of semiconductor substrates: wherein the semiconductor substrates are moved or stored during the cleaning step and during transport from the first reactor into the second reactor in an interruption-free manner in a reducing gas atmosphere as long as the substrate temperature is above a critical temperature Tc which is dependent on the substrate... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080050931 - Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080050932 - Overall defect reduction for pecvd films: The present invention generally provides an apparatus and method for reducing defects on films deposited on semiconductor substrates. One embodiment of the present invention provides a method for depositing a film on a substrate. The method comprises treating the substrate with a first plasma configured to reduce pre-existing defects on... Agent: Patterson & Sheridan, LLP

20080050933 - Insulator film, manufacturing method of multilayer wiring device and multilayer wiring device: In a method for manufacturing a semiconductor device, including forming an insulator film including a material having Si—CH3 bond and Si—OH bond, and irradiating the insulator film with ultraviolet rays, the rate of decrease of C concentration by X-ray photoelectron spectroscopy is not more than 30%, and the rate of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080044931 - Packaging substrate and method of manufacturing the same: A packaging substrate and a method of manufacturing the same are provided. The method includes following steps. First, a first substrate including at least one defected packaging unit and several first packaging units is provided. The defected packaging unit and the first packaging units are arranged in an array on... Agent: Birch Stewart Kolasch & Birch

20080044933 - Method for forming matching table of inner pads and outer pads and method for matching inner pads with outer pads using the same: A method for forming a matching table of inner pads and outer pads includes the steps of: obtaining a pitch Pi and a space Si between two neighboring inner pads; computing Wim=m×Pi−Si; obtaining a pitch Po and a space So between two neighboring outer pads; computing Won=n×Po−So; computing Rn=Won+(So×C); comparing... Agent: Bacon & Thomas, PLLC

20080044934 - Methods of forming semiconductor light emitting device packages by liquid injection molding and molded semiconductor light emitting device strips: Semiconductor light emitting device packaging methods include fabricating a substrate configured to mount a semiconductor light emitting device thereon. The substrate may include a cavity configured to mount the semiconductor light emitting device therein. The semiconductor light emitting device is mounted on the substrate and electrically connected to a contact... Agent: Myers Bigel Sibley & Sajovec

20080044937 - Method of forming surface irregularities and method of manufacturing gallium nitride-based light emitting diode: A method of forming surface irregularities comprises preparing a GaN substrate; forming a mask on a surface of the GaN substrate, the mask defining a surface-irregularity formation region; and wet-etching portions of the surface of the GaN substrate by using the mask as an etching mask. The wet-etching of the... Agent: Mcdermott Will & Emery LLP

20080044938 - Technique for low-temperature ion implantation: A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter. The apparatus may also comprise a cooling... Agent: Varian Semiconductor Equipment Assc., Inc.

20080044941 - Fabricating cmos image sensor: A fabrication method of a CMOS image sensor provides forms micro lenses over a substrate by etching a plurality of holes in a wiring layer over a pixel area. An oxide layer is deposited to form a surface with a semi-circular cross section over the holes. The oxide layer may... Agent: Sherr & Nourse, PLLC

20080044942 - Method of fabricating cmos image sensor: A method of manufacturing a complimentary metal oxide semiconductor (CMOS) image sensor. The method includes a step of performing a silicide process relative to a plug for transferring electrons generated from a photodiode. The silicide of the plug blocks light irradiated through the plug, so that the performance of the... Agent: Sherr & Nourse, PLLC

20080044930 - Transplanted magnetic random access memory (mram) devices on thermally-sensitive substrates using laser transfer and method of making the same: A method of forming a magnetic memory device (and a resulting structure) on a low-temperature substrate, includes forming the memory device on a transparent substrate coated with a decomposable material layer subject to rapid heating resulting in a predetermined high pressure, and transferring the memory device to the low-temperature substrate.... Agent: Mcginn Intellectual Property Law Group, PLLC

20080044932 - Carbon precursors for use during silicon epitaxial film formation: The present invention provides systems and methods of forming an epitaxial film on a substrate. After heating in a process chamber, the substrate is exposed to a silicon source and at least one of SiH2(CH3)2, SiH(CH3)3, Si(CH3)4, 1,3-disilabutane, and C2H2, at a temperature of greater than about 250 degrees Celsius... Agent: Dugan & Dugan, PC

20080044935 - Method for manufacturing contact structure of pixel electrode of liquid crystal display device: A method for manufacturing a pixel electrode contact structure of a thin-film transistors liquid crystal display is disclosed. First, a transparent substrate having a first insulating layer thereon is provided. Afterward, a first metal layer and a second metal layer are sequentially formed on the substrate and then be patterned... Agent: Bacon & Thomas, PLLC

20080044936 - Semiconductor laser module, optical amplifier, and method of manufacturing the semiconductor laser module: A semiconductor laser module has a semiconductor laser device; a package for housing the semiconductor laser device; a PBC fixed in the package for polarization-synthesizing two laser beams output from the semiconductor laser device; a depolarizing element fixed in the package for depolarizing a synthesizing light output from the PBC;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080044939 - Low power silicon thermal sensors and microfluidic devices based on the use of porous sealed air cavity technology or microchannel technology: This invention provides a miniaturized silicon thermal flow sensor with improved characteristics, based on the use of two series of integrated thermocouples (6, 7) on each side of a heater (4), all integrated on a porous silicon membrane (2) on top of a cavity (3). Porous silicon (2) with the... Agent: Marshall, Gerstein & Borun LLP

20080044940 - Laminating system: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it... Agent: Nixon Peabody

20080044943 - Manufacture of silicon-based devices having disordered sulfur-doped surface layers: The present invention provides methods of fabricating a radiation-absorbing semiconductor wafer by irradiating at least one surface location of a silicon substrate, e.g., an n-doped crystalline silicon, by a plurality of temporally short laser pulses, e.g., femtosecond pulses, while exposing that location to a substance, e.g., SF6, having an electron-donating... Agent: Nutter Mcclennen & Fish LLP

20080044944 - Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080044945 - Filling paste structure and process for wl-csp: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate.... Agent: Kusner & Jaffe Highland Place Suite 310

20080044946 - Semiconductor die package using leadframe and clip and method of manufacturing: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used... Agent: Townsend And Townsend And Crew, LLP

20080044947 - A method to provide substrate-ground coupling for semiconductor integrated circuit dice constructed from soi and related materials in stacked-die packages: An apparatus and a method for packaging semiconductor devices. Disclosed are multi-die packaging apparatuses and techniques, especially useful for integrated circuit dice involving insulative substrates, such as silicon-on-insulator (SOI), where grounding of a base layer is not reasonably practical. Disclosed is a means for effectively grounding all layers of an... Agent: Schneck & Schneck

20080044948 - Manufacturing method for resin sealed semiconductor device: The present invention relates to a leadless, resin sealed semiconductor device structure and manufacturing method. In the semiconductor device according to the present invention, one side of a thin plate made of copper or the like is subjected to half etching, and a plurality of die pad portions (3) and... Agent: Bruce L. Adams, Esq.

20080044949 - High performance reworkable heatsink and packaging structure with solder release layer and method of making: A method of making and a high performance reworkable heatsink and packaging structure with solder release layer are provided. A heatsink structure includes a heatsink base frame. A selected one of a heatpipe or a vapor chamber, and a plurality of parallel fins are soldered to the heatsink base frame.... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080044950 - Multi-layer fin wiring interposer fabrication process: An interposer having multi-layer fine wiring structure which comprises an insulating layer made of photosensitive polyimide which is photosensitive organic material and a wiring layer portion made of metal, such as copper, silver, gold, aluminum, palladium, indium, titanium, tantalum, and niobium, functions as wiring in an integrated circuit chip, wherein... Agent: Rader Fishman & Grauer PLLC

20080044951 - Semiconductor package and method of manufacturing the same: A semiconductor package may include a substrate having external contact terminals. A semiconductor chip having bonding pads may be formed on the substrate. Conductive bumps may connect the external contact terminals of the substrate to the bonding pads of the semiconductor chip. An underfill may be interposed between the substrate... Agent: Harness, Dickey & Pierce, P.L.C

20080044952 - Selective removal of gold from a lead frame: A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions... Agent: Texas Instruments Incorporated

20080044953 - Method for forming an array substrate: Disclosed is a method for manufacturing an array substrate utilizing a laser ablation process. With the laser ablation process, a photoresist layer is removed along with the transparent conductive layer therefrom, while maintaining other portions of the transparent conductive layer. Moreover, the laser ablation process of the invention does not... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080044954 - Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby: A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact.... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080044955 - Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply: An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise... Agent: Mh2 Technology Law Group, LLP

20080044956 - Apparatus for etching substrate and method of fabricating thin-glass substrate: An apparatus for etching a substrate includes (a) a nozzle system including at least one nozzle through which acid solution containing at least hydrofluoric acid is sprayed onto the substrate, (b) a mover which moves at least one of the nozzle system and the substrate relative to the other in... Agent: Scully Scott Murphy & Presser, PC

20080044958 - Method of fabricating complementary metal-oxide semiconductor (cmos) thin film transistor (tft): A method of fabricating a Complementary Metal-Oxide Semiconductor (CMOS) Thin Film Transistor (TFT) using a reduced number of masks includes: forming a buffer layer on the entire surface of a substrate; forming polysilicon and photoresist layers on the entire surface of the substrate having the buffer layer; exposing and developing... Agent: Robert E. Bushnell

20080044957 - Work function control of metals: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the... Agent: Texas Instruments Incorporated

20080044959 - Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures: A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080044960 - Semiconductor on insulator vertical transistor fabrication and doping process: A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into... Agent: Law Office Of Robert M. Wallace

20080044961 - Thin film transistor array panel: The present invention provides a thin film transistor array panel comprising: an insulating substrate; a first signal line formed on the insulating substrate and extending in a first direction; a second signal line formed on the insulating substrate, extending in a second direction, and intersecting the first signal line; a... Agent: Cantor Colburn, LLP

20080044962 - Electro-optical device and thin film transistor and method for forming the same: A semiconductor device having a pair of impurity doped second semiconductor layers, formed on a first semiconductor layer having a channel formation region therein, an outer edge of the first semiconductor film being at least partly coextensive with an outer edge of the impurity doped second semiconductor layers. The semiconductor... Agent: Eric Robinson

20080044963 - Tft substrate for liquid crystal display apparatus and method of manufacturing the same: There are provided a TFT substrate for an LCD apparatus and a method of manufacturing the same. A substrate (10), a diffusion barrier layer (11) and a copper alloy layer (12) are formed on the TET substrate, consecutively. The copper alloy includes a material from about 0.5 at % to... Agent: Cantor Colburn, LLP

20080044964 - Printed dopant layers: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080044965 - Method of manufacturing thin film transistor array panel: A method of manufacturing a thin film transistor array panel includes forming an amorphous silicon film on an insulating substrate; forming a sacrificial film having an embossed surface on the amorphous silicon film; contacting a metal plate with the sacrificial film and performing heat-treatment for crystallizing the amorphous silicon film... Agent: Cantor Colburn, LLP

20080044966 - Enhancement of electron and hole mobilities in <110> si under biaxial compressive strain: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress... Agent: Scully, Scott, Murphy & Presser, P.C.

20080044967 - Integrated circuit system having strained transistor: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer on the wafer, protecting a portion of the stress formation layer, and irradiating the wafer for modification of a stress value of an unprotected portion of the stress formation layer.... Agent: Law Offices Of Mikio Ishimaru

20080044968 - Method for improving transistor performance through reducing the salicide interface resistance: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon... Agent: Intel/blakely

20080044969 - Turn-on-efficient bipolar structures with deep n-well for on-chip esd protection: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the... Agent: Berkeley Law & Technology Group, LLP

20080044970 - Memory structure and method for preparing the same: A memory structure comprises a semiconductor substrate, an active are positioned in the semiconductor substrate, a plurality of doped regions positioned in the semiconductor substrate, a first conductive plug connecting a bit line and one of the doped regions and a second conductive plug connecting a capacitor and another one... Agent: Oliff & Berridge, PLC

20080044971 - Method for fabricating a semiconductor device having a capacitor: A method for fabricating a semiconductor device is disclosed. The method includes forming an etch stop layer on a substrate, forming a mold layer on the substrate, and forming an opening exposing the substrate by patterning the mold layer and the etch stop layer, wherein the opening includes a lower... Agent: Volentine & Whitt PLLC

20080044972 - Methods of forming nonvolatile memories with shaped floating gates: In a nonvolatile memory using floating gates to store charge, individual floating gates are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may also alternate in the word line direction. L-shaped floating gates are formed by etching conductive portions using etch masks of different... Agent: Winston & Strawn, LLP

20080044973 - Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose cmos technology: A method and corresponding structure for shielding a floating gate tunneling element. The method comprises disposing a floating gate over a gate oxide using standard CMOS processing in two active areas defined by first and second doped well regions formed in a substrate surrounded by field oxide, and forming a... Agent: Nixon Peabody, LLP

20080044974 - Embedded stressed nitride liners for cmos performance improvement: The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying... Agent: Scully, Scott, Murphy & Presser, P.C.

20080044975 - Thin-film transistor, method for manufacturing thin-film transistor, and display using thin-film transistors: The present invention provides a thin-film transistor offering a higher electron (or hole) mobility, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. The present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080044976 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin Science-based Industrial Park

20080044977 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080044978 - Isolation structures for integrated circuits and modular methods of forming the same: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall... Agent: Patentability Associates

20080044979 - Integrated circuitry, electromagnetic radiation interaction components, transistor devices and semiconductor construction; and methods of forming integrated circuitry, electromagnetic radiation interaction components, transistor devices and semiconductor: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The... Agent: Wells St. John P.s.

20080044980 - Method of forming a semiconductor device: A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric... Agent: Slater & Matsil LLP

20080044981 - Trench isolation methods, methods of forming gate structures using the trench isolation methods and methods of fabricating non-volatile memory devices using the trench isolation methods: Methods of fabricating semiconductor devices including forming a mask pattern on a semiconductor substrate are provided. The mask pattern defines a first opening that at least partially exposes the semiconductor substrate and includes a pad oxide layer and a nitride layer pattern on the pad oxide layer pattern. The nitride... Agent: Myers Bigel Sibley & Sajovec

20080044982 - Thin film transistor array panel for a display device and a method of manufacturing the same: A method of manufacturing a thin film transistor array panel includes forming gate lines including gate electrodes on an insulation substrate; forming a gate insulating layer, semiconductor layer, and etch stop layer on the gate lines; etching and patterning the etch stop and semiconductor layers at the same time using... Agent: F. Chau & Associates, LLC

20080044983 - Element formation substrate, method of manufacturing the same, and semiconductor device: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080044984 - Methods of avoiding wafer breakage during manufacture of backside illuminated image sensors: A process for forming backside illuminated devices is disclosed. Specifically, the process reduces processing damage to wafers caused by poor bond quality at the wafer edge ring. In one embodiment, a wafer edge trimming step is implemented prior to bonding the wafer to the substrate. A pre-grind blade is used... Agent: Duane Morris LLPIPDepartment (tsmc)

20080044985 - Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods: Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods are disclosed herein. One embodiment, for example, is directed to a method for processing a microfeature workpiece releasably attached to a first support member. The workpiece includes a microelectronic substrate, a plurality of... Agent: Perkins Coie LLP Patent-sea

20080044986 - Method for improved dielectric performance: A method of decreasing the density of dielectric interface traps in an integrated circuit device. In accordance with the teachings of the present invention, the method includes providing a semiconductor substrate, processing the semiconductor substrate to form an integrated circuit device, such as a field effect transistor including forming a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080044987 - Enhancement of electron and hole mobilities in <110> si under biaxial compressive strain: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress... Agent: Scully, Scott, Murphy & Presser, P.C.

20080044988 - Method for producing an integrated circuit having semiconductor zones with a steep doping profile: An integrated circuit and method, producing semiconductor zones with a steep doping profile is disclosed. In one embodiment, dopants are implanted in a region corresponding to the semiconductor zone to be formed and which has at least one topology process. During the subsequent laser irradiation for activating the dopants in... Agent: Dicke, Billig & Czaja

20080044989 - Photomask and its method of manufacture: An embodiment of a photomask for forming gate lines and a method of manufacturing semiconductor devices using the photomask is disclosed. The photomask includes a photomask substrate, gate line mask patterns that define gate lines that cross at least one active region on a semiconductor substrate, and that are arranged... Agent: Marger Johnson & Mccollom, P.C.

20080044990 - Method for fabricating a semiconductor device comprising surface cleaning: A method for fabricating a semiconductor device including surface cleaning includes forming a gate stack on a semiconductor substrate, cleaning contaminants present on the surface of the semiconductor substrate exposed through a contact hole using an etchant including a fluorine (F)-containing species dispersed in an alcohol, and filling a contact... Agent: Marshall, Gerstein & Borun LLP

20080044991 - Semiconductor device and method of fabricating the same: A semiconductor device including silicide layers with different thicknesses corresponding to diffusion layer junction depths, and a method of fabricating the same are provided. According to one aspect, there is provided a semiconductor device comprising a first semiconductor element device and a second semiconductor element device, wherein the first semiconductor... Agent: Foley And Lardner LLP Suite 500

20080044992 - Method for fabricating a recess gate in a semiconductor device: A method for fabricating a recess gate in a semiconductor device is provided. The method includes selectively etching an active region of a substrate to form a recess pattern, performing a post treatment on the recess pattern using a plasma, and forming a gate pattern in the recess pattern.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080044993 - Semiconductor device and method of manufacturing the same: Disclosed herein are a method of manufacturing a semiconductor device, which can prevent a stepped gate from leaning and increase the channel length of the device, thus contributing to an increase in the degree of integration of the device, as well as a semiconductor device manufactured thereby. The method comprises... Agent: Ladas & Parry LLP

20080044994 - Semiconductor device capable of threshold voltage adjustment by applying an external voltage: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region... Agent: Ladas & Parry LLP

20080044995 - Trilayer resist organic layer etch: A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the... Agent: Beyer Weaver LLP

20080044996 - Contact structure of semiconductor device, manufacturing method thereof, thin film transistor array panel including contact structure, and manufacturing method thereof: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a—Si layer, an extrinsic a—Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel... Agent: Cantor Colburn, LLP

20080044997 - Semiconductor device and method for manufacturing same: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer... Agent: Muirhead And Saturnelli, LLC

20080044998 - Method of fabricating metal interconnection of semiconductor device: A method of fabricating a metal interconnection of a semiconductor device is provided. According to an embodiment, spacers are formed at sidewalls of a first via hole in a first interlayer dielectric layer. Then, a second interlayer dielectric layer is deposited on the via hole having the spacers. A second... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080044999 - Method for an improved air gap interconnect structure: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one... Agent: Intel/blakely

20080045000 - Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction.... Agent: Harness, Dickey & Pierce, P.L.C

20080045003 - Method of wire bonding over active area of a semiconductor circuit: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over... Agent: Megica Corporation

20080045001 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080045002 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin

20080045004 - Post passivation interconnection schemes on top of ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin Room 301/302, No. 47

20080045005 - Pattern formation method and method for forming semiconductor device: A pattern formation method includes the steps of forming a flowable film made of a material with flowability; forming at least one of a concave portion and a convex portion provided on a pressing face of a pressing member onto the flowable film by pressing the pressing member against the... Agent: Mcdermott Will & Emery LLP

20080045006 - Semiconductor device: An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole... Agent: Mcdermott Will & Emery LLP

20080045007 - Top layers of metal for integrated circuits: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses... Agent: Megica Corporation

20080045008 - Post passivation interconnection schemes on top of ic chip: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Mou-shiung Lin Room 301/302, No. 47

20080045009 - Method and apparatus for simultaneously removing multiple conductive materials from microelectronic substrates: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include... Agent: Perkins Coie LLP Patent-sea

20080045010 - Reducing silicon attack and improving resistivity of tungsten nitride film: The present invention provides improved methods of depositing tungsten-containing films on substrates, particularly on silicon substrates. The methods involve depositing an interfacial or “flash” layer of tungsten on the silicon prior to deposition of tungsten nitride. The tungsten flash layer is typically deposited by a CVD reaction of a tungsten... Agent: Beyer Weaver LLP

20080045011 - Trilayer resist scheme for gate etching applications: A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20080045012 - Electroprocessing profile control: Embodiments of the present invention provide methods of electroprocessing a substrate. One embodiment of the present invention provides a method comprises pressing a substrate against a polishing pad with a force less than about two pounds per square inch, the substrate contacting a first electrode of the polishing pad, applying... Agent: Patterson & Sheridan, LLP

20080045013 - Iridium encased metal interconnects for integrated circuit applications: An iridium encased copper interconnect comprises an iridium liner formed within a trench in a dielectric layer, wherein the iridium liner is formed directly on the dielectric layer, a copper interconnect formed on the iridium liner, and an iridium capping layer formed on the copper interconnect. The iridium encased copper... Agent: Intel Corporation C/o Intellevate, LLC

20080045014 - Complex chemical mechanical polishing and method for manufacturing shallow trench isolation structure: A complex chemical mechanical polishing process for planarizing a structure. The process comprises steps of performing a main polishing process with a first polishing rate, wherein a slurry is provided. An assisted polishing process is then performed to planarizing the structure. The assisted polishing process comprises steps of providing the... Agent: Jianq Chyun Intellectual Property Office

20080045015 - Method of etching wafer: A method of etching a wafer includes the steps of holding the wafer on a chuck table in the condition where a recessed part formed in the wafer by grinding is directed up, and supplying a required amount of an etchant into the recessed part to perform etching. Subsequently, the... Agent: Greer, Burns & Crain

20080045016 - Cleaning composition, cleaning method, and manufacturing method of semiconductor device: m

20080045017 - Semiconductor wafer handler: A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor wafer through orifices (100) containing in the ring (70). Water and/or nitrogen can be applied to the surface of the semiconductor wafer... Agent: Texas Instruments Incorporated

20080045018 - Method of chemical-mechanical polishing and method of forming isolation layer using the same: A method of chemical-mechanical polishing (CMP) and a method of forming an isolation layer using the same are provided. The method of chemical-mechanical polishing includes performing a first chemical-mechanical polishing operation on an insulating layer having a zeta potential with a first polarity by supplying a first slurry on the... Agent: Harness, Dickey & Pierce, P.L.C

20080045020 - Slurry composition for a chemical mechanical polishing process, method of polishing an object layer and method of manufacturing a semiconductor memory device using the slurry composition: A slurry composition for a chemical mechanical processing process includes about 0.05 to about 0.3 percent by weight of a ceria abrasive, about 0.005 to about 0.04 percent by weight of an anionic surfactant, about 0.0005 to about 0.003 percent by weight of a polyoxyethylene-based nonionic surfactant, about 0.2 to... Agent: F. Chau & Associates, LLC

20080045021 - Dual reduced agents for barrier removal in chemical mechanical polishing: Compositions and methods for removal of barrier layer materials by a chemical mechanical polishing technique are provided. In one aspect, the invention provides a composition adapted for removing a barrier layer material in a chemical mechanical polishing technique including at least one reducing agent selected from the group of bicarboxylic... Agent: Patent Counsel Applied Materials, Inc.

20080045019 - Method of fabricating semiconductor device: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer;... Agent: F. Chau & Associates, LLC

20080045022 - Semiconductor device manufacturing method: After a polycrystalline silicon film (5) is formed on a semiconductor substrate via an insulating film for a gate insulating film (step S1), an organic antireflection film (21) is formed on the polycrystalline silicon film (5) (step S2), and a resist pattern (22) is formed on the antireflection film (21)... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080045023 - Method for manufacturing semiconductor device, and semiconductor device: A method for manufacturing a semiconductor device includes: a) forming a first single-crystalline semiconductor layer having a higher etching selection ratio than a semiconductor substrate, in a manner covering an exposed part of a single-crystalline region on an active surface of the semiconductor substrate; b) forming a second single-crystalline semiconductor... Agent: Advantedge Law Group, LLC

20080045024 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a predetermined structure including a first inorganic insulating film covering a copper interconnection, an organic insulating film formed above the first inorganic insulating film and having a hole pattern, and a second inorganic insulating film formed above the organic insulating film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080045026 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a photo-resist pattern above a first film, implanting a predetermined dopant that increases an etching rate of the first film into the first film using the photo-resist pattern as a mask, thereby forming an implantation layer in the first film, and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080045025 - Semiconductor device manufacturing method: A method includes forming an etching mask having a predetermined circuit pattern on an Si-containing low dielectric constant film disposed on a semiconductor substrate; performing etching on the Si-containing low dielectric constant film through the etching mask by use of an F-containing gas, thereby forming a groove or hole; performing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080045027 - Method for fabricating semiconductor intergrated circuit device: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080045028 - Wafer probe: The present invention relates to a probe for testing of integrated circuits or other microelectronic devices.... Agent: Chernoff, Vilhauer, Mcclung & Stenzel

20080045029 - Semiconductor substrate processing apparatus: According to one aspect of the invention, a semiconductor substrate processing apparatus and a method for processing semiconductor substrates are provided. The semiconductor substrate processing apparatus may include a semiconductor substrate support, a dispense head positioned over the semiconductor substrate support, a liquid container, and a transport subsystem. A semiconductor... Agent: Blakely Sokoloff Taylor & Zafman

20080045030 - Substrate processing method, substrate processing system and storage medium: [Subject In a plasma process using an ammonia gas after conducting a plasma process by using a process gas containing fluorine and carbon to a silicone-containing substrate, an ammonium silicofluoride having toxicity and water absorbancy is formed on the substrate. [Means for Solution]After conducting the plasma process using an ammonia... Agent: Smith, Gambrell & Russell

20080045031 - Plasma etching method and computer readable storage medium: A plasma etching method for plasma-etching an anti-reflective coating formed on a target object includes the step of placing the target object into a processing chamber having a first electrode and a second electrode provided while facing each other, the target object including an etching target film, the anti-reflective coating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080045032 - Method for producing semiconductor device: There is provided a method for producing a semiconductor device which forms a deep hole contact ultra-finely without generating distortion of an opening and Twisting in a contact hole. The method for producing a semiconductor device has the steps of: (a) forming a contact hole 6 in an upper part... Agent: Mcginn Intellectual Property Law Group, PLLC

20080045033 - Stacked structure and patterning method using the same: A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer... Agent: Jianq Chyun Intellectual Property Office

20080045034 - Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral... Agent: Wells St. John P.s.

20080045035 - Etching solution for etching metal layer, etching method using the etching solution, and method of fabricating semiconductor product using the etching solution: A metal etching solution may include nitric acid, hydrochloric acid, organic acid and water. A semiconductor product fabricating method may include forming a seed layer on a substrate with a metal pad, forming a sacrificial layer that may have an opening exposing the seed layer on the substrate with the... Agent: Lee & Morse, P.C.

20080045036 - Via hole forming method: m

20080045037 - Method for producing layers located on a hybrid circuit: This hybrid circuit comprises a substrate (20) and at least one elementary circuit (22) which comprises a first facet and a second facet, being hybridized via this second facet to a facet of the substrate. According to the invention, this facet of the substrate and each elementary circuit are coated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080045038 - Method of forming an insulative film: A method of forming an insulative film includes a step of vacuum laminating an insulative organic material on a substrate that has a peripheral ring electrode formed in a peripheral region of the substrate and a device element(s) formed inside the peripheral region, and has a surface configuration including raised... Agent: Kanesaka Berner And Partners LLP

20080045039 - Method of forming nitride films with high compressive stress for improved pfet device performance: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited... Agent: International Business Machines Corporation Dept. 18g

20080045040 - Laser spike anneal with plural light sources: A semiconductor wafer is preheated in advance of laser annealing by directing focused energy from a first energy source onto a local area of the wafer. High power laser light from a second energy source is then directed onto the preheated local area to further increase the temperature for annealing.... Agent: Banner & Witcoff, Ltd.

20080045041 - Liquid immersion laser spike anneal: A method and apparatus for laser annealing a semiconductor wafer comprises placing a semiconductor wafer in a liquid bath such that at least a portion of the wafer is immersed in the liquid. Laser light is directed through the liquid and onto a surface of the wafer to heat the... Agent: Banner & Witcoff, Ltd.

20080045042 - Method for crystalizing amorphous silicon layer and mask therefor: A method for crystallizing an amorphous silicon layer is provided. (A) A substrate with an amorphous silicon layer thereon is provided. (B) A mask with a mask pattern is provided. The mask pattern includes a first region pattern and a second region pattern in mirror symmetry. (C) The first region... Agent: J C Patents, Inc.

20080038847 - Method of forming dummy pattern: A method for forming a dummy pattern according to the embodiment comprises the step of: for first chip area and second chip area in which devices are formed, forming the dummy pattern formed between a first chip area and a second chip area in a plurality of patterns having various... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080038848 - Apparatus and method for fabricating semiconductor packages: An apparatus for fabricating semiconductor packages may include a thickness measurer configured to measure the thickness of a printed circuit board (PCB); mold dies, clamped to the top and the bottom of the PCB, through which a molding compound may be injected; and a pressure controller configured to control a... Agent: Harness, Dickey & Pierce, P.L.C

20080038849 - Evaluation method of fine pattern, manufacturing method of device having the fine pattern: An evaluation method includes the steps of forming a dummy pattern having a patterned part with the same critical dimension as a minimum critical dimension of an actual device having a fine pattern that is so fine that a probe for a continuity test cannot be connected to both ends... Agent: Kratz, Quintos & Hanson, LLP

20080038850 - Method for manufacturing semiconductor device: A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench,... Agent: Posz Law Group, PLC

20080038851 - Pattern for evaluating electric characteristics, method for evaluating electric characteristics, method for manufacturing semiconductor device and method for providing reliability assurance: An increased area of an element transistor to be evaluated causes an increased leakage current due to a tunnel effect, leading to a reduced accuracy in predicting a TDDB lifetime. A test element group (TEG) 1 is a pattern for evaluating electric characteristics, comprising a plurality of unit transistors T11,... Agent: Mcginn Intellectual Property Law Group, PLLC

20080038852 - Method for manufacturing layered periodic structures: A method of manufacturing a periodic grating structure for a component. The method includes forming first structured layer including a final periodic grating structure of a first material and a second material filling spaces between individual features of the final periodic grating structure, removing the second material using a first... Agent: Fitzpatrick Cella Harper & Scinto

20080038857 - Method of manufacturing nitride-based semiconductor light-emitting device: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas... Agent: Harness, Dickey & Pierce, P.L.C

20080038859 - Method for forming micromachined structure: The invention provides a method of fabricating a micromachined structure, and in particular to a method of forming a micro-electro-mechanical system (MEMS) structure. A thin silicon cantilevered or suspended structure used to make micromachined structures is first formed from a SOI wafer or a bulk silicon wafer, followed by formation... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080038863 - Profiling solid state samples: Methods and apparatus may operate to position a sample, including an imager lens surface, within a processing chamber. Further activities may include creating a layer of reactive material in proximity with the imager lens surface, and exciting a portion of the layer of reactive material in proximity with the imager... Agent: Schwegman, Lundberg & Woessner, P.A.

20080038865 - Method of manufacturing image sensor: Provided is a method of manufacturing an image sensor which may include forming a plurality of photoelectric converters on a semiconductor substrate, forming a silicon nitride (SiN) film on the plurality of photoelectric converters, supplying plasma gas including hydrogen to the SiN film, and performing a heat treatment on the... Agent: Harness, Dickey & Pierce, P.L.C

20080038866 - Method for fabricating active matrix organic electro-luminescence display panel: A method for fabricating an active matrix organic electro-luminescence (OEL) display panel is provided. First, a driving circuit array including a plurality of driving circuits is formed on a substrate. A patterned conductive layer is then formed over the driving circuit array, wherein the patterned conductive layer is electrically coupled... Agent: J C Patents, Inc.

20080038867 - Method for manufacturing a thin film transistor array panel: A method for manufacturing a thin film transistor array panel includes forming a gate electrode, forming a source electrode and a drain electrode opposing each other and separated from each other on the gate electrode, forming a gate insulator on the gate electrode, forming an organic semiconductor on the gate... Agent: Cantor Colburn, LLP

20080038846 - Method of fabricating a capacitor of a memory device: A capacitor of a memory device, and a method of fabricating the same, includes a lower electrode electrically coupled to a doping region of a transistor structure, the lower electrode having a metal electrode and a metal oxide electrode, a ferroelectric layer covering and extending laterally along the lower electrode,... Agent: Lee & Morse, P.C.

20080038853 - Led of side view type and the method for manufacturing the same: A side view type light emitting diode and a method of manufacturing the same are disclosed. The method may include (a) providing lead frames which include a cathode terminal and an anode terminal, (b) forming a reflector which surrounds the lead frames, such that portions of the cathode terminal and... Agent: Knobbe Martens Olson & Bear LLP

20080038854 - Light emitting diode package and fabrication method thereof: The present invention provides a light emitting diode (LED) package and the fabrication method thereof. The LED package includes a lower metal layer, and a first silicon layer, a first insulation layer, a second silicon layer, a second insulation layer, and a package electrode pattern formed in their order on... Agent: Mcdermott Will & Emery LLP

20080038855 - Light-emitting device, light-emitting apparatus, image display apparatus, method of manufacturing light-emitting device, and method of manufacturing image display apparatus: Light-emitting devices, light-emitting apparatuses, image display apparatuses and methods of manufacturing same are provided. The devices and apparatuses include a transparent electrode that is connected directly to light output surfaces so as to cover the whole areas of the light output surfaces. The transparent electrode is formed to be larger... Agent: Bell, Boyd & Lloyd, LLP

20080038856 - Semiconductor device and method of fabricating the same: The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in... Agent: Nixon Peabody, LLP

20080038858 - Methods of fabricating group iii nitride based light emitting diode structures with a quantum well and superlattice, group iii nitride based quantum well structures and group iii nitride based superlattice structures: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well stricture. The quantum well structure includes a first Group III nitride based barrier layer, a Group III... Agent: Myers Bigel Sibley & Sajovec, P.A.

20080038860 - Dielectric actuator or sensor structure and method of making it: The present invention relates to dielectric actuators or sensors of the kind wherein electrostatic attraction between two electrodes located on an elastomeric body leads to a compression of the body in a first direction and a corresponding extension of the body in a second direction. The dielectric actuator/sensor structure comprises... Agent: Mccormick, Paulding & Huber LLP

20080038861 - Support with integrated deposit of gas absorbing material for manufacturing microelectronic microoptoelectronic or micromechanical devices: The specification teaches a device for use in the manufacturing of microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In a preferred embodiment the invention includes a mechanical supporting base, and a layer of a gas absorbing or... Agent: Technology & Intellectual Property Strategies Group PC (dba Tips Group)

20080038862 - Microlens, an image sensor including a microlens, method of forming a microlens and method for manufacturing an image sensor: A microlens, an image sensor including the microlens, a method of forming the microlens and a method of manufacturing the image sensor are provided. The microlens includes a polysilicon pattern, having a cylindrical shape, formed on a substrate, and a round-type shell portion enclosing the polysilicon pattern. The microlens may... Agent: Harness, Dickey & Pierce, P.L.C

20080038864 - Method of manufacturing image sensor: A method of manufacturing an image sensor includes forming a device isolation region in an active pixel sensor area of a semiconductor substrate and alignment keys in a scribe lane area of the semiconductor substrate, such that the depth of the alignment keys is equal to or shallower than the... Agent: F. Chau & Associates, LLC

20080038868 - Process for packaging components, and packaged components: A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20080038869 - High performance system-on-chip using post passivation process: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... Agent: Mou-shiung Lin

20080038871 - Multipath soldered thermal interface between a chip and its heat sink: The invention comprises a process for joining a first surface and a second surface where the first surface comprises an initially non-solderable surface which comprises coating the first surface with a solder-adhesion layer to produce a solder-adhesion layer on the first surface and providing a Thermal Interface Material (“TIM”) composition... Agent: The Law Offices Of Robert J. Eichelburg

20080038870 - Thermal method to control underfill flow in semiconductor devices: A method and apparatus for assembling a semiconductor device. A chip (901) with solder bodies (903) on its contact pads is flipped onto a substrate (904). After the reflow process, a gap (910) spaces chip and substrate apart. A polymer precursor is selected for its viscosity of known temperature dependence.... Agent: Texas Instruments Incorporated

20080038872 - Method of manufacturing semiconductor device: Provided are a semiconductor device capable of mounting a plurality of semiconductor chips in compact on a leadframe and reducing manufacturing costs, and a method of manufacturing the same. The semiconductor device includes: a semiconductor chip (20) having a top surface (20a) provided with a plurality of electrode pads (22)... Agent: Mcginn Intellectual Property Law Group, PLLC

20080038873 - Apparatus and method for manufacturing semiconductor device: An apparatus for manufacturing a semiconductor device is provided. The semiconductor device includes a chip packaged with a resin mold. The apparatus includes a first mold, a second mold, and a buffer sheet. The first mold has a first cavity for forming the resin mold on a first side of... Agent: Posz Law Group, PLC

20080038874 - Chip package and method for fabricating the same: A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next... Agent: Megica Corporation

20080038875 - Physical quantity sensor, lead frame, and manufacturing method therefor: A physical quantity sensor is constituted using a lead frame having at least one stage and a plurality of leads whose bases are arranged in the same plane, wherein at least one physical quantity sensor chip having a plurality of electrode pads is mounted on the stage and is inclined... Agent: Dickstein Shapiro LLP

20080038876 - Method and system for sealing a substrate: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate a... Agent: Knobbe, Martens, Olson & Bear, LLP

20080038877 - Light-weight flash hard drive with plastic frame: A light-weight flash hard drive includes a printed circuit board assembly (PCBA) mounted in a housing formed by a plastic frame and a pair of metal panels that are mounted on the plastic frame over the PCBA. The PCBA includes a PC board and a plug connector that is mounted... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20080038878 - Encapsulation circuitry on a substrate: An assembly for a circuit board includes a substrate, at least one circuit component formed on the substrate, and a frame. The frame comprises a first substantially planar surface attached to the substrate, and a hole formed through the frame and defined by a wall that surrounds the at least... Agent: Medtronic, Inc.

20080038879 - Split-channel antifuse array architecture: An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080038880 - Method of manufacturing a semiconductor device: There is the need to grind a semiconductor substrate from its back surface in order to thin a drift region for forming the NPT type IGBT. A collector region is then formed on the back surface of the semiconductor substrate by performing ion-implantation, a heat treatment and the like to... Agent: Morrison & Foerster LLP

20080038881 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor array panel according to an embodiment of the present invention includes a gate electrode, a source electrode and a drain electrode opposing each other and separated from each other on the gate electrode. An organic semiconductor is in contact with the source electrode and the drain... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080038882 - Thin-film device and method of fabricating the same: A thin-film device includes a first electrical insulator, an oxide-semiconductor film formed on the first electrical insulator, and a second electrical insulator formed on the oxide-semiconductor film, the oxide-semiconductor film defining an active layer. The oxide-semiconductor film is comprised of a first interface layer located at an interface with the... Agent: Scully Scott Murphy & Presser, PC

20080038883 - Method for manufacturing semiconductor device utilizing recrystallized semiconductor film formed on an insulating film: A method for manufacturing a semiconductor device, the method comprising: forming a semiconductor device using a crystalline semiconductor film after the surface of the crystalline semiconductor film with two plane directions or more is treated by chemical mechanical polishing, wherein an alkali solution with a hydrogen ion concentration of PH... Agent: Oliff & Berridge, PLC

20080038884 - Method of fabricating thin film transistor array substrate: A method of fabricating a TFT array substrate that prevents mobile ions from moving from a photoresist to channels of the TFT by the gate electrode of the TFT by performing photolithography processes for ion injection after forming gate electrode of TFT and, in addition, a method of fabricating a... Agent: Robert E. Bushnell

20080038885 - Method of fabricating a thin film transistor array panel: A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be... Agent: Macpherson Kwok Chen & Heid LLP

20080038886 - Stress enhanced mos circuits and methods for their fabrication: A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080038887 - Method for fabricating semiconductor mos device: A method of making a transistor device having silicided source/drain is provided. A gate electrode is formed on a substrate with a gate dielectric layer therebetween. A spacer is formed on sidewalls of the gate electrode. A source/drain is implanted into the substrate. A pre-amorphization implant (PAI) is performed to... Agent: North America Intellectual Property Corporation

20080038888 - Integrated circuit arrangement with capacitor and fabrication method: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the... Agent: Brinks Hofer Gilson & Lione Infineon

20080038889 - Fin structure and method of manufacturing fin transistor adopting the fin structure: Provided are a fin structure and a method of manufacturing a fin transistor adopting the fin structure. A plurality of mesa structures including sidewalls are formed on the substrate. A semiconductor layer is formed on the mesa structures. A capping layer is formed on the semiconductor layer. Thus, the semiconductor... Agent: Harness, Dickey & Pierce, P.L.C

20080038890 - Method for improved trench protection in vertical umosfet devices: A method of forming a self-aligned protective layer within a UMOSFET device includes forming a trench within an upper surface of a drift layer, the drift layer of a first polarity type, and epitaxially growing a protective layer on a bottom surface of the trench, the protective layer comprising dopant... Agent: General Electric Company Global Research

20080038891 - High voltage mosfet having si/sige heterojunction structure and method of manufacturing the same: Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a... Agent: Ladas & Parry LLP

20080038892 - Semiconductor device having an under stepped gate for preventing gate failure and method of manufacturing the same: A semiconductor device and a method of manufacturing the same capable of preventing a not open fail of a landing plug contact caused by the leaning of a gate. The method includes the steps of preparing a semiconductor substrate, forming first recesses by etching an active area of the semiconductor... Agent: Ladas & Parry LLP

20080038893 - Reverse metal process for creating a metal silicide transistor gate structure: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting... Agent: Dickstein Shapiro LLP

20080038894 - Electronic beam processing device and method using carbon nanotube emitter: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated... Agent: Schwegman, Lundberg & Woessner, P.A.

20080038895 - Capacitor of semiconductor device and method of manufacturing the same: A MIM capacitor includes a lower electrode disposed on a semiconductor substrate. A dielectric layer is disposed on the lower electrode to completely cover an exposed surface of-the lower electrode. An upper electrode is disposed on the dielectric layer. A method for forming a MIM capacitor includes forming a lower... Agent: Lowe Hauptman Ham & Berner, LLP

20080038896 - Methods for etching doped oxides in the manufacture of microfeature devices: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method... Agent: Perkins Coie LLP Patent-sea

20080038897 - Method of manufacturing a semiconductor device: A semiconductor-device manufacturing method includes forming an element separating insulating film on a semiconductor substrate; forming a gate multilayer film for forming a gate electrode thereon; removing the gate multilayer film in an alignment mark forming area positioned on the element separating insulating film; forming a pattern of a first... Agent: Scully Scott Murphy & Presser, PC

20080038898 - Structure and method for mixed-substrate simox technology: The present invention provides a semiconductor structure that includes a substrate having a crystal lattice; a first structure formed in a first region of the substrate, the first structure includes at least a heterostructure that generates a lattice stress in said crystal lattice in the first region; and a second... Agent: Scully, Scott, Murphy & Presser, P.C.

20080038899 - Method of manufacturing a flash memory device: A method of manufacturing a flash memory device includes the steps of forming a tunnel oxide layer and a polysilicon layer over a semiconductor substrate. An etch process is then performed to form a pattern and a trench. An isolation layer is formed in the trench. A polysilicon spacer layer... Agent: Marshall, Gerstein & Borun LLP

20080038900 - Methods for surface activation by plasma immersion ion implantation process utilized in silicon-on-insulator structure: Methods for promoting interface bonding energy utilized in SOI technology are provided. In one embodiment, the method for promoting interface bonding energy includes providing a first substrate and a second substrate, wherein the first substrate has a silicon oxide layer formed thereon and a cleavage plane defined therein, performing a... Agent: Patterson & Sheridan, LLP

20080038901 - Controlled process and resulting device: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define... Agent: Townsend And Townsend And Crew, LLP

20080038902 - Semiconductor bonding and layer transfer method: The present invention provides a method of coupling substrates together. The method includes providing first and second substrates and then coupling the first and second substrates together. One of the first and second substrates includes devices with an interconnect region positioned thereon and the other substrate carries a device structure.... Agent: Schmeiser Olsen & Watts

20080038903 - Semiconductor wafer holding method, semiconductor wafer holding apparatus and semiconductor wafer holding structure: On a back face of a semiconductor wafer, an annular convex portion is formed at an outer periphery so as to surround a flat concave portion formed by back grinding. The back face of the semiconductor wafer is pressed against an adhesive surface of a supporting adhesive tape joined to... Agent: Rader Fishman & Grauer PLLC

20080038904 - Method and device for handling an article in the course of semiconductor fabrication: The invention relates inter alia to a method and apparatus for handling an article in semiconductor fabrication. For example, the method includes handling the article by completely separating the article from a gripper by a frozen liquid.... Agent: Slater & Matsil, L.L.P.

20080038905 - Method of forming hfsin metal for n-fet applications: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20080038906 - Method for producing p-type ga2o3 film and method for producing pn junction-type ga2o3 film: Disclosed are a method for producing a p-type Ga2O3 film and a method for producing a pn junction-type Ga2O3 film which enable to form a thin film composed of a high-quality Ga2O3 compound semiconductor. Specifically, the pressure in a vacuum chamber (52) is reduced, and while introducing oxygen radicals, a... Agent: Mcginn Intellectual Property Law Group, PLLC

20080038907 - Method for fabricating non-volatile memory device: A method for manufacturing a non-volatile memory device is provided, including the step of performing an ion implantation process to form an impurity area in a field oxide area formed on a substrate, where the ion implantation process is performed at least two times while varying ion implantation angles relative... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080038908 - Method and system for continuous large-area scanning implantation process: A method for manufacturing doped substrates using a continuous large area scanning implantation process is disclosed. In one embodiment, the method includes providing a movable track member. The movable track member is provided in a chamber. The chamber includes an inlet and an outlet. In a specific embodiment, the movable... Agent: Townsend And Townsend And Crew, LLP

20080038909 - Method of fabricating lateral double diffused metal oxide semiconductor field effect transistor: Provided is a method of fabricating a lateral double diffused MOSFET. In the method, ions are implanted onto a substrate to form a body region of the LDMOS transistor using a photoresist pattern as an ion implantation mask. Herein, the photoresist can be patterned to have a slope of with... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080038910 - Multiple lithography for reduced negative feature corner rounding: Corner rounding of negative features is reduced by etching a targeted opening defined by the intersection of a hard mask opening and a photoresist mask opening. Embodiments include forming a hard mask over an underlayer in which the targeted opening is to be formed in a targeted area, forming a... Agent: Mcdermott Will & Emery LLP

20080038911 - Method for manufacturing semiconductor device: The invention is directed to a method for manufacturing a field plate of a high voltage device. The field plate is located on a drift region of a substrate, wherein an isolation structure is located on the drift region. The method comprises steps of forming a first dielectric layer over... Agent: Jianq Chyun Intellectual Property Office

20080038912 - Interconnect for improved die to substrate electrical coupling: A method is provided for forming peripheral contacts between a die and a substrate. In accordance with the method, a die (305) is provided which has first and second opposing major surfaces, wherein the first major surface is attached to a substrate (303) having a first group (323) of contact... Agent: Fortkort & Houston P.C.

20080038913 - Methods of forming aluminum-free wire bond pad and pad so formed: Methods of forming an aluminum-free wire bond pad and the pad so formed are disclosed. In one embodiment, the method includes forming an opening through a dielectric layer to a last metal of a chip; forming a tantalum nitride (TaN) layer over the chip and over the opening; removing the... Agent: Hoffman, Warnick & D'alessandro LLC

20080038914 - Semiconductor element and manufacturing method thereof: In a semiconductor element, if a crack is generated inside a bonding pad, the crack does not propagate inside the semiconductor element. The semiconductor element has an electrode on a surface thereof. A wiring layer is formed inside the semiconductor element. A conductive layer is formed separate from the wiring... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080038915 - Device and methodology for reducing effective dielectric constant in semiconductor devices: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.... Agent: Greenblum & Bernstein, P.L.C

20080038916 - Method for the production of planar structures: A method for the production of a planar structure is disclosed. The method comprises producing on a substrate a plurality of structures of substantially equal height, and there being a space in between the plurality of structures. The method further comprises providing a fill layer of electromagnetic radiation curable material... Agent: Knobbe Martens Olson & Bear LLP

20080038917 - Multilayer hardmask scheme for damage-free dual damascene processing of sicoh dielectrics: Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080038918 - Semiconductor device and method for manufacturing the same: A semiconductor device has multi-layered interlayer insulating layers 3 formed on a semiconductor substrate 1, and wirings 4 formed in the interlayer insulating layers 3. The interlayer insulating layers 3 are composed of porous bodies having fine columnar pores and parent-material regions consisting mainly of silicon oxides surrounding the fine... Agent: Fitzpatrick Cella Harper & Scinto

20080038919 - Plasma sputtering film deposition method and equipment: The present invention relates to a technology for depositing a thin metal film by using a plasma sputtering technique on a top surface of a target object, e g a semiconductor wafer or the like, and on a surface of a recess opened at the top surface The film deposition... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080038920 - System and method of selectively depositing ruthenium films by digital chemical vapor deposition: A chemical vapor deposition reaction system converts a reactant precursor, which includes the metal Ruthenium, to a vapor during a chemical reaction in order to deposit the metal on a semiconductor wafer. The reactant precursor is Bis(2,2,6,6-tetramethyl-3,5-heptanedionato)(1,5-cyclooctadiene)Ru. An energy source provides energy to the reaction chamber to induce the chemical... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080038921 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device. In this method, a concave portion is formed in one surface in the thickness direction of a primary base plate comprising a semiconductor substrate with a relatively large thickness dimension. Then, through-holes are formed by a reactive-ion etching process using as a mask... Agent: Greenblum & Bernstein, P.L.C

20080038922 - Etch-stop layer and method of use: An etch-stop layer and method of use is disclosed.... Agent: Kathy Manke Avago Technologies Limited

20080038923 - Device and methodology for reducing effective dielectric constant in semiconductor devices: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning... Agent: Greenblum & Bernstein, P.L.C

20080038924 - Highly-selective metal etchants: A highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is described. In one embodiment, the wet etchant is utilized to pattern a metal layer in a semiconductor structure. In another embodiment, a highly selective metal wet... Agent: Blakely Sokoloff Taylor & Zafman

20080038926 - Method of treating a mask layer prior to performing an etching process: A method of pre-treating a mask layer prior to etching an underlying thin film is described. A thin film, such as a dielectric film, is etched using plasma that is enhanced with a ballistic electron beam. In order to reduce the loss of pattern definition, such as line edge roughness... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080038927 - Method for multi-layer resist plasma etch: A method for etching a multi-layer resist defined over a substrate in a plasma etch chamber is provided. The method initiates with introducing the substrate having a pattern defined on a first layer of the multi-layer resist into the etch chamber. SO2 gas flows into the etch chamber and a... Agent: Martine Penilla & Gencarella, LLP

20080038925 - Methods and apparatus for igniting a low pressure plasma: In a plasma processing system having a plasma processing chamber, at least one powered electrode and an ignition electrode, a method for igniting a plasma is disclosed. The method includes introducing a substrate into the plasma processing chamber. The method also includes flowing a gas mixture into the plasma processing... Agent: Ipsg, P.C.

20080038928 - Electron beam etching device and method: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated... Agent: Schwegman, Lundberg & Woessner, P.A.

20080038929 - Method of dry etching oxide semiconductor film: Provided is a dry etching method for an oxide semiconductor film containing at least In, Ga, and Zn, which includes etching an oxide semiconductor film in a gas atmosphere containing a halogen-based gas.... Agent: Fitzpatrick Cella Harper & Scinto

20080038930 - Method of ashing an object and apparatus for performing the same: Example embodiments relate to a method and an apparatus of ashing an object. The method may include converting a first reaction fluid into plasma, reacting the plasma with a second reaction fluid to generate radicals, and ashing the object using the radicals and the plasma.... Agent: Lee & Morse, P.C.

20080038931 - Method of manufacturing a capacitor deep trench and of etching a deep trench opening: A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is... Agent: North America Intellectual Property Corporation

20080038932 - Method for selective etching: Method of selectively etching a first material on a substrate with a high selectivity towards a second material by flowing a liquid etchant across a substrate surface at a flow sufficiently fast to generate a minimum mean velocity parallel to the substrate's surface, wherein the first material is selected from... Agent: Young & Thompson

20080038933 - Plasma and electron beam etching device and method: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated... Agent: Schwegman, Lundberg & Woessner, P.A.

20080038935 - Aperture masks for circuit fabrication: Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circuit elements for electronic displays and low-cost integrated circuits such as radio frequency... Agent: 3m Innovative Properties Company

20080038934 - Materials and methods of forming controlled void: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removale of the porogen material in the composite layer to form a porous... Agent: Air Products And Chemicals, Inc. Patent Department

20080038936 - Method to form ultra high quality silicon-containing compound layers: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon... Agent: Knobbe, Martens, Olsen & Bear LLP

20080038937 - Method for reducing hot carrier effect of mos transistor: A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and the dielectric layer, and covers the source/drain region, the spacer and the... Agent: Jianq Chyun Intellectual Property Office

20080032424 - Ald of zr-substituted batio3 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a zirconium substituted layer of barium titanium oxide (BaTiO3), produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared... Agent: Schwegman, Lundberg & Woessner, P.A.

20080032425 - Method of assembling displays on substrates: Various embodiments of methods and systems for designing and constructing displays from multiple light-modulating elements are disclosed. Display elements having different light-modulating and self-assembling characteristics may be used during display assembly and operation.... Agent: Searete LLC Clarence T. Tegreene

20080032427 - Ion analysis system based on analyzer of ion energy distribution using retarded electric field: An ion analysis system to measure ion energy distribution at several points during a process of manufacturing a semiconductor circuit includes at least two ion flux sensors combined in a single system to measure an ion energy distribution function, each of the ion flux sensors having cells including an opening... Agent: Stanzione & Kim, LLP

20080032429 - Methods, defect review tools, and systems for locating a defect in a defect review process: Methods, defect review tools, and systems for locating a defect in a defect review process are provided. One method includes acquiring one or more images and data from an inspection tool. The one or more images illustrate an area on a specimen in which a defect to be reviewed is... Agent: Baker & Mckenzie LLP

20080032431 - Method for fabricating a system for displaying images: The invention provides a method for manufacturing systems for displaying images. A representative system incorporates electroluminescent devices, comprising the following steps. A substrate having an active region and a pad region is provided. A thin film transistor is formed on the active region and a pad electrode is formed on... Agent: Liu & Liu

20080032434 - Method for making a light emitting diode by electroless plating: One embodiment of the invention relates to a method of manufacturing a light emitting diode. The method includes forming an insulating layer on an area, not covered by a seed layer, of at least one of a p-type semiconductor layer and an n-type semiconductor layer, wherein the impurity concentration varies... Agent: Bacon & Thomas, PLLC

20080032435 - Method for manufacturing semiconductor laser element: The method for manufacturing a semiconductor laser element according to the present invention has the steps of: forming a semiconductor laminated structure having an active layer composed of a semiconductor material containing Al; etching the semiconductor laminated structure to form a mesa; forming a first burying layer at a first... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080032437 - Exposure method for upper layer of hole of semiconductor device: An exposure method executed after processing a hole in a substrate of a semiconductor device, has an exposure step of transferring a pattern on a mask onto an upper layer of the hole and forming a wiring groove by exposure, wherein a quantity of exposure with which a wiring groove... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080032438 - Image sensor and method of manufacturing the same: An image sensor and a method of manufacturing the same, in which, a planarized layer is formed on a semiconductor substrate including a pixel array region, an optical black region, and a logic region to cover a photo sensing unit array in the pixel array region, a patterned metal layer... Agent: North America Intellectual Property Corporation

20080032439 - Selective etching of mems using gaseous halides and reactive co-etchants: A method for etching a target material in the presence of a structural material with improved selectivity uses a vapor phase etchant and a co-etchant. Embodiments of the method exhibit improved selectivities of from at least about 2-times to at least about 100-times compared with a similar etching process not... Agent: Knobbe, Martens, Olson & Bear, LLP

20080032440 - Organic semiconductor device and method of fabricating the same: An organic semiconductor device is provided. A conductive gate layer and a gate dielectric layer are formed on a substrate. Patterned metal layers are formed on the gate dielectric layer beside the conductive gate layer. An electrode modified layer is formed on a top surface and sidewall of each of... Agent: Jianq Chyun Intellectual Property Office

20080032426 - Methods and systems for controlling critical dimensions in track lithography tools: A method of controlling wafer critical dimension (CD) uniformity on a track lithography tool includes obtaining a CD map for a wafer. The CD map includes a plurality of CD data points correlated with a multi-zone heater geometry map. The multi-zone heater includes a plurality of heater zones. The method... Agent: Townsend And Townsend And Crew, LLP

20080032428 - Method and system for line-dimension control of an etch process: A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature... Agent: Schmeiser, Olsen & Watts

20080032430 - Light emitting device and manufacturing method thereof: In a light emitting device, it is preferable that a surface of a film below a light-emitting element has flatness. Therefore, treatment such as planarization of a surface of a film is performed after forming the film. The present invention proposes a structure of a light-emitting device that can make... Agent: Nixon Peabody, LLP

20080032432 - Composition for stripping photoresist and method for manufacturing thin transistor array panel using the same: The present invention provides a photoresist stripper including about 5 wt % to about 20 wt % alcohol amine, about 40 wt % to about 70 wt % glycol ether, about 20 wt % to about 40 wt % N-methyl pyrrolidone, and about 0.2 wt % to about 6 wt... Agent: F. Chau & Associates, LLC

20080032433 - Reflective liquid crystal display device and fabricating method thereof: A method of fabricating a reflective liquid crystal display device includes forming a gate line on a substrate having first and second pixel regions, forming a data line crossing the gate line and defining the pixel regions, forming a thin film transistor connected to the gate line and the data... Agent: Morgan Lewis & Bockius LLP

20080032436 - Light emitting diode and method of fabricating the same: A light emitting diode (LED) and a method are provided for fabricating the a LED with an improved structure for better light emitting efficiency and better light output performance. The LED includes an n-GaN layer formed on a substrate to have a plurality of protrusions, thereby having an uneven surface,... Agent: Buchanan, Ingersoll & Rooney PC

20080032442 - Novel compound and method for synthesizing the same, ink, ink cartridge, recording unit, ink-jet recording apparatus, recording method, liquid composition, pattern generating method, article, environmental history-detecting method: Provided is a solubility-controllable compound being soluble in a solvent due to a solvent-philic group thereof, of which solubility in the solvent is irreversibly lowered when the group is removed by retro-Diels-Alder reaction.... Agent: Fitzpatrick Cella Harper & Scinto

20080032441 - Organic thin-film transistor and manufacturing method thereof: Disclosed are an organic thin-film transistor and a manufacturing method thereof, the organic thin-film transistor comprising a support and provided thereon, a gate electrode, an insulation layer, a source electrode, a drain electrode, and an organic semiconductor layer, the support comprising at least one of resins, and the organic semiconductor... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080032444 - Fabricating amorphous zinc oxide semiconductor layer: A process for fabricating a semiconductor layer of an electronic device including: liquid depositing one or more zinc oxide precursor compositions and forming at least one semiconductor layer of the electronic device comprising predominately amorphous zinc oxide from the liquid deposited one or more zinc oxide precursor compositions.... Agent: Patent Documentation Center

20080032443 - Fabricating zinc oxide semiconductor using hydrolysis: A process for fabricating at least one semiconductor layer of an electronic device including: performing on a composition including a hydrolyzable zinc compound a number of activities including: (a) hydrolyzing at least a portion of the hydrolyzable zinc compound to form zinc oxide; (b) liquid depositing; and (c) optionally heating,... Agent: Patent Documentation Center

20080032445 - High voltage metal oxide semiconductor device and fabricating method thereof: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is... Agent: Jianq Chyun Intellectual Property Office

20080032446 - combination heat dissipation device with termination and a method of making the same: An integrated circuit assembly including an integrated circuit device electrically connected to a signal line, and method of making the same. The invention also includes a heat dissipation device thermally coupled to the integrated circuit device and a termination resistor electrically connected to the signal line and the heat dissipation... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080032447 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality of through holes in a substrate with the through holes arranged in arrays, and attaching a plurality of singulated microelectronic dies to the substrate with an active side of... Agent: Perkins Coie LLP Patent-sea

20080032448 - Semiconductor device with stacked chips and method for manufacturing thereof: A semiconductor device includes a first semiconductor device and a second semiconductor device. Through-holes in the second semiconductor device extend from an upper side of the second semiconductor device adjacent contact pads to a bottom side of the second device. Tower contact bumps are electrically connected to contact pads of... Agent: Slater & Matsil LLP

20080032450 - Method for fabricating chip-stacked semiconductor package: A chip-stacked semiconductor package and a method for fabricating the same are proposed. A chip carrier module plate including a plurality of chip carriers, and a heat sink module plate including a plurality of heat sinks are provided, wherein a plurality of through holes are formed around each of the... Agent: Edwards Angell Palmer & Dodge LLP

20080032449 - Stacked die in die bga package: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20080032451 - Method of providing inverted pyramid multi-die package reducing wire sweep and weakening torques: An inverted pyramid multi-die package provides, for each die pad on an upper die, a rigid support underneath extending to a substrate. Such configuration reduces both the wire sweep and weakening torques. A lower die, smaller than the upper die in at least one dimension, may be positioned between the... Agent: Mark M. Friedman

20080032452 - Chip scale package and method for manufacturing the same: A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080032453 - Method of manufacturing a semiconductor device: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is... Agent: Miles & Stockbridge PC

20080032454 - Thermally enhanced bga package substrate structure and methods: Methods for preparing thermally enhanced multilayer substrates and methods for their use in assembling BGA packages are disclosed. Steps in preferred embodiments of the invention include opening a hole in a dielectric material at one surface of a multilayer substrate thereby forming a die pad on the second metal layer... Agent: Texas Instruments Incorporated

20080032455 - Reliability enhancement process: A method of packaging a semiconductor component with a printed wiring board is disclosed. The method includes determining a first distance, applying a thin film onto a surface of the semiconductor component such that the thin film is spaced apart from a support of the semiconductor, applying a solder pad... Agent: Michael Best & Friedrich LLP

20080032456 - Integrated circuit package system with down-set die pad: An integrated circuit package system includes a substrate, a down-set conductive die pad on the substrate, and an integrated circuit over the down-set conductive die pad.... Agent: Law Offices Of Mikio Ishimaru

20080032457 - Structure and method of making sealed capped chips: A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces... Agent: Tessera Lerner David Et Al.

20080032459 - Mold compound cap in a flip chip multi-matrix array package and process of making same: A molding compound cap structure is disclosed. A process of forming the molding compound cap structure is also disclosed. A microelectronic package is also disclosed that uses the molding compound cap structure. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes... Agent: Blakely Sokoloff Taylor & Zafman

20080032458 - Semiconductor device and method of manufacturing same: The present invention provides a semiconductor device capable of improving productivity while maintaining electrical characteristics, and a manufacturing method thereof. One characteristic point of the present invention is that a plating processing condition (A) for forming a metal wiring layer (redistribution wiring) corresponding to a first conductive layer and a... Agent: Rabin & Berdo, P.C.

20080032460 - Programmable random logic arrays using pn isolation: Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of... Agent: Scully, Scott, Murphy & Presser, P.C.

20080032461 - Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density: An LED display assembly, comprising a grid of electrical conductors; light emitting diodes in association with the grid and in electrical communication with the conductors that provide power for LED operation, the grid operable to receive heat from the diodes during diode operation, and the array configured for passing coolant... Agent: William W. Haefliger

20080032462 - Low capacitance two-terminal barrier controlled tvs diodes: A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the... Agent: Tyco Electronics Corporation

20080032463 - Semiconductor memory device: A method of forming a circuit includes providing a substrate; providing an interconnect region positioned on the substrate; bonding a device structure to a surface of the interconnect region; and processing the device structure to form a first stack of layers on the interconnect region and a second stack of... Agent: Schmeiser Olsen & Watts

20080032465 - Deposition of zraion films: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and... Agent: Schwegman, Lundberg & Woessner, P.A.

20080032464 - Memory cell system with nitride charge isolation: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a first intermediate layer over the first insulator layer, forming a charge trap layer over the first intermediate layer, forming a second intermediate layer over the charge trap layer, and forming a second... Agent: Law Offices Of Mikio Ishimaru

20080032466 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a silicon layer pattern in a Silicon-on-Insulator (“SOI”) semiconductor substrate to define an active region, selectively patterning an insulating film in the SOI semiconductor substrate by using a gate mask to form an under-cut space under the silicon layer pattern, and... Agent: Townsend And Townsend And Crew, LLP

20080032467 - Integrated circuit with metal heat flow path coupled to transistor and method for manufacturing such circuit: In some embodiments, a chip with a metal heat flow path extending between a terminal of a transistor thereof and bulk semiconductor material of the chip (e.g., from the terminal to a substrate over which the transistor is formed or to the body of a semiconductor device adjacent to the... Agent: Girard & Equitz LLP

20080032468 - Mos transistor and fabrication thereof: A method of fabricating a MOS transistor is described. A substrate is provided, and then a composite layer for forming a gate structure and a carbon-containing mask material layer are formed thereon in turn, wherein the carbon-containing mask material layer is formed with a carbon-containing precursor gas and a reaction... Agent: J C Patents, Inc.

20080032469 - Semiconductor devices having a field effect transistor and methods of fabricating the same: A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer.... Agent: Marger Johnson & Mccollom, P.C.

20080032470 - Method for fabricating non-volatile memory: A method for fabricating non-volatile memory on a substrate includes forming a plurality of doped lines in the substrate along a first direction, wherein the doped lines serve as a plurality of bit lines, and portions of each of the doped lines serves as source/drain regions for a plurality of... Agent: Jianq Chyun Intellectual Property Office

20080032471 - Methods for forming shallow trench isolation structures in deep trenches and uses of the same: A method for manufacturing a shallow trench isolation structure in a deep trench and application thereof are provided, wherein the deep trench having an upper electrode and an insulation layer on the upper electrode is formed in a substrate which has a pad insulation layer. The method comprises the following... Agent: Nixon Peabody LLP - Patent Group

20080032472 - Methods for improving uniformity of cap layers: A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing... Agent: Slater & Matsil, L.L.P.

20080032473 - Method and apparatus for charging partitioned capacitors: One aspect of this disclosure relates to an apparatus for providing a selective capacitance. An embodiment of the apparatus includes a first and second capacitor in a stack, and a switching circuit connected between the first and second capacitors. The switching circuit has at least two states, and is adapted... Agent: Schwegman, Lundberg & Woessner, P.A.

20080032474 - Semiconductor memory device and semiconductor memory device manufacturing method: This disclosure concerns a method of manufacturing a semiconductor memory device comprising forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080032475 - Memory cell system with gradient charge isolation: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer having a gradient of a silicon above and below the charge trap layer over the first insulator layer, and forming a second insulator layer over the charge trap layer.... Agent: Law Offices Of Mikio Ishimaru

20080032476 - Method for fabricating recessed-gate mos transistor device: A method of fabricating gate trench utilizing pad pullback technology is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad layer is provided. Trench capacitors are formed in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO)... Agent: North America Intellectual Property Corporation

20080032477 - Semiconductor device and method for manufacturing same: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor... Agent: Mcginn Intellectual Property Law Group, PLLC

20080032478 - Stacking fault and twin blocking barrier for integrating iii-v on si: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of... Agent: Intel/blakely

20080032479 - Semiconductor device with constricted current passage: A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the source/drain region.... Agent: Hitt Gaines, PC Lsi Corporation

20080032480 - Semiconductor structures including vertical diode structures and methods of making the same: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the... Agent: Trask Britt, P.C./ Micron Technology

20080032481 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor structure formed above the semiconductor substrate and comprising a first electrode, a second electrode provided below the first electrode, a third electrode provided below the second electrode, a first dielectric film provided between the first electrode and the second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080032482 - Isolation structures and methods of fabricating isolation structures: A method of forming an isolation structure includes the steps of: (a) forming an opening within a substrate; (b) forming a substantially conformal layer comprising tetraethoxysilane (TEOS) layer along the opening; and (c) forming a dielectric layer over the TEOS layer, the dielectric layer substantially filling the opening.... Agent: Duane Morris LLPIPDepartment (tsmc)

20080032483 - Trench isolation methods of semiconductor device: In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A... Agent: Mills & Onello LLP

20080032485 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device can suppress the generation of burrs when an array of integrated circuits to which a supporting member is bonded for assistance is separated into chips. The supporting member having thinned regions (or void regions which are openings in the supporting member) located correspondingly... Agent: Nixon & Vanderhye, PC

20080032484 - Substrate bonding process with integrated vents: m

20080032486 - Semiconductor wafer and manufacturing method thereof: A semiconductor wafer manufacturing method comprising the steps of preparing a first semiconductor wafer having a plurality of cuts formed at edge portions in crystal directions, preparing a second semiconductor wafer having a cut formed at an edge portion in a crystal direction that is different from the crystal direction... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080032487 - Semiconductor wafer and manufacturing method thereof: A semiconductor wafer manufacturing method comprising the steps of preparing first and second semiconductor wafers, bonding a main surface of said second semiconductor wafer to a main surface of said first semiconductor wafer, thinning said first semiconductor wafer, implanting oxygen ions from said first semiconductor wafer side into a neighborhood... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080032488 - Method of separating semiconductor dies: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, a seed metal layer may be used to grow hard metal layers above it for handling. Metal may be plated above these metal layers everywhere except... Agent: Patterson & Sheridan, L.L.P.

20080032489 - Removable wafer expander for die bonding equipment: A removable wafer expander for die bonding equipment for a singularized wafer supported by a flexible sticky substrate, the removable wafer expander provided with a first ring member to be coupled with a second ring member for remote expansion of the flexible sticky substrate therebetween before the mounting of the... Agent: Seed Intellectual Property Law Group PLLC

20080032490 - Nanocylinder arrays: Pathways to rapid and reliable fabrication of nanocylinder arrays are provided. Simple methods are described for the production of well-ordered arrays of nanopores, nanowires, and other materials. This is accomplished by orienting copolymer films and removing a component from the film to produce nanopores, that in turn, can be filled... Agent: Fish & Richardson PC

20080032491 - Wafer backside particle removal for track tools: An apparatus for removing one or more backside particles from a semiconductor substrate. The apparatus includes a substrate support member adapted to support the semiconductor substrate. The substrate has a substrate diameter, a substrate frontside, and a substrate backside. The apparatus also includes a curing ring having an annular shape... Agent: Townsend And Townsend And Crew, LLP

20080032492 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device including at least one of the following steps: Forming a poly-silicon layer on a semiconductor substrate. Forming a plurality of photo-resist patterns on the poly-silicon layer to be spaced apart from each other by a predetermined distance. Forming a spacer oxidation film... Agent: Sherr & Nourse, PLLC

20080032493 - Semiconductor device: A semiconductor device includes a fuse wire, a portion to be fused that overlies the fuse wire with an insulation film interposed therebetween, and a plug connecting the portion to be fused and the fuse wire together. The portion to be fused underlies an insulation film having a thickness, and... Agent: Mcdermott Will & Emery LLP

20080032495 - Ball transferring method and apparatus: Balls are sucked onto a carrier board so as to be temporarily arranged in a ball arrangement region of the board, and then the balls are transferred and bonded onto an objective substance with their positions being adjusted. Gas blow is applied to the temporarily arranged balls or alternatively the... Agent: Kenyon & Kenyon LLP

20080032494 - Interconnect structures with bond-pads and methods of forming bump sites on bond-pads: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further... Agent: Perkins Coie LLP Patent-sea

20080032496 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: Saile Ackerman LLC

20080032497 - Preparing method of cnt-based semiconductor sensitized solar cell: A solar cell is prepared. The solar cell is photo-sensitized. The solar cell has a semiconductor layer. And carbon nanotubes are deposited on the semiconductor layer with an arrangement. The solar cell is prepared with a reduced amount of fabrication material, a lowered fabrication cost and a prolonged lifetime.... Agent: Troxell Law Office PLLC

20080032498 - Method for fabricating metal line of semiconductor device: Provided is a method for fabricating a metal line of a semiconductor device. In a method according to one embodiment, an interlayer insulating layer is formed on a semiconductor substrate. After that, a first trench and a second trench having a wider width than that of the first trench are... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080032499 - Method for manufacturing contact structures of wiring: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a... Agent: Macpherson Kwok Chen & Heid LLP

20080032500 - Substrate processing system and substrate processing method: Disclosed is a substrate processing method that dissolves and deforms a photoresist film having a first pattern formed on a substrate to reshape the resist film into a second pattern During the reflow process, an atmosphere of a thinner vapor-containing gas is established in a processing chamber. A substrate is... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080032501 - Silicon on metal for mems devices: Micro-electromechanical systems (MEMS) pre-fabrication products and methods for forming MEMS devices using silicon-on-metal (SOM) wafers. An embodiment of a method may include the steps of bonding a patterned SOM wafer to a cover wafer, thinning the handle layer of the SOM wafer, selectively removing the exposed metal layer, and either... Agent: Honeywell International Inc. Patent Services Ab-2b

20080032502 - Safety features for semiconductor processing apparatus using pyrophoric precursor: A semiconductor processing apparatus comprises a pyrophoric source vessel within an enclosure, the vessel containing a pyrophoric material. An air intake labyrinth extends away from the enclosure and has an inlet and an outlet. The inlet is in fluid communication with an exterior of the enclosure, and the outlet is... Agent: Knobbe, Martens, Olsen & Bear LLP

20080032503 - High nucleation density organometallic compounds: This invention relates to high nucleation density organometallic ruthenium compounds. This invention also relates to a process for producing a high nucleation density organometallic ruthenium compound comprising reacting a bis(substituted-pentadienyl)ruthenium compound with a substituted cyclopentadiene compound under reaction conditions sufficient to produce said high nucleation density organometallic ruthenium compound. This... Agent: Praxair, Inc. Law Department - M1 557

20080032504 - Polishing cloth and method of manufacturing semiconductor device: A polishing cloth used in the chemical mechanical polishing treatment comprises a molded body of (meth)acrylic copolymer having an acid value of 10 to 100 mg KOH/g and a hydroxyl group value of 50 to 150 mg KOH/g.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080032505 - Polishing composition and polishing process: A polishing composition comprising an anionic surfactant and a nonionic surfactant, characterized in that the composition is prepared so that the water contact angle of the surface of an object to be polished, after being polished by the composition, would be at most 60°. Particularly, a polishing composition having a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080032506 - Method of forming a mask pattern: A method of forming a mask pattern and, more particularly, a method of forming a mask pattern wherein micro patterns having resolutions lower than those of exposure equipment by overcoming the resolutions of the exposure equipment, wherein, a silicon layer is formed over a substrate and is patterned. The patterned... Agent: Marshall, Gerstein & Borun LLP

20080032507 - Method of treating a mask layer prior to performing an etching process: A method of pre-treating a mask layer prior to etching an underlying thin film is described. A thin film, such as a dielectric film, is etched using plasma that is enhanced with a ballistic electron beam. In order to reduce the loss of pattern definition, such as line edge roughness... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080032508 - Method and material for forming a double exposure lithography pattern: A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second... Agent: Haynes And Boone, LLP

20080032509 - Method for forming a nitrogen-containing gate insulating film: A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitride layer by... Agent: Sughrue Mion, PLLC

20080032510 - Cmos sion gate dielectric performance with double plasma nitridation containing noble gas: A method of forming a layer comprising silicon and nitrogen on a substrate is provided. The layer may also include oxygen and be used as a silicon oxynitride gate dielectric layer. In one aspect, forming the layer includes exposing a silicon substrate to a plasma of nitrogen and a noble... Agent: Patterson & Sheridan, LLP

20080032512 - Method forming silicon oxynitride gate dielectric layer with uniform nitrogen concentration: A method of manufacturing a semiconductor device in a process camber is disclosed. The method includes forming a preliminary dielectric layer including oxynitride on a substrate by performing a plasma oxidation treatment and a first plasma nitridation treatment, wherein the preliminary dielectric layer has a substantially uniform nitrogen concentration profile... Agent: Volentine & Whitt PLLC

20080032511 - Semiconductor device manufacturing method and plasma oxidation treatment method: A selective oxidation process is performed on a gate electrode in a plasma processing apparatus 100. A wafer W with the gate electrode formed thereon is placed on a susceptor 2 within a chamber 1. Ar gas, H2 gas, and O2 gas are supplied from an Ar gas supply source... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080032513 - Integrated circuit system including nitride layer technology: An integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer... Agent: Law Offices Of Mikio Ishimaru

20080032514 - Method for manufacturing semiconductor device, and substrate processing apparatus: A step is provided for supplying a first raw material, which contains a metal atom, and a second raw material, which contains a silicon atom and a nitrogen atom, into a processing chamber (4); and forming on a substrate (30) a metal silicate film containing the metal atom and silicon... Agent: Oliff & Berridge, PLC