Semiconductor device manufacturing: process inventions 01/08

20080026487 - Method of forming an etch indicator layer for reducing etch non-uniformities: By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advantageously, the material may be incorporated by ion implantation which provides... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080026488 - Method and apparatus for detecting endpoint in a dry etching system by monitoring a superimposed dc current: A method and apparatus for detecting the endpoint in a dry plasma etching system comprising a first electrode (e.g., upper electrode) and a second electrode (e.g., lower electrode) upon which a substrate rests is described. A direct current (DC) voltage is applied between the first electrode and a ring electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080026489 - Method and system for modeling statistical leakage-current distribution: Disclosed is a method and system for modeling statistical leakage current distribution using logarithmic skew-normal distribution by generating statistical data with a statistical analysis method based on Monte-Carlo simulations or based on a pre-characterization response modeling step for a plurality of representative chip-unit models, deriving a plurality of parameters from... Agent: Brinks Hofer Gilson & Lione

20080026491 - Method of wafer segmenting: A method of wafer segmenting is provided. Initially, a wafer having a plurality of devices on a top surface thereof is provided. A passivation layer is formed on the top surface of the wafer to cover the devices. A bottom surface of the first bonding layer is attached to a... Agent: North America Intellectual Property Corporation

20080026492 - Method of reducing contamination by providing a removable polymer protection film during microstructure processing: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective... Agent: Williams, Morgan & Amerson

20080026495 - Electromagnetic waveguide: A method of manufacturing an electromagnetic (EM) waveguide capable of guiding a wave along a pre-defined propagation path is described. The method includes providing a core region that extends along the propagation path and printing a colloidal crystal comprised of first particles on the waveguide core region.... Agent: Hewlett Packard Company

20080026494 - Method of fabricating a terbium-doped electroluminescence device via metal organic deposition processes: A method of fabricating an electroluminescent device includes preparing a wafer and a doped-silicon oxide precursor solution. The doped-silicon oxide precursor solution is spin coated onto the wafer to form a doped-silicon oxide thin film on the wafer, which is baked at progressively increasing temperatures. The wafer is then rapidly... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080026497 - Manufacturing method of light-emitting element: A manufacturing method of a light-emitting element includes emitting a laser light to a division region for separating a light-emitting element formed on a substrate, physically dividing the substrate along the division region, and removing a surface layer on at least one of the side faces of the substrate that... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080026496 - Method of making organic light emitting devices: The present invention provides a method for the preparation of organic light-emitting devices comprising a bilayer structure made by forming a first film layer comprising an electroactive material and an INP precursor material, and exposing the first film layer to a radiation source under an inert atmosphere to generate an... Agent: General Electric Company Global Research

20080026498 - Light emitting diode package element with internal meniscus for bubble free lens placement: A method for fabricating a light emitting diode (LED) package comprising providing an LED chip and covering at least part of the LED chip with a liquid encapsulant having a radius of curvature. An optical element is provided having a bottom surface with at least a portion having a radius... Agent: Koppel, Patrick & Heybl

20080026499 - Method for forming pattern, and method for manufacturing liquid crystal display: A method for forming a pattern, comprises: forming a bank film on a substrate; performing a lyophobic treatment on a surface of the bank film; patterning the bank film on which the lyophobic treatment has been performed to form a bank; performing a surface modification treatment in which a hydroxyl... Agent: Harness, Dickey & Pierce, P.L.C

20080026503 - On-chip sensor array for temperature management in integrated circuits: Embodiments of the invention provide methods and apparatus for managing temperature in integrated circuits. In accordance with an aspect of the invention, an integrated circuit comprises a monitored region defined by three or more edges. What is more, the integrated circuit comprises at least two temperature sensors for each of... Agent: Ryan, Mason & Lewis, LLP

20080026490 - Evaluation method using a teg, a method of manufacturing a semiconductor device having the teg, an element substrate and a panel having the teg, a program for controlling dosage and a computer-readable recording medium recording the program: The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped region. According to the present invention, plural TEGs... Agent: Nixon Peabody, LLP

20080026493 - Efficient method to predict integrated circuit temperature and power maps: The temperature distribution associated with a design of an integrated circuit is calculated by convoluting a surface power usage represented by a power matrix with a heat spreading function. The heat spreading function may be calculated from a simulation of a point source on the integrated circuit using a finite... Agent: Lumen Intellectual Property Services, Inc.

20080026500 - Flat panel display device and method for manufacturing the same: A flat panel display device includes a substrate including a pixel area having a plurality of pixel parts and a peripheral circuit area disposed adjacent to the pixel area to drive the pixel parts, a circuit TFT disposed in the peripheral circuit area, the circuit TFT including a first semiconductor... Agent: F. Chau & Associates, LLC

20080026501 - Method of manufacturing a light emitting device: A technique capable of efficient, high speed processing for the formation of an organic compound layer by using an ink jet method is provided. In the method of forming an organic compound layer by using the ink jet method, a composition containing an organic compound having light emitting characteristics is... Agent: Nixon Peabody, LLP

20080026502 - Growth of non-polar m-plane iii-nitride film using metalorganic chemical vapor deposition (mocvd): A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO2 or LiAlO2 substrate, using metalorganic chemical vapor deposition (MOCVD). The method includes performing a solvent clean and... Agent: Gates & Cooper LLP Howard Hughes Center

20080026504 - Solid-state image pickup device and manufacturing method for the same: A solid-state image pickup device includes, in a substrate, a plurality of photoelectric conversion regions for subjecting incoming light to photoelectric conversion, a reading gate for reading a signal charge from the photoelectric conversion regions, and a transfer register (vertical register) for transferring the signal charge read by the reading... Agent: Robert J. Depke Lewis T. Steadman

20080026505 - Electronic packages with roughened wetting and non-wetting zones: The flow of polymer formulations in in integrated circuit packages can be controlled by altering the roughness and surface chemistry of package surfaces. The surface roughness can be altered by forming protrusions having a dimension less than 500 nanometers and their chemistry can be controlled by chemical or plasma treatment.... Agent: Trop Pruner & Hu, PC

20080026506 - Semiconductor multi-chip package and fabrication method: A multi-chip package comprises a package substrate having bond fingers disposed thereon. A first chip have center bonding pads formed on a substantially center portion thereof. The first chip is disposed on the package substrate. Insulating support structures are formed on the first chip located outward of the bonding pads.... Agent: Marger Johnson & Mccollom, P.C.

20080026507 - Stack package using anisotropic conductive film (acf) and method of making same: Provided is a stack package using an anisotropic conductive film (ACF) for reducing thermal stresses exerted on chip scale packages (CSPs) during the initial manufacture of stack packages from a plurality of CSPs and for facilitating the repair and/or rework of stack packages incorporating CSPs while reducing the likelihood of... Agent: Harness, Dickey & Pierce, P.L.C

20080026509 - Cooling apparatuses and methods employing discrete cold plates compliantly coupled between a common manifold and electronics components of an assembly to be cooled: Cooling apparatuses and methods are provided for cooling an assembly including a planar support structure supporting multiple electronics components. The cooling apparatus includes: multiple discrete cold plates, each having a coolant inlet, coolant outlet and at least one coolant carrying channel disposed therebetween; and a manifold for distributing coolant to... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080026508 - Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a... Agent: Hitt Gaines, PC Lsi Corporation

20080026510 - Nonvolatile memory cell comprising a reduced height vertical diode: A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types... Agent: Dugan & Dugan, PC

20080026511 - Semiconductor device and method for manufacturing thereof: A method for manufacturing a semiconductor device includes: a) forming a first semiconductor layer which can be etched faster than a semiconductor substrate, on the semiconductor substrate including a first region that is arranged at a predetermined interval and is to be provided with a silicon on insulator (SOI) structure;... Agent: Advantedge Law Group, LLC

20080026512 - Integrated circuit chip with fets having mixed body thicknesses and method of manufacture thereof: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080026513 - Method and structure for self-aligned device contacts: Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080026514 - Method for producing nitride semiconductor device: A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen among a group consisting of nitrogen, phosphorus... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080026515 - Silicide block isolated junction field effect transistor source, drain and gate: An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among... Agent: Texas Instruments Incorporated

20080026517 - Method for forming a stressor layer: In one aspect, a method for forming a semiconductor device includes forming a stressor layer over a gate stack and a spacer adjacent the gate stack, implanting a species into at least a portion of the stressor layer, and curing the stressor layer. In another aspect, a method includes forming... Agent: Freescale Semiconductor, Inc. Law Department

20080026516 - Raised sti structure and superdamascene technique for nmosfet performance enhancement with embedded silicon carbon: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing... Agent: Whitham, Curtis & Christofferson, P.C.

20080026519 - Semiconductor devices and methods of fabricating the same: In a method of fabricating a semiconductor device, a first mask pattern is formed on a substrate. The first mask pattern has a first opening formed to expose the substrate. An oxidation barrier region is formed in the substrate exposed by the first opening, and the first mask pattern is... Agent: Harness, Dickey & Pierce, P.L.C

20080026518 - Spacer layer etch method providing enhanced microelectronic device performance: A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080026520 - Semiconductor method and device with mixed orientation substrate: In a method of forming a semiconductor device, a wafer includes a first semiconductor region of a first crystal orientation and a second semiconductor region of a second crystal orientation. Insulating material is formed over the wafer. A first portion of the insulating material is removed to expose the first... Agent: Slater & Matsil LLP

20080026521 - Method for manufacturing a transistor of a semiconductor device: A method for manufacturing a transistor of a semiconductor device is provided. The method includes the steps of: forming a gate over a semiconductor substrate including an NMOS transistor region and a PMOS transistor region; forming a photoresist pattern to open the gate of the PMOS transistor region; forming a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080026522 - High performance cmos device structures and method of manufacture: A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably,... Agent: International Business Machines Corporation Dept. 18g

20080026523 - Structure and method to implement dual stressor layers with improved silicide control: An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the... Agent: HorizonIPPte Ltd

20080026524 - Semiconductor device having a well structure for improving soft error rate immunity and latch-up immunity and a method of making such a device: A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain... Agent: Marger Johnson & Mccollom, P.C.

20080026525 - Semiconductor processing method and chemical mechanical polishing methods: This invention includes a chemical mechanical polishing method including providing a substrate having an organic material to be polished by chemical mechanical polishing. In one implementation, the organic material is chemical mechanically polished using a polishing pad downforce on the substrate of less than or equal to 1.75 psi, using... Agent: Wells St. John P.s.

20080026527 - An apparatus and associated method for making a floating gate memory device with increased gate coupling ratio: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate... Agent: Baker & Mckenzie LLP Patent Department

20080026526 - Method for removing nanoclusters from selected regions: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer.... Agent: Freescale Semiconductor, Inc. Law Department

20080026528 - Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080026531 - Field effect transistor and method of forming a field effect transistor: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080026530 - Method of forming a doped portion of a semiconductor and method of forming a transistor: A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion... Agent: Edell, Shapiro & Finnan, LLC

20080026529 - Transistor with asymmetry for data storage circuitry: A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region... Agent: Freescale Semiconductor, Inc. Law Department

20080026532 - Nano-enabled memory devices and anisotropic charge carrying arrays: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the... Agent: Nanosys Inc.

20080026533 - Semiconductor device and manufacturing method thereof: An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in... Agent: Mcdermott Will & Emery LLP

20080026534 - Self-aligned process for nanotube/nanowire fets: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention... Agent: Scully, Scott, Murphy & Presser, P.C.

20080026535 - Phase-changeable memory device and method of manufacturing the same: A phase changeable random access memory (PRAM) and methods for manufacturing the same. An example unit cell of a non-volatile memory, such as a PRAM, includes a MOS transistor, connected to an address line and a data line, where the MOS transistor receives a voltage from the data line. The... Agent: Harness, Dickey & Pierce, P.L.C

20080026536 - Integrated process for thin film resistors with silicides: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of the semiconductor... Agent: Fogg & Powers LLC

20080026537 - Method for forming capacitor of semiconductor device: A method for forming a capacitor of a semiconductor device includes forming a first capacitor in a storage node contact region to form a two-stage structured capacitor, thereby increasing the height and the capacitance of the capacitor.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080026538 - Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first... Agent: Myers Bigel Sibley & Sajovec

20080026539 - Capacitance element manufacturing method and etching method: An etching technique suitable for miniaturization is provided. An inorganic film is formed on an object to be subjected, the object having a lower electrode film, a dielectric film, and an upper electrode film laminated in that order on a substrate. A patterned organic resist film is disposed on the... Agent: Kratz, Quintos & Hanson, LLP

20080026540 - Integration for buried epitaxial stressor: Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the stressor layer. We form STI trenches down... Agent: HorizonIPPte Ltd

20080026541 - Air-gap interconnect structures with selective cap: A method of forming a semiconductor structure and the semiconductor structure. The method of manufacturing a structure includes applying a selective cap deposition to at least partially fill perforations, openings, or nano-holes formed above exposed portions of an interconnect during air-gap formation. The structure includes an insulator layer having the... Agent: Greenblum & Bernstein, P.L.C

20080026542 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is provided. According to an embodiment, a first opening is formed on a semiconductor substrate, and a sacrificial layer is formed to fill the first opening. Then, a second opening is formed on a region of the semiconductor substrate having the first opening.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080026543 - Method of manufacturing semiconductor device: A method of forming a semiconductor device is provided, including a step of forming a layer which absorbs light over one face of a first substrate, a step of providing a second substrate over the layer which absorbs light, a step of providing a mask to oppose the other face... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080026544 - Method for improving the quality of an sic crystal and an sic semiconductor device: (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically... Agent: The Webb Law Firm, P.C.

20080026545 - Integrated devices on a common compound semiconductor iii-v wafer: A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to... Agent: Fish & Richardson P.C.

20080026546 - Crystal growth method and reactor design: A crystal growth process comprising providing a reactor having a crucible with an injector apparatus and a seed holder. The injector apparatus has an inner gas conduit and an outer gas conduit wherein an inert gas is introduced into the outer conduit. The injector apparatus has an upper injector and... Agent: Schnader Harrison Segal & Lewis, LLP

20080026547 - Method of forming poly-si pattern, diode having poly-si pattern, multi-layer cross point resistive memory device having poly-si pattern, and method of manufacturing the diode and the memory device: A method of forming a poly-silicon pattern may include forming an amorphous silicon pattern on a lower layer; forming a capping layer on the substrate covering the amorphous silicon pattern; poly-crystallizing the amorphous silicon pattern using an excimer laser annealing process; and removing the capping layer.... Agent: Harness, Dickey & Pierce, P.L.C

20080026548 - Film forming apparatus and film forming method: An optical film having a thin film stacked and optical characteristics close to design values is provided. In a vacuum chamber (2), a rotating drum (3) holding a substrate (4), an Si target (22) for forming a metal film on a film forming plane of the substrate (4), a Ta... Agent: Arent Fox LLP

20080026549 - Methods of controlling morphology during epitaxial layer formation: A first aspect of the invention provides a method of selectively forming an epitaxial layer on a substrate. The method includes heating the substrate to a temperature of less than about 800° C. and employing both silane and dichlorosilane as silicon sources during epitaxial film formation. Numerous other aspects are... Agent: Dugan & Dugan, PC

20080026550 - Laser doping of solid bodies using a linear-focussed laser beam and production of solar-cell emitters based on said method: In the laser doping method in accordance with the invention firstly a medium containing a dopant is brought into contact with a surface of the solid-state material. Then, by beaming with laser pulses, a region of the solid-state material below the surface contacted by the medium is melted so that... Agent: Straub & Pokotylo

20080026551 - Formation of fully silicided metal gate using dual self-aligned silicide process: An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also... Agent: Scully, Scott, Murphy & Presser, P.C.

20080026552 - Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography: In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the... Agent: Williams, Morgan & Amerson

20080026553 - Method for fabricating an integrated gate dielectric layer for field effect transistors: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing... Agent: Patterson & Sheridan, LLP

20080026556 - Barrier process/structure for transistor trench contact applications: A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration... Agent: Lee & Hayes, PLLC C/o Intellevate

20080026554 - Interconnect structure for beol applications: A semiconductor interconnect structure is provided that includes a new capping layer/dielectric material interface which is embedded inside the dielectric material. In particular, the new interface is an air gap that is located in the upper surface of a dielectric material that is adjacent to a conductive region or feature.... Agent: Scully, Scott, Murphy & Presser, P.C.

20080026555 - Sacrificial tapered trench opening for damascene interconnects: A method for forming a trench with a flared opening in a dielectric layer comprises providing a semiconductor substrate having a dielectric layer deposited thereon, depositing and patterning a photoresist layer atop the dielectric layer to form at least two photoresist structures, applying a plasma etch to define a flared... Agent: Intel Corporation C/o Intellevate, LLC

20080026557 - Electronic system modules and method of fabrication: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection... Agent: Townsend And Townsend And Crew, LLP

20080026558 - Pad structure for liquid crystal display and method of manufacturing thereof: A liquid crystal display has a pad structure. The pad structure includes at least one pad formed on a substrate, an insulating film formed on the pad, and at least one conductive layer connected to the pad through contact holes defined through the insulating film. The insulating film covers side... Agent: Mckenna Long & Aldridge LLP

20080026560 - Methods of forming electronic structures including conductive shunt layers and related structures: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the... Agent: Myers Bigel Sibley & Sajovec

20080026559 - Solder ball pad structure: An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact... Agent: Texas Instruments Incorporated

20080026561 - Methods of trench and contact formation in memory cells: Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20080026562 - Novel metallization scheme and method of manufacture therefor: The present invention provides a metallization scheme, a method for manufacturing the metallization scheme, and an integrated circuit including the metallization scheme. In one aspect, the metallization scheme (300) includes a protective layer (320) located over a substrate (310), and a conductive layer (330) located over the protective layer (320).... Agent: Texas Instruments Incorporated

20080026563 - Semiconductor device manufacturing device: A process for production of a semiconductor device having a multi-layer wiring of dual damascene structure in a low-dielectric constant interlayer insulating film. The process consists of the following steps. A first insulating film and a second insulating film are formed. A first to third mask forming layers are formed.... Agent: Sonnenschein Nath & Rosenthal LLP

20080026564 - Method of forming an electrically conductive line in an integrated circuit: A method of forming a semiconductor structure comprises providing a semiconductor structure comprising a layer of a dielectric material provided over an electrically conductive feature. An opening is formed in the layer of dielectric material. The opening is located over the electrically conductive feature and has a first lateral dimension.... Agent: J. Mike Amerson, Williams, Morgan & Amerson , P.C.

20080026566 - Dual damascene interconnect structures having different materials for line and via conductors: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner... Agent: International Business Machines Corporation Dept. 18g

20080026567 - Increasing electromigration lifetime and current density in ic using vertically upwardly extending dummy via: An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the... Agent: Hoffman, Warnick & D'alessandro LLC

20080026565 - Method of manufacturing a composite of copper and resin: A metallic copper and resin composite body manufacturing method of forming a copper wiring layer that forms an inner layer circuit, establishing an insulating layer with a resin on said wiring layer, forming via holes which expose the copper surface under the insulative layer, and depositing a metal on the... Agent: John J. Piskorski Rohm And Haas Electronic Materials LLC

20080026568 - Interconnect structure and process of making the same: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings... Agent: International Business Machines Corporation Dept. 18g

20080026569 - Advanced seed layers for interconnects: One embodiment of the present invention is a method for making metallic interconnects over a substrate, the substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the at least one opening has sidewalls and bottom and a width... Agent: Uri Cohen

20080026570 - Method of forming a metal line of a semiconductor memory device: A method of forming a metal line of a semiconductor memory device is disclosed. An interlayer insulating layer, an etch-stop layer, a trench oxide layer, a hard mask layer and a photoresist layer are laminated over a semiconductor substrate in which a contact is formed. An exposure process is performed... Agent: Townsend And Townsend And Crew, LLP

20080026571 - Bit line barrier metal layer for semiconductor device and process for preparing the same: The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing... Agent: Marshall, Gerstein & Borun LLP

20080026572 - Method for forming a strained transistor by stress memorization based on a stressed implantation mask: By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080026573 - Method of producing active matrix substrate: The invention provides a production method for an active matrix substrate in which a plurality of contact holes are formed by a one-mask process so as to reach metal films which are present at different depth positions in an insulating layer and are not evaporated by dry etching using a... Agent: Sughrue Mion, PLLC

20080026574 - Method and apparatus of distributed plasma processing system for conformal ion stimulated nanoscale deposition process: A deposition system and method of operating thereof is described for depositing a conformal metal or other similarly responsive coating material film in a high aspect ratio feature using a high density plasma is described. The deposition system includes a plasma source, and a distributed metal source for forming plasma... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080026575 - Dispenser system for atomic beam assisted metal organic chemical vapor deposition (mocvd): A dispenser system for use in atomic beam assisted metal organic chemical vapor deposition is provided as well as a method of depositing an ultra-thin film using the same. The inventive dispenser system includes an atomic source having an unimpeded line of site to a substrate and an annular metal... Agent: Scully, Scott, Murphy & Presser, P.C.

20080026576 - Organometallic compounds: Certain organometallic compounds in the form of imino complexes are provided. Such complexes are particularly suitable for use as vapor deposition precursors. Also provided are methods of depositing thin films, such as by ALD and CVD, using such compounds.... Agent: Rohm And Haas Electronic Materials LLC

20080026577 - Organometallic compounds: Organometallic compounds containing a phosphoamidinate ligand are provided. Such compounds are particularly suitable for use as vapor deposition precursors. Also provided are methods of depositing thin films, such as by ALD and CVD, using such compounds.... Agent: Rohm And Haas Electronic Materials LLC

20080026578 - Organometallic compounds: Organometallic compounds containing an electron donating group-substituted alkenyl ligand are provided. Such compounds are particularly suitable for use as vapor deposition precursors. Also provided are methods of depositing thin films, such as by ALD and CVD, using such compounds.... Agent: Rohm And Haas Electronic Materials LLC

20080026579 - Copper damascene process: A copper damascene process includes providing a substrate having a dielectric layer thereon, forming at least a copper damascene structure in the dielectric layer, performing a heat treatment on the substrate, and performing a reduction plasma treatment on a surface of the copper damascene structure. The impurities formed in the... Agent: North America Intellectual Property Corporation

20080026580 - Method for forming copper metal lines in semiconductor integrated circuit devices: A method of forming copper metal lines capable of improving surface coatability without forming overhangs of a diffusion barrier film for preventing diffusion of copper in an upper portion of a hole and preventing formation of a copper void is disclosed. The method includes coating a lower layer on a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080026581 - Flexible substrate with electronic devices formed thereon: A method of manufacturing an electronic device (10) provides a substrate (20) that has a plastic material. A particulate material (16) is embedded in at least one surface of the substrate. A layer of thin-film semiconductor material is deposited onto the substrate (20).... Agent: Mark G. Bocchetti Patent Legal Staff

20080026582 - Planarization process for pre-damascene structure including metal hard mask: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP... Agent: Jianq Chyun Intellectual Property Office

20080026583 - Compositions and methods for modifying a surface suited for semiconductor fabrication: The disclosure pertains to compositions and methods for modifying or refining the surface of a wafer suited for semiconductor fabrication. The compositions include working liquids useful in modifying a surface of a wafer suited for fabrication of a semiconductor device. In some embodiments, the working liquids are aqueous solutions of... Agent: 3m Innovative Properties Company

20080026584 - Lpcvd gate hard mask: A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate... Agent: Patterson & Sheridan, LLP

20080026585 - Composition for removing a film, method of removing a film using the same, and method of forming a pattern using the same: A film (e.g., silicon polymer film, photoresist film) may be removed by applying a composition including a quaternary ammonium hydroxide, a sulfoxide compound, a dialkylene glycol alkyl ether, and/or water to the film. A silicon polymer film (e.g., hard mask layer) and a photoresist film, for example, may be removed... Agent: Harness, Dickey & Pierce, P.L.C

20080026586 - Phase change memory cell and method and system for forming the same: For fabricating a phase change memory cell, a layer of phase change material and a layer of a first electrode material are deposited. In addition, the first electrode material is patterned using an etchant including a low-reactivity halogen element such as bromine or iodine to form a first electrode. By... Agent: Law Office Of Monica H Choi

20080026587 - Semiconductor device: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be... Agent: Sherr & Nourse, PLLC

20080026588 - Method of forming inductor in semiconductor device: Disclosed herein is a method of forming an inductor in a semiconductor device, the method including forming an etching-prevention film, a first interlayer insulating film, and a first hard mask film over a silicon semiconductor substrate in this sequence; selectively etching the first hard mask film to form a hole;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080026589 - Electrode for plasma processes and method for manufacture and use thereof: A silicon electrode for a plasma reaction chamber wherein processing of a semiconductor substrate such as a single wafer can be carried out and a method of processing a semiconductor substrate with the electrode. The electrode is a low resistivity electrode having an electrical resistivity of less than 1 ohm-cm.... Agent: Buchanan, Ingersoll & Rooney PC

20080026590 - Metal organic deposition precursor solution synthesis and terbium-doped sio2 thin film deposition: A method of making a doped silicon oxide thin film using a doped silicon oxide precursor solution includes mixing a silicon source in an organic acid and adding 2-methoxyethyl ether to the silicon source and organic acid to from a preliminary precursor solution. The resultant solution is heated, stirred and... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080026591 - Sintered metal components for crystal growth reactors: An injector apparatus for a crystal growth reactor having a graphite casing, a stainless steel nozzle, a nozzle holder to position the nozzle within the graphite casing, a lower injector disposed within the graphite casing and extending around the nozzle to a point above the nozzle to direct gas flow... Agent: Schnader Harrison Segal & Lewis, LLP

20080026592 - Multilayer substrate: A multilayer substrate device formed from a base substrate and alternating metalization layers and dielectric layers. Each layer is formed without firing. Vias may extend through one of the dielectric layers such that two metalization layers surrounding the dielectric layers make contact with each other. The vias may be formed... Agent: Foley & Lardner

20080026593 - Method and apparatus for the manufacture of electric circuits: A method of manufacturing a patterned electric circuit. The method comprises the steps of providing a cold gas-dynamic spraying (CGDS) device, providing a substrate, and depositing a pattern of electrically conductive material with the CGDS device on the substrate by relative movement between the CGDS device to the substrate.... Agent: Welsh & Flaxman LLC

20080026594 - Reduction of cracking in low-k spin-on dielectric films: The present invention relates to a process that minimizes the cracking of low-k dielectric polymers. In an example embodiment, on a semiconductor substrate (200), there is a method of forming a composite dielectric disposed on a metal layer passivated with plasma deposited silicon oxide SiOx. The method comprises depositing depositing... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080026595 - Method of forming an integrated circuit having a device wafer with a diffused doped backside layer: A method for forming a diffused, doped backside layer on a device wafer oxide bonded to a handle wafer in an integrated circuit is provided. The method comprises forming a thermal bond oxide layer on a backside surface of the device wafer of the integrated circuit. Implanting the bond oxide... Agent: Fogg & Powers LLC

20080026596 - Method of forming metallic oxide films using atomic layer deposition: Example embodiments are directed to methods of forming a metallic oxide film using Atomic Layer Deposition while controlling the power reflected by a reactor. The method may include feeding metallic source gases, for example, first and second metallic source gases, and/or a reactant gas including oxygen into the reactor individually.... Agent: Harness, Dickey & Pierce, P.L.C

20080026597 - Method for depositing and curing low-k films for gapfill and conformal film applications: Methods of making a silicon oxide layer on a substrate are described. The methods may include forming the silicon oxide layer on the substrate in a reaction chamber by reacting an atomic oxygen precursor and a silicon precursor and depositing reaction products on the substrate. The atomic oxygen precursor is... Agent: Townsend And Townsend And Crew LLP / Amat

20080026598 - Semiconductor manufacturing device and method: A semiconductor manufacturing device and a method thereof capable of processing semiconductor substrates having a large diameter in a state that the semiconductor substrates keep standing and are opposed to each other are disclosed. The semiconductor manufacturing device includes a reaction chamber for providing an airtight process space; a boat... Agent: Ditthavong Mori & Steiner, P.C.

20080026599 - Transfer of stress to a layer: A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric... Agent: Freescale Semiconductor, Inc. Law Department

20080020490 - Method for manufacturing ferroelectric memory: A method for manufacturing a ferroelectric memory includes the steps of: (a) forming a ferroelectric capacitor by sequentially laminating, on a substrate, a lower electrode, a ferroelectric layer and an upper electrode; (b) forming a first dielectric layer that covers the ferroelectric capacitor; (c) forming a contact hole in the... Agent: Harness, Dickey & Pierce, P.L.C

20080020489 - Methods of fabricating ferroelectric devices: A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.... Agent: Myers Bigel Sibley & Sajovec

20080020488 - Semiconductor integrated circuit devices having high-q wafer backside inductors and methods of fabricating same: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside... Agent: F. Chau & Associates, LLC

20080020494 - Film formation apparatus, precursor introduction method and film formation method: The present invention is to use a film formation apparatus having: a film formation chamber; a preparation device for preparing a solid precursor solution by dissolving the solid precursor in supercritical carbon dioxide; a first supercritical carbon dioxide feeding line for feeding supercritical carbon dioxide into the preparation device; a... Agent: Young & Thompson

20080020497 - Method for evaluating quality of semiconductor substrate and method for manufacturing semiconductor substrate: Methods for evaluating a quality of a semiconductor substrate. In one aspect, etching a surface of the semiconductor substrate by dry-etching, detecting bright points on the surface of the etched surface with a foreign matter inspection device, and evaluating the quality of the semiconductor substrate based on the number and/or... Agent: Greenblum & Bernstein, P.L.C

20080020502 - Method for manufacturing semiconductor optical device: A method for manufacturing a laser diode includes: providing a semiconductor structure in which semiconductor layers are laminated; forming a waveguide ridge in the layers; forming an SiO2 film over the entire surface; forming a second resist pattern covering the SiO2 film in channels adjacent the waveguide ridge such that... Agent: Leydig Voit & Mayer, Ltd

20080020504 - Sensors for detecting nox in a gas and methods for fabricating the same: Nitrogen oxide sensors and methods for fabricating them are provided. According to an exemplary embodiment of the present invention, the method comprises providing an electrically insulating substrate having a first surface and a second surface. Two electrodes are fabricated on the first surface of the substrate. Each of the electrodes... Agent: Honeywell International Inc.

20080020506 - Method for forming color filter: A method for forming a color filter is provided. The method comprises steps of providing a substrate having a passivasion layer formed thereon. The substrate has at least one complementary metal-oxide semiconductor formed therein and the passivasion layer has at least trench formed therein in a peripheral region of the... Agent: Jianq Chyun Intellectual Property Office

20080020507 - Method for manufacturing semiconductor integrated circuit device: Due to a difference in a film thickness generated in structure layers located on top of a light receiver, a bottom surface of an open part does not flatten and an amount of incident light within a surface of the light receiver becomes nonuniform. A flat layer is formed by... Agent: Oliff & Berridge, PLC

20080020487 - Alignment of carbon nanotubes on a substrate via solution deposition: Carbon nanotubes, associated with a charged dispersant are aligned on a substrate by deposition on the substrate directly from solution. Preferred dispersants are charged polymers such as biopolymers.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080020492 - Ferroelectric memory and its manufacturing method: A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above... Agent: Harness, Dickey & Pierce, P.L.C

20080020491 - Magneticially lined conductors: A method of making a conductor with improved magnetic field per current ratio is disclosed. The conductor includes a magnetic liner lining a second surface and sides thereof. The magnetic liner is preferably a super-paramagnet with high susceptibility or a ferromagnet with a microstructure where the size of the non-exchanged... Agent: Ference & Associates LLC

20080020493 - Apparatus for supplying chemical, semiconductor manufacturing apparatus having the same, and method for supplying chemical: Embodiments disclosed herein are generally directed to a chemical supplying apparatus, a semiconductor manufacturing equipment having the same and a method for supplying chemicals. The apparatus includes a tank, a first sensor, and a second sensor. The tank is filled with a liquid chemical and includes an outlet for the... Agent: Marger Johnson & Mccollom, P.C.

20080020495 - Semiconductor fabricating apparatus with function of determining etching processing state: A semiconductor fabricating method including: placing the semiconductor wafer having a film thereon inside of a chamber; generating plasma; detecting a quantity of interference lights for each of at least two wavelengths obtained from a surface of the wafer for a predetermined time period during the etching of the wafer;... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080020498 - Fabrication method of semiconductor integrated circuit device: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080020496 - Method of evaluating thermal treatment and method of manufacturing semiconductor wafer: Provided are the methods of evaluating thermal treatment. In the methods, a wafer comprising a silicon substrate having an oxygen concentration of approximately equal to or less than 1.0×1018 atoms/cm3 and a silicon epitaxial layer on at least one surface of the substrate is employed.... Agent: Greenblum & Bernstein, P.L.C

20080020499 - Nanotube assembly including protective layer and method for making the same: Nanotube assemblies and methods for manufacturing the same, including one or more protective layers. A nanotube assembly may include a substrate, a nanotube array, formed on the substrate, and a protective layer, formed on a first area of the substrate where the nanotube array is not, the protective layer reducing... Agent: Harness, Dickey & Pierce, P.L.C

20080020500 - Flat panel display and method of fabricating the same: A light-emitting display device the same includes an insulating substrate having a thin film transistor formed thereon. The thin film transistor includes a source electrode and/or a drain electrode. A passivation layer is formed on the insulating substrate over at least a portion of the thin film transistor, and has... Agent: H.c. Park & Associates, PLC

20080020501 - Liquid crystal display device and a manufacturing method of the same: A four-mask process and a three-mask process proposal are constructed for a TN-type liquid crystal display device and an IPS-type liquid crystal device in which the formation of a passivation insulating layer is not required by streamlining the formation of a scan line and a pseudo-pixel element, both comprising a... Agent: Bacon & Thomas, PLLC

20080020503 - Series interconnected optoelectronic device module assembly: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One... Agent: Nanosolar, Inc.

20080020505 - Packaged microelectronic imagers and methods of packaging microelectronic imagers: Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried... Agent: Dickstein Shapiro LLP

20080020508 - Reducing oxidation of phase change memory electrodes: A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped... Agent: Trop Pruner & Hu, PC

20080020509 - Thin film materials of amorphous metal oxides: Amorphous metal oxide thin film is produced by removing through oxygen plasma treatment the organic component from an organics/metal oxide composite thin film having thoroughly dispersed therein such organic component at molecular scale. This ensures production of amorphous metal oxide thin film with low density and excellent thickness precision.... Agent: Birch Stewart Kolasch & Birch

20080020510 - Fabrication method of semiconductor device: A technique able to effect automation of a molding process corresponding to a multifarious small lot semiconductor device manufacturing process is provided. As to a frame supply unit, a lead frame conveying unit and molding press sets, which are each operated by a motor within a molding apparatus, the amount... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080020511 - Structure of image sensor module and a method for manufacturing of wafer level package: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises a metal alloy base, a wafer level package, a lens holder, and flexible printed circuits (F.P.C.). The wafer level package having a plurality of image sensor dice and a plurality... Agent: Bacon & Thomas, PLLC

20080020512 - Method for making a semiconductor multi-package module having inverted wire bond carrier second package: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a wire bond... Agent: Law Offices Of Mikio Ishimaru

20080020513 - Method of fabricating semiconductor device having conducting portion of upper and lower conductive layers on a peripheral surface of the semiconductor device: A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080020514 - Method for producing bonded wafer: A bonded wafer is produced by a method comprising a step of implanting ions of a light element such as hydrogen, helium or the like into a wafer for active layer at a predetermined depth position to form an ion implanted layer, a step of bonding the wafer for active... Agent: Sughrue Mion, PLLC

20080020515 - Twisted dual-substrate orientation (dso) substrates: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer... Agent: Hamilton & Terrile, LLP

20080020516 - Method for attaching ic tag, article with ic tag attached, and ic tag: The present invention provides a method for attaching an IC tag. In the method, an IC tag performing wireless communication using an electronic component appropriately disposed is attached to an article made from an elastically deformable material. Specifically, the IC tag is attached to a predetermined portion of the article,... Agent: Dickstein Shapiro LLP

20080020517 - Multi lead frame power package: According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed within the mold compound, and in operation generates thermal energy. The first lead frame is... Agent: Texas Instruments Incorporated

20080020518 - Liquid crystal display panel: A laminated spacer portion formed by laminating various thin films that constitute thin-film transistors is disposed in peripheral driver circuits. As a result, even in a structure in which part of a sealing member is disposed above the peripheral driver circuits, pressure exerted from spacers in the sealing member is... Agent: Fish & Richardson P.C.

20080020519 - Ltps-lcd structure and method for manufacturing the same: An LTPS-LCD structure and a method for manufacturing the structure are provided. The structure comprises a substrate where a plurality of pixels are formed thereon. Each of these pixels comprises a control area, a capacitance area, and a display area. The structure is initially formed with a transparent electrode on... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080020520 - Method for manufacturing lower substrate of liquid crystal display device: A method for improving the tapered angles of the insulating layer and the semiconductor layer of a lower substrate of a thin film transistor liquid crystal display device is disclosed. The method mainly applies an etching gas including a sulfur fluoride compound to etch the insulating layer. After etching, the... Agent: Bacon & Thomas, PLLC

20080020521 - Hybrid substrate technology for high-mobility planar and multiple-gate mosfets: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper... Agent: Scully, Scott, Murphy & Presser, P.C.

20080020522 - Field effect transistors with dielectric source drain halo regions and reduced miller capacitance: A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed... Agent: Cantor Colburn LLP - IBM Fishkill

20080020523 - Method of fabricating complementary metal-oxide-semiconductor transistor and metal-oxide-semiconductor transistor: A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides... Agent: J.c. Patents, Inc.

20080020524 - Process for controlling performance characteristics of a negative differential resistance (ndr) device: A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with... Agent: Bever, Hoffman & Harms, LLP

20080020526 - Method and system for determining semiconductor characteristics: Method and system for determining semiconductor characteristics. In a specific embodiment, the present invention provides a method for determining one or more characteristics of a partially processed integrated circuit. The method includes a step for providing a substrate material. The method further includes a step for forming at least one... Agent: Townsend And Townsend And Crew, LLP

20080020525 - Method for fabricating semiconductor device: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in... Agent: J C Patents, Inc.

20080020527 - Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell: A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a programming operation, electrons... Agent: Marger Johnson & Mccollom, P.C.

20080020528 - Method of manufacturing semiconductor device and method of manufacturing nonvolatile semiconductor storage device: An object is to provide a technique for manufacturing an insulating layer with favorable withstand voltage. Another object is to provide a technique for manufacturing a semiconductor device having an insulating layer with favorable withstand voltage. By subjecting a semiconductor layer or semiconductor substrate mainly containing silicon to a high... Agent: Eric Robinson

20080020529 - Non-volatile memory and fabrication thereof: A non-volatile memory cell is described, including a semiconductor body of a first conductivity type, a trapping layer, a gate, and a first to a third doped regions of a second conductivity type. The semiconductor body has a trench thereon, the trapping layer is disposed on the surface of the... Agent: J.c. Patents

20080020530 - Manufacturing method of semiconductor device and semiconductor device: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; forming a second member to be patterned on the first member; forming a third member to be patterned on the second member; patterning the third member to form a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080020531 - Semiconductor devices having torsional stresses: A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of... Agent: International Business Machines Corporation Dept. 18g

20080020532 - Transistor with a channel comprising germanium: A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and... Agent: Docket Clerk

20080020533 - Method and apparatus for semiconductor device with improved source/drain junctions: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the... Agent: Slater & Matsil, L.L.P.

20080020534 - Semiconductor device fabrication methods: Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the workpiece between at least two of the plurality of active area... Agent: Slater & Matsil LLP

20080020535 - Silicide cap structure and process for reduced stress and improved gate sheet resistance: A silicide cap structure and method of fabricating a silicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and... Agent: Scully, Scott, Murphy & Presser, P.C.

20080020536 - Transistor structure with recessed source/drain and buried etch stop layer and related method: A transistor structure having a recessed source/drain and buried etch stop layer (e.g., a silicon germanium layer), and a related method, are disclosed. In one embodiment, the transistor structure includes a substrate including a substantially trapezoidal silicon pedestal over an etch stop layer; a gate atop the substantially trapezoidal silicon... Agent: Hoffman, Warnick & D'alessandro LLC

20080020537 - Method of fabricating field effect transistor (fet) having wire channels: In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns... Agent: Lee & Morse, P.C.

20080020538 - One mask high density capacitor for integrated circuits: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides... Agent: Texas Instruments Incorporated

20080020539 - Dynamic random access memory and fabrication method thereof: A dynamic random access memory including a substrate, an isolation structure, two transistors, two trench capacitors and two passing gates is provided. The isolation structure, including a first isolation structure and a second isolation structure, is disposed in the substrate. The second isolation structure is disposed in the substrate above... Agent: J.c. Patents

20080020540 - Manufacturing method of semiconductor device: The present invention provides an MIM capacitor using a high-k dielectric film preventing degradation of breakdown field strength of the MIM capacitor and suppressing the increase of the leakage current. The MIM capacitor comprises a first metal interconnect, a fabricated capacitance film, a fabricated upper electrode, and a third metal... Agent: Miles & Stockbridge PC

20080020541 - Method for manufacturing bonded soi wafer and bonded soi wafer manufactured thereby: A bonded SOI wafer is manufactured by performing bonding in a state where organics exist on a surface of an active layer wafer and/or on a surface of a supporting wafer and performing heat-treating for bonding reinforcement in a state where the organics are trapped at an interface between the... Agent: Clark & Brody

20080020542 - Semiconductor devices and methods of manufacture thereof: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer... Agent: Slater & Matsil LLP

20080020543 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device according to an embodiment includes: forming a trench for a device isolation area and a semiconductor projection with a first width by etching a semiconductor substrate; forming an oxide film on the trench and the semiconductor projections; forming an insulating layer on the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080020544 - Method for forming wall oxide layer and isolation layer in flash memory device: Methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam Generation) oxidization process is performed to form wall oxide films on sidewalls of the trenches. This process prohibits formation of facets at the... Agent: Marshall, Gerstein & Borun LLP

20080020546 - Process for interfacial adhesion in laminate structures through patterned roughing of a surface: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves,... Agent: Greenblum & Bernstein, P.L.C

20080020545 - Silicon-on-insulator semiconductor wafer: A method of fabricating a semiconductor-on-insulator semiconductor substrate is disclosed that includes providing first and second semiconductor substrates. Either oxygen or nitrogen is introduced into a region adjacent the surface of the first semiconductor substrate and a rare earth and hydrogen are implanted at different energy levels into the second... Agent: Robert A. Parsons

20080020547 - Method of transferring at least one object of micrometric or millimetric size by means of a polymer handle: The invention concerns a method for transferring at least one object of micrometric or millimetric size onto a host substrate by means of a handle. The method comprises the following steps: fixing a polymer handle on said object in order to be able to obtain a structure, constituted of the... Agent: Hayes Soloway P.C.

20080020548 - Wafer laser processing method: A wafer laser processing method for forming grooves along streets by applying a pulse laser beam along the streets for sectioning a plurality of devices of a wafer having the plurality of devices which are composed of a laminate consisting of an insulating film and a functional film, on the... Agent: Smith, Gambrell & Russell

20080020549 - Method and apparatus for forming an oxide layer on semiconductors: A method and apparatus for forming an oxide layer on semiconductors using a combination of ultraviolet rays and heat. The apparatus comprises a chamber having a top surface and a bottom surface and defining a wafer holding cavity; an ultraviolet source at the top surface of said chamber; an infrared... Agent: Kirkpatrick & Lockhart Preston Gates Ellis LLP (formerly Kirkpatrick & Lockhart Nicholson Graham)

20080020550 - Process for making thin film field effect transistors using zinc oxide: The present invention comprises a method of forming a zinc oxide based thin film transistor by blanket depositing the zinc