Semiconductor device manufacturing: process inventions 01/08

20080026487 - Method of forming an etch indicator layer for reducing etch non-uniformities: By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advantageously, the material may be incorporated by ion implantation which provides... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080026488 - Method and apparatus for detecting endpoint in a dry etching system by monitoring a superimposed dc current: A method and apparatus for detecting the endpoint in a dry plasma etching system comprising a first electrode (e.g., upper electrode) and a second electrode (e.g., lower electrode) upon which a substrate rests is described. A direct current (DC) voltage is applied between the first electrode and a ring electrode... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080026489 - Method and system for modeling statistical leakage-current distribution: Disclosed is a method and system for modeling statistical leakage current distribution using logarithmic skew-normal distribution by generating statistical data with a statistical analysis method based on Monte-Carlo simulations or based on a pre-characterization response modeling step for a plurality of representative chip-unit models, deriving a plurality of parameters from... Agent: Brinks Hofer Gilson & Lione

20080026491 - Method of wafer segmenting: A method of wafer segmenting is provided. Initially, a wafer having a plurality of devices on a top surface thereof is provided. A passivation layer is formed on the top surface of the wafer to cover the devices. A bottom surface of the first bonding layer is attached to a... Agent: North America Intellectual Property Corporation

20080026492 - Method of reducing contamination by providing a removable polymer protection film during microstructure processing: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective... Agent: Williams, Morgan & Amerson

20080026495 - Electromagnetic waveguide: A method of manufacturing an electromagnetic (EM) waveguide capable of guiding a wave along a pre-defined propagation path is described. The method includes providing a core region that extends along the propagation path and printing a colloidal crystal comprised of first particles on the waveguide core region.... Agent: Hewlett Packard Company

20080026494 - Method of fabricating a terbium-doped electroluminescence device via metal organic deposition processes: A method of fabricating an electroluminescent device includes preparing a wafer and a doped-silicon oxide precursor solution. The doped-silicon oxide precursor solution is spin coated onto the wafer to form a doped-silicon oxide thin film on the wafer, which is baked at progressively increasing temperatures. The wafer is then rapidly... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080026497 - Manufacturing method of light-emitting element: A manufacturing method of a light-emitting element includes emitting a laser light to a division region for separating a light-emitting element formed on a substrate, physically dividing the substrate along the division region, and removing a surface layer on at least one of the side faces of the substrate that... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080026496 - Method of making organic light emitting devices: The present invention provides a method for the preparation of organic light-emitting devices comprising a bilayer structure made by forming a first film layer comprising an electroactive material and an INP precursor material, and exposing the first film layer to a radiation source under an inert atmosphere to generate an... Agent: General Electric Company Global Research

20080026498 - Light emitting diode package element with internal meniscus for bubble free lens placement: A method for fabricating a light emitting diode (LED) package comprising providing an LED chip and covering at least part of the LED chip with a liquid encapsulant having a radius of curvature. An optical element is provided having a bottom surface with at least a portion having a radius... Agent: Koppel, Patrick & Heybl

20080026499 - Method for forming pattern, and method for manufacturing liquid crystal display: A method for forming a pattern, comprises: forming a bank film on a substrate; performing a lyophobic treatment on a surface of the bank film; patterning the bank film on which the lyophobic treatment has been performed to form a bank; performing a surface modification treatment in which a hydroxyl... Agent: Harness, Dickey & Pierce, P.L.C

20080026503 - On-chip sensor array for temperature management in integrated circuits: Embodiments of the invention provide methods and apparatus for managing temperature in integrated circuits. In accordance with an aspect of the invention, an integrated circuit comprises a monitored region defined by three or more edges. What is more, the integrated circuit comprises at least two temperature sensors for each of... Agent: Ryan, Mason & Lewis, LLP

20080026490 - Evaluation method using a teg, a method of manufacturing a semiconductor device having the teg, an element substrate and a panel having the teg, a program for controlling dosage and a computer-readable recording medium recording the program: The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped region. According to the present invention, plural TEGs... Agent: Nixon Peabody, LLP

20080026493 - Efficient method to predict integrated circuit temperature and power maps: The temperature distribution associated with a design of an integrated circuit is calculated by convoluting a surface power usage represented by a power matrix with a heat spreading function. The heat spreading function may be calculated from a simulation of a point source on the integrated circuit using a finite... Agent: Lumen Intellectual Property Services, Inc.

20080026500 - Flat panel display device and method for manufacturing the same: A flat panel display device includes a substrate including a pixel area having a plurality of pixel parts and a peripheral circuit area disposed adjacent to the pixel area to drive the pixel parts, a circuit TFT disposed in the peripheral circuit area, the circuit TFT including a first semiconductor... Agent: F. Chau & Associates, LLC

20080026501 - Method of manufacturing a light emitting device: A technique capable of efficient, high speed processing for the formation of an organic compound layer by using an ink jet method is provided. In the method of forming an organic compound layer by using the ink jet method, a composition containing an organic compound having light emitting characteristics is... Agent: Nixon Peabody, LLP

20080026502 - Growth of non-polar m-plane iii-nitride film using metalorganic chemical vapor deposition (mocvd): A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO2 or LiAlO2 substrate, using metalorganic chemical vapor deposition (MOCVD). The method includes performing a solvent clean and... Agent: Gates & Cooper LLP Howard Hughes Center

20080026504 - Solid-state image pickup device and manufacturing method for the same: A solid-state image pickup device includes, in a substrate, a plurality of photoelectric conversion regions for subjecting incoming light to photoelectric conversion, a reading gate for reading a signal charge from the photoelectric conversion regions, and a transfer register (vertical register) for transferring the signal charge read by the reading... Agent: Robert J. Depke Lewis T. Steadman

20080026505 - Electronic packages with roughened wetting and non-wetting zones: The flow of polymer formulations in in integrated circuit packages can be controlled by altering the roughness and surface chemistry of package surfaces. The surface roughness can be altered by forming protrusions having a dimension less than 500 nanometers and their chemistry can be controlled by chemical or plasma treatment.... Agent: Trop Pruner & Hu, PC

20080026506 - Semiconductor multi-chip package and fabrication method: A multi-chip package comprises a package substrate having bond fingers disposed thereon. A first chip have center bonding pads formed on a substantially center portion thereof. The first chip is disposed on the package substrate. Insulating support structures are formed on the first chip located outward of the bonding pads.... Agent: Marger Johnson & Mccollom, P.C.

20080026507 - Stack package using anisotropic conductive film (acf) and method of making same: Provided is a stack package using an anisotropic conductive film (ACF) for reducing thermal stresses exerted on chip scale packages (CSPs) during the initial manufacture of stack packages from a plurality of CSPs and for facilitating the repair and/or rework of stack packages incorporating CSPs while reducing the likelihood of... Agent: Harness, Dickey & Pierce, P.L.C

20080026509 - Cooling apparatuses and methods employing discrete cold plates compliantly coupled between a common manifold and electronics components of an assembly to be cooled: Cooling apparatuses and methods are provided for cooling an assembly including a planar support structure supporting multiple electronics components. The cooling apparatus includes: multiple discrete cold plates, each having a coolant inlet, coolant outlet and at least one coolant carrying channel disposed therebetween; and a manifold for distributing coolant to... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080026508 - Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a... Agent: Hitt Gaines, PC Lsi Corporation

20080026510 - Nonvolatile memory cell comprising a reduced height vertical diode: A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types... Agent: Dugan & Dugan, PC

20080026511 - Semiconductor device and method for manufacturing thereof: A method for manufacturing a semiconductor device includes: a) forming a first semiconductor layer which can be etched faster than a semiconductor substrate, on the semiconductor substrate including a first region that is arranged at a predetermined interval and is to be provided with a silicon on insulator (SOI) structure;... Agent: Advantedge Law Group, LLC

20080026512 - Integrated circuit chip with fets having mixed body thicknesses and method of manufacture thereof: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080026513 - Method and structure for self-aligned device contacts: Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080026514 - Method for producing nitride semiconductor device: A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen among a group consisting of nitrogen, phosphorus... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080026515 - Silicide block isolated junction field effect transistor source, drain and gate: An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among... Agent: Texas Instruments Incorporated

20080026517 - Method for forming a stressor layer: In one aspect, a method for forming a semiconductor device includes forming a stressor layer over a gate stack and a spacer adjacent the gate stack, implanting a species into at least a portion of the stressor layer, and curing the stressor layer. In another aspect, a method includes forming... Agent: Freescale Semiconductor, Inc. Law Department

20080026516 - Raised sti structure and superdamascene technique for nmosfet performance enhancement with embedded silicon carbon: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing... Agent: Whitham, Curtis & Christofferson, P.C.

20080026519 - Semiconductor devices and methods of fabricating the same: In a method of fabricating a semiconductor device, a first mask pattern is formed on a substrate. The first mask pattern has a first opening formed to expose the substrate. An oxidation barrier region is formed in the substrate exposed by the first opening, and the first mask pattern is... Agent: Harness, Dickey & Pierce, P.L.C

20080026518 - Spacer layer etch method providing enhanced microelectronic device performance: A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080026520 - Semiconductor method and device with mixed orientation substrate: In a method of forming a semiconductor device, a wafer includes a first semiconductor region of a first crystal orientation and a second semiconductor region of a second crystal orientation. Insulating material is formed over the wafer. A first portion of the insulating material is removed to expose the first... Agent: Slater & Matsil LLP

20080026521 - Method for manufacturing a transistor of a semiconductor device: A method for manufacturing a transistor of a semiconductor device is provided. The method includes the steps of: forming a gate over a semiconductor substrate including an NMOS transistor region and a PMOS transistor region; forming a photoresist pattern to open the gate of the PMOS transistor region; forming a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080026522 - High performance cmos device structures and method of manufacture: A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably,... Agent: International Business Machines Corporation Dept. 18g

20080026523 - Structure and method to implement dual stressor layers with improved silicide control: An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the... Agent: HorizonIPPte Ltd

20080026524 - Semiconductor device having a well structure for improving soft error rate immunity and latch-up immunity and a method of making such a device: A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain... Agent: Marger Johnson & Mccollom, P.C.

20080026525 - Semiconductor processing method and chemical mechanical polishing methods: This invention includes a chemical mechanical polishing method including providing a substrate having an organic material to be polished by chemical mechanical polishing. In one implementation, the organic material is chemical mechanically polished using a polishing pad downforce on the substrate of less than or equal to 1.75 psi, using... Agent: Wells St. John P.s.

20080026527 - An apparatus and associated method for making a floating gate memory device with increased gate coupling ratio: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate... Agent: Baker & Mckenzie LLP Patent Department

20080026526 - Method for removing nanoclusters from selected regions: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer.... Agent: Freescale Semiconductor, Inc. Law Department

20080026528 - Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080026531 - Field effect transistor and method of forming a field effect transistor: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080026530 - Method of forming a doped portion of a semiconductor and method of forming a transistor: A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion... Agent: Edell, Shapiro & Finnan, LLC

20080026529 - Transistor with asymmetry for data storage circuitry: A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region... Agent: Freescale Semiconductor, Inc. Law Department

20080026532 - Nano-enabled memory devices and anisotropic charge carrying arrays: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the... Agent: Nanosys Inc.

20080026533 - Semiconductor device and manufacturing method thereof: An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in... Agent: Mcdermott Will & Emery LLP

20080026534 - Self-aligned process for nanotube/nanowire fets: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention... Agent: Scully, Scott, Murphy & Presser, P.C.

20080026535 - Phase-changeable memory device and method of manufacturing the same: A phase changeable random access memory (PRAM) and methods for manufacturing the same. An example unit cell of a non-volatile memory, such as a PRAM, includes a MOS transistor, connected to an address line and a data line, where the MOS transistor receives a voltage from the data line. The... Agent: Harness, Dickey & Pierce, P.L.C

20080026536 - Integrated process for thin film resistors with silicides: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of the semiconductor... Agent: Fogg & Powers LLC

20080026537 - Method for forming capacitor of semiconductor device: A method for forming a capacitor of a semiconductor device includes forming a first capacitor in a storage node contact region to form a two-stage structured capacitor, thereby increasing the height and the capacitance of the capacitor.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080026538 - Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first... Agent: Myers Bigel Sibley & Sajovec

20080026539 - Capacitance element manufacturing method and etching method: An etching technique suitable for miniaturization is provided. An inorganic film is formed on an object to be subjected, the object having a lower electrode film, a dielectric film, and an upper electrode film laminated in that order on a substrate. A patterned organic resist film is disposed on the... Agent: Kratz, Quintos & Hanson, LLP

20080026540 - Integration for buried epitaxial stressor: Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the stressor layer. We form STI trenches down... Agent: HorizonIPPte Ltd

20080026541 - Air-gap interconnect structures with selective cap: A method of forming a semiconductor structure and the semiconductor structure. The method of manufacturing a structure includes applying a selective cap deposition to at least partially fill perforations, openings, or nano-holes formed above exposed portions of an interconnect during air-gap formation. The structure includes an insulator layer having the... Agent: Greenblum & Bernstein, P.L.C

20080026542 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is provided. According to an embodiment, a first opening is formed on a semiconductor substrate, and a sacrificial layer is formed to fill the first opening. Then, a second opening is formed on a region of the semiconductor substrate having the first opening.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080026543 - Method of manufacturing semiconductor device: A method of forming a semiconductor device is provided, including a step of forming a layer which absorbs light over one face of a first substrate, a step of providing a second substrate over the layer which absorbs light, a step of providing a mask to oppose the other face... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20080026544 - Method for improving the quality of an sic crystal and an sic semiconductor device: (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically... Agent: The Webb Law Firm, P.C.

20080026545 - Integrated devices on a common compound semiconductor iii-v wafer: A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to... Agent: Fish & Richardson P.C.

20080026546 - Crystal growth method and reactor design: A crystal growth process comprising providing a reactor having a crucible with an injector apparatus and a seed holder. The injector apparatus has an inner gas conduit and an outer gas conduit wherein an inert gas is introduced into the outer conduit. The injector apparatus has an upper injector and... Agent: Schnader Harrison Segal & Lewis, LLP

20080026547 - Method of forming poly-si pattern, diode having poly-si pattern, multi-layer cross point resistive memory device having poly-si pattern, and method of manufacturing the diode and the memory device: A method of forming a poly-silicon pattern may include forming an amorphous silicon pattern on a lower layer; forming a capping layer on the substrate covering the amorphous silicon pattern; poly-crystallizing the amorphous silicon pattern using an excimer laser annealing process; and removing the capping layer.... Agent: Harness, Dickey & Pierce, P.L.C

20080026548 - Film forming apparatus and film forming method: An optical film having a thin film stacked and optical characteristics close to design values is provided. In a vacuum chamber (2), a rotating drum (3) holding a substrate (4), an Si target (22) for forming a metal film on a film forming plane of the substrate (4), a Ta... Agent: Arent Fox LLP

20080026549 - Methods of controlling morphology during epitaxial layer formation: A first aspect of the invention provides a method of selectively forming an epitaxial layer on a substrate. The method includes heating the substrate to a temperature of less than about 800° C. and employing both silane and dichlorosilane as silicon sources during epitaxial film formation. Numerous other aspects are... Agent: Dugan & Dugan, PC

20080026550 - Laser doping of solid bodies using a linear-focussed laser beam and production of solar-cell emitters based on said method: In the laser doping method in accordance with the invention firstly a medium containing a dopant is brought into contact with a surface of the solid-state material. Then, by beaming with laser pulses, a region of the solid-state material below the surface contacted by the medium is melted so that... Agent: Straub & Pokotylo

20080026551 - Formation of fully silicided metal gate using dual self-aligned silicide process: An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also... Agent: Scully, Scott, Murphy & Presser, P.C.

20080026552 - Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography: In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the... Agent: Williams, Morgan & Amerson

20080026553 - Method for fabricating an integrated gate dielectric layer for field effect transistors: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing... Agent: Patterson & Sheridan, LLP

20080026556 - Barrier process/structure for transistor trench contact applications: A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration... Agent: Lee & Hayes, PLLC C/o Intellevate

20080026554 - Interconnect structure for beol applications: A semiconductor interconnect structure is provided that includes a new capping layer/dielectric material interface which is embedded inside the dielectric material. In particular, the new interface is an air gap that is located in the upper surface of a dielectric material that is adjacent to a conductive region or feature.... Agent: Scully, Scott, Murphy & Presser, P.C.

20080026555 - Sacrificial tapered trench opening for damascene interconnects: A method for forming a trench with a flared opening in a dielectric layer comprises providing a semiconductor substrate having a dielectric layer deposited thereon, depositing and patterning a photoresist layer atop the dielectric layer to form at least two photoresist structures, applying a plasma etch to define a flared... Agent: Intel Corporation C/o Intellevate, LLC

20080026557 - Electronic system modules and method of fabrication: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection... Agent: Townsend And Townsend And Crew, LLP

20080026558 - Pad structure for liquid crystal display and method of manufacturing thereof: A liquid crystal display has a pad structure. The pad structure includes at least one pad formed on a substrate, an insulating film formed on the pad, and at least one conductive layer connected to the pad through contact holes defined through the insulating film. The insulating film covers side... Agent: Mckenna Long & Aldridge LLP

20080026560 - Methods of forming electronic structures including conductive shunt layers and related structures: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the... Agent: Myers Bigel Sibley & Sajovec

20080026559 - Solder ball pad structure: An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact... Agent: Texas Instruments Incorporated

20080026561 - Methods of trench and contact formation in memory cells: Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20080026562 - Novel metallization scheme and method of manufacture therefor: The present invention provides a metallization scheme, a method for manufacturing the metallization scheme, and an integrated circuit including the metallization scheme. In one aspect, the metallization scheme (300) includes a protective layer (320) located over a substrate (310), and a conductive layer (330) located over the protective layer (320).... Agent: Texas Instruments Incorporated

20080026563 - Semiconductor device manufacturing device: A process for production of a semiconductor device having a multi-layer wiring of dual damascene structure in a low-dielectric constant interlayer insulating film. The process consists of the following steps. A first insulating film and a second insulating film are formed. A first to third mask forming layers are formed.... Agent: Sonnenschein Nath & Rosenthal LLP

20080026564 - Method of forming an electrically conductive line in an integrated circuit: A method of forming a semiconductor structure comprises providing a semiconductor structure comprising a layer of a dielectric material provided over an electrically conductive feature. An opening is formed in the layer of dielectric material. The opening is located over the electrically conductive feature and has a first lateral dimension.... Agent: J. Mike Amerson, Williams, Morgan & Amerson , P.C.

20080026566 - Dual damascene interconnect structures having different materials for line and via conductors: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner... Agent: International Business Machines Corporation Dept. 18g

20080026567 - Increasing electromigration lifetime and current density in ic using vertically upwardly extending dummy via: An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the... Agent: Hoffman, Warnick & D'alessandro LLC

20080026565 - Method of manufacturing a composite of copper and resin: A metallic copper and resin composite body manufacturing method of forming a copper wiring layer that forms an inner layer circuit, establishing an insulating layer with a resin on said wiring layer, forming via holes which expose the copper surface under the insulative layer, and depositing a metal on the... Agent: John J. Piskorski Rohm And Haas Electronic Materials LLC

20080026568 - Interconnect structure and process of making the same: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings... Agent: International Business Machines Corporation Dept. 18g

20080026569 - Advanced seed layers for interconnects: One embodiment of the present invention is a method for making metallic interconnects over a substrate, the substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the at least one opening has sidewalls and bottom and a width... Agent: Uri Cohen

20080026570 - Method of forming a metal line of a semiconductor memory device: A method of forming a metal line of a semiconductor memory device is disclosed. An interlayer insulating layer, an etch-stop layer, a trench oxide layer, a hard mask layer and a photoresist layer are laminated over a semiconductor substrate in which a contact is formed. An exposure process is performed... Agent: Townsend And Townsend And Crew, LLP

20080026571 - Bit line barrier metal layer for semiconductor device and process for preparing the same: The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing... Agent: Marshall, Gerstein & Borun LLP

20080026572 - Method for forming a strained transistor by stress memorization based on a stressed implantation mask: By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20080026573 - Method of producing active matrix substrate: The invention provides a production method for an active matrix substrate in which a plurality of contact holes are formed by a one-mask process so as to reach metal films which are present at different depth positions in an insulating layer and are not evaporated by dry etching using a... Agent: Sughrue Mion, PLLC

20080026574 - Method and apparatus of distributed plasma processing system for conformal ion stimulated nanoscale deposition process: A deposition system and method of operating thereof is described for depositing a conformal metal or other similarly responsive coating material film in a high aspect ratio feature using a high density plasma is described. The deposition system includes a plasma source, and a distributed metal source for forming plasma... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20080026575 - Dispenser system for atomic beam assisted metal organic chemical vapor deposition (mocvd): A dispenser system for use in atomic beam assisted metal organic chemical vapor deposition is provided as well as a method of depositing an ultra-thin film using the same. The inventive dispenser system includes an atomic source having an unimpeded line of site to a substrate and an annular metal... Agent: Scully, Scott, Murphy & Presser, P.C.

20080026576 - Organometallic compounds: Certain organometallic compounds in the form of imino complexes are provided. Such complexes are particularly suitable for use as vapor deposition precursors. Also provided are methods of depositing thin films, such as by ALD and CVD, using such compounds.... Agent: Rohm And Haas Electronic Materials LLC

20080026577 - Organometallic compounds: Organometallic compounds containing a phosphoamidinate ligand are provided. Such compounds are particularly suitable for use as vapor deposition precursors. Also provided are methods of depositing thin films, such as by ALD and CVD, using such compounds.... Agent: Rohm And Haas Electronic Materials LLC

20080026578 - Organometallic compounds: Organometallic compounds containing an electron donating group-substituted alkenyl ligand are provided. Such compounds are particularly suitable for use as vapor deposition precursors. Also provided are methods of depositing thin films, such as by ALD and CVD, using such compounds.... Agent: Rohm And Haas Electronic Materials LLC

20080026579 - Copper damascene process: A copper damascene process includes providing a substrate having a dielectric layer thereon, forming at least a copper damascene structure in the dielectric layer, performing a heat treatment on the substrate, and performing a reduction plasma treatment on a surface of the copper damascene structure. The impurities formed in the... Agent: North America Intellectual Property Corporation

20080026580 - Method for forming copper metal lines in semiconductor integrated circuit devices: A method of forming copper metal lines capable of improving surface coatability without forming overhangs of a diffusion barrier film for preventing diffusion of copper in an upper portion of a hole and preventing formation of a copper void is disclosed. The method includes coating a lower layer on a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080026581 - Flexible substrate with electronic devices formed thereon: A method of manufacturing an electronic device (10) provides a substrate (20) that has a plastic material. A particulate material (16) is embedded in at least one surface of the substrate. A layer of thin-film semiconductor material is deposited onto the substrate (20).... Agent: Mark G. Bocchetti Patent Legal Staff

20080026582 - Planarization process for pre-damascene structure including metal hard mask: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP... Agent: Jianq Chyun Intellectual Property Office

20080026583 - Compositions and methods for modifying a surface suited for semiconductor fabrication: The disclosure pertains to compositions and methods for modifying or refining the surface of a wafer suited for semiconductor fabrication. The compositions include working liquids useful in modifying a surface of a wafer suited for fabrication of a semiconductor device. In some embodiments, the working liquids are aqueous solutions of... Agent: 3m Innovative Properties Company

20080026584 - Lpcvd gate hard mask: A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate... Agent: Patterson & Sheridan, LLP

20080026585 - Composition for removing a film, method of removing a film using the same, and method of forming a pattern using the same: A film (e.g., silicon polymer film, photoresist film) may be removed by applying a composition including a quaternary ammonium hydroxide, a sulfoxide compound, a dialkylene glycol alkyl ether, and/or water to the film. A silicon polymer film (e.g., hard mask layer) and a photoresist film, for example, may be removed... Agent: Harness, Dickey & Pierce, P.L.C

20080026586 - Phase change memory cell and method and system for forming the same: For fabricating a phase change memory cell, a layer of phase change material and a layer of a first electrode material are deposited. In addition, the first electrode material is patterned using an etchant including a low-reactivity halogen element such as bromine or iodine to form a first electrode. By... Agent: Law Office Of Monica H Choi

20080026587 - Semiconductor device: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be... Agent: Sherr & Nourse, PLLC

20080026588 - Method of forming inductor in semiconductor device: Disclosed herein is a method of forming an inductor in a semiconductor device, the method including forming an etching-prevention film, a first interlayer insulating film, and a first hard mask film over a silicon semiconductor substrate in this sequence; selectively etching the first hard mask film to form a hole;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080026589 - Electrode for plasma processes and method for manufacture and use thereof: A silicon electrode for a plasma reaction chamber wherein processing of a semiconductor substrate such as a single wafer can be carried out and a method of processing a semiconductor substrate with the electrode. The electrode is a low resistivity electrode having an electrical resistivity of less than 1 ohm-cm.... Agent: Buchanan, Ingersoll & Rooney PC

20080026590 - Metal organic deposition precursor solution synthesis and terbium-doped sio2 thin film deposition: A method of making a doped silicon oxide thin film using a doped silicon oxide precursor solution includes mixing a silicon source in an organic acid and adding 2-methoxyethyl ether to the silicon source and organic acid to from a preliminary precursor solution. The resultant solution is heated, stirred and... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20080026591 - Sintered metal components for crystal growth reactors: An injector apparatus for a crystal growth reactor having a graphite casing, a stainless steel nozzle, a nozzle holder to position the nozzle within the graphite casing, a lower injector disposed within the graphite casing and extending around the nozzle to a point above the nozzle to direct gas flow... Agent: Schnader Harrison Segal & Lewis, LLP

20080026592 - Multilayer substrate: A multilayer substrate device formed from a base substrate and alternating metalization layers and dielectric layers. Each layer is formed without firing. Vias may extend through one of the dielectric layers such that two metalization layers surrounding the dielectric layers make contact with each other. The vias may be formed... Agent: Foley & Lardner

20080026593 - Method and apparatus for the manufacture of electric circuits: A method of manufacturing a patterned electric circuit. The method comprises the steps of providing a cold gas-dynamic spraying (CGDS) device, providing a substrate, and depositing a pattern of electrically conductive material with the CGDS device on the substrate by relative movement between the CGDS device to the substrate.... Agent: Welsh & Flaxman LLC

20080026594 - Reduction of cracking in low-k spin-on dielectric films: The present invention relates to a process that minimizes the cracking of low-k dielectric polymers. In an example embodiment, on a semiconductor substrate (200), there is a method of forming a composite dielectric disposed on a metal layer passivated with plasma deposited silicon oxide SiOx. The method comprises depositing depositing... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080026595 - Method of forming an integrated circuit having a device wafer with a diffused doped backside layer: A method for forming a diffused, doped backside layer on a device wafer oxide bonded to a handle wafer in an integrated circuit is provided. The method comprises forming a thermal bond oxide layer on a backside surface of the device wafer of the integrated circuit. Implanting the bond oxide... Agent: Fogg & Powers LLC

20080026596 - Method of forming metallic oxide films using atomic layer deposition: Example embodiments are directed to methods of forming a metallic oxide film using Atomic Layer Deposition while controlling the power reflected by a reactor. The method may include feeding metallic source gases, for example, first and second metallic source gases, and/or a reactant gas including oxygen into the reactor individually.... Agent: Harness, Dickey & Pierce, P.L.C

20080026597 - Method for depositing and curing low-k films for gapfill and conformal film applications: Methods of making a silicon oxide layer on a substrate are described. The methods may include forming the silicon oxide layer on the substrate in a reaction chamber by reacting an atomic oxygen precursor and a silicon precursor and depositing reaction products on the substrate. The atomic oxygen precursor is... Agent: Townsend And Townsend And Crew LLP / Amat

20080026598 - Semiconductor manufacturing device and method: A semiconductor manufacturing device and a method thereof capable of processing semiconductor substrates having a large diameter in a state that the semiconductor substrates keep standing and are opposed to each other are disclosed. The semiconductor manufacturing device includes a reaction chamber for providing an airtight process space; a boat... Agent: Ditthavong Mori & Steiner, P.C.

20080026599 - Transfer of stress to a layer: A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric... Agent: Freescale Semiconductor, Inc. Law Department

20080020490 - Method for manufacturing ferroelectric memory: A method for manufacturing a ferroelectric memory includes the steps of: (a) forming a ferroelectric capacitor by sequentially laminating, on a substrate, a lower electrode, a ferroelectric layer and an upper electrode; (b) forming a first dielectric layer that covers the ferroelectric capacitor; (c) forming a contact hole in the... Agent: Harness, Dickey & Pierce, P.L.C

20080020489 - Methods of fabricating ferroelectric devices: A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.... Agent: Myers Bigel Sibley & Sajovec

20080020488 - Semiconductor integrated circuit devices having high-q wafer backside inductors and methods of fabricating same: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside... Agent: F. Chau & Associates, LLC

20080020494 - Film formation apparatus, precursor introduction method and film formation method: The present invention is to use a film formation apparatus having: a film formation chamber; a preparation device for preparing a solid precursor solution by dissolving the solid precursor in supercritical carbon dioxide; a first supercritical carbon dioxide feeding line for feeding supercritical carbon dioxide into the preparation device; a... Agent: Young & Thompson

20080020497 - Method for evaluating quality of semiconductor substrate and method for manufacturing semiconductor substrate: Methods for evaluating a quality of a semiconductor substrate. In one aspect, etching a surface of the semiconductor substrate by dry-etching, detecting bright points on the surface of the etched surface with a foreign matter inspection device, and evaluating the quality of the semiconductor substrate based on the number and/or... Agent: Greenblum & Bernstein, P.L.C

20080020502 - Method for manufacturing semiconductor optical device: A method for manufacturing a laser diode includes: providing a semiconductor structure in which semiconductor layers are laminated; forming a waveguide ridge in the layers; forming an SiO2 film over the entire surface; forming a second resist pattern covering the SiO2 film in channels adjacent the waveguide ridge such that... Agent: Leydig Voit & Mayer, Ltd

20080020504 - Sensors for detecting nox in a gas and methods for fabricating the same: Nitrogen oxide sensors and methods for fabricating them are provided. According to an exemplary embodiment of the present invention, the method comprises providing an electrically insulating substrate having a first surface and a second surface. Two electrodes are fabricated on the first surface of the substrate. Each of the electrodes... Agent: Honeywell International Inc.

20080020506 - Method for forming color filter: A method for forming a color filter is provided. The method comprises steps of providing a substrate having a passivasion layer formed thereon. The substrate has at least one complementary metal-oxide semiconductor formed therein and the passivasion layer has at least trench formed therein in a peripheral region of the... Agent: Jianq Chyun Intellectual Property Office

20080020507 - Method for manufacturing semiconductor integrated circuit device: Due to a difference in a film thickness generated in structure layers located on top of a light receiver, a bottom surface of an open part does not flatten and an amount of incident light within a surface of the light receiver becomes nonuniform. A flat layer is formed by... Agent: Oliff & Berridge, PLC

20080020487 - Alignment of carbon nanotubes on a substrate via solution deposition: Carbon nanotubes, associated with a charged dispersant are aligned on a substrate by deposition on the substrate directly from solution. Preferred dispersants are charged polymers such as biopolymers.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20080020492 - Ferroelectric memory and its manufacturing method: A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above... Agent: Harness, Dickey & Pierce, P.L.C

20080020491 - Magneticially lined conductors: A method of making a conductor with improved magnetic field per current ratio is disclosed. The conductor includes a magnetic liner lining a second surface and sides thereof. The magnetic liner is preferably a super-paramagnet with high susceptibility or a ferromagnet with a microstructure where the size of the non-exchanged... Agent: Ference & Associates LLC

20080020493 - Apparatus for supplying chemical, semiconductor manufacturing apparatus having the same, and method for supplying chemical: Embodiments disclosed herein are generally directed to a chemical supplying apparatus, a semiconductor manufacturing equipment having the same and a method for supplying chemicals. The apparatus includes a tank, a first sensor, and a second sensor. The tank is filled with a liquid chemical and includes an outlet for the... Agent: Marger Johnson & Mccollom, P.C.

20080020495 - Semiconductor fabricating apparatus with function of determining etching processing state: A semiconductor fabricating method including: placing the semiconductor wafer having a film thereon inside of a chamber; generating plasma; detecting a quantity of interference lights for each of at least two wavelengths obtained from a surface of the wafer for a predetermined time period during the etching of the wafer;... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080020498 - Fabrication method of semiconductor integrated circuit device: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080020496 - Method of evaluating thermal treatment and method of manufacturing semiconductor wafer: Provided are the methods of evaluating thermal treatment. In the methods, a wafer comprising a silicon substrate having an oxygen concentration of approximately equal to or less than 1.0×1018 atoms/cm3 and a silicon epitaxial layer on at least one surface of the substrate is employed.... Agent: Greenblum & Bernstein, P.L.C

20080020499 - Nanotube assembly including protective layer and method for making the same: Nanotube assemblies and methods for manufacturing the same, including one or more protective layers. A nanotube assembly may include a substrate, a nanotube array, formed on the substrate, and a protective layer, formed on a first area of the substrate where the nanotube array is not, the protective layer reducing... Agent: Harness, Dickey & Pierce, P.L.C

20080020500 - Flat panel display and method of fabricating the same: A light-emitting display device the same includes an insulating substrate having a thin film transistor formed thereon. The thin film transistor includes a source electrode and/or a drain electrode. A passivation layer is formed on the insulating substrate over at least a portion of the thin film transistor, and has... Agent: H.c. Park & Associates, PLC

20080020501 - Liquid crystal display device and a manufacturing method of the same: A four-mask process and a three-mask process proposal are constructed for a TN-type liquid crystal display device and an IPS-type liquid crystal device in which the formation of a passivation insulating layer is not required by streamlining the formation of a scan line and a pseudo-pixel element, both comprising a... Agent: Bacon & Thomas, PLLC

20080020503 - Series interconnected optoelectronic device module assembly: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One... Agent: Nanosolar, Inc.

20080020505 - Packaged microelectronic imagers and methods of packaging microelectronic imagers: Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried... Agent: Dickstein Shapiro LLP

20080020508 - Reducing oxidation of phase change memory electrodes: A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped... Agent: Trop Pruner & Hu, PC

20080020509 - Thin film materials of amorphous metal oxides: Amorphous metal oxide thin film is produced by removing through oxygen plasma treatment the organic component from an organics/metal oxide composite thin film having thoroughly dispersed therein such organic component at molecular scale. This ensures production of amorphous metal oxide thin film with low density and excellent thickness precision.... Agent: Birch Stewart Kolasch & Birch

20080020510 - Fabrication method of semiconductor device: A technique able to effect automation of a molding process corresponding to a multifarious small lot semiconductor device manufacturing process is provided. As to a frame supply unit, a lead frame conveying unit and molding press sets, which are each operated by a motor within a molding apparatus, the amount... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080020511 - Structure of image sensor module and a method for manufacturing of wafer level package: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises a metal alloy base, a wafer level package, a lens holder, and flexible printed circuits (F.P.C.). The wafer level package having a plurality of image sensor dice and a plurality... Agent: Bacon & Thomas, PLLC

20080020512 - Method for making a semiconductor multi-package module having inverted wire bond carrier second package: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a wire bond... Agent: Law Offices Of Mikio Ishimaru

20080020513 - Method of fabricating semiconductor device having conducting portion of upper and lower conductive layers on a peripheral surface of the semiconductor device: A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080020514 - Method for producing bonded wafer: A bonded wafer is produced by a method comprising a step of implanting ions of a light element such as hydrogen, helium or the like into a wafer for active layer at a predetermined depth position to form an ion implanted layer, a step of bonding the wafer for active... Agent: Sughrue Mion, PLLC

20080020515 - Twisted dual-substrate orientation (dso) substrates: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer... Agent: Hamilton & Terrile, LLP

20080020516 - Method for attaching ic tag, article with ic tag attached, and ic tag: The present invention provides a method for attaching an IC tag. In the method, an IC tag performing wireless communication using an electronic component appropriately disposed is attached to an article made from an elastically deformable material. Specifically, the IC tag is attached to a predetermined portion of the article,... Agent: Dickstein Shapiro LLP

20080020517 - Multi lead frame power package: According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed within the mold compound, and in operation generates thermal energy. The first lead frame is... Agent: Texas Instruments Incorporated

20080020518 - Liquid crystal display panel: A laminated spacer portion formed by laminating various thin films that constitute thin-film transistors is disposed in peripheral driver circuits. As a result, even in a structure in which part of a sealing member is disposed above the peripheral driver circuits, pressure exerted from spacers in the sealing member is... Agent: Fish & Richardson P.C.

20080020519 - Ltps-lcd structure and method for manufacturing the same: An LTPS-LCD structure and a method for manufacturing the structure are provided. The structure comprises a substrate where a plurality of pixels are formed thereon. Each of these pixels comprises a control area, a capacitance area, and a display area. The structure is initially formed with a transparent electrode on... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080020520 - Method for manufacturing lower substrate of liquid crystal display device: A method for improving the tapered angles of the insulating layer and the semiconductor layer of a lower substrate of a thin film transistor liquid crystal display device is disclosed. The method mainly applies an etching gas including a sulfur fluoride compound to etch the insulating layer. After etching, the... Agent: Bacon & Thomas, PLLC

20080020521 - Hybrid substrate technology for high-mobility planar and multiple-gate mosfets: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper... Agent: Scully, Scott, Murphy & Presser, P.C.

20080020522 - Field effect transistors with dielectric source drain halo regions and reduced miller capacitance: A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed... Agent: Cantor Colburn LLP - IBM Fishkill

20080020523 - Method of fabricating complementary metal-oxide-semiconductor transistor and metal-oxide-semiconductor transistor: A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides... Agent: J.c. Patents, Inc.

20080020524 - Process for controlling performance characteristics of a negative differential resistance (ndr) device: A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with... Agent: Bever, Hoffman & Harms, LLP

20080020526 - Method and system for determining semiconductor characteristics: Method and system for determining semiconductor characteristics. In a specific embodiment, the present invention provides a method for determining one or more characteristics of a partially processed integrated circuit. The method includes a step for providing a substrate material. The method further includes a step for forming at least one... Agent: Townsend And Townsend And Crew, LLP

20080020525 - Method for fabricating semiconductor device: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in... Agent: J C Patents, Inc.

20080020527 - Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell: A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a programming operation, electrons... Agent: Marger Johnson & Mccollom, P.C.

20080020528 - Method of manufacturing semiconductor device and method of manufacturing nonvolatile semiconductor storage device: An object is to provide a technique for manufacturing an insulating layer with favorable withstand voltage. Another object is to provide a technique for manufacturing a semiconductor device having an insulating layer with favorable withstand voltage. By subjecting a semiconductor layer or semiconductor substrate mainly containing silicon to a high... Agent: Eric Robinson

20080020529 - Non-volatile memory and fabrication thereof: A non-volatile memory cell is described, including a semiconductor body of a first conductivity type, a trapping layer, a gate, and a first to a third doped regions of a second conductivity type. The semiconductor body has a trench thereon, the trapping layer is disposed on the surface of the... Agent: J.c. Patents

20080020530 - Manufacturing method of semiconductor device and semiconductor device: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; forming a second member to be patterned on the first member; forming a third member to be patterned on the second member; patterning the third member to form a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080020531 - Semiconductor devices having torsional stresses: A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of... Agent: International Business Machines Corporation Dept. 18g

20080020532 - Transistor with a channel comprising germanium: A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and... Agent: Docket Clerk

20080020533 - Method and apparatus for semiconductor device with improved source/drain junctions: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the... Agent: Slater & Matsil, L.L.P.

20080020534 - Semiconductor device fabrication methods: Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the workpiece between at least two of the plurality of active area... Agent: Slater & Matsil LLP

20080020535 - Silicide cap structure and process for reduced stress and improved gate sheet resistance: A silicide cap structure and method of fabricating a silicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and... Agent: Scully, Scott, Murphy & Presser, P.C.

20080020536 - Transistor structure with recessed source/drain and buried etch stop layer and related method: A transistor structure having a recessed source/drain and buried etch stop layer (e.g., a silicon germanium layer), and a related method, are disclosed. In one embodiment, the transistor structure includes a substrate including a substantially trapezoidal silicon pedestal over an etch stop layer; a gate atop the substantially trapezoidal silicon... Agent: Hoffman, Warnick & D'alessandro LLC

20080020537 - Method of fabricating field effect transistor (fet) having wire channels: In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns... Agent: Lee & Morse, P.C.

20080020538 - One mask high density capacitor for integrated circuits: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides... Agent: Texas Instruments Incorporated

20080020539 - Dynamic random access memory and fabrication method thereof: A dynamic random access memory including a substrate, an isolation structure, two transistors, two trench capacitors and two passing gates is provided. The isolation structure, including a first isolation structure and a second isolation structure, is disposed in the substrate. The second isolation structure is disposed in the substrate above... Agent: J.c. Patents

20080020540 - Manufacturing method of semiconductor device: The present invention provides an MIM capacitor using a high-k dielectric film preventing degradation of breakdown field strength of the MIM capacitor and suppressing the increase of the leakage current. The MIM capacitor comprises a first metal interconnect, a fabricated capacitance film, a fabricated upper electrode, and a third metal... Agent: Miles & Stockbridge PC

20080020541 - Method for manufacturing bonded soi wafer and bonded soi wafer manufactured thereby: A bonded SOI wafer is manufactured by performing bonding in a state where organics exist on a surface of an active layer wafer and/or on a surface of a supporting wafer and performing heat-treating for bonding reinforcement in a state where the organics are trapped at an interface between the... Agent: Clark & Brody

20080020542 - Semiconductor devices and methods of manufacture thereof: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer... Agent: Slater & Matsil LLP

20080020543 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device according to an embodiment includes: forming a trench for a device isolation area and a semiconductor projection with a first width by etching a semiconductor substrate; forming an oxide film on the trench and the semiconductor projections; forming an insulating layer on the... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080020544 - Method for forming wall oxide layer and isolation layer in flash memory device: Methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam Generation) oxidization process is performed to form wall oxide films on sidewalls of the trenches. This process prohibits formation of facets at the... Agent: Marshall, Gerstein & Borun LLP

20080020546 - Process for interfacial adhesion in laminate structures through patterned roughing of a surface: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves,... Agent: Greenblum & Bernstein, P.L.C

20080020545 - Silicon-on-insulator semiconductor wafer: A method of fabricating a semiconductor-on-insulator semiconductor substrate is disclosed that includes providing first and second semiconductor substrates. Either oxygen or nitrogen is introduced into a region adjacent the surface of the first semiconductor substrate and a rare earth and hydrogen are implanted at different energy levels into the second... Agent: Robert A. Parsons

20080020547 - Method of transferring at least one object of micrometric or millimetric size by means of a polymer handle: The invention concerns a method for transferring at least one object of micrometric or millimetric size onto a host substrate by means of a handle. The method comprises the following steps: fixing a polymer handle on said object in order to be able to obtain a structure, constituted of the... Agent: Hayes Soloway P.C.

20080020548 - Wafer laser processing method: A wafer laser processing method for forming grooves along streets by applying a pulse laser beam along the streets for sectioning a plurality of devices of a wafer having the plurality of devices which are composed of a laminate consisting of an insulating film and a functional film, on the... Agent: Smith, Gambrell & Russell

20080020549 - Method and apparatus for forming an oxide layer on semiconductors: A method and apparatus for forming an oxide layer on semiconductors using a combination of ultraviolet rays and heat. The apparatus comprises a chamber having a top surface and a bottom surface and defining a wafer holding cavity; an ultraviolet source at the top surface of said chamber; an infrared... Agent: Kirkpatrick & Lockhart Preston Gates Ellis LLP (formerly Kirkpatrick & Lockhart Nicholson Graham)

20080020550 - Process for making thin film field effect transistors using zinc oxide: The present invention comprises a method of forming a zinc oxide based thin film transistor by blanket depositing the zinc oxide layer and the source-drain metal layer and then wet etching through the zinc oxide while etching through the source-drain electrode layer. Thereafter, the active channel is formed by dry... Agent: Patterson & Sheridan, LLP

20080020552 - Semiconductor substrates having low defects and methods of manufacturing the same: A semiconductor substrate includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. At least one amorphous region and at least one crystalloid region are formed in the first... Agent: Harness, Dickey & Pierce, P.L.C

20080020553 - Dielectric vcsel gain guide: A vertical cavity surface emitting laser having a dielectric gain guide. The gain guide may provide current confinement, device isolation and possibly optical confinement. The first mirror and an active region may be grown. A pattern may be placed on or near the active region. A dielectric material may be... Agent: Workman Nydegger

20080020551 - Methods for preserving strained semiconductor substrate layers during cmos processing: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad... Agent: Goodwin Procter LLP Patent Administrator

20080020555 - Method for manufacturing semiconductor device: It is an object to provide a method of manufacturing a crystalline silicon device and a semiconductor device in which formation of cracks in a substrate, a base protective film, and a crystalline silicon film can be suppressed. First, a layer including a semiconductor film is formed over a substrate,... Agent: Eric Robinson

20080020554 - Method for manufacturing semiconductor device: [Structure] A crystalline silicon film having improved crystallinity is obtained by the following steps: forming a silicon nitride film substantially in contact with an amorphous silicon film on glass substrate; introducing a catalyst element such as nickel; performing an annealing treatment at a temperature of 500 to 600° C. for... Agent: Nixon Peabody, LLP

20080020556 - Semiconductor device and method for fabricating the same: Provided is a method for fabricating a semiconductor device. In the method, a poly layer on a semiconductor substrate is etched to a predetermined depth. Ions are implanted into the poly layer at a predetermined angle. The poly layer is etched again to expose a portion of the semiconductor substrate.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20080020557 - Method for forming transistor of semiconductor device using double patterning technology: A method for forming a transistor of a semiconductor device comprises: forming an isolation film over a semiconductor substrate to define an active region; forming a first recess in an active region (one side) between the isolation films; forming a second recess having the same size as that of the... Agent: Townsend And Townsend And Crew, LLP

20080020558 - multi-step process for patterning a metal gate electrode: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on... Agent: Texas Instruments Incorporated

20080020559 - Pad structure design with reduced density: An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different... Agent: Duane Morris LLPIPDepartment (tsmc)

20080020560 - Method for manufacturing fuse box having vertically formed protective film: A method for manufacturing a fuse box of a semiconductor device includes forming an interlayer dielectric film over a semiconductor substrate including a given lower structure; forming a metal line and a fuse over the interlayer dielectric film; forming a first protective film over the resulting structure; etching the first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080020561 - Ball capturing apparatus, solder ball disposing apparatus, ball capturing method, and solder ball disposing method: The present invention relates to a ball capturing apparatus and method of capturing one ball from plural balls having the same size, and to a solder ball disposing apparatus and method of disposing a solder ball containing solder in a predetermined position on a circuit board, thereby reliably capturing one... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080020562 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device of the present invention includes a step (S100) of judging whether an interconnect pitch of an interconnect pattern having the smallest interconnect pitch out of all interconnect patterns to be formed in the insulating film is not larger than a predetermined value or... Agent: Mcginn Intellectual Property Law Group, PLLC

20080020563 - Protective film structure: A protective film structure (100) includes a base (110) and a resistive film (120) formed on a surface of the base. The base is comprised of amorphous boron nitride or amorphous boron carbide, and is formed on a surface of a substrate (10) to be protected. The resistive film includes... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080020564 - Methods of forming a semiconductor device including a phase change material layer: A method includes forming a phase change material layer on a substrate using a deposition process that employs a process gas. The process gas includes a germanium source gas, and the germanium source gas includes at least one of the atomic groups “—N═C═O”, “—N═C═S”, “—N═C═Se”, “—N═C═Te”, “—N═C═Po” and “—C≡N”.... Agent: Volentine & Whitt PLLC

20080020565 - Dual damascene copper process using a selected mask: A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene... Agent: Townsend And Townsend And Crew, LLP

20080020566 - Method of making an interposer: A method of making an interposer in which at least two dielectric layers are bonded to each other to sandwich a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts which are formed within and protrude from openings which are also formed within... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20080020567 - Method of manufacturing a semiconductor device: Provided are methods of manufacturing a semiconductor device. Some embodiments of such methods may include forming a preliminary gate pattern on a substrate. The preliminary gate pattern may include silicon. Methods may include forming an insulation layer pattern on the substrate after forming the preliminary gate pattern. The insulation layer... Agent: Myers Bigel Sibley & Sajovec

20080020568 - Semiconductor device having a silicide layer and method of fabricating the same: A method of fabricating a semiconductor device having a silicide layer, including forming an interlayer insulating layer on an entire surface of a semiconductor substrate, forming a contact hole in the interlayer insulating layer, sequentially forming a silicide material and a barrier metal layer over the interlayer insulating layer including... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080020569 - Method for manufacturing semiconductor device: Provided is a method for manufacturing a semiconductor device. In the method, photoresist patterns having a first width are formed on a semiconductor substrate, and the semiconductor substrate is etched using the photoresist patterns as a mask to form a semiconductor protrusion portion. An oxide layer is formed on an... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080020570 - Dual damascene fabrication with low k materials: The invention provides methods and apparatuses for fabricating a dual damascene structure on a substrate. First, trench lithography and trench patterning are performed on the surface of a substrate to etch a low-k dielectric material layer to a desired etch depth to form a trench prior to forming of a... Agent: Patterson & Sheridan, LLP

20080020571 - Dense seed layer and method of formation: Methods of forming dense seed layers and structures thereof are provided. Seed layers including a monolayer of molecules having a density of about 0.5 or greater may be manufactured over a metal layer, resulting in a well-defined interface region between the metal layer and a subsequently formed material layer. A... Agent: Ira S. Matsil Slater & Matsil, L.L.P.

20080020572 - Electrically conductive feature fabrication process: A process for fabricating an electrically conductive feature comprising: (a) liquid depositing a low viscosity composition comprising starting ingredients including an organic anine, a silver compound, and optionally an organic acid, to result in a deposited composition; and (b) heating the deposited composition, resulting in the electrically conductive feature comprising... Agent: Patent Documentation Center

20080020574 - Hybrid rf capacitively and inductively coupled plasma source using multifrequency rf powers and methods of use thereof: A device for inductively confining capacitively coupled RF plasma formed in a plasma processing apparatus. The apparatus includes an upper electrode and a lower electrode that is adapted to support a substrate and to generate the plasma between the substrate and the upper electrode. The device includes a dielectric support... Agent: Buchanan, Ingersoll & Rooney PC

20080020573 - Sacrificial substrate for etching: A method of etching a silicon substrate is described. The method includes bonding a first silicon substrate to a sacrificial silicon substrate. The first silicon substrate is etched. A pressure is applied at an interface of the first silicon substrate and the sacrificial silicon substrate to cause the first silicon... Agent: Fish & Richardson P.C.

20080020575 - Semiconductor wafer surface protecting sheet and semiconductor wafer protecting method using such protecting sheet: A semiconductor wafer surface protection sheet which can prevent breakage of a semiconductor wafer even when a circuit-formed surface of the semiconductor wafer has a significant unevenness, and a method for protecting the semiconductor wafer by using such protection sheet. The semiconductor wafer surface protection sheet includes at least one... Agent: Buchanan, Ingersoll & Rooney PC

20080020576 - Method of forming polysilicon pattern: Embodiments relate to a method of forming a polysilicon pattern, which may be able to form a minute pattern. In embodiments, the method may in clued forming a first polysilicon pattern by selectively etching a polysilicon layer using a photoresist pattern at a fixed interval, forming an oxide layer having... Agent: Sherr & Nourse, PLLC

20080020577 - Gallium and chromium ions for oxide rate enhancement: The invention provides a chemical-mechanical polishing composition comprising silica, a compound in an amount sufficient to provide about 0.2 mM to about 10 mM of a metal cation selected from the group consisting of gallium (III), chromium (II), and chromium (III), and water, wherein the polishing composition has a pH... Agent: Steven Weseman Associate General Counsel, I.p.

20080020578 - Composition for chemical-mechanical polishing (cmp): e

20080020579 - Method for manufacturing a membrane in a (111) surface of a (100) silicon wafer: The invention relates to a method for the fabrication of a membrane oriented in a (111) plane of a (100) silicon wafer. To this end the method comprises the following steps: applying a mask to both sides of the wafer, wherein portions of the sides are covered by the mask;... Agent: Akerman Senterfitt

20080020580 - Minimizing resist poisoning in the manufacture of semiconductor devices: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via... Agent: Texas Instruments Incorporated

20080020581 - Method of fabricating dual damascene structure: A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a trench and expose the conductive layer.... Agent: North America Intellectual Property Corporation

20080020582 - Method of forming an opening in a semiconductor device and method of manufacturing a semiconductor device using the same: In methods of forming an opening in a semiconductor device and methods of manufacturing a semiconductor device, a mask pattern may be formed on a layer to selectively expose the layer through the mask pattern. The layer may be partially etched using the mask pattern as an etching mask and... Agent: Harness, Dickey & Pierce, P.L.C

20080020583 - Plasma etching method and computer-readable storage medium: In a plasma etching method, a substrate, on which an oxide film as a target layer to be etched, a hard mask layer, and a patterned photoresist are sequentially formed, is loaded into the processing chamber and mounted on a lower electrode. A processing gas containing CxFy (x is 3... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080020584 - Method of manufacturing semiconductor device and plasma processing apparatus: The method of manufacturing a semiconductor device according to the present invention includes a step of etching an organic film formed to be embedded in recesses in a low dielectric constant film which is made of a material containing silicon, carbon, oxygen, and hydrogen. The organic film is typically a... Agent: Smith, Gambrell & Russell

20080020586 - Photoresist trimming process: A photoresist trimming gas compound is provided which will selectively remove a resist foot or scum from the lower portions of sidewalls of a photoresist. Additionally, the trimmer compound hardens or toughens an upper surface of the photoresist thereby strengthening the photoresist. The trimmer compound includes O2 and at least... Agent: Greenblum & Bernstein, P.L.C

20080020585 - Semiconductor device fabricating method, plasma processing system and storage medium: In a substrate including a photoresist film, wherein a pattern for forming holes for embedding the wiring material on the upper layer of the above etch target film, a thickness of the above organic layer is greater than a thickness of an etch target layer composed of the above insulating... Agent: Smith, Gambrell & Russell

20080020587 - Method of stripping remnant metal: A method of stripping a remnant metal is disclosed. The remnant metal is formed on a transitional silicide of a silicon substrate. Firstly, a surface oxidation process is performed on the transitional silicide, so as to form a protective layer on the transitional silicide. Then, a HPM stripping process is... Agent: North America Intellectual Property Corporation

20080020589 - Method and system for isolated and discretized process sequence integration: A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch... Agent: Martine Penilla Gencarella, LLP

20080020588 - Method for forming semiconductor device: A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the... Agent: Jianq Chyun Intellectual Property Office

20080020590 - Controlling carbon nanotubes using optical traps: An embodiment of the present invention is a technique to control carbon nanotubes (CNTs). A laser beam is focused to a carbon nanotube (CNT) in a fluid. The CNT is responsive to a trapping frequency. The CNT is manipulated by controlling the focused laser beam.... Agent: Intel/blakely

20080020592 - Method for forming a pattern on a semiconductor device and semiconductor device resulting from the same: Disclosed are a light absorbent agent polymer for organic anti-reflective coating which can prevent diffused light reflection of bottom film layer or substrate and reduce standing waves caused by a variation of thickness of the photoresist itself, thereby, increasing uniformity of the photoresist pattern, in a process for forming ultra-fine... Agent: Marshall, Gerstein & Borun LLP

20080020591 - Method to increase silicon nitride tensile stress using nitrogen plasma in-situ treatment and ex-situ uv cure: Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for... Agent: Townsend And Townsend And Crew LLP / Amat

20080020593 - Ald of metal silicate films: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a metal source chemical, a silicon source chemical and an oxidizing agent. In preferred embodiments, an alkyl amide metal compound and a silicon halide compound are used. Methods... Agent: Knobbe, Martens, Olsen & Bear LLP

20080020594 - Methods of manufacturing a phase-changeable memory device: In a method of manufacturing a phase-changeable memory device, a lower electrode is formed on a substrate. Silicon oxynitride is then deposited on the lower electrode at a temperature of about 450° C. to about 650° C. to form an insulating interlayer that is relatively dense on the lower electrode.... Agent: Myers Bigel Sibley & Sajovec

20080014661 - Method for the manufacture of solar panels and special transport carrier: A method for the manufacture of solar panels from scrapped wafers and/or scrapped dies is provided, including the following steps: identifying scrap wafers and/or scrap dies; cleaning and removing remaining structures from the surface of the wafers/dies; grinding both surfaces of the wafers/dies down to a required thickness; doping the... Agent: Ibm Microelectronics Intellectual Property Law

20080014665 - Method of fabricating liquid crystal display device: A method of fabricating a liquid crystal display device includes the steps of forming a gate electrode and a gate line on a first substrate, forming a gate insulating layer on the gate electrode, forming an active layer on the gate insulating layer and an ohmic contact layer on the... Agent: Morgan Lewis & Bockius LLP

20080014669 - Dual seed semiconductor photodetectors: Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a dual seed semiconductor layer. The dual seed semiconductor layer includes a seed... Agent: Blakely Sokoloff Taylor & Zafman

20080014671 - Semiconductor manufacturing method and semiconductor laser device manufacturing method: There are provided preflow periods t11, t12 in which group III element materials TMG, TMA and TMI are not supplied from a group III element material container to a reaction region (reactor), while a group V element material PH3 and an Mg dopant material are supplied from a group V... Agent: Nixon & Vanderhye, PC

20080014673 - Method of making a deep junction for electrical crosstalk reduction of an image sensor: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of sensor elements configured to receive light directed towards the... Agent: Haynes And Boone, LLP

20080014674 - Method for manufacturing semiconductor device: A method for manufacturing an image sensor is provided. The method includes: forming a plurality of photodiodes on a semiconductor substrate; forming an interlayer dielectric on the semiconductor substrate; forming a color filter layer on the interlayer dielectric; forming a planarization layer on the color filter layer; and forming microlenses... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080014676 - Method for making a pillar-type phase change memory element: A pillar-type phase change memory element comprises first and second electrode elements and a phase change element therebetween. A second electrode material and a chlorine-sensitive phase change material are selected. A first electrode element is formed. The phase change material is deposited on the first electrode element and the second... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080014662 - Semiconductor light emitting apparatus and method of fabricating the same: A semiconductor light emitting apparatus is proposed, which has thyristor without increasing number of constituent semiconductor layers, with large degree of freedom of selection of ON voltage. It comprises first-conductivity-type first cladding layer, active layer, and second-conductivity-type second cladding layer on substrate; pair of opposing first recesses forming stripe-patterned ridge... Agent: Robert J. Depke Lewis T. Steadman

20080014663 - Structure and method of fabricating a hinge type mems switch: A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring... Agent: International Business Machines Corporation Dept. 18g

20080014664 - Manufacturing method of light emitting diode: A method for fabricating a light emitting diode (LED) is provided. A first-type doped semiconductor layer, a light emitting layer and a second-type doped semiconductor layer are formed on an epitaxy substrate sequentially. Then, a gold layer is formed on the second-type doped semiconductor layer. Next, a bonding substrate is... Agent: Jianq Chyun Intellectual Property Office

20080014666 - Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof: A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080014668 - Imprinted waveguide printed circuit board structure: In some embodiments a channel is formed by combining two imprinted subparts each made of printed circuit board material and the imprinted subparts are laminated to form a waveguide. Other embodiments are described and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20080014667 - Modifying the optical properties of a nitride optoelectronic device: A method of modifying the optical properties of a processed nitride semiconductor light-emitting device initially comprises disposing the processed nitride semiconductor light-emitting device in a vacuum chamber. One or more nitride semiconductor layers are then grown by molecular beam epitaxy thereby to modify the optical properties of the processed light-emitting... Agent: Mark D. Saralino ( Sharp ) Renner, Otto, Boisselle & Sklar, LLP

20080014670 - Semiconductor laser element: A method of producing a semiconductor laser element including a step of growing a lower cladding layer, an active layer, a left upper cladding layer, a etching stopper layer having a multiple quantum well structure, an upper cladding layer and a contact layer in the order on a semiconductor substrate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080014672 - Semiconductor laser device, semiconductor laser system, optical pickup module and manufacturing for semiconductor laser system: A semiconductor laser device comprises an n-type cladding layer 103 made of n− type (Al0.3Ga0.7)0.5In0.5P, an undoped active layer 104 and a first p-type cladding layer 105 made of p− type (Al0.3Ga0.7)0.5In0.5P. These layers are successively stacked in bottom-to-top order. The active layer 104 has a multi-quantum well structure composed... Agent: Mcdermott Will & Emery LLP

20080014675 - Method for producing electronic device and electronic device: Upon fixing fine particulate active element members AE1 to AE3, which are carbon nanotube, rod-shaped semiconductor crystal, or the like, in an electronic device at predetermined positions thereof respectively, a method for producing an electronic device includes: dispersing the fine particulate active element members in a dielectric liquid 12 and... Agent: Oliff & Berridge, PLC

20080014677 - Chip scale package (csp) assembly apparatus and method: In one embodiment the present invention includes a method of fabricating a chip scale package (CSP). The method includes forming conductive bumps on a top side of a semiconductor wafer; mounting the top side of the semiconductor wafer on adhesive tape; sawing the semiconductor wafer a first time such that... Agent: Chad R. Walsh Fountainhead Law Group

20080014679 - Packaging structure with protective layers and packaging method thereof: A packaging structure with protective layers and a packaging method thereof are provided. A protective layer is formed on the surface and the pre-dicing line of the wafer to protect the chip and the die during the wafer grinding process, so as to prevent the wafer from being damaged due... Agent: Birch Stewart Kolasch & Birch

20080014678 - System and method of attenuating electromagnetic interference with a grounded top film: A plastic integrated circuit package often includes one or more integrated circuit elements that are sensitive to outside electromagnetic fields and also may generate electromagnetic fields that may interfere with other circuits outside of the package. The package herein has a top metal film to attenuate such electromagnetic fields, using... Agent: Texas Instruments Incorporated

20080014680 - Method of fabrication of a semiconductor chip package: A semiconductor chip package includes a first semiconductor chip, that is an MEMS chip having a movable structure. The movable structure has a movable section. The first semiconductor chip includes a plurality of first electrode pads, and a first sealing section. The first sealing section is a closed loop formed... Agent: Rabin & Berdo, PC

20080014681 - Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same: A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent... Agent: Frishauf, Holtz, Goodman & Chick, PC

20080014682 - Method and system for sealing packages for optics: A system for wafer-level packaging of a plurality of MEMS devices includes a substrate having a plurality of individual chips. Each of the plurality of individual chips includes a plurality of MEMS devices and each of the plurality of individual chips is arranged in a spatial manner as a first... Agent: Townsend And Townsend And Crew, LLP

20080014683 - Wiring base, semiconductor device, manufacturing method thereof and electronic equipment: A method for manufacturing a semiconductor device is provided. A resin paste is applied to a wiring base including a wiring pattern. Then, a semiconductor chip having a plurality of electrodes is mounted to the wiring base. The electrodes and the wiring pattern face one another and are electrically connected.... Agent: Harness, Dickey & Pierce, P.L.C

20080014684 - Two-print-two-etch method for enhancement of cd control using ghost poly: According to various embodiments, two-print two-etch methods and devices are disclosed that can be used to form features, such as ghost features, on a substrate. The disclosed methods can be incorporated into, for example, altPSM, attPSM, and binary lithographic method for making semiconductor devices. a method of forming a semiconductor... Agent: Texas Instruments Incorporated

20080014685 - Amorphous silicon crystallization using combined beams from optically pumped semiconductor lasers: An amorphous silicon layer on a glass substrate is crystallized by concentrating CW radiation from a number of OPS-lasers into a line of light on the layer. The layer is moved with respect to the line of light to control the dwell time of the line on any location on... Agent: Stallman & Pollock LLP

20080014686 - Method of fabricating vertical thin film transistor: A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate... Agent: Jianq Chyun Intellectual Property Office

20080014687 - Oxide isolated metal silicon-gate jfet: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric... Agent: Ronald Craig Fish, A Law Corporation

20080014690 - Ldmos using a combination of enhanced dielectric stress layer and dummy gates: First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming... Agent: HorizonIPPte Ltd

20080014691 - Mask rom cell, nor-type mask rom device, and related methods of fabrication: A mask read-only memory (ROM) cell, a method for fabricating the mask ROM cell, a NOR-type mask ROM device, and a method for fabricating the NOR-type mask ROM device are disclosed. A mask ROM cell includes a substrate including an ON cell region and an OFF cell region, a first... Agent: Volentine & Whitt PLLC

20080014689 - Method for making planar nanowire surround gate mosfet: Embodiments provide a method of fabricating a plurality of planar nanowires surround gate semiconductor device. The planar nanowires can be formed between a source and a drain over an insulating layer of a semiconductor substrate. A gate stack can be grown or deposited all-around the planar nanowires. The gate stack... Agent: Texas Instruments Incorporated

20080014688 - Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit: A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient... Agent: Freescale Semiconductor, Inc.

20080014692 - Method for fabricating a nitrided silicon-oxide gate dielectric: A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed... Agent: Schmeiser, Olsen & Watts

20080014694 - Capacitors and methods of forming capacitors: A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiOxNy having resistivity no greater than 1 ohm·cm over the TiN-comprising material where x is greater than 0 and y... Agent: Wells St. John P.s.

20080014693 - Silicon carbide vertical mosfet design for fast switching applications: A vertical MOSFET device includes a well region of a first conductivity type formed within a surface of a substrate of a second conductivity type opposite the first conductivity type. A doped source region of the second conductivity type is formed within the well region. A plurality of highly doped... Agent: General Electric Company Global Research

20080014695 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and... Agent: F. Chau & Associates, LLC

20080014696 - Trench capacitor and method of manufacturing the same: A trench capacitor and the method of manufacturing the same are provided. A rough polysilicon layer is formed on an inner electrode layer and subsequently mantled by a dielectric layer, and then filled up with an outer electrode layer. The present invention utilizes the characteristic that the rough polysilicon layer... Agent: Rosenberg, Klein & Lee

20080014697 - Semiconductor device with dram cell and method of manufacturing the same: A semiconductor device including a semiconductor substrate a trench forming in the substrate, an insulating film forming on an inner surface of the trench so as to be rendered thicker from a substrate surface side thereof toward a trench deep side thereof, and an electrode layer forming inside the insulating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080014698 - Method of forming memory devices by performing halogen ion implantation and diffusion processes: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process... Agent: Williams, Morgan & Amerson

20080014700 - Methods for fabricating improved gate dielectrics: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance... Agent: Harness, Dickey & Pierce, P.L.C

20080014699 - Subresolution silicon features and methods for forming the same: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent... Agent: Knobbe Martens Olson & Bear LLP

20080014701 - Direct tunneling memory with separated transistor and tunnel areas: A semiconductor device has: an isolation region formed on a semiconductor substrate and defining a continuous active region including a select transistor region and a direct tunnel element region; a gate insulating film formed on a channel region of the select transistor region; a tunnel insulating film formed on a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080014702 - Direct tunneling memory with separated transistor and tunnel areas: A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and... Agent: Posz Law Group, PLC

20080014703 - Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device manufactured using the same: A method of fabricating a semiconductor integrated circuit device may include forming a first gate insulating film and a first gate electrode on a first region of a substrate, and forming a second gate insulating film and a second gate electrode on which a plurality of recesses are formed on... Agent: Lee & Morse, P.C.

20080014704 - Field effect transistors and methods for fabricating the same: Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate.... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20080014705 - Structure and method for performance improvement in vertical bipolar transistors: A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains... Agent: Greenblum & Bernstein, P.L.C

20080014706 - Increasing dielectric constant in local regions for the formation of capacitors: A method for increasing capacitances of capacitors and the resulting integrated structure are provided. The method includes providing a substrate, forming a low-k dielectric layer over the substrate wherein the low-k dielectric layer includes a capacitor region and a non-capacitor region, forming a capacitor in the capacitor region, forming a... Agent: Slater & Matsil, L.L.P.

20080014707 - Process integration scheme of sonos technology: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches... Agent: HorizonIPPte Ltd

20080014708 - Method of fabricating semiconductor device: Disclosed is a method of fabricating a semiconductor device having improved processing stability. A protection layer may be formed on a semiconductor substrate. A sacrificial layer having an etch selectivity with respect to the protection layer may be formed on the protection layer. A part of the sacrificial layer may... Agent: Harness, Dickey & Pierce, P.L.C

20080014710 - Isolation regions: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the... Agent: Leffert Jay & Polglaze, P.A.

20080014709 - Method and apparatus for electroprocessing a substrate with edge profile control: A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a first electroprocessing zone between the electrode and the substrate, and biasing a second electrode disposed radially inward of the first... Agent: Patterson & Sheridan, LLP

20080014711 - Semiconductor device isolation structures and methods of fabricating such structures: Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill... Agent: Harness, Dickey & Pierce, P.L.C

20080014712 - Method for direct bonding two semiconductor substrates: The invention provides methods of direct bonding substrates at least one of which includes a layer of semiconductor material that extends over its front face or in the proximity thereof. The provided methods include, prior to bonding, subjecting the bonding face of at least one substrate comprising a semiconductor material... Agent: Winston & Strawn LLP Patent Department

20080014713 - Treatment for bonding interface stabilization: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the... Agent: Edwards Angell Palmer & Dodge LLP

20080014714 - Method of fabricating a hybrid substrate: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that... Agent: Winston & Strawn LLP Patent Department

20080014715 - Device and method for the processing of wafers: A device and a method for the processing of wafers is disclosed. One embodiment provides a method and a device in which a system wafer is bonded to a carrier work piece by using a bonding substance so as to increase the stability of the system wafer. After processing of... Agent: Dicke, Billig & Czaja

20080014716 - Method for manufacturing soi substrate: The object of the invention is to provide a method for manufacturing an SOI layer which is devoid of damages, has a reduced variation in thickness, and is uniform in thickness. The object is met by providing a method for manufacturing an SOI substrate comprising the steps of forming an... Agent: Jules E. Goldberg, Esq. Reed Smith LLP

20080014717 - Method for manufacturing soi substrate: The object of the invention is to provide a method for manufacturing an SOI layer which is devoid of damages, has a reduced variation in thickness, and is uniform in thickness. The object is met by providing a method for manufacturing an SOI substrate comprising the steps of forming an... Agent: Jules E. Goldberg, Esq. Reed Smith LLP

20080014718 - Treatment for bonding interface stabilization: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the... Agent: Edwards Angell Palmer & Dodge LLP

20080014719 - Semiconductor device and manufacturing method for the same: A semiconductor device has a semiconductor substrate having first and second surface, a first resin film formed on the first surface of the semiconductor substrate and a second resin film formed on the second surface of the semiconductor substrate. A projection electrode or an interconnection is formed on the first... Agent: Hamre, Schumann, Mueller & Larson, P.C.

20080014720 - Street smart wafer breaking mechanism: The present invention discloses a Street Smart breaking technique for breaking a wafer into individual dies with minimal damage to the devices on the wafer surface by applying forces only on the street areas of the wafer. The disclosed wafer breaking mechanism comprises a breaking bar creating a fulcrum against... Agent: Tue Nguyen

20080014721 - Dual channel heterostructure: Dual channel heterostructures comprising strained Si and strained Ge-containing layers are disclosed, along with methods for producing such structures. In preferred embodiments, a strain-relaxed buffer layer is deposited on a carrier substrate, a strained Si layer is deposited over the strain-relaxed buffer layer and a strained Ge-containing layer is deposited... Agent: Knobbe, Martens, Olsen & Bear LLP

20080014722 - Semiconductor device and method for forming the same: Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different... Agent: Marger Johnson & Mccollom, P.C.

20080014723 - Iii-v nitride semiconductor substrate and its production method: A self-supported III-V nitride semiconductor substrate having a substantially uniform carrier concentration distribution in a surface layer existing from a top surface to a depth of at least 10 μm is produced by growing a III-V nitride semiconductor crystal while forming a plurality of projections on a crystal growth interface... Agent: Sughrue Mion, PLLC

20080014724 - Methods for depositing tungsten after surface treatment: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes positioning a substrate containing a metal nitride barrier layer within a process chamber and exposing the substrate to a reagent gas containing diborane to form a reagent layer on the metal nitride barrier... Agent: Patterson & Sheridan, LLP

20080014725 - Deposition over mixed substrates using trisilane: Trisilane is used in chemical vapor deposition methods to deposit silicon-containing films over mixed substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. An example is in forming the base region of... Agent: Knobbe, Martens, Olsen & Bear LLP

20080014726 - Methods of fabricating semiconductor devices having laser-formed single crystalline active structures: Methods of fabricating a semiconductor device are provided. A semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A thin layer is formed on the semiconductor substrate. The thin layer is patterned to form a plurality of spaced apart field structures and... Agent: Myers Bigel Sibley & Sajovec

20080014727 - Method for manufacturing a semiconductor device including a memory cell array area and peripheral circuit area: A method for manufacturing a semiconductor device includes the consecutive steps of selectively implanting first-conductivity-type impurities into a silicon substrate in a memory cell array area to form first source/drain regions, heat treating to diffuse the impurities in the first source/din regions; selectively implanting impurities into the silicon substrate in... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080014728 - Method to improve metal defects in semiconductor device fabrication: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion... Agent: Hitt Gaines, PC Lsi Corporation

20080014729 - Method of manufacturing a memory device: In a method of manufacturing a memory device, a tunnel insulation layer and a floating gate layer are formed on a semiconductor substrate. A top surface of the floating gate layer is converted into a first nitride layer by a first nitridation treatment process. The first nitride layer is converted... Agent: Mills & Onello LLP

20080014730 - Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier: A method and apparatus of preventing lateral oxidation through gate dielectrics that are highly permeable to oxygen diffusion, such as high-k gate dielectrics. According to one embodiment of the invention, a gate structure is formed on a substrate, the gate structure having an oxygen-permeable gate dielectric. An oxygen diffusion barrier... Agent: Michael A. Bernadicou Blakely, Sokoloff, Taylor & Zafman LLP

20080014731 - An interconnect structure with dielectric air gaps: An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a portion of the dielectric layer surrounding the interconnect features. The... Agent: International Business Machines Corporation Dept. 18g

20080014732 - Application of pvd w/wn bilayer barrier to aluminum bondpad in wire bonding: An aluminum bondpad and method for making the aluminum bondpad is disclosed. In forming aluminum bondpads, a barrier layer is necessary between a copper interconnect layer and the aluminum bondpad layer. Additionally, a gold wiring layer is deposited on the aluminum bondpad layer and annealed at a high temperature to... Agent: Patterson & Sheridan, LLP

20080014733 - Bottom electrode contacts for semiconductor devices and methods of forming same: Bottom electrode contact structures for a semiconductor assembly and a method for forming same are described. An exemplary semiconductor device comprises electrode contact structures in a phase change memory device. The phase change memory device comprising a phase change cell is made up of a bottom electrode contact structure comprising... Agent: Micron Technology, Inc.

20080014734 - Metal line of semiconductor device and method of fabricating the same: A metal line of a semiconductor device comprising contact plugs, a plurality of first trenches, first metal lines, a plurality of second trenches, and second metal lines. The contact plugs are formed over a semiconductor substrate and are insulated from each other by a first insulating layer. The plurality of... Agent: Lowe Hauptman Ham & Berner, LLP

20080014735 - Method of forming semiconductor chips, the semiconductor chips so formed and chip-stack package having the same: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of... Agent: Marger Johnson & Mccollom, P.C.

20080014736 - Semiconductor device and manufacturing process therefor: A semiconductor device including a polysilicon plug with a reduced contact resistance and a manufacturing process therefor. The process includes the steps of forming a hole in an insulating layer on a semiconductor substrate; forming polysilicon over the whole surface of the insulating layer such that it fills the hole;... Agent: Young & Thompson

20080014737 - Electrically programmable pi-shaped fuse structures and methods of fabrication thereof: Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and... Agent: Ibm Corporation Department 417

20080014738 - Integrated circuit mount system with solder mask pad: An integrated circuit mount system includes an integrated circuit, a solder mask for the integrated circuit, and a solder mask pad on the substrate with the solder mask.... Agent: Law Offices Of Mikio Ishimaru

20080014740 - Semiconductor-on-insulator (soi) structures including gradient nitrided buried oxide (box): A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor... Agent: Scully Scott Murphy & Presser, PC

20080014739 - Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability: In accordance with the invention, there are semiconductor devices and methods for making semiconductor devices and film stacks in an integrated circuits. The method of making a semiconductor device can comprise forming a semiconductor structure comprising at least one copper interconnect, forming an etch stop bi-layer comprising a first layer... Agent: Texas Instruments Incorporated

20080014741 - Process for improving the reliability of interconnect structures and resulting structure: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a... Agent: Slater & Matsil, L.L.P.

20080014742 - Method of manufacturing a semiconductor device with through-chip vias: An electrode is formed in a hole extending partway into the substrate of a semiconductor device by depositing an insulating film and a barrier metal layer on the substrate surface and the interior of the hole, then filling the hole with a layer of electrode material that also covers the... Agent: Rabin & Berdo, PC

20080014743 - Method of fabricating semiconductor interconnections: A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080014744 - Interconnect structure and method of fabrication of same: A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing... Agent: Schmeiser, Olsen & Watts

20080014745 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, forming the second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080014746 - Reducing corrosion in copper damascene processes: Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through, a copper diffusion barrier layer. The copper diffusion barrier layer may be removed using a different technique. Thereafter, suitable chemicals may... Agent: Trop Pruner & Hu, PC

20080014747 - Process for removing high stressed film using lf or hf bias power and capacitively coupled vhf source power with enhanced residue capture: A method of fabricating multilayer interconnect structures on a semiconductor wafer begins by roughening the interior surface of a metal lid to a surface roughness in excess of SA 2000 with a reentrant surface profile, and installing the metal lid as the ceiling of a plasma clean reactor chamber having... Agent: Law Office Of Robert M. Wallace

20080014748 - Method and system for electronic spatial filtering of spectral reflectometer optical signals: A method for determining endpoint of plasma processing of a semiconductor wafer includes providing a light source, and providing a lens system to collimate and align light from the light source to an active surface of the semiconductor wafer. A plurality of light detector fibers are interleaved among light source... Agent: Martine Penilla & Gencarella, LLP

20080014749 - Method of etching and etching apparatus: Silicon oxide film having, as a sublayer, a silicon nitride film layer serving as a protective film layer for 5 gate formed on silicon substrate is etched by introducing a processing gas including a gaseous mixture containing at least C4F6, Ar, O2 and N2 into an airtight processing chamber and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080014750 - Systems and methods for fabricating self-aligned memory cell: Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr1-XCaXMnO3 (PCMO) layer above the insulator and the metal... Agent: Tran & Associates

20080014751 - Method of manufacturing semiconductor device: A method of manufacturing semiconductor device, providing the CMP method in a stable manner. A SiO2 film 104 is formed on or above a silicon substrate 101, and the SiO2 film 104 is processed by chemical mechanical polishing. The chemical mechanical polishing includes a first polishing process polishing the SiO2... Agent: Young & Thompson

20080014752 - Method of forming fine pitch hardmask patterns and method of forming fine patterns of semiconductor device using the same: A method of forming fine pitch hardmask patterns includes forming a hardmask layer on a substrate and forming a plurality of first mask patterns on the hardmask layer. A buffer layer is formed on the plurality of first mask patterns, and has an upper surface defining recesses between adjacent first... Agent: F. Chau & Associates, LLC

20080014753 - Method of manufacturing a semiconductor device using a radical oxidation process: In a method of manufacturing a semiconductor device, a polysilicon layer doped with impurities is formed on a front side and a backside of a substrate. An insulation layer is formed on the substrate having the polysilicon layer to cover the polysilicon layer on the backside of the substrate. The... Agent: F. Chau & Associates, LLC

20080014754 - Methods of finishing quartz glass surfaces and components made by the methods: Methods of surface finishing a component useful for a plasma processing apparatus are provided. The component includes at least one plasma-exposed quartz glass surface. The method includes mechanically polishing, chemically etching and cleaning the plasma-exposed surface to achieve a desired surface morphology. Quartz glass sealing surfaces of the component also... Agent: Buchanan, Ingersoll & Rooney PC

20080014755 - Plasma etching method and computer-readable storage medium: In a plasma etching method, a plasma of a processing gas containing CxFy (x, y are integers equal to or greater than 1), a rare gas and O2 by applying a high frequency power to the upper or the lower electrode while the processing gas is being supplied into the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080014756 - Method of producing group 3 nitride substrate wafers and group 3 nitride substrate wafers: Quality of one-surface planar processed group 3 nitride wafers depends upon a direction of pasting of wafers on a polishing plate. Low surface roughness and high yield are obtained by pasting a plurality of group 3 nitride as-grown wafers on a polishing plate with OFs or notches facing forward (f),... Agent: Mcdermott Will & Emery LLP

20080014758 - Film formation apparatus for semiconductor process and method for using the same: A method for using a film formation apparatus performs a first film formation process, while supplying a first film formation gas into a process field inside a process container, thereby forming a first thin film on a first target substrate inside the process field. After unloading the first target substrate... Agent: Smith, Gambrell & Russell

20080014757 - Leadframes for improved moisture reliability and enhanced solderability of semiconductor devices: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of... Agent: Texas Instruments Incorporated

20080014759 - Method for fabricating a gate dielectric layer utilized in a gate structure: Methods for forming a gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a silicon substrate, depositing a silicon nitride layer on the silicon oxide layer by a thermal process, wherein the silicon oxide layer and the silicon nitride... Agent: Patterson & Sheridan, LLP

20080014760 - Semiconductor device and method of manufacturing the same: A semiconductor device has a semiconductor substrate which has a main front surface, a plurality of convex patterns formed on the main front surface of a semiconductor substrate so that each might have a floating gate and a control gate, a first insulating film formed so that the upper surface... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080014761 - Decreasing the etch rate of silicon nitride by carbon addition: Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence... Agent: Patterson & Sheridan, LLP

20080014762 - Process for producing zirconium oxide thin films: This invention concerns a process for producing oxide thin film on a substrate by an ALD type process. According to the process, alternating vapour-phase pulses of at least one metal source material, and at least one oxygen source material are fed into a reaction space and contacted with the substrate.... Agent: Knobbe Martens Olson & Bear LLP

20080014763 - Method of heating semiconductor wafer to improve wafer flatness: A method of heating-treating a semiconductor wafer is provided. In one embodiment, a first layer is formed over a first side of a substrate. A second layer is formed over the first layer and over a second side of the substrate and the wafer is then flash annealed. In another... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080014764 - Low temperature, long term annealing of nickel contacts to lower interfacial resistance: A method of annealing semiconductor devices to form substantially ohmic contact regions between a layer of wide band-gap semiconductor material and contact areas disposed thereon includes exposing the semiconductor devices to an annealing temperature less than approximately 900 degrees Celsius for an annealing duration of greater than approximately two hours.... Agent: Hiscock & Barclay, LLP

20080009081 - Managing and using metrology data for process and equipment control: An apparatus to examine a patterned structure formed on a semiconductor wafer using an optical metrology model includes a fabrication system and a metrology processor. The fabrication system includes a fabrication cluster, metrology cluster, metrology model optimizer, and real time profile estimator. The fabrication cluster is configured to process wafers,... Agent: Morrison & Foerster LLP

20080009085 - Method for manufacturing probe card: A method for manufacturing a probe card is provided. A first inactive layer, a first patterned photoresist layer and a first metal layer are sequentially formed on a substrate. The first metal layer has first through holes exposing a portion of the first patterned photoresist layer. A second inactive layer... Agent: J C Patents, Inc.

20080009084 - System and method for digital light valve processing: A system and method are provided for processing a semiconductor film using a digital light valve. The method enables pixel elements from an array of selectable pixel elements; gates a light in response to enabling the pixel elements; exposes selected areas of a semiconductor film, such as Si, to the... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20080009086 - Method of packaging light emitting diodes: A method of packaging light emitting diodes includes providing a wafer having a plurality of LEDs thereon, forming at least a sealant surrounding the LEDs, providing a glass substrate to cover the LEDs, the sealant, and the wafer, providing a UV hardening process to harden the sealant, forming a polarization... Agent: North America Intellectual Property Corporation

20080009089 - Method of manufacturing semiconductor device: A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap... Agent: Foley And Lardner LLP Suite 500

20080009092 - Use of chlorinated copper phthalocyanines as air-stable n-channel organic semiconductors: The present invention relates to the use of chlorinated copper phthalocyanines as air-stable n-type organic semiconductors.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080009080 - Method of manufacturing a multi-purpose magnetic film structure: Provided are a multi-purpose magnetic film structure using a spin charge, a method of manufacturing the same, a semiconductor device having the same, and a method of operating the semiconductor memory device. The multi-purpose magnetic film structure includes a lower magnetic film, a tunneling film formed on the lower magnetic... Agent: Lee & Morse, P.C.

20080009082 - Connection device and test system: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080009083 - Semiconductor device with electrode pad having probe mark: A semiconductor device is formed by bonding bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark... Agent: Mcdermott Will & Emery LLP

20080009087 - Miniature optical element for wireless bonding in an electronic instrument: A method of manufacturing an optical element including the steps of: forming a through hole in a semiconductor element which has an optical section and an electrode electrically connected to the optical section; and forming a conductive layer extending from a first surface of the semiconductor element on which the... Agent: Oliff & Berridge, PLC

20080009088 - Method of producing multi-wavelength semiconductor laser device: A method for producing a multi-wavelength semiconductor laser device includes steps of: forming first and second nitride epitaxial layers in parallel on a substrate for growth of a nitride single crystal; separating the first and second nitride epitaxial layers from the substrate; attaching the separated first and second nitride epitaxial... Agent: Lowe Hauptman Ham & Berner, LLP

20080009090 - Method for manufacturing physical quantity sensor: A physical quantity sensor includes: a semiconductor substrate; a cavity disposed in the substrate and extending in a horizontal direction of the substrate; a groove disposed on the substrate and reaching the cavity; a movable portion separated by the cavity and the groove so that the movable portion is movably... Agent: Posz Law Group, PLC

20080009091 - Wafer level capped sensor: A sensor has a die (with a working portion), a cap coupled with the die to at least partially cover the working portion, and a conductive pathway extending through the cap to the working portion. The pathway provides an electrical interface to the working portion.... Agent: Bromberg & Sunstein LLP

20080009093 - Silicon material having a mark on the surface thereof and the method of making the same: The present invention relates to a silicon material having a mark on the surface thereof and the method for making the same. The method comprises the following steps: (a) providing a silicon material; (b) providing a glass substrate; (c) putting the silicon material on the glass substrate; and (d) focusing... Agent: Volentine & Whitt PLLC

20080009094 - Print stripper for esd control: A system may include a static dissipative device to secure a semiconductor component, and a printer to print indicia on the semiconductor component while the semiconductor component is secured with the static dissipative device.... Agent: Buckley, Maschoff & Talwalkar LLC

20080009095 - Advanced thin flexible microelectronic assemblies and methods for making same: A thin, flexible microelectronic assembly using thinned die (5-10 microns and lower) produced by growing a 1 μm-10 μm silicon epitaxial (Epi) layer on an oxidized silicon carrier. The integrated circuit process takes place in the standard manner in the Epi layer. The oxide layer and the silicon carrier serve... Agent: The Johns Hopkins Universityapplied Physics Labora Office Of Patent Counsel

20080009096 - Package-on-package and method of fabricating the same: A package-on-package and a method of fabricating the same capable of increasing mounting density of a semiconductor package are provided. The method includes providing a flexible substrate first, second, and third printed circuit patterns formed on the upper and lower surfaces of the flexible substrate. First and second semiconductor chips... Agent: Marger Johnson & Mccollom, P.C.

20080009097 - Integrated circuit package, panel and methods of manufacturing the same: A method of manufacturing an integrated circuit package includes: assembling a composite wafer including alternating rows or columns of first and second strips on an adhesive tape, the first strips including a plurality of first dies and the second strips including a plurality of second dies, singulating the first dies... Agent: Edell , Shapiro & Finnan , LLC

20080009098 - Structure of high performance combo chip and processing method: A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the... Agent: Saile Ackerman LLC

20080009099 - System and method of monitoring contamination: The present invention provides passive sampling systems and methods for monitoring contaminants in a semiconductor processing system. In one embodiment, that passive sampling system comprises a collection device in fluid communication with a sample line that provides a flow of gas from a semiconductor processing system. The collection device is... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20080009100 - Method and apparatus for imprinting a circuit pattern using ultrasonic vibrations: Embodiments of a method and apparatus for imprinting a trench pattern on a substrate using ultrasonic vibrations. The trench pattern corresponds to a circuit pattern that is to be formed on the substrate, the circuit pattern including a number of conductive traces and other conductive elements. In one embodiment, the... Agent: Intel Corporation C/o Intellevate, LLC

20080009101 - Compressible films surrounding solder connectors: Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the... Agent: Frederick W. Gibb, Iii Mcginn & Gibb, PLLC

20080009102 - Method for encasulating sensor chips: A method for encapsulating sensor chips is disclosed. A protective layer is formed on an active surface of a sensor chip, and at least covers a sensor region in the active surface. The active surface of the sensor chip faces to a temporary carrier, so that the protective layer is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080009103 - Quad flat no-lead (qfn) chip package assembly apparatus and method: In one embodiment the present invention includes a method of fabricating a quad flat no-lead (QFN) chip package. The method includes forming a stamped lead frame; forming a die pad and a lead shrink on one side of the stamped lead frame; mounting a die on the die pad; performing... Agent: Chad R. Walsh Fountainhead Law Group

20080009104 - Semiconductor package having electromagnetic interference shielding and fabricating method thereof: A method of fabricating a semiconductor package having electromagnetic interference shielding starts with providing a substrate and a semiconductor device. Subsequently, a molding compound is provided. The molding compound covers the semiconductor device, and contacts with parts of the substrate. Next, a conductive adhesive layer is formed on the surface... Agent: North America Intellectual Property Corporation

20080009105 - Silicide-silicon oxide-semiconductor antifuse device and method of making: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.... Agent: Foley And Lardner LLP Suite 500

20080009106 - Method for manufacturing semiconductor device: It is an object of the invention to provide a peeling method which does not damage a peeling layer, and to perform peeling not only a peeling layer having a small-size area but also an entire peeling layer having a large-size area with a preferable yield. In the invention, after... Agent: Eric Robinson

20080009107 - Thin film transistor and manufacturing method thereof: A thin film transistor (TFT) and the manufacturing method thereof are disclosed, and the thin film transistor comprises: a substrate, a gate electrode, a first CuSix layer, a gate-insulting layer, a semiconductor layer, a second CuSix layer, and a source electrode and a drain electrode. The gate electrode is disposed... Agent: Rosenberg, Klein & Lee

20080009108 - Display panel structure and manufacture method thereof: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080009109 - Epitaxial filled deep trench structures: A method of forming and a structure of an electronic device. The method including: forming a trench in a single-crystal semiconductor substrate; forming a dopant diffusion barrier layer on sidewalls and a bottom of the trench; and epitaxially growing a single-crystal semiconductor layer in the trench, the single-crystal semiconductor layer... Agent: Schmeiser, Olsen & Watts

20080009111 - Manufacturing method of semiconductor device: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080009110 - Metal-oxide semiconductor field effect transistor and method for manufacturing the same: The invention is directed to a method for forming a metal-oxide semiconductor field effect transistor. The method comprises steps of providing a substrate having a gate structure formed thereon, wherein a plurality of isolation structures are located in the substrate adjacent to both sides of the gate structure and then... Agent: Jianq Chyun Intellectual Property Office

20080009112 - Method for forming a memory device with a recessed gate: A method for forming a semiconductor memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed... Agent: Quintero Law Office, PC

20080009113 - Semiconductor device, method of manufacturing semiconductor device, and method of evaluating manufacturing process of semiconductor device: A p impurity region (3) defines a RESURF isolation region in an n− semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n− semiconductor layer (2) in the RESURF isolation region. An nMOS transistor (103) is provided... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080009114 - Hybrid crystal orientation cmos structure for adaptive well biasing and for power and performance enhancement: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device... Agent: Scully, Scott, Murphy & Presser, P.C.

20080009115 - Method of manufacturing at least one semiconductor component and memory cells: A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at... Agent: Slater & Matsil LLP

20080009116 - Method for fabricating semiconductor device: Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080009117 - Band-engineered multi-gated non-volatile memory device with enhanced attributes: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and... Agent: Leffert Jay & Polglaze, P.A.

20080009118 - Metal oxide semiconductor device and fabricating method thereof: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the... Agent: J.c. Patents

20080009119 - Method for manufacturing a semiconductor device including a crown-type capacitor: A method for forming a semiconductor device includes a plurality of crown-type capacitors in a capacitor-receiving insulating film, wherein bottom electrodes of the capacitors have an insulating spacer between each two of the bottom electrodes. The insulating spacer is formed by removing a hard mask used as an etching mask... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20080009120 - Program for controlling laser apparatus and recording medium for recording program for controlling laser apparatus and capable of being read out by computer: The object of the present invention is to solve problems of treatment time when using an SLS method or continuous-oscillation laser. An indispensable portion is scanned with a laser beam in order to crystallize a semiconductor film by driving a laser and so on in accordance with the positions of... Agent: Nixon Peabody, LLP

20080009121 - Fabrication of aligned nanowire lattices: Methodologies associated with fabricating aligned nanowire lattices are described. One exemplary method embodiment includes providing a twist wafer bonded thin single crystal semiconductor film and a bulk single crystal substrate of the same material. Periodic non-uniform elastic strains present on the surface of the film control the positions where nanocrystals... Agent: Hewlett Packard Company

20080009122 - Arrangement for solder bump formation on wafers: An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate... Agent: Donald N. Halgren

20080009123 - Method for bonding two free surfaces, respectively of first and second different substrates: A method for bonding two free surfaces, respectively of first and second different substrates, includes a formation step, on the free surface of the first substrate, of a self-assembled mono-molecular layer consisting of a thiol compound of the SH—R—X type, where —R is a carbonaceous chain and —X is a... Agent: Oliff & Berridge, PLC

20080009124 - Method of forming a semiconductor device: A method of forming a semiconductor device includes the following processes. A semiconductor wafer including chips and through electrodes is diced into chip groups. The chip groups are stacked to form a module group.... Agent: Scully Scott Murphy & Presser, PC

20080009125 - Manufacturing method of thin film integrated circuit device and manufacturing method of non-contact type thin film integrated circuit device: With non-contact and contact IC chips becoming common, it is necessary to mass-produce enormous amount of IC chips, which are utilizable for human beings, animals and plants, commercial products, banknotes, and the like, at low cost. For example, it is necessary to manufacture IC chips to be applied to commercial... Agent: Eric Robinson

20080009126 - Plasma deposition apparatus and method for making polycrystalline silicon: A plasma deposition apparatus for making polycrystalline silicon including a chamber for depositing said polycrystalline silicon, the chamber having an exhaust system for recovering un-deposited gases; a support located within the deposition chamber for holding a target substrate having a deposition surface, the deposition surface defining a deposition zone; at... Agent: Patton Boggs LLP

20080009127 - Method of removing photoresist: A method includes forming a photoresist pattern over a certain portion of a material layer to expose an ion implantation region, implanting impurities in the ion implantation region of the material layer using the photoresist pattern as an ion implantation barrier, and removing the photoresist pattern using plasma of a... Agent: Lowe Hauptman Ham & Berner, LLP

20080009128 - Buried pattern substrate and manufacturing method thereof: A buried pattern substrate and a manufacturing method thereof are disclosed. A method of manufacturing a buried pattern substrate having a circuit pattern formed on a surface, in which the circuit pattern is connected electrically by a stud bump, includes (a) forming the circuit pattern and the stud bump by... Agent: Staas & Halsey LLP

20080009129 - Methods and systems for laser assisted wirebonding: The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for wirebonding by removing impurities such as residues from manufacturing processes, oxides, or irregularities on the bonding surface. Subsequently, a free air ball is brought into contact... Agent: Texas Instruments Incorporated

20080009130 - Underfill and mold compounds including siloxane-based aromatic diamines: A method including introducing a composition including a siloxane-based aromatic diamine in a flowable state between a first substrate including a first set of contact points and a second substrate including a second set of contact points coupled to the first substrate through interconnections between a portion of the first... Agent: Intel/blakely

20080009131 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick... Agent: John Chen

20080009132 - Via hole forming method: n

20080009133 - Sidewall coverage for copper damascene filling: A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the... Agent: Haynes And Boone, LLP

20080009134 - Method for fabricating metal silicide: A method for fabricating a metal silicide is described. First, a silicon material layer is provided. An alloy layer is formed on the silicon material layer, and the alloy layer is made from a first metal and a second metal, wherein, the first metal is a refractory metal, and the... Agent: J.c. Patents, Inc.

20080009135 - Method for fabricating semiconductor storage device: The semiconductor storage device comprises memory cell transistors formed on a semiconductor substrate 10; first insulation films 42 covering the top surfaces and the side surfaces of gate electrodes 20 of the memory cell transistors; through-holes 40 opened on first diffused layers 24; a second insulation film 36 with through-holes... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080009136 - Polishing method: A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry... Agent: Lee & Morse, P.C.

20080009137 - Method for forming fine patterns of a semiconductor device: A method for forming a fine pattern of a semiconductor device overcomes resolution limits of exposure equipment. The method includes forming a first photoresist pattern over an underlying layer formed over a semiconductor substrate. An amorphous carbon film and a second photoresist film are sequentially deposited over the first photoresist... Agent: Townsend And Townsend And Crew, LLP

20080009138 - Method for forming pattern of a semiconductor device: A method for forming a pattern of a semiconductor device comprises sequentially forming a carbon-rich polymer, an antireflection film containing silicon, and a photoresist film over a semiconductor substrate. A double patterning process is then performed. The double patterning process may be a negative tone double patterning process or a... Agent: Townsend And Townsend And Crew, LLP

20080009139 - Structure in a substrate for the manufacturing of a semiconductor device and process for manufacturing of a semiconductor device: A structure in a substrate for the manufacturing of a semiconductor device, wherein a first material and at least one second material are to be etched by at least one etching medium, wherein the at least one second material has a higher etch rate for the at least one etching... Agent: Slater & Matsil LLP

20080009140 - Electron induced chemical etching for device level diagnosis: A method of imaging and identifying materials, contamination, fabrication errors, and defects on and below the surface of an integrated circuit (IC) is described. The method may be used in areas smaller than one micron in diameter, and may remove IC layers, either selectively or non-selectively, until a desired depth... Agent: Schwegman, Lundberg & Woessner, P.A.

20080009141 - Methods to form sicoh or sicnh dielectrics and structures including the same: Methods of forming dielectric films comprising Si, C, O and H atoms (SiCOH) or Si, C, N and H atoms (SiCHN) that have improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking, Cu ingress, and other... Agent: Scully Scott Murphy & Presser, PC

20080009142 - Evaporation control using coating: A novel arrangement and method for depositing evaporation control agents so as to coat immersion lithographic solutions which are employed on the surface of semiconductor wafers in connection with the etching of the surfaces of the wafer through the intermediary of an immersion lithographic process.... Agent: Scully, Scott, Murphy & Presser, P.C.

20080009143 - Method of forming silicon oxide layer: Disclosed is a method of forming a silicon oxide layer comprising: supplying at least a gas containing Si as a raw gas to a semiconductor substrate having a recess formed on its surface to form a primary reactant on the surface, then performing dehydration condensation to form a silicon oxide... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP