Semiconductor device manufacturing: process inventions 12/07

20070298521 - Method for cleaning post-etch noble metal residues: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on... Agent: Texas Instruments Incorporated

20070298522 - Method and apparatus for process control with in-die metrology: Various embodiments include a method for providing instructions to a process tool. The method includes emitting an incident light beam at a substrate, receiving a reflected light beam from the substrate and determining a spectrum of the reflected light beam. The method further includes determining a first property of a... Agent: Carr & Ferrell LLP

20070298525 - Integrated microelectronic package stress sensor: Stress in microelectronic integrated circuit packages may be measured in situ using carbon nanotube networks. An array of carbon nanotubes strung between upstanding structures may be used to measure the local stress in two dimensions. Because of the characteristics of the carbon nanotubes, a highly accurate stress measurement may be... Agent: Trop Pruner & Hu, PC

20070298524 - Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same: The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical... Agent: Williams, Morgan & Amerson

20070298527 - Determining geometrical configuration of interconnect structure: Methods are disclosed for determining a geometrical configuration of an interconnect structure of a test structure without cross-sectioning or optical measurements. In one embodiment, the method includes obtaining simulation data correlating capacitance data, resistance data and geometrical configuration data for a plurality of interconnect structures having different geometrical configurations; measuring... Agent: Hoffman, Warnick & D'alessandro LLC

20070298532 - Micro-electro-mechanical (mems) encapsulation using buried porous silicon: An apparatus comprising a substrate having therein one or more porous regions, a micro-electro-mechanical (MEMS) device formed on the substrate, a cap formed on the substrate, wherein the cap encapsulates the MEMS device and is formed over at least one of the one or more porous regions, and a sealing... Agent: Blakely Sokoloff Taylor & Zafman

20070298533 - Method and apparatus providing imager pixel array with grating structure and imager device containing the same: An imager pixel array capable of separating and detecting the spectral components of an incident light without the use of a color filter array. The imager pixel array employs a grating layer which allows one or more spectral components of incident light to be transmitted therethrough, but diffracts other spectral... Agent: Dickstein Shapiro LLP

20070298520 - Method of producing an element comprising an electrical conductor encircled by magnetic material: A method of producing an electrical inductor circuit element comprising an elongate electrical conductor encircled by magnetic material extending along at least a part of the conductor. First and second sacrificial layers are formed across the conductor respectively above and below the conductor, at least parts of the sacrificial layers... Agent: Freescale Semiconductor, Inc. Law Department

20070298523 - Silicon wafers and method of fabricating the same: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution... Agent: Marshall, Gerstein & Borun LLP

20070298526 - Programmable semiconductor device: A design structure for designing and manufacturing a programmable device. The design structure includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is... Agent: Ibm Microelectronics Intellectual Property Law

20070298528 - Semiconductor laser manufacturing method: A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a conductive film, which... Agent: Mcdermott Will & Emery LLP

20070298529 - Semiconductor light-emitting device and method for separating semiconductor light-emitting devices: The invention provides a method for separating semiconductor light-emitting devices formed on a substrate. In the method, a pulse laser beam having a pulse width less than 10 ps in a substrate is focused on the substrate, to thereby cause multi-photon absorption in the substrate. Through multi-photon absorption, a groove... Agent: Mcginn Intellectual Property Law Group, PLLC

20070298530 - Process for making an organic electronic device: There is provided a process for forming an organic electronic device. The process includes the steps: forming a first layer, which includes an electrically conductive material and a fluorinated acid polymer, the first layer having a first surface energy; forming a second layer over the first layer, the second layer... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070298531 - Quantum well intermixing in semiconductor photonic devices: A method for fabricating a semiconductor device in a semiconductor structure, provides enhanced quantum well intermixing in desired regions of the device by forming a first, relatively high quality, epitaxial layer on a substrate, the high quality layer including a quantum well; forming a second, relatively lower quality, epitaxial defect... Agent: Momkus Mccluskey Monroe Marsh & Spyratos, LLC

20070298534 - Electronic device and method of manufacturing the same: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070298535 - Memory cell with memory material insulation and manufacturing method: A memory cell, the memory cell includes first and second electrodes and a memory material element electrically coupling the first and second electrodes. The memory material element comprises a first memory material, such as GST, the first memory material having an electrical property that can be changed by the application... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070298536 - Single-crystal metal nanocrystals: Methods for producing nanocrystals comprising metallic materials utilizing an inverse micelle solvothermal process are disclosed. Nanocrystals comprising well-ordered, single-crystalline germanium (Ge) materials with predeterminable morphologies in relatively high purity are produced by suspending a Ge salt material comprising a metal ion in a non-aqueous inverse micelle solvent comprising at least... Agent: Greenberg Traurig, LLP

20070298537 - Diamond composite heat spreader and associated methods: Diamond heat spreaders are produced having thermal properties approaching that of pure diamond. Diamond particles of relatively large grain size are tightly packed to maximize diamond-to-diamond contact. Subsequently, smaller diamond particles may be introduced into the interstitial voids to further increase the diamond content per volume. An interstitial material is... Agent: Thorpe North & Western, LLP.

20070298538 - Liquid crystal display device: The present invention provides a liquid crystal display device having a large holding capacitance in the inside of a pixel. A liquid crystal display device includes a first substrate, a second substrate arranged to face the first substrate in an opposed manner, and liquid crystal sandwiched between the first substrate... Agent: Stanley P. Fisher Reed Smith LLP

20070298539 - Method for bonding semiconductor chip: A method for bonding a semiconductor chip is disclosed. In accordance with the method of the present invention, a front surface of a wafer is mounted in a wafer holder to face downward. Each of dies of the wafer is then pushed downward to a tray disposed therebelow, thereby eliminating... Agent: Sughrue Mion, PLLC

20070298540 - Dicing and packing metod of sheet-like wafer, packed product of water, and separation jig: To provide a dicing and packing method of a sheet-like wafer that can collectively solve conventional problems such as damage of an individual piece, generation of dusts, and increase of troublesome work at a time of packing, caused in a process of packing the individual pieces obtained by dicing a... Agent: Quinn Emanuel Koda & Androlia

20070298541 - Method and system for sealing a substrate: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate a... Agent: Knobbe Martens Olson & Bear LLP

20070298542 - Multiple internal seal ring micro-electro-mechanical system vacuum packaging method: A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum packaging method that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk... Agent: Canady & Lortz LLP

20070298543 - Method for manufacturing heat sink of semiconductor device: A method for manufacturing a heat sink of a semiconductor device is described. In the method, an adhesive tape is provided, wherein the adhesive tape includes a first surface and a second surface on opposite sides, and the first surface of the adhesive tape adheres to a surface of a... Agent: Lowe Hauptman Ham & Berner, LLP

20070298544 - Manufacturing method for a leadless multi-chip electronic module: A leadless multi-chip electronic module with leadframe bond pads is manufactured in a manner to place small signal bond pads in a central region of the module for significantly increased reliability of solder joints between such bond pads and a substrate of the module. A linear array of parallel leadframe... Agent: Delphi Technologies, Inc.

20070298545 - Method of manufacturing a semiconductor device: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070298546 - Manufacturing method package substrate: A manufacturing method of a package substrate is disclosed. The method for manufacturing a package substrate is by forming a bump on a bump pad in a core board, where a first circuit pattern including the bump pad is formed on one surface, a second circuit pattern electrically connected with... Agent: Staas & Halsey LLP

20070298547 - Semiconductor device having a composite passivation layer and method of manufacturing the same: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device comprises a fuse bank with a fuse window, a pad area with a pad window, and a composite passivation layer comprising a sacrificial dielectric layer and a final passivation layer. Both the fuse window and... Agent: Nixon Peabody LLP - Patent Group

20070298548 - Active matrix display: The active matrix display includes a polysilicon layer including a source region, a drain region and a channel region and placed on an insulating substrate, a gate insulating layer placed on the polysilicon layer, a gate electrode placed on the gate insulating layer, an interlayer insulating layer placed on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070298550 - Method for making thin-film semiconductor device: A method for making a thin-film semiconductor device includes an annealing step of irradiating an amorphous semiconductor thin film with a laser beam so as to crystallize the amorphous semiconductor thin film. In the annealing step, the semiconductor thin film is continuously irradiated with the laser beam while shifting the... Agent: Wolf Greenfield & Sacks, P.C.

20070298549 - Method of fabricating a strained multi-gate transistor and devices obtained thereof: A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a... Agent: Knobbe Martens Olson & Bear LLP

20070298551 - Fabrication of silicon nano wires and gate-all-around mos devices: The invention relates to methods for manufacturing semiconductor devices. Processes are disclosed for implementing suspended single crystal silicon nano wires (NWs) using a combination of anisotropic and isotropic etches and spacer creation for sidewall protection. The core dimensions of the NWs are adjustable with the integration sequences: they can be... Agent: Nixon & Vanderhye, PC

20070298552 - High performance 3d fet structures, and methods for forming the same using preferential crystallographic etching: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used... Agent: Scully, Scott, Murphy & Presser, P.C.

20070298553 - Thin film transistor and method for production thereof: The production method of the thin film transistor according to the present invention involves the reactive heat CVD process to form the active layer and the source-drain layer. This offers the advantage of eliminating additional steps to crystallize the semiconductor thin film. The resulting stacked thin film transistor is composed... Agent: Sonnenschein Nath & Rosenthal LLP

20070298554 - Tft lcd array substrate and manufacturing method thereof: The present invention discloses a method for manufacturing a TFT LCD array substrate by utilizing the gray tone mask technology and the photoresist lifting-off technology with only two masks in two photolithography processes, and to a TFT LCD array substrate manufactured by the same. In the resultant array substrate, the... Agent: Hasse & Nesbitt LLC

20070298555 - Method of manufacturing a semiconductor device: An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device.... Agent: Eric Robinson

20070298556 - Field effect transistor with enhanced insulator structure: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and... Agent: Ostrolenk Faber Gerb & Soffen

20070298557 - Junction leakage reduction in sige process by tilt implantation: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a stressor in the semiconductor substrate adjacent to an edge of the gate electrode; and tilt implanting... Agent: Slater & Matsil, L.L.P.

20070298558 - Method of fabricating semiconductor device and semiconductor device: A semiconductor device includes a first semiconductor region of first type conductivity with a channel region being formed therein, a gate electrode insulatively formed above the channel region, a layer of SixGe1-x (0<x<1) on both sides of the channel region, a pair of second semiconductor regions of second type conductivity... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070298559 - Vertical field-effect transistor and method of forming the same: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes... Agent: Slater & Matsil, L.L.P.

20070298560 - Semiconductor device: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070298561 - Integrated sige nmos and pmos transistors: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar... Agent: Texas Instruments Incorporated

20070298562 - Method of manufacturing a semiconductor integrated circuit device: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an... Agent: Staas & Halsey LLP

20070298563 - Method of manufacturing a semiconductor integrated circuit device: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an... Agent: Staas & Halsey LLP

20070298564 - Vertical field-effect transistor and method of forming the same: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes... Agent: Slater & Matsil, L.L.P.

20070298565 - Junction leakage reduction in sige process by implantation: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity... Agent: Slater & Matsil, L.L.P.

20070298566 - Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance: Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20070298567 - Sram cell structure and manufacturing method thereof: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over... Agent: J.c. Patents

20070298568 - Scaled dielectric enabled by stack sidewall process: Non-volatile storage elements (or other device) are created. One embodiment includes creating floating gate stacks comprising a floating gate, a control gate and a dielectric between the floating gate and the control gate. One example of a suitable dielectric includes a first layer of oxide, a layer of nitride and... Agent: Vierra Magen/sandisk Corporation

20070298569 - Non-volatile memory having three states and method for manufacturing the same: Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon substrate and the floating gate below... Agent: Ladas & Parry LLP

20070298570 - Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors: The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain... Agent: Wells St. John P.s.

20070298571 - Single chip data processing device with embedded nonvolatile memory and method thereof: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant... Agent: Harness, Dickey & Pierce, P.L.C

20070298572 - Field effect transistors (fets) with multiple and/or staircase silicide: A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact... Agent: Schmeiser, Olsen & Watts

20070298573 - Semiconductor device and method for manufacturing the same: The invention is directed to a method for manufacturing a semiconductor device. The method comprises steps of forming a gate dielectric layer, a polysilicon layer and a patterned cap layer over a substrate sequentially and patterning the polysilicon layer to be a polysilicon gate by using the patterned cap layer... Agent: Jianq Chyun Intellectual Property Office

20070298574 - Method of fabricating different semiconductor device types with reduced sets of pattern levels: A method of manufacturing an integrated circuit comprising forming gate structures for first, second and third semiconductor device types located on a semiconductor substrate. A dopant block is formed over the second semiconductor device type and first dopants are implanted into unblocked regions of the semiconductor substrate corresponding to the... Agent: Texas Instruments Incorporated

20070298575 - Methods for contact resistance reduction of advanced cmos devices: Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by... Agent: Patterson & Sheridan, LLP

20070298577 - Method for manufacturing semiconductor device: An excessive etch in the conventional manufacturing process causes a roughened surface of a contact bottom, resulting in an increased variation in characteristics of semiconductor devices. A bipolar transistor having a collector region 4 provided in a bottom of a trench formed in a P-type silicon substrate 1 is formed.... Agent: Young & Thompson

20070298576 - Methods of forming bipolar transistors by silicide through contact and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming an opening in a masking layer, implanting an amorphizing species into a silicon region disposed within the opening, wherein the silicon region comprises a portion of an emitter of a bipolar transistor; and forming... Agent: Intel Corporation C/o Intellevate, LLC

20070298578 - Bipolar transistor with dual shallow trench isolation and low base resistance: An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair... Agent: Scully Scott Murphy & Presser, PC

20070298579 - Methods of employing a thin oxide mask for high dose implants: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate... Agent: Texas Instruments Incorporated

20070298580 - Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating: Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a... Agent: Mills & Onello LLP

20070298581 - Method of manufacturing suspension structure and chamber: A method of manufacturing a suspension structure including providing a substrate, forming a hole and a sacrificial layer filling the hole on the substrate, forming a patterned photoresist layer on the substrate and the sacrificial layer, the patterned photoresist layer exposing a part of the substrate and the sacrificial layer,... Agent: North America Intellectual Property Corporation

20070298582 - Method of performing a double-sided process: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the... Agent: North America Intellectual Property Corporation

20070298583 - Method for forming a shallow trench isolation region: A method for forming a shallow trench isolation region (STI) is disclosed. The method comprises the steps of sequentially forming a pad oxide layer and a nitride silicon layer over a provided substrate. Next, the pad oxide layer, the nitride silicon layer, and the substrate are partially etched to form... Agent: Baker & Mckenzie LLP Patent Department

20070298584 - Method for fabricating semiconductor device: m

20070298585 - Dielectric deposition and etch back processes for bottom up gapfill: Methods to reduce film cracking in a dielectric layer are described. The methods may include the steps of depositing a first dielectric film on a substrate and removing a top portion of the first dielectric film by performing an etch on the film. The methods may also include depositing a... Agent: Townsend And Townsend And Crew LLP / Amat

20070298586 - Method of manufacturing semiconductor device: The present invention provides a method of manufacturing a semiconductor device. The semiconductor device comprises a semiconductor base made of a first semiconductor material; and a hetero-semiconductor region made of a second semiconductor material having a different band gap from the first semiconductor material and forming a heterojunction with the... Agent: Foley And Lardner LLP Suite 500

20070298587 - Method of separating layers of material: A lift off process is used to separate a layer of material from a substrate by irradiating an interface between the layer of material and the substrate. According to one exemplary process, the layer is separated into a plurality of sections corresponding to dies on the substrate and a homogeneous... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20070298588 - Transfer method for forming a silicon-on-plastic wafer: A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070298589 - Method of producing bonded wafer: There is provided a method of producing a bonded wafer by bonding two silicon wafers for active layer and support layer to each other and then thinning the wafer for active layer, in which nitrogen ions are implanted from the surface of the wafer for active layer to form a... Agent: Sughrue Mion, PLLC

20070298591 - Epitaxial silicon wafer and method for fabricating the same: An epitaxial silicon wafer includes a bulk wafer having a first doping concentration, a first epitaxial layer formed over the bulk wafer, the first epitaxial layer having a second doping concentration which is higher than the first doping concentration, and a second epitaxial layer formed over the first epitaxial layer,... Agent: Morgan Lewis & Bockius LLP

20070298590 - Methods and apparatus for depositing a microcrystalline silicon film for photovoltaic device: Methods for depositing a microcrystalline silicon film layer with improved deposition rate and film quality are provided in the present invention. Also, photovoltaic (PV) cell having a microcrystalline silicon film is provided. In one embodiment, the method produces a microcrystalline silicon film on a substrate at a deposition rate greater... Agent: Patterson & Sheridan, LLP

20070298593 - Epitaxy silicon on insulator (esoi): Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a... Agent: Slater & Matsil, L.L.P.

20070298592 - Method for manufacturing single crystalline gallium nitride material substrate: A gallium nitride substrate is originally grown above a silicon substrate. The present invention easily separates the gallium nitride substrate from the silicon substrate. And the separation is done with a simple etching so that the cost is low.... Agent: Troxell Law Office PLLC

20070298594 - Semiconductor device fabrication method: A semiconductor device fabrication method includes forming an insulating film having an opening on the major surface of single-crystal silicon, and forming an amorphous silicon film on the surface of the single-crystal silicon exposed in the opening and on the surface of the insulating film. The semiconductor device fabrication method... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070298595 - Method for fabricating polysilicon film: A method of fabricating a polysilicon film includes: forming a seed layer on a surface of a substrate; forming a silicon layer over the surface of the seed layer; and performing a laser annealing process to transform the silicon layer into a polysilicon layer at a laser energy equal to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070298596 - Method of removing a photoresist pattern, method of forming a dual polysilicon layer using the removing method and method of manufacturing a semiconductor device using the removing: In a method of removing a photoresist pattern, a photoresist pattern may be formed on an object layer. Impurities may be implanted into the object layer by a first ion implantation process employing the first photoresist pattern as a first ion implantation mask. The photoresist pattern hardened by the first... Agent: Harness, Dickey & Pierce, P.L.C

20070298597 - Method for manufacturing a semiconductor device having a doped silicon film: A method for manufacturing a semiconductor device includes the step of depositing a doped silicon layer doped with a first-conductivity-type dopant and a non-doped silicon layer to form a layered silicon film, implanting a first-conductivity-type dopant into a portion of the layered silicon film disposed in a first region, implanting... Agent: Scully Scott Murphy & Presser, PC

20070298598 - Semiconductor device and method of fabricating semiconductor device: A semiconductor device capable of improving the operating speed and inhibiting the threshold voltage from fluctuation is obtained. In this semiconductor device, fluorine is introduced into at least any of regions extending over the junction interfaces between a first conductivity type semiconductor region and second conductivity type source/drain regions, at... Agent: Mcdermott Will & Emery LLP

20070298599 - Method for fabricating multiple fets of different types: For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region... Agent: Law Office Of Monica H Choi

20070298600 - Method of fabricating semiconductor device and semiconductor device fabricated thereby: A method of fabricating a semiconductor device and a semiconductor device fabricated thereby. The method of fabricating the semiconductor device includes forming gate electrodes on a semiconductor substrate; forming source/drain regions within the semiconductor substrate so as to be located at both sides of each of the gate electrodes; forming... Agent: Myers Bigel Sibley & Sajovec

20070298601 - Method and system for controlled plating of vias: Methods and systems for controlled formation of a resist in a via. In one embodiment, a method for plating at least a portion of the inside of a via formed in an object may include filling the via with a resist capable of selective three-dimensional polymerization. The resist may be... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070298602 - Method for applying solder to redistribution lines: In a method of making an electronic component, an electrically conductive redistribution line is formed on a surface of a semiconductor chip. The redistribution line includes a solder pad. A covering material is formed over the solder pad and an uncovered portion of the redistribution line is passivated. The covering... Agent: Slater & Matsil, L.L.P.

20070298603 - Die configurations and methods of manufacture: A die configuration includes a die having an active side and an inactive side being opposed to the active side. The inactive side is connected to a heat sink. The connecting members can be provided on the active side.... Agent: Slater & Matsil LLP

20070298604 - Method for fabricating single-damascene structure, dual damascene structure, and opening thereof: A method for fabricating a single-damascene opening is described. The method includes providing a substrate having a conductive line formed therein. A barrier layer, a dielectric layer, a metal hard mask layer, a silicon oxynitride layer, a bottom antireflection layer and a patterned photoresist layer are sequentially formed on the... Agent: Jianq Chyun Intellectual Property Office

20070298605 - Method for forming planarizing copper in a low-k dielectric: Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive film has an ability to reflow to form a planar surface upon a thermal... Agent: Blakely Sokoloff Taylor & Zafman

20070298606 - Chemical-mechanical polishing method and apparatus: A method for manufacturing a semiconductor multilayer wafer by manufacturing an intermediate multilayer wafer having a polished layer from which a surface layer is obtained. The surface roughness is reduced by chemical-mechanical polishing (CMP) removal of part of the polish layer with the CMP monitored through reflectometry of light. The... Agent: Winston & Strawn LLP Patent Department

20070298607 - Method for copper damascence fill for forming an interconnect: Methods of fabricating an interconnect, which fundamentally comprises etching back on an overhang section formed over a portion of an opening formed in a dielectric layer, said etching back is selected from one of an electropolishing process and chemical etching process, and said etching back removes the overhang section at... Agent: Blakely Sokoloff Taylor & Zafman

20070298608 - Forming a copper diffusion barrier: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered... Agent: Timothy N. Trop Trop, Pruner & Hu, P.C.

20070298609 - Capping of metal interconnects in integrated circuit electronic devices: A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.... Agent: Senniger Powers

20070298610 - Method for producing electro-optical apparatus: A method for producing an electro-optical apparatus includes forming a WSi film by sputtering including bombarding a target with plasma ions of an atmosphere injected into a vacuum chamber under reduced pressure to eject particles from the target and depositing the particles on a substrate to be used to form... Agent: Advantedge Law Group, LLC

20070298611 - Selective barrier slurry for chemical mechanical polishing: The present invention provides an aqueous polishing composition useful for polishing semiconductor substrates. The composition comprises 0.05 to 50 weight percent abrasive and 0.001 to 5 weight percent iota type carrageenan. The iota type carrageenan has a concentration useful for accelerating the removal rate of tantalum, tantalum nitride and other... Agent: Rohm And Haas Electronic Materials Cmp Holdings, Inc.

20070298612 - Compositions and methods for polishing silicon nitride materials: The present invention provides a method for polishing silicon nitride-containing substrates. The method comprises abrading a surface of a silicon nitride substrate with a polishing composition, which comprises colloidal silica, at least one acidic component, and an aqueous carrier. The at least one acidic component has a pKa in the... Agent: Steven Weseman Associate General Counsel, I.p.

20070298613 - Method of manufacturing suspension structure: A method of manufacturing a suspension structure including providing a substrate, forming a first photoresist pattern on the substrate, heating the first photoresist pattern to harden it as a sacrificial layer, forming a second photoresist pattern on the substrate and the sacrificial layer, the second photoresist pattern exposing a part... Agent: North America Intellectual Property Corporation

20070298614 - Apparatus for etching wafer by single-wafer process and single wafer type method for etching wafer: An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating... Agent: Kolisch Hartwell, P.C.

20070298615 - Pattern forming method and method of manufacturing semiconductor devices: A pattern forming method is provided. The pattern forming method includes a first step of forming a resist pattern including a lactone group-containing skeleton above an etched layer provided on a substrate; a second step of performing plasma processing using a hydrogen-containing gas to lower a glass transition temperature or... Agent: Sonnenschein Nath & Rosenthal LLP

20070298616 - Method of forming a mask pattern for fabricating a semiconductor device: A method of forming a mask pattern for fabricating a semiconductor device. A first region and a second region, having an intersecting third region, are defined in the semiconductor substrate. An inorganic mask layer is etched in the first region to a predetermined thickness, and etched in the second region... Agent: Marger Johnson & Mccollom, P.C.

20070298617 - Processing method: A processing method which, when an organic film layer such as a PR film layer 202 formed on the surface of a wafer W is to be removed from an SiO2 film layer 204 below it by generating plasma of a process gas in a chamber 1 comprises the step... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070298618 - Alkaline etchant for controlling surface roughness of semiconductor wafer: An alkali etchant for controlling surface roughness of a semiconductor wafer, which is a sodium hydroxide solution or a potassium hydroxide solution having a weight concentration of 55 wt % to 70 wt %.... Agent: Greenblum & Bernstein, P.L.C

20070298619 - Method for stripping photoresist: Disclosed is a method for stripping a photoresist comprising: (I) providing a photoresist pattern on a substrate where the substrate has at least a copper (Cu) wiring and a low-dielectric layer thereon, and selectively etching the low-dielectric layer by using the photoresist pattern as a mask; (II) contacting the substrate... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070298620 - Surface treatment, sorting and assembling methods of microelectronic devices and storage structure thereof: A storage structure for a microelectronic device including a chip which has completed all back-end-of-line (BEOL) processes and a solvent dissolvable polymer layer covering the surface of the chip. Since the surface of the chip is isolated from the external environment by the solvent dissolvable polymer layer, corrosion, discoloring or... Agent: Jianq Chyun Intellectual Property Office

20070298621 - Baking method of quartz products, computer program and storage medium: The present invention relates to control of copper contamination to semiconductor substrates upon operation of a heat treatment apparatus which is a semiconductor manufacturing apparatus and which is constructed with quartz products having been contaminated with copper when machined. The quartz product is placed in a heating atmosphere on the... Agent: Smith, Gambrell & Russell

20070298622 - Producing method of semiconductor device: Disclosed is a producing method of a semiconductor device comprising a step of forming a tunnel insulating film of a flash device comprising a first nitridation step of forming a first silicon oxynitride film by nitriding a silicon oxide film formed on a semiconductor silicon base by one of plasma... Agent: Birch Stewart Kolasch & Birch

20070298623 - Method for straining a semiconductor device: A strained semiconductor layer is achieved by an overlying stressed dielectric layer. The stress in the dielectric layer is increased by a radiation anneal. The radiation anneal can be either by scanning using a laser beam or a flash tool that provides the anneal to the whole dielectric layer simultaneously.... Agent: Freescale Semiconductor, Inc. Law Department

20070292977 - Method for monitoring temperature in thermal process: A method for monitoring a temperature in a thermal process is described. A monitor substrate is provided and subject to ion implantation, and a characteristic parameter of the monitor substrate correlated to the disorder degree of the lattice structure of the same is measured to obtain a first value. The... Agent: Jianq Chyun Intellectual Property Office

20070292978 - Method for manufacturing gallium nitride light emitting diode devices: A method for manufacturing GaN LED devices is disclosed herein. First, a LED epitaxial layer is formed on a provisional substrate. Part of the LED epitaxial layer is removed to form a plurality of LED epitaxial areas. Then, a first transparent conductive layer, a metal reflective layer, and a first... Agent: Rosenberg, Klein & Lee

20070292981 - Structure for protecting feataures during the removal of sacrificial materials and a method of manufacture therefor: The present invention provides a process and an apparatus. The process, in one embodiment, includes providing a micro-electro-mechanical system (MEMS) device, the micro-electro-mechanical system (MEMS) device including an actuator coupled to a movable feature, sacrificial material fixing the actuator and movable feature with respect to one another, and a layer... Agent: Hitt Gaines, PC Alcatel-lucent

20070292982 - Method for manufacturing transparent windows in molded semiconductor packages: Methods for packaging light-sensitive semiconductor devices in packages are described in which a transparent window aligned with light-sensitive surfaces of the devices are provided. The methods of the invention include steps for affixing a transparent body to a light-sensitive surface of the semiconductor device, affixing the device to a leadframe,... Agent: Texas Instruments Incorporated

20070292985 - Phase change memory with nanofiber heater: Phase change memories may be formed with nanofiber bottom electrodes or heaters. Because of the use of the relatively well controlled, small diameter nanofibers, better current density, and lower current utilization may be achieved, in some cases, because less phase change material may need to change phase. In some embodiments,... Agent: Trop Pruner & Hu, PC

20070292986 - Method for manufacturing semiconductor device: An object is to provide a semiconductor device with excellent reproducibility which is manufactured at low cost. A method for manufacturing a semiconductor device includes steps of forming a first electrode over a substrate; forming an insulating layer over the substrate and the first electrode; pressing a mold against the... Agent: Nixon Peabody, LLP

20070292973 - Mram layer having domain wall traps: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells... Agent: Knobbe Martens Olson & Bear LLP

20070292974 - Substrate processing method and substrate processing apparatus: Disclosed is a substrate processing method in which a plurality of processing gases are alternately supplied to and exhausted from a processing chamber forming a space in which a substrate or substrates are to be processed to form a desired thin film on the substrate or each of the substrates... Agent: Birch Stewart Kolasch & Birch

20070292975 - Transfer molding apparatus and method for manufacturing semiconductor device: A transfer molding apparatus, wherein said top-half mold and said bottom-half mold form a plurality of cavities interconnected, and wherein said pressure adjusting means reduces the pressure of the cavities every time a specified amount of resin is supplied into any one of a plurality of cavities.... Agent: Volentine & Whitt PLLC

20070292976 - Method and device for the independent extraction of carrier concentration level and electrical junction depth in a semiconductor substrate: The present invention provides a method and device for determining, in a non-destructive way, carrier concentration level and junction depth in a semiconductor substrate, independent from each other, during a single measurement.... Agent: Knobbe Martens Olson & Bear LLP

20070292979 - Semiconductor device and method of fabricating the same: A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the... Agent: Mcdermott Will & Emery LLP

20070292980 - Method for producing nitride semiconductor laser light source and apparatus for producing nitride semiconductor laser light source: A method for producing a nitride semiconductor laser light source is provided. The nitride semiconductor laser light source has a nitride semiconductor laser chip, a stem for mounting the laser chip thereon, and a cap for covering the laser chip. The laser chip is encapsulated in a sealed container composed... Agent: Harness, Dickey & Pierce, P.L.C

20070292983 - Methods for manufacturing a sensor assembly: A method for connecting substrates having electrical conductive elements thereon, comprising: providing at least one spacer between the substrates; applying a conductive material to at least one of the electrical conductive elements; aligning the electrical conductive elements; and, connecting the substrates by urging them together, wherein the at least one... Agent: Martin D Moynihan Prtsi, Inc.

20070292984 - Solid-state imaging device and method for fabricating same: A solid-state imaging device includes a plurality of pixels two-dimensionally arrayed in a well region disposed on a semiconductor substrate, each pixel including a photoelectric conversion section having a charge accumulation region which accumulates signal charge; an element isolation layer which is disposed on the surface of the well region... Agent: Robert J. Depke Lewis T. Steadman

20070292987 - Method of fabricating strained thin film semiconductor layer: A method of fabricating a strained thin film semiconductor layer having less dislocation and less defects than conventional methods, or no dislocation and no defects by controlling a stress distribution in a semiconductor substrate is provided. The method includes forming a trench in a semiconductor substrate, and epitaxially growing a... Agent: Ladas & Parry LLP

20070292988 - Manufacturing method of wiring substrate: A bonding pad and flip chip pads in which the surfaces are formed by different metals are juxtaposed on a substrate. The substrate is immersion-treated with a first adhesive treatment liquid which contains an adhesive giving compound for reacting with only a metal surface and giving adhesion properties and is... Agent: Rankin, Hill, Porter & Clark LLP

20070292989 - Semiconductor device and a method of assembling a semiconductor device: A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070292990 - Semiconductor multi-package module having wire bond interconnect between stacked packages: A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate... Agent: Ishimaru & Zahrt LLP

20070292991 - Method for quantification of analytes in a titanium, tin or silcon tetrachloride sample: s

20070292992 - Method of aligning a contactless semiconductor device interface: Contactless interconnects between an integrated circuit die and an electrical structure are aligned by charging alignment pads on the integrated circuit die to a first voltage, and charging counterpart alignment pads on the electrical structure to a second voltage. The integrated circuit die is disposed in an initial position relative... Agent: Shemwell Gregory & Courtney LLP

20070292993 - Manufacturing method of semiconductor device: Package substrate 3 by which ring shape common wiring 3p for electric supply was formed in the inner area of bonding lead 3j in device region 3v of main surface 3a is used. Since a plurality of first plating lines 3r and fourth plating lines 3u for electric supply connected... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070292994 - Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein: A lead frame comprises a stage for mounting a semiconductor chip thereon, a plurality of leads arranged in the periphery of the stage, and a plurality of lead interconnection members (e.g., dam bars) for interconnecting the leads, wherein a plurality of through holes are formed to penetrate through the lead... Agent: Dickstein Shapiro LLP

20070292995 - Reverse blocking semiconductor device and a method for manufacturing the same: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state... Agent: Rossi, Kimms & Mcdowell LLP.

20070292996 - Method and structure to process thick and thin fins and variable fin to fin spacing: Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070292997 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a... Agent: Eric Robinson

20070292998 - Thin film transistor array substrate and method for manufacturing the same: A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost... Agent: Jianq Chyun Intellectual Property Office

20070292999 - Transistors having implanted channel layers and methods of fabricating the same: A MESFET includes a silicon carbide layer, spaced apart source and drain regions in the silicon carbide layer, a channel region positioned within the silicon carbide layer between the source and drain regions and doped with implanted dopants, and a gate contact on the silicon carbide layer. Methods of forming... Agent: Myers Bigel Sibley & Sajovec

20070293000 - Metal resistor, resistor material and method: A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W),... Agent: Hoffman, Warnick & D'alessandro LLC

20070293001 - Silicon carbide schottky diode and method of making the same: A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n− silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried... Agent: Birch Stewart Kolasch & Birch

20070293002 - Method of fabricating a high-voltage transistor with an extended drain structure: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls partially filling each of the trenches with a dielectric material that covers the... Agent: The Law Offices Of Bradley J. Bereznak

20070293003 - Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there... Agent: Goodwin Procter LLP Patent Administrator

20070293004 - Integrated cmos and bipolar devices method and structure: A method is provided for forming bipolar (103) and MOS (105) semiconductor devices in a common substrate (46), comprising, forming a combination comprising an MOS device (105) in a first region (44) of the substrate (46) and a portion (50) of a collector region (82, 64, 62, 50) of the... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070293005 - Parts combining structure, and electronic apparatus: A parts combining structure is provided with first part having thermoplastic projection, and a second part having through portion to insert the projection. By thermally crushing the distal end of the projection projecting from the through portion, the first part and second part are combined. The through portion of the... Agent: Blakely Sokoloff Taylor & Zafman

20070293006 - Method for fabricating a charg trapping memory device: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070293007 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the... Agent: Mcdermott Will & Emery LLP

20070293008 - Trench drain with sloping rails: A modular trench drain system with sloping overlay rails. A non-sloping section of trench drain is transformed into a sloping trench drain by installing sloping overlay rails. The overlay rails rest on the top of the upper edge of the sidewalls and may have a ledge which allows grating, which... Agent: Christie, Parker & Hale, LLP

20070293009 - Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there... Agent: Goodwin Procter LLP Patent Administrator

20070293010 - Buried biasing wells in fets (field effect transistors): A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region... Agent: Schmeiser, Olsen & Watts

20070293011 - Field effect transistor device with channel fin structure and method of fabricating the same: A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess... Agent: Marger Johnson & Mccollom, P.C.

20070293012 - Reduction of slip and plastic deformations during annealing by the use of ultra-fast thermal spikes: Exemplary embodiments provide methods for reducing and/or removing slip and plastic deformations in semiconductor materials by use of one or more ultra-fast thermal spike anneals. The ultra-fast thermal spike anneal can be an ultra-high temperature (UHT) anneal having an ultra-short annealing time. During the ultra-fast thermal spike anneal, an increased... Agent: Texas Instruments Incorporated

20070293013 - Method of forming a bipolar transistor and semiconductor component thereof: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the... Agent: Walter P. Opaska Bryan Cave LLP

20070293014 - Method for forming metal-insulator-metal capacitor of semiconductor device: A method for forming a Metal-Insulator-Metal capacitor of a semiconductor device includes forming an insulation layer, a lower conductive layer, a dielectric layer and an upper conductive layer on a semiconductor substrate; forming, on the upper conductive layer, a protective insulation layer wherein an etching selectivity of the lower conductive... Agent: Lowe Hauptman Ham & Berner, LLP

20070293015 - Iii-nitride device and method with variable epitaxial growth direction: A semiconductor device composed of III-nitride materials is produced with epitaxial growth that permits vertical and lateral growth geometries to improve device characteristics. The resulting device has a greater breakdown voltage due to the greater integrity of the semiconductor material structure since no ion implantation processes are used. The epitaxially... Agent: Ostrolenk Faber Gerb & Soffen

20070293017 - Method of fabricating shallow trench isolation structure: A method of fabricating a shallow trench isolation structure is provided. A substrate is provided with a pad layer, a mask layer and a shallow trench formed therein. A liner oxide layer is formed on the sidewall of the shallow trench and then a silicon nitride layer is formed conformably... Agent: J.c. Patents, Inc.

20070293016 - Semiconductor structure including isolation region with variable linewidth and method for fabrication therof: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within... Agent: Scully, Scott, Murphy & Presser, P.C.

20070293018 - Method of fabricating semiconductor device with shallow trench isolation: In fabrication of a semiconductor device, a first insulating film, electrode film and silicon nitride film sequentially stacked on a semiconductor substrate are etched with the substrate so that a trench is formed. The electrode film is then exposed. A second insulating film buried in the trench is isotropically etched... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070293019 - Methods of die sawing and structures formed thereby: A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one... Agent: Duane Morris LLPIPDepartment (tsmc)

20070293020 - Singulating semiconductor wafers to form semiconductor chips: One aspect relates to a method for singulating semiconductor wafers to form semiconductor chips. A semiconductor wafer is provided with semiconductor chip positions arranged in rows and columns, rectilinear separating tracks being arranged between the positions. Crystallographic strains are induced into the region of the separating tracks. This is followed... Agent: Dicke, Billig & Czaja

20070293021 - Wafer dividing method: A method of dividing a wafer having a plurality of areas defined by the plurality of streets formed in a lattice on the front surface, devices formed in the defined areas and an adhesive film for die bonding on the rear surface and put on a dicing tape affixed to... Agent: Smith, Gambrell & Russell

20070293022 - Method of and apparatus for detaching semiconductor chips from a tape: An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first... Agent: Volentine & Whitt PLLC

20070293023 - Method of fabricating suspended structure: A method of fabricating a suspended structure. First, a substrate including a photoresist layer hardened by heat is provided. Subsequently, the hardened photoresist layer is etched so as to turn the photoresist layer into a predetermined edge profile. Thereafter, a structure layer is formed on parts of the substrate and... Agent: North America Intellectual Property Corporation

20070293024 - Method of crystallizing amorphous silicon and device fabricated using the same: A method of crystallizing amorphous silicon includes forming an amorphous silicon film over a substrate, crystallizing the amorphous silicon film to form a polycrystalline silicon film using a sequential lateral solidification crystallization method, and performing a surface treatment to the polycrystalline silicon film, wherein the sequential lateral solidification crystallization method... Agent: Mckenna Long & Aldridge LLP

20070293025 - Protect diodes for hybrid-orientation substrate structures: A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from... Agent: Schmeiser, Olsen & Watts

20070293026 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes the step of performing an ion implantation process for implanting an impurity ion into a semiconductor substrate, and performing annealing in a state where temperature of respective portions of an annealing chamber are set differently in order to activate the impurity ion.... Agent: Townsend And Townsend And Crew, LLP

20070293027 - Dopant diffusion method and method of manufacturing semiconductor device: A dopant diffusion method includes: diffusing a dopant element into a semiconductor through an oxide film. The dopant element is contained in a compound gas having a gas partial pressure of not less than 0.1 torr and not more than 800 torr. A temperature of the semiconductor is set less... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070293028 - Method of forming low forward voltage shottky barrier diode with locos structure therein: A method of forming a power Schottky rectifier device is disclosed. The Schottky rectifier device including LOCOS structure and two p doped layers formed thereunder to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n− drift layer formed on an n+ substrate; a cathode metal layer formed... Agent: Birch Stewart Kolasch & Birch

20070293029 - Method for fabricating semiconductor device: The method for fabricating the semiconductor device includes the steps of: forming an insulating film 20, a conductive film 22 and an insulating film 24 over a semiconductor substrate 10 having a first to a third region; removing an insulating film 24, the conductive film 22 and an insulating film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070293030 - Semiconductor device having silicide thin film and method of forming the same: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed... Agent: Marger Johnson & Mccollom, P.C.

20070293031 - Split poly-sige/poly-si alloy gate stack: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of... Agent: John A. Jordan, Esq.

20070293032 - Semiconductor manufacturing apparatus and semiconductor device manufacturing method: A semiconductor manufacturing apparatus includes a controller, a wafer stage and an optical unit. The wafer stage is configured to move a semiconductor wafer. The optical unit is configured to expose a first resist film in each of shots of the semiconductor wafer by using a first mask pattern and... Agent: Mcginn Intellectual Property Law Group, PLLC

20070293033 - Microelectronic assembly with back side metallization and method for forming the same: A method is provided for forming a microelectronic assembly. A contact structure (46) is formed over a first side of a first substrate (20) having a microelectronic device formed over a second side thereof. The contact structure is electrically connected to the microelectronic device. A non-solderable layer (52) is formed... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070293034 - Unlanded via process without plasma damage: A semiconductor device with an unlanded via having an air gap dielectric layer and a silicon-rich oxide (SRO) inter-metal dielectric (IMD) layer, and a method of making the same are provided. The SRO layer acts as an etch-stop layer to prevent unlanded via penetration completely through the IMD layer. In... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070293035 - Interlayer insulating layer and method of manufacturing the same: When an insulating layer is patterned by etching, end surfaces of the insulating layer are perpendicularly formed. By doing so, for example, the diameter of a coil of a magnetic head can be reduced and in turn the magnetic head can be miniaturized. A method of manufacturing an interlayer insulating... Agent: Greer, Burns & Crain

20070293036 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070293037 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Room 301/302

20070293038 - Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate: The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A... Agent: Robert J. Depke Lewis T. Steadman

20070293039 - Combined copper plating method to improve gap fill: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like... Agent: HorizonIPPte Ltd

20070293040 - Filling deep features with conductors in semiconductor manufacturing: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor... Agent: Knobbe, Martens, Olsen & Bear LLP

20070293041 - Sub-lithographic feature patterning using self-aligned self-assembly polymers: A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling... Agent: Scully Scott Murphy & Presser, PC

20070293042 - Semiconductor die with protective layer and related method of processing a semiconductor wafer: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.... Agent: Volentine & Whitt PLLC

20070293045 - Semiconductor device and method for fabricating the same: A semiconductor device may include a semiconductor substrate having a trench, a device isolation layer filling the trench, and a liner nitride layer disposed between the semiconductor substrate and the device isolation layer. The device isolation layer may additionally cover a portion of the substrate surrounding the trench. The liner... Agent: Harness, Dickey & Pierce, P.L.C

20070293043 - Edge gas injection for critical dimension uniformity improvement: A method of etching a semiconductor substrate with improved critical dimension uniformity comprises supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber; supplying a first etch gas to a central region over the semiconductor substrate; supplying a second gas comprising at least one silicon... Agent: Buchanan, Ingersoll & Rooney PC

20070293044 - Patterning 3d features in a substrate: Methods of forming a 3D structure in a substrate are disclosed. A layer of resist is deposited on the substrate. The layer of resist is patterned to define an edge at a predetermined location. The resist is reflowed to form a tapered region extending from the etch. Both the reflowed... Agent: Townsend And Townsend And Crew LLP / Amat

20070293046 - Method for forming metal wiring of semiconductor device and a semiconductor device manufactured by the same: A method for forming a metal wiring of a semiconductor device, includes forming a first metal layer on a wafer, partially etching a portion of the first metal layer where a metal wiring is to be formed, sequentially forming a first copper barrier layer, a copper seed layer, and a... Agent: Lowe Hauptman Ham & Berner, LLP

20070293048 - Polishing slurry: A polishing slurry, including an oxidizer, a corrosion inhibitor, and a polishing rate enhancer, wherein the polishing rate enhancer is a heterocyclic compound having at least one nitrogen in the ring, and the nitrogen is not directly bonded to a hydrogen atom which is mostly dissociated in the slurry.... Agent: Lee & Morse, P.C.

20070293047 - Polishing method and method for fabricating semiconductor device: A polishing method includes causing a polishing pad arranged on a turn table to rotate together with the turn table, and polishing a surface of a substrate by using the rotating polishing pad while supplying a chemical fluid to a surface of the polishing pad on a fore side of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

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