Semiconductor device manufacturing: process inventions 12/07

20070298521 - Method for cleaning post-etch noble metal residues: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on... Agent: Texas Instruments Incorporated

20070298522 - Method and apparatus for process control with in-die metrology: Various embodiments include a method for providing instructions to a process tool. The method includes emitting an incident light beam at a substrate, receiving a reflected light beam from the substrate and determining a spectrum of the reflected light beam. The method further includes determining a first property of a... Agent: Carr & Ferrell LLP

20070298525 - Integrated microelectronic package stress sensor: Stress in microelectronic integrated circuit packages may be measured in situ using carbon nanotube networks. An array of carbon nanotubes strung between upstanding structures may be used to measure the local stress in two dimensions. Because of the characteristics of the carbon nanotubes, a highly accurate stress measurement may be... Agent: Trop Pruner & Hu, PC

20070298524 - Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same: The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical... Agent: Williams, Morgan & Amerson

20070298527 - Determining geometrical configuration of interconnect structure: Methods are disclosed for determining a geometrical configuration of an interconnect structure of a test structure without cross-sectioning or optical measurements. In one embodiment, the method includes obtaining simulation data correlating capacitance data, resistance data and geometrical configuration data for a plurality of interconnect structures having different geometrical configurations; measuring... Agent: Hoffman, Warnick & D'alessandro LLC

20070298532 - Micro-electro-mechanical (mems) encapsulation using buried porous silicon: An apparatus comprising a substrate having therein one or more porous regions, a micro-electro-mechanical (MEMS) device formed on the substrate, a cap formed on the substrate, wherein the cap encapsulates the MEMS device and is formed over at least one of the one or more porous regions, and a sealing... Agent: Blakely Sokoloff Taylor & Zafman

20070298533 - Method and apparatus providing imager pixel array with grating structure and imager device containing the same: An imager pixel array capable of separating and detecting the spectral components of an incident light without the use of a color filter array. The imager pixel array employs a grating layer which allows one or more spectral components of incident light to be transmitted therethrough, but diffracts other spectral... Agent: Dickstein Shapiro LLP

20070298520 - Method of producing an element comprising an electrical conductor encircled by magnetic material: A method of producing an electrical inductor circuit element comprising an elongate electrical conductor encircled by magnetic material extending along at least a part of the conductor. First and second sacrificial layers are formed across the conductor respectively above and below the conductor, at least parts of the sacrificial layers... Agent: Freescale Semiconductor, Inc. Law Department

20070298523 - Silicon wafers and method of fabricating the same: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution... Agent: Marshall, Gerstein & Borun LLP

20070298526 - Programmable semiconductor device: A design structure for designing and manufacturing a programmable device. The design structure includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is... Agent: Ibm Microelectronics Intellectual Property Law

20070298528 - Semiconductor laser manufacturing method: A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a conductive film, which... Agent: Mcdermott Will & Emery LLP

20070298529 - Semiconductor light-emitting device and method for separating semiconductor light-emitting devices: The invention provides a method for separating semiconductor light-emitting devices formed on a substrate. In the method, a pulse laser beam having a pulse width less than 10 ps in a substrate is focused on the substrate, to thereby cause multi-photon absorption in the substrate. Through multi-photon absorption, a groove... Agent: Mcginn Intellectual Property Law Group, PLLC

20070298530 - Process for making an organic electronic device: There is provided a process for forming an organic electronic device. The process includes the steps: forming a first layer, which includes an electrically conductive material and a fluorinated acid polymer, the first layer having a first surface energy; forming a second layer over the first layer, the second layer... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070298531 - Quantum well intermixing in semiconductor photonic devices: A method for fabricating a semiconductor device in a semiconductor structure, provides enhanced quantum well intermixing in desired regions of the device by forming a first, relatively high quality, epitaxial layer on a substrate, the high quality layer including a quantum well; forming a second, relatively lower quality, epitaxial defect... Agent: Momkus Mccluskey Monroe Marsh & Spyratos, LLC

20070298534 - Electronic device and method of manufacturing the same: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070298535 - Memory cell with memory material insulation and manufacturing method: A memory cell, the memory cell includes first and second electrodes and a memory material element electrically coupling the first and second electrodes. The memory material element comprises a first memory material, such as GST, the first memory material having an electrical property that can be changed by the application... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070298536 - Single-crystal metal nanocrystals: Methods for producing nanocrystals comprising metallic materials utilizing an inverse micelle solvothermal process are disclosed. Nanocrystals comprising well-ordered, single-crystalline germanium (Ge) materials with predeterminable morphologies in relatively high purity are produced by suspending a Ge salt material comprising a metal ion in a non-aqueous inverse micelle solvent comprising at least... Agent: Greenberg Traurig, LLP

20070298537 - Diamond composite heat spreader and associated methods: Diamond heat spreaders are produced having thermal properties approaching that of pure diamond. Diamond particles of relatively large grain size are tightly packed to maximize diamond-to-diamond contact. Subsequently, smaller diamond particles may be introduced into the interstitial voids to further increase the diamond content per volume. An interstitial material is... Agent: Thorpe North & Western, LLP.

20070298538 - Liquid crystal display device: The present invention provides a liquid crystal display device having a large holding capacitance in the inside of a pixel. A liquid crystal display device includes a first substrate, a second substrate arranged to face the first substrate in an opposed manner, and liquid crystal sandwiched between the first substrate... Agent: Stanley P. Fisher Reed Smith LLP

20070298539 - Method for bonding semiconductor chip: A method for bonding a semiconductor chip is disclosed. In accordance with the method of the present invention, a front surface of a wafer is mounted in a wafer holder to face downward. Each of dies of the wafer is then pushed downward to a tray disposed therebelow, thereby eliminating... Agent: Sughrue Mion, PLLC

20070298540 - Dicing and packing metod of sheet-like wafer, packed product of water, and separation jig: To provide a dicing and packing method of a sheet-like wafer that can collectively solve conventional problems such as damage of an individual piece, generation of dusts, and increase of troublesome work at a time of packing, caused in a process of packing the individual pieces obtained by dicing a... Agent: Quinn Emanuel Koda & Androlia

20070298541 - Method and system for sealing a substrate: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate a... Agent: Knobbe Martens Olson & Bear LLP

20070298542 - Multiple internal seal ring micro-electro-mechanical system vacuum packaging method: A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum packaging method that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk... Agent: Canady & Lortz LLP

20070298543 - Method for manufacturing heat sink of semiconductor device: A method for manufacturing a heat sink of a semiconductor device is described. In the method, an adhesive tape is provided, wherein the adhesive tape includes a first surface and a second surface on opposite sides, and the first surface of the adhesive tape adheres to a surface of a... Agent: Lowe Hauptman Ham & Berner, LLP

20070298544 - Manufacturing method for a leadless multi-chip electronic module: A leadless multi-chip electronic module with leadframe bond pads is manufactured in a manner to place small signal bond pads in a central region of the module for significantly increased reliability of solder joints between such bond pads and a substrate of the module. A linear array of parallel leadframe... Agent: Delphi Technologies, Inc.

20070298545 - Method of manufacturing a semiconductor device: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070298546 - Manufacturing method package substrate: A manufacturing method of a package substrate is disclosed. The method for manufacturing a package substrate is by forming a bump on a bump pad in a core board, where a first circuit pattern including the bump pad is formed on one surface, a second circuit pattern electrically connected with... Agent: Staas & Halsey LLP

20070298547 - Semiconductor device having a composite passivation layer and method of manufacturing the same: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device comprises a fuse bank with a fuse window, a pad area with a pad window, and a composite passivation layer comprising a sacrificial dielectric layer and a final passivation layer. Both the fuse window and... Agent: Nixon Peabody LLP - Patent Group

20070298548 - Active matrix display: The active matrix display includes a polysilicon layer including a source region, a drain region and a channel region and placed on an insulating substrate, a gate insulating layer placed on the polysilicon layer, a gate electrode placed on the gate insulating layer, an interlayer insulating layer placed on the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070298550 - Method for making thin-film semiconductor device: A method for making a thin-film semiconductor device includes an annealing step of irradiating an amorphous semiconductor thin film with a laser beam so as to crystallize the amorphous semiconductor thin film. In the annealing step, the semiconductor thin film is continuously irradiated with the laser beam while shifting the... Agent: Wolf Greenfield & Sacks, P.C.

20070298549 - Method of fabricating a strained multi-gate transistor and devices obtained thereof: A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a... Agent: Knobbe Martens Olson & Bear LLP

20070298551 - Fabrication of silicon nano wires and gate-all-around mos devices: The invention relates to methods for manufacturing semiconductor devices. Processes are disclosed for implementing suspended single crystal silicon nano wires (NWs) using a combination of anisotropic and isotropic etches and spacer creation for sidewall protection. The core dimensions of the NWs are adjustable with the integration sequences: they can be... Agent: Nixon & Vanderhye, PC

20070298552 - High performance 3d fet structures, and methods for forming the same using preferential crystallographic etching: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used... Agent: Scully, Scott, Murphy & Presser, P.C.

20070298553 - Thin film transistor and method for production thereof: The production method of the thin film transistor according to the present invention involves the reactive heat CVD process to form the active layer and the source-drain layer. This offers the advantage of eliminating additional steps to crystallize the semiconductor thin film. The resulting stacked thin film transistor is composed... Agent: Sonnenschein Nath & Rosenthal LLP

20070298554 - Tft lcd array substrate and manufacturing method thereof: The present invention discloses a method for manufacturing a TFT LCD array substrate by utilizing the gray tone mask technology and the photoresist lifting-off technology with only two masks in two photolithography processes, and to a TFT LCD array substrate manufactured by the same. In the resultant array substrate, the... Agent: Hasse & Nesbitt LLC

20070298555 - Method of manufacturing a semiconductor device: An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device.... Agent: Eric Robinson

20070298556 - Field effect transistor with enhanced insulator structure: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and... Agent: Ostrolenk Faber Gerb & Soffen

20070298557 - Junction leakage reduction in sige process by tilt implantation: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a stressor in the semiconductor substrate adjacent to an edge of the gate electrode; and tilt implanting... Agent: Slater & Matsil, L.L.P.

20070298558 - Method of fabricating semiconductor device and semiconductor device: A semiconductor device includes a first semiconductor region of first type conductivity with a channel region being formed therein, a gate electrode insulatively formed above the channel region, a layer of SixGe1-x (0<x<1) on both sides of the channel region, a pair of second semiconductor regions of second type conductivity... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070298559 - Vertical field-effect transistor and method of forming the same: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes... Agent: Slater & Matsil, L.L.P.

20070298560 - Semiconductor device: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070298561 - Integrated sige nmos and pmos transistors: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar... Agent: Texas Instruments Incorporated

20070298562 - Method of manufacturing a semiconductor integrated circuit device: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an... Agent: Staas & Halsey LLP

20070298563 - Method of manufacturing a semiconductor integrated circuit device: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an... Agent: Staas & Halsey LLP

20070298564 - Vertical field-effect transistor and method of forming the same: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes... Agent: Slater & Matsil, L.L.P.

20070298565 - Junction leakage reduction in sige process by implantation: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity... Agent: Slater & Matsil, L.L.P.

20070298566 - Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance: Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20070298567 - Sram cell structure and manufacturing method thereof: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over... Agent: J.c. Patents

20070298568 - Scaled dielectric enabled by stack sidewall process: Non-volatile storage elements (or other device) are created. One embodiment includes creating floating gate stacks comprising a floating gate, a control gate and a dielectric between the floating gate and the control gate. One example of a suitable dielectric includes a first layer of oxide, a layer of nitride and... Agent: Vierra Magen/sandisk Corporation

20070298569 - Non-volatile memory having three states and method for manufacturing the same: Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon substrate and the floating gate below... Agent: Ladas & Parry LLP

20070298570 - Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors: The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain... Agent: Wells St. John P.s.

20070298571 - Single chip data processing device with embedded nonvolatile memory and method thereof: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant... Agent: Harness, Dickey & Pierce, P.L.C

20070298572 - Field effect transistors (fets) with multiple and/or staircase silicide: A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact... Agent: Schmeiser, Olsen & Watts

20070298573 - Semiconductor device and method for manufacturing the same: The invention is directed to a method for manufacturing a semiconductor device. The method comprises steps of forming a gate dielectric layer, a polysilicon layer and a patterned cap layer over a substrate sequentially and patterning the polysilicon layer to be a polysilicon gate by using the patterned cap layer... Agent: Jianq Chyun Intellectual Property Office

20070298574 - Method of fabricating different semiconductor device types with reduced sets of pattern levels: A method of manufacturing an integrated circuit comprising forming gate structures for first, second and third semiconductor device types located on a semiconductor substrate. A dopant block is formed over the second semiconductor device type and first dopants are implanted into unblocked regions of the semiconductor substrate corresponding to the... Agent: Texas Instruments Incorporated

20070298575 - Methods for contact resistance reduction of advanced cmos devices: Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by... Agent: Patterson & Sheridan, LLP

20070298577 - Method for manufacturing semiconductor device: An excessive etch in the conventional manufacturing process causes a roughened surface of a contact bottom, resulting in an increased variation in characteristics of semiconductor devices. A bipolar transistor having a collector region 4 provided in a bottom of a trench formed in a P-type silicon substrate 1 is formed.... Agent: Young & Thompson

20070298576 - Methods of forming bipolar transistors by silicide through contact and structures formed thereby: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming an opening in a masking layer, implanting an amorphizing species into a silicon region disposed within the opening, wherein the silicon region comprises a portion of an emitter of a bipolar transistor; and forming... Agent: Intel Corporation C/o Intellevate, LLC

20070298578 - Bipolar transistor with dual shallow trench isolation and low base resistance: An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair... Agent: Scully Scott Murphy & Presser, PC

20070298579 - Methods of employing a thin oxide mask for high dose implants: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate... Agent: Texas Instruments Incorporated

20070298580 - Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating: Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a... Agent: Mills & Onello LLP

20070298581 - Method of manufacturing suspension structure and chamber: A method of manufacturing a suspension structure including providing a substrate, forming a hole and a sacrificial layer filling the hole on the substrate, forming a patterned photoresist layer on the substrate and the sacrificial layer, the patterned photoresist layer exposing a part of the substrate and the sacrificial layer,... Agent: North America Intellectual Property Corporation

20070298582 - Method of performing a double-sided process: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the... Agent: North America Intellectual Property Corporation

20070298583 - Method for forming a shallow trench isolation region: A method for forming a shallow trench isolation region (STI) is disclosed. The method comprises the steps of sequentially forming a pad oxide layer and a nitride silicon layer over a provided substrate. Next, the pad oxide layer, the nitride silicon layer, and the substrate are partially etched to form... Agent: Baker & Mckenzie LLP Patent Department

20070298584 - Method for fabricating semiconductor device: m

20070298585 - Dielectric deposition and etch back processes for bottom up gapfill: Methods to reduce film cracking in a dielectric layer are described. The methods may include the steps of depositing a first dielectric film on a substrate and removing a top portion of the first dielectric film by performing an etch on the film. The methods may also include depositing a... Agent: Townsend And Townsend And Crew LLP / Amat

20070298586 - Method of manufacturing semiconductor device: The present invention provides a method of manufacturing a semiconductor device. The semiconductor device comprises a semiconductor base made of a first semiconductor material; and a hetero-semiconductor region made of a second semiconductor material having a different band gap from the first semiconductor material and forming a heterojunction with the... Agent: Foley And Lardner LLP Suite 500

20070298587 - Method of separating layers of material: A lift off process is used to separate a layer of material from a substrate by irradiating an interface between the layer of material and the substrate. According to one exemplary process, the layer is separated into a plurality of sections corresponding to dies on the substrate and a homogeneous... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20070298588 - Transfer method for forming a silicon-on-plastic wafer: A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070298589 - Method of producing bonded wafer: There is provided a method of producing a bonded wafer by bonding two silicon wafers for active layer and support layer to each other and then thinning the wafer for active layer, in which nitrogen ions are implanted from the surface of the wafer for active layer to form a... Agent: Sughrue Mion, PLLC

20070298591 - Epitaxial silicon wafer and method for fabricating the same: An epitaxial silicon wafer includes a bulk wafer having a first doping concentration, a first epitaxial layer formed over the bulk wafer, the first epitaxial layer having a second doping concentration which is higher than the first doping concentration, and a second epitaxial layer formed over the first epitaxial layer,... Agent: Morgan Lewis & Bockius LLP

20070298590 - Methods and apparatus for depositing a microcrystalline silicon film for photovoltaic device: Methods for depositing a microcrystalline silicon film layer with improved deposition rate and film quality are provided in the present invention. Also, photovoltaic (PV) cell having a microcrystalline silicon film is provided. In one embodiment, the method produces a microcrystalline silicon film on a substrate at a deposition rate greater... Agent: Patterson & Sheridan, LLP

20070298593 - Epitaxy silicon on insulator (esoi): Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a... Agent: Slater & Matsil, L.L.P.

20070298592 - Method for manufacturing single crystalline gallium nitride material substrate: A gallium nitride substrate is originally grown above a silicon substrate. The present invention easily separates the gallium nitride substrate from the silicon substrate. And the separation is done with a simple etching so that the cost is low.... Agent: Troxell Law Office PLLC

20070298594 - Semiconductor device fabrication method: A semiconductor device fabrication method includes forming an insulating film having an opening on the major surface of single-crystal silicon, and forming an amorphous silicon film on the surface of the single-crystal silicon exposed in the opening and on the surface of the insulating film. The semiconductor device fabrication method... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070298595 - Method for fabricating polysilicon film: A method of fabricating a polysilicon film includes: forming a seed layer on a surface of a substrate; forming a silicon layer over the surface of the seed layer; and performing a laser annealing process to transform the silicon layer into a polysilicon layer at a laser energy equal to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070298596 - Method of removing a photoresist pattern, method of forming a dual polysilicon layer using the removing method and method of manufacturing a semiconductor device using the removing: In a method of removing a photoresist pattern, a photoresist pattern may be formed on an object layer. Impurities may be implanted into the object layer by a first ion implantation process employing the first photoresist pattern as a first ion implantation mask. The photoresist pattern hardened by the first... Agent: Harness, Dickey & Pierce, P.L.C

20070298597 - Method for manufacturing a semiconductor device having a doped silicon film: A method for manufacturing a semiconductor device includes the step of depositing a doped silicon layer doped with a first-conductivity-type dopant and a non-doped silicon layer to form a layered silicon film, implanting a first-conductivity-type dopant into a portion of the layered silicon film disposed in a first region, implanting... Agent: Scully Scott Murphy & Presser, PC

20070298598 - Semiconductor device and method of fabricating semiconductor device: A semiconductor device capable of improving the operating speed and inhibiting the threshold voltage from fluctuation is obtained. In this semiconductor device, fluorine is introduced into at least any of regions extending over the junction interfaces between a first conductivity type semiconductor region and second conductivity type source/drain regions, at... Agent: Mcdermott Will & Emery LLP

20070298599 - Method for fabricating multiple fets of different types: For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region... Agent: Law Office Of Monica H Choi

20070298600 - Method of fabricating semiconductor device and semiconductor device fabricated thereby: A method of fabricating a semiconductor device and a semiconductor device fabricated thereby. The method of fabricating the semiconductor device includes forming gate electrodes on a semiconductor substrate; forming source/drain regions within the semiconductor substrate so as to be located at both sides of each of the gate electrodes; forming... Agent: Myers Bigel Sibley & Sajovec

20070298601 - Method and system for controlled plating of vias: Methods and systems for controlled formation of a resist in a via. In one embodiment, a method for plating at least a portion of the inside of a via formed in an object may include filling the via with a resist capable of selective three-dimensional polymerization. The resist may be... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070298602 - Method for applying solder to redistribution lines: In a method of making an electronic component, an electrically conductive redistribution line is formed on a surface of a semiconductor chip. The redistribution line includes a solder pad. A covering material is formed over the solder pad and an uncovered portion of the redistribution line is passivated. The covering... Agent: Slater & Matsil, L.L.P.

20070298603 - Die configurations and methods of manufacture: A die configuration includes a die having an active side and an inactive side being opposed to the active side. The inactive side is connected to a heat sink. The connecting members can be provided on the active side.... Agent: Slater & Matsil LLP

20070298604 - Method for fabricating single-damascene structure, dual damascene structure, and opening thereof: A method for fabricating a single-damascene opening is described. The method includes providing a substrate having a conductive line formed therein. A barrier layer, a dielectric layer, a metal hard mask layer, a silicon oxynitride layer, a bottom antireflection layer and a patterned photoresist layer are sequentially formed on the... Agent: Jianq Chyun Intellectual Property Office

20070298605 - Method for forming planarizing copper in a low-k dielectric: Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive film has an ability to reflow to form a planar surface upon a thermal... Agent: Blakely Sokoloff Taylor & Zafman

20070298606 - Chemical-mechanical polishing method and apparatus: A method for manufacturing a semiconductor multilayer wafer by manufacturing an intermediate multilayer wafer having a polished layer from which a surface layer is obtained. The surface roughness is reduced by chemical-mechanical polishing (CMP) removal of part of the polish layer with the CMP monitored through reflectometry of light. The... Agent: Winston & Strawn LLP Patent Department

20070298607 - Method for copper damascence fill for forming an interconnect: Methods of fabricating an interconnect, which fundamentally comprises etching back on an overhang section formed over a portion of an opening formed in a dielectric layer, said etching back is selected from one of an electropolishing process and chemical etching process, and said etching back removes the overhang section at... Agent: Blakely Sokoloff Taylor & Zafman

20070298608 - Forming a copper diffusion barrier: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered... Agent: Timothy N. Trop Trop, Pruner & Hu, P.C.

20070298609 - Capping of metal interconnects in integrated circuit electronic devices: A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.... Agent: Senniger Powers

20070298610 - Method for producing electro-optical apparatus: A method for producing an electro-optical apparatus includes forming a WSi film by sputtering including bombarding a target with plasma ions of an atmosphere injected into a vacuum chamber under reduced pressure to eject particles from the target and depositing the particles on a substrate to be used to form... Agent: Advantedge Law Group, LLC

20070298611 - Selective barrier slurry for chemical mechanical polishing: The present invention provides an aqueous polishing composition useful for polishing semiconductor substrates. The composition comprises 0.05 to 50 weight percent abrasive and 0.001 to 5 weight percent iota type carrageenan. The iota type carrageenan has a concentration useful for accelerating the removal rate of tantalum, tantalum nitride and other... Agent: Rohm And Haas Electronic Materials Cmp Holdings, Inc.

20070298612 - Compositions and methods for polishing silicon nitride materials: The present invention provides a method for polishing silicon nitride-containing substrates. The method comprises abrading a surface of a silicon nitride substrate with a polishing composition, which comprises colloidal silica, at least one acidic component, and an aqueous carrier. The at least one acidic component has a pKa in the... Agent: Steven Weseman Associate General Counsel, I.p.

20070298613 - Method of manufacturing suspension structure: A method of manufacturing a suspension structure including providing a substrate, forming a first photoresist pattern on the substrate, heating the first photoresist pattern to harden it as a sacrificial layer, forming a second photoresist pattern on the substrate and the sacrificial layer, the second photoresist pattern exposing a part... Agent: North America Intellectual Property Corporation

20070298614 - Apparatus for etching wafer by single-wafer process and single wafer type method for etching wafer: An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating... Agent: Kolisch Hartwell, P.C.

20070298615 - Pattern forming method and method of manufacturing semiconductor devices: A pattern forming method is provided. The pattern forming method includes a first step of forming a resist pattern including a lactone group-containing skeleton above an etched layer provided on a substrate; a second step of performing plasma processing using a hydrogen-containing gas to lower a glass transition temperature or... Agent: Sonnenschein Nath & Rosenthal LLP

20070298616 - Method of forming a mask pattern for fabricating a semiconductor device: A method of forming a mask pattern for fabricating a semiconductor device. A first region and a second region, having an intersecting third region, are defined in the semiconductor substrate. An inorganic mask layer is etched in the first region to a predetermined thickness, and etched in the second region... Agent: Marger Johnson & Mccollom, P.C.

20070298617 - Processing method: A processing method which, when an organic film layer such as a PR film layer 202 formed on the surface of a wafer W is to be removed from an SiO2 film layer 204 below it by generating plasma of a process gas in a chamber 1 comprises the step... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070298618 - Alkaline etchant for controlling surface roughness of semiconductor wafer: An alkali etchant for controlling surface roughness of a semiconductor wafer, which is a sodium hydroxide solution or a potassium hydroxide solution having a weight concentration of 55 wt % to 70 wt %.... Agent: Greenblum & Bernstein, P.L.C

20070298619 - Method for stripping photoresist: Disclosed is a method for stripping a photoresist comprising: (I) providing a photoresist pattern on a substrate where the substrate has at least a copper (Cu) wiring and a low-dielectric layer thereon, and selectively etching the low-dielectric layer by using the photoresist pattern as a mask; (II) contacting the substrate... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070298620 - Surface treatment, sorting and assembling methods of microelectronic devices and storage structure thereof: A storage structure for a microelectronic device including a chip which has completed all back-end-of-line (BEOL) processes and a solvent dissolvable polymer layer covering the surface of the chip. Since the surface of the chip is isolated from the external environment by the solvent dissolvable polymer layer, corrosion, discoloring or... Agent: Jianq Chyun Intellectual Property Office

20070298621 - Baking method of quartz products, computer program and storage medium: The present invention relates to control of copper contamination to semiconductor substrates upon operation of a heat treatment apparatus which is a semiconductor manufacturing apparatus and which is constructed with quartz products having been contaminated with copper when machined. The quartz product is placed in a heating atmosphere on the... Agent: Smith, Gambrell & Russell

20070298622 - Producing method of semiconductor device: Disclosed is a producing method of a semiconductor device comprising a step of forming a tunnel insulating film of a flash device comprising a first nitridation step of forming a first silicon oxynitride film by nitriding a silicon oxide film formed on a semiconductor silicon base by one of plasma... Agent: Birch Stewart Kolasch & Birch

20070298623 - Method for straining a semiconductor device: A strained semiconductor layer is achieved by an overlying stressed dielectric layer. The stress in the dielectric layer is increased by a radiation anneal. The radiation anneal can be either by scanning using a laser beam or a flash tool that provides the anneal to the whole dielectric layer simultaneously.... Agent: Freescale Semiconductor, Inc. Law Department

20070292977 - Method for monitoring temperature in thermal process: A method for monitoring a temperature in a thermal process is described. A monitor substrate is provided and subject to ion implantation, and a characteristic parameter of the monitor substrate correlated to the disorder degree of the lattice structure of the same is measured to obtain a first value. The... Agent: Jianq Chyun Intellectual Property Office

20070292978 - Method for manufacturing gallium nitride light emitting diode devices: A method for manufacturing GaN LED devices is disclosed herein. First, a LED epitaxial layer is formed on a provisional substrate. Part of the LED epitaxial layer is removed to form a plurality of LED epitaxial areas. Then, a first transparent conductive layer, a metal reflective layer, and a first... Agent: Rosenberg, Klein & Lee

20070292981 - Structure for protecting feataures during the removal of sacrificial materials and a method of manufacture therefor: The present invention provides a process and an apparatus. The process, in one embodiment, includes providing a micro-electro-mechanical system (MEMS) device, the micro-electro-mechanical system (MEMS) device including an actuator coupled to a movable feature, sacrificial material fixing the actuator and movable feature with respect to one another, and a layer... Agent: Hitt Gaines, PC Alcatel-lucent

20070292982 - Method for manufacturing transparent windows in molded semiconductor packages: Methods for packaging light-sensitive semiconductor devices in packages are described in which a transparent window aligned with light-sensitive surfaces of the devices are provided. The methods of the invention include steps for affixing a transparent body to a light-sensitive surface of the semiconductor device, affixing the device to a leadframe,... Agent: Texas Instruments Incorporated

20070292985 - Phase change memory with nanofiber heater: Phase change memories may be formed with nanofiber bottom electrodes or heaters. Because of the use of the relatively well controlled, small diameter nanofibers, better current density, and lower current utilization may be achieved, in some cases, because less phase change material may need to change phase. In some embodiments,... Agent: Trop Pruner & Hu, PC

20070292986 - Method for manufacturing semiconductor device: An object is to provide a semiconductor device with excellent reproducibility which is manufactured at low cost. A method for manufacturing a semiconductor device includes steps of forming a first electrode over a substrate; forming an insulating layer over the substrate and the first electrode; pressing a mold against the... Agent: Nixon Peabody, LLP

20070292973 - Mram layer having domain wall traps: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells... Agent: Knobbe Martens Olson & Bear LLP

20070292974 - Substrate processing method and substrate processing apparatus: Disclosed is a substrate processing method in which a plurality of processing gases are alternately supplied to and exhausted from a processing chamber forming a space in which a substrate or substrates are to be processed to form a desired thin film on the substrate or each of the substrates... Agent: Birch Stewart Kolasch & Birch

20070292975 - Transfer molding apparatus and method for manufacturing semiconductor device: A transfer molding apparatus, wherein said top-half mold and said bottom-half mold form a plurality of cavities interconnected, and wherein said pressure adjusting means reduces the pressure of the cavities every time a specified amount of resin is supplied into any one of a plurality of cavities.... Agent: Volentine & Whitt PLLC

20070292976 - Method and device for the independent extraction of carrier concentration level and electrical junction depth in a semiconductor substrate: The present invention provides a method and device for determining, in a non-destructive way, carrier concentration level and junction depth in a semiconductor substrate, independent from each other, during a single measurement.... Agent: Knobbe Martens Olson & Bear LLP

20070292979 - Semiconductor device and method of fabricating the same: A semiconductor device capable of stabilizing operations thereof is provided. This semiconductor device comprises a substrate provided with a region having concentrated dislocations at least on part of the back surface thereof, a semiconductor element layer formed on the front surface of the substrate, an insulator film formed on the... Agent: Mcdermott Will & Emery LLP

20070292980 - Method for producing nitride semiconductor laser light source and apparatus for producing nitride semiconductor laser light source: A method for producing a nitride semiconductor laser light source is provided. The nitride semiconductor laser light source has a nitride semiconductor laser chip, a stem for mounting the laser chip thereon, and a cap for covering the laser chip. The laser chip is encapsulated in a sealed container composed... Agent: Harness, Dickey & Pierce, P.L.C

20070292983 - Methods for manufacturing a sensor assembly: A method for connecting substrates having electrical conductive elements thereon, comprising: providing at least one spacer between the substrates; applying a conductive material to at least one of the electrical conductive elements; aligning the electrical conductive elements; and, connecting the substrates by urging them together, wherein the at least one... Agent: Martin D Moynihan Prtsi, Inc.

20070292984 - Solid-state imaging device and method for fabricating same: A solid-state imaging device includes a plurality of pixels two-dimensionally arrayed in a well region disposed on a semiconductor substrate, each pixel including a photoelectric conversion section having a charge accumulation region which accumulates signal charge; an element isolation layer which is disposed on the surface of the well region... Agent: Robert J. Depke Lewis T. Steadman

20070292987 - Method of fabricating strained thin film semiconductor layer: A method of fabricating a strained thin film semiconductor layer having less dislocation and less defects than conventional methods, or no dislocation and no defects by controlling a stress distribution in a semiconductor substrate is provided. The method includes forming a trench in a semiconductor substrate, and epitaxially growing a... Agent: Ladas & Parry LLP

20070292988 - Manufacturing method of wiring substrate: A bonding pad and flip chip pads in which the surfaces are formed by different metals are juxtaposed on a substrate. The substrate is immersion-treated with a first adhesive treatment liquid which contains an adhesive giving compound for reacting with only a metal surface and giving adhesion properties and is... Agent: Rankin, Hill, Porter & Clark LLP

20070292989 - Semiconductor device and a method of assembling a semiconductor device: A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070292990 - Semiconductor multi-package module having wire bond interconnect between stacked packages: A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate... Agent: Ishimaru & Zahrt LLP

20070292991 - Method for quantification of analytes in a titanium, tin or silcon tetrachloride sample: s

20070292992 - Method of aligning a contactless semiconductor device interface: Contactless interconnects between an integrated circuit die and an electrical structure are aligned by charging alignment pads on the integrated circuit die to a first voltage, and charging counterpart alignment pads on the electrical structure to a second voltage. The integrated circuit die is disposed in an initial position relative... Agent: Shemwell Gregory & Courtney LLP

20070292993 - Manufacturing method of semiconductor device: Package substrate 3 by which ring shape common wiring 3p for electric supply was formed in the inner area of bonding lead 3j in device region 3v of main surface 3a is used. Since a plurality of first plating lines 3r and fourth plating lines 3u for electric supply connected... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070292994 - Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein: A lead frame comprises a stage for mounting a semiconductor chip thereon, a plurality of leads arranged in the periphery of the stage, and a plurality of lead interconnection members (e.g., dam bars) for interconnecting the leads, wherein a plurality of through holes are formed to penetrate through the lead... Agent: Dickstein Shapiro LLP

20070292995 - Reverse blocking semiconductor device and a method for manufacturing the same: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state... Agent: Rossi, Kimms & Mcdowell LLP.

20070292996 - Method and structure to process thick and thin fins and variable fin to fin spacing: Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070292997 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a... Agent: Eric Robinson

20070292998 - Thin film transistor array substrate and method for manufacturing the same: A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost... Agent: Jianq Chyun Intellectual Property Office

20070292999 - Transistors having implanted channel layers and methods of fabricating the same: A MESFET includes a silicon carbide layer, spaced apart source and drain regions in the silicon carbide layer, a channel region positioned within the silicon carbide layer between the source and drain regions and doped with implanted dopants, and a gate contact on the silicon carbide layer. Methods of forming... Agent: Myers Bigel Sibley & Sajovec

20070293000 - Metal resistor, resistor material and method: A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W),... Agent: Hoffman, Warnick & D'alessandro LLC

20070293001 - Silicon carbide schottky diode and method of making the same: A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n− silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried... Agent: Birch Stewart Kolasch & Birch

20070293002 - Method of fabricating a high-voltage transistor with an extended drain structure: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls partially filling each of the trenches with a dielectric material that covers the... Agent: The Law Offices Of Bradley J. Bereznak

20070293003 - Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there... Agent: Goodwin Procter LLP Patent Administrator

20070293004 - Integrated cmos and bipolar devices method and structure: A method is provided for forming bipolar (103) and MOS (105) semiconductor devices in a common substrate (46), comprising, forming a combination comprising an MOS device (105) in a first region (44) of the substrate (46) and a portion (50) of a collector region (82, 64, 62, 50) of the... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070293005 - Parts combining structure, and electronic apparatus: A parts combining structure is provided with first part having thermoplastic projection, and a second part having through portion to insert the projection. By thermally crushing the distal end of the projection projecting from the through portion, the first part and second part are combined. The through portion of the... Agent: Blakely Sokoloff Taylor & Zafman

20070293006 - Method for fabricating a charg trapping memory device: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070293007 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the... Agent: Mcdermott Will & Emery LLP

20070293008 - Trench drain with sloping rails: A modular trench drain system with sloping overlay rails. A non-sloping section of trench drain is transformed into a sloping trench drain by installing sloping overlay rails. The overlay rails rest on the top of the upper edge of the sidewalls and may have a ledge which allows grating, which... Agent: Christie, Parker & Hale, LLP

20070293009 - Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there... Agent: Goodwin Procter LLP Patent Administrator

20070293010 - Buried biasing wells in fets (field effect transistors): A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region... Agent: Schmeiser, Olsen & Watts

20070293011 - Field effect transistor device with channel fin structure and method of fabricating the same: A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess... Agent: Marger Johnson & Mccollom, P.C.

20070293012 - Reduction of slip and plastic deformations during annealing by the use of ultra-fast thermal spikes: Exemplary embodiments provide methods for reducing and/or removing slip and plastic deformations in semiconductor materials by use of one or more ultra-fast thermal spike anneals. The ultra-fast thermal spike anneal can be an ultra-high temperature (UHT) anneal having an ultra-short annealing time. During the ultra-fast thermal spike anneal, an increased... Agent: Texas Instruments Incorporated

20070293013 - Method of forming a bipolar transistor and semiconductor component thereof: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the... Agent: Walter P. Opaska Bryan Cave LLP

20070293014 - Method for forming metal-insulator-metal capacitor of semiconductor device: A method for forming a Metal-Insulator-Metal capacitor of a semiconductor device includes forming an insulation layer, a lower conductive layer, a dielectric layer and an upper conductive layer on a semiconductor substrate; forming, on the upper conductive layer, a protective insulation layer wherein an etching selectivity of the lower conductive... Agent: Lowe Hauptman Ham & Berner, LLP

20070293015 - Iii-nitride device and method with variable epitaxial growth direction: A semiconductor device composed of III-nitride materials is produced with epitaxial growth that permits vertical and lateral growth geometries to improve device characteristics. The resulting device has a greater breakdown voltage due to the greater integrity of the semiconductor material structure since no ion implantation processes are used. The epitaxially... Agent: Ostrolenk Faber Gerb & Soffen

20070293017 - Method of fabricating shallow trench isolation structure: A method of fabricating a shallow trench isolation structure is provided. A substrate is provided with a pad layer, a mask layer and a shallow trench formed therein. A liner oxide layer is formed on the sidewall of the shallow trench and then a silicon nitride layer is formed conformably... Agent: J.c. Patents, Inc.

20070293016 - Semiconductor structure including isolation region with variable linewidth and method for fabrication therof: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within... Agent: Scully, Scott, Murphy & Presser, P.C.

20070293018 - Method of fabricating semiconductor device with shallow trench isolation: In fabrication of a semiconductor device, a first insulating film, electrode film and silicon nitride film sequentially stacked on a semiconductor substrate are etched with the substrate so that a trench is formed. The electrode film is then exposed. A second insulating film buried in the trench is isotropically etched... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070293019 - Methods of die sawing and structures formed thereby: A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one... Agent: Duane Morris LLPIPDepartment (tsmc)

20070293020 - Singulating semiconductor wafers to form semiconductor chips: One aspect relates to a method for singulating semiconductor wafers to form semiconductor chips. A semiconductor wafer is provided with semiconductor chip positions arranged in rows and columns, rectilinear separating tracks being arranged between the positions. Crystallographic strains are induced into the region of the separating tracks. This is followed... Agent: Dicke, Billig & Czaja

20070293021 - Wafer dividing method: A method of dividing a wafer having a plurality of areas defined by the plurality of streets formed in a lattice on the front surface, devices formed in the defined areas and an adhesive film for die bonding on the rear surface and put on a dicing tape affixed to... Agent: Smith, Gambrell & Russell

20070293022 - Method of and apparatus for detaching semiconductor chips from a tape: An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first... Agent: Volentine & Whitt PLLC

20070293023 - Method of fabricating suspended structure: A method of fabricating a suspended structure. First, a substrate including a photoresist layer hardened by heat is provided. Subsequently, the hardened photoresist layer is etched so as to turn the photoresist layer into a predetermined edge profile. Thereafter, a structure layer is formed on parts of the substrate and... Agent: North America Intellectual Property Corporation

20070293024 - Method of crystallizing amorphous silicon and device fabricated using the same: A method of crystallizing amorphous silicon includes forming an amorphous silicon film over a substrate, crystallizing the amorphous silicon film to form a polycrystalline silicon film using a sequential lateral solidification crystallization method, and performing a surface treatment to the polycrystalline silicon film, wherein the sequential lateral solidification crystallization method... Agent: Mckenna Long & Aldridge LLP

20070293025 - Protect diodes for hybrid-orientation substrate structures: A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from... Agent: Schmeiser, Olsen & Watts

20070293026 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes the step of performing an ion implantation process for implanting an impurity ion into a semiconductor substrate, and performing annealing in a state where temperature of respective portions of an annealing chamber are set differently in order to activate the impurity ion.... Agent: Townsend And Townsend And Crew, LLP

20070293027 - Dopant diffusion method and method of manufacturing semiconductor device: A dopant diffusion method includes: diffusing a dopant element into a semiconductor through an oxide film. The dopant element is contained in a compound gas having a gas partial pressure of not less than 0.1 torr and not more than 800 torr. A temperature of the semiconductor is set less... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070293028 - Method of forming low forward voltage shottky barrier diode with locos structure therein: A method of forming a power Schottky rectifier device is disclosed. The Schottky rectifier device including LOCOS structure and two p doped layers formed thereunder to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n− drift layer formed on an n+ substrate; a cathode metal layer formed... Agent: Birch Stewart Kolasch & Birch

20070293029 - Method for fabricating semiconductor device: The method for fabricating the semiconductor device includes the steps of: forming an insulating film 20, a conductive film 22 and an insulating film 24 over a semiconductor substrate 10 having a first to a third region; removing an insulating film 24, the conductive film 22 and an insulating film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070293030 - Semiconductor device having silicide thin film and method of forming the same: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed... Agent: Marger Johnson & Mccollom, P.C.

20070293031 - Split poly-sige/poly-si alloy gate stack: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of... Agent: John A. Jordan, Esq.

20070293032 - Semiconductor manufacturing apparatus and semiconductor device manufacturing method: A semiconductor manufacturing apparatus includes a controller, a wafer stage and an optical unit. The wafer stage is configured to move a semiconductor wafer. The optical unit is configured to expose a first resist film in each of shots of the semiconductor wafer by using a first mask pattern and... Agent: Mcginn Intellectual Property Law Group, PLLC

20070293033 - Microelectronic assembly with back side metallization and method for forming the same: A method is provided for forming a microelectronic assembly. A contact structure (46) is formed over a first side of a first substrate (20) having a microelectronic device formed over a second side thereof. The contact structure is electrically connected to the microelectronic device. A non-solderable layer (52) is formed... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070293034 - Unlanded via process without plasma damage: A semiconductor device with an unlanded via having an air gap dielectric layer and a silicon-rich oxide (SRO) inter-metal dielectric (IMD) layer, and a method of making the same are provided. The SRO layer acts as an etch-stop layer to prevent unlanded via penetration completely through the IMD layer. In... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070293035 - Interlayer insulating layer and method of manufacturing the same: When an insulating layer is patterned by etching, end surfaces of the insulating layer are perpendicularly formed. By doing so, for example, the diameter of a coil of a magnetic head can be reduced and in turn the magnetic head can be miniaturized. A method of manufacturing an interlayer insulating... Agent: Greer, Burns & Crain

20070293036 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070293037 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Room 301/302

20070293038 - Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate: The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A... Agent: Robert J. Depke Lewis T. Steadman

20070293039 - Combined copper plating method to improve gap fill: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like... Agent: HorizonIPPte Ltd

20070293040 - Filling deep features with conductors in semiconductor manufacturing: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor... Agent: Knobbe, Martens, Olsen & Bear LLP

20070293041 - Sub-lithographic feature patterning using self-aligned self-assembly polymers: A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling... Agent: Scully Scott Murphy & Presser, PC

20070293042 - Semiconductor die with protective layer and related method of processing a semiconductor wafer: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.... Agent: Volentine & Whitt PLLC

20070293045 - Semiconductor device and method for fabricating the same: A semiconductor device may include a semiconductor substrate having a trench, a device isolation layer filling the trench, and a liner nitride layer disposed between the semiconductor substrate and the device isolation layer. The device isolation layer may additionally cover a portion of the substrate surrounding the trench. The liner... Agent: Harness, Dickey & Pierce, P.L.C

20070293043 - Edge gas injection for critical dimension uniformity improvement: A method of etching a semiconductor substrate with improved critical dimension uniformity comprises supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber; supplying a first etch gas to a central region over the semiconductor substrate; supplying a second gas comprising at least one silicon... Agent: Buchanan, Ingersoll & Rooney PC

20070293044 - Patterning 3d features in a substrate: Methods of forming a 3D structure in a substrate are disclosed. A layer of resist is deposited on the substrate. The layer of resist is patterned to define an edge at a predetermined location. The resist is reflowed to form a tapered region extending from the etch. Both the reflowed... Agent: Townsend And Townsend And Crew LLP / Amat

20070293046 - Method for forming metal wiring of semiconductor device and a semiconductor device manufactured by the same: A method for forming a metal wiring of a semiconductor device, includes forming a first metal layer on a wafer, partially etching a portion of the first metal layer where a metal wiring is to be formed, sequentially forming a first copper barrier layer, a copper seed layer, and a... Agent: Lowe Hauptman Ham & Berner, LLP

20070293048 - Polishing slurry: A polishing slurry, including an oxidizer, a corrosion inhibitor, and a polishing rate enhancer, wherein the polishing rate enhancer is a heterocyclic compound having at least one nitrogen in the ring, and the nitrogen is not directly bonded to a hydrogen atom which is mostly dissociated in the slurry.... Agent: Lee & Morse, P.C.

20070293047 - Polishing method and method for fabricating semiconductor device: A polishing method includes causing a polishing pad arranged on a turn table to rotate together with the turn table, and polishing a surface of a substrate by using the rotating polishing pad while supplying a chemical fluid to a surface of the polishing pad on a fore side of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070293049 - Slurry for cmp of cu film, polishing method and method for manufacturing semiconductor device: A slurry for CMP of Cu film is provided, which includes water, peroxosulfuric acid or a salt thereof, basic amino acid, a complexing agent which forms a water-insoluble metal complex, a surfactant, and colloidal silica having a primary diameter ranging from 5 to 50 nm. The basic amino acid is... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070293050 - Reduction of feature critical dimensions: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce... Agent: Beyer Weaver LLP

20070293051 - Method for manufacturing a semiconductor device including a silicon film: A method for manufacturing a semiconductor device includes: mounting a wafer having an exposed silicon nitride film, on an electrode received in a plasma chamber; dry-cleaning the chamber to remove reaction products accumulated on the wall and ceiling of the chamber, anisotropic-etching the silicon nitride film and an underlying silicon... Agent: Young & Thompson

20070293052 - Apparatus and method for optical interference fringe based integrated circuit processing: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam... Agent: Sughrue Mion, PLLC

20070293053 - Method for manufacturing probe structure of probe card: A method for manufacturing a probe structure of a probe card is disclosed. In accordance with the method of the present invention, a dual etching process of a silicon substrate or an etching process of an SOI substrates is carried out using a sidewall insulating film pattern as an etching... Agent: Sughrue Mion, PLLC

20070293054 - Etching, cleaning and drying methods using supercritical fluid and chamber systems using these methods: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between... Agent: Myers Bigel Sibley & Sajovec

20070293055 - Method for self-limiting deposition of one or more monolayers: The invention relates to a method for deposition of at least one layer containing at least one first component on at least one substrate in a process chamber, wherein first and second starting materials are introduced in gaseous form into the process chamber in alternation cyclically, at least the first... Agent: Sonnenschein Nath & Rosenthal LLP

20070293057 - Method of direct coulomb explosion in laser ablation of semiconductor structures: A new technique and Method of Direct Coulomb Explosion in Laser Ablation of Semiconductor Structures in semiconductor materials is disclosed. The Method of Direct Coulomb Explosion in Laser Ablation of Semiconductor Structures provides activation of the “Coulomb explosion” mechanism in a manner which does not invoke or require the conventional... Agent: William Chism

20070293058 - Method of laser annealing using two wavelengths of radiation: A thermal processing apparatus and method in which a first laser source, for example, a CO2 emitting at 10.6 μm is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20070293056 - Surface modification method for solid sample, impurity activation method, and method for manufacturing semiconductor device: The present invention intends to provide a method for manufacturing a semiconductor device in which source/drain extension regions having a uniform depth are created with high reproducibility. This objective is achieved by the following method: A gate electrode 24 is formed on a semiconductor substrate 21 via a gate insulator... Agent: Oliff & Berridge, PLC

20070287199 - Base oxide engineering for high-k gate stacks: A method of forming a semiconductor structure includes providing a semiconductor substrate, performing a hydrogen annealing to the semiconductor substrate, forming a base oxide layer after the step of hydrogen annealing, and forming a high-k dielectric layer on the base oxide layer.... Agent: Slater & Matsil, L.L.P.

20070287200 - Variable overlap of dummy shapes for improved rapid thermal anneal uniformity: Embodiments of the invention provide a method, structure, service, etc. for variable overlap of dummy shapes for improved rapid thermal anneal uniformity. A method of providing uniform temperatures across a limited region of a wafer during a rapid thermal anneal process comprises determining a first reflectivity in a first portion... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070287204 - A method for locating a sub-surface feature using a scatterometer: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a substrate having a sub-surface feature and a surface feature, and determining a location of the sub-surface feature relative to the surface feature using a scatterometer.... Agent: Texas Instruments Incorporated

20070287207 - Method for manufacturing semiconductor device: An object is to provide a semiconductor device with excellent reproducibility which is manufactured at low cost. A manufacturing method of a semiconductor device includes steps of forming a first electrode over a substrate; forming an insulating layer over the substrate and the first electrode; pressing a mold against the... Agent: Nixon Peabody, LLP

20070287209 - Method for manufacturing light-emitting device: To obtain a long-life light-emitting device. The invention relates to a manufacturing method of a light-emitting device, including forming a first electrode over a substrate, forming a partition wall using a resin material over the substrate and the first electrode, holding the partition wall for a first time period by... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070287208 - Method of making light emitting device with multilayer silicon-containing encapsulant: A method of making an LED light emitting device is disclosed. The method includes forming a multilayer encapsulant in contact with an LED by contacting the LED with a first encapsulant that is a silicone gel, silicone gum, silicone fluid, organosiloxane, polysiloxane, polyimide, polyphosphazene, sol-gel composition, or a first photopolymerizable... Agent: 3m Innovative Properties Company

20070287211 - Method of improving the flatness of a microdisplay surface, liquid crystal on silicon (lcos) display panel and method of manufacturing the same: A method of improving the flatness of a microdisplay surface. A reflective mirror layer and a raised layer are formed in order on a semiconductor substrate. The raised layer may comprise a buffer layer and a stop layer, and pixel electrode areas are defined therefrom and gaps are consequently formed... Agent: North America Intellectual Property Corporation

20070287213 - Methods of fabricating a micromechanical structure: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070287215 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on... Agent: Mcdermott Will & Emery LLP

20070287217 - Production of an improved color filter on a microelectronic imaging device comprising a cavity: A microelectronic device includes a color filter equipped with a plurality of filtering elements, including several filtering elements. The device includes at least one first zone located inside a cavity and includes a first group of filtering elements having a first critical dimension, and at least one second zone at... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070287218 - Digital filter: A method is for filtering data output from an array of pixels in an image sensor. The method may include filtering noise from variation in pixel response across the array. An electronic device may have a device for filtering data output from an array of pixels in an image sensor.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070287220 - Organic semiconductor materials using stacking-inducing compounds, compositions comprising such materials, organic semiconductor thin films formed using such compositions, and organic electronic devices incorporating such thin films: Disclosed are organic semiconductor materials, including mixtures of relatively low molecular weight aromatic ring compounds, in which at least one nitrogen atom or oxygen atom is present as a heteroatom in the aromatic ring compounds for forming hydrogen bonds between the heteroatom(s) and adjacent molecules and thereby increase intermolecular stacking.... Agent: Harness, Dickey & Pierce, P.L.C

20070287202 - Method for producing nano-scale low-dimensional quantum structure, and method for producing integrated circuit using the method for producing the structure: A method of an embodiment of the present of the present application is for producing a nano-scale low dimensional quantum structure. The method includes: bringing a catalyst on a substrate into contact with vaporized carbon source, and emitting an electromagnetic wave to the catalyst so as to form single-walled carbon... Agent: Harness, Dickey & Pierce, P.L.C

20070287201 - Power supply regulating apparatus, semiconductor manufacturing apparatus, method for controlling power to heater, and method for manufacturing semiconductor device: A supplying power adjusting apparatus has excellent temperature response and excellent stabilities to power supply change and load change. The apparatus is provided with a semiconductor inverter for high-speed switching power control, which converts a direct current rectified by a rectifying circuit (10) into alternating current power in response to... Agent: Oliff & Berridge, PLC

20070287203 - Method and system of beam energy control: A method and system of automatic beam energy control. First, a substrate is provided. Next, hydrogen content of the substrate is measured to determine whether hydrogen content exceeds a critical hydrogen content limit. A warning is issued when hydrogen content exceeds a critical hydrogen content limit. Substrate thickness is measured... Agent: Alessandro Steinfl C/o Ladas & Parry LLP

20070287205 - Method of measuring minority carrier diffusion length and method of manufacturing silicon wafer: A method of measuring a diffusion length of a minority carrier in a silicon wafer by a surface photovoltage method including irradiating the surface-treated silicon wafer with ultraviolet radiation in an oxygen-containing atmosphere, and measuring a diffusion length of a minority carrier in a silicon wafer by a surface photovoltage... Agent: Greenblum & Bernstein, P.L.C

20070287206 - Method for manufactuing a semiconductor integrated circuit device: A burn-in process for a semiconductor integrated circuit device includes a first process of positioning bump electrodes of the semiconductor integrated circuit device with respect to pads of a socket having detachment mechanisms, a second process of pressing the bump electrodes against the pads by weighting the semiconductor integrated circuit... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070287210 - Method for assembling a semiconductor laser module: A method and an apparatus for assembling a semiconductor laser module to prevent excess solder from scattering without saving an amount of the solder is disclosed. The method has a feature that, after heating up the die-bonder and holding the temperature of the die-bonder in a preset period, the excess... Agent: Smith, Gambrell & Russell

20070287212 - Planar waveguide with patterned cladding and method for producing same: Methods for the production of integrated optical waveguides which have a patterned upper cladding with a defined opening to allow at least one side or at least one end of a light transmissive element to be air clad The at least one side or at least one end is, for... Agent: Miller, Matthias & Hull

20070287214 - Method of fabricating reflective spatial light modulator having high contrast ratio: The contrast offered by a spatial light modulator device may be enhanced by positioning nonreflective elements such as supporting posts and moveable hinges, behind the reflecting surface of the pixel. In accordance with one embodiment, the reflecting surface is suspended over and underlying hinge-containing layer by integral ribs of the... Agent: Townsend And Townsend And Crew, LLP

20070287216 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the... Agent: Dickstein Shapiro LLP

20070287219 - Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.... Agent: Dickstein Shapiro LLP

20070287221 - Fabrication process for crystalline zinc oxide semiconductor layer: A process for fabricating at least one semiconductor layer of a thin film transistor composed of: liquid depositing one or more zinc oxide-precursor compositions and forming the at least one semiconductor layer of the thin film transistor including crystalline zinc oxide preferentially oriented with the c-axis perpendicular to the plane... Agent: Patent Documentation Center

20070287222 - Method of fixing curved circuit board and wire bonding apparatus: A method of holding a curved circuit board in a flat fashion and a wire bonding apparatus thereof, including suction cavities provided in a suction stage to which a curved circuit board is suctioned. While evacuating air from the vacuum suction cavities, a capillary attached to the tip end of... Agent: Quinn Emanuel Koda & Androlia

20070287223 - Light emitting diode and method for improving luminescence efficiency of light emitting diode: A light emitting diode comprising a semiconductor layer, a first electrode, a second electrode and a diamond-like carbon layer is provided. The semiconductor layer includes a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer. Wherein, the light emitting layer locates between the... Agent: Jianq Chyun Intellectual Property Office

20070287224 - Three dimensional integrated circuit and method of design: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20070287226 - Manufacturing apparatus of semiconductor device and manufacturing method of semiconductor device: The manufacturing apparatus of the semiconductor device concerning the present invention has a stage where a substrate is arranged, a movable member formed made it possible to advance or retreat towards the stage, an elastic member formed in the movable member, a chip adsorption means which can adsorb the chip... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070287225 - Method of manufacturing an integrated circuit: A method of manufacturing an integrated circuit including a first isolated chip electrically and mechanically connected via wafer bonding to a second isolated chip, wherein the active faces of the chips face one another, includes: forming metallic contact zones on active faces of first and second wafers, positioning and fixing... Agent: Edell, Shapiro & Finnan, LLC

20070287227 - Stacked chips with underpinning: Methods for assembling multi-chip semiconductor packages, and the resulting assemblies themselves, are disclosed. According to the preferred embodiments of the invention, a first semiconductor chip is affixed to a package substrate and a second semiconductor chip is affixed to at least a portion of a surface of the first semiconductor... Agent: Texas Instruments Incorporated

20070287228 - Semiconductor package and method of assembling the same: An encapsulated semiconductor package includes a substrate including a chip mounting area and inner contact pads on its upper surface and at least two semiconductor chips, each having an active surface with a plurality of chip contact pads and a passive surface. A first semiconductor chip is mounted on the... Agent: Edell, Shapiro & Finnan, LLC

20070287230 - Electronic device and production method thereof: An object is to provide an electronic device of a multilayer structure with high density and high reliability that can be reduced in size while incorporating an electronic component therein, and further provide a production method for easily producing such an electronic device. An electronic device of the present invention... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070287229 - Integrated circuit device with electronically accessible device identifier: An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwise continuous signal path that extends... Agent: Shemwell Mahamedi LLP

20070287231 - Method of forming decoupled comb electrodes by self-alignment etching: A method of etching decoupled comb electrodes by self-alignment is provided The etching method is a self-alignment etching method for forming upper comb electrodes in a first silicon layer of a silicon on insulator (SOI) substrate and lower comb electrodes in a second silicon layer of the SOI substrate. The... Agent: Sughrue Mion, PLLC

20070287232 - Bottom gate thin film transistor and method of manufacturing the same: A method of manufacturing a bottom gate thin film transistor (“TFT”), in which a polycrystalline channel region having a large grain size is formed relatively simply and easily, includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the gate electrode,... Agent: Cantor Colburn, LLP

20070287233 - Piezo-tft cantilever mems fabrication: A piezo-TFT cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method comprises: providing a substrate, such as glass for example; forming thin-films overlying the substrate; forming a thin-film cantilever beam; and simultaneously forming a TFT within the cantilever beam. The TFT is can be formed least partially... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070287234 - Bipolar transistor, bicmos device, and method for fabricating thereof: Provided are bipolar transistor, BiCMOS device and method of fabricating thereof, in which an existing sub-collector disposed beneath a collector of a SiGe HBT is removed and a collector plug disposed at a lateral side of the collector is approached to a base when fabricating a Si-based very high-speed device,... Agent: Lowe Hauptman Ham & Berner, LLP

20070287236 - In film transistor, method of manufacturing the same, and organic light-emitting diode display using the same: A thin film transistor, a method for manufacturing the thin film transistor, and an organic electroluminescence display using the thin film transistor are disclosed. The thin film transistor includes a gate electrode, a semiconductor layer that overlaps the gate electrode, a first insulating layer disposed between the semiconductor layer and... Agent: Brinks Hofer Gilson & Lione

20070287235 - Method of manufacturing an array substrate of a transflective liquid crystal display: A method of manufacturing an array substrate of a transflective liquid crystal display is provided. Utilizing backward exposure and half-tone photo-mask to reduce the number of photo-masks used in the manufacturing process, only three to four photo-masks are used to manufacture a transflective liquid crystal display.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070287237 - Printed, self-aligned, top gate thin film transistor: A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070287238 - Si nanowire substrate, method of manufacturing the same, and method of manufacturing thin film transistor using the same: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing... Agent: Harness, Dickey & Pierce, P.L.C

20070287239 - Intentional pocket shadowing to compensate for the effects of cross-diffusion in srams: Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species... Agent: Texas Instruments Incorporated

20070287240 - Advanced forming method and structure of local mechanical strained transistor: Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have... Agent: Slater & Matsil, L.L.P.

20070287241 - Fabrication method of semiconductor integrated circuit device: Provided is a fabrication method of a semiconductor integrated circuit device, which comprises disposing, in a ultrapure water preparing system, UF equipment having therein a UF module which has been manufactured by disposing, in a body thereof, a plurality of capillary hollow fiber membranes composed of a polysulfone membrane or... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070287242 - Thin film device supply body, method of fabricating thin film device, method of transfer, method of fabricating semiconductor device, and electronic equipment: A technique is described in which a layer to be transferred is easily peeled and transferred to a transferred body that is pliable or flexible. Also, a method of fabricating a semiconductor device using these peeling and transfer techniques, and electronic equipment fabricated with the semiconductor device is described. A... Agent: Oliff & Berridge, PLC

20070287243 - Semiconductor devices: A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises... Agent: Greenblum & Bernstein, P.L.C

20070287244 - Alternative integration scheme for cmos s/d sige process: A method for fabricating a semiconductor device with adjacent PMOS and NMOS devices on a substrate includes forming a PMOS gate electrode with a PMOS hardmask on a semiconductor substrate with a PMOS gate dielectric layer in between, forming an NMOS gate electrode with an NMOS hardmask on a semiconductor... Agent: Townsend And Townsend And Crew LLP / Amat

20070287245 - Semiconductor device and method of manufacture thereof: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070287246 - Method for making split dual gate field effect transistor: A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming... Agent: Townsend And Townsend And Crew, LLP

20070287247 - Embedded capacitor in semiconductor device and method for fabricating the same: A semiconductor device with an embedded capacitor structure. A dielectric layer is disposed on a substrate, having a contact opening exposing the substrate and a trench opening above the contact opening. A first metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings.... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20070287248 - Method for manufacturing capacity element, method for manufacturing semiconductor device and semiconductor-manufacturing apparatus: A method of manufacturing a capacity element, including the steps of (a) forming an insulating film on a substrate to be processed, (b) forming a lower electrode layer on the insulating film, (c) feeding a vaporized organic solvent onto the lower electrode layer under a condition wherein an oxidizing gas... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070287249 - Method for manufacturing dielectric memory: A method includes the steps of: forming a first insulation film on a substrate; forming a hole in the first insulation film; forming a lower electrode on a bottom surface and a sidewall surface of the hole; forming a capacitor insulation film on the lower electrode; forming a second conductive... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070287250 - Method for fabricating a semiconductor device having an insulation film with reduced water content: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070287251 - Method for forming a memory device with at least one memory cell, in particular a phase change memory cell, and memory device: A method for forming a memory device with at least one memory cell, the memory cell including a volume of switching active material is disclosed. The method includes the process of depositing a first layer of insulating material on a substrate, depositing a layer of switching active material on the... Agent: Dicke, Billig & Czaja

20070287252 - Methods of forming variable resistance memory cells, and methods of etching germanium, antimony, and tellurium-comprising materials: A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching chemistry comprising Cl2 and CH2F2. A method of forming a variable resistance memory cell includes forming a conductive inner electrode material over a substrate. A variable resistance chalcogenide material... Agent: Wells St. John P.s.

20070287253 - Semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070287254 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070287255 - Protection of three dimensional transistor structures during gate stack etch: Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.... Agent: Intel Corporation C/o Intellevate, LLC

20070287256 - Contact scheme for finfet structures with multiple fins: A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack... Agent: Scully Scott Murphy & Presser, PC

20070287257 - Method for producing si1-ygey based zones with different contents in ge on a same substrate by condensation of germanium: F

20070287258 - A method of manufacturing gate sidewalls that avoids recessing: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the... Agent: Texas Instruments Incorporated

20070287259 - Forming ultra-shallow junctions: A method to form an ultra-shallow junction is described. In one embodiment, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where tip extensions reside. In another embodiment, a sacrificial spacer is utilized in conjunction with the replacement... Agent: Intel/blakely

20070287260 - Methods for forming an isolation structure in a silicon substrate: A process for forming STI regions comprises performing an In Situ Steam Generation (ISSG) radical conversion on a SiN liner layer within an STI trench in order to expose the top corner of the trench and simultaneously cause rounding the top corner of a liner oxide layer within the trench.... Agent: Baker & Mckenzie LLP Patent Department

20070287261 - Trench isolation structures for integrated circuits: A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely... Agent: Knobbe Martens Olson & Bear LLP

20070287262 - Fabrication method of semiconductor integrated circuit device: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070287263 - Highly compliant plate for wafer bonding: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer,... Agent: Intel/blakely

20070287264 - Method and equipment for wafer bonding: A method and apparatus for performing in-situ wafer surface activation, precision alignment of features on each wafer and bonding of the wafers in the same apparatus. The direct bonding part of this processes optionally includes apparatus for the controlled contacting of wafers in order to ensure single point bond initiation... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20070287265 - Substrate treating method and method of manufacturing semiconductor apparatus: The present invention provides a substrate treating method including the steps of joining a one-side surface of a substrate to be treated to a support substrate, treating the substrate to be treated in the condition where the substrate to be treated is supported by the support substrate, and removing the... Agent: Robert J. Depke Lewis T. Steadman

20070287266 - Method of cutting and machining a silicon wafer: The present invention discloses a method of cutting and machining a silicon wafer. It comprises to provide a CO2 laser apparatus, a glass or a metal-coated substrate to be put on a supporter and a silicon wafer to be fixed on the glass or the metal-coated substrate. The CO2 laser... Agent: Birch Stewart Kolasch & Birch

20070287267 - Laser processing method and object to be processed: In this laser processing method, modified regions differing from each other in terms of easiness to cause the substrate 4 to fracture are formed along respective lines to cut 5a to 5d. Therefore, when an expandable tape is attached to the rear face of a substrate 4 and expanded, an... Agent: Drinker Biddle & Reath (dc)

20070287268 - Vapor-phase growth method, semicondutor manufacturing method and semiconductor device manufacturing method: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in... Agent: Sonnenschein Nath & Rosenthal LLP

20070287270 - Device fabrication by ink-jet printing materials into bank structures, and embossing tool: The invention disclosed relates to the fabrication of electronic devices. A method for fabricating an electronic device is disclosed, comprising embossing a surface of a work-piece 200, 202 using an embossing tool 204, so as to form a microstructure having at least two levels of thickness contrast on the work-piece... Agent: Oliff & Berridge, PLC

20070287269 - Method for producing semiconductor wafer: The present invention is a method for producing a semiconductor wafer, comprising at least steps of: epitaxially growing a SiGe layer on a surface of a silicon single crystal wafer that is to be a bond wafer; implanting at least one kind of hydrogen ion and rare gas ion through... Agent: Oliff & Berridge, PLC

20070287271 - Deposition of nano-crystal silicon using a single wafer chamber: Numerous embodiments of a method for depositing a layer of nano-crystal silicon on a substrate. In one embodiment of the present invention, a substrate is placed in a single wafer chamber and heated to a temperature between about 300° C. to about 490° C. A silicon source is also fed... Agent: Intel/blakely

20070287272 - Selective epitaxial formation of semiconductor films: Epitaxial layers are selectively formed in semiconductor windows by a cyclical process of repeated blanket deposition and selective etching. The blanket deposition phases leave non-epitaxial material over insulating regions, such as field oxide, and the selective etch phases preferentially remove non-epitaxial material while deposited epitaxial material builds up cycle-by-cycle. Quality... Agent: Knobbe, Martens, Olsen & Bear LLP

20070287273 - Methods for making substrates and substrates formed therefrom: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the... Agent: Winston & Strawn LLP Patent Department

20070287274 - Implantation of carbon and/or fluorine in nmos fabrication: Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in... Agent: Texas Instruments Incorporated

20070287275 - Method for fabricating doped polysilicon lines: A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the... Agent: Schmeiser, Olsen & Watts

20070287276 - Unguarded schottky barrier diodes: One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A... Agent: Texas Instruments Incorporated

20070287277 - Semiconductor system with surface modification: A semiconductor system includes: providing a dielectric layer; providing a conductor in the dielectric layer, the conductor exposed at the top of the dielectric layer; capping the exposed conductor; and modifying the surface of the dielectric layer, modifying the surface of the dielectric layer, wherein modifying the surface includes cleaning... Agent: Ishimaru & Zahrt LLP

20070287278 - Methods of forming solder connections and structure thereof: In a first aspect, a method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment... Agent: Greenblum & Bernstein, P.L.C

20070287279 - Methods of forming solder connections and structure thereof: A method for forming solder connections using dummy vias and the device. The dummy vias are formed prior to the application of ball limiting metals or solder material. After placing the under ball materials and the solder materials, the material covering the dummy vias has an increased surface contact and... Agent: Greenblum & Bernstein, P.L.C

20070287280 - Composition for removing a photoresist and method of forming a bump electrode: A composition for removing a photoresist and a method of forming a bump electrode using the composition are provided. The composition includes an amine compound having a hydroxyl group, a polar organic solvent having a heteroatom, an alkylammonium hydroxide and water. The method of forming the bump electrode includes forming... Agent: Harness, Dickey & Pierce, P.L.C

20070287281 - Circuit carrier and manufacturing process thereof: A circuit carrier including a core layer, a passive component, a plurality of dielectric layers, and a plurality of circuit layers is provided. The core layer has a first surface and a second surface. In addition, the core layer has a hole, and the passive component is embedded in the... Agent: Jianq Chyun Intellectual Property Office

20070287282 - Semiconductor device, wiring substrate forming method, and substrate processing apparatus: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070287283 - Semiconductor device capable of suppressing current concentration in pad and its manufacture method: An interlayer insulating film is formed on a semiconductor substrate. An intra-layer insulating film is formed on the interlayer film. A recess is formed through the intra-layer film. The recess has a pad-part and a wiring-part continuous with the pad-part. The pad-part is wider than the width of the wiring-part.... Agent: Kratz, Quintos & Hanson, LLP

20070287284 - Method of processing metal surface in dual damascene manufacturing: A processing method for the metal surface in a dual damascene manufacturing is applied to a dual damascene semiconductor structure. The dual damascene semiconductor structure has a metal structure and a spin-on-dielectric (SOD) layer formed on the metal structure, wherein the SOD layer has at least one opening exposing a... Agent: Rosenberg, Klein & Lee

20070287285 - Manufacturing method of circuit board: A manufacturing method of a circuit board is provided. Firstly, a substrate board having a plurality of through holes is provided. Next, a first metal layer is electro-less plated on the surface of the substrate board and the surface of the through holes. Then, a second metal layer is plated... Agent: Birch Stewart Kolasch & Birch

20070287286 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate having a given structure, forming a hard mask pattern over the insulation layer, performing a main etch on the insulation layer with a high etch selectivity with respect to a hard mask pattern to form... Agent: Blakely Sokoloff Taylor & Zafman

20070287287 - Method of fabricating semiconductor device having contact hole with high aspect-ratio: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning... Agent: Marger Johnson & Mccollom, P.C.

20070287288 - Method of preparing metal nanocrystal: Methods of preparing capped metal nanocrystals are provided. One method includes reacting a metal nanocrystal precursor with a reducing agent in a solution having a platinum catalyst.... Agent: Christie, Parker & Hale, LLP

20070287289 - Production method of conductive pattern: [Solution] The production method of a conductive pattern in accordance with the present invention comprises the step of electroplating for forming a conductive pattern by electroplating on a metal seed layer formed on an insulated substrate using a plating bath containing an accelerator for reducing the deposition overpotential of a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070287290 - Manufacturing method for non-active electrically structures of an integrated electronic circuit formed on a semiconductor substrate and corresponding electronic circuit: Electrically non-active structures are formed for an electronic circuit to make uniform a surface above a semiconductor substrate. The electronic circuit includes first electrically active structures comprising conductive elements of a first height projecting from the semiconductor substrate, and second electrically active structures comprising conductive elements of a second height... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070287291 - Post ion implant photoresist strip using a pattern fill and method: A method is described for use in a system that removes an implant crust that is formed as an outermost layer of photoresist in a photoresist pattern that is supported by a workpiece. The photoresist pattern defines apertures which lead to an active device region. The active device region is... Agent: Pritzkau Patent Group, LLC

20070287292 - Preventing damage to low-k materials during resist stripping: A method of forming a feature in a low-k dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer. At least one feature is etched into the low-k dielectric layer. A CO conditioning is preformed on... Agent: Beyer Weaver LLP

20070287293 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes preparing a substrate comprising a first surface and a second surface formed at a lower position than the first surface, forming an insulation layer over the substrate, etching the insulation layer to form a first contact hole exposing the first surface and... Agent: Blakely Sokoloff Taylor & Zafman

20070287294 - Interconnect structures and methods for fabricating the same: Methods for fabricating interconnect structures are provided. An exemplary method for fabricating an interconnect comprises providing a substrate with a first dielectric layer thereon. At least one conductive feature is formed in the first dielectric layer. A conductive cap is selectively formed to overlie the conductive feature. A surface treatment... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070287296 - Dry etching method for oxide semiconductor film: Provided is a dry etching method for an oxide semiconductor film made of In—Ga—Zn—O, in which an etching gas containing a hydrocarbon is used in a dry etching process for the oxide semiconductor film made of In—Ga—Zn—O formed on a substrate.... Agent: Fitzpatrick Cella Harper & Scinto

20070287295 - Adaptively plasma source and method of processing semiconductor wafer using the same: An adaptive plasma source, and a method for processing a semiconductor wafer using the same are disclosed. The adaptive plasma source comprises a first planar bushing equipped at an upper center of a reaction chamber defining a reaction space for processing a semiconductor wafer so as to face a planar... Agent: Morgan & Finnegan, L.L.P.

20070287297 - Plasma etching method, plasma processing apparatus, control program and computer readable storage medium: A plasma etching method includes the step of: etching a silicon layer of a target object by using a plasma generated from a processing gas containing a fluorocarbon gas, a hydrofluorocarbon gas, a rare gas and an O2 gas and by employing a patterned resist film as a mask. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070287298 - Manufacturing method of semiconductor device: It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the deterioration in processed configuration and the pattern roughness of a film to be processed, and is close to the original design and applicable to a dual damascene step and the... Agent: Mcdermott Will & Emery LLP

20070287299 - Method of forming a semiconductor device: A method of forming a semiconductor device includes forming a first mask pattern on a target layer, the first mask pattern exposing a first portion of the target layer, forming an intermediate material layer, including depositing an intermediate material layer film on a side of the first mask pattern and... Agent: Lee & Morse, P.C.

20070287300 - Method of forming a layer of material using an atomic layer deposition process: Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative embodiment, the method includes identifying a target characteristic for the layer of material, determining a precursor pulse time for introducing a precursor... Agent: Williams, Morgan & Amerson

20070287301 - Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics: Methods of processing films on substrates are provided. In one aspect, the methods comprise treating a patterned low dielectric constant film after a photoresist is removed form the film by depositing a thin layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on the film. The thin layer provides a... Agent: Patterson & Sheridan, LLP

20070281372 - Memory element, method for manufacturing memory element, memory device, electronic apparatus and method for manufacturing transistor: A method for manufacturing a memory element including forming a first electrode on a first face of a substrate; forming a ferroelectric layer on a second face of the first electrode, the second face being on an opposite side to the substrate side, and the ferroelectric layer being mainly made... Agent: Oliff & Berridge, PLC

20070281375 - Manufacturing method of display device: A first light-transmitting substrate having a first light-transmitting electrode layer and a second substrate having at least a second electrode layer are attached to each other with a resin which is cured by UV light or the like, to form an inorganic EL light-emitting element. Thus, a display device is... Agent: Fish & Richardson P.C.

20070281376 - Manufacturing method of light emitting device: An object is, in a display device, to reduce the light quantity which is totally reflected after being transmitted through an electrode, whereby light extraction efficiency is improved. In addition, it is another object of the present invention to provide a manufacturing method of a display device with high performance,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070281377 - Deformable surface: A large, thin, variable focus lens that would be practical in a variety of applications, such as eyeglasses. An example of the present invention is a surface that can be deformed to a desirable shape in a simple, controllable fashion. In particular, a surface shape with desirable optical properties is... Agent: Black Lowe & Graham, PLLC

20070281379 - Microelectromechanical systems having stored charge and methods for fabricating and using same: Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on... Agent: Kenyon & Kenyon LLP

20070281381 - Method for sealing and backside releasing of microelectromechanical systems: Disclosed are methods for fabricating encapsulated microelectromechanical systems (MEMS) devices. A MEMS device fabricated on a CMOS wafer is encapsulated using an etch resistant thin film layer prior to the release of the MEMS device. Once CMOS processing is completed, the wafer is etched to release the MEMS device. If... Agent: Law Offices Of Kenneth W. Float

20070281383 - Method of manufacturing semiconductor multilayer structure: A method of manufacturing a semiconductor multilayer structure having an interface between a first semiconductor layer and a second semiconductor layer includes forming the first semiconductor layer by introducing at least a first raw material gas into a reactor, forming a dummy layer including at least one of the elements... Agent: Leydig Voit & Mayer, Ltd

20070281386 - Organic semiconductor device and method for manufacturing the same: An organic semiconductor device having enhanced uniformity of light-emission and excellent luminance with relatively low driving voltage and manufactured by a wet process and method for manufacturing the same are disclosed. The method for manufacturing an organic semiconductor device, comprises the steps of: forming a first electrode on a substrate;... Agent: Hyun Jong Park

20070281374 - Chip stack package and manufacturing method thereof: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test... Agent: Harness, Dickey & Pierce, P.L.C

20070281373 - Method and apparatus for determining the thickness of a dielectric layer: The method for determining a dielectric layer thickness according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070281378 - Light emitting diode and fabrication method thereof: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer... Agent: Birch Stewart Kolasch & Birch

20070281380 - Manufacturing method of an acceleration sensing device: An acceleration sensing device includes a movable sensing member, a frame member and a supporting member. The supporting member is coupled between the movable sensing member and the frame member so as to support the movable sensing member. The acceleration sensing device further includes a covering member disposed above the... Agent: Volentine & Whitt PLLC

20070281382 - Solid-state imaging device and method of manufacturing the same: A solid-state imaging device including: a semiconductor substrate on which an imaging region having a light receiving section is formed; and a predetermined layer formed on the semiconductor substrate by planarization processing using liquid containing a metal element, wherein at least a first diffusion protection film is formed between the... Agent: Sonnenschein Nath & Rosenthal LLP

20070281384 - Method of manufacturing a semiconductor device having an organic thin film transistor: An electrode substrate in which a lower electrode and an upper electrode are well positioned by way of an insulating film could not be formed by a printing method since positional displacement is caused. The cost was increased outstandingly when using photomasks for positioning. In the present invention, positional displacement... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070281385 - Process for fabricating electronic components and electronic components obtained by this process: The invention relates to a method for producing electronic components consisting in carrying out a first anodisation of a carrier material (1) for forming at least one first pore (3) extending in a first direction in said carrier material (1) and in carrying out a second anodisation for forming at... Agent: Miller, Matthias & Hull

20070281390 - Manufacturing method of a package substrate: The present invention relates to a manufacturing method of a package substrate. A manufacturing method of a package substrate for mounting an electric component by connecting electrodes of the electric component to bonding pads, includes: manufacturing a buried pattern substrate having a circuit pattern and bonding pads buried in an... Agent: Staas & Halsey LLP

20070281389 - Method for fabricating electrical conductive structure of circuit board: A method for fabricating an electrical conductive structure of a circuit board is disclosed. The method includes providing a circuit board having a plurality of first and second electrically conductive pads; forming on the circuit board an insulating protection layer having a plurality of openings for exposing the first and... Agent: Ishimaru & Zahrt LLP

20070281387 - Methods for trapping charge in a microelectromechanical system and microelectromechanical system employing same: Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on... Agent: Kenyon & Kenyon LLP

20070281388 - Selective metal surface treatment process and apparatus for circuit board and resist used in the process: A selective metal surface treatment process of a circuit board, which has a solder mask and a multiple of selective metal treatment surface areas, wherein the solder mask covers the surface of the circuit board but exposes the selective metal surface treatment areas, is provided. The selective metal surface treatment... Agent: Jianq Chyun Intellectual Property Office

20070281391 - Attachment method, attachment apparatus, manufacturing method of semiconductor device, and manufacturing apparatus of semiconductor device: The invention proposes a method and an apparatus for attaching a plurality of components having different arrangement densities or arrangement intervals, which can achieve shorter takt time. An object is to provide a low-cost manufacturing method of a semiconductor device and a manufacturing apparatus capable of manufacturing a semiconductor device... Agent: Nixon Peabody, LLP

20070281392 - Multiple row exposed leads for mlp high density packages: A leadframe strip production process provides encapsulated semiconductor chips with more than two annular rows of exposed leads by utilizing two types of frames, a leadframe to which IC devices are mounted, and a ring frame strip that is attached to the leadframe with a non-conductive adhesive. The leadframe includes... Agent: Townsend And Townsend And Crew, LLP

20070281393 - Method of forming a trace embedded package: A method of forming a semiconductor package (32) includes etching a conductive sheet (10) to form a first interconnection system (12). An integrated circuit (IC) die (22) is placed on and electrically connected to the first interconnection system (12). Next, a molding operation is performed to encapsulate the IC die... Agent: Freescale Semiconductor, Inc. Law Department

20070281394 - Method for manufacturing wiring board: A method for manufacturing a wiring board which can simplify a manufacturing step. In a preparation step, a core board and an electronic component are prepared. In an insulating layer formation and fixing step, after accommodating the electronic component in an accommodation hole, a lowermost resin insulating layer is formed,... Agent: Kusner & Jaffe Highland Place Suite 310

20070281395 - Method and system for fabricating a semiconductor device: A fabrication method of a semiconductor device is disclosed. The method includes the following steps. First, a given number of projection electrodes are formed on each of a given number of semiconductor chips, and a thermosetting insulating adhesive is applied to areas of mounting parts where the semiconductor chips are... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070281396 - Method of dissipating heat, packaging and shaping for light emitting diodes: A method of dissipating heat, packaging and shaping for light emitting diodes enhances the heat dissipation performance of light emitting diodes, and its structure includes a substrate and a light emitting diode chip. An antioxidation is performed at a high temperature at a predetermined position for installing a chip on... Agent: Hdsl

20070281397 - Method of forming semiconductor packaged device: A method of forming a semiconductor packaged device (10) including die bonding a flip chip die (12) to a first surface (14) of a lead frame (28). A lid (34) is attached to a top surface (36) of the flip chip die (12). A wire bond die (40) is attached... Agent: Freescale Semiconductor, Inc. Law Department

20070281398 - Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses: A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20070281399 - Producing soi structure using high-purity ion shower: Disclosed are methods for making SOI and SOG structures using purified ion shower for implanting ions to the donor substrate. The purified ion shower provides expedient, efficient, low-cost and effective ion implantation while minimizing damage to the exfoliation film.... Agent: Corning Incorporated

20070281402 - Schottky barrier tunnel single electron transistor and method of manufacturing the same: Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a... Agent: Ladas & Parry LLP

20070281400 - Semiconductor device and manufacturing method thereof: The semiconductor device has a semiconductor layer, a gate electrode which covers an end portion of the semiconductor layer, and an insulating layer for insulating the semiconductor layer and the gate electrode. The film thickness of the insulating layer which insulates a region where an end portion of the semiconductor... Agent: Nixon Peabody, LLP

20070281401 - Semiconductor device and method of fabricating the same: There is provided a crystalline TFT in which reliability comparable to or superior to a MOS transistor can be obtained and excellent characteristics can be obtained in both an on state and an off state. A gate electrode of the crystalline TFT is formed of a laminate structure of a... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070281403 - Method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing: A method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing includes depositing a gate polysilicon layer on a semiconductor substrate which has a field oxide isolation structure, and then performing a polysilicon chemical-mechanical polishing after a gate polysilicon layer is deposited in order to smooth the uneven polysilicon surface... Agent: Rosenberg, Klein & Lee

20070281404 - Poly silicon layer and method of fabricating the same: A method of fabricating a poly silicon layer comprising the following steps is provided. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing process is performed to... Agent: Jianq Chyun Intellectual Property Office

20070281405 - Methods of stressing transistor channel with replaced gate and related structures: Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of... Agent: Hoffman, Warnick & D'alessandro LLC

20070281406 - Method of making a self aligned ion implanted gate and guard ring structure for use in a sit: A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect... Agent: Birch Stewart Kolasch & Birch

20070281407 - Versatile system for cross-lateral junction field effect transistor: The present, invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122)... Agent: Texas Instruments Incorporated

20070281408 - Versatile system for cross-lateral junction field effect transistor: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122)... Agent: Texas Instruments Incorporated

20070281411 - Formation of strain-inducing films: A method to form a strain-inducing three-component epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is formed by formed by a multiple deposition/etch step sequence, followed by an amorphizing dopant impurity-implant and, finally, a kinetically-driven crystallization process. In one embodiment, the charge-neutral lattice-substitution atoms are smaller and... Agent: Blakely Sokoloff Taylor & Zafman

20070281410 - Spacer-less low-k dielectric processes: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing... Agent: HorizonIPPte Ltd

20070281412 - Ambipolar organic thin-film field-effect transistor and making method: In a thin-film field-effect transistor having metal/insulator/semiconductor (MIS) structure, the semiconductor layer is formed of an organic compound, and the insulator layer is formed of an organic compound which is soluble in an organic solvent and exhibits spontaneous polarization similar to ferroelectric material. The transistor exhibits n-type transistor characteristics when... Agent: Birch Stewart Kolasch & Birch

20070281409 - Multi-gate carbon nano-tube transistors: According to one aspect of the invention, a semiconducting transistor is described. The channel portion of the transistor includes carbon nanotubes formed on top of an insulating layer which covers a local bottom gate. Source and drain conductors are located at ends of the carbon nanotubes. A gate dielectric surrounds... Agent: Intel/blakely

20070281413 - N-channel mosfets comprising dual stressors, and methods for forming the same: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is... Agent: Scully, Scott, Murphy & Presser, P.C.

20070281414 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070281415 - Semiconductor device and manufacturing method thereof: A manufacturing method for a CMOS semiconductor device in which gate electrodes are adjusted to have different work function values comprises forming an device region of a first and second conductivity type for forming first and second MOS semiconductor element devices, respectively, in a semiconductor substrate, forming a gate insulator,... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070281418 - Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single... Agent: Bo-in Lin

20070281416 - Manufacturing method for an integrated semiconductor structure: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers... Agent: Eschweiler & Associates LLC

20070281417 - Manufacturing method for an integrated semiconductor structure: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070281419 - Titanium dioxide thin film systems and method of making same: A thin film titanium dioxide and method for producing the same are disclosed. The thin film titanium dioxide may be produced to have a thickness in the range of 100-1000 nm. The disclosed method for producing the thin film titanium dioxide includes performing a magnetron reactive sputtering process to vaporize... Agent: Brinks Hofer Gilson & Lione

20070281421 - Device and method for making air, gas or vacuum capacitors and other microwave components: A device and method for making a capacitor and other high frequency and/or microwave components. In particular, an air dielectric capacitor has a first electrode and a second electrode that are spaced apart, planar and each of a different size or area. The first electrode is a smaller, planar electrode... Agent: Connolly Bove Lodge & Hutz LLP

20070281420 - Resistor random access memory cell with reduced active area and reduced contact areas: A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070281423 - Method for manufacuring semiconductor device: A method for manufacturing a plurality of memory devices and a plurality of high voltage devices on a substrate are provided. The substrate has a memory region and a high voltage region. The method comprises steps of forming a first dielectric layer on the substrate and then performing a thermal... Agent: J.c. Patents, Inc.

20070281422 - Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are... Agent: Texas Instruments Incorporated

20070281424 - Semiconductor device and method of its formation: In an embodiment a first silicon pattern and a second silicon pattern are formed on a substrate. The second silicon pattern has a lower top surface than the first silicon pattern. A first spacer covering a sidewall of the first silicon pattern is formed and a second spacer covering a... Agent: Marger Johnson & Mccollom, P.C.

20070281425 - Method and apparatus transporting charges in semiconductor device and semiconductor memory device: A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the channel; arranging a charge... Agent: Harness, Dickey & Pierce P.L.C

20070281426 - Method and apparatus transporting charges in semiconductor device and semiconductor memory device: A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the substrate; arranging a charge... Agent: Harness, Dickey & Pierce P.L.C

20070281427 - Bottom conductor for integrated mram: A method to fabricate an MTJ device and its connections to a CMOS integrated circuit is described. The device is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its... Agent: Saile Ackerman LLC

20070281428 - Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070281429 - Method for fabricating semiconductor device: In a method for fabricating a semiconductor device, a first region in a semiconductor substrate is formed with a first-gate-electrode formation portion composed of a first silicon film, a second silicon film, and a second protective film, and a second region therein is formed with a second-gate-electrode formation portion composed... Agent: Mcdermott Will & Emery LLP

20070281430 - Electro-optical device and electronic apparatus: An electro-optical device includes pixel regions arranged at intersections of a plurality of data lines and a plurality of scanning lines on an element substrate. A sensor element, a sensor signal line for outputting a signal from the sensor element, a common wiring line, and a capacitive-coupling-operation bidirectional diode element... Agent: Oliff & Berridge, PLC

20070281431 - Formation of fully silicided (fusi) gate using a dual silicide process: A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of... Agent: Scully, Scott, Murphy & Presser, P.C.

20070281432 - Transistor and method of providing interlocking strained silicon on a silicon substrate: A method for providing interlocking strained silicon on a silicon substrate, comprises providing a mask on a surface of the substrate. The mask comprises a first plurality of openings corresponding to a first plurality of holes to be etched and comprises a second plurality of openings corresponding to a second... Agent: Slater & Matsil LLP

20070281433 - A method for reducing dislocation threading using a suppression implant: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for... Agent: Texas Instruments Incorporated

20070281434 - Capacitor of semiconductor device applying damascene process and method of fabricating the same: According to embodiments of the invention, a height of a capacitor lower electrode is increased. Portions of the lower electrode and an interlayer insulating layer are etched within the interlayer insulating layer that is formed with the lower electrode thereon, so that a trench having a double damascene structure is... Agent: Marger Johnson & Mccollom, P.C.

20070281435 - Engineering strain in thick strained-soi substrates: A semiconductor fabrication process preferably used with a semiconductor on insulator (SOI) wafer. The wafer's active layer is biaxially strained and has first and second regions. The second region is amorphized to alter its strain component(s). The wafer is annealed to re-crystallize the amorphous semiconductor. First and second types of... Agent: Freescale Semiconductor, Inc.

20070281436 - Trench liner for dso integration: A semiconductor process and apparatus provide a shallow trench isolation region (96) with a trench liner (95, 104) for use in a hybrid substrate device (21) by lining a first trench with a first trench liner (95), and then lining a second trench formed within the first trench by depositing... Agent: Hamilton & Terrile, LLP

20070281437 - Image sensor applied with device isolation technique for reducing dark signals and fabrication method thereof: The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each... Agent: Blakely Sokoloff Taylor & Zafman

20070281438 - Methods and apparatus for rf shielding in vertically-integrated semiconductor devices: A patterned ground shield (PGS) (130) in a vertically-integrated structure includes a patterned conductor (e.g., a metallic layer) provided between a first substrate (110) having a first semiconductor device (1120 formed therein and a second substrate (120) having a second device (122) formed therein. A bonding layer (140) is used... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070281439 - Techniques for layer transfer processing: Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein In another aspect, a method... Agent: Ryan, Mason & Lewis, LLP

20070281440 - Producing soi structure using ion shower: Disclosed are methods for making SOI and SOG structures using ion shower for implanting ions to the donor substrate. The ion shower provides expedient, efficient, low-cost and effective ion implantation while minimizing damage to the exfoliation film.... Agent: Corning Incorporated

20070281441 - Semiconductor substrate and process for producing it: A semiconductor substrate useful as a donor wafer is a single-crystal silicon wafer having a relaxed, single-crystal layer containing silicon and germanium on its surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight, and a layer of... Agent: Brooks Kushman P.C.

20070281442 - Power semiconductor: In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the... Agent: Buchanan, Ingersoll & Rooney PC

20070281443 - Method of manufacturing devices, positioning method, dicing method and dicing apparatus: In a dicing method, a dicing is performed in such a way that in such a way that a device substrate, on which two or more devices and alignment marks for positioning are formed, is positioned in accordance with the alignment mark. The dicing method comprises: a substrate fixing step... Agent: Kratz, Quintos & Hanson, LLP

20070281444 - Substrate dividing system, substrate manufacturing equipment, substrate scribing method and substrate dividing method: The objective of the present invention is to provide a substrate cutting system which requires a small footprint area so as to be compact, and also which is capable of efficiently cutting a substrate. Clamp devices 50 are attached to the substrate cutting system. The clamp devices can hold at... Agent: Snell & Wilmer L.L.P. (main)

20070281445 - Method for self-supported transfer of a fine layer by pulsation after implantation or co-implantation: A method for self-supported transfer of a fine layer, in which at least one species of ions is implanted in a source-substrate at a specified depth in relation to the surface of the source-substrate. A stiffener is applied in intimate contact with the source-substrate and the source-substrate undergoes a heat... Agent: Brinks Hofer Gilson & Lione Jasper W. Dockrey

20070281446 - Dual surface soi by lateral epitaxial overgrowth: A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first... Agent: Hamilton & Terrile, LLP

20070281447 - Method of loading and/or unloading wafer in semiconductor manufacturing apparatus: In a method of unloading and/or loading a wafer in a semiconductor device manufacturing apparatus, pumping and/or purge operations are performed in a process chamber while the wafer is separated from a susceptor by a desired distance using a plurality of lift pins.... Agent: Volentine & Whitt PLLC

20070281448 - Novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide: Methods of filling a gap on a substrate with silicon oxide are described. The methods may include the steps of introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber, reacting the precursors to form a first silicon oxide layer in the gap on the substrate, and etching... Agent: Townsend And Townsend And Crew LLP / Amat

20070281449 - Substrate transportation method and apparatus: The substrate transportation apparatus 10 comprises a plurality of transportation rollers 22A-22D disposed at a predetermined spacing for transporting the substrate 40 in response to rotation of the transportation rollers 22. Each of the transportation rollers 22 is generally hollow cylindrical member formed with a plurality of slit nozzles 24... Agent: Young & Thompson

20070281450 - Use of scanning theme implanters and annealers for selective implantation and annealing: A method and system for integrated circuit (IC) processing combines an ion implantation tool and a laser anneal tool in a single unit with a shared precision X-Y scanner. A semiconductor wafer is loaded onto a the X-Y table of the scanner. Data defining the desired ion implantation is used... Agent: Winstead PC

20070281451 - Method for forming schottky diodes and ohmic contacts in the same integrated circuit: A method for forming an ohmic contact and a Schottky diode in an integrated circuit includes providing a semiconductor substrate; forming first and second diffusion regions in the semiconductor substrate; forming an insulating layer on the semiconductor substrate; forming a first contact opening in the insulating layer and over the... Agent: Patent Law Group LLP

20070281453 - Electronic component, laser device, optical writing device and image forming apparatus: An electronic component includes: a base a seal body fixed to the base, constituting a hermetically sealed space together with the base; and an electronic component main body attached to a metal substrate via an adhesive containing silver within the hermetically sealed space. The base has a nickel plated layer,... Agent: Morgan Lewis & Bockius LLP

20070281452 - Methods of forming carbon nanotubes and methods of fabricating integrated circuitry: A step wall is formed over a substrate. Catalytic material of different composition than the step wall is provided proximate thereto. A carbon nanotube is grown from the catalytic material along the step wall generally parallel to the substrate. A method of fabricating integrated circuitry includes forming a step wall... Agent: Wells St. John P.s.

20070281454 - Method of manufacturing semiconductor device for formation of pin transistor: A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation... Agent: Ladas & Parry LLP

20070281455 - Semiconductor device with bulb recess and saddle fin and method of manufacturing the same: A semiconductor device includes an active region, a bulb recess with a certain depth formed in a channel-forming region of the active region, a device isolation structure encompassing the active region, wherein the device isolation structure has a line-shaped opening such that a surface of the device isolation structure is... Agent: Lowe Hauptman Ham & Berner, LLP

20070281456 - Method of forming line of semiconductor device: A method of forming a line of a semiconductor device, wherein electrical characteristics of the device can be improved by reducing the resistance of the line. According to the method, an amorphous silicide layer or an amorphous TiSiN layer is formed on a semiconductor substrate in which given structures are... Agent: Marshall, Gerstein & Borun LLP

20070281457 - Copper layer and a method for manufacturing said copper layer: A copper layer on a substrate has a copper seed layer and an interface. The copper seed layer contains insoluble substances that are insoluble with copper. The interface is formed between the copper seed layer and the substrate. The copper layer replaces a conventional barrier and has significantly improved thermal... Agent: Rabin & Berdo, PC

20070281458 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin

20070281460 - Front-end processed wafer having through-chip connections: A method involves forming vias in a blank semiconductor wafer, making at least some of the vias in the blank semiconductor wafer electrically conductive, and performing front end processing on the blank wafer so as to create devices on the wafer that are connected to the electrically conductive vias.... Agent: Morgan & Finnegan, L.L.P.

20070281459 - Multilayer substrate manufacturing method: A manufacturing method of a multilayer substrate that suppresses relative displacement of layers and forms interconnecting portions electrically connecting layers having an accurate positioning. A manufacturing method of a multilayer substrate for laminating, via an insulating film, a wiring layer formed by patterning a conductive film comprises providing a positioning... Agent: Fish & Richardson P.C.

20070281462 - Method for manufacturing silicon carbide semiconductor device: A method for manufacturing a silicon carbide (SiC) semiconductor device is disclosed that uses dry etching with the use of high-density inductive coupled plasma (ICP). The method employs a first dry etching and a sequential second dry etching under conditions that differ from those used in the first dry etching.... Agent: Rossi, Kimms & Mcdowell LLP.

20070281461 - Semiconductor device having a contact structure with a contact spacer and method of fabricating the same: Methods of manufacturing a semiconductor device having reduced susceptibility to void formation between upper metal wiring layers and lower contact pads are provided. According to the methods, an etch shield layer is formed to protect contact pads from subsequent etch processes. Semiconductor devices manufactured according to the methods are also... Agent: Marger Johnson & Mccollom, P.C.

20070281463 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070281464 - Multi-layer circuit board with fine pitches and fabricating method thereof: A method for fabricating a multi-layer circuit board with fine pitches is provided. First, a plurality of conductive pads is disposed on a core circuit board. Next, a first dielectric layer and a second dielectric are formed on the core circuit board, in which a plurality of pattern openings are... Agent: North America Intellectual Property Corporation

20070281465 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a lower interconnection part 12 which is formed on a silicon substrate 10 and includes an inter-layer insulation film 36 formed of a low-k film 32 and a hydrophilic insulation film 34 formed on the low-k film 32, and an interconnection layer 44a, 44b buried in... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070281466 - Front-end processed wafer having through-chip connections: A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metallization layer. An alternative method... Agent: Morgan & Finnegan, L.L.P.

20070281467 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070281468 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within... Agent: Mou-shiung Lin Science-based Industrial Park

20070281469 - Modified via bottom structure for reliability enhancement: The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the... Agent: Scully, Scott, Murphy & Presser, P.C.

20070281470 - Semiconductor device and method for manufacturing the same: The present invention provides a method for manufacturing a semiconductor device, including the step of forming a hole penetrating an insulating film over a semiconductor substrate, wherein the step includes the steps of forming a pedestal at a position where a hole to be formed; forming an insulating film to... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser, P.C.

20070281471 - Advanced multilayered coreless support structures and their fabrication: e

20070281472 - Method of increasing transistor performance by dopant activation after silicidation: By performing a laser-based or flash-based anneal process after silicidation, the degree of dopant activation with reduced diffusion activity may be accomplished, while the characteristics of the metal silicide may be improved or the complexity for manufacturing the same may be reduced.... Agent: Williams, Morgan & Amerson

20070281473 - Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces: Methods and systems for forming electrical interconnects through microelectronic workpieces are disclosed herein. One aspect of the invention is directed to a method of manufacturing an electrical interconnect in a microelectronic workpiece having a plurality of dies. Each die can include at least one terminal electrically coupled to an integrated... Agent: Perkins Coie LLP Patent-sea

20070281474 - Manufacturing method of semiconductor device: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by... Agent: Morrison & Foerster LLP

20070281475 - Diethylsilane as a silicon source in the deposition of metal silicate films: A method for forming a metal silicate as a high k dielectric in an electronic device, comprising the steps of: providing diethylsilane to a reaction zone; concurrently providing a source of oxygen to the reaction zone; concurrently providing a metal precursor to the reaction zone; reacting the diethylsilane, source of... Agent: Air Products And Chemicals, Inc. Patent Department

20070281476 - Methods for forming thin copper films and structures formed thereby: Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a thin conformal copper layer on a surface by utilizing a formation temperature below about 125 degrees Celsius.... Agent: Intel Corporation C/o Intellevate, LLC

20070281480 - Method for fabricating semiconductor device having capacitor: A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer; forming... Agent: Townsend And Townsend And Crew, LLP

20070281478 - Plasma processing method and apparatus: Plasma processing of plural substrates is performed in a plasma processing apparatus, which is provided with a plasma processing chamber having an antenna electrode and a lower electrode for placing and retaining the plural substrates in turn within the plasma processing chamber, a gas feeder for feeding processing gas into... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070281479 - Process including silo-chloro passivation for etching tungsten silicide overlying polysilicon: A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20070281481 - Controlled growth of gallium nitride nanostructures: A transition metal substituted, amorphous mesoporous silica framework with a high degree of structural order and a narrow pore diameter distribution (±0.15 nm FWHM) was synthesized and used for the templated growth of GaN nanostructures, such as single wall nanotubes, nanopipes and nanowires. The physical properties of the GaN nanostructures... Agent: Ropes & Gray LLP Patent Docketing 39/41

20070281477 - Process for etching tungsten silicide overlying polysilicon particularly in a flash memory: A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20070281482 - Method for cmp with variable down-force adjustment: The present invention relates to a method for performing chemical mechanical polishing. A high down-force step is performed. A low down-force step is performed. At least one of the down-force steps is modified, based on if one of the down-force steps exceeds an acceptable tolerance associated therewith. Other systems and... Agent: Texas Instruments Incorporated

20070281485 - Method of and apparatus for semiconductor device: A semiconductor device fabrication method by which a semiconductor wafer is polished by pressing the semiconductor wafer against a polishing pad includes: an optimum condition calculation step for finding polishing conditions based on the hardness of the polishing pad; and a step of polishing the semiconductor wafer according to the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070281486 - Slurry composition, method of polishing an object layer and method of manufacturing a non-volatile memory device using the slurry composition: Methods of polishing an object layer and for manufacturing a non-volatile memory device that incorporates such a polished object layer using a specially formulated slurry composition are disclosed. The slurry compositions include a ceria abrasive, a nonionic surfactant having a hydrophilic-lipophilic balance (HLB) value in a range of about 12... Agent: Mills & Onello LLP

20070281484 - Surface treatment method for nitride crystal, nitride crystal substrate, nitride crystal substrate with epitaxial layer and semiconductor device, and method of manufacturing nitride crystal substrate with epitaxial layer and semiconductor device: A surface treatment method for a nitride crystal is a surface treatment method of chemically and mechanically polishing a surface of the nitride crystal. Oxide abrasive grains are used. The abrasive grains have a standard free energy of formation of at least −850 kJ/mol as a converted value per 1... Agent: Mcdermott Will & Emery LLP

20070281483 - Compositions for chemical mechanical polishing silica and silicon nitride having improved endpoint detection: The present invention provides a method of manufacturing a composition for polishing silica and silicon nitride on a semiconductor substrate. The method comprises ion-exchanging carboxylic acid polymer to reduce ammonia and combining by weight percent 0.01 to 5 of the ion-exchanged carboxylic acid polymer with 0.001 to 1 quaternary ammonium... Agent: Rohm And Haas Electronic Materials Cmp Holdings, Inc.

20070281487 - Method for an integrated circuit contact: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating... Agent: Trask Britt, P.C./ Micron Technology

20070281488 - Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon: A method of forming at least one undercut structure in a semiconductor substrate. The method comprises providing a semiconductor substrate, forming at least one doped region in the semiconductor substrate, and removing the at least one doped region to form at least one undercut structure in the semiconductor substrate. The... Agent: Trask Britt, P.C./ Micron Technology

20070281489 - Methods for minimizing mask undercuts and notches for plasma processing system: A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first,... Agent: Ipsg, P.C.

20070281490 - Electron beam writing data creating method and electron beam writing data creating apparatus: An electron beam writing data creating method for creating writing data used for electron beam lithography includes judging whether resizing process need to be performed to a figure cell in device pattern data by cell base design or not, the figure cell including a cell layout frame and a pattern... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070281491 - Residue free hardmask trim: A method for forming features in a polysilicon layer is provided. A hardmask layer is formed over the polysilicon layer. A photoresist mask is formed over the hardmask layer. The hardmask layer is etched through the photoresist mask to form a patterned hardmask. The patterned hardmask is trimmed by providing... Agent: Beyer Weaver LLP

20070281492 - Protective thin films for use during fabrication of semiconductors, mems, and microstructures: A method of protecting a substrate during fabrication of semiconductor, MEMS, or biotechnology devices. The method includes application of a protective thin film which typically has a thickness ranging from about 3 Å to about 1,000 Å, wherein precursor materials used to deposit the protective thin film are organic-based precursors... Agent: Shirley L. Church, Esq.

20070281493 - Methods of shaping vertical single crystal silicon walls and resulting structures: A single crystal silicon etching method includes providing single crystal silicon substrate having at least one trench therein. The substrate is exposed to an anisotropic etchant which undercuts the silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon... Agent: Trask Britt, P.C./ Micron Technology

20070281494 - Transparent contact and method for the production thereof: The invention relates to a method for producing a transparent, low-resistance contact on a substrate, a layer sequence consisting of a first layer, a second layer, and a third layer being applied to the substrate. According to the invention, the first layer consists of a material containing AlnGa1-n AsmSb1-m, and... Agent: Leydig Voit & Mayer, Ltd

20070281495 - Formation of high quality dielectric films of silicon dioxide for sti: usage of different siloxane-based precursors for harp ii - remote plasma enhanced deposition processes: Methods of depositing a dielectric layer in a gap formed on a substrate are described. The methods include introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber. The organo-silicon precursor has a C:Si atom ratio of less than 8, and the oxygen precursor comprises atomic oxygen that... Agent: Townsend And Townsend And Crew LLP / Amat

20070281496 - Chemical vapor deposition of high quality flow-like silicon dioxide using a silicon containing precursor and atomic oxygen: Methods of depositing a silicon oxide layer on a substrate are described. The methods may include the steps of providing a substrate to a deposition chamber, generating an atomic oxygen precursor outside the deposition chamber, and introducing the atomic oxygen precursor into the chamber. The methods may also include introducing... Agent: Townsend And Townsend And Crew LLP / Amat

20070281497 - Method to mitigate impact of uv and e-beam exposure on semiconductor device film properties by use of a bilayer film: Methods are provided for processing a substrate comprising a bilayer barrier film thereon. In one aspect, a method comprises depositing a first barrier layer, depositing a second barrier layer on the first barrier layer, depositing a dielectric layer on the bilayer barrier film formed by the first barrier layer and... Agent: Patterson & Sheridan, LLP

20070281498 - Spin-on glass composition and method of forming silicon oxide layer in semiconductor manufacturing process using the same: A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing polysilazane having a compound of the formula —(SiH2NH)n— wherein n represents a positive integer,... Agent: Harness, Dickey & Pierce, P.L.C