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Semiconductor device manufacturing: process November USPTO class patent listing 11/07

20070275484 - Ferroelectric memory and method for manufacturing the same: A method for manufacturing a ferroelectric memory, comprising the steps of: (a) forming a conductive layer; (b) heating a surface of the conductive layer in an atmosphere containing nitrogen; (c) forming an orientation control layer above the conductive layer; (d) forming a first electrode above the orientation control layer; (e)... Agent: Harness, Dickey & Pierce, P.L.C

20070275489 - Reflective electrode for a semiconductor light emitting apparatus: A process is disclosed for forming a reflective electrode on a semiconductor light emitting device, the light emitting device having an active layer for generating light and a cladding layer in electrical contact with the active layer. The process involves depositing an intermediate layer of electrically conductive material on the... Agent: Patent Law Group LLP

20070275497 - Method of aligning a substrate, mask to be aligned with the same, and flat panel display apparatus using the same: A method of aligning a substrate includes forming a first alignment hole in the substrate, preparing a mask with a second alignment hole narrower than the first alignment hole, modifying a surface reflectance around either the first alignment hole or the second alignment hole to form a treatment region, positioning... Agent: Lee & Morse, P.C.

20070275498 - Enhancing performance in ink-jet printed organic semiconductors: Systems and methods are provided to improve the performance of electronic and optoelectronic devices made using organic semiconductor processing technology. An ink-jet device dispenses an organic composite mixture onto a substrate. The mixture includes a semiconducting polymer and nanomaterials dispersed into an organic solvent. The type of solvent used preferably... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070275499 - Nonostructure arrays and methods of making same: A method of making a nanostructure array including disposing a masking material on a nanoporous template such that a first number of the plurality of nanopores are fully coated while a second number of the plurality of nanopores are not-fully coated by the masking material is provided. The method includes... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20070275500 - Wiring and organic transistor, and manufacturing method thereof: The organic transistor has electrodes whose bodies are formed mainly of an inexpensive first metal and whose surfaces are formed of a second metal that is expensive but provides high performance properties. To obtain stability of this structure with a low cost, the present invention uses a property of the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070275485 - Real-time gate etch critical dimension control by oxygen monitoring: A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow... Agent: Law Office Of Jeffrey M. Weinick, LLC

20070275486 - Equipment and method for processing semiconductor: Semiconductor processing equipment includes a transfer chamber (3) having a plurality of transfer ports (33) arranged at different positions in a lateral direction. A process chamber (4A) for performing a semiconductor process to a substrate (W) to be processed is connected with the transfer chamber (3) through one of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070275487 - Free-standing electrostatically-doped carbon nanotube device and method for making same: A method and associated structure for forming a free-standing electrostatically-doped carbon nanotube device is described. The method includes providing a carbon nanotube on a substrate in such a way as to have a free-standing portion. One way of forming a free-standing portion of the carbon nanotube is to remove a... Agent: General Electric Company Global Research

20070275488 - Method for manufacturing backside-illuminated optical sensor: A CCD portion 3 is formed on a front surface side of a semiconductor substrate 1. A region of a back surface side of semiconductor substrate 1 that corresponds to CCD portion 3 is thinned while leaving peripheral regions 1a of the region, and an accumulation layer 5 is formed... Agent: Drinker Biddle & Reath (dc)

20070275490 - Light emitting device and method of manufacturing thereof: A device of forming a film from an organic compound material at low cost is provided, using an organic compound material having high light emission efficiency. An organic compound film is formed on a substrate under an inert gas atmosphere by spraying of a colloid solution in which organic compound... Agent: Nixon Peabody, LLP

20070275491 - Methods of manufacturing interferometric modulators with thin film transistors: A modulator has a transparent substrate with a first surface. At least one interferometric modulator element resides on the first surface. At least one thin film circuit component electrically connected to the element resides on the surface. When more than one interferometric element resides on the first surface, there is... Agent: Knobbe, Martens, Olson & Bear, LLP

20070275492 - Hybrid integration based on wafer-bonding of devices to aisb monolithically grown on si: Exemplary embodiments provide a semiconductor fabrication method including a combination of monolithic integration techniques with wafer bonding techniques. The resulting semiconductor devices can be used in a wide variety of opto-electronic and/or electronic applications such as lasers, light emitting diodes (LEDs), phototvoltaics, photodetectors and transistors. In an exemplary embodiment, the... Agent: Mh2 Technology Law Group

20070275493 - Method of manufacturing image display device and method of dividing device: A manufacturing method of manufacturing an image display device having a wiring and a display element electrically connected to the wiring, comprises a step of dividing a device having the wiring and a substrate holding the wiring, at a predetermined division position, and the dividing step further comprises a step... Agent: Fitzpatrick Cella Harper & Scinto

20070275495 - Method for fabricating a pressure sensor using soi wafers: A pressure sensor is manufactured by joining two wafers (1a, 14), the first wafer comprising CMOS circuitry and the second being an SOI wafer. A recess is formed in the top material layer of the first wafer, which is covered by the silicon layer of the second wafer to form... Agent: Richard F. Jaworski Cooper & Dunham LLP

20070275494 - Pressure sensor having a chamber and a method for fabricating the same: A pressure sensor is manufactured by joining two wafers, the first wafer comprising CMOS circuitry and the second being an SOI wafer. A recess is formed in the top material layer of the first wafer, which is covered by the silicon layer of the second wafer to form a cavity.... Agent: Richard F. Jaworski Cooper & Dunham LLP

20070275496 - Solid-state imaging device and method of manufacturing same: A solid-state imaging device includes: a substrate; a photo-receiving portion formed in the substrate; a wiring layer formed on the substrate and having a trench being formed on a region directly above the photo-receiving portion; and a light guiding member provided in the trench and made of organic material. An... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070275501 - Fabricating tft having fluorocarbon-containing layer: A process for fabricating a thin film transistor comprising: (a) forming a gate dielectric; (b) forming a layer including a substance comprising a fluorocarbon structure; and (c) forming a semiconductor layer including a thiophene compound comprising one or more substituted thiophene units, one or more unsubstituted thiophene units, and optionally... Agent: Patent Documentation Center

20070275502 - Air cavity wafer level packaging assembly and method: A wafer level packaging method and assembly for packaging a wafer segment having active and inactive areas. A sacrificial layer is provided over the wafer segment. Then the sacrificial layer is modified to create a sacrificial structure having sacrificial layer openings which expose inactive areas. A cover layer is then... Agent: Bereskin And Parr

20070275504 - Electronic component mounting structure: Such electronic component mounting structure comprises a substrate and a quadrate electronic component mounted on the substrate, wherein a gap between the substrate and the electronic component is filled with a first cured resin filling at least a corner area of the electronic component and a second cured resin filling... Agent: Loctite Corporation

20070275503 - Method for fabricating chip package: The present invention provides a method for fabricating chip package comprises the following steps: forming a photoresist layer on a metal layer over a passivation layer, an opening in the photoresist layer exposing the metal layer, wherein said forming the photoresist layer comprises exposing the photoresist layer using 1X stepper... Agent: Megica Corporation

20070275505 - Camera device, method of manufacturing a camera device, wafer scale package: The invention relates to a camera device and a method for manufacturing such a device. The camera device comprises an image capturing element, a lens element for imaging an object at the image capturing element and a spacer means for maintaining a predetermined distance along the main optical axis through... Agent: Wood, Phillips, Katz, Clark & Mortimer

20070275506 - Semiconductor device and a method of manufacturing the same: It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the... Agent: Eric Robinson

20070275507 - Molding apparatus for manufacturing semiconductor device and method using the same: The present invention provides a molding apparatus for encapsulating a semiconductor substrate in which a plurality of semiconductor chips are formed and a method of manufacturing the semiconductor substrate using the same. The molding apparatus includes an upper half for fixing the semiconductor substrate and a lower half having a... Agent: Rabin & Berdo, PC

20070275508 - Memory device with high dielectric constant gate dielectrics and metal floating gates: A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070275509 - Method of manufacturing nor-type mask rom device and semiconductor device including the same: A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed... Agent: Lee & Morse, P.C.

20070275510 - Metal oxide field effect transistor with a sharp halo and a method of forming the transistor: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070275512 - Method for manufacturing thin film transistor substrate using maskless exposing device: A method for manufacturing a thin film transistor substrate using a maskless exposing device includes forming a data metal layer on a substrate having a gate pattern and common electrodes along with gate insulation layers, active layers, and ohmic contact layers for a thin film transistors; forming a photoresist on... Agent: Seyfarth Shaw, LLP

20070275511 - Method of fabricating thin film transistor: A method for fabricating a thin film transistor is provided. A conductive layer is formed on a substrate. A patterned mask is formed on the conductive layer to cover a predetermined thin film transistor (TFT) area, and at least one portion of the conductive layer exposed by the patterned mask... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070275513 - Formation of shallow sige conduction channel: m

20070275514 - Semiconductor device and method of manufacturing same: Semiconductor device is prevented from undergoing decline in characteristics and reliability even if width of isolation trench is reduced. Semiconductor device includes: substrate obtained by building up second silicon substrate on first silicon substrate via silicon oxide film; element-forming region in which elements (gate electrode and source/drain region) have been... Agent: Mcginn Intellectual Property Law Group, PLLC

20070275515 - Deep buried channel junction field effect transistor (dbcjfet): A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside... Agent: Texas Instruments Incorporated

20070275517 - Dual poly deposition and through gate oxide implants: Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off,... Agent: Texas Instruments Incorporated

20070275521 - Method of manufacturing hollow micro-needle structures: A method of manufacturing a hollow micro-needle structure includes the steps of: disposing a first mask layer and a second mask layer respectively aside a first substrate and aside a rear surface of the first substrate, wherein the first substrate is transparent to predetermined light; forming a photoresist layer on... Agent: Birch Stewart Kolasch & Birch

20070275519 - Method of manufacturing non-volatile memory device: A method of manufacturing a non-volatile memory device includes the steps of forming gates respectively having a structure in which a gate insulating layer, a first conductive layer, a dielectric layer, a second conductive layer and a metal-silicide layer are laminated over a semiconductor substrate, annealing the metal-silicide layer at... Agent: Marshall, Gerstein & Borun LLP

20070275520 - Method of manufacturing semiconductor device: An object of the present inventions is to overcome a problem that the presence of a metal film, which is opaque to a visible light, between a lower layer alignment mark and a photoresist prevents the detection of the lower layer alignment mark, to make the pattern formation difficult. In... Agent: Foley And Lardner LLP Suite 500

20070275518 - Pixel structure and fabrication method thereof: A pixel structure and a fabrication method thereof are provided. The pixel comprises a substrate, a gate, a gate insulating layer, a channel layer, a first source/drain, a second source/drain, a dielectric layer, a first pixel electrode, and a second pixel electrode. The gate is disposed on the substrate and... Agent: Jianq Chyun Intellectual Property Office

20070275516 - Manufacturing method of semiconductor device: SiH3CH3 having the concentration of 1 to 10% is diluted with H2 and a portion of the diluted SiH3CH3, GeH4 and SiH4 (or DCS) are respectively supplied to a chamber of an epitaxial device at predetermined flow rates, and SiGe:C is formed by an epitaxial growth technique. By diluting the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070275522 - Method to enhance cmos transistor performance by inducing strain in the gate and channel: A method of manufacturing complementary metal oxide semiconductor transistors forms different types of transistors such as N-type metal oxide semiconductor (NMOS) transistors and P-type metal oxide semiconductor (PMOS) transistors (first and second type transistors) on a substrate. The method forms an optional oxide layer on the NMOS transistors and the... Agent: Frederick W. Gibb, Iii Mcginn & Gibb, PLLC

20070275523 - Trench-capacitor dram device and manufacture method thereof: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched... Agent: North America Intellectual Property Corporation

20070275524 - Semiconductor device fabrication method: In fabrication of a semiconductor device which is provided with resistances and MOS transistors on the same substrate, preventing conduction failures of contacts and preventing leaching of wiring metal into a silicon substrate. Firstly, an underlying structure is prepared. Then, a silicon oxide layer is formed on the underlying structure.... Agent: Volentine & Whitt PLLC

20070275525 - Capacitive substrate and method of making same: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20070275526 - Methods of programming memory cells using manipulation of oxygen vacancies: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070275527 - Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making: Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source... Agent: Merchant & Gould PC

20070275528 - Method of manufacturing semiconductor device: A dummy oxide film having a film thickness that is the same as that of a gate oxide film of a high voltage transistor is formed on a gate electrode of a transistor, and the dummy oxide film and the gate oxide film formed on a substrate surface are removed... Agent: Volentine & Whitt PLLC

20070275529 - Semiconductor device manufacturing method: After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating film to be a first gate insulating film is formed on each of the first and third active regions, and then,... Agent: Mcdermott Will & Emery LLP

20070275531 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device includes forming a gate over a semiconductor substrate in which a cell region, a low voltage region and a high voltage region are defined. First ions are implanted into the cell region to form doped junctions in the cell region, the low... Agent: Townsend And Townsend And Crew, LLP

20070275530 - Semiconductor structure and fabricating method thereof: A semiconductor structure and a method of fabricating the same are provided. A substrate having a metal-oxide-semiconductor transistor is provided. The metal-oxide-semiconductor transistor includes a gate, a source/drain extended region, a first spacer, a liner, a source/drain and a metal silicide layer. A portion of the first spacer is removed... Agent: Jianq Chyun Intellectual Property Office

20070275532 - Optimized deep source/drain junctions with thin poly gate in a field effect transistor: A semiconductor structure in which the poly depletion and parasitic capacitance problems with poly-Si gate are reduced is provided as well as a method of making the same. The structure includes a thin poly-Si gate and optimized deep source/drain doping. The method changes the sequence of the different implantations steps... Agent: Scully Scott Murphy & Presser, PC

20070275533 - Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance: The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first conductive contact is located over the front surface of... Agent: Scully Scott Murphy & Presser, PC

20070275534 - Varied impurity profile region formation for varying breakdown voltage of devices: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the... Agent: Hoffman, Warnick & D'alessandro LLC

20070275535 - Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base.... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070275536 - Mim capacitor: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070275537 - Formation of improved soi substrates using bulk semiconductor wafers: The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical... Agent: Scully Scott Murphy & Presser, PC

20070275538 - Method with high gapfill capability for semiconductor devices: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a... Agent: Townsend And Townsend And Crew, LLP

20070275541 - Back side wafer dicing: Systems and methods for scribing a semiconductor wafer with reduced or no damage or debris to or on individual integrated circuits caused by the scribing process. The semiconductor wafer is scribed from a back side thereof. In one embodiment, the back side of the wafer is scribed following a back... Agent: Electro Scientific Industries/stoel Rives, LLP

20070275540 - Backside via formation prior to die attachment: Backside via formation in one or more dice prior to the one or more dice being attached to an underlying substrate is described herein. The resulting backside vias having substantially no air voids or air voids occupying not greater than 8 percent of the total volume of the backside vias.... Agent: Schwabe, Williamson & Wyatt, P.C.

20070275539 - Method of stimulating die circuitry and structure therefor: A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further... Agent: Freescale Semiconductor, Inc. Law Department

20070275542 - Substrate separation method and liquid ejecting head production method using the substrate separation method: The invention provides a substrate separation method for separating a substrate into a plurality of chips. The substrate separation method according to the invention includes: a first step of irradiating a laser beam on boundary lines of each area, which constitutes a chip, of the substrate, while concentrating the beam... Agent: Workman Nydegger

20070275544 - Fabrication method of semiconductor device: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum... Agent: Miles & Stockbridge PC

20070275543 - Manufacturing method of a semiconductor device: This invention aims at improvement in reliability of a semiconductor device. In this invention, a semiconductor wafer is irradiated with laser light so as to have a fractured layer formed in the interior of the semiconductor wafer, the semiconductor wafer is mounted on a dicing tape via paste (adhesive layer),... Agent: Miles & Stockbridge PC

20070275545 - Higher selectivity, method for passivating short circuit current paths in semiconductor devices: Certain modifications and additions to the prior art short passivation technique have lead to improvements in the low light voltage of solar cells which are made using the improved passivation technique. Examples of the modifications include: 1) reducing the voltage bias on the cell while increasing the time of application... Agent: Energy Conversion Devices, Inc.

20070275546 - Electrolyte for photovoltaic device as well as photovoltaic device and dye-sensitized solar cell including that electrolyte: An electrolyte for a photovoltaic device including (i) a layered clay mineral and/or an organically modified layered clay mineral and (ii) an ionic liquid as well as a photovoltaic device including a photoelectrode including a transparent conducting layer and a metal oxide semiconductor mesoporous film using, as an electrolyte layer,... Agent: Connolly Bove Lodge & Hutz LLP

20070275547 - Integrated circuit structure and manufacturing method thereof: An integrated circuit structure is described, and includes a substrate, a contact window, and a Schottky contact metal layer. A heavily doped region and a lightly doped region are formed in the substrate. The contact window is disposed above the heavily doped region, and the Schottky contact metal layer is... Agent: J.c. Patents

20070275548 - Method and structure for reducing contact resistance between silicide contact and overlying metallization: A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu... Agent: Scully Scott Murphy & Presser, PC

20070275550 - Barrier layer for fine-pitch mask-based substrate bumping: A structure that may be used in substrate solder bumping comprises a substrate (110), a solder resist layer (120) disposed over the substrate, a plurality of solder resist openings (121) in a surface (122) of the solder resist layer, a conformal barrier layer (130) having a first portion (131) over... Agent: Intel Corporation C/o Intellevate, LLC

20070275549 - Contact surrounded by passivation and polymide and method therefor: A semiconductor device has contact between the last interconnect layer and the bond pad that includes a barrier metal between the bond pad and the last interconnect layer. Both a passivation layer and a polyimide layer separate the last interconnect layer and the bond pad. The passivation layer is patterned... Agent: Freescale Semiconductor, Inc. Law Department

20070275551 - Shapes-based migration of aluminum designs to copper damascene: An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.... Agent: Schmeiser, Olsen & Watts

20070275553 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device according to the present invention includes the steps of providing a semiconductor substrate in which an element isolation region and active regions surrounded by the element isolation region are formed, forming a plurality of conductive lines disposed such that the conductive lines cross... Agent: Mcginn Intellectual Property Law Group, PLLC

20070275552 - Structure for reducing lateral fringe capacitance in semiconductor devices and method of forming the same: A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.... Agent: Cantor Colburn LLP - IBM Fishkill

20070275554 - Semiconductor device with interconnection structure for reducing stress migration: The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the... Agent: Sughrue Mion, PLLC

20070275555 - Method of forming an electrical contact in a semiconductor device using an improved self-aligned contact (sac) process: A contact for a semiconductor device is made by performing, inter alia, a CMP process on an interlayer insulation layer to expose a first hard mask layer of each conductive line. The interlayer insulation layer is partially removed. A second hard mask layer is formed on a resultant substrate. Another... Agent: Ladas & Parry LLP

20070275556 - Fabrication method: A method for forming a multilevel structure on a surface by depositing a curable liquid layer on the surface; pressing a stamp having a multilevel pattern therein into the liquid layer to produce in the liquid layer a multilevel structure defined by the pattern; and, curing the liquid layer to... Agent: Anne Vachon Dougherty

20070275557 - Formation of oxidation-resistant seed layer for interconnect applications: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to... Agent: Scully, Scott, Murphy & Presser, P.C.

20070275558 - Method for manufacuturing semiconductor device: The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a metal interconnect on a substrate; forming a refractory metal layer containing titanium (Ti) or tantalum (Ta) on a surface of the metal interconnect; forming an insulating interlayer so as to cover the refractory metal layer;... Agent: Mcginn Intellectual Property Law Group, PLLC

20070275559 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device which an etch-prevention layer, first and second interlayer insulating layers, and first, second and third hard mask layers are sequentially formed on a semiconductor substrate. The third hard mask layer is etched to expose a portion of a region on the second... Agent: Marshall, Gerstein & Borun LLP

20070275560 - Method of manufacturing semiconductor device: A low dielectric constant film containing a silicon, a carbon, an oxygen, and a hydrogen is formed on a substrate as a semiconductor wafer, and a resist film is formed on the low dielectric constant film. Then, the low dielectric constant film is etched with the use of the resist... Agent: Smith, Gambrell & Russell

20070275561 - Gas switching during an etch process to modulate the characteristics of the etch: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while... Agent: Texas Instruments Incorporated

20070275562 - Apparatus and method for treating substrate, and injection head used in the apparatus: Provided are an injection head, and a substrate treatment apparatus and method using the same. The substrate treatment apparatus includes a rotatable spin head supporting a substrate, an injection head installed on the spin head to supply a fluid to a bottom surface of the substrate supported on the spin... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070275563 - Mask forming and implanting methods using implant stopping layer and mask so formed: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing... Agent: Hoffman, Warnick & D'alessandro LLC

20070275564 - Etching method and storage medium: An etching method which makes it possible to obtain a desired etching shape with ease, and a computer-readable storage medium storing a program for implementing the method. The etching method is executed by a substrate processing apparatus that performs plasma processing on a semiconductor wafer by plasma. The apparatus comprises... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070275565 - Full removal of dual damascene metal level: A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070275566 - Method of producing semiconductor substrate: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not... Agent: Sughrue Mion, PLLC

20070275567 - Methods of manufacturing metal oxide nanowires: Metal oxide nanowires are being investigated to make nanodevices and nanosensors. High operation temperatures or vacuum is required in the manufacturing of metal oxide nanowires by existing vapour phase evaporation methods. This invention provides a method of manufacturing metal oxide nanowires by first providing a metal to form a non-linear... Agent: Buchanan, Ingersoll & Rooney PC

20070275568 - Insulation film forming method, insulation film forming system, and semiconductor device manufacturing method: In a CVD apparatus (111), a reforming process is performed on a porous low dielectric constant film containing silicon, by heating a semiconductor wafer W by a heater, introducing 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS), and performing heat treatment without applying a high frequency voltage. Then, in the same CVD apparatus (111), an insulation... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070275569 - Methods and apparatus for e-beam treatment used to fabricate integrated circuit devices: One embodiment of the present invention is a method for fabricating a dielectric film, comprising chemical vapor depositing a dielectric film, and curing the dielectric film, wherein the dielectric film comprises silicon and carbon, and the chemical vapor depositing utilizes a precursor comprising one or more organo-silicon compounds and one... Agent: Patterson & Sheridan, LLP

20070275570 - Heat treatment apparatus: A heat treatment device where intervals between substrates supported by a supporter is reduced so that the number of substrates to be treated can be increased. A heat treatment device has a reaction furnace for treating substrates and a supporter for supporting the substrates in plural stages in the reaction... Agent: Oliff & Berridge, PLC

20070269907 - Novel conductor layout technique to reduce stress-induced void formations: A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the... Agent: Tung & Associates Randy W. Tung

20070269908 - Method for in-line controlling hybrid chemical mechanical polishing process: A hybrid CMP system having a first platen and a second platen is provided. Two types of polish pads are mounted on the first platen and second platen. A lot of pattern wafers is prepared. Each pattern wafer has patterned features, and a first dielectric layer is disposed over a... Agent: North America Intellectual Property Corporation

20070269911 - Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in: Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inserted into memory-module burn-in boards and placed into a burn-in oven. The memory... Agent: Stuart T Auvinen

20070269912 - In line test circuit and method for determining interconnect electrical properties and integerated circuit incorporating the same: A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and... Agent: Texas Instruments Incorporated

20070269913 - Method of fabricating light emitting diode: Disclosed herein is a method of fabricating a light emitting diode. The method comprises preparing a substrate, forming a lower semiconductor layer, an active layer and an upper semiconductor layer on the substrate, forming a photoresist pattern over the upper semiconductor layer such that a sidewall of the photoresist pattern... Agent: Marger Johnson & Mccollom, P.C.

20070269914 - Apparatus for aligning microchips on substrate and method for the same: An apparatus for aligning microelements on a substrate and a method for the same are provided. The steps of the method include providing a substrate, forming a protruding structure on the substrate, providing a microelement, forming a microdroplet on the protruding structure, and forcing the microelement to contact the microdroplet.... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070269915 - Led devices incorporating moisture-resistant seals and having ceramic substrates: A New Moisture-Resistant LED Device with Ceramic Substrate is disclosed. The Moisture-Resistant LED Device with Ceramic Substrate includes a ceramic substrate having a concave cavity, a light emitting diode (“LED”) in the concave cavity, a filler body over the LED, and a window sealed at an interface with the ceramic... Agent: Kathy Manke Avago Technologies Limited

20070269916 - Organic light emitting diode display and manufacturing method: An organic light emitting diode (OLED) display includes a substrate, a first electrode disposed on the substrate, a second electrode facing the first electrode, an emission layer disposed between the first electrode and the second electrode, and a hole transport layer disposed between the first electrode and the emission layer.... Agent: Macpherson Kwok Chen & Heid LLP

20070269921 - Method and apparatus for microjoining dissimilar materials: Disclosed are apparatus and methods that provide for electrical contacts in a substrate. For example, the apparatus may comprise a trench formed in a substrate, with an electrical contact pad formed on interior walls of the trench that comprises a narrowed opening. A conductive wire is squeezed into the trench... Agent: Law Offices Of Kenneth W. Float

20070269920 - Method of making dimple structure for prevention of mems device stiction: A MEMS device having a proof mass resiliently mounted above a substrate has projections formed on adjacent surfaces of the mass and substrate. The device is formed by creating a plurality of holes in the upper layer. A substance suitable for removing the intermediate layer without substantially removing the upper... Agent: Honeywell International Inc.

20070269923 - Semiconductor electrode containing phosphate and solar cell using the same: M

20070269924 - Patterning nanowires on surfaces for fabricating nanoscale electronic devices: contacting the surface of the substrate with a suspension of nanowires in a liquid medium to enable at least a portion of the applied nanowires to bind to at least a portion of the surface of the substrate covered with (C1) and/or not covered with (C2).... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070269909 - Method for processing an integrated circuit: Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The... Agent: N. Kenneth Burraston Kirton & Mcconkie

20070269910 - Wafer tilt detection apparatus and method: An exemplary embodiment providing one or more improvements includes a wafer tilt detection apparatus for use with a wafer processing or manufacturing device that applies a process to the wafer and which utilizes an endpoint signal for determining control of the process applied to the wafer. The wafer tilt apparatus... Agent: Pritzkau Patent Group, LLC

20070269917 - Electronic devices having a layer overlying an edge of a different layer and a process for forming the same: An electronic device includes a radiation-emitting component, a radiation-responsive component, or a combination thereof. In one embodiment, the electronic device includes a substrate and a first structure overlying the substrate. The electronic device also includes a second structure that includes a first layer, wherein the first layer has a first... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070269918 - Method of manufacturing nitride-based semiconductor light emitting device: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having an improved structure in which optical extraction efficiency is improved. The method of manufacturing a nitride-based semiconductor light-emitting device including an n-doped semiconductor layer, an active layer, a p-doped semiconductor layer, an n-electrode and a p-electrode includes: forming... Agent: Cantor Colburn, LLP

20070269919 - Controlling overspray coating in semiconductor devices: A manufacturing method, in which two device bars are bonded prior to facet coating to form a stacked bar pair. In one embodiment, each of the device bars has a p-side and an n-side, each side having a plurality of bonding pads, with at least some bonding pads located at... Agent: Mendelsohn & Associates, P.C.

20070269922 - Fingerprint detection device and method of its manufacture, and apparatus for forming a protective film: A fingerprint detection device has a fingerprint sensor chip and a diamond-like carbon (DLC) film covering the outermost surface of the sensor chip. The DLC film provides sufficient strength and enhanced electrostatic discharge withstand voltage to the fingerprint sensor chip. Thus, the DLC film protects the fingerprint sensor chip without... Agent: Robert J. Depke Lewis T. Steadman

20070269926 - Method and apparatus for forming an electrical connection to a semiconductor substrate: A device (100) may use one or more conductive elements (112) to electrically couple a substrate (116) and a cap (114). In one embodiment, an acceleration sense element may be formed on the substrate (116), and the cap (114) may be used to provide hermetic protection to the acceleration sense... Agent: Freescale Semiconductor, Inc. Law Department

20070269925 - Process for preparing a semiconductor light-emitting device for mounting: A process for preparing a semiconductor light-emitting device for mounting is disclosed. The light-emitting device has a mounting face for mounting to a sub-mount. The process involves treating at least one surface of the light-emitting device other than the mounting face to lower a surface energy of the at least... Agent: Patent Law Group LLP

20070269927 - Method for producing an optoelectronic device with patterned-metallized package body and method for the patterned metalization of a plastic-containing body: A method for patterned metallization of a plastic-containing body, which comprises the steps of producing the body via a two-component injection-molding process with at least two plastics, one of which is non-metallizable, and metallizing the body in such a way that a metallized region and a non-metallized region are formed,... Agent: Cohen, Pontani, Lieberman & Pavane

20070269929 - Method of reducing stress on a semiconductor die with a distributed plating pattern: A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may... Agent: Vierra Magen/sandisk Corporation

20070269930 - Methodology to control underfill fillet size, flow-out and bleed in flip chips (fc), chip scale packages (csp) and ball grid arrays (bga): In a method and system for underfilling a gap (140) disposed between a substrate (120) and a die (110), a selective surface (152) of the substrate (120) is treated by a plasma source. A matching surface (154) of the die (110) may be treated by the plasma source. The treating... Agent: Texas Instruments Incorporated

20070269928 - Temporary chip attach using injection molded solder: An improved method for performing an improved Temporary Chip Attach utilizing an Injection Molded Solder (IMS) process to allow efficient testing of die for creating a Known Good Die Bank. The IMS is applied to the testing substrate to form a column on the substrate. The die to be tested... Agent: International Business Machines Corporation Dept. 18g

20070269931 - Wafer level package and method of fabricating the same: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the... Agent: Marger Johnson & Mccollom, P.C.

20070269932 - Semiconductor device having post-mold nickel/palladium/gold plated leads: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The... Agent: Texas Instruments Incorporated

20070269933 - Integrated circuit encapsulation and method therefor: A device (12) may have a pressure sensitive portion (17) which is protected from corrosion by a pressure transmitting material (20). Pressure transmitting material (20) may also be used to transmit pressure to pressure sensitive portion (17). A masking material (22) may be used to define an opening (26) in... Agent: Freescale Semiconductor, Inc. Law Department

20070269934 - System and method for providing access to an encapsulated device: A method for providing access to a feature on a device wafer, and located outside an encapsulation region is described. The method includes forming a cavity in the lid wafer, aligning the lid wafer with the device wafer so that the cavity is located substantially above the feature, and removing... Agent: Jaquelin K. Spong

20070269935 - Fabrication of conductive micro traces using a deform and selective removal process: In a method of forming micro traces, stamping techniques are employed to define a target pattern of the micro traces. The stamping is applied to electrically conductive material and may be limited to pressure, but a thermal stamping approach may be utilized. Following the stamping, a portion of the conductive... Agent: Terry Mchugh Law Offices Of Terry Mchugh

20070269936 - Method of manufacturing lcd apparatus by using halftone exposure method: The present invention discloses a method of manufacturing a super large wide-angle super high-speed response LCD apparatus by using a photolithographic process for three times. The invention adopts a halftone exposure technology and a nitrogen ion doped technology to form a gate electrode, a common electrode, a pixel electrode and... Agent: Schmeiser, Olsen & Watts

20070269938 - Stacked film patterning method and gate electrode forming method: A stacked film patterning method is provided which is capable of reliably removing residual substances remaining after etching of a metal film, improving etching uniformity of a silicon film, and preventing an occurrence of etching residues. A micro-crystal film and a chromium film are sequentially formed on an insulating film... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20070269937 - Thin-film transistor and fabrication method thereof: A fabrication method of a TFT includes successively forming four thin films containing a first conductive layer, an insulation layer, a semiconductor layer, and a second conductive layer on a substrate, performing a first PEP process to pattern the four thin films for forming a semiconductor island and a gate... Agent: North America Intellectual Property Corporation

20070269939 - Flat panel display and method of fabricating the same: Disclosed is a flat panel display which comprises a substrate; a gate line formed on the substrate along a predetermined direction; and a gate electrode electrically connected to the gate line, and having a sheet resistance different from the gate line. With this configuration, a wiring resistance of the gate... Agent: H.c. Park & Associates, PLC

20070269940 - Thin film transistor and fabrication method thereof: A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at... Agent: J.c. Patents

20070269941 - Method of forming semiconductor device having a dopant-doped region: There is provided a method of forming a semiconductor device including a dopant-doped region. Lattice defect inducing element ions are implanted to a semiconductor channel layer to form a lattice defect region. After dopants are implanted to the lattice defect region, an annealing process is performed to form the dopant-doped... Agent: Mills & Onello LLP

20070269942 - Dual stress liner: A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second... Agent: International Business Machines Corporation Dept. 18g

20070269943 - Non-volatile memory and method of fabricating the same: A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner... Agent: J.c. Patents, Inc.

20070269944 - Cmos image sensor: A pixel of a complementary metal oxide semiconductor (CMOS) image sensor includes a plurality of photodiodes for sensing light to thereby generate photoelectric charges in different regions; a plurality of transfer transistors for transferring photoelectric charges of corresponding photodiodes in response to a first control signal; a floating diffusion region... Agent: Blakely Sokoloff Taylor & Zafman

20070269945 - Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator cmos devices: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs... Agent: Scully, Scott, Murphy & Presser, P.C.

20070269946 - Dynamic random access memory and fabrication method thereof: A dynamic random access memory including a substrate, an isolation structure, two transistors, two trench capacitors and two passing gates is provided. The isolation structure, including a first isolation structure and a second isolation structure, is disposed in the substrate. The second isolation structure is disposed in the substrate above... Agent: J.c. Patents, Inc.

20070269947 - Method for manufacturing nand flash memory: A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer,... Agent: J.c. Patents, Inc.

20070269948 - Non-volatile memory array and method of fabricating the same: A two-bits-per-cell flash memory cell is based on a localized trapping storage mechanism. The memory cell may be programmed via a hot hole injection mechanism and erased via a Fowler-Nordheim electron tunneling mechanism. The memory cells are arranged according to a virtual-ground wiring scheme. Gate structures of the memory cells... Agent: Edell, Shapiro & Finnan, LLC

20070269949 - Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least... Agent: Mcdermott Will & Emery LLP

20070269950 - Double gate isolation: A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a buried oxide (BOX) layer on a substrate. Independent first and second... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070269951 - Low stress sacrificial cap layer: A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300,... Agent: Texas Instruments Incorporated

20070269952 - Method of fabricating a transistor structure: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming... Agent: Ishimaru & Zahrt LLP

20070269953 - Method for the production of a bipolar transistor comprising an improved base terminal: For the production of an improved bipolar transistor comprising a low-resistance base terminal, a dielectric layer is deposited over the semiconductor substrate and is highly doped via an implantation mask. In a subsequent controlled thermal step, the dopant is then indiffused into the semiconductor substrate from the dielectric layer serving... Agent: Cohen, Pontani, Lieberman & Pavane

20070269954 - Semiconductor device including a capacitor having reduced leakage current: A process for forming bottom and top electrodes of a capacitor uses a source gas including tungsten nitride carbide (WNC) which contains no chlorine, to form an amorphous electrode film. This prevents the amorphous capacitor insulation from being crystallized, and also prevents addition of chlorine into the capacitor insulation film,... Agent: Mcginn Intellectual Property Law Group, PLLC

20070269955 - Semiconductor device and method for manufacturing same: A semiconductor device is provided which has a capacitor insulating film made up of zirconium aliminate being an amorphous film obtained by having crystalline dielectric contain amorphous aluminum oxide and having its composition of AlXZr(1-X)OY (0.05≦X≦0.3), hereby being capable of preventing, in a process of forming a capacitor of MIM... Agent: Sughrue Mion, PLLC

20070269956 - Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures: Embodiments of the invention include apparatuses and methods relating to air gap interconnect structures having interconnects protected by a sealant. In various embodiments, the sealant includes alumina or silicon nitride. In some embodiments, the interconnect structures include cobalt alloy liners and cobalt shunts to encase a conductive material.... Agent: Intel Corporation C/o Intellevate, LLC

20070269957 - Methods of fabricating semiconductor devices having isolation regions formed from annealed oxygen ion implanted regions: Methods of fabricating a semiconductor device include forming a mask pattern on a semiconductor substrate and which exposes defined regions of the semiconductor substrate. Oxygen ions are implanted into the defined regions of the semiconductor substrate using the mask pattern as an ion implantation mask. The oxygen ion implanted regions... Agent: Myers Bigel Sibley & Sajovec

20070269958 - Methods for filling trenches in a semiconductor material: Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the first dielectric layer is etched to create a recess in... Agent: Fletcher Yoder (micron Technology, Inc.)

20070269959 - Method of aligning mask layers to buried features: A method for fabricating microchip devices is provided. The method includes the steps of providing a first planar substrate, locating at least one first alignment feature in the surface of the first planar substrate, and bonding a second substrate to the surface of the first planar substrate. The method further... Agent: Delphi Technologies, Inc.

20070269960 - Fabrication of substrates with a useful layer of monocrystalline semiconductor material: A method for fabricating a semiconductor substrate. In an embodiment, this method includes the steps of transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal... Agent: Winston & Strawn LLP Patent Department

20070269961 - Semiconductor wafer and method for making the same: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT... Agent: North America Intellectual Property Corporation

20070269962 - Surface protection film peeling method and surface protection film peeling device: A film peeling device for peeling a film (11) adhered to a front surface of a wafer (20), on the back surface of which a dicing tape (3) is adhered, the wafer is integrated with a mount frame (36) into one body, comprises: a movable table (31), which can be... Agent: Christie, Parker & Hale, LLP

20070269964 - Semiconductor-on-diamond devices and associated methods: Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer... Agent: Thorpe North & Western, LLP.

20070269963 - Strained hot (hybrid orientation technology) mosfets: A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide... Agent: Schmeiser, Olsen & Watts

20070269965 - Indium nitride layer production: The invention relates to a structure usable in electronic, optical or optoelectronic engineering which comprises a substantially crystalline layer made of an alloy consisting of at least one element of the column II of the periodic elements system and/or at least one element of the column IV of the periodic... Agent: Foley And Lardner LLP Suite 500

20070269966 - Methods and apparatus for fabricating semiconductor devices having reduced implant contamination and related devices: A method of fabricating a semiconductor device includes selecting an element for implanting into a substrate. The element has at least a first isotope and a second isotope. At least one implant contaminant is identified as having a particle weight that is substantially identical to an atomic weight of the... Agent: Myers Bigel Sibley & Sajovec

20070269967 - Manufacturing method of semiconductor device: A method for manufacturing a semiconductor device is provided, which is capable of solving a junction leakage problem. According to the manufacturing method of the present invention, arsenic is implanted to reduce the series resistance after formation of a contact hole. A sidewall film is then formed on the side... Agent: Mcginn Intellectual Property Law Group, PLLC

20070269968 - Semiconductor devices including self aligned refractory contacts and methods of fabricating the same: Methods of forming semiconductor devices are provided by forming a semiconductor layer on a semiconductor substrate. A mask is formed on the semiconductor layer. Ions having a first conductivity type are implanted into the semiconductor layer according to the mask to form implanted regions on the semiconductor layer. Metal layers... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070269969 - Semiconductor structure pattern formation: Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an... Agent: Freescale Semiconductor, Inc. Law Department

20070269970 - Structure and method for forming cmos devices with intrinsically stressed silicide using silicon nitride cap: The present invention provides a semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first... Agent: Scully, Scott, Murphy & Presser, P.C.

20070269971 - Method for manufacturing semiconductor device: A method for forming a semiconductor device includes forming a bit line contact region with a line pattern and then performing a process to form a bit line so that a multi-layered bit line contact is expended, thereby preventing a short between bit line contact plugs and improving the process... Agent: Townsend And Townsend And Crew, LLP

20070269972 - Method of manufacturing a semiconductor device: Provided is a method of manufacturing a semiconductor device having an ONO film composed of a bottom silicon oxide film, a silicon nitride film and a top silicon oxide film over a substrate. The top silicon oxide film of the ONO film is formed in the following manner. A silicon... Agent: Miles & Stockbridge PC

20070269973 - Method of providing solder bumps using reflow in a forming gas atmosphere: A method of providing electrically conductive bumps on electrode pads of a microelectronic substrate. The method includes: providing a microelectronic substrate including electrode pads thereon; disposing a mask onto the substrate such that openings defined in the mask are placed in registration with the electrode pads; providing solder portions onto... Agent: Intel Corporation C/o Intellevate, LLC

20070269974 - Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon layer. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact... Agent: Myers Bigel Sibley & Sajovec

20070269976 - Method of manufacturing semiconductor device: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070269975 - System and method for removal of photoresist and stop layer following contact dielectric etch: In device fabrication, a photoresist layer is formed on an insulation layer, above a stop layer that is supported directly on an active device structure. Holes are needed through the insulation layer to reach a contact arrangement, defined by the active device structure in which each contact is covered by... Agent: Pritzkau Patent Group, LLC

20070269977 - Method of forming a multilayer wiring by the use of copper damascene technique: In a formation method of a copper damascene multilayer wiring in a semiconductor integrated circuit device, after performing an oxidation process on a surface of copper, a heating process of 300° C. to 400° C. is performed in a reducing gas atmosphere, or a plasma annealing process is performed in... Agent: Young & Thompson

20070269978 - Process for improving copper line cap formation: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a... Agent: Slater & Matsil, L.L.P.

20070269979 - Method of forming a pattern and method of manufacturing a semiconductor device using the same: A method of forming a tungsten pattern includes forming a preliminary tungsten pattern on a substrate and partially removing a surface of the preliminary tungsten pattern using deionized water to form the tungsten pattern.... Agent: Lee & Morse, P.C.

20070269981 - Electroless treatment of noble metal barrier and adhesion layer: A method of forming an EL-Cu enhanced noble metal layer begins with providing a semiconductor substrate in a reaction chamber, wherein the semiconductor substrate includes a trench etched into a dielectric layer. Next, an organometallic precursor containing a noble metal and a reactive gas are pulsed into the reaction chamber... Agent: Intel Corporation C/o Intellevate, LLC

20070269980 - Methods for reducing contamination of semiconductor devices and materials during wafer processing: Methods of processing a semiconductor structure including a metal layer in the presence of organic material include flowing an aqueous mixture including an oxidizing agent over the semiconductor structure during processing of the semiconductor structure. Processing the semiconductor structure may include sawing the semiconductor structure and/or scrubbing the semiconductor structure... Agent: Myers Bigel Sibley & Sajovec

20070269982 - Method and device to vary growth rate of thin films over semiconductor structures: Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use of a reaction inhibitor that selectively varies a deposition rate along a surface. One specific method includes atomic layer deposition. One method shown provides high step... Agent: Schwegman, Lundberg & Woessner, P.A.

20070269984 - Method of manufacturing semiconductor device, method of manufacturing semiconductor substrate and semiconductor substrate: A method of manufacturing a semiconductor device and a semiconductor substrate including: a step of subjecting the semiconductor substrate to a wet process by relatively moving a process liquid and the semiconductor substrate during the wet process in an environment where there is not a static electricity removing effect with... Agent: Foley And Lardner LLP Suite 500

20070269983 - Ald apparatus and method: Improved apparatus and method for SMFD ALD include a method designed to enhance chemical utilization as well as an apparatus that implements lower conductance out of SMFD-ALD process chamber while maintaining full compatibility with standard wafer transport. Improved SMFD source apparatuses (700, 700′, 700″) and methods from volatile and non-volatile... Agent: Patton Boggs LLP

20070269985 - Two-step chemical mechanical polishing process: A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to... Agent: Baker & Mckenzie LLP Patent Department

20070269986 - Method, apparatus and system for use in processing wafers: The present embodiment provides for methods and systems for use in processing objects such as wafers, including polishing and/or grinding wafers. Some embodiments provide systems that include a front-end module and a processing module. The front end module couples with a storage device that stores objects for processing. The front-end... Agent: Sinsheimer Juhnke Lebens & Mcivor, LLP

20070269987 - Polishing liquid for cmp process and polishing method: An abrasive liquid for CMP process characterized by comprising an abrasive material, an aqueous solvent and an addition agent, and containing abrasive particles having a particle diameter of 20 to 80 nm by 15 weight % or more on the basis of the weight of the abrasive liquid; and a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070269988 - Method for forming contact opening: The present invention relates to a method for forming a contact opening. First, a substrate having at least a dielectric layer formed thereon is provided. Then, a photoresist layer having a first opening is formed on the dielectric layer. A plasma etching operation is performed to form a second opening... Agent: Jianq Chyun Intellectual Property Office

20070269989 - Inspection method of compound semiconductor substrate, compound semiconductor substrate, surface treatment method of compound semiconductor substrate, and method of producing compound semiconductor crystal: There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In... Agent: Mcdermott Will & Emery LLP

20070269990 - Method of removing ion implanted photoresist: A method of removing an ion implanted photoresist comprises performing first cleaning a semiconductor substrate having the ion implanted photoresist using hot deionized water to which a megasonic process is applied, first rinsing the semiconductor substrate using cold deionized water, drying the semiconductor substrate, removing the ion implanted photoresist, and... Agent: Marshall, Gerstein & Borun LLP

20070269991 - Semiconductor nanocrystal-metal complex and method of preparing the same: Disclosed herein are a semiconductor nanocrystal-metal complex and a method for preparing the same. The semiconductor nanocrystal-metal complex includes a semiconductor nanocrystal and one or more metal particles bound to the semiconductor nanocrystal. The semiconductor nanocrystal-metal complex exhibits excellent photocurrent characteristics and an improved binding force, in addition to the... Agent: Cantor Colburn, LLP

20070269992 - Compressive nitride film and method of manufacturing thereof: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane,... Agent: International Business Machines Corporation Dept. 18g

20070269993 - Method for forming poly-silicon film: A method for forming a poly-silicon film, using sequential lateral solidification (SLS) by laser irradiation through an optical device to pattern the laser beam and provide a periodic energy profile on the edges of transparent regions so as to widen the poly-silicon grains and achieve grain size uniformity. The optical... Agent: Birch Stewart Kolasch & Birch

20070269994 - Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semicondu: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate... Agent: Wells St. John P.s.

20070264728 - Manufacturing method of tunnel magnetoresistive effect element, manufacturing method of thin-film magnetic head, and manufacturing method of magnetic memory: A manufacturing method of a TMR element having a magnetization fixed layer, a magnetization free layer and a tunnel barrier layer sandwiched between the magnetization fixed layer and the magnetization free layer. A fabricating process of the tunnel barrier layer includes a step of depositing a first metallic material film... Agent: Buchanan, Ingersoll & Rooney PC

20070264733 - Method of manufacturing vertical gallium nitride-based light emitting diode: A method of manufacturing a vertical GaN-based LED comprises preparing an n-type GaN substrate; sequentially forming an active layer and a p-type nitride semiconductor layer on the n-type GaN substrate through an epitaxial growth method; forming a p-electrode on the p-type nitride semiconductor layer; wet-etching the lower surface of the... Agent: Lowe Hauptman Ham & Berner, LLP

20070264735 - Array substrate and display panel: A manufacturing method for an array substrate, comprising forming a gate metal on a base substrate, patterning the gate metal to form a gate part having a gate electrode, a gate line and a gate pad. Then, a gate insulating layer, an active layer and a data metal are sequentially... Agent: Macpherson Kwok Chen & Heid LLP

20070264731 - Method for local hot spot fixing: Efficient and cost-effective systems and methods for detecting and correcting hot spots of semiconductor devices are disclosed. In one aspect, a method includes providing an input file having a device layout; performing a hot spot detection on the input file; and then modifying the device layout based on the hot... Agent: Haynes And Boone, LLP

20070264729 - Method for reducing within chip device parameter variations: A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test... Agent: Schmeiser, Olsen & Watts

20070264730 - Redundant acknowledgment in loopback entry: Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example the acknowledgment is performed by initiating loopback communications from a first agent to a second agent, sending a packet including a redundant acknowledgment sequence from the first agent to the second agent, receiving... Agent: Blakely Sokoloff Taylor & Zafman

20070264732 - Three-dimensional, ultrasonic transducer arrays, methods of making ultrasonic transducer arrays, and devices including ultrasonic transducer arrays: Medical imaging devices may comprise an array of ultrasonic transducer elements. Each transducer element may comprise a substrate having a doped surface creating a highly conducting surface layer, a layer of thermal oxide on the substrate, a layer of silicon nitride on the layer of thermal oxide, a layer of... Agent: Rissman Jobse Hendricks & Oliverio, LLP

20070264734 - Solid-state laser device and method for manufacturing wavelength conversion optical member: A solid-state laser device, comprising a wavelength conversion optical member, wherein the wavelength conversion optical member comprises a laser crystal and a wavelength conversion element cemented together, and a first dielectric reflection film poorly reflective to a fundamental wave and highly reflective to a wavelength conversion light is formed on... Agent: Nields & Lemack

20070264736 - Array substrates for use in liquid crystal displays and fabrication methods thereof: Array substrates for use in TFT-LCDs and fabrication methods thereof. A transparent conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer and a sacrificial layer are sequentially formed on a substrate. With a first photomask, a photoresist layer with various thicknesses is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070264737 - Dual layer color-center patterned light source: A thin layer of ionic crystal is grown on a substrate. The crystal could be any type of ionic crystal, such as sodium chloride or potassium chloride. The crystal is a pure form of the chosen compound and may contain contaminants which would shift the wavelength of created color centers.... Agent: Plevy, Howard & Darcy, P.C.

20070264738 - Monolithic semiconductor laser and method of manufacturing the same: A monolithic semiconductor laser having plural semiconductor lasers having different emission wavelengths from each other, including: a semiconductor substrate; a first double hetero-structure formed within a first area on the semiconductor substrate and having first clad layers disposed above and below a first active layer; and a second double hetero-structure... Agent: Mcdermott Will & Emery LLP

20070264739 - Light emitting device using a thermally activated coating and method of manufacturing: An improved method for encapsulating LEDs in a polymer coat is described. A substrate houses an LED, and a polymer layer is brought into proximity with the substrate and LED. The polymer layer is melted over the substrate, encapsulating the LED onto the substrate.... Agent: Kathy Manke Avago Technologies Limited

20070264740 - Method for fabricating a component having an electrical contact region: A method for fabricating a component having an electrical contact region on an n-conducting AlGaInP-based or AlGaInAs-based outer layer of an epitaxially grown semiconductor layer sequence, in which electrical contact material, which includes Au and at least one dopant, is applied and the outer layer is then annealed. The dopant... Agent: Cohen, Pontani, Lieberman & Pavane

20070264741 - Methods for making fixed parallel plate mems capacitor microsensors and microsensor arrays: A fixed parallel plate micro-mechanical systems (MEMS) based sensor is fabricated to allow a dissolved dielectric to flow through a porous top plate, coming to rest on a bottom plate. A post-deposition bake ensures further purity and uniformity of the dielectric layer. In one embodiment the dielectric is a polymer.... Agent: Biotechnology Law Group C/o Portfolioip

20070264742 - Glass substrate and capacitance-type pressure sensor using the same: A glass substrate has a pair of main surfaces opposite to each other. Two island-shaped portions made of silicon are buried in the glass substrate. The tow island-shaped portions are exposed from the two main surfaces of the glass substrate, respectively. An electrode is formed on one main surface of... Agent: Beyer Weaver LLP

20070264743 - Semiconductor input control device: A force input control device suitable for high-volume applications such as cell phones, portable gaming devices and other handheld electronic devices is disclosed. The device comprises a force sensor die formed within semiconductor substrate and containing a force sensor providing electrical output signal in response to applied external force, connection... Agent: Walt Froloff

20070264744 - Optical bench, slim optical pickup employing the same and method of manufacturing the optical bench: An optical bench is provided, as are a thin optical pickup that employs the optical bench, and a method of manufacturing the optical bench. The optical bench includes a light source for generating light for recording and reproducing information to and from an optical disc, a light source stand on... Agent: Sughrue Mion, PLLC

20070264745 - Image sensor device and method of manufacturing the same: An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in... Agent: Harness, Dickey & Pierce, P.L.C

20070264746 - Back junction solar cell and process for producing the same: The present invention can finely arrange p+-type diffusion layers and n+-type diffusion layers. A p+-type diffusion layer 2 and an n+-type diffusion layer 3 are simultaneously formed on a back surface 1a of a semiconductor substrate 1 in a state that the p+-type diffusion layer 2 and the n+-type diffusion... Agent: Greenblum & Bernstein, P.L.C

20070264748 - Aligned polymers for an organic tft: A method for forming an electronic device having a semiconducting active layer comprising a polymer, the method comprising aligning the chains of the polymer parallel to each other by bringing the polymer into a liquid-crystalline phase.... Agent: Sughrue Mion, PLLC

20070264747 - Patterning process and method of manufacturing organic thin film transistor using the same: A patterning process is provided. The patterning process includes the following steps. First, a substrate is provided. Then, a patterned self-assembled monolayer (SAM) is formed on the substrate. Afterwards, an organic material layer is formed over the substrate to cover the self-assembled monolayer. Thereafter, a portion of the organic material... Agent: Jianq Chyun Intellectual Property Office

20070264750 - Method of manufacturing the substrate for packaging integrated circuits: A method of manufacturing a substrate for packaging ICs is disclosed, which coats a thin conductive layer on the bottom surface of the laminated circuit board, for electrically connecting the pad and the circuit pattern formed on the bottom surface after one line photolithography/etching step. The pad formed on the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070264749 - Multi-post structures: Micromechanical devices having complex multilayer structures and techniques for forming the devices are described.... Agent: Fish & Richardson P.C.

20070264751 - Super high density module with integrated wafer level packages: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment,... Agent: Whyte Hirschboeck Dudek S.c.

20070264752 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device flip-chip bonds electrode terminals of a substrate and a semiconductor chip together by solid-phase diffusion and underfills a gap between the substrate and the semiconductor chip with a thermosetting resin without the bonds between the terminals breaking due to heat in an underfill... Agent: Kratz, Quintos & Hanson, LLP

20070264753 - Semiconductor package and method for manufacturing the same: A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically connected to the functional element via the... Agent: Sughrue Mion, PLLC

20070264754 - Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion: A semiconductor device includes metal foil to which a ground potential is applied, at a semiconductor constructing body provided on the metal foil and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. An insulating layer is provided around the semiconductor constructing body... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070264755 - Method of manufacturing printed circuit board for fine circuit formation: Disclosed is a method of manufacturing a printed circuit board for fine circuit formation, in which an unnecessary metal layer formed on the upper portion of a circuit pattern is removed through mechanical polishing and then chemical etching. In place of expensive chemical mechanical polishing, in the method of the... Agent: Staas & Halsey LLP

20070264756 - Method and apparatus for manufacture and inspection of semiconductor device: A semiconductor device is manufactured in such a way that a semiconductor chip connected with leads whose internal ends are interconnected with bonding wires are completely sealed and enclosed in a resin corresponding to a package while external ends of leads are exposed from the surface of the package. In... Agent: Dickstein Shapiro LLP

20070264757 - Micro-package, multi-stack micro-package, and manufacturing method therefor: A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas... Agent: Sughrue Mion, PLLC

20070264758 - Systems and arrangements to interconnect components of a semiconductor device: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070264759 - Manufacturing semiconductor device and method of manufacturing electronic apparatus: A method for manufacturing a semiconductor device, includes: forming an insulating film on a substrate; selectively removing the insulating film, so as to form a groove including a first groove area having a first depth and a second groove area having a second depth, the second depth being smaller than... Agent: Oliff & Berridge, PLC

20070264760 - Method of forming a memory cell array: A semiconductor substrate is provided. A plurality of first conductive lines is formed, followed by forming a plurality of second conductive lines above the first conductive lines. Memory cells are at least partially formed in the semiconductor substrate. Thereafter, at least one of the second conductive lines is removed, thereby... Agent: Edell, Shapiro & Finnan, LLC

20070264761 - Method of forming a gate insulator and thin film transistor incorporating the same: Disclosed herein is a method of manufacturing a gate insulator and a thin film transistor (“TFT”) incorporating the gate insulator, including forming an oxygen-containing, conductive gate on a substrate; forming a gate insulator material layer on the substrate so as to cover the gate; and applying a heat treatment so... Agent: Cantor Colburn, LLP

20070264762 - Semiconductor-on-insulator sram configured using partially-depleted and fully-depleted transistors: A static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to a right bit node. A second inverter has an input coupled to the right bit node and an output coupled to the left right bit node. A first... Agent: Slater & Matsil, L.L.P.

20070264763 - Method for the production of a semiconductor component having a metallic gate electrode disposed in a double-recess structure: The production of a microelectronic component, particularly a pHEMT, having a T-shaped gate electrode in a double-recess structure uses a production method for self-adjusting alignment of the two recesses of the double-recess structure and of the gate foot of the gate electrode.... Agent: William Collard Collard & Roe, P.C.

20070264764 - Formation of carbon and semiconductor nanomaterials using molecular assemblies: The invention is directed to a method of forming carbon nanomaterials or semiconductor nanomaterials. The method comprises providing a substrate and attaching a molecular precursor to the substrate. The molecular precursor includes a surface binding group for attachment to the substrate and a binding group for attachment of metal-containing species.... Agent: Connolly Bove Lodge & Hutz LLP

20070264766 - Nos non-volatile memory cell and method of operating the same: A nitride/oxide/semiconductor (NOS) non-volatile memory cell formed in an n-well, having no control gate and capable of storing two bits is provided. The NOS non-volatile memory cell includes at least one NO (nitride layer, oxide layer) storage gate capable of storing one bit of data in the nitride layer adjacent... Agent: Jianq Chyun Intellectual Property Office

20070264767 - Enhanced pmos via transverse stress: In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel... Agent: Texas Instruments Incorporated

20070264765 - Method of manufacturing metal oxide semiconductor and complementary metal oxide semiconductor: A method of manufacturing a metal oxide semiconductor is provided. The method includes forming an offset spacer and a disposable spacer around the offset spacer. Then, forming a plurality of epitaxial layers outside the disposable spacer and removing the disposable spacer. In addition, the method includes forming a plurality of... Agent: North America Intellectual Property Corporation

20070264768 - Method for designing and manufacturing a pmos device with drain junction breakdown point located for reduced drain breakdown voltage walk-in: A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far... Agent: Alfred A. Equitz Girard & Equitz LLP

20070264769 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and... Agent: F. Chau & Associates, LLC

20070264770 - Capacitor forming method: A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric... Agent: Townsend And Townsend And Crew, LLP

20070264772 - Method for fabricating recessed gate mos transistor device: A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the... Agent: North America Intellectual Property Corporation

20070264771 - Dual work function recessed access device and methods of forming: A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom... Agent: Trask Britt, P.C./ Micron Technology

20070264775 - Non-volatile memory device and method of manufacturing the same: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a... Agent: Marshall, Gerstein & Borun LLP

20070264774 - Method of manufacturing a flash memory device: A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070264773 - Methods of etching stacks having metal layers and hard mask layers: Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer disposed above the hard mask layer wherein the... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070264776 - Precision creation of inter-gates insulator: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the... Agent: Macpherson Kwok Chen & Heid LLP

20070264777 - Method for forming a floating gate using chemical mechanical planarization: An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical planarization to provide “stop on polysilicon” capabilities, allowing a thin nitride layer, or in the alternative no nitride layer, to be used and reducing the number of... Agent: Dickstein Shapiro LLP

20070264778 - Memory device with quantum dot and method for manufacturing the same: Provided is a memory device formed using quantum devices and a method for manufacturing the same. A memory device comprises a substrate; a source region and a drain region formed in the substrate so as to be separated from each other by a predetermined interval; a memory cell which is... Agent: Buchanan, Ingersoll & Rooney PC

20070264779 - Methods for forming floating gate memory structures: Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The... Agent: Macpherson Kwok Chen & Heid LLP

20070264780 - Method of fabricating a vertical nano-transistor: A method of fabricating a vertical nano-transistor by forming holes in a thin metal film to provide the gate region for forming the channel region, applying insulation material to the walls of the holes and to the upper and lower surface of the metal film, applying semiconductor material in the... Agent: Law Offices Of Karl Hormann

20070264781 - Method for the production of a semiconductor component having a metallic gate electrode disposed in a double-recess structure: A semiconductor component, particularly a pHEMT, having a T-shaped gate electrode deposited in a double-recess structure, is produced with a method with self-adjusting alignment of the recesses and of the T-shaped gate electrode.... Agent: William Collard Collard & Roe, P.C.

20070264782 - Method of making a mos-gated transistor with reduced miller capacitance: A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within... Agent: Townsend And Townsend And Crew, LLP

20070264783 - High performance stress-enhanced mosfets using si:c and sige epitaxial source/drain and method of manufacture: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of... Agent: Greenblum & Bernstein, P.L.C

20070264784 - Reduction of field edge thinning in peripheral devices: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the... Agent: Ropes & Gray LLP Patent Docketing 39/361

20070264785 - Method of forming high breakdown voltage low on-resistance lateral dmos transistor: A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is formed over the substrate. A second buried layer of the first conductivity type is formed in the first... Agent: Townsend And Townsend And Crew, LLP

20070264786 - Method of manufacturing metal oxide semiconductor transistor: A method of manufacturing a metal oxide semiconductor (MOS) transistor is provided. The method includes first providing a substrate and forming an MOS transistor on the substrate. Then, a self-aligned metal silicidation process is performed. Afterwards, an infrared radiation (IR) treatment is performed on the substrate in order to repair... Agent: Jianq Chyun Intellectual Property Office

20070264787 - Method to build self-aligned npn in advanced bicmos technology: The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using... Agent: Scully, Scott, Murphy & Presser, P.C.

20070264788 - Method to define a transistor gate of a dram and the transistor gate using same: A method to determine the predetermined location of a transistor gate of a dynamic random access memory (DRAM). A trench capacitor is respectively provided in a silicon substrate at the two sides of the gate, along the direction of a bit line. The method is to first form a patterned... Agent: Bacon & Thomas, PLLC

20070264791 - Method of gap-filling using amplitude modulation radiofrequency power and apparatus for the same: A method of filling a gap on a substrate comprises disposing the substrate, on which the gap is formed, on a susceptor in a chamber; applying a source power to the chamber to generate plasmas into the chamber; supplying a process gas into the chamber; filling a thin film into... Agent: Marger Johnson & Mccollom, P.C.

20070264790 - Method of manufacturing semiconductor device: A method of manufacturing semiconductor devices includes forming a trench in a predetermined region of a substrate. A first insulating layer and a second insulating layer are formed on a entire surface so that the trench is gap-filled. The first and second insulating layers are polished until a top surface... Agent: Townsend And Townsend And Crew, LLP

20070264789 - Semiconductor device having a device isolation trench: A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming... Agent: Townsend And Townsend And Crew, LLP

20070264792 - Method for producing deep trench structures: A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070264793 - Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers: In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is... Agent: Myers Bigel Sibley & Sajovec

20070264794 - Methods of forming trench isolation and methods of forming arrays of flash memory cells: This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is deposited and solidified within the isolation trenches to form a solidified dielectric within the isolation trenches. The dielectric comprises carbon and silicon, and can be considered as having... Agent: Wells St. John P.s.

20070264795 - Method and materials to control doping profile in integrated circuit substrate material: Methods and materials for silicon on insulator wafer production in which the doping concentration in a handle wafer is sufficiently high to inhibit dopant from diffusing from the bond wafer during or after bonding to the handle wafer.... Agent: Schneck & Schneck

20070264796 - Method for forming a semiconductor on insulator structure: A method of bonding a thin semiconductor film onto a rectangular substrate is disclosed. The method makes it possible to exfoliate rectangular semiconductor films from a round precursor semiconductor wafer, thereby providing for efficient tiling of the substrate with semiconductor film. The method includes the steps of creating a damage... Agent: Corning Incorporated

20070264797 - Method for producing semiconductor substrate: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having no oxide film wherein hydrogen ions are implanted into a wafer for active layer having no oxide film on its surface to form a hydrogen ion implanted layer,... Agent: Sughrue Mion, PLLC

20070264798 - Method and system for partially removing circuit patterns from a multi-project wafer: Disclosed are a method and a system for partially removing circuit patterns from a multi-project wafer. This method and this system can be used to provide a multi-project-wafer to a user without disclosing proprietary circuit information of other customers. At least one integrated circuit design of a user is identified... Agent: Haynes And Boone, LLP

20070264799 - Wafer laser processing method: A wafer laser processing method for forming a groove along streets in a wafer by moving the wafer at a predetermined feed rate while a laser beam whose focal spot is elliptic is applied along the streets formed on the wafer, comprising: a groove forming step for forming a groove... Agent: Smith, Gambrell & Russell

20070264800 - Method of degassing thin layer and method of manufacturing silicon thin film: A method of degassing a thin layer and a method of manufacturing a silicon thin film includes applying microwaves to a silicon thin film deposited on a substrate to induce a resonance of impurities of H2, Ar, He, Xe, O2, and the like present in the silicon thin film so... Agent: Cantor Colburn, LLP

20070264802 - Method for manufacturing nitride semiconductor laser element, and nitride semiconductor laser element: A method for manufacturing a nitride semiconductor laser element, equipped with a laminate that has a first conductivity type nitride semiconductor layer, an active layer, and a second conductivity type nitride semiconductor layer on a substrate, and constitutes a resonator, comprises the steps of: forming a first auxiliary groove having... Agent: GlobalIPCounselors, LLP

20070264803 - Semiconductor substrate, and semiconductor device and method of manufacturing the semiconductor device: In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of... Agent: Steptoe & Johnson LLP

20070264801 - Semiconductor buffer structures: Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon... Agent: Knobbe, Martens, Olsen & Bear LLP

20070264804 - Method and system for reducing charge damage in silicon-on-insulator technology: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between... Agent: Texas Instruments Incorporated

20070264805 - Integrated light emitting device and photodiode with ohmic contact: Optoelectronic device including integrated light emitting device and photodiode. The optoelectronic device includes a light emitting device such as a vertical cavity surface emitting laser (VCSEL) or resonant cavity light emitting diode (RCLED). A photodiode is also included in the optoelectronic device. Between the light emitting device and the photodiode... Agent: Workman Nydegger

20070264806 - Mask for sequential lateral solidification and method of performing sequential lateral solidification using the same: Embodiments of a mask for sequential lateral solidification are disclosed herein. In some embodiments, a mask of the present disclosure comprises a transmission region including a first slit column having a plurality of first slits separated from one another by a predetermined interval, and a second slit column having a... Agent: Macpherson Kwok Chen & Heid LLP

20070264807 - Cleaining process and operating process for a cvd reactor: The present invention relates to a process for cleaning the reaction chamber (12) of a CVD reactor, comprising the steps of heating the chamber walls to a suitable temperature and introducing a gas flow into the chamber, this cleaning process may be advantageously used within an operating process of a... Agent: Katten Muchin Rosenman LLP

20070264808 - Plasma doping method and method for fabricating semiconductor device using the same: A plasma doping method includes providing a doping source over a substrate. The doping source includes dopants that are to be injected into the substrate. At least two different bias voltages are applied to inject the dopants from the doping source to the substrate.... Agent: Townsend And Townsend And Crew, LLP

20070264809 - Process for manufacture of trench schottky: A trench-type Schottky semiconductor device and a method for fabricating the trench-type Schottky semiconductor device are disclosed. The method includes the steps of forming an epitaxial (EPI) layer atop a silicon substrate, forming a nitride layer atop the EPI layer, patterning a plurality of windows in the nitride layer into... Agent: Ostrolenk Faber Gerb & Soffen

20070264810 - Semiconductor devices and methods of forming the same: A semiconductor device and a method of manufacturing the same, including obtaining a semiconductor substrate, forming a device isolating layer having a depression part and a protrusion part in the semiconductor substrate, forming a gate insulating layer and a gate electrode on the semiconductor substrate, forming a spacer in communication... Agent: Lee & Morse, P.C.

20070264811 - Method for forming salicide in semiconductor device: Forming salicide in a semiconductor device includes the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard... Agent: Ladas & Parry LLP

20070264812 - High density chalcogenide memory cells: A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar... Agent: Stout, Uxa, Buyan & Mullins LLP

20070264813 - Process for producing a film carrier tape for mounting an electronic part: A film carrier tape for mounting an electronic part, comprising an insulating film, a wiring pattern formed on a surface of the insulating film and a solder resist layer formed on the wiring pattern except connecting lead portions of the wiring pattern, wherein the solder resist coating thickness at the... Agent: The Webb Law Firm, P.C.

20070264815 - Method for fabricating semiconductor device: The method of fabricating a semiconductor device according to the present invention is applied to a semiconductor device fabricated by forming a seed film in recesses formed in an interlayer film and forming a thick film embedded in the recesses by electrolytic plating using the seed film as an electrode.... Agent: Mcdermott Will & Emery LLP

20070264814 - Method for forming metal wiring line, method for manufacturing active matrix substrate, device, electro-optical device, and electronic apparatus: A method for forming a metal wiring line, comprises: (a) forming a bank including a first opening corresponding to a first film pattern and a second opening corresponding to a second film pattern that is coupled to the first film pattern and has a width narrower than a width of... Agent: Harness, Dickey & Pierce, P.L.C

20070264816 - Copper alloy layer for integrated circuit interconnects: A method for forming a metal interconnect comprises providing a dielectric layer on a substrate within a reaction chamber where the dielectric layer includes a trench, conformally depositing a barrier layer on the dielectric layer within the trench, conformally depositing a Cu—Al alloy layer on the barrier layer within the... Agent: Intel Corporation C/o Intellevate, LLC

20070264818 - Method for manufacturing semiconductor device including a landing pad: A process for manufacturing a semiconductor device includes the steps of: forming a metal plug in a contact hole of an isolation film; growing a tungsten film in self-alignment with the metal plug by using a selective CVD technique to form a landing pad on the metal plug and a... Agent: Sughrue Mion, PLLC

20070264817 - Via line barrier and etch stop structure: A semiconductor device and a method for making the semiconductor device having a barrier layer in a via hole region and a barrier layer in a via line region. The barrier layer in the via line region is initially thicker than the barrier layer in the via hole region, prior... Agent: Banner & Witcoff, Ltd.

20070264819 - Method of forming an electrical isolation associated with a wiring level on a semiconductor wafer: A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines... Agent: Slater & Matsil LLP

20070264820 - Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the... Agent: HorizonIPPte Ltd

20070264821 - Methods of forming a semiconductor device: A method of forming a semiconductor device may include forming a first conductive metal compound layer on a substrate using a metal organic chemical vapor deposition (MOCVD) process and/or forming a second conductive metal compound layer on the first conductive metal compound layer using a physical vapor deposition (PVD) process.... Agent: Harness, Dickey & Pierce, P.L.C

20070264822 - Peripheral processing method and method of manufacturing a semiconductor device: A peripheral processing method includes: by at least one of locally heating the periphery of a workpiece including a silicon-based substrate and selectively supplying reacting activation species to the periphery, allowing oxidation rate on the periphery to be higher than oxidation rate of native oxide film on a surface of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070264823 - Semiconductor device with sti structure and method of fabricating the same: A semiconductor device such as a flash memory includes a semiconductor substrate having a surface, and a plurality of trenches formed in the substrate so as to be open at the surface of the substrate, the trenches having opening widths different from each other. The trench with a smaller opening... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070264824 - Methods to eliminate contact plug sidewall slit: A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed... Agent: William Stoffel

20070264825 - Etching method and manufacturing method of semiconductor device: The present invention discloses technique of etching selectively a layer containing siloxane. The present invention provides a semiconductor device with reduced operation deterioration due to etching failure. A method for manufacturing a semiconductor device comprises steps of forming a conductive layer electrically connecting to a transistor, an insulating layer covering... Agent: Eric Robinson

20070264826 - Methods of making self-aligned nano-structures: A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or... Agent: Fletcher Yoder (micron Technology, Inc.)

20070264828 - Method for forming fine pattern of semiconductor device: A method for forming fine patterns of a semiconductor device includes forming hard mask patterns over an underlying layer. A first organic film is formed over the hard mask patterns. A second organic film is formed over the first organic film. The second organic film is planarized until the first... Agent: Townsend And Townsend And Crew, LLP

20070264829 - Slurry and method for chemical mechanical polishing: A chemical mechanical polishing slurry, contains an abrasive dispersed in deionized water and an organic viscosity modifier added to adjust the viscosity of the slurry to within a range of 0.5 to 3.2 cps.... Agent: Townsend And Townsend And Crew, LLP

20070264827 - Method for achieving uniform chemical mechanical polishing in integrated circuit manufacturing: A method for planarizing a surface in an integrated circuit manufacturing process provides a first film of a first material over a non-uniform surface, such as a surface including isolation trenches. The first material includes, for example, a polysilicon layer to be used to form floating gates in a non-volatile... Agent: Macpherson Kwok Chen & Heid LLP

20070264830 - Pitch reduction: A method for providing features in an etch layer is provided. A sacrificial patterned layer with sacrificial features is provided over an etch layer. Conformal sidewalls are formed in the sacrificial features, comprising at least two cycles of a sidewall formation process, wherein each cycle comprises a sidewall deposition phase... Agent: Beyer Weaver LLP

20070264831 - Use of ion implantation in chemical etching: A method for controlling chemical dry etching to improve smoothness of an etched surface is disclosed. Ions are implanted into a surface to form a volatilizable compound at a temperature low enough to avoid, reduce, or eliminate formation of three-dimensional structures of the volatilizable compound that might create the roughness... Agent: Joshua D. Isenberg Jdi Patent

20070264832 - Manufacturing method for semiconductor chips: The semiconductor chip manufacturing process is carried out in processes including a protective sheet sticking process for sticking a protective sheet onto a first surface of a semiconductor wafer so that the sheet comes in contact with the TEG, a mask placing process for placing a mask on a second... Agent: Wenderoth, Lind & Ponack L.L.P.

20070264833 - High resolution patterning of surface energy utilizing high resolution monomolecular resist for fabrication of patterned media masters: A method for patterning and forming very small structures on a substrate such as a wafer. The process uses a difference in surface energy between a mask and the substrate to selectively deposit a hard mask material such as a metal onto the surface of the substrate. The mask can... Agent: Zilka-kotab, PC

20070264834 - Method for synthesis of colloidal nanoparticles: A method for synthesis of high quality colloidal nanoparticles using comprises a high heating rate process. Irradiation of single mode, high power, microwave is a particularly well suited technique to realize high quality semiconductor nanoparticles. The use of microwave radiation effectively automates the synthesis, and more importantly, permits the use... Agent: Gates & Cooper LLP Howard Hughes Center

20070264835 - Photodiode array, method for manufacturing the same, and the optical measurement system thereof: A photodiode array for near infrared rays that includes photodiodes having a uniform size and a uniform shape, has high selectivity for the wavelength of received light between the photodiodes, and has high sensitivity with the aid of a high-quality semiconducting crystal containing a large amount of nitrogen, a method... Agent: Fish & Richardson P.C.

20070264836 - Method for forming a gate and etching a conductive layer: A method for forming a gate and a method for etching a conductive layer are provided. First, a substrate is provided, including a dielectric layer and a conductive layer on its surface in order. Subsequently, a patterned silicon nitride layer is formed on the conductive layer as a hard mask,... Agent: North America Intellectual Property Corporation

20070264838 - Electrical components for microelectronic devices and methods of forming the same: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying... Agent: Perkins Coie LLP Patent-sea

20070264839 - Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer: A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can... Agent: Larson Newman Abel Polansky & White, LLP

20070264840 - Substrate processing apparatus and method of manufacturing semiconductor device: To prevent particles from generating by reducing a contact-gas area and improve a purge efficiency by reducing a flow passage capacity. There is provided a substrate processing apparatus, comprising a processing chamber 1 for processing a substrate 2; a substrate carrying port 10 provided on a sidewall of the processing... Agent: Oliff & Berridge, PLC

20070264837 - Thin transition layer between a group iii-v substrate and a high-k gate dielectric layer: Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on... Agent: Intel Corporation C/o Intellevate, LLC

20070264842 - Insulation film deposition method for a semiconductor device: A thin-film deposition method for a semiconductor device includes injecting a process gas into a process chamber to deposit a thin film and forming a plasma atmosphere inside the process chamber while injecting the process gas to deposit a thin film on a semiconductor substrate. The thin film is formed... Agent: F. Chau & Associates, LLC

20070264841 - Photoresist stripping chamber and methods of etching photoresist on substrates: Methods of processing a substrate so as to protect an active area include positioning a substrate in an inductively coupled plasma processing chamber, supplying process gas to the chamber, generating plasma from the process gas and processing the substrate so as to protect the active area by maintaining a plasma... Agent: Buchanan, Ingersoll & Rooney PC

20070264843 - Formation and applications of nitrogen-free silicon carbide in semiconductor manufacturing: A method for manufacturing an integrated circuit is provided. In one example, the method includes forming a substantially nitrogen-free silicon carbide layer over a substrate using a methyl silicate gas.... Agent: Haynes And Boone, LLP

20070264844 - Method of hiding transparent electrodes on a transparent substrate: A method of hiding transparent electrodes on a transparent substrate coats a solution of non-conductive nanoparticles onto the transparent substrate and the transparent electrodes after forming a plurality of transparent electrodes on the transparent substrate, and both non-conductive nanoparticles and transparent electrodes have the same reflective index of light. After... Agent: Bacon & Thomas, PLLC

20070259468 - Processing piezoelectric material: Techniques are described for forming actuators having piezoelectric material. A block of piezoelectric material is bonded to a transfer substrate. The block is then polished. The polished surface is bonded to a MEMS body.... Agent: Fish & Richardson P.C.

20070259476 - Compositions for forming organic insulating films, methods for forming organic insulating films using the compositions and organic thin film transistors comprising an organic insulating film formed by such a method: Disclosed are compositions for forming organic insulating films and methods for forming organic insulating films using one or more of the compositions. The compositions include at least one ultraviolet (UV) curing agent, at least one water-soluble polymer and at least one water-soluble fluorine compound, and the method includes applying the... Agent: Harness, Dickey & Pierce, P.L.C

20070259474 - Method for forming high-resolution pattern having desired thickness or high aspect ratio using deep ablation: Disclosed herein is a method of forming a pattern, comprising: attaching a single-layer or multi-layer sacrificial film made of a semi-solid or solid material on part or all of the surface of a substrate; irradiating the sacrificial film with a focusable energy beam such as a laser beam to form... Agent: Cantor Colburn, LLP

20070259475 - Method for producing organic field-effect transistors: s

20070259454 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device that comprises a first impurity diffusion region formed on a silicon substrate (semiconductor substrate), a first interlayer insulating film (first insulating film) formed over the silicon substrate, a first hole formed in the first interlayer insulating film, a first conductive plug formed in the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070259455 - Method for repairing thin film transistor array substrate: A thin film transistor array substrate and method for repairing the same are provided. Repairing lines are formed when the data lines on the thin film transistor array substrate are defined. Furthermore, the protruding portions and branches of common lines overlap with the repairing lines and the data lines respectively.... Agent: J C Patents, Inc.

20070259456 - Extended probe tips: Probe tips, methods for making probe tips, and method for using such probe trips are described. The probe tips can include a pedestal portion connected to a beam of a cantilever structure and a contact portion that can contact an electronic component that to be tested. The pedestal portion and... Agent: N. Kenneth Burraston Kirton & Mcconkie

20070259457 - Optical endpoint detection of planarization: In accordance with the invention, there is a semiconductor device comprising optical enhancement medium and there are methods of end point detection in an etching process and also in a planarization process using an optical enhancement medium such as an anti-reflective coating. The method can include forming a semiconductor structure... Agent: Texas Instruments Incorporated

20070259458 - Semiconductor wafer examination method and semiconductor chip manufacturing method: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.... Agent: Harness, Dickey & Pierce, P.L.C

20070259459 - Semiconductor wafer examination method and semiconductor chip manufacturing method: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.... Agent: Harness, Dickey & Pierce, P.L.C

20070259460 - Semiconductor wafer examination method and semiconductor chip manufacturing method: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.... Agent: Harness, Dickey & Pierce, P.L.C

20070259461 - Semiconductor wafer examination method and semiconductor chip manufacturing method: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.... Agent: Harness, Dickey & Pierce, P.L.C

20070259462 - Carbon nanotube structures and methods of manufacture and use: A method of making a carbon nanotube structure includes forming a plurality of carbon nanotubes and contacting the carbon nanotubes with a polymer. A solid composition is formed from the carbon nanotubes and polymer and then shaped. For example, the solid composition can be shaped into an elongated structure such... Agent: Darby & Darby P.C.

20070259464 - Dislocation-specific dielectric mask deposition and lateral epitaxial overgrowth to reduce dislocation density of nitride films: In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching... Agent: Townsend And Townsend And Crew LLP / Amat

20070259463 - Wafer-level method for thinning imaging sensors for backside illumination: A method for fabricating an imaging system is disclosed. The method starts with a wafer having front and backsides. A plurality of the imaging systems are fabricated on the front side of the wafer, each imaging system includes an imaging array that includes a plurality of pixels. Each pixel converts... Agent: Calvin B . Ward Suite 305

20070259465 - Integration of vacuum microelectronic device with integrated circuit: A device includes an integrated circuit (IC) and at least one ultra-small resonant structure formed on said IC. At least the ultra-small resonant structure portion of the device is vacuum packaged. The ultra-small resonant structure portion of the device may be grounded or connected to a known electrical potential. The... Agent: Davidson Berquist Jackson & Gowdey LLP

20070259466 - Light emitting element and manufacturing method thereof: According to the invention, an insulating or semi-insulating barrier layer which has a thickness where a tunnel current can flow through is provided between a hole injection electrode and an organic compound layer with hole transport characteristics (a hole injection layer or a hole transport layer). Specifically, a thin insulating... Agent: Fish & Richardson P.C.

20070259467 - Fabrication of vertical sidewalls on (110) silicon substrates for use in si/sige photodetectors: A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors includes preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface. Masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane and... Agent: David C. Ripma Sharp Laboratories Of America, Inc.

20070259469 - Liquid detection method and apparatus: A liquid detection method, apparatus, and system are disclosed. In one embodiment, an apparatus includes a non-conductive housing base having an absorbing material to expand on contact with a liquid and a conductive material coupled with the absorbing material to form a closed circuit when the conductive material contacts a... Agent: Raj Abhyanker, LLP C/o Portfolioip

20070259471 - Mems device including a laterally movable portion with piezo-resistive sensing elements and electrostatic actuating elements on trench side walls, and methods for producing the same: A method to create piezoresistive sensing elements and electrostatic actuator elements on trench sidewalls is disclosed. P-type doped region(s) 25 are formed in the upper surface of an n-type substrate 20. A trench 22 is formed in the substrate (e.g. by DRIE process) intersecting with the doped regions and defining... Agent: Stephen B. Ackerman

20070259470 - Method of creating a predefined internal pressure within a cavity of a semiconductor device: A method of creating a predefined internal pressure within a cavity of a semiconductor device, the method including providing the semiconductor device, the semiconductor device including a semiconductor oxide area which is continuously arranged between the cavity of the semiconductor device and an external surface of the semiconductor device, exposing... Agent: Glenn Patent Group

20070259472 - Semiconductor photo-detector, semiconductor photo-detection device, and production method thereof: In a semiconductor photo-detector of the present invention, a first semiconductor layer, a second semiconductor layer having, and a photo-absorption part composed of a photo-absorption layer sandwiched between these layers are disposed on a substrate, at least the photo-absorption layer is formed at a position apart inwardly by a finite... Agent: Ostrolenk Faber Gerb & Soffen

20070259473 - Process to form tft gate dielectric with crosslinked polymer: A process for fabricating a thin film transistor including: (a) depositing a gate dielectric precursor composition, wherein the gate dielectric precursor composition includes a polymer comprising polymerized one or more monomers, wherein the one or more monomers includes an optionally substituted vinyl arylalcohol; and (b) irradiating the gate dielectric precursor... Agent: Patent Documentation Center

20070259478 - Manufacturing method of semiconductor device having organic semiconductor film: A method of manufacturing a semiconductor device having an organic semiconductor film comprises a step of preparing a transparent substrate at least having an opaque gate electrode and a gate insulator thereover, a step of forming a layer containing metal-nano-particles as a conductive layer for a source electrode and a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070259477 - Process for making an organic field effect transistor: The present invention relates to a process for reducing the mobility of an semiconductor (OSC) layer in an electronic device, which has a semiconducting channel area, in specific areas outside said channel area by applying an oxidzing agent to the OSC layer.... Agent: Millen, White, Zelano & Branigan, P.C.

20070259479 - Forming phase change memory arrays: A phase change memory may be formed to have a dimension that is sub-lithographic in one embodiment by forming a surface feature over the phase change material, and coating the surface feature with a mask of sub-lithographic dimensions. The horizontal portions of the mask and the surface feature may then... Agent: Trop Pruner & Hu, PC

20070259481 - Process for fabricating chip package structure: A process for fabricating a chip package structure with the following steps is provided. First, a chip having an active surface is provided. A plurality of solder bumps is disposed on the active surface. Then, a polymer material including flux is placed on the surface of the solder bumps by... Agent: Jianq Chyun Intellectual Property Office

20070259480 - System and method of attaching an integrated circuit assembly to a printed wiring board: A method of coupling an integrated circuit (IC) assembly to a printed wiring board (PWB) is provided. The method comprises applying a solder paste to at least one IC assembly interfacial attach pad having a first size on a surface of the IC assembly and applying a solder paste to... Agent: Honeywell International Inc.

20070259482 - Method and apparatus for stacking electrical components using via to provide interconnection: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on... Agent: Stout, Uxa, Buyan & Mullins LLP

20070259483 - Sawing apparatus and a control method for manufacturing processes of semiconductor package: Disclosed is a sawing apparatus for manufacturing a semiconductor package, capable of simultaneously performing strip loading work and package unloading work during the sawing process to improve productivity of the semiconductor packages. The sawing apparatus includes a chuck table base 200; a chuck table 23 installed on the chuck table... Agent: Townsend And Townsend And Crew, LLP

20070259484 - Integrated circuit chip packaging assembly: An integrated circuit chip packaging assembly having a first and second package side. An integrated circuit chip has a substrate side and an active circuit side. The chip includes integrated circuit devices formed on the active circuit side. The active circuit side of the chip is on the first package... Agent: Texas Instruments Incorporated

20070259485 - Electronic device including semiconductor fins and a process for forming the electronic device: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each... Agent: Larson Newman Abel Polansky & White, LLP

20070259487 - Method of forming a polysilicon film and method of manufacturing a thin film transistor including a polysilicon film: In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent... Agent: Lee & Morse, P.C.

20070259486 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a thin film transistor including a semiconductor layer that includes a channel region, a source region and a drain region, a gate insulating film provided on the semiconductor layer, and a gate electrode for controlling the conductivity of the channel region, wherein the surface of the... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20070259488 - Single layer construction for ultra small devices: An array of ultra-small structures of between ones of nanometers to hundreds of micrometers in size that can be energized to produce at least two different frequencies of out put energy or data, with the ultra small structures being formed on a single conductive layer on a substrate. The array... Agent: Davidson Berquist Jackson & Gowdey LLP

20070259489 - Method of forming transistor structure having stressed regions of opposite types: A method of fabrication is provided in which a field effect transistor (FET) is formed having a channel region and source and drain regions adjacent to the channel region. A first stressed region underlies the channel region, in which the first type of stress is either compressive type or tensile... Agent: International Business Machines Corporation Dept. 18g

20070259491 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the side wall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate electrode 112 with the sidewall spacer 116 formed on, and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070259490 - Structure and method for latchup suppression: A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped... Agent: Greenblum & Bernstein, P.L.C

20070259492 - Method for forming storage node contacts in semiconductor device: A method for forming storage node contacts in a semiconductor device includes forming an interlayer dielectric layer on a semiconductor substrate provided with transistors; forming a hydrogen diffusion preventing layer on the interlayer dielectric layer; forming a hard mask layer containing hydrogen atoms on the hydrogen diffusion preventing layer; forming... Agent: Townsend And Townsend And Crew, LLP

20070259493 - Method of fabricating memeory: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory... Agent: J.c. Patents

20070259494 - Methods for forming resistors including multiple layers for integrated circuit devices: Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer... Agent: Myers Bigel Sibley & Sajovec

20070259495 - A non-volatile memory device including nitrogen pocket implants and methods for making the same: In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The nitrogen atoms can improve data retention, and performance of cycled... Agent: Baker & Mckenzie LLP Patent Department

20070259497 - Fabricating method of non-volatile memory: A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are... Agent: Jianq Chyun Intellectual Property Office

20070259496 - Fabrication method of non-volatile memory: A method for fabricating a non-volatile memory is provided. A dielectric layer, a first conductive layer, and a mask layer are formed sequentially on a substrate and then patterned to form a number of openings and floating gates. In addition, spacers are formed on the sidewalls of the openings. A... Agent: J.c.patents, Inc.

20070259499 - Method for manufacturing semiconductor device having recess gate: A method for manufacturing a semiconductor device having recess gates includes forming an etch stop film on a semiconductor substrate; forming an etch stop film pattern selectively exposing the semiconductor substrate by patterning the etch stop film; forming a semiconductor layer on the semiconductor substrate; forming a hard mask film... Agent: Townsend And Townsend And Crew, LLP

20070259498 - Method of fabricating metal-oxide-semiconductor transistor: A method of fabricating a metal-oxide-semiconductor (MOS) transistor is provided. First, a patterned hard mask layer with an opening therein is formed over the substrate. A spacer is formed on the sidewall of the patterned hard mask layer in the opening. An isotropic etching process is performed on the substrate... Agent: Jianq Chyun Intellectual Property Office

20070259500 - Structure having isolation structure including deuterium within a substrate and related method: Structures having an isolation structure including deuterium and a related method are disclosed. The deuterium is preferably substantially uniformly distributed, and has a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. One structure includes a substrate for a semiconductor device including an isolation... Agent: Hoffman, Warnick & D'alessandro LLC

20070259501 - Integrating high performance and low power multi-gate devices: A semiconductor device comprising a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprising a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width... Agent: Texas Instruments Incorporated

20070259502 - Parasitic particle suppression in growth of iii-v nitride films using mocvd and hvpe: A method of suppressing parasitic particle formation in a metal organic chemical vapor deposition process is described. The method may include providing a substrate to a reaction chamber, and introducing an organometallic precursor, a particle suppression compound and at least a second precursor to the reaction chamber. The second precursor... Agent: Townsend And Townsend And Crew LLP / Amat

20070259503 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device is provided herein. The semiconductor device includes a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer. The gate dielectric layer is disposed on the substrate and the gate whose top area is larger than its... Agent: Jianq Chyun Intellectual Property Office

20070259504 - Dislocation-specific lateral epitaxial overgrowth to reduce dislocation density of nitride films: In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching... Agent: Townsend And Townsend And Crew LLP / Amat

20070259505 - Non-volatile memory devices and methods for forming the same: Non-volatile memory devices and methods for forming the same are provided. A device isolation layer may be formed on the semiconductor substrate to define an active region. A tunneling insulation pattern, a charge storage pattern, and a blocking insulation pattern may be disposed on the active region. A gate electrode... Agent: Myers Bigel Sibley & Sajovec

20070259506 - Probe needle, method for manufacturing the probe needle and method for constructing a three-dimensional structure: A method for manufacturing a probe needle having beams and a contactor placed on tips of the beams comprises preparing a Si wafer 20, forming a seed layer 21 on the Si wafer 20, and forming grooves in a desired shape of the beams on the seed layer 21 by... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070259507 - Manufacturing method of semiconductor device: In a manufacturing method of semiconductor device, initially, a trench pattern is laid out along a <100> direction of a (100) silicon substrate. Next, a trench is formed in the silicon substrate based on the laid-out trench pattern. Further, the silicon substrate with the trench formed therein is annealed in... Agent: Foley And Lardner LLP Suite 500

20070259508 - Method of fabricating microconnectors: A method of fabricating microconnectors. A wafer is provided, and a dielectric layer is formed on a first surface of the wafer. The dielectric layer is bonded to a support wafer, and a thinning process is performed. A second surface of the wafer is then bonded to the support wafer,... Agent: North America Intellectual Property Corporation

20070259509 - Method of thinning a wafer: A method of thinning a wafer. A wafer is provided, and the front surface of the wafer is bonded to a carrier wafer with a bonding layer. The bonding layer is a thermal release tape or a UV tape. Subsequently, a wafer thinning process is performed to thin the wafer... Agent: North America Intellectual Property Corporation

20070259510 - Semiconductor device, semiconductor layer and production method thereof: A semiconductor device is prepared by the use of a vapor phase method and is provided with a semiconductor layer composed of boron phosphide (BP) having a band gap at room temperature of not less than 2.8 eV and not more than 3.4 eV or a boron phosphide (BP)-base mixed... Agent: Sughrue Mion, PLLC

20070259511 - Method of implanting a substrate and an ion implanter for performing the method: An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the subsequent fast scan speed... Agent: Birch Stewart Kolasch & Birch

20070259512 - Method of manufacturing a semiconductor device: For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film successively over a gate insulating film disposed over the main... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070259513 - Methods of forming contact openings: The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature above a semiconducting substrate, forming a layer stack comprised of a plurality of layers of material above the feature, the layer stack having an original height, reducing the original... Agent: Williams, Morgan & Amerson

20070259515 - Method for manufacturing wafer-level packages for flip chips capable of preventing adhesives from absorbing water: The present invention provides a method for manufacturing a wafer-level package comprising the steps of coating adhesives on a wafer on which bumps are already formed and irradiating the adhesive layer using a laser to divide the wafer into individual chip units. According to the present invention, it is possible... Agent: Metcalf Intellectual Property Law, LLC

20070259514 - Interconnection structure, electronic component and method of manufacturing the same: An interconnection structure includes an electrically conductive bump, wherein the electrically conductive bump has a metal body having a distal end. The metal body is free of solder. An outermost layer of diffusion solder is positioned on at least regions of the metal body of the electrically conductive bump.... Agent: Baker Botts, L.L.P.

20070259517 - Low temperature methods of forming back side redistribution layers in association with through wafer interconnects: Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to forming the RDLs, after forming the RDLs, or substantially... Agent: Trask Britt, P.C./ Micron Technology

20070259516 - Multilayer interconnect structure containing air gaps and method for making: A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect structure includes a collection of interspersed line levels and via levels, with via levels comprising conductive vias embedded in one or more dielectric layers in which the dielectric layers are solid underneath... Agent: Scully Scott Murphy & Presser, PC

20070259518 - Method and apparatus for diverting void diffusion in integrated circuit conductors: A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer... Agent: Lsi Corporation

20070259519 - Interconnect metallization process with 100% or greater step coverage: An interconnect structure with a thicker barrier material coverage at the sidewalls of a feature as compared to the thickness of said barrier material at the feature bottom as well as a method of fabricating such an interconnect structure are provided. The interconnect structure of the present invention has improved... Agent: Scully, Scott, Murphy & Presser, P.C.

20070259520 - Beveled trench forming device for concrete slab foundations: An assemblage which form a beveled edge in a slab-on-grade foundation trench. The device is comprised of straight members corner members, and a connector member to hold the larger members together, an angle brace to maintain the proper bevel angle of 45° degrees, and a stake to anchor the device... Agent: Marvin D. Cooper

20070259521 - Display substrate and method for manufacturing the same: A method of forming a display substrate includes forming an array layer on a substrate, forming a passivation layer on the array layer, forming a photoresist pattern on the passivation layer corresponding to a gate line, a source line and a thin-film transistor of the array layer, etching the passivation... Agent: Cantor Colburn, LLP

20070259522 - Fabrication method of semiconductor integrated circuit device: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070259523 - Method of fabricating high speed integrated circuits: This invention describes a new method of fabricating high speed chips such as microprocessors used in servers. The biggest problem limiting the speed of these chips is the heat generated by such a large number of transistors in such a small area operating at such a high frequency. This invention... Agent: Sitaramarao Srinivas Yechuri

20070259524 - Method for fabricating fine pattern in semiconductor device: A method for forming a fine pattern in a semiconductor device includes forming a first polymer layer over an etch target layer, the first polymer layer including a carbon-rich polymer layer, forming a second polymer layer over the first polymer layer, the second polymer layer including a silicon-rich polymer layer,... Agent: Townsend And Townsend And Crew, LLP

20070259525 - Cmp process: A CMP process is provided. A first polishing process on a wafer is performed using a first hard polishing pad with a first slurry. Then, a buffering process on the wafer is performed using a soft polishing pad with a cleaning agent to buffer the pH value in the first... Agent: Jianq Chyun Intellectual Property Office

20070259526 - Surface finishing of soi substrates using an epi process: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which is characterized by a predetermined surface roughness value. The substrate also has a distribution of hydrogen bearing particles defined from the cleaved... Agent: Townsend And Townsend And Crew, LLP

20070259527 - Automatic process control of after-etch-inspection critical dimension: Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickness and the second thickness is substantially constant. An ADI CD... Agent: North America Intellectual Property Corporation

20070259528 - Method for providing mixed stacked structures, with various insulating zones and/or electrically conductiong zones vertically localized: t

20070259529 - Forming integrated circuit devices: Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask layer further overlies a second mask layer overlying a second portion of the semiconductor substrate. The first mask layer overlying the first portion of the... Agent: Lefferty Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070259530 - Method for producing a layer structure: A layer structure comprising a smoothed interlayer and an overlying layer applied on the interlayer, wherein the interlayer is treated with a gaseous etchant containing hydrogen fluoride, a material removal being obtained thereby and the interlayer being smoothed.... Agent: Brooks Kushman P.C.

20070259531 - Method for producing a polished semiconductor: an etching step in which the semiconductor wafers are oxidized and material is removed from the front side of the wafers with the aid of a gaseous etchant containing hydrofluoric acid at a temperature of 20 to 70° C., and a polishing step in which the front side of the... Agent: Brooks Kushman P.C.

20070259532 - Producing method of semiconductor device and substrate processing apparatus: Disclosed is a producing method of a semiconductor device comprising: loading a substrate into a reaction furnace; forming a film on the substrate in the reaction furnace; unloading the substrate from the reaction furnace after the film has been formed, and forcibly cooling an interior of the reaction furnace in... Agent: Birch Stewart Kolasch & Birch

20070259533 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a structure comprising at least two heterogeneous layers having different stress levels; and a stress relief layer disposed between the two heterogeneous layers to relive a difference in the stress levels. The stress relief layer may include: a first layer formed over a first heterogeneous layer;... Agent: Blakely Sokoloff Taylor & Zafman

20070259534 - In-situ formation of oxidized aluminum nitride films: A method is provided for in-situ formation of a thin oxidized AlN film on a substrate. The method includes providing the substrate in a process chamber, depositing an AlN film on the substrate, and post-treating the AlN film with exposure to a nitrogen and oxygen-containing gas. The post-treating increases the... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070259535 - Radial temperature control for lattice-mismatched epitaxy: Methods are disclosed of fabricating a compound nitride semiconductor structure. A substrate is disposed over a susceptor in a processing chamber, with the susceptor in thermal communication with the substrate. A group-III precursor and a nitrogen precursor are flowed into the processing chamber. The susceptor is heated with a nonuniform... Agent: Townsend And Townsend And Crew LLP / Amat

20070254383 - Method of manufacturing ferroelectric thin film for data storage and method of manufacturing ferroelectric recording medium using the same method: A method of manufacturing a ferroelectric thin film with good crystallinity and improved surface roughness includes: forming on a substrate a metal nitride-based precursor layer containing one selected from the group consisting of TiN, ZrxTi(1-x)N (0<x<1), FeN, and NbN; forming on the metal nitride-based precursor layer a mixed gas atmosphere... Agent: Sughrue Mion, PLLC

20070254387 - Semiconductor strain gauge and the manufacturing method: A high-density impurity diff-used layer of an identical conduction type to the semiconductor substrate on which the impurity is doped higher in density than the semiconductor substrate around the diffuse resistance region is provided, one side of the electrodes is formed extending to the high-density impurity diffused layer and the... Agent: Jordan And Hamburg LLP

20070254389 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device is provided. The method includes forming a mold for forming a storage electrode, forming sacrificial spacers at side walls of openings in the mold, forming a conductive film for a storage electrode along the inside of the openings, removing the mold by a... Agent: Marger Johnson & Mccollom, P.C.

20070254395 - Method for producing gallium nitride light emitting diode wafer: The present invention relates to a method for improving the performance of P-type ohmic contact of gallium nitride LED wafer. Magneto sputtering is used to spray nickel material in nano particles onto the surface of gallium nitride epitaxial layer. The thickness of nickel is between 1 nm to 100 nm.... Agent: Eric Chan

20070254398 - Method of manufacturing semiconductor device: A method of manufacturing a high-speed operable and broadband operable semiconductor device where a light-receiving element section, a CMOS element and a bipolar transistor element having a double polysilicon structure are formed on one chip. By performing the same conductivity type ion implantation, the same conductivity type diffusion layers (examples... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070254400 - Method for manufacturing integrated circuit: The flatness of the surface of the light-receiving portion must be increased when the upper structural layer of a light detector is etched. The present invention provides a method for manufacturing an integrated circuit in which an aperture is formed in a stack in which an underlayer, a light-receiving area... Agent: Oliff & Berridge, PLC

20070254401 - Method of processing a surface of group iii nitride crystal and group iii nitride crystal substrate: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing... Agent: Mcdermott Will & Emery LLP

20070254384 - Process monitoring apparatus and method for monitoring process: A sensor on a semiconductor wafer is used as a process monitor and a capacitor is employed as a power supply for the sensor. The capacitor can be formed by stacking a poly-silicon layer and a silicon nitride layer on the wafer. A timer can be used to specify an... Agent: Crowell & Moring LLP Intellectual Property Group

20070254386 - Measurement coordinate setting system and method: A measurement coordinate setting system is disclosed, which includes a measuring apparatus which measures a dimension in each of a plurality of portions of a first product, a sampling approximation module which approximates a distribution of the dimensions of the plurality of portions using a sampling orthogonal polynomial as a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070254385 - Method of manufacturing light-emitting diode module: A method of manufacturing a light-emitting diode module comprises the steps of: coupling an electronic device with a circuit board such that a distinguishing resistor is coupled adjacent to a light-emitting diode; baking the circuit board by a reflow oven; and testing the baked circuit board, whereby the related information... Agent: Troxell Law Office PLLC

20070254388 - Semiconductor wafer examination method and semiconductor chip manufacturing method: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.... Agent: Harness, Dickey & Pierce, P.L.C

20070254390 - Nitride optoelectronic devices with backside deposition: Nitride optoelectronic devices that have asymmetric double-sided structures and methods fabricating such structures are disclosed. Two n-type III-N layers are formed simultaneously over opposite sides of a substrate with substantially the same composition. Thereafter, a p-type III-N active layer is formed over one of the n-type III-N layers but not... Agent: Townsend And Townsend And Crew LLP / Amat

20070254391 - Light emitting device and method of manufacturing the same: A light emitting device and a method of manufacturing the same are provided. A light emitting device has a structure wherein a substrate, an n-type clad layer, a light emitting layer, a p-type clad layer, an ohmic contact layer, and a reflective layer are successively stacked. The ohmic contact layer... Agent: Buchanan, Ingersoll & Rooney PC

20070254392 - Laser annealing method and semiconductor device fabricating method: When the second harmonic of a YAG laser is irradiated onto semiconductor films, concentric-circle patterns are observed on some of the semiconductor films. This phenomenon is due to the non-uniformity of the properties of the semiconductor films. If such semiconductor films are used to fabricate TFTs, the electrical characteristics of... Agent: Eric Robinson

20070254393 - Passivation of vcsel sidewalls: A semiconductor structure configured for use in a VCSEL or RCLED. The semiconductor structure includes an oxidizing layer constructed from materials that can be oxidized during a lithographic process so as to create an oxide aperture. The semiconductor structure further includes a number of layers near the oxidizing layer. A... Agent: Workman Nydegger

20070254394 - Gallium nitride-based light emitting device having esd protection capacity and method for manufacturing the same: A gallium nitride-based light emitting device, and a method for manufacturing the same are disclosed. The light emitting device comprises an n-type GaN-based clad layer, an active layer, a p-type GaN-based clad layer and a p-side electrode sequentially stacked on a substrate. The device further comprises an n-side electrode formed... Agent: Mcdermott Will & Emery LLP

20070254396 - Systems and methods for creating mems gyros: Methods and systems for creating microelectromechanical system (MEMS) gyros. The methods and systems include generating a map of motor bias and creating MEMS gyros based on the map of motor bias to achieve a higher yield of usable MEMS gyros per wafer. The systems include a processor with components configured... Agent: Honeywell International Inc.

20070254397 - Method for manufacturing a patterned bottom electrode in a piezoelectric device: A method for manufacturing a patterned bottom electrode in a piezoelectric device comprises the steps of providing a basic material and producing a layer structure of a conductive material on the basic material. A protective layer is applied on the layer structure over an area. Thereafter, a planarization layer is... Agent: Maginot, Moore & Beck Chase Tower

20070254399 - Low temperature direct deposited polycrystalline silicon thin film transistor structure and method for manufacturing the same: A method for manufacturing a thin film transistor (“TFT”) device includes providing a substrate, forming a patterned first metal layer on the substrate, forming an insulating layer over the patterned first metal layer, forming an amorphous silicon layer over the insulating layer, forming a first polycrystalline silicon layer over the... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070254402 - Structure and fabrication of self-aligned high-performance organic fets: A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor... Agent: Hogan & Hartson LLP

20070254403 - Encapsulation for particle entrapment: A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents the generation of debris that could interfere with the operation of the micromechanical device (100). Debris-generating regions of the device (100), including debris-creating sidewalls and any debris-harboring cavities, as well as... Agent: Texas Instruments Incorporated

20070254405 - 3d interconnect with protruding contacts: This invention relates to a semiconductor having protruding contacts comprising, a first semiconductor substrate having at least one interconnect located substantially within the first substrate, and a second semiconductor substrate having at least one protruding contact point that substantially contacts at least one interconnect.... Agent: Hewlett Packard Company

20070254406 - Method for manufacturing stacked package structure: A method for manufacturing a stacked package structure is disclosed, comprising: forming a first chip package structure, comprising: providing a chip carrier having a first and a second surface in opposition to each other; forming bonding wires on the first surface; providing at least one chip on and electrically connected... Agent: Birch Stewart Kolasch & Birch

20070254404 - Semiconductor package-on-package system including integrated passive components: A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate... Agent: Texas Instruments Incorporated

20070254407 - Method of reducing mechanical stress on a semiconductor die during fabrication: A method of reducing mechanical stress on an integrated circuit is disclosed including applying solder columns to the substrate for adding structural support to the package during the fabrication process.... Agent: Vierra Magen/sandisk Corporation

20070254408 - Method of making wirebond electronic package with enhanced chip pad design: A method of making a wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20070254409 - Method of forming stackable package: A method of forming a semiconductor package (50 and 52) includes providing a substrate (14) having a die pad and bond pads on a first surface (20) and conductive pads (66, 68 and 74) on a second surface (22). An integrated circuit (IC) die (38) is attached to the die... Agent: Freescale Semiconductor, Inc. Law Department

20070254411 - Systems and methods for high density multi-component modules: A method for forming a device, comprising providing a first substrate carrying a first set of components disposed in a first encapsulating layer over the first set of components, providing a second substrate carrying a second set of components disposed in a second encapsulating layer over the second set of... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070254410 - Semiconductor sealing resin sheet and semiconductor device manufacturing method using the same: A semiconductor sealing resin sheet is composed of a supporting sheet and a sealing resin layer releasably laminated on the supporting sheet, wherein the sealing resin layer has a thermosetting property, the elastic modulus of the sealing resin layer before thermosetting is 1.0×103 to 1.0×104 Pa, the melt viscosity 120°... Agent: The Webb Law Firm, P.C.

20070254412 - High performance 3d fet structures, and methods for forming the same using preferential crystallographic etching: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used... Agent: Scully Scott Murphy & Presser, PC

20070254413 - Ccd with improved charge transfer: A method of forming a charge-coupled device including the steps of forming well or substrate of a first conductivity type; a buried channel of a second conductivity type; a plurality of first gate electrodes; partially coating the first gate electrodes with a mask substantially aligned to an edge of the... Agent: Pamela R. Crocker Patent Legal Staff

20070254414 - Method of manufacturing semiconductor device, and semiconductor device: A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The... Agent: Sonnenschein Nath & Rosenthal LLP

20070254415 - Thin film transistor substrate, method of manufacturing the same and method of manufacturing liquid crystal display panel including the same: A thin film transistor substrate, a method of manufacturing the same and a method of manufacturing a liquid crystal display including the same, in which a process of patterning an active pattern and a storage electrode pattern for a storage capacitor and a process of implanting impurity ions into the... Agent: F. Chau & Associates, LLC

20070254416 - Manufacturing method for semiconductor device: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried... Agent: Eric Robinson

20070254417 - Method of fabricating a semiconductor device having a capacitor: A semiconductor device having a capacitor is provided. The semiconductor device includes a substrate, a capacitor and a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is located in a MOS transistor region of the substrate, and the MOS transistor region has a first bottom diffusion region. The capacitor is located in... Agent: Jianq Chyun Intellectual Property Office

20070254418 - Methods of fabricating nitride-based transistors with a cap layer and a recessed gate: An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage... Agent: Myers Bigel Sibley & Sajovec

20070254419 - Semiconductor device and method for fabricating the same: A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic... Agent: Mcdermott Will & Emery LLP

20070254420 - Source/drain implantation and channel strain transfer using different sized spacers and related semiconductor device: Methods for source/drain implantation and strain transfer to a channel of a semiconductor device and a related semiconductor device are disclosed. In one embodiment, the method includes using a first size spacer for deep source/drain implantation adjacent a gate region of a semiconductor device; and using a second, smaller size... Agent: Hoffman, Warnick & D'alessandro LLC

20070254424 - Method for fabricating cmos image sensor with plasma damage-free photodiode: A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes providing a semi-finished substrate, forming a patterned blocking layer over a photodiode region of the substrate, implanting impurities on regions other than the photodiode region using a mask while the patterned blocking layer remains, and removing the mask.... Agent: Morgan Lewis & Bockius LLP

20070254422 - High performance stress-enhance mosfet and method of manufacture: A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the... Agent: Greenblum & Bernstein, P.L.C

20070254423 - High performance stress-enhance mosfet and method of manufacture: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure... Agent: Greenblum & Bernstein, P.L.C

20070254421 - Metal oxide semiconductor field effect transistor and method of fabrication thereof: A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure.... Agent: Jianq Chyun Intellectual Property Office

20070254425 - Methods of fabricating a semiconductor device: Example embodiments of the present invention relates to methods of fabricating a semiconductor device. Other example embodiments of the present invention relate to methods of fabricating a semiconductor device using a metal nitride layer as a gate electrode. The methods may include providing a semiconductor substrate having a first region... Agent: Harness, Dickey & Pierce, P.L.C

20070254426 - Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so... Agent: Bruce L. Adams, Esq.

20070254427 - Method for fabricating semiconductor: A method for fabricating a semiconductor device includes forming a first trench by etching a substrate already provided with a storage node contact (SNC) region and a bit line contact (BLC) region, forming a protection layer on sidewalls of the first trench, forming a sacrificial layer over the substrate and... Agent: Townsend And Townsend And Crew, LLP

20070254429 - Display device and manufacturing method thereof: A display device includes an insulation substrate, a source electrode and a drain electrode disposed on the insulation substrate and distanced from each other and including a channel area interposed therebetween, a wall exposing portions of the source electrode and the drain electrode, and defining an opening area surrounding the... Agent: Cantor Colburn, LLP

20070254428 - Integrated circuit including resistivity changing memory cells: Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a... Agent: Dicke, Billig & Czaja

20070254430 - A trench capacitor and method for fabricating the same: A trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The method of fabricating the trench capacitor includes the steps of forming a trench in the semiconductor substrate; depositing a dielectric layer on a... Agent: International Business Machines Corporation Dept. 18g

20070254432 - Semiconductor device and manufacturing method thereof: In the present invention, a semiconductor device that has a nonvolatile memory element to which data can be written at times other than during manufacture and in which forgery and the like performed by rewriting of data can be prevented is provided. In addition, a semiconductor device in which a... Agent: Eric Robinson

20070254431 - Nitride semiconductor device: A nitride semiconductor device includes: a conductive substrate; a first semiconductor layer provided on the substrate; a second semiconductor layer provided on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a first main electrode connected to the third semiconductor layer; a second main electrode connected... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070254433 - Method of fabricating flash memory device: A method of fabricating a non-volatile memory device forming a first polysilicon film over a semiconductor substrate; forming a mitigation film over the first polysilicon film; forming a mask film over the mitigation film; etching the mask film, the mitigation film, and the first polysilicon film to form a first... Agent: Townsend And Townsend And Crew, LLP

20070254434 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate including an active area (AA) surrounded by an isolation insulating film, and a nonvolatile memory cell on the AA, the nonvolatile memory cell including a tunnel insulating film on the AA, a FG electrode on the tunnel insulating film, a CG electrode above... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070254435 - Method for forming a semiconductor device having a fin an structure thereof: A method for forming a semiconductor device includes providing a semiconductor layer, forming a passivation layer over the semiconductor layer, wherein the passivation layer has an opening having sidewalls, forming a fin over the semiconductor layer, wherein after forming the passivation layer the fin is within the opening, and forming... Agent: Freescale Semiconductor, Inc. Law Department

20070254436 - Flash memory and methods of fabricating the same: Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed within the epitaxial layer to expose the first source; a floating... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070254437 - Method for reducing silicide defects by removing contaminants prior to drain/source activation: By consuming a surface portion of polysilicon material or silicon material after implantation and prior to activation of dopants, contaminants may be efficiently removed, thereby significantly enhancing the process uniformity during a subsequent silicidation process. Hence, the defect rate during the silicidation process, for instance “missing silicide” defects, may be... Agent: Williams, Morgan & Amerson

20070254438 - Double gated transistor and method of fabrication: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The... Agent: Schmeiser, Olsen & Watts

20070254439 - Method for making semiconductor transistor: A semiconductor transistor includes a substrate, a gate insulating layer positioned on the surface of the substrate, a gate positioned on the gate insulating layer, a channel region positioned in the substrate corresponding to the gate, and a source region and a drain region respectively positioned alongside the channel region.... Agent: North America Intellectual Property Corporation

20070254440 - Thermal oxidation of a sige layer and applications thereof: The invention concerns a method for oxidizing a surface region of a SiGe layer that includes an oxidizing thermal treatment of the SiGe layer for oxidizing the surface region. The method includes two phases—a first phase of oxidizing thermal treatment, carried out directly on the SiGe layer, so as to... Agent: Winston & Strawn LLP Patent Department

20070254441 - Method of forming a field effect transistor: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070254443 - Method for reducing overlap capacitance in field effect transistors: A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations... Agent: Cantor Colburn LLP - IBM Fishkill

20070254442 - Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method: A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the... Agent: Edell, Shapiro & Finnan, LLC

20070254444 - A semiconductor device having stressed etch stop layers of different intrinsic stress in combination with pn junctions of different design in different device regions: By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.... Agent: Williams, Morgan & Amerson

20070254445 - Method of forming nitride film and nitride structure: A method of forming a nitride film by hydride vapor phase epitaxy, the method including: sequentially disposing at least one group III metal source including impurities and a substrate in an external reaction chamber and an internal reaction chamber sequentially located in the direction of gas supply and heating each... Agent: Mcdermott Will & Emery LLP

20070254446 - Self-aligned biopolar junction transistors: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second... Agent: Trop Pruner & Hu, PC

20070254447 - Decoupled pocket and ldd formation: A method of decoupling the formation of LDD and pocket regions is provided. The method includes providing a semiconductor chip including active regions, forming gate structures in the active regions, forming N-LDD regions on the semiconductor chip using an N-LDD mask, forming N-Pocket regions on the semiconductor chip using an... Agent: Slater & Matsil, L.L.P.

20070254448 - Integrated circuit with inductor having horizontal magnetic flux lines: An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor... Agent: Lsi Corporation

20070254449 - Tunable temperature coefficient of resistance resistors and method of fabricating same: Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about... Agent: Schmeiser, Olsen & Watts

20070254450 - Process for forming a silicon-based single-crystal portion: A silicon-based single-crystal portion is produced on a substrate selectively in a zone where a single-crystal material is initially exposed. The portion is produced outside other surface zones where the surface of the substrate is made of insulating material. The single-crystal portion is formed from a gas mixture including a... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20070254451 - Process for forming a silicon-based single-crystal portion: Silicon-based single-crystal portions are produced on a surface of a substrate, selectively in zones where a single-crystal material is initially exposed. To do this, a layer is firstly formed over the entire surface of the substrate, using a silicon precursor of the non-chlorinated hydride type, and under suitable conditions so... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20070254452 - Mask structure for manufacture of trench type semiconductor device: A mask structure and process for forming trenches in a silicon carbide or other wafer, and for implanting impurities into the walls of the trenches using the same mask where the mask includes a thin aluminum layer and a patterned hard photoresist mask. A thin LTO oxide may be placed... Agent: Ostrolenk Faber Gerb & Soffen

20070254453 - Method of improving a shallow trench isolation gapfill process: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the... Agent: Townsend And Townsend And Crew, LLP

20070254455 - Semiconductor integrated circuit, manufacturing method thereof, and semiconductor device using semiconductor integrated circuit: A step of forming a through hole in a semiconductor substrate, or a step of polishing the semiconductor substrate from its back surface requires a very long time and causes decrease of productivity. In addition, when semiconductor substrates are stacked, a semiconductor integrated circuit which is formed of the stack... Agent: Eric Robinson

20070254454 - Process for bonding and electrically connecting microsystems integrated in several distinct substrates: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates... Agent: Seed Intellectual Property Law Group PLLC

20070254456 - Method for manufacturing semiconductor device: A technique for peeling an element manufactured through a process at relatively low temperature (lower than 500° C.) from a substrate and transferring the element to a flexible substrate (typically, a plastic film). With the use of an existing manufacturing device for a large glass substrate, a molybdenum film (Mo... Agent: Fish & Richardson P.C.

20070254457 - Technique for stable processing of thin/fragile substrates: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070254458 - Buffer-layer treatment of mocvd-grown nitride structures: Methods are disclosed for fabricating a compound nitride semiconductor structure. An amorphous buffer layer that includes nitrogen and a group-III element is formed over a substrate disposed within a substrate processing chamber at a first temperature. The temperature within the chamber is increased to a second temperature at which the... Agent: Townsend And Townsend And Crew LLP / Amat

20070254459 - Method of growing non-polar m-plane nitride semiconductor: A method of growing a non-polar m-plane nitride semiconductor. A (11-23) plane sapphire substrate is prepared, and a non-polar (10-10) nitride semiconductor is grown on the sapphire substrate. The present invention can also be applied to a method for manufacturing other m-plane hexagonal semiconductors.... Agent: Mcdermott Will & Emery LLP

20070254460 - Method for introducing impurities and apparatus for introducing impurities: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous... Agent: Mcdermott Will & Emery LLP

20070254461 - Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same: By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20070254462 - Method and apparatus for doping semiconductors: Semiconductor materials such as silicon particles are doped by mixing the semiconductor material with a solution having a dopan and a solvent. The solvent is removed from the wetted surface of the particles of the semiconductor material, thereby yielding particles that are substantially free from the solvent and are uniformly... Agent: Proskauer Rose LLP

20070254463 - Semiconductor device and method of manufacturing the same: According to an aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate which includes a number of chip areas, a processed film which is formed on the semiconductor substrate, and a ring-shaped pattern which is formed on the processed film and along a peripheral... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070254464 - Method and structure to reduce contact resistance on thin silicon-on-insulator device: A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070254465 - Method of fabricating recess channel in semiconductor device: A method of fabricating a recess channel in a semiconductor device includes forming a hard mask pattern over a substrate, etching the substrate using the hard mask pattern to form first recesses, forming an insulation layer over the hard mask pattern and the first recesses, etching the insulation layer to... Agent: Lowe Hauptman Ham & Berner, LLP

20070254466 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes providing a substrate formed with a plurality of gate lines, each gate line including a hard mask, forming an etch barrier layer over the gate lines, forming an inter-layer insulation layer to cover the etch barrier layer, etching the inter-layer insulation layer... Agent: Blakely Sokoloff Taylor & Zafman

20070254467 - Hexagonal array structure for ball grid array packages: Solder balls may be arranged in hexagonal array on an integrated circuit package. The hexagonal array may increase the solder ball density, reducing solder ball fatigue. In some embodiments, the hexagonal array may be utilized under the die shadow and an orthogonal array may be used outbound thereof.... Agent: Trop Pruner & Hu, PC

20070254468 - Lithography transfer for high density interconnect circuits: A method for fabricating an interconnect comprising providing a carrier substrate, wherein the carrier substrate comprises a plurality of interconnect traces and a plurality of input/output contacts; providing a flexible substrate having a first side and a second side, disposing the second side of the sacrificial layer onto the first... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20070254470 - Method for fabricating a semiconductor device having a repair fuse: A method for fabricating a semiconductor device is provided. The method includes forming a repair fuse over a substrate, forming an insulation layer over the repair fuse and the substrate, forming a metal line for use as a pad over the insulation layer, the metal line including a first metal... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070254469 - Surface mounting method: An improved surface mounting method applied in a semiconductor package process is provided, wherein the method comprises the following steps: First a substrate having at least one pad set on one surface of the substrate is provided. Then a mask having at least one opening associated with one of the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070254471 - Semiconductor device and manufacturing method thereof: A result of formation of an opening in a semiconductor substrate can be judged without cutting a semiconductor wafer and observing a cross-section of the cut wafer. A semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, an opening formed in the... Agent: Morrison & Foerster LLP

20070254472 - Manufacturing method of semiconductor device and semiconductor storage device including fine contact holes: A manufacturing method of a semiconductor device is carried out as follows. A first mask layer having a first linear opening pattern is formed above the first interlayer insulating layer. A second mask layer having a plurality of second linear opening patterns and first dummy opening patterns is formed above... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070254473 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes: forming a first inter-layer insulation layer over a substrate where a plurality of first contact holes are formed; forming a conductive layer over the first inter-layer insulation layer to fill the first contact holes; etching the conductive layer such that a surface... Agent: Blakely Sokoloff Taylor & Zafman

20070254474 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes forming a copper anti-diffusion film on a copper trench wiring layer, and forming an opening portion in the copper anti-diffusion film by laser aberration, the opening portion being formed in a region corresponding to an alignment region used for lithography process for... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070254475 - Semiconductor device with a barrier layer and a metal layer: This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon... Agent: Morrison & Foerster LLP

20070254476 - Cleaning porous low-k material in the formation of an interconnect structure: A cleaning solution and a method for cleaning a semiconductor wafer using the cleaning solution are provided. The method includes submerging the semiconductor wafer in a cleaning solution to remove by-products generated during integrated circuit formation processes. The cleaning solution includes an organic solvent, a metal reagent, a substitutive agent,... Agent: Slater & Matsil, L.L.P.

20070254477 - Film forming method, fabrication process of semiconductor device, computer-readable recording medium and sputtering apparatus: A film-forming method for forming a metal film on a substrate by a sputtering process includes the steps of depressurizing a processing space, in which deposition of the metal film is caused by the sputtering process, applying a DC bias voltage between the substrate and a target disposed in the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070254480 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in... Agent: Young & Thompson

20070254479 - Method for forming self-aligned metal silicide contacts: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide... Agent: Scully Scott Murphy & Presser, PC

20070254478 - Silicide gate field effect transistors and methods for fabrication thereof: A method for fabricating a silicide gate field effect transistor includes masking a silicon source/drain region prior to forming the silicide gate by annealing a metal silicide forming metal layer contacting a silicon-containing gate. The silicide gate may be either a fully silicided gate or a partially silicided gate. After... Agent: Scully Scott Murphy & Presser, PC

20070254481 - Method for forming tungsten materials during vapor deposition processes: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer... Agent: Patterson & Sheridan, LLP

20070254482 - Method and system for manufacturing a semiconductor device: A method for manufacturing a semiconductor device has measuring a finished state of a wafer in a completed process, estimating an in-surface tendency of the wafer based on a result of the measuring, estimating a surface characteristic of the wafer based on the estimated in-surface tendency, setting a process condition... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070254483 - Plasma etch process using polymerizing etch gases and an inert diluent gas in independent gas injection zones to improve etch profile or etch rate uniformity: A plasma etch process for etching high aspect ratio openings in a dielectric film on a workpiece is carried out in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through at least one... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20070254485 - Abrasive composition for electrochemical mechanical polishing: Compositions and methods for processing a substrate having a conductive material layer disposed thereon are provided. In certain embodiments, a composition for processing a substrate having a conductive material layer disposed thereon is provided wherein the composition includes an acid based electrolyte, a chelating agent, a corrosion inhibitor, a passivating... Agent: Patterson & Sheridan, LLP

20070254484 - Substantially spherical composite ceria/titania particles: The present invention provides substantially spherical composite ceria/titania particles, a method of forming the same, and chemical mechanical polishing compositions comprising such particles. The substantially spherical particles include a substantially crystalline core portion including one or more crystallites having a cubic lattice structure including Ce(1-x)Ti(x)O2, where x is <0.25, and... Agent: Rankin, Hill, Porter & Clark, LLP

20070254486 - Plasma etch process with separately fed carbon-lean and carbon-rich polymerizing etch gases in independent inner and outer gas injection zones: A plasma etch process for etching high aspect ratio openings in a dielectric film on a workpiece is carried out in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a first polymerizing etch process gas through a radially... Agent: Robert W. Wallace Law Office Of Robert M. Wallace

20070254487 - Submicron device fabrication: A method for fabricating substrate material to include trenches and unreleashed beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer is accreted to the first oxide... Agent: Honeywell International Inc.

20070254488 - Methods for forming roughened surfaces and applications thereof: Methods of forming a roughened metal surface on a substrate are provided, along with structures comprising such roughened surfaces. In preferred embodiments roughened surfaces are formed by selectively depositing metal or metal oxide on a substrate surface to form discrete, three-dimensional islands. Selective deposition may be obtained, for example, by... Agent: Knobbe Martens Olson & Bear LLP

20070254489 - Method for removing a halogen-containing residue: The invention provides for a method and integrated system for removing a halogen-containing residue from a substrate comprising etching the substrate, heating the substrate and exposing the heated substrate to a plasma that removes the halogen-containing residue.... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070254490 - Method of making a microelectronic and/or optoelectronic circuitry sheet: A circuitry sheet comprising an electronic device layer stack containing electronic devices, e.g., thin-film transistors, or portions thereof, formed by removing material from both sides of the device layer stack. The circuitry sheet may be made by an electronic/optoelectronic device manufacturing method that includes the steps of forming the device... Agent: Downs Rachlin Martin PLLC

20070254491 - Protective layer for a low k dielectric film and methods of forming the same: A semiconductor stack having a protective layer formed into a low k dielectric material is provided. The method for forming the protective layer in a low k dielectric material may include plasma etching the low k dielectric material to form Si—OH bonds on a surface of the low k dielectric... Agent: Dugan & Dugan, PC

20070254492 - Technique for forming a silicon nitride layer having high intrinsic compressive stress: By forming a compressively stressed silicon nitride material on the basis of a mixed frequency plasma-enhanced chemical vapor deposition (PECVD) process, a higher compressive stress may be achieved at a reduced defect rate compared to conventional single frequency processes. Consequently, a more efficient strain-inducing mechanism for P-channel transistors and a... Agent: Williams, Morgan & Amerson

20070254494 - Faceplate with rapid temperature change: The present invention relates to a thermal unit comprising a faceplate with rapid temperature change capabilities. The methods and components of the present invention may be used in post-exposure bake processes where varied temperatures are used. In accordance with the advantages of the present invention, the thermal units and faceplates... Agent: Townsend And Townsend And Crew, LLP

20070254493 - Integrated thermal unit having vertically arranged bake and chill plates: An integrated thermal unit comprising a housing; a bake station positioned within the housing, the bake station comprising a bake plate configured to heat a substrate supported on a surface of the bake plate; a chill station positioned within the housing, the chill station comprising a chill plate configured to... Agent: Townsend And Townsend And Crew, LLP