Semiconductor device manufacturing: process inventions 11/07

20070275484 - Ferroelectric memory and method for manufacturing the same: A method for manufacturing a ferroelectric memory, comprising the steps of: (a) forming a conductive layer; (b) heating a surface of the conductive layer in an atmosphere containing nitrogen; (c) forming an orientation control layer above the conductive layer; (d) forming a first electrode above the orientation control layer; (e)... Agent: Harness, Dickey & Pierce, P.L.C

20070275489 - Reflective electrode for a semiconductor light emitting apparatus: A process is disclosed for forming a reflective electrode on a semiconductor light emitting device, the light emitting device having an active layer for generating light and a cladding layer in electrical contact with the active layer. The process involves depositing an intermediate layer of electrically conductive material on the... Agent: Patent Law Group LLP

20070275497 - Method of aligning a substrate, mask to be aligned with the same, and flat panel display apparatus using the same: A method of aligning a substrate includes forming a first alignment hole in the substrate, preparing a mask with a second alignment hole narrower than the first alignment hole, modifying a surface reflectance around either the first alignment hole or the second alignment hole to form a treatment region, positioning... Agent: Lee & Morse, P.C.

20070275498 - Enhancing performance in ink-jet printed organic semiconductors: Systems and methods are provided to improve the performance of electronic and optoelectronic devices made using organic semiconductor processing technology. An ink-jet device dispenses an organic composite mixture onto a substrate. The mixture includes a semiconducting polymer and nanomaterials dispersed into an organic solvent. The type of solvent used preferably... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070275499 - Nonostructure arrays and methods of making same: A method of making a nanostructure array including disposing a masking material on a nanoporous template such that a first number of the plurality of nanopores are fully coated while a second number of the plurality of nanopores are not-fully coated by the masking material is provided. The method includes... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20070275500 - Wiring and organic transistor, and manufacturing method thereof: The organic transistor has electrodes whose bodies are formed mainly of an inexpensive first metal and whose surfaces are formed of a second metal that is expensive but provides high performance properties. To obtain stability of this structure with a low cost, the present invention uses a property of the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070275485 - Real-time gate etch critical dimension control by oxygen monitoring: A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow... Agent: Law Office Of Jeffrey M. Weinick, LLC

20070275486 - Equipment and method for processing semiconductor: Semiconductor processing equipment includes a transfer chamber (3) having a plurality of transfer ports (33) arranged at different positions in a lateral direction. A process chamber (4A) for performing a semiconductor process to a substrate (W) to be processed is connected with the transfer chamber (3) through one of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070275487 - Free-standing electrostatically-doped carbon nanotube device and method for making same: A method and associated structure for forming a free-standing electrostatically-doped carbon nanotube device is described. The method includes providing a carbon nanotube on a substrate in such a way as to have a free-standing portion. One way of forming a free-standing portion of the carbon nanotube is to remove a... Agent: General Electric Company Global Research

20070275488 - Method for manufacturing backside-illuminated optical sensor: A CCD portion 3 is formed on a front surface side of a semiconductor substrate 1. A region of a back surface side of semiconductor substrate 1 that corresponds to CCD portion 3 is thinned while leaving peripheral regions 1a of the region, and an accumulation layer 5 is formed... Agent: Drinker Biddle & Reath (dc)

20070275490 - Light emitting device and method of manufacturing thereof: A device of forming a film from an organic compound material at low cost is provided, using an organic compound material having high light emission efficiency. An organic compound film is formed on a substrate under an inert gas atmosphere by spraying of a colloid solution in which organic compound... Agent: Nixon Peabody, LLP

20070275491 - Methods of manufacturing interferometric modulators with thin film transistors: A modulator has a transparent substrate with a first surface. At least one interferometric modulator element resides on the first surface. At least one thin film circuit component electrically connected to the element resides on the surface. When more than one interferometric element resides on the first surface, there is... Agent: Knobbe, Martens, Olson & Bear, LLP

20070275492 - Hybrid integration based on wafer-bonding of devices to aisb monolithically grown on si: Exemplary embodiments provide a semiconductor fabrication method including a combination of monolithic integration techniques with wafer bonding techniques. The resulting semiconductor devices can be used in a wide variety of opto-electronic and/or electronic applications such as lasers, light emitting diodes (LEDs), phototvoltaics, photodetectors and transistors. In an exemplary embodiment, the... Agent: Mh2 Technology Law Group

20070275493 - Method of manufacturing image display device and method of dividing device: A manufacturing method of manufacturing an image display device having a wiring and a display element electrically connected to the wiring, comprises a step of dividing a device having the wiring and a substrate holding the wiring, at a predetermined division position, and the dividing step further comprises a step... Agent: Fitzpatrick Cella Harper & Scinto

20070275495 - Method for fabricating a pressure sensor using soi wafers: A pressure sensor is manufactured by joining two wafers (1a, 14), the first wafer comprising CMOS circuitry and the second being an SOI wafer. A recess is formed in the top material layer of the first wafer, which is covered by the silicon layer of the second wafer to form... Agent: Richard F. Jaworski Cooper & Dunham LLP

20070275494 - Pressure sensor having a chamber and a method for fabricating the same: A pressure sensor is manufactured by joining two wafers, the first wafer comprising CMOS circuitry and the second being an SOI wafer. A recess is formed in the top material layer of the first wafer, which is covered by the silicon layer of the second wafer to form a cavity.... Agent: Richard F. Jaworski Cooper & Dunham LLP

20070275496 - Solid-state imaging device and method of manufacturing same: A solid-state imaging device includes: a substrate; a photo-receiving portion formed in the substrate; a wiring layer formed on the substrate and having a trench being formed on a region directly above the photo-receiving portion; and a light guiding member provided in the trench and made of organic material. An... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070275501 - Fabricating tft having fluorocarbon-containing layer: A process for fabricating a thin film transistor comprising: (a) forming a gate dielectric; (b) forming a layer including a substance comprising a fluorocarbon structure; and (c) forming a semiconductor layer including a thiophene compound comprising one or more substituted thiophene units, one or more unsubstituted thiophene units, and optionally... Agent: Patent Documentation Center

20070275502 - Air cavity wafer level packaging assembly and method: A wafer level packaging method and assembly for packaging a wafer segment having active and inactive areas. A sacrificial layer is provided over the wafer segment. Then the sacrificial layer is modified to create a sacrificial structure having sacrificial layer openings which expose inactive areas. A cover layer is then... Agent: Bereskin And Parr

20070275504 - Electronic component mounting structure: Such electronic component mounting structure comprises a substrate and a quadrate electronic component mounted on the substrate, wherein a gap between the substrate and the electronic component is filled with a first cured resin filling at least a corner area of the electronic component and a second cured resin filling... Agent: Loctite Corporation

20070275503 - Method for fabricating chip package: The present invention provides a method for fabricating chip package comprises the following steps: forming a photoresist layer on a metal layer over a passivation layer, an opening in the photoresist layer exposing the metal layer, wherein said forming the photoresist layer comprises exposing the photoresist layer using 1X stepper... Agent: Megica Corporation

20070275505 - Camera device, method of manufacturing a camera device, wafer scale package: The invention relates to a camera device and a method for manufacturing such a device. The camera device comprises an image capturing element, a lens element for imaging an object at the image capturing element and a spacer means for maintaining a predetermined distance along the main optical axis through... Agent: Wood, Phillips, Katz, Clark & Mortimer

20070275506 - Semiconductor device and a method of manufacturing the same: It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the... Agent: Eric Robinson

20070275507 - Molding apparatus for manufacturing semiconductor device and method using the same: The present invention provides a molding apparatus for encapsulating a semiconductor substrate in which a plurality of semiconductor chips are formed and a method of manufacturing the semiconductor substrate using the same. The molding apparatus includes an upper half for fixing the semiconductor substrate and a lower half having a... Agent: Rabin & Berdo, PC

20070275508 - Memory device with high dielectric constant gate dielectrics and metal floating gates: A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070275509 - Method of manufacturing nor-type mask rom device and semiconductor device including the same: A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed... Agent: Lee & Morse, P.C.

20070275510 - Metal oxide field effect transistor with a sharp halo and a method of forming the transistor: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070275512 - Method for manufacturing thin film transistor substrate using maskless exposing device: A method for manufacturing a thin film transistor substrate using a maskless exposing device includes forming a data metal layer on a substrate having a gate pattern and common electrodes along with gate insulation layers, active layers, and ohmic contact layers for a thin film transistors; forming a photoresist on... Agent: Seyfarth Shaw, LLP

20070275511 - Method of fabricating thin film transistor: A method for fabricating a thin film transistor is provided. A conductive layer is formed on a substrate. A patterned mask is formed on the conductive layer to cover a predetermined thin film transistor (TFT) area, and at least one portion of the conductive layer exposed by the patterned mask... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070275513 - Formation of shallow sige conduction channel: m

20070275514 - Semiconductor device and method of manufacturing same: Semiconductor device is prevented from undergoing decline in characteristics and reliability even if width of isolation trench is reduced. Semiconductor device includes: substrate obtained by building up second silicon substrate on first silicon substrate via silicon oxide film; element-forming region in which elements (gate electrode and source/drain region) have been... Agent: Mcginn Intellectual Property Law Group, PLLC

20070275515 - Deep buried channel junction field effect transistor (dbcjfet): A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside... Agent: Texas Instruments Incorporated

20070275517 - Dual poly deposition and through gate oxide implants: Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off,... Agent: Texas Instruments Incorporated

20070275521 - Method of manufacturing hollow micro-needle structures: A method of manufacturing a hollow micro-needle structure includes the steps of: disposing a first mask layer and a second mask layer respectively aside a first substrate and aside a rear surface of the first substrate, wherein the first substrate is transparent to predetermined light; forming a photoresist layer on... Agent: Birch Stewart Kolasch & Birch

20070275519 - Method of manufacturing non-volatile memory device: A method of manufacturing a non-volatile memory device includes the steps of forming gates respectively having a structure in which a gate insulating layer, a first conductive layer, a dielectric layer, a second conductive layer and a metal-silicide layer are laminated over a semiconductor substrate, annealing the metal-silicide layer at... Agent: Marshall, Gerstein & Borun LLP

20070275520 - Method of manufacturing semiconductor device: An object of the present inventions is to overcome a problem that the presence of a metal film, which is opaque to a visible light, between a lower layer alignment mark and a photoresist prevents the detection of the lower layer alignment mark, to make the pattern formation difficult. In... Agent: Foley And Lardner LLP Suite 500

20070275518 - Pixel structure and fabrication method thereof: A pixel structure and a fabrication method thereof are provided. The pixel comprises a substrate, a gate, a gate insulating layer, a channel layer, a first source/drain, a second source/drain, a dielectric layer, a first pixel electrode, and a second pixel electrode. The gate is disposed on the substrate and... Agent: Jianq Chyun Intellectual Property Office

20070275516 - Manufacturing method of semiconductor device: SiH3CH3 having the concentration of 1 to 10% is diluted with H2 and a portion of the diluted SiH3CH3, GeH4 and SiH4 (or DCS) are respectively supplied to a chamber of an epitaxial device at predetermined flow rates, and SiGe:C is formed by an epitaxial growth technique. By diluting the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070275522 - Method to enhance cmos transistor performance by inducing strain in the gate and channel: A method of manufacturing complementary metal oxide semiconductor transistors forms different types of transistors such as N-type metal oxide semiconductor (NMOS) transistors and P-type metal oxide semiconductor (PMOS) transistors (first and second type transistors) on a substrate. The method forms an optional oxide layer on the NMOS transistors and the... Agent: Frederick W. Gibb, Iii Mcginn & Gibb, PLLC

20070275523 - Trench-capacitor dram device and manufacture method thereof: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched... Agent: North America Intellectual Property Corporation

20070275524 - Semiconductor device fabrication method: In fabrication of a semiconductor device which is provided with resistances and MOS transistors on the same substrate, preventing conduction failures of contacts and preventing leaching of wiring metal into a silicon substrate. Firstly, an underlying structure is prepared. Then, a silicon oxide layer is formed on the underlying structure.... Agent: Volentine & Whitt PLLC

20070275525 - Capacitive substrate and method of making same: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20070275526 - Methods of programming memory cells using manipulation of oxygen vacancies: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070275527 - Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making: Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source... Agent: Merchant & Gould PC

20070275528 - Method of manufacturing semiconductor device: A dummy oxide film having a film thickness that is the same as that of a gate oxide film of a high voltage transistor is formed on a gate electrode of a transistor, and the dummy oxide film and the gate oxide film formed on a substrate surface are removed... Agent: Volentine & Whitt PLLC

20070275529 - Semiconductor device manufacturing method: After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating film to be a first gate insulating film is formed on each of the first and third active regions, and then,... Agent: Mcdermott Will & Emery LLP

20070275531 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device includes forming a gate over a semiconductor substrate in which a cell region, a low voltage region and a high voltage region are defined. First ions are implanted into the cell region to form doped junctions in the cell region, the low... Agent: Townsend And Townsend And Crew, LLP

20070275530 - Semiconductor structure and fabricating method thereof: A semiconductor structure and a method of fabricating the same are provided. A substrate having a metal-oxide-semiconductor transistor is provided. The metal-oxide-semiconductor transistor includes a gate, a source/drain extended region, a first spacer, a liner, a source/drain and a metal silicide layer. A portion of the first spacer is removed... Agent: Jianq Chyun Intellectual Property Office

20070275532 - Optimized deep source/drain junctions with thin poly gate in a field effect transistor: A semiconductor structure in which the poly depletion and parasitic capacitance problems with poly-Si gate are reduced is provided as well as a method of making the same. The structure includes a thin poly-Si gate and optimized deep source/drain doping. The method changes the sequence of the different implantations steps... Agent: Scully Scott Murphy & Presser, PC

20070275533 - Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance: The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first conductive contact is located over the front surface of... Agent: Scully Scott Murphy & Presser, PC

20070275534 - Varied impurity profile region formation for varying breakdown voltage of devices: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the... Agent: Hoffman, Warnick & D'alessandro LLC

20070275535 - Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base.... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070275536 - Mim capacitor: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070275537 - Formation of improved soi substrates using bulk semiconductor wafers: The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical... Agent: Scully Scott Murphy & Presser, PC

20070275538 - Method with high gapfill capability for semiconductor devices: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a... Agent: Townsend And Townsend And Crew, LLP

20070275541 - Back side wafer dicing: Systems and methods for scribing a semiconductor wafer with reduced or no damage or debris to or on individual integrated circuits caused by the scribing process. The semiconductor wafer is scribed from a back side thereof. In one embodiment, the back side of the wafer is scribed following a back... Agent: Electro Scientific Industries/stoel Rives, LLP

20070275540 - Backside via formation prior to die attachment: Backside via formation in one or more dice prior to the one or more dice being attached to an underlying substrate is described herein. The resulting backside vias having substantially no air voids or air voids occupying not greater than 8 percent of the total volume of the backside vias.... Agent: Schwabe, Williamson & Wyatt, P.C.

20070275539 - Method of stimulating die circuitry and structure therefor: A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further... Agent: Freescale Semiconductor, Inc. Law Department

20070275542 - Substrate separation method and liquid ejecting head production method using the substrate separation method: The invention provides a substrate separation method for separating a substrate into a plurality of chips. The substrate separation method according to the invention includes: a first step of irradiating a laser beam on boundary lines of each area, which constitutes a chip, of the substrate, while concentrating the beam... Agent: Workman Nydegger

20070275544 - Fabrication method of semiconductor device: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum... Agent: Miles & Stockbridge PC

20070275543 - Manufacturing method of a semiconductor device: This invention aims at improvement in reliability of a semiconductor device. In this invention, a semiconductor wafer is irradiated with laser light so as to have a fractured layer formed in the interior of the semiconductor wafer, the semiconductor wafer is mounted on a dicing tape via paste (adhesive layer),... Agent: Miles & Stockbridge PC

20070275545 - Higher selectivity, method for passivating short circuit current paths in semiconductor devices: Certain modifications and additions to the prior art short passivation technique have lead to improvements in the low light voltage of solar cells which are made using the improved passivation technique. Examples of the modifications include: 1) reducing the voltage bias on the cell while increasing the time of application... Agent: Energy Conversion Devices, Inc.

20070275546 - Electrolyte for photovoltaic device as well as photovoltaic device and dye-sensitized solar cell including that electrolyte: An electrolyte for a photovoltaic device including (i) a layered clay mineral and/or an organically modified layered clay mineral and (ii) an ionic liquid as well as a photovoltaic device including a photoelectrode including a transparent conducting layer and a metal oxide semiconductor mesoporous film using, as an electrolyte layer,... Agent: Connolly Bove Lodge & Hutz LLP

20070275547 - Integrated circuit structure and manufacturing method thereof: An integrated circuit structure is described, and includes a substrate, a contact window, and a Schottky contact metal layer. A heavily doped region and a lightly doped region are formed in the substrate. The contact window is disposed above the heavily doped region, and the Schottky contact metal layer is... Agent: J.c. Patents

20070275548 - Method and structure for reducing contact resistance between silicide contact and overlying metallization: A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu... Agent: Scully Scott Murphy & Presser, PC

20070275550 - Barrier layer for fine-pitch mask-based substrate bumping: A structure that may be used in substrate solder bumping comprises a substrate (110), a solder resist layer (120) disposed over the substrate, a plurality of solder resist openings (121) in a surface (122) of the solder resist layer, a conformal barrier layer (130) having a first portion (131) over... Agent: Intel Corporation C/o Intellevate, LLC

20070275549 - Contact surrounded by passivation and polymide and method therefor: A semiconductor device has contact between the last interconnect layer and the bond pad that includes a barrier metal between the bond pad and the last interconnect layer. Both a passivation layer and a polyimide layer separate the last interconnect layer and the bond pad. The passivation layer is patterned... Agent: Freescale Semiconductor, Inc. Law Department

20070275551 - Shapes-based migration of aluminum designs to copper damascene: An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.... Agent: Schmeiser, Olsen & Watts

20070275553 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device according to the present invention includes the steps of providing a semiconductor substrate in which an element isolation region and active regions surrounded by the element isolation region are formed, forming a plurality of conductive lines disposed such that the conductive lines cross... Agent: Mcginn Intellectual Property Law Group, PLLC

20070275552 - Structure for reducing lateral fringe capacitance in semiconductor devices and method of forming the same: A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.... Agent: Cantor Colburn LLP - IBM Fishkill

20070275554 - Semiconductor device with interconnection structure for reducing stress migration: The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the... Agent: Sughrue Mion, PLLC

20070275555 - Method of forming an electrical contact in a semiconductor device using an improved self-aligned contact (sac) process: A contact for a semiconductor device is made by performing, inter alia, a CMP process on an interlayer insulation layer to expose a first hard mask layer of each conductive line. The interlayer insulation layer is partially removed. A second hard mask layer is formed on a resultant substrate. Another... Agent: Ladas & Parry LLP

20070275556 - Fabrication method: A method for forming a multilevel structure on a surface by depositing a curable liquid layer on the surface; pressing a stamp having a multilevel pattern therein into the liquid layer to produce in the liquid layer a multilevel structure defined by the pattern; and, curing the liquid layer to... Agent: Anne Vachon Dougherty

20070275557 - Formation of oxidation-resistant seed layer for interconnect applications: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to... Agent: Scully, Scott, Murphy & Presser, P.C.

20070275558 - Method for manufacuturing semiconductor device: The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a metal interconnect on a substrate; forming a refractory metal layer containing titanium (Ti) or tantalum (Ta) on a surface of the metal interconnect; forming an insulating interlayer so as to cover the refractory metal layer;... Agent: Mcginn Intellectual Property Law Group, PLLC

20070275559 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device which an etch-prevention layer, first and second interlayer insulating layers, and first, second and third hard mask layers are sequentially formed on a semiconductor substrate. The third hard mask layer is etched to expose a portion of a region on the second... Agent: Marshall, Gerstein & Borun LLP

20070275560 - Method of manufacturing semiconductor device: A low dielectric constant film containing a silicon, a carbon, an oxygen, and a hydrogen is formed on a substrate as a semiconductor wafer, and a resist film is formed on the low dielectric constant film. Then, the low dielectric constant film is etched with the use of the resist... Agent: Smith, Gambrell & Russell

20070275561 - Gas switching during an etch process to modulate the characteristics of the etch: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while... Agent: Texas Instruments Incorporated

20070275562 - Apparatus and method for treating substrate, and injection head used in the apparatus: Provided are an injection head, and a substrate treatment apparatus and method using the same. The substrate treatment apparatus includes a rotatable spin head supporting a substrate, an injection head installed on the spin head to supply a fluid to a bottom surface of the substrate supported on the spin... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070275563 - Mask forming and implanting methods using implant stopping layer and mask so formed: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing... Agent: Hoffman, Warnick & D'alessandro LLC

20070275564 - Etching method and storage medium: An etching method which makes it possible to obtain a desired etching shape with ease, and a computer-readable storage medium storing a program for implementing the method. The etching method is executed by a substrate processing apparatus that performs plasma processing on a semiconductor wafer by plasma. The apparatus comprises... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070275565 - Full removal of dual damascene metal level: A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070275566 - Method of producing semiconductor substrate: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not... Agent: Sughrue Mion, PLLC

20070275567 - Methods of manufacturing metal oxide nanowires: Metal oxide nanowires are being investigated to make nanodevices and nanosensors. High operation temperatures or vacuum is required in the manufacturing of metal oxide nanowires by existing vapour phase evaporation methods. This invention provides a method of manufacturing metal oxide nanowires by first providing a metal to form a non-linear... Agent: Buchanan, Ingersoll & Rooney PC

20070275568 - Insulation film forming method, insulation film forming system, and semiconductor device manufacturing method: In a CVD apparatus (111), a reforming process is performed on a porous low dielectric constant film containing silicon, by heating a semiconductor wafer W by a heater, introducing 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS), and performing heat treatment without applying a high frequency voltage. Then, in the same CVD apparatus (111), an insulation... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070275569 - Methods and apparatus for e-beam treatment used to fabricate integrated circuit devices: One embodiment of the present invention is a method for fabricating a dielectric film, comprising chemical vapor depositing a dielectric film, and curing the dielectric film, wherein the dielectric film comprises silicon and carbon, and the chemical vapor depositing utilizes a precursor comprising one or more organo-silicon compounds and one... Agent: Patterson & Sheridan, LLP

20070275570 - Heat treatment apparatus: A heat treatment device where intervals between substrates supported by a supporter is reduced so that the number of substrates to be treated can be increased. A heat treatment device has a reaction furnace for treating substrates and a supporter for supporting the substrates in plural stages in the reaction... Agent: Oliff & Berridge, PLC

20070269907 - Novel conductor layout technique to reduce stress-induced void formations: A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the... Agent: Tung & Associates Randy W. Tung

20070269908 - Method for in-line controlling hybrid chemical mechanical polishing process: A hybrid CMP system having a first platen and a second platen is provided. Two types of polish pads are mounted on the first platen and second platen. A lot of pattern wafers is prepared. Each pattern wafer has patterned features, and a first dielectric layer is disposed over a... Agent: North America Intellectual Property Corporation

20070269911 - Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in: Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inserted into memory-module burn-in boards and placed into a burn-in oven. The memory... Agent: Stuart T Auvinen

20070269912 - In line test circuit and method for determining interconnect electrical properties and integerated circuit incorporating the same: A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and... Agent: Texas Instruments Incorporated

20070269913 - Method of fabricating light emitting diode: Disclosed herein is a method of fabricating a light emitting diode. The method comprises preparing a substrate, forming a lower semiconductor layer, an active layer and an upper semiconductor layer on the substrate, forming a photoresist pattern over the upper semiconductor layer such that a sidewall of the photoresist pattern... Agent: Marger Johnson & Mccollom, P.C.

20070269914 - Apparatus for aligning microchips on substrate and method for the same: An apparatus for aligning microelements on a substrate and a method for the same are provided. The steps of the method include providing a substrate, forming a protruding structure on the substrate, providing a microelement, forming a microdroplet on the protruding structure, and forcing the microelement to contact the microdroplet.... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070269915 - Led devices incorporating moisture-resistant seals and having ceramic substrates: A New Moisture-Resistant LED Device with Ceramic Substrate is disclosed. The Moisture-Resistant LED Device with Ceramic Substrate includes a ceramic substrate having a concave cavity, a light emitting diode (“LED”) in the concave cavity, a filler body over the LED, and a window sealed at an interface with the ceramic... Agent: Kathy Manke Avago Technologies Limited

20070269916 - Organic light emitting diode display and manufacturing method: An organic light emitting diode (OLED) display includes a substrate, a first electrode disposed on the substrate, a second electrode facing the first electrode, an emission layer disposed between the first electrode and the second electrode, and a hole transport layer disposed between the first electrode and the emission layer.... Agent: Macpherson Kwok Chen & Heid LLP

20070269921 - Method and apparatus for microjoining dissimilar materials: Disclosed are apparatus and methods that provide for electrical contacts in a substrate. For example, the apparatus may comprise a trench formed in a substrate, with an electrical contact pad formed on interior walls of the trench that comprises a narrowed opening. A conductive wire is squeezed into the trench... Agent: Law Offices Of Kenneth W. Float

20070269920 - Method of making dimple structure for prevention of mems device stiction: A MEMS device having a proof mass resiliently mounted above a substrate has projections formed on adjacent surfaces of the mass and substrate. The device is formed by creating a plurality of holes in the upper layer. A substance suitable for removing the intermediate layer without substantially removing the upper... Agent: Honeywell International Inc.

20070269923 - Semiconductor electrode containing phosphate and solar cell using the same: M

20070269924 - Patterning nanowires on surfaces for fabricating nanoscale electronic devices: contacting the surface of the substrate with a suspension of nanowires in a liquid medium to enable at least a portion of the applied nanowires to bind to at least a portion of the surface of the substrate covered with (C1) and/or not covered with (C2).... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070269909 - Method for processing an integrated circuit: Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The... Agent: N. Kenneth Burraston Kirton & Mcconkie

20070269910 - Wafer tilt detection apparatus and method: An exemplary embodiment providing one or more improvements includes a wafer tilt detection apparatus for use with a wafer processing or manufacturing device that applies a process to the wafer and which utilizes an endpoint signal for determining control of the process applied to the wafer. The wafer tilt apparatus... Agent: Pritzkau Patent Group, LLC

20070269917 - Electronic devices having a layer overlying an edge of a different layer and a process for forming the same: An electronic device includes a radiation-emitting component, a radiation-responsive component, or a combination thereof. In one embodiment, the electronic device includes a substrate and a first structure overlying the substrate. The electronic device also includes a second structure that includes a first layer, wherein the first layer has a first... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070269918 - Method of manufacturing nitride-based semiconductor light emitting device: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having an improved structure in which optical extraction efficiency is improved. The method of manufacturing a nitride-based semiconductor light-emitting device including an n-doped semiconductor layer, an active layer, a p-doped semiconductor layer, an n-electrode and a p-electrode includes: forming... Agent: Cantor Colburn, LLP

20070269919 - Controlling overspray coating in semiconductor devices: A manufacturing method, in which two device bars are bonded prior to facet coating to form a stacked bar pair. In one embodiment, each of the device bars has a p-side and an n-side, each side having a plurality of bonding pads, with at least some bonding pads located at... Agent: Mendelsohn & Associates, P.C.

20070269922 - Fingerprint detection device and method of its manufacture, and apparatus for forming a protective film: A fingerprint detection device has a fingerprint sensor chip and a diamond-like carbon (DLC) film covering the outermost surface of the sensor chip. The DLC film provides sufficient strength and enhanced electrostatic discharge withstand voltage to the fingerprint sensor chip. Thus, the DLC film protects the fingerprint sensor chip without... Agent: Robert J. Depke Lewis T. Steadman

20070269926 - Method and apparatus for forming an electrical connection to a semiconductor substrate: A device (100) may use one or more conductive elements (112) to electrically couple a substrate (116) and a cap (114). In one embodiment, an acceleration sense element may be formed on the substrate (116), and the cap (114) may be used to provide hermetic protection to the acceleration sense... Agent: Freescale Semiconductor, Inc. Law Department

20070269925 - Process for preparing a semiconductor light-emitting device for mounting: A process for preparing a semiconductor light-emitting device for mounting is disclosed. The light-emitting device has a mounting face for mounting to a sub-mount. The process involves treating at least one surface of the light-emitting device other than the mounting face to lower a surface energy of the at least... Agent: Patent Law Group LLP

20070269927 - Method for producing an optoelectronic device with patterned-metallized package body and method for the patterned metalization of a plastic-containing body: A method for patterned metallization of a plastic-containing body, which comprises the steps of producing the body via a two-component injection-molding process with at least two plastics, one of which is non-metallizable, and metallizing the body in such a way that a metallized region and a non-metallized region are formed,... Agent: Cohen, Pontani, Lieberman & Pavane

20070269929 - Method of reducing stress on a semiconductor die with a distributed plating pattern: A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may... Agent: Vierra Magen/sandisk Corporation

20070269930 - Methodology to control underfill fillet size, flow-out and bleed in flip chips (fc), chip scale packages (csp) and ball grid arrays (bga): In a method and system for underfilling a gap (140) disposed between a substrate (120) and a die (110), a selective surface (152) of the substrate (120) is treated by a plasma source. A matching surface (154) of the die (110) may be treated by the plasma source. The treating... Agent: Texas Instruments Incorporated

20070269928 - Temporary chip attach using injection molded solder: An improved method for performing an improved Temporary Chip Attach utilizing an Injection Molded Solder (IMS) process to allow efficient testing of die for creating a Known Good Die Bank. The IMS is applied to the testing substrate to form a column on the substrate. The die to be tested... Agent: International Business Machines Corporation Dept. 18g

20070269931 - Wafer level package and method of fabricating the same: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the... Agent: Marger Johnson & Mccollom, P.C.

20070269932 - Semiconductor device having post-mold nickel/palladium/gold plated leads: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The... Agent: Texas Instruments Incorporated

20070269933 - Integrated circuit encapsulation and method therefor: A device (12) may have a pressure sensitive portion (17) which is protected from corrosion by a pressure transmitting material (20). Pressure transmitting material (20) may also be used to transmit pressure to pressure sensitive portion (17). A masking material (22) may be used to define an opening (26) in... Agent: Freescale Semiconductor, Inc. Law Department

20070269934 - System and method for providing access to an encapsulated device: A method for providing access to a feature on a device wafer, and located outside an encapsulation region is described. The method includes forming a cavity in the lid wafer, aligning the lid wafer with the device wafer so that the cavity is located substantially above the feature, and removing... Agent: Jaquelin K. Spong

20070269935 - Fabrication of conductive micro traces using a deform and selective removal process: In a method of forming micro traces, stamping techniques are employed to define a target pattern of the micro traces. The stamping is applied to electrically conductive material and may be limited to pressure, but a thermal stamping approach may be utilized. Following the stamping, a portion of the conductive... Agent: Terry Mchugh Law Offices Of Terry Mchugh

20070269936 - Method of manufacturing lcd apparatus by using halftone exposure method: The present invention discloses a method of manufacturing a super large wide-angle super high-speed response LCD apparatus by using a photolithographic process for three times. The invention adopts a halftone exposure technology and a nitrogen ion doped technology to form a gate electrode, a common electrode, a pixel electrode and... Agent: Schmeiser, Olsen & Watts

20070269938 - Stacked film patterning method and gate electrode forming method: A stacked film patterning method is provided which is capable of reliably removing residual substances remaining after etching of a metal film, improving etching uniformity of a silicon film, and preventing an occurrence of etching residues. A micro-crystal film and a chromium film are sequentially formed on an insulating film... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20070269937 - Thin-film transistor and fabrication method thereof: A fabrication method of a TFT includes successively forming four thin films containing a first conductive layer, an insulation layer, a semiconductor layer, and a second conductive layer on a substrate, performing a first PEP process to pattern the four thin films for forming a semiconductor island and a gate... Agent: North America Intellectual Property Corporation

20070269939 - Flat panel display and method of fabricating the same: Disclosed is a flat panel display which comprises a substrate; a gate line formed on the substrate along a predetermined direction; and a gate electrode electrically connected to the gate line, and having a sheet resistance different from the gate line. With this configuration, a wiring resistance of the gate... Agent: H.c. Park & Associates, PLC

20070269940 - Thin film transistor and fabrication method thereof: A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at... Agent: J.c. Patents

20070269941 - Method of forming semiconductor device having a dopant-doped region: There is provided a method of forming a semiconductor device including a dopant-doped region. Lattice defect inducing element ions are implanted to a semiconductor channel layer to form a lattice defect region. After dopants are implanted to the lattice defect region, an annealing process is performed to form the dopant-doped... Agent: Mills & Onello LLP

20070269942 - Dual stress liner: A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second... Agent: International Business Machines Corporation Dept. 18g

20070269943 - Non-volatile memory and method of fabricating the same: A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner... Agent: J.c. Patents, Inc.

20070269944 - Cmos image sensor: A pixel of a complementary metal oxide semiconductor (CMOS) image sensor includes a plurality of photodiodes for sensing light to thereby generate photoelectric charges in different regions; a plurality of transfer transistors for transferring photoelectric charges of corresponding photodiodes in response to a first control signal; a floating diffusion region... Agent: Blakely Sokoloff Taylor & Zafman

20070269945 - Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator cmos devices: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs... Agent: Scully, Scott, Murphy & Presser, P.C.

20070269946 - Dynamic random access memory and fabrication method thereof: A dynamic random access memory including a substrate, an isolation structure, two transistors, two trench capacitors and two passing gates is provided. The isolation structure, including a first isolation structure and a second isolation structure, is disposed in the substrate. The second isolation structure is disposed in the substrate above... Agent: J.c. Patents, Inc.

20070269947 - Method for manufacturing nand flash memory: A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer,... Agent: J.c. Patents, Inc.

20070269948 - Non-volatile memory array and method of fabricating the same: A two-bits-per-cell flash memory cell is based on a localized trapping storage mechanism. The memory cell may be programmed via a hot hole injection mechanism and erased via a Fowler-Nordheim electron tunneling mechanism. The memory cells are arranged according to a virtual-ground wiring scheme. Gate structures of the memory cells... Agent: Edell, Shapiro & Finnan, LLC

20070269949 - Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least... Agent: Mcdermott Will & Emery LLP

20070269950 - Double gate isolation: A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a buried oxide (BOX) layer on a substrate. Independent first and second... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070269951 - Low stress sacrificial cap layer: A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300,... Agent: Texas Instruments Incorporated

20070269952 - Method of fabricating a transistor structure: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming... Agent: Ishimaru & Zahrt LLP

20070269953 - Method for the production of a bipolar transistor comprising an improved base terminal: For the production of an improved bipolar transistor comprising a low-resistance base terminal, a dielectric layer is deposited over the semiconductor substrate and is highly doped via an implantation mask. In a subsequent controlled thermal step, the dopant is then indiffused into the semiconductor substrate from the dielectric layer serving... Agent: Cohen, Pontani, Lieberman & Pavane

20070269954 - Semiconductor device including a capacitor having reduced leakage current: A process for forming bottom and top electrodes of a capacitor uses a source gas including tungsten nitride carbide (WNC) which contains no chlorine, to form an amorphous electrode film. This prevents the amorphous capacitor insulation from being crystallized, and also prevents addition of chlorine into the capacitor insulation film,... Agent: Mcginn Intellectual Property Law Group, PLLC

20070269955 - Semiconductor device and method for manufacturing same: A semiconductor device is provided which has a capacitor insulating film made up of zirconium aliminate being an amorphous film obtained by having crystalline dielectric contain amorphous aluminum oxide and having its composition of AlXZr(1-X)OY (0.05≦X≦0.3), hereby being capable of preventing, in a process of forming a capacitor of MIM... Agent: Sughrue Mion, PLLC

20070269956 - Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures: Embodiments of the invention include apparatuses and methods relating to air gap interconnect structures having interconnects protected by a sealant. In various embodiments, the sealant includes alumina or silicon nitride. In some embodiments, the interconnect structures include cobalt alloy liners and cobalt shunts to encase a conductive material.... Agent: Intel Corporation C/o Intellevate, LLC

20070269957 - Methods of fabricating semiconductor devices having isolation regions formed from annealed oxygen ion implanted regions: Methods of fabricating a semiconductor device include forming a mask pattern on a semiconductor substrate and which exposes defined regions of the semiconductor substrate. Oxygen ions are implanted into the defined regions of the semiconductor substrate using the mask pattern as an ion implantation mask. The oxygen ion implanted regions... Agent: Myers Bigel Sibley & Sajovec

20070269958 - Methods for filling trenches in a semiconductor material: Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the first dielectric layer is etched to create a recess in... Agent: Fletcher Yoder (micron Technology, Inc.)

20070269959 - Method of aligning mask layers to buried features: A method for fabricating microchip devices is provided. The method includes the steps of providing a first planar substrate, locating at least one first alignment feature in the surface of the first planar substrate, and bonding a second substrate to the surface of the first planar substrate. The method further... Agent: Delphi Technologies, Inc.

20070269960 - Fabrication of substrates with a useful layer of monocrystalline semiconductor material: A method for fabricating a semiconductor substrate. In an embodiment, this method includes the steps of transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal... Agent: Winston & Strawn LLP Patent Department

20070269961 - Semiconductor wafer and method for making the same: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT... Agent: North America Intellectual Property Corporation

20070269962 - Surface protection film peeling method and surface protection film peeling device: A film peeling device for peeling a film (11) adhered to a front surface of a wafer (20), on the back surface of which a dicing tape (3) is adhered, the wafer is integrated with a mount frame (36) into one body, comprises: a movable table (31), which can be... Agent: Christie, Parker & Hale, LLP

20070269964 - Semiconductor-on-diamond devices and associated methods: Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer... Agent: Thorpe North & Western, LLP.

20070269963 - Strained hot (hybrid orientation technology) mosfets: A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide... Agent: Schmeiser, Olsen & Watts

20070269965 - Indium nitride layer production: The invention relates to a structure usable in electronic, optical or optoelectronic engineering which comprises a substantially crystalline layer made of an alloy consisting of at least one element of the column II of the periodic elements system and/or at least one element of the column IV of the periodic... Agent: Foley And Lardner LLP Suite 500

20070269966 - Methods and apparatus for fabricating semiconductor devices having reduced implant contamination and related devices: A method of fabricating a semiconductor device includes selecting an element for implanting into a substrate. The element has at least a first isotope and a second isotope. At least one implant contaminant is identified as having a particle weight that is substantially identical to an atomic weight of the... Agent: Myers Bigel Sibley & Sajovec

20070269967 - Manufacturing method of semiconductor device: A method for manufacturing a semiconductor device is provided, which is capable of solving a junction leakage problem. According to the manufacturing method of the present invention, arsenic is implanted to reduce the series resistance after formation of a contact hole. A sidewall film is then formed on the side... Agent: Mcginn Intellectual Property Law Group, PLLC

20070269968 - Semiconductor devices including self aligned refractory contacts and methods of fabricating the same: Methods of forming semiconductor devices are provided by forming a semiconductor layer on a semiconductor substrate. A mask is formed on the semiconductor layer. Ions having a first conductivity type are implanted into the semiconductor layer according to the mask to form implanted regions on the semiconductor layer. Metal layers... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070269969 - Semiconductor structure pattern formation: Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an... Agent: Freescale Semiconductor, Inc. Law Department

20070269970 - Structure and method for forming cmos devices with intrinsically stressed silicide using silicon nitride cap: The present invention provides a semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first... Agent: Scully, Scott, Murphy & Presser, P.C.

20070269971 - Method for manufacturing semiconductor device: A method for forming a semiconductor device includes forming a bit line contact region with a line pattern and then performing a process to form a bit line so that a multi-layered bit line contact is expended, thereby preventing a short between bit line contact plugs and improving the process... Agent: Townsend And Townsend And Crew, LLP

20070269972 - Method of manufacturing a semiconductor device: Provided is a method of manufacturing a semiconductor device having an ONO film composed of a bottom silicon oxide film, a silicon nitride film and a top silicon oxide film over a substrate. The top silicon oxide film of the ONO film is formed in the following manner. A silicon... Agent: Miles & Stockbridge PC

20070269973 - Method of providing solder bumps using reflow in a forming gas atmosphere: A method of providing electrically conductive bumps on electrode pads of a microelectronic substrate. The method includes: providing a microelectronic substrate including electrode pads thereon; disposing a mask onto the substrate such that openings defined in the mask are placed in registration with the electrode pads; providing solder portions onto... Agent: Intel Corporation C/o Intellevate, LLC

20070269974 - Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon layer. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact... Agent: Myers Bigel Sibley & Sajovec

20070269976 - Method of manufacturing semiconductor device: To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070269975 - System and method for removal of photoresist and stop layer following contact dielectric etch: In device fabrication, a photoresist layer is formed on an insulation layer, above a stop layer that is supported directly on an active device structure. Holes are needed through the insulation layer to reach a contact arrangement, defined by the active device structure in which each contact is covered by... Agent: Pritzkau Patent Group, LLC

20070269977 - Method of forming a multilayer wiring by the use of copper damascene technique: In a formation method of a copper damascene multilayer wiring in a semiconductor integrated circuit device, after performing an oxidation process on a surface of copper, a heating process of 300° C. to 400° C. is performed in a reducing gas atmosphere, or a plasma annealing process is performed in... Agent: Young & Thompson

20070269978 - Process for improving copper line cap formation: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a... Agent: Slater & Matsil, L.L.P.

20070269979 - Method of forming a pattern and method of manufacturing a semiconductor device using the same: A method of forming a tungsten pattern includes forming a preliminary tungsten pattern on a substrate and partially removing a surface of the preliminary tungsten pattern using deionized water to form the tungsten pattern.... Agent: Lee & Morse, P.C.

20070269981 - Electroless treatment of noble metal barrier and adhesion layer: A method of forming an EL-Cu enhanced noble metal layer begins with providing a semiconductor substrate in a reaction chamber, wherein the semiconductor substrate includes a trench etched into a dielectric layer. Next, an organometallic precursor containing a noble metal and a reactive gas are pulsed into the reaction chamber... Agent: Intel Corporation C/o Intellevate, LLC

20070269980 - Methods for reducing contamination of semiconductor devices and materials during wafer processing: Methods of processing a semiconductor structure including a metal layer in the presence of organic material include flowing an aqueous mixture including an oxidizing agent over the semiconductor structure during processing of the semiconductor structure. Processing the semiconductor structure may include sawing the semiconductor structure and/or scrubbing the semiconductor structure... Agent: Myers Bigel Sibley & Sajovec

20070269982 - Method and device to vary growth rate of thin films over semiconductor structures: Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use of a reaction inhibitor that selectively varies a deposition rate along a surface. One specific method includes atomic layer deposition. One method shown provides high step... Agent: Schwegman, Lundberg & Woessner, P.A.

20070269984 - Method of manufacturing semiconductor device, method of manufacturing semiconductor substrate and semiconductor substrate: A method of manufacturing a semiconductor device and a semiconductor substrate including: a step of subjecting the semiconductor substrate to a wet process by relatively moving a process liquid and the semiconductor substrate during the wet process in an environment where there is not a static electricity removing effect with... Agent: Foley And Lardner LLP Suite 500

20070269983 - Ald apparatus and method: Improved apparatus and method for SMFD ALD include a method designed to enhance chemical utilization as well as an apparatus that implements lower conductance out of SMFD-ALD process chamber while maintaining full compatibility with standard wafer transport. Improved SMFD source apparatuses (700, 700′, 700″) and methods from volatile and non-volatile... Agent: Patton Boggs LLP

20070269985 - Two-step chemical mechanical polishing process: A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to... Agent: Baker & Mckenzie LLP Patent Department

20070269986 - Method, apparatus and system for use in processing wafers: The present embodiment provides for methods and systems for use in processing objects such as wafers, including polishing and/or grinding wafers. Some embodiments provide systems that include a front-end module and a processing module. The front end module couples with a storage device that stores objects for processing. The front-end... Agent: Sinsheimer Juhnke Lebens & Mcivor, LLP

20070269987 - Polishing liquid for cmp process and polishing method: An abrasive liquid for CMP process characterized by comprising an abrasive material, an aqueous solvent and an addition agent, and containing abrasive particles having a particle diameter of 20 to 80 nm by 15 weight % or more on the basis of the weight of the abrasive liquid; and a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070269988 - Method for forming contact opening: The present invention relates to a method for forming a contact opening. First, a substrate having at least a dielectric layer formed thereon is provided. Then, a photoresist layer having a first opening is formed on the dielectric layer. A plasma etching operation is performed to form a second opening... Agent: Jianq Chyun Intellectual Property Office

20070269989 - Inspection method of compound semiconductor substrate, compound semiconductor substrate, surface treatment method of compound semiconductor substrate, and method of producing compound semiconductor crystal: There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In... Agent: Mcdermott Will & Emery LLP

20070269990 - Method of removing ion implanted photoresist: A method of removing an ion implanted photoresist comprises performing first cleaning a semiconductor substrate having the ion implanted photoresist using hot deionized water to which a megasonic process is applied, first rinsing the semiconductor substrate using cold deionized water, drying the semiconductor substrate, removing the ion implanted photoresist, and... Agent: Marshall, Gerstein & Borun LLP

20070269991 - Semiconductor nanocrystal-metal complex and method of preparing the same: Disclosed herein are a semiconductor nanocrystal-metal complex and a method for preparing the same. The semiconductor nanocrystal-metal complex includes a semiconductor nanocrystal and one or more metal particles bound to the semiconductor nanocrystal. The semiconductor nanocrystal-metal complex exhibits excellent photocurrent characteristics and an improved binding force, in addition to the... Agent: Cantor Colburn, LLP

20070269992 - Compressive nitride film and method of manufacturing thereof: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane,... Agent: International Business Machines Corporation Dept. 18g

20070269993 - Method for forming poly-silicon film: A method for forming a poly-silicon film, using sequential lateral solidification (SLS) by laser irradiation through an optical device to pattern the laser beam and provide a periodic energy profile on the edges of transparent regions so as to widen the poly-silicon grains and achieve grain size uniformity. The optical... Agent: Birch Stewart Kolasch & Birch

20070269994 - Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semicondu: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate... Agent: Wells St. John P.s.

20070264728 - Manufacturing method of tunnel magnetoresistive effect element, manufacturing method of thin-film magnetic head, and manufacturing method of magnetic memory: A manufacturing method of a TMR element having a magnetization fixed layer, a magnetization free layer and a tunnel barrier layer sandwiched between the magnetization fixed layer and the magnetization free layer. A fabricating process of the tunnel barrier layer includes a step of depositing a first metallic material film... Agent: Buchanan, Ingersoll & Rooney PC

20070264733 - Method of manufacturing vertical gallium nitride-based light emitting diode: A method of manufacturing a vertical GaN-based LED comprises preparing an n-type GaN substrate; sequentially forming an active layer and a p-type nitride semiconductor layer on the n-type GaN substrate through an epitaxial growth method; forming a p-electrode on the p-type nitride semiconductor layer; wet-etching the lower surface of the... Agent: Lowe Hauptman Ham & Berner, LLP

20070264735 -