Semiconductor device manufacturing: process inventions 10/07

20070249065 - Manufacturing method of semiconductor device: After an interlayer insulating film and a lower side layer of a conductive film for a bottom electrode and the like are formed above a substrate, a Pt film of a thickness of 50 nm to 500 nm, for example, about 175 nm is formed on the lower side layer... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070249072 - Method and apparatus for producing interferometric lithography patterns with circular symmetry: Exemplary embodiments provide optical systems and methods for producing interferometric lithography (IL) patterns with circular symmetry for applications such as memory devices including CD ROMs, DVDs, magnetic hard disk storage, and the like. Specifically, one or more axicon optics can be configured in the optical systems for IL patterning processes... Agent: Mh2 Technology Law Group

20070249073 - Method for determining the electrically active dopant density profile in ultra-shallow junction (usj) structures: In a method of determining that a semiconductor wafer or sample has a desirable density of electrically active dopant, minimum and maximum capacitances associated with the semiconducting material forming the wafer or sample at a first point adjacent a topside thereof are determined and minimum and maximum capacitances associated with... Agent: The Webb Law Firm, P.C.

20070249074 - Active device array substrate, color filter substrate and manufacturing methods thereof: An active device array substrate comprising a substrate, a pixel array, a partition configuration and an alignment material layer is provided. The substrate has an alignment region and a predetermined sealing region. The predetermined sealing region surrounds the alignment region. The pixel array is disposed on the substrate within the... Agent: J C Patents, Inc.

20070249066 - Ferroelectric rare-earch manganese-titanium oxides: Ferroelectric rare-earth manganese-titanium oxides and methods of their manufacture. The ferroelectric materials can provide nonvolatile data storage in rapid access memory devices.... Agent: Quine Intellectual Property Law Group, P.C.

20070249067 - Method for applying rewiring to a panel while compensating for position errors of semiconductor chips in component positions of the panel: The invention relates to a method for applying rewiring to a panel. For this purpose, a panel is provided which has a coplanar overall upper side of an upper side of a plastic compound and the upper sides of semiconductor chips. The method provides a rewiring layer with implementation of... Agent: Dicke, Billig & Czaja

20070249068 - Semiconductor device system and method for modifying a semiconductor device: A semiconductor device system and a method for modifying a semiconductor device is disclosed. In one embodiment, a function provided by a circuit positioned on the semiconductor device is replaced, modified, and/or supplemented by a function provided by a circuit positioned on a further semiconductor device.... Agent: Dicke, Billig & Czaja

20070249069 - Semiconductor devices and methods of manufacturing thereof: A method of manufacturing a semiconductor device includes providing a workpiece comprising a plurality of active areas, and analyzing the active areas to determine desired stress levels for each active area. The method includes determining at least one first active area to have a first amount of stress and at... Agent: Slater & Matsil LLP

20070249071 - Neural network methods and apparatuses for monitoring substrate processing: Aspects of the present invention include methods and apparatuses that may be used for monitoring substrate processing systems. One embodiment may provide an apparatus for obtaining in-situ data regarding processing of a substrate in a substrate processing chamber, comprising a data collecting assembly for acquiring training data related to a... Agent: Patterson & Sheridan, LLP

20070249070 - Topography compensated film application methods: Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable depth of a film to the wafer, such that the... Agent: Hoffman, Warnick & D'alessandro LLC

20070249075 - Led package and method for producing the same: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and... Agent: Rosenberg, Klein & Lee

20070249076 - Organic electroluminescent device, method of manufacturing the same, and electronic apparatus: An organic electroluminescent device comprising: an organic thin-film transistor element including at least an active layer made of an organic material; and an organic electroluminescent element driven by the organic thin-film transistor element.... Agent: Harness, Dickey & Pierce, P.L.C

20070249080 - Magnetic field sensing device and a fabricating method of the same: A magnetic field sensing device and a fabrication method of the same featuring an easy planarization process for a substrate and a simplified procedure by the benefit of a slim planarizing substance. The magnetic field sensing device includes a substrate with a well of a predetermined depth and a plurality... Agent: Sughrue Mion, PLLC

20070249078 - Non-planar surface structures and process for microelectromechanical systems: Methods of making MEMS devices including interferometric modulators involve depositing various layers, including stationary layers, movable layers and sacrificial layers, on a substrate. Apertures are formed in one or more of the various layers so as to form a non-planar surface on the movable and/or the stationary layers. Other layers... Agent: Knobbe, Martens, Olson & Bear, LLP

20070249079 - Non-planar surface structures and process for microelectromechanical systems: Methods of making MEMS devices including interferometric modulators involve depositing various layers, including stationary layers, movable layers and sacrificial layers, on a substrate. A non-planar surface is formed on one or more layers by flowing an etchant through a permeable layer. In one embodiment the non-planar surface is formed on... Agent: Knobbe, Martens, Olson & Bear, LLP

20070249077 - Photo diode and related method for fabrication: A method for fabricating a photo diode first involves providing a substrate. A doping area is then formed on the substrate. Afterwards, a dielectric layer, and a first poly-silicon layer are formed on the substrate. An opening is then formed to expose a surface of the doping area. A second... Agent: North America Intellectual Property Corporation

20070249081 - Non-planar surface structures and process for microelectromechanical systems: Methods of making MEMS devices including interferometric modulators involve depositing various layers, including stationary layers, movable layers and sacrificial layers, on a substrate. Voids are formed in one or more of the various layers so as to form a non-planar surface on the movable and/or the stationary layers. The voids... Agent: Knobbe, Martens, Olson & Bear, LLP

20070249082 - Manufacturing method of mems structures and manufacturing method of mems structures with semiconductor device: The objects of the present invention are to form MEMS structures of which stress is controlled while maintaining the performance of high-performance LSI, to integrate MEMS Structures and LSI on a single chip, to electrically and chemically protect the MEMS structure and to reduce the stress of the whole movable... Agent: Stanley P. Fisher Reed Smith LLP

20070249083 - Multilevel phase-change memory element and operating method: A multilevel phase-change memory, operating method and manufacturing method thereof. The phase-change memory includes two phase-change layers and electrodes, which are configured in a parallel structure to form a memory cell. A voltage-drive mode is employed to control and drive the memory such that multilevel memory states may be achieved... Agent: Rabin & Berdo, PC

20070249084 - Active matrix display device and method of manufacturing the same: In an active matrix display device integrated with peripheral drive circuits, an image sensor is provided on the same substrate as a pixel matrix and peripheral drive circuits. The image sensor is formed on the substrate having pixel electrodes, pixel TFTs connected to the pixel electrodes and CMOS-TFTs for driving... Agent: Eric Robinson

20070249085 - Solar cell and method of fabricating the same: A method of fabricating a solar cell forms a large number of grooves on a first main surface of a p-type silicon single crystal substrate sliced out from a silicon single crystal ingot as described below. First an edge portion of a groove-carving blade is projected out from a flat... Agent: Snider & Associates

20070249086 - Phase change memory: A memory cell includes a first electrode, a second electrode, a layer of phase change material positioned between the first and second electrodes, and a stress layer contacting the layer of phase change material. The phase change material includes a high temperature state, and the stress layer defines an interface... Agent: Dicke, Billig & Czaja

20070249088 - Electronic device and manufacturing method therefor: A manufacturing method for an electronic device, the method including forming a transparent conductive film, including conductive polymers, on a base material, and irradiating ultraviolet light onto a part of the transparent conductive film such that first regions of the transparent conductive film are not irradiated and second regions, adjacent... Agent: Sughrue Mion, PLLC

20070249087 - Electronic devices containing acene-thiophene copolymers with silylethynyl groups: Electronic devices that include an acene-thiophene copolymer and methods of making such electronic devices are described. More specifically, the acene-thiophene copolymer has attached silylethynyl groups. The copolymer can be used, for example, in a semiconductor layer or in a layer positioned between a first electrode and a second electrode.... Agent: 3m Innovative Properties Company

20070249089 - Method of making circuitized substrate with internal organic memory device: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20070249090 - Phase-change memory cell adapted to prevent over-etching or under-etching: A memory cell includes a first electrode and a second electrode. The second electrode has a first layer and a second layer. The first layer has a lower etch rate relative to the second layer. The memory cell includes a phase-change material positioned between the first electrode and the second... Agent: Dicke, Billig & Czaja

20070249091 - Micro device encapsulation: A packaged die includes a substrate having an upper surface and a micro device on the upper surface and an encapsulation cover comprising one or more grooves on its lower surface. The lower surface of the encapsulation cover and the upper surface of the substrate are bonded together to form... Agent: Fish & Richardson P.C.

20070249092 - Semiconductor die package including multiple dies and a common node structure: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at... Agent: Townsend And Townsend And Crew, LLP

20070249093 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device comprises a semiconductor chip, a wiring layer formed on the semiconductor chip, a column electrode connected at a first end to the wiring layer, and an encapsulation resin formed on the semiconductor chip. In the semiconductor device, the column electrode is provided with a second end, opposite... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070249094 - Method for fabricating multi-chip semiconductor package: A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper... Agent: Edwards Angell Palmer & Dodge LLP

20070249095 - Semiconductor package and method of manufacturing the same: Disclosed herein are a semiconductor package used in digital optical instruments and a method of manufacturing the same. The semiconductor package comprises a wafer made of a silicon material and having pad electrodes formed at one side surface thereof, an IR filter attached on the pad electrodes of the wafer... Agent: Lowe Hauptman Ham & Berner, LLP

20070249096 - Method of forming a metal line and method of manufacturing a display substrate by using the same: In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070249097 - Method of forming a metal line and method of manufacturing a display substrate by using the same: In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070249098 - Bonding plate mechanism for use in anodic bonding: A bonding plate mechanism for use in anodic bonding of first and second material sheets together, the apparatus comprising: a base including first and second spaced apart surfaces; a thermal insulator supported by the second surface of the base and operable to impede heat transfer to the base; a heating... Agent: Corning Incorporated

20070249100 - Carrierless chip package for integrated circuit devices, and methods of making same: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each... Agent: Williams, Morgan & Amerson

20070249099 - Method of and apparatus for manufacturing elements: A method of separating individual elements (e.g. conducting preforms or Gunn diodes) from an array of such elements comprises the application of energy (e.g. electric current) via a pick-up tool to melt tabs which hold the element to a supporting structure.... Agent: Venable LLP

20070249101 - Method for fabricating semiconductor package free of substrate: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the... Agent: Edwards Angell Palmer & Dodge LLP

20070249102 - Panel and semiconductor device having a structure with a low-k dielectric: A panel and a semiconductor device, in one embodiment composed of a composite plate with semiconductor chips and plastic housing composition and to a method for producing the same is disclosed. The embodiments include a wiring structure with interconnects and dielectric layers composed of a low-k dielectric is arranged on... Agent: Dicke, Billig & Czaja

20070249103 - Method of making a multi-gate device: A semiconductor device has two types of multi-gate transistors, N channel and P channel, in which each type has a bottom gate and a top gate. The bottom gate and the top gate of the N channel transistors are chosen to be of a metal or metals that are for... Agent: Freescale Semiconductor, Inc. Law Department

20070249104 - Method for fabricating a thin-film transistor: A method for fabricating a thin-film transistor contains successively forming four thin films on a substrate and performing an etching process to pattern the four thin films, wherein the four thin films are a first conductive layer, a first insulation layer, a semiconductor film, and a metal-containing sacrificial layer from... Agent: North America Intellectual Property Corporation

20070249105 - Liquid crystal display, thin film transistor array panel for liquid crystal display and manufacturing method thereof: A gate wire is formed on the insulating substrate. The gate wire has gate lines, first and second gate electrodes connected to the gate lines, and gate pads. A gate insulating layer, first and second semiconductor layers and an ohmic contact layer are sequentially formed thereon. A data wire is... Agent: F. Chau & Associates, LLC

20070249106 - Semiconductor device and method of manufacturing the same: It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070249107 - Touch panel and manufacturing method thereof: Proving a touch panel having a superior transparent visibility, easy to manufacture and of low cost, to be used for various electronic devices. In manufacturing, forming a notch with an adhesive layer formed on an undersurface of an under substrate, under a connecting portion of the under substrate with a... Agent: Ratnerprestia

20070249108 - Thin film transistor having ldd structure: A thin film transistor having a LDD structure that may improve its channel reliability and output characteristics. A semiconductor layer comprises source/drain regions, a channel region positioned between the source/drain regions, and an LDD region positioned between the channel region and a source/drain region, wherein a projected range of ions... Agent: H.c. Park & Associates, PLC

20070249110 - Nonvolatile memory device, method of fabricating the same, and organic lighting emitting diode display device including the same: A nonvolatile memory device may include a substrate, a semiconductor layer on the substrate, and including a source region, a drain region having a relatively shallower impurity injection region than that of the source region and a channel region disposed between the source and drain regions, a first gate insulating... Agent: Lee & Morse, P.C.

20070249109 - Optical device and optical module: A high resistance re-grown layer is disposed around an optical device having a mesa structure. Thus, a mesa portion having a plane direction that appears in etching of a circular main structure is coated with the re-grown layer. Because of this coating, it is possible to reduce the capacitance in... Agent: Mcdermott Will & Emery LLP

20070249111 - Tft array substrate and photo-masking method for fabricating same: An exemplary TFT array substrate (2) includes an insulating substrate (201); a transparent conductive line (221) formed on the insulating substrate; a plurality of gate lines (210) formed on the transparent conductive line, that are parallel to each other and that each extend along a first direction; a plurality of... Agent: Wei Te Chung Foxconn International, Inc.

20070249112 - Differential spacer formation for a field effect transistor: A method for manufacturing an integrated circuit includes providing one or more n-type field effect transistor and one or more p-type field effect transistor on a semiconductor substrate. Each of the transistors separated by a trench isolation structure. Each of the transistors has a source and drain regions formed in... Agent: International Business Machines Corporation Dept. 18g

20070249113 - Stressor integration and method thereof: A method is provided for making a semiconductor device. In accordance with the method, a substrate (203) is provided which has first (205) and second (207) gate structures thereon. A first stressor layer (215) is formed over the substrate, and a sacrificial layer (216) is formed over the first stressor... Agent: Fortkort & Houston P.C.

20070249114 - Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the... Agent: International Business Machines Corporation Dept. 18g

20070249115 - Dynamic memory cell structures: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater... Agent: Ryan, Mason & Lewis, LLP

20070249116 - Transitioning the state of phase change material by annealing: A semiconductor device includes a preprocessed wafer and an annealed phase change material layer contacting the preprocessed wafer. The semiconductor device includes a first material layer contacting the annealed phase change material layer.... Agent: Dicke, Billig & Czaja

20070249117 - Polymer resin composition, related method for forming a pattern, and related method for fabricating a capacitor: A polymer resin composition, a method for forming a pattern using the polymer resin composition, and a method for fabricating a capacitor using the polymer resin composition are disclosed. The polymer resin composition includes about 75 to 93 percent by weight of a copolymer prepared from benzyl methacrylate, methacrylic acid,... Agent: Volentine & Whitt PLLC

20070249118 - Semiconductor device and method of manufacturing the same: Recessed portions (passages) are formed in a surface of a passivation film so as to eliminate an adverse influence from air bubbles that would be generated between a surface of a semiconductor wafer and a surface protection sheet covering the surface of the semiconductor wafer during plasma etching a rear... Agent: Sughrue Mion, PLLC

20070249119 - Nitride semiconductor device: A nitride semiconductor device includes: a first semiconductor layer; a second semiconductor layer provided on the first semiconductor layer; a p-type region selectively provided in the second semiconductor layer; a gate insulating film provided on the p-type region; a field insulating film provided on the second semiconductor layer surrounding the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070249120 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070249122 - Array substrate for liquid crystal display device using organic semiconductor material and method of fabricating the same: An array substrate for a liquid crystal display device comprises a data line disposed on a substrate that has a pixel region, and source and drain electrodes disposed on the substrate. The source electrode extends from the data line and is separated from the drain electrode. The array substrate for... Agent: Brinks Hofer Gilson & Lione

20070249121 - Method of fabricating non-volatile memory: A method of fabricating a non-volatile memory is provided. The method includes providing a substrate. Next, a tunneling oxide layer is formed on the substrate and a surface nitridation process is performed to nitridize the upper surface of the tunneling oxide layer. A plurality of nanocrystals is formed on the... Agent: Jianq Chyun Intellectual Property Office

20070249123 - Method of fabricating a recess channel transistor: A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a... Agent: Birch Stewart Kolasch & Birch

20070249124 - Dmos device of small dimensions and manufacturing process thereof: In a body of semiconductor material, a field region separates a first active area and a second active area. A drain region is formed in the first active area; a body region is formed in the second active area and accommodates a source region. A body-contact region is formed inside... Agent: Graybeal, Jackson, Haley LLP

20070249125 - Flash memory device with stacked dielectric structure including zirconium oxide and method for fabricating the same: A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second dielectric layer disposed between the first dielectric... Agent: Townsend And Townsend And Crew, LLP

20070249126 - A structure and method for fabrication of deep junction silicon-on-insulator transistors: A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant... Agent: International Business Machines Corporation Dept. 18g

20070249127 - Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same: An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening... Agent: Larson Newman Abel Polansky & White, LLP

20070249129 - Sti stressor integration for minimal phosphoric exposure and divot-free topography: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer (224) disposed on a buried dielectric layer (222). A trench (229) is created in the semiconductor structure which exposes a portion of the buried... Agent: Fortkort & Houston P.C.

20070249128 - Ultraviolet (uv) radiation treatment methods for subatmospheric chemical vapor deposition (sacvd) of ozone-tetraethoxysilane (o3-teos): Dielectric layers are formed on a substrate by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O3-TEOS) to form a layer of O3-TEOS on the substrate, and treating the layer of O3-TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the O3-TEOS layer by... Agent: Myers Bigel Sibley & Sajovec

20070249130 - Finfet/trigate stress-memorization method: Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the semiconductor fin. Specifically, a protective cap layer is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070249131 - Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing... Agent: Scully Scott Murphy & Presser, PC

20070249132 - Semiconductor device with fixed channel ions: A method for manufacturing a semiconductor device includes subjecting a semiconductor substrate to thermal treatment at a temperature ranging from 770 to 830° C. to fix channel ions then forming a HTO film. The method thereby prevents a threshold voltage of a gate from changing due to diffusion of channel... Agent: Heller Ehrman LLP

20070249133 - Semiconductor device with fixed channel ions: A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20070249134 - Method and apparatus for irradiating laser: A laser irradiation process includes: scanning a substrate with laser having a predetermined lasing frequency at different irradiation intensities to form a plurality of first irradiation areas corresponding to the irradiation intensities; illuminating the first irradiation areas to reflected light receive from the fist irradiation areas; determining microcrystallization intensity based... Agent: Dickstein Shapiro LLP

20070249135 - Collector tailored structures for integration of binary junction transistors: A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic dilute mask is... Agent: Texas Instruments Incorporated

20070249136 - Silicon structures with improved resistance to radiation events: A silicon structure with improved protection against failures induced by excess radiation-induced charge carrier migration from the bulk region into the near-surface region. The structure comprises bulk and near-surface regions that are doped with a dopant, wherein the concentration in the near-surface region is at least 10 times the maximum... Agent: Senniger Powers

20070249137 - Method and system for wafer backside alignment: Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer... Agent: David M. O'dell Attorney For Applicants

20070249138 - Buried dielectric slab structure for cmos imager: A substrate structure, and method of forming the structure, are provided. The structure, which may be used for a CMOS imager device, is provided with a buried dielectric structure. Recesses are formed on a semiconductor substrate, e.g., silicon, and a dielectric material is used to fill the recesses. A layer... Agent: Dickstein Shapiro LLP

20070249140 - Method for the production of thin substrates: A method is provided for producing a thin substrate with a thickness below 750 microns, comprising providing a mother substrate, the mother substrate having a first main surface and a toughness; inducing a stress with predetermined stress profile in at least a portion of the mother substrate, said portion comprising... Agent: Knobbe Martens Olson & Bear LLP

20070249139 - Semiconductor on glass insulator made using improved thinning process: Methods and apparatus for producing a semiconductor on glass (SiOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis;... Agent: Corning Incorporated

20070249141 - Method of manufacturing electrode pattern: A method of manufacturing an electrode pattern comprises preparing a first support film; forming a mold release pattern on one surface of the first support film, the mold release pattern defining an internal electrode formation region; forming an electrode layer on the mold release pattern by using a thin film... Agent: Mcdermott Will & Emery LLP

20070249143 - Method and device of manufacturing thin substrate: An easy and low-cost method of manufacturing a thin substrate reduced in surface wobbling by bonding two thin sheets together is provided. A step of bonding thin substrate sheets together is performed by using a device in which a spacer is incorporated into a turntable provided with a through-hole for... Agent: Birch Stewart Kolasch & Birch

20070249142 - Semiconductor devices and method of manufacturing them: A semiconductor device of the present invention comprises a super junction structure in which a pair semiconductor regions, comprising of a p-type semiconductor region and an n-type semiconductor region, is disposed repeatedly along at least one direction, wherein a Si1-x-yGexCy (0≦x<1, 0<y<1, 0<-x-y<1) crystal region is disposed repeatedly along, at... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070249144 - Method of forming silicon-on-insulator wafer having reentrant shape dielectric trenches: A method for forming a bonded SOI wafer is provided in which a first wafer having a single-crystal semiconductor region has a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly into the single-crystal... Agent: International Business Machines Corporation Dept. 18g

20070249145 - Method of dividing an adhesive film bonded to a wafer: A method of dividing an adhesive film for die bonding which is bonded to the rear surface of a wafer having devices in a plurality of areas sectioned by dividing lines formed in a lattice pattern on the front surface, into pieces corresponding to the devices, comprising the steps of... Agent: Smith, Gambrell & Russell

20070249146 - Protective tape applying method: A protective tape applying method includes: preparing a substrate which has plural devices formed on a surface of the substrate; and holding the substrate on a chuck table such that a rear surface of the substrate is chucked by the chuck table and the surface of the substrate is exposed.... Agent: Brinks Hofer Gilson & Lione

20070249147 - Process and system for laser annealing and laser-annealed semiconductor film: In a laser annealing process: the first to fourth sections of a bandlike area of a nonmonocrystalline semiconductor film are consecutively scanned and irradiated with laser light so as to produce a fused region in the bandlike area, where the fourth section contains a portion required to have higher crystallinity... Agent: Sughrue Mion, PLLC

20070249148 - Method for producing a layer consisting of a doped semiconductor material: The invention concerns a method for depositing a layer consisting of a doped semiconductor material on a substrate, as well as a device for implementing said method. According to said method, the doped semiconductor material contains at least one semiconductor matrix material and at least one doping material. Said method... Agent: Schmeiser, Olsen & Watts

20070249149 - Improved thermal budget using nickel based silicides for enhanced semiconductor device performance: The use of nickel, Ni, based alloys that enables higher contact module which, in turn, provides the device designers additional gains in transistor speeds is provided. Specifically, the use of Ni based alloys for silicide formation in 90 nm technologies and beyond enables higher temperature (greater than 450° C.) processing... Agent: Scully Scott Murphy & Presser, PC

20070249153 - Chip structure with half-tunneling electrical contact to have one electrical contact formed on inactive side thereof and method for producing the same: A method for producing a chip structure with one electrical contact formed on inactive side thereof includes by pre-forming at least one half-tunneling electrical contact to penetrate a processed substrate prepared for processing a chip, and when finishing processing the chip the half-tunneling electrical contact is without completely penetrated the... Agent: Bacon & Thomas, PLLC

20070249150 - Method of forming a metal line and method of manufacturing a display substrate by using the same: In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070249152 - Method of manufacturing semiconductor apparatus: A method of manufacturing a semiconductor apparatus includes forming an electrode on a semiconductor device, forming a conductive bump on the electrode, placing an external wire on the conductive bump, and laser-welding the external wire and the conductive bump to establish electrical connection.... Agent: Foley And Lardner LLP Suite 500

20070249151 - Method of manufacturing semiconductor device and semiconductor device: Gate electrodes each covered by protective insulating films are formed, a first interlayer insulating film is formed on the entire surface including regions between the protective insulating films and on the protective insulating films, the first interlayer insulating film is polished and removed until top surfaces of the protective insulating... Agent: Sughrue Mion, PLLC

20070249154 - Method to manufacture a coreless packaging substrate: A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to... Agent: Bacon & Thomas, PLLC

20070249155 - Method to manufacture a coreless packaging substrate: A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to... Agent: Bacon & Thomas, PLLC

20070249156 - Method for enabling hard mask free integration of ultra low-k materials and structures produced thereby: A method is described for the repair of process induced damage sustained by low-k organosilicate dielectrics as a result of reactive ion etch, resist strip, wet clean and CMP operations in a hard mask free integration of these dielectrics into microelectronic interconnect structures incorporating a dielectric cap which is an... Agent: Ibm Corporation, T.j. Watson Research Center

20070249157 - Semiconductor device and method for manufacturing same: A semiconductor device includes an interconnect group (TEG region) composed of a plurality of interconnects, which elongate along a first direction in a substrate surface of the substrate, and are arranged with a minimum interconnect interval therebetween in the semiconductor device, and a third interconnect, which elongates along a second... Agent: Young & Thompson

20070249158 - Semiconductor device and manufacturing method thereof: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top... Agent: Morrison & Foerster LLP

20070249161 - Anisotropic conductive sheet and method of manufacturing the same: Disclosed is an anisotropic conductive sheet which is equipped with an insulating base portion and a plurality of conductive portions extending through the base portion in a thickness direction thereof, which easily allows temporary fixation at a time of attachment thereof, and which, if pressurized, causes no adhesive material to... Agent: Rader Fishman & Grauer PLLC

20070249162 - Semiconductor device: In the conventional technology, a region of larger data rate causes a varied level of the light exposure in the lithographic operation in the process for manufacturing the semiconductor device, causing a problem of allowing narrower process window. A semiconductor device includes interconnects (first interconnects) elongating along a first direction... Agent: Young & Thompson

20070249163 - Semiconductor device and method of manufacturing the same: The invention is directed to a semiconductor device having a via hole and a method of manufacturing the same that achieve both the prevention of a barrier layer insufficiently covering the via hole and the control of via resistance at the same time. A semiconductor substrate having a pad electrode... Agent: Morrison & Foerster LLP

20070249159 - Method for forming dielectric film to improve adhesion of low-k film: A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer... Agent: Slater & Matsil, L.L.P.

20070249160 - Process of forming an electronic device including a layer formed using an inductively coupled plasma: A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the... Agent: Larson Newman Abel Polansky & White, LLP

20070249165 - Dual damascene process: A dual damascene process is provided. A substrate having a conductive area is provided. An etching stop layer, a dielectric layer and a patterned hard mask layer are sequentially formed on the substrate. A first opening is formed in the dielectric layer exposed by the patterned hard mask layer. A... Agent: J.c. Patents, Inc.

20070249164 - Method of fabricating an interconnect structure: An interconnect structure for a semiconductor device is provided. The interconnect structure for a semiconductor device comprises a substrate having a conductive region thereon, a first dielectric layer having a modified surface portion serving as an etch stop layer and a second dielectric layer having a hardness less than that... Agent: Daniel R. Mcclure Thomas, Kayden, Horstemeyer & Risley, LLP

20070249166 - Method for fabricating a semiconductor component including a high capacitance per unit area capacitor: A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20070249167 - Cmp method for copper-containing substrates: The invention provides a chemical-mechanical polishing composition comprising an abrasive, a benzotriazole derivative, an oxidizing agent selected from the group consisting of iodate compounds, organic oxidizing agents, and mixtures thereof, and water, wherein the polishing composition comprises substantially no organic carboxylic acid having a molecular weight of less than about... Agent: Steven Weseman Associate General Counsel, I.p.

20070249168 - Crystallographic preferential etch to define a recessed-region for epitaxial growth: A semiconductor device 100 comprising a gate structure 105 on a semiconductor substrate 110 and a recessed-region 115 in the semiconductor substrate. The recessed-region has a widest lateral opening 120 that is near a top surface 122 of the semiconductor substrate. The widest lateral opening undercuts the gate structure.... Agent: Texas Instruments Incorporated

20070249169 - Mask and method of manufacturing liquid crystal display device using the same: A method for fabricating a device is disclosed. The method includes providing a substrate; forming a thin film on the substrate; forming a photoresistable layer on the thin film; irradiating light onto the photoresistable layer through a photo mask having a transmissive region, a semi-transmissive region, a diffractive region and... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070249171 - Dielectric plasma etch process with in-situ amorphous carbon mask with improved critical dimension and etch selectivity: A plasma-enhanced process is performed in a single plasma reactor chamber for etching a thin film layer on a workpiece, using a hard mask layer including an amorphous carbon layer (ACL) overlying the thin film layer and an anti-reflection coating (ARC) overlying the ACL. The process includes etching a pattern... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20070249170 - Process for improving critical dimension uniformity of integrated circuit arrays: Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features... Agent: Knobbe Martens Olson & Bear LLP

20070249173 - Plasma etch process using etch uniformity control by using compositionally independent gas feed: A plasma etch process etches high aspect ratio openings in a dielectric film on a workpiece in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through an inner annular zone of gas injection... Agent: Robert Mulcahy Law Office Of Robert W Mulcahy

20070249172 - Method for removing masking materials with reduced low-k dielectric material damage: Methods for removing masking materials from a substrate having exposed low-k materials while minimizing damage to exposed surfaces of the low-k material are provided herein. In one embodiment a method for removing masking materials from a substrate includes providing a substrate having exposed low-k materials and a masking material to... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070249174 - Patterning sub-lithographic features with variable widths: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls... Agent: International Business Machines Corporation Dept. 18g

20070249175 - Pitch-shrinking technologies for lithographic application: Two pitch-shrinking technologies are invented, which allow us to further reduce the pitch size significantly smaller than the minimum feature size resolvable with any conventional lithographic technology. One technology can be used to shrink the pitch size of both line/space (straight or wiggling) and contact-hole patterns by half from the... Agent: Yijian Chen

20070249176 - Active device array substrate and fabricating method thereof: A method of fabricating an active device array substrate is provided. A substrate having scan lines, data lines and active devices formed thereon is provided. Each of the active devices is electrically connected to the corresponding scan line and data line. An organic material layer is formed over the substrate... Agent: Jianq Chyun Intellectual Property Office

20070249177 - Method for hard mask cd trim: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and... Agent: Martine Penilla & Gencarella, LLP

20070249178 - Semiconductor device, manufacturing method of semconductor device, manufacturing equipment of semiconductor device, light emitting diode head, and image forming apparatus: The manufacturing method comprises steps of performing a first etching process to etch a separation area on a front surface of a substrate, arranging a supporter on a back surface of the first substrate to prevent semiconductor devices from coming apart, coating with a thin film a non-etching area including... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070249179 - Method of forming a low-k dielectric layer with improved damage resistance and chemical integrity: A method of forming a low-k dielectric layer or film includes forming a porous low-k dielectric layer or film over a wafer or substrate. Active bonding is introduced into the porous low-k dielectric layer or fihm to improve damage resistance and chemical integrity of the layer or film, to retain... Agent: Duane Morris LLPIPDepartment (tsmc)

20070249180 - Method of making a molecule-surface interface: This invention is generally related to a method of making a molecule-surface interface comprising at least one surface comprising at least one material and at least one organic group wherein the organic group is adjoined to the surface and the method comprises contacting at least one organic group precursor with... Agent: Winstead PC

20070249181 - Process using a broken gelled composition: A process including: (a) providing a gelable composition comprising a gelable semiconductor polymer and a liquid, wherein the polymer is at a low concentration in the liquid; (b) gelling the gelable composition to result in a gelled composition; (c) breaking the gelled composition to result in a flowable, broken gelled... Agent: Patent Documentation Center

20070249182 - Etching of sio2 with high selectivity to si3n4 and etching metal oxides with high selectivity to sio2 at elevated temperatures with bcl3 based etch chemistries: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be... Agent: Townsend And Townsend And Crew LLP / Amat

20070243640 - Method for manufacturing ferroelectric memory device: A method for manufacturing a ferroelectric memory device includes the steps of forming an active element on a substrate; forming an interlayer dielectric film on the substrate; forming a contact hole in the interlayer dielectric film; forming, in the contact hole, a contact plug that conductively connects to the active... Agent: Harness, Dickey & Pierce, P.L.C

20070243644 - Semiconductor laser device and method of manufacturing the same, and optical transmission module and optical disk apparatus using the semiconductor laser device: Provided are a semiconductor laser device capable of stable operation at the time of high power output without damage to a resonator end surface and a method of manufacturing the same, as well as an optical transmission module and an optical disk apparatus using the semiconductor laser device. A method... Agent: Harness, Dickey & Pierce, P.L.C

20070243649 - Centrifugally cast electrochemical cell components: A component for an electrochemical cell is formed using centrifugal forces to densify an electrode or electrode material. In some embodiments, a binding agent may be used to mechanically bind active material for processing and normal operation. The binding agent may be a dispersed solid material as well as a... Agent: Krajec Patent Offices, LLC

20070243648 - Manufacturing method of pixel structure: A method of manufacturing a pixel structure is provided. A gate, a scan line, and at least one first auxiliary pattern are formed on a substrate. A gate insulating layer is formed on the substrate to cover the gate and the scan line and expose the first auxiliary pattern and... Agent: J C Patents, Inc.

20070243655 - Self-aligned process for fabricating imprint templates containing variously etched features: A process that enables coplanarization of the structures that have been created in multiple independent etch steps. The various etches are performed independently by selectively exposing only certain patterns to particular etching conditions. After these structures have been created, it is possible that the various structures will exist at different... Agent: Molecular Imprints

20070243658 - Production method of crystalline organic semiconductor thin film, organic semiconductor thin film, electronic device, and thin film transistor: A method of producing a crystalline organic semiconductor thin film including the steps of: (a) coating a solution of an organic semiconductor material in a solvent onto a substrate to form a liquid coating film; and (b) crystallizing the organic semiconductor material in the liquid coating film at an edge... Agent: Cantor Colburn, LLP

20070243641 - Method for forming ferroelectric memory device: A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface... Agent: Lee & Morse, P.C.

20070243639 - Methods and apparatus for a synthetic anti-ferromagnet structure with reduced temperature dependence: A synthetic antiferromagnet (SAF) structure includes a first ferromagnetic layer, a first insertion layer, a coupling layer, a second insertion layer, and a second ferromagnetic layer. The insertion layers comprise materials selected such that SAF exhibits reduced temperature dependence of antiferromagnetic coupling strength. The insertion layers may include CoFe or... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070243638 - Novel method to form a nonmagnetic cap for the nife(free) mtj stack to enhance dr/r: An MTJ in an MRAM array or TMR read head is disclosed in which a capping layer has a bilayer configuration with a non-magnetic NiFeX inner layer on a NiFe free layer and a Ta layer on the NiFeX layer to improve dR/R and minimize magnetostriction. Optionally, a trilayer configuration... Agent: Stephen B. Ackerman

20070243642 - Method of evaluating characteristics of and forming of an insulating film for a semiconductor device: A method of evaluating characteristics of an insulating film 1 is disclosed. The insulating film 1 is formed of an insulative inorganic material as a main material, the insulative inorganic material containing silicon and oxygen. The insulating film 1 further contains hydrogen atoms. The method includes the steps of: analyzing... Agent: Harness, Dickey & Pierce, P.L.C

20070243643 - Circular test pads on scribe street area: A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe street (34) such that any cracks generated in the test... Agent: Texas Instruments Incorporated

20070243645 - High-power led chip packaging structure and fabrication method thereof: A packaging structure and a related fabrication method for high-power LED chip are provided herein, which mainly contains a base made of a metallic material and an electrically insulating material integrated into a single object. The metallic material forms a heat sinking seat in the middle of the base, which... Agent: Lin & Associates Intellectual Property

20070243646 - Led package and method for producing the same: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and... Agent: Rosenberg, Klein & Lee

20070243647 - Led package and method for producing the same: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and... Agent: Rosenberg, Klein & Lee

20070243650 - Liquid crystal display device and method of fabricating the same: A method of fabricating a liquid crystal display device includes steps of forming a first metal layer on the substrate to form a gate line including a gate electrode, a gate pad, and a first capacitor electrode, forming an insulating layer, an active layer, and a second metal layer on... Agent: Morgan Lewis & Bockius LLP

20070243651 - Organic el light emitting display device and method of manufacturing the same: Disclosed is a method for manufacturing an organic EL light emitting display device, comprising forming an anode electrode above a substrate, forming an organic light emitting layer above the anode electrode, performing a fluorinating treatment on a surface of the organic light emitting layer, and forming a cathode electrode directly... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070243653 - Methods for controllable doping of aluminum nitride bulk crystals: Fabrication of doped and undoped stoichiometric polycrystalline AlN ceramics with high purity is accomplished by, for example, reacting Al pellets with nitrogen gas. Such polycrystalline AlN ceramics may be utilized in the fabrication of high purity AlN single crystals, which may be annealed to enhance a conductivity thereof.... Agent: Goodwin Procter LLP Patent Administrator

20070243652 - Stacked-substrate processes for production of nitride semiconductor structures: Methods are provided of fabricating compound nitride semiconductor structures. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over a surface of a first substrate with a thermal chemical-vapor-deposition process. A second layer is deposited over a surface of a second... Agent: Townsend And Townsend And Crew LLP / Amat

20070243654 - Microelectromechanical device with integrated conductive shield: A microelectromechanical device and method of fabricating the same, including a layer of patterned and deposited metal or mechanical-quality, doped polysilicon inserted between the appropriate device element layers, which provides a conductive layer to prevent the microelectromechanical device's output from drifting. The conductive layer may encapsulate of the device's sensing... Agent: Honeywell International Inc.

20070243656 - Photodiode and method of manufacturing the same: A photodiode and a method of manufacturing the photodiode are provided. The method includes forming a diode junction structure including a light receiving unit and an electrode unit on a semiconductor substrate, forming a buffer oxide layer and an etching blocking layer on the junction structure, forming an interlayer insulating... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070243657 - Method and apparatus to form thin layers of materials on a base: The present invention relates to method and apparatus for preparing thin films of materials for various applications including electronic devices such as solar cells. In one aspect, each of the method and apparatus passing an electrical current through at least one of the base or sheet to provide controlled localized... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070243659 - Phase-changeable memory device and method of manufacturing the same: In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer... Agent: Marger Johnson & Mccollom, P.C.

20070243663 - Method of wafer level chip size packaging: A method of wafer level chip size packaging includes the steps of: grinding a wafer on a back surface to a predetermined thickness; sawing the wafer into a plurality of wafer slices; spray coating a photo resist layer on top of the wafer slice; applying a lithography process to form... Agent: Birch Stewart Kolasch & Birch

20070243660 - Method for fabricating white-light-emitting flip-chip diode having silicon quantum dots: The present invention is to fabricate a flip-chip diode which emits a white light. The diode has a film embedded with silicon quantum dots. And the white light is formed by mixing colorful lights through the film.... Agent: Troxell Law Office PLLC

20070243662 - Packaging of mems devices: The present invention is directed to a process for packaging a microelectrical, micromechanical, microelectromechanical (MEMS) or microfluidic component on a substrate by forming cavities made from crosslinked photoresists on an easily removable second substrate, bonding the cavities to third substrates containing selected microdevices, then peeling off the removable second substrate.... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070243661 - Thin semiconductor device package: A thin semiconductor device package, comprising a thin substrate, at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate, a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface... Agent: Intel Corporation C/o Intellevate, LLC

20070243664 - Flip-chip mounting method and bump formation method: [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are... Agent: Mcdermott Will & Emery LLP

20070243665 - Palladium-spot leadframes for high adhesion semiconductor devices and method of fabrication: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said... Agent: Texas Instruments Incorporated

20070243667 - Pop semiconductor device manufacturing method: The objective of the invention is to prevent electrostatic destruction of semiconductor chips during resin molding. With the semiconductor device manufacturing method, a substrate 400 that includes on the surface multiple semiconductor chips 410 and liquid resin 434 supplied to multiple semiconductor devices is supported by an electrically insulated lower... Agent: Texas Instruments Incorporated

20070243666 - Semiconductor package, array arranged substrate structure for the semiconductor package and fabrication method of the semiconductor package: A semiconductor package, an array arranged substrate structure for the semiconductor package, and fabrication method of the semiconductor package are disclosed. First, a substrate having a plurality of array arranged substrate units is provided, and electroplating buses are formed between the substrate units. Each substrate unit has a plurality of... Agent: Edwards Angell Palmer & Dodge LLP

20070243668 - Normally-off integrated jfet power switches in wide bandgap semiconductors and methods of making: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant... Agent: Merchant & Gould PC

20070243669 - Method for manufacturing solid-state image pickup element and solid-state image pickup element: The present invention provides a method for manufacturing a solid-state image pickup element in which an intralayer lens is formed above a solid-state image pickup element by: a first step of forming a film using an intralayer lens forming material; a second step of reducing an aspect ratio which is... Agent: Sughrue Mion, PLLC

20070243670 - Thin film transistor (tft) and method for fabricating the same: A method for fabricating a thin film transistor (“TFT”) device includes providing a substrate, forming a patterned amorphous silicon layer over the substrate including a pair of first regions, a second region disposed between the pair of first regions, and at least one third region, each of which being disposed... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070243671 - Butted source contact and well strap: A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a... Agent: Tung & Associates

20070243672 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a semiconductor layer 18 formed on an insulation layer 16, a gate electrode 22 formed on the semiconductor layer with a gate insulation film 20 formed therebetween, a source/drain region 24 formed on the semiconductor layer on both sides of the gate electrode, and a semiconductor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070243673 - Thin-film transistor array for lcd and the method for manufacturing the same: The present invention provides a thin-film transistor array, of which the units provide with a storage capacitor disposed in the thin-film transistor array and a protective layer of transparent conductive material covering the source/drain metal of the thin-film transistor array. The present invention also provides a method for manufacturing the... Agent: Lowe Hauptman Ham & Berner, LLP

20070243674 - Polytype hetero-interface high electron mobility device and method of making: A high electron mobility device and method of making is provided whereby a two-dimensional electron gas is formed at a hetero-junction or hetero-interface between different polytypes of a semiconductor material. The different crystal forms or polytypes of the semiconductor material having different electronic bandgaps are used to provide the bandgap... Agent: Volentine & Whitt PLLC

20070243675 - Use of silicon block process step to camouflage a false transistor: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.... Agent: Robert Popa C/o Ladas & Parry

20070243676 - Image sensor device and manufacturing method thereof: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS)... Agent: North America Intellectual Property Corporation

20070243677 - Semiconductor device having a schottky source/drain transistor: A semiconductor device comprises an island shaped channel layer formed on a substrate, the channel later being composed of a semiconductor material, a gate insulation film formed on the channel layer, a gate electrode formed on the gate insulation film, an insulation film formed on both side faces opposite to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070243678 - Inkjet printing of cross point passive matrix devices: A method of manufacturing a cross-point device, comprises: providing at least one first electrode on a substrate; providing first regions of an electrically functional material over the at least one first electrode; and providing at least one second electrode over the at least one first electrode and the plurality of... Agent: Oliff & Berridge, PLC

20070243679 - Process for manufacturing a non-volatile memory structure via soft lithography: A process for manufacturing a non-volatile memory structure, in particular of a cross-point type provided with an array of memory cells, including forming bottom electrodes on a substrate; forming areas of active material on the bottom electrodes; and forming top electrodes on the areas of active material. The memory cells... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070243680 - Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element: Methods of fabricating a dual control gate non-volatile memory array are described. Parallel strips of floating gate material are formed over the substrate in a first direction but separated from it by a tunnel dielectric. In the gaps between these strips control gate material is formed forming a second set... Agent: Davis Wright Tremaine LLP

20070243681 - Method of fabricating flash memory device using sidewall process: A method of fabricating a flash memory device includes depositing and etching an insulating layer on a substrate having STI structures, depositing a first polysilicon layer over the insulating layer and the substrate, etching the first polysilicon layer to form floating gates and removing the insulating layer. The method also... Agent: Sherr & Nourse, PLLC

20070243682 - Flash memory device having a graded composition, high dielectric constant gate insulator: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator is comprised of amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070243683 - A method for forming multi gate devices using a silicon oxide masking layer: The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate... Agent: Texas Instruments Incorporated

20070243684 - Semiconductor device and method of manufaturing the same: The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A... Agent: Young & Thompson

20070243685 - Method and structure for self aligned formation of a gate polysilicon layer: A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon... Agent: Townsend And Townsend And Crew, LLP

20070243686 - Method of forming compressive nitride film and method of manufacturing metal oxide semiconductor: A method of forming compressive nitride film is provided. The method includes performing a chemical vapor deposition (CVD) process to form a nitride film on a substrate, and the method is characterized by adding a certain gas, selected from among Ar, N2, Kr, Xe, and mixtures thereof. Due to the... Agent: Jianq Chyun Intellectual Property Office

20070243687 - Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulting film: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070243688 - Method for forming strained semiconductor device and method for forming source/drain region: A method for forming a strained semiconductor device is described. A substrate including a first semiconductor material and having a first conductivity type is provided. A semiconductor layer of a second conductivity type is formed contacting with the substrate, wherein the semiconductor layer includes the first semiconductor material and a... Agent: Jianq Chyun Intellectual Property Office

20070243689 - Semiconductor device having semiconductor and base contact pad mesa portions: A semiconductor device, able to be produced while suppressing the occurrence of mesa shaped abnormalities without restriction as to the pattern layout, the type of etchant used, etc., provided with a semiconductor mesa portion including a stack of a collector layer, a base layer, and an emitter layer on a... Agent: Rader Fishman & Grauer PLLC

20070243691 - Manufacturing method of semiconductor device: Even in the case of manufacturing a fine ferroelectric memory, deterioration of a ferroelectric film can be prevented. An aluminum oxide film is formed by an ALD method to cover a ferroelectric capacitor formed above a semiconductor substrate, and after the aluminum oxide film is formed, annealing treatment is performed... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070243690 - Methods for fabricating a capacitor: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to... Agent: Quintero Law Office, PC

20070243692 - Methods of filling isolation trenches for semiconductor devices and resulting structures: The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a... Agent: Dickstein Shapiro LLP

20070243693 - Integrated process modulation (ipm) a novel solution for gapfill with hdp-cvd: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of... Agent: Townsend And Townsend And Crew LLP / Amat

20070243694 - Bonded wafer and method of producing the same: A bonded wafer is produced by bonding an ion-implanted wafer for an active layer onto a wafer for a supporting substrate, and thereafter exfoliating the wafer for the active layer at the ion-implanted position through a heat treatment and then polishing a terrace portion of the resulting active layer with... Agent: Sughrue Mion, PLLC

20070243695 - Method for producing semiconductor wafers and a system for determining a cut position in a semiconductor ingot: A method for producing semiconductor wafers, from a semiconductor ingot, wherein an oxygen concentration distribution in the growth axis direction is measured in the ingot state (F2), a position at which the oxygen concentration is maximum or minimum in a range of a predetermined length is determined as a cut... Agent: Oliff & Berridge, PLC

20070243696 - Laser beam processing machine: A laser beam processing machine comprising a path distribution means for distributing a pulse laser beam oscillated by pulse laser beam oscillation means to a first path and a second path alternately, and one laser beam that passes through one of the paths and is converged by one condensing lens... Agent: Smith, Gambrell & Russell

20070243697 - Lithographic apparatus and device manufacturing method: An immersion lithographic exposure appa