Semiconductor device manufacturing: process inventions 10/07

20070249065 - Manufacturing method of semiconductor device: After an interlayer insulating film and a lower side layer of a conductive film for a bottom electrode and the like are formed above a substrate, a Pt film of a thickness of 50 nm to 500 nm, for example, about 175 nm is formed on the lower side layer... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070249072 - Method and apparatus for producing interferometric lithography patterns with circular symmetry: Exemplary embodiments provide optical systems and methods for producing interferometric lithography (IL) patterns with circular symmetry for applications such as memory devices including CD ROMs, DVDs, magnetic hard disk storage, and the like. Specifically, one or more axicon optics can be configured in the optical systems for IL patterning processes... Agent: Mh2 Technology Law Group

20070249073 - Method for determining the electrically active dopant density profile in ultra-shallow junction (usj) structures: In a method of determining that a semiconductor wafer or sample has a desirable density of electrically active dopant, minimum and maximum capacitances associated with the semiconducting material forming the wafer or sample at a first point adjacent a topside thereof are determined and minimum and maximum capacitances associated with... Agent: The Webb Law Firm, P.C.

20070249074 - Active device array substrate, color filter substrate and manufacturing methods thereof: An active device array substrate comprising a substrate, a pixel array, a partition configuration and an alignment material layer is provided. The substrate has an alignment region and a predetermined sealing region. The predetermined sealing region surrounds the alignment region. The pixel array is disposed on the substrate within the... Agent: J C Patents, Inc.

20070249066 - Ferroelectric rare-earch manganese-titanium oxides: Ferroelectric rare-earth manganese-titanium oxides and methods of their manufacture. The ferroelectric materials can provide nonvolatile data storage in rapid access memory devices.... Agent: Quine Intellectual Property Law Group, P.C.

20070249067 - Method for applying rewiring to a panel while compensating for position errors of semiconductor chips in component positions of the panel: The invention relates to a method for applying rewiring to a panel. For this purpose, a panel is provided which has a coplanar overall upper side of an upper side of a plastic compound and the upper sides of semiconductor chips. The method provides a rewiring layer with implementation of... Agent: Dicke, Billig & Czaja

20070249068 - Semiconductor device system and method for modifying a semiconductor device: A semiconductor device system and a method for modifying a semiconductor device is disclosed. In one embodiment, a function provided by a circuit positioned on the semiconductor device is replaced, modified, and/or supplemented by a function provided by a circuit positioned on a further semiconductor device.... Agent: Dicke, Billig & Czaja

20070249069 - Semiconductor devices and methods of manufacturing thereof: A method of manufacturing a semiconductor device includes providing a workpiece comprising a plurality of active areas, and analyzing the active areas to determine desired stress levels for each active area. The method includes determining at least one first active area to have a first amount of stress and at... Agent: Slater & Matsil LLP

20070249071 - Neural network methods and apparatuses for monitoring substrate processing: Aspects of the present invention include methods and apparatuses that may be used for monitoring substrate processing systems. One embodiment may provide an apparatus for obtaining in-situ data regarding processing of a substrate in a substrate processing chamber, comprising a data collecting assembly for acquiring training data related to a... Agent: Patterson & Sheridan, LLP

20070249070 - Topography compensated film application methods: Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable depth of a film to the wafer, such that the... Agent: Hoffman, Warnick & D'alessandro LLC

20070249075 - Led package and method for producing the same: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and... Agent: Rosenberg, Klein & Lee

20070249076 - Organic electroluminescent device, method of manufacturing the same, and electronic apparatus: An organic electroluminescent device comprising: an organic thin-film transistor element including at least an active layer made of an organic material; and an organic electroluminescent element driven by the organic thin-film transistor element.... Agent: Harness, Dickey & Pierce, P.L.C

20070249080 - Magnetic field sensing device and a fabricating method of the same: A magnetic field sensing device and a fabrication method of the same featuring an easy planarization process for a substrate and a simplified procedure by the benefit of a slim planarizing substance. The magnetic field sensing device includes a substrate with a well of a predetermined depth and a plurality... Agent: Sughrue Mion, PLLC

20070249078 - Non-planar surface structures and process for microelectromechanical systems: Methods of making MEMS devices including interferometric modulators involve depositing various layers, including stationary layers, movable layers and sacrificial layers, on a substrate. Apertures are formed in one or more of the various layers so as to form a non-planar surface on the movable and/or the stationary layers. Other layers... Agent: Knobbe, Martens, Olson & Bear, LLP

20070249079 - Non-planar surface structures and process for microelectromechanical systems: Methods of making MEMS devices including interferometric modulators involve depositing various layers, including stationary layers, movable layers and sacrificial layers, on a substrate. A non-planar surface is formed on one or more layers by flowing an etchant through a permeable layer. In one embodiment the non-planar surface is formed on... Agent: Knobbe, Martens, Olson & Bear, LLP

20070249077 - Photo diode and related method for fabrication: A method for fabricating a photo diode first involves providing a substrate. A doping area is then formed on the substrate. Afterwards, a dielectric layer, and a first poly-silicon layer are formed on the substrate. An opening is then formed to expose a surface of the doping area. A second... Agent: North America Intellectual Property Corporation

20070249081 - Non-planar surface structures and process for microelectromechanical systems: Methods of making MEMS devices including interferometric modulators involve depositing various layers, including stationary layers, movable layers and sacrificial layers, on a substrate. Voids are formed in one or more of the various layers so as to form a non-planar surface on the movable and/or the stationary layers. The voids... Agent: Knobbe, Martens, Olson & Bear, LLP

20070249082 - Manufacturing method of mems structures and manufacturing method of mems structures with semiconductor device: The objects of the present invention are to form MEMS structures of which stress is controlled while maintaining the performance of high-performance LSI, to integrate MEMS Structures and LSI on a single chip, to electrically and chemically protect the MEMS structure and to reduce the stress of the whole movable... Agent: Stanley P. Fisher Reed Smith LLP

20070249083 - Multilevel phase-change memory element and operating method: A multilevel phase-change memory, operating method and manufacturing method thereof. The phase-change memory includes two phase-change layers and electrodes, which are configured in a parallel structure to form a memory cell. A voltage-drive mode is employed to control and drive the memory such that multilevel memory states may be achieved... Agent: Rabin & Berdo, PC

20070249084 - Active matrix display device and method of manufacturing the same: In an active matrix display device integrated with peripheral drive circuits, an image sensor is provided on the same substrate as a pixel matrix and peripheral drive circuits. The image sensor is formed on the substrate having pixel electrodes, pixel TFTs connected to the pixel electrodes and CMOS-TFTs for driving... Agent: Eric Robinson

20070249085 - Solar cell and method of fabricating the same: A method of fabricating a solar cell forms a large number of grooves on a first main surface of a p-type silicon single crystal substrate sliced out from a silicon single crystal ingot as described below. First an edge portion of a groove-carving blade is projected out from a flat... Agent: Snider & Associates

20070249086 - Phase change memory: A memory cell includes a first electrode, a second electrode, a layer of phase change material positioned between the first and second electrodes, and a stress layer contacting the layer of phase change material. The phase change material includes a high temperature state, and the stress layer defines an interface... Agent: Dicke, Billig & Czaja

20070249088 - Electronic device and manufacturing method therefor: A manufacturing method for an electronic device, the method including forming a transparent conductive film, including conductive polymers, on a base material, and irradiating ultraviolet light onto a part of the transparent conductive film such that first regions of the transparent conductive film are not irradiated and second regions, adjacent... Agent: Sughrue Mion, PLLC

20070249087 - Electronic devices containing acene-thiophene copolymers with silylethynyl groups: Electronic devices that include an acene-thiophene copolymer and methods of making such electronic devices are described. More specifically, the acene-thiophene copolymer has attached silylethynyl groups. The copolymer can be used, for example, in a semiconductor layer or in a layer positioned between a first electrode and a second electrode.... Agent: 3m Innovative Properties Company

20070249089 - Method of making circuitized substrate with internal organic memory device: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20070249090 - Phase-change memory cell adapted to prevent over-etching or under-etching: A memory cell includes a first electrode and a second electrode. The second electrode has a first layer and a second layer. The first layer has a lower etch rate relative to the second layer. The memory cell includes a phase-change material positioned between the first electrode and the second... Agent: Dicke, Billig & Czaja

20070249091 - Micro device encapsulation: A packaged die includes a substrate having an upper surface and a micro device on the upper surface and an encapsulation cover comprising one or more grooves on its lower surface. The lower surface of the encapsulation cover and the upper surface of the substrate are bonded together to form... Agent: Fish & Richardson P.C.

20070249092 - Semiconductor die package including multiple dies and a common node structure: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at... Agent: Townsend And Townsend And Crew, LLP

20070249093 - Semiconductor device and method of manufacturing the semiconductor device: A semiconductor device comprises a semiconductor chip, a wiring layer formed on the semiconductor chip, a column electrode connected at a first end to the wiring layer, and an encapsulation resin formed on the semiconductor chip. In the semiconductor device, the column electrode is provided with a second end, opposite... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070249094 - Method for fabricating multi-chip semiconductor package: A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper... Agent: Edwards Angell Palmer & Dodge LLP

20070249095 - Semiconductor package and method of manufacturing the same: Disclosed herein are a semiconductor package used in digital optical instruments and a method of manufacturing the same. The semiconductor package comprises a wafer made of a silicon material and having pad electrodes formed at one side surface thereof, an IR filter attached on the pad electrodes of the wafer... Agent: Lowe Hauptman Ham & Berner, LLP

20070249096 - Method of forming a metal line and method of manufacturing a display substrate by using the same: In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070249097 - Method of forming a metal line and method of manufacturing a display substrate by using the same: In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070249098 - Bonding plate mechanism for use in anodic bonding: A bonding plate mechanism for use in anodic bonding of first and second material sheets together, the apparatus comprising: a base including first and second spaced apart surfaces; a thermal insulator supported by the second surface of the base and operable to impede heat transfer to the base; a heating... Agent: Corning Incorporated

20070249100 - Carrierless chip package for integrated circuit devices, and methods of making same: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each... Agent: Williams, Morgan & Amerson

20070249099 - Method of and apparatus for manufacturing elements: A method of separating individual elements (e.g. conducting preforms or Gunn diodes) from an array of such elements comprises the application of energy (e.g. electric current) via a pick-up tool to melt tabs which hold the element to a supporting structure.... Agent: Venable LLP

20070249101 - Method for fabricating semiconductor package free of substrate: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the... Agent: Edwards Angell Palmer & Dodge LLP

20070249102 - Panel and semiconductor device having a structure with a low-k dielectric: A panel and a semiconductor device, in one embodiment composed of a composite plate with semiconductor chips and plastic housing composition and to a method for producing the same is disclosed. The embodiments include a wiring structure with interconnects and dielectric layers composed of a low-k dielectric is arranged on... Agent: Dicke, Billig & Czaja

20070249103 - Method of making a multi-gate device: A semiconductor device has two types of multi-gate transistors, N channel and P channel, in which each type has a bottom gate and a top gate. The bottom gate and the top gate of the N channel transistors are chosen to be of a metal or metals that are for... Agent: Freescale Semiconductor, Inc. Law Department

20070249104 - Method for fabricating a thin-film transistor: A method for fabricating a thin-film transistor contains successively forming four thin films on a substrate and performing an etching process to pattern the four thin films, wherein the four thin films are a first conductive layer, a first insulation layer, a semiconductor film, and a metal-containing sacrificial layer from... Agent: North America Intellectual Property Corporation

20070249105 - Liquid crystal display, thin film transistor array panel for liquid crystal display and manufacturing method thereof: A gate wire is formed on the insulating substrate. The gate wire has gate lines, first and second gate electrodes connected to the gate lines, and gate pads. A gate insulating layer, first and second semiconductor layers and an ohmic contact layer are sequentially formed thereon. A data wire is... Agent: F. Chau & Associates, LLC

20070249106 - Semiconductor device and method of manufacturing the same: It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070249107 - Touch panel and manufacturing method thereof: Proving a touch panel having a superior transparent visibility, easy to manufacture and of low cost, to be used for various electronic devices. In manufacturing, forming a notch with an adhesive layer formed on an undersurface of an under substrate, under a connecting portion of the under substrate with a... Agent: Ratnerprestia

20070249108 - Thin film transistor having ldd structure: A thin film transistor having a LDD structure that may improve its channel reliability and output characteristics. A semiconductor layer comprises source/drain regions, a channel region positioned between the source/drain regions, and an LDD region positioned between the channel region and a source/drain region, wherein a projected range of ions... Agent: H.c. Park & Associates, PLC

20070249110 - Nonvolatile memory device, method of fabricating the same, and organic lighting emitting diode display device including the same: A nonvolatile memory device may include a substrate, a semiconductor layer on the substrate, and including a source region, a drain region having a relatively shallower impurity injection region than that of the source region and a channel region disposed between the source and drain regions, a first gate insulating... Agent: Lee & Morse, P.C.

20070249109 - Optical device and optical module: A high resistance re-grown layer is disposed around an optical device having a mesa structure. Thus, a mesa portion having a plane direction that appears in etching of a circular main structure is coated with the re-grown layer. Because of this coating, it is possible to reduce the capacitance in... Agent: Mcdermott Will & Emery LLP

20070249111 - Tft array substrate and photo-masking method for fabricating same: An exemplary TFT array substrate (2) includes an insulating substrate (201); a transparent conductive line (221) formed on the insulating substrate; a plurality of gate lines (210) formed on the transparent conductive line, that are parallel to each other and that each extend along a first direction; a plurality of... Agent: Wei Te Chung Foxconn International, Inc.

20070249112 - Differential spacer formation for a field effect transistor: A method for manufacturing an integrated circuit includes providing one or more n-type field effect transistor and one or more p-type field effect transistor on a semiconductor substrate. Each of the transistors separated by a trench isolation structure. Each of the transistors has a source and drain regions formed in... Agent: International Business Machines Corporation Dept. 18g

20070249113 - Stressor integration and method thereof: A method is provided for making a semiconductor device. In accordance with the method, a substrate (203) is provided which has first (205) and second (207) gate structures thereon. A first stressor layer (215) is formed over the substrate, and a sacrificial layer (216) is formed over the first stressor... Agent: Fortkort & Houston P.C.

20070249114 - Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the... Agent: International Business Machines Corporation Dept. 18g

20070249115 - Dynamic memory cell structures: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater... Agent: Ryan, Mason & Lewis, LLP

20070249116 - Transitioning the state of phase change material by annealing: A semiconductor device includes a preprocessed wafer and an annealed phase change material layer contacting the preprocessed wafer. The semiconductor device includes a first material layer contacting the annealed phase change material layer.... Agent: Dicke, Billig & Czaja

20070249117 - Polymer resin composition, related method for forming a pattern, and related method for fabricating a capacitor: A polymer resin composition, a method for forming a pattern using the polymer resin composition, and a method for fabricating a capacitor using the polymer resin composition are disclosed. The polymer resin composition includes about 75 to 93 percent by weight of a copolymer prepared from benzyl methacrylate, methacrylic acid,... Agent: Volentine & Whitt PLLC

20070249118 - Semiconductor device and method of manufacturing the same: Recessed portions (passages) are formed in a surface of a passivation film so as to eliminate an adverse influence from air bubbles that would be generated between a surface of a semiconductor wafer and a surface protection sheet covering the surface of the semiconductor wafer during plasma etching a rear... Agent: Sughrue Mion, PLLC

20070249119 - Nitride semiconductor device: A nitride semiconductor device includes: a first semiconductor layer; a second semiconductor layer provided on the first semiconductor layer; a p-type region selectively provided in the second semiconductor layer; a gate insulating film provided on the p-type region; a field insulating film provided on the second semiconductor layer surrounding the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070249120 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070249122 - Array substrate for liquid crystal display device using organic semiconductor material and method of fabricating the same: An array substrate for a liquid crystal display device comprises a data line disposed on a substrate that has a pixel region, and source and drain electrodes disposed on the substrate. The source electrode extends from the data line and is separated from the drain electrode. The array substrate for... Agent: Brinks Hofer Gilson & Lione

20070249121 - Method of fabricating non-volatile memory: A method of fabricating a non-volatile memory is provided. The method includes providing a substrate. Next, a tunneling oxide layer is formed on the substrate and a surface nitridation process is performed to nitridize the upper surface of the tunneling oxide layer. A plurality of nanocrystals is formed on the... Agent: Jianq Chyun Intellectual Property Office

20070249123 - Method of fabricating a recess channel transistor: A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a... Agent: Birch Stewart Kolasch & Birch

20070249124 - Dmos device of small dimensions and manufacturing process thereof: In a body of semiconductor material, a field region separates a first active area and a second active area. A drain region is formed in the first active area; a body region is formed in the second active area and accommodates a source region. A body-contact region is formed inside... Agent: Graybeal, Jackson, Haley LLP

20070249125 - Flash memory device with stacked dielectric structure including zirconium oxide and method for fabricating the same: A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second dielectric layer disposed between the first dielectric... Agent: Townsend And Townsend And Crew, LLP

20070249126 - A structure and method for fabrication of deep junction silicon-on-insulator transistors: A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant... Agent: International Business Machines Corporation Dept. 18g

20070249127 - Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same: An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening... Agent: Larson Newman Abel Polansky & White, LLP

20070249129 - Sti stressor integration for minimal phosphoric exposure and divot-free topography: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer (224) disposed on a buried dielectric layer (222). A trench (229) is created in the semiconductor structure which exposes a portion of the buried... Agent: Fortkort & Houston P.C.

20070249128 - Ultraviolet (uv) radiation treatment methods for subatmospheric chemical vapor deposition (sacvd) of ozone-tetraethoxysilane (o3-teos): Dielectric layers are formed on a substrate by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O3-TEOS) to form a layer of O3-TEOS on the substrate, and treating the layer of O3-TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the O3-TEOS layer by... Agent: Myers Bigel Sibley & Sajovec

20070249130 - Finfet/trigate stress-memorization method: Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the semiconductor fin. Specifically, a protective cap layer is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070249131 - Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing... Agent: Scully Scott Murphy & Presser, PC

20070249132 - Semiconductor device with fixed channel ions: A method for manufacturing a semiconductor device includes subjecting a semiconductor substrate to thermal treatment at a temperature ranging from 770 to 830° C. to fix channel ions then forming a HTO film. The method thereby prevents a threshold voltage of a gate from changing due to diffusion of channel... Agent: Heller Ehrman LLP

20070249133 - Semiconductor device with fixed channel ions: A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20070249134 - Method and apparatus for irradiating laser: A laser irradiation process includes: scanning a substrate with laser having a predetermined lasing frequency at different irradiation intensities to form a plurality of first irradiation areas corresponding to the irradiation intensities; illuminating the first irradiation areas to reflected light receive from the fist irradiation areas; determining microcrystallization intensity based... Agent: Dickstein Shapiro LLP

20070249135 - Collector tailored structures for integration of binary junction transistors: A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic dilute mask is... Agent: Texas Instruments Incorporated

20070249136 - Silicon structures with improved resistance to radiation events: A silicon structure with improved protection against failures induced by excess radiation-induced charge carrier migration from the bulk region into the near-surface region. The structure comprises bulk and near-surface regions that are doped with a dopant, wherein the concentration in the near-surface region is at least 10 times the maximum... Agent: Senniger Powers

20070249137 - Method and system for wafer backside alignment: Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer... Agent: David M. O'dell Attorney For Applicants

20070249138 - Buried dielectric slab structure for cmos imager: A substrate structure, and method of forming the structure, are provided. The structure, which may be used for a CMOS imager device, is provided with a buried dielectric structure. Recesses are formed on a semiconductor substrate, e.g., silicon, and a dielectric material is used to fill the recesses. A layer... Agent: Dickstein Shapiro LLP

20070249140 - Method for the production of thin substrates: A method is provided for producing a thin substrate with a thickness below 750 microns, comprising providing a mother substrate, the mother substrate having a first main surface and a toughness; inducing a stress with predetermined stress profile in at least a portion of the mother substrate, said portion comprising... Agent: Knobbe Martens Olson & Bear LLP

20070249139 - Semiconductor on glass insulator made using improved thinning process: Methods and apparatus for producing a semiconductor on glass (SiOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis;... Agent: Corning Incorporated

20070249141 - Method of manufacturing electrode pattern: A method of manufacturing an electrode pattern comprises preparing a first support film; forming a mold release pattern on one surface of the first support film, the mold release pattern defining an internal electrode formation region; forming an electrode layer on the mold release pattern by using a thin film... Agent: Mcdermott Will & Emery LLP

20070249143 - Method and device of manufacturing thin substrate: An easy and low-cost method of manufacturing a thin substrate reduced in surface wobbling by bonding two thin sheets together is provided. A step of bonding thin substrate sheets together is performed by using a device in which a spacer is incorporated into a turntable provided with a through-hole for... Agent: Birch Stewart Kolasch & Birch

20070249142 - Semiconductor devices and method of manufacturing them: A semiconductor device of the present invention comprises a super junction structure in which a pair semiconductor regions, comprising of a p-type semiconductor region and an n-type semiconductor region, is disposed repeatedly along at least one direction, wherein a Si1-x-yGexCy (0≦x<1, 0<y<1, 0<-x-y<1) crystal region is disposed repeatedly along, at... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070249144 - Method of forming silicon-on-insulator wafer having reentrant shape dielectric trenches: A method for forming a bonded SOI wafer is provided in which a first wafer having a single-crystal semiconductor region has a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly into the single-crystal... Agent: International Business Machines Corporation Dept. 18g

20070249145 - Method of dividing an adhesive film bonded to a wafer: A method of dividing an adhesive film for die bonding which is bonded to the rear surface of a wafer having devices in a plurality of areas sectioned by dividing lines formed in a lattice pattern on the front surface, into pieces corresponding to the devices, comprising the steps of... Agent: Smith, Gambrell & Russell

20070249146 - Protective tape applying method: A protective tape applying method includes: preparing a substrate which has plural devices formed on a surface of the substrate; and holding the substrate on a chuck table such that a rear surface of the substrate is chucked by the chuck table and the surface of the substrate is exposed.... Agent: Brinks Hofer Gilson & Lione

20070249147 - Process and system for laser annealing and laser-annealed semiconductor film: In a laser annealing process: the first to fourth sections of a bandlike area of a nonmonocrystalline semiconductor film are consecutively scanned and irradiated with laser light so as to produce a fused region in the bandlike area, where the fourth section contains a portion required to have higher crystallinity... Agent: Sughrue Mion, PLLC

20070249148 - Method for producing a layer consisting of a doped semiconductor material: The invention concerns a method for depositing a layer consisting of a doped semiconductor material on a substrate, as well as a device for implementing said method. According to said method, the doped semiconductor material contains at least one semiconductor matrix material and at least one doping material. Said method... Agent: Schmeiser, Olsen & Watts

20070249149 - Improved thermal budget using nickel based silicides for enhanced semiconductor device performance: The use of nickel, Ni, based alloys that enables higher contact module which, in turn, provides the device designers additional gains in transistor speeds is provided. Specifically, the use of Ni based alloys for silicide formation in 90 nm technologies and beyond enables higher temperature (greater than 450° C.) processing... Agent: Scully Scott Murphy & Presser, PC

20070249153 - Chip structure with half-tunneling electrical contact to have one electrical contact formed on inactive side thereof and method for producing the same: A method for producing a chip structure with one electrical contact formed on inactive side thereof includes by pre-forming at least one half-tunneling electrical contact to penetrate a processed substrate prepared for processing a chip, and when finishing processing the chip the half-tunneling electrical contact is without completely penetrated the... Agent: Bacon & Thomas, PLLC

20070249150 - Method of forming a metal line and method of manufacturing a display substrate by using the same: In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070249152 - Method of manufacturing semiconductor apparatus: A method of manufacturing a semiconductor apparatus includes forming an electrode on a semiconductor device, forming a conductive bump on the electrode, placing an external wire on the conductive bump, and laser-welding the external wire and the conductive bump to establish electrical connection.... Agent: Foley And Lardner LLP Suite 500

20070249151 - Method of manufacturing semiconductor device and semiconductor device: Gate electrodes each covered by protective insulating films are formed, a first interlayer insulating film is formed on the entire surface including regions between the protective insulating films and on the protective insulating films, the first interlayer insulating film is polished and removed until top surfaces of the protective insulating... Agent: Sughrue Mion, PLLC

20070249154 - Method to manufacture a coreless packaging substrate: A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to... Agent: Bacon & Thomas, PLLC

20070249155 - Method to manufacture a coreless packaging substrate: A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to... Agent: Bacon & Thomas, PLLC

20070249156 - Method for enabling hard mask free integration of ultra low-k materials and structures produced thereby: A method is described for the repair of process induced damage sustained by low-k organosilicate dielectrics as a result of reactive ion etch, resist strip, wet clean and CMP operations in a hard mask free integration of these dielectrics into microelectronic interconnect structures incorporating a dielectric cap which is an... Agent: Ibm Corporation, T.j. Watson Research Center

20070249157 - Semiconductor device and method for manufacturing same: A semiconductor device includes an interconnect group (TEG region) composed of a plurality of interconnects, which elongate along a first direction in a substrate surface of the substrate, and are arranged with a minimum interconnect interval therebetween in the semiconductor device, and a third interconnect, which elongates along a second... Agent: Young & Thompson

20070249158 - Semiconductor device and manufacturing method thereof: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top... Agent: Morrison & Foerster LLP

20070249161 - Anisotropic conductive sheet and method of manufacturing the same: Disclosed is an anisotropic conductive sheet which is equipped with an insulating base portion and a plurality of conductive portions extending through the base portion in a thickness direction thereof, which easily allows temporary fixation at a time of attachment thereof, and which, if pressurized, causes no adhesive material to... Agent: Rader Fishman & Grauer PLLC

20070249162 - Semiconductor device: In the conventional technology, a region of larger data rate causes a varied level of the light exposure in the lithographic operation in the process for manufacturing the semiconductor device, causing a problem of allowing narrower process window. A semiconductor device includes interconnects (first interconnects) elongating along a first direction... Agent: Young & Thompson

20070249163 - Semiconductor device and method of manufacturing the same: The invention is directed to a semiconductor device having a via hole and a method of manufacturing the same that achieve both the prevention of a barrier layer insufficiently covering the via hole and the control of via resistance at the same time. A semiconductor substrate having a pad electrode... Agent: Morrison & Foerster LLP

20070249159 - Method for forming dielectric film to improve adhesion of low-k film: A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer... Agent: Slater & Matsil, L.L.P.

20070249160 - Process of forming an electronic device including a layer formed using an inductively coupled plasma: A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the... Agent: Larson Newman Abel Polansky & White, LLP

20070249165 - Dual damascene process: A dual damascene process is provided. A substrate having a conductive area is provided. An etching stop layer, a dielectric layer and a patterned hard mask layer are sequentially formed on the substrate. A first opening is formed in the dielectric layer exposed by the patterned hard mask layer. A... Agent: J.c. Patents, Inc.

20070249164 - Method of fabricating an interconnect structure: An interconnect structure for a semiconductor device is provided. The interconnect structure for a semiconductor device comprises a substrate having a conductive region thereon, a first dielectric layer having a modified surface portion serving as an etch stop layer and a second dielectric layer having a hardness less than that... Agent: Daniel R. Mcclure Thomas, Kayden, Horstemeyer & Risley, LLP

20070249166 - Method for fabricating a semiconductor component including a high capacitance per unit area capacitor: A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20070249167 - Cmp method for copper-containing substrates: The invention provides a chemical-mechanical polishing composition comprising an abrasive, a benzotriazole derivative, an oxidizing agent selected from the group consisting of iodate compounds, organic oxidizing agents, and mixtures thereof, and water, wherein the polishing composition comprises substantially no organic carboxylic acid having a molecular weight of less than about... Agent: Steven Weseman Associate General Counsel, I.p.

20070249168 - Crystallographic preferential etch to define a recessed-region for epitaxial growth: A semiconductor device 100 comprising a gate structure 105 on a semiconductor substrate 110 and a recessed-region 115 in the semiconductor substrate. The recessed-region has a widest lateral opening 120 that is near a top surface 122 of the semiconductor substrate. The widest lateral opening undercuts the gate structure.... Agent: Texas Instruments Incorporated

20070249169 - Mask and method of manufacturing liquid crystal display device using the same: A method for fabricating a device is disclosed. The method includes providing a substrate; forming a thin film on the substrate; forming a photoresistable layer on the thin film; irradiating light onto the photoresistable layer through a photo mask having a transmissive region, a semi-transmissive region, a diffractive region and... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070249171 - Dielectric plasma etch process with in-situ amorphous carbon mask with improved critical dimension and etch selectivity: A plasma-enhanced process is performed in a single plasma reactor chamber for etching a thin film layer on a workpiece, using a hard mask layer including an amorphous carbon layer (ACL) overlying the thin film layer and an anti-reflection coating (ARC) overlying the ACL. The process includes etching a pattern... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20070249170 - Process for improving critical dimension uniformity of integrated circuit arrays: Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features... Agent: Knobbe Martens Olson & Bear LLP

20070249173 - Plasma etch process using etch uniformity control by using compositionally independent gas feed: A plasma etch process etches high aspect ratio openings in a dielectric film on a workpiece in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through an inner annular zone of gas injection... Agent: Robert Mulcahy Law Office Of Robert W Mulcahy

20070249172 - Method for removing masking materials with reduced low-k dielectric material damage: Methods for removing masking materials from a substrate having exposed low-k materials while minimizing damage to exposed surfaces of the low-k material are provided herein. In one embodiment a method for removing masking materials from a substrate includes providing a substrate having exposed low-k materials and a masking material to... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070249174 - Patterning sub-lithographic features with variable widths: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls... Agent: International Business Machines Corporation Dept. 18g

20070249175 - Pitch-shrinking technologies for lithographic application: Two pitch-shrinking technologies are invented, which allow us to further reduce the pitch size significantly smaller than the minimum feature size resolvable with any conventional lithographic technology. One technology can be used to shrink the pitch size of both line/space (straight or wiggling) and contact-hole patterns by half from the... Agent: Yijian Chen

20070249176 - Active device array substrate and fabricating method thereof: A method of fabricating an active device array substrate is provided. A substrate having scan lines, data lines and active devices formed thereon is provided. Each of the active devices is electrically connected to the corresponding scan line and data line. An organic material layer is formed over the substrate... Agent: Jianq Chyun Intellectual Property Office

20070249177 - Method for hard mask cd trim: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and... Agent: Martine Penilla & Gencarella, LLP

20070249178 - Semiconductor device, manufacturing method of semconductor device, manufacturing equipment of semiconductor device, light emitting diode head, and image forming apparatus: The manufacturing method comprises steps of performing a first etching process to etch a separation area on a front surface of a substrate, arranging a supporter on a back surface of the first substrate to prevent semiconductor devices from coming apart, coating with a thin film a non-etching area including... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070249179 - Method of forming a low-k dielectric layer with improved damage resistance and chemical integrity: A method of forming a low-k dielectric layer or film includes forming a porous low-k dielectric layer or film over a wafer or substrate. Active bonding is introduced into the porous low-k dielectric layer or fihm to improve damage resistance and chemical integrity of the layer or film, to retain... Agent: Duane Morris LLPIPDepartment (tsmc)

20070249180 - Method of making a molecule-surface interface: This invention is generally related to a method of making a molecule-surface interface comprising at least one surface comprising at least one material and at least one organic group wherein the organic group is adjoined to the surface and the method comprises contacting at least one organic group precursor with... Agent: Winstead PC

20070249181 - Process using a broken gelled composition: A process including: (a) providing a gelable composition comprising a gelable semiconductor polymer and a liquid, wherein the polymer is at a low concentration in the liquid; (b) gelling the gelable composition to result in a gelled composition; (c) breaking the gelled composition to result in a flowable, broken gelled... Agent: Patent Documentation Center

20070249182 - Etching of sio2 with high selectivity to si3n4 and etching metal oxides with high selectivity to sio2 at elevated temperatures with bcl3 based etch chemistries: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be... Agent: Townsend And Townsend And Crew LLP / Amat

20070243640 - Method for manufacturing ferroelectric memory device: A method for manufacturing a ferroelectric memory device includes the steps of forming an active element on a substrate; forming an interlayer dielectric film on the substrate; forming a contact hole in the interlayer dielectric film; forming, in the contact hole, a contact plug that conductively connects to the active... Agent: Harness, Dickey & Pierce, P.L.C

20070243644 - Semiconductor laser device and method of manufacturing the same, and optical transmission module and optical disk apparatus using the semiconductor laser device: Provided are a semiconductor laser device capable of stable operation at the time of high power output without damage to a resonator end surface and a method of manufacturing the same, as well as an optical transmission module and an optical disk apparatus using the semiconductor laser device. A method... Agent: Harness, Dickey & Pierce, P.L.C

20070243649 - Centrifugally cast electrochemical cell components: A component for an electrochemical cell is formed using centrifugal forces to densify an electrode or electrode material. In some embodiments, a binding agent may be used to mechanically bind active material for processing and normal operation. The binding agent may be a dispersed solid material as well as a... Agent: Krajec Patent Offices, LLC

20070243648 - Manufacturing method of pixel structure: A method of manufacturing a pixel structure is provided. A gate, a scan line, and at least one first auxiliary pattern are formed on a substrate. A gate insulating layer is formed on the substrate to cover the gate and the scan line and expose the first auxiliary pattern and... Agent: J C Patents, Inc.

20070243655 - Self-aligned process for fabricating imprint templates containing variously etched features: A process that enables coplanarization of the structures that have been created in multiple independent etch steps. The various etches are performed independently by selectively exposing only certain patterns to particular etching conditions. After these structures have been created, it is possible that the various structures will exist at different... Agent: Molecular Imprints

20070243658 - Production method of crystalline organic semiconductor thin film, organic semiconductor thin film, electronic device, and thin film transistor: A method of producing a crystalline organic semiconductor thin film including the steps of: (a) coating a solution of an organic semiconductor material in a solvent onto a substrate to form a liquid coating film; and (b) crystallizing the organic semiconductor material in the liquid coating film at an edge... Agent: Cantor Colburn, LLP

20070243641 - Method for forming ferroelectric memory device: A ferroelectric memory device and a method of forming the same are provided. At least two lower electrode patterns are formed on an interlayer insulating layer covering a semiconductor substrate. A seed layer pattern filling a space between at least the two lower electrode patterns and having a planar surface... Agent: Lee & Morse, P.C.

20070243639 - Methods and apparatus for a synthetic anti-ferromagnet structure with reduced temperature dependence: A synthetic antiferromagnet (SAF) structure includes a first ferromagnetic layer, a first insertion layer, a coupling layer, a second insertion layer, and a second ferromagnetic layer. The insertion layers comprise materials selected such that SAF exhibits reduced temperature dependence of antiferromagnetic coupling strength. The insertion layers may include CoFe or... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070243638 - Novel method to form a nonmagnetic cap for the nife(free) mtj stack to enhance dr/r: An MTJ in an MRAM array or TMR read head is disclosed in which a capping layer has a bilayer configuration with a non-magnetic NiFeX inner layer on a NiFe free layer and a Ta layer on the NiFeX layer to improve dR/R and minimize magnetostriction. Optionally, a trilayer configuration... Agent: Stephen B. Ackerman

20070243642 - Method of evaluating characteristics of and forming of an insulating film for a semiconductor device: A method of evaluating characteristics of an insulating film 1 is disclosed. The insulating film 1 is formed of an insulative inorganic material as a main material, the insulative inorganic material containing silicon and oxygen. The insulating film 1 further contains hydrogen atoms. The method includes the steps of: analyzing... Agent: Harness, Dickey & Pierce, P.L.C

20070243643 - Circular test pads on scribe street area: A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe street (34) such that any cracks generated in the test... Agent: Texas Instruments Incorporated

20070243645 - High-power led chip packaging structure and fabrication method thereof: A packaging structure and a related fabrication method for high-power LED chip are provided herein, which mainly contains a base made of a metallic material and an electrically insulating material integrated into a single object. The metallic material forms a heat sinking seat in the middle of the base, which... Agent: Lin & Associates Intellectual Property

20070243646 - Led package and method for producing the same: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and... Agent: Rosenberg, Klein & Lee

20070243647 - Led package and method for producing the same: An LED package and method for producing the same are described. The LED package has an LED die with a conductive region-forming surface and a plurality of conductive regions disposed on the conductive region-forming surface. An insulation layer is formed on the conductive region-forming surface of the LED die, and... Agent: Rosenberg, Klein & Lee

20070243650 - Liquid crystal display device and method of fabricating the same: A method of fabricating a liquid crystal display device includes steps of forming a first metal layer on the substrate to form a gate line including a gate electrode, a gate pad, and a first capacitor electrode, forming an insulating layer, an active layer, and a second metal layer on... Agent: Morgan Lewis & Bockius LLP

20070243651 - Organic el light emitting display device and method of manufacturing the same: Disclosed is a method for manufacturing an organic EL light emitting display device, comprising forming an anode electrode above a substrate, forming an organic light emitting layer above the anode electrode, performing a fluorinating treatment on a surface of the organic light emitting layer, and forming a cathode electrode directly... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070243653 - Methods for controllable doping of aluminum nitride bulk crystals: Fabrication of doped and undoped stoichiometric polycrystalline AlN ceramics with high purity is accomplished by, for example, reacting Al pellets with nitrogen gas. Such polycrystalline AlN ceramics may be utilized in the fabrication of high purity AlN single crystals, which may be annealed to enhance a conductivity thereof.... Agent: Goodwin Procter LLP Patent Administrator

20070243652 - Stacked-substrate processes for production of nitride semiconductor structures: Methods are provided of fabricating compound nitride semiconductor structures. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over a surface of a first substrate with a thermal chemical-vapor-deposition process. A second layer is deposited over a surface of a second... Agent: Townsend And Townsend And Crew LLP / Amat

20070243654 - Microelectromechanical device with integrated conductive shield: A microelectromechanical device and method of fabricating the same, including a layer of patterned and deposited metal or mechanical-quality, doped polysilicon inserted between the appropriate device element layers, which provides a conductive layer to prevent the microelectromechanical device's output from drifting. The conductive layer may encapsulate of the device's sensing... Agent: Honeywell International Inc.

20070243656 - Photodiode and method of manufacturing the same: A photodiode and a method of manufacturing the photodiode are provided. The method includes forming a diode junction structure including a light receiving unit and an electrode unit on a semiconductor substrate, forming a buffer oxide layer and an etching blocking layer on the junction structure, forming an interlayer insulating... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070243657 - Method and apparatus to form thin layers of materials on a base: The present invention relates to method and apparatus for preparing thin films of materials for various applications including electronic devices such as solar cells. In one aspect, each of the method and apparatus passing an electrical current through at least one of the base or sheet to provide controlled localized... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070243659 - Phase-changeable memory device and method of manufacturing the same: In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer... Agent: Marger Johnson & Mccollom, P.C.

20070243663 - Method of wafer level chip size packaging: A method of wafer level chip size packaging includes the steps of: grinding a wafer on a back surface to a predetermined thickness; sawing the wafer into a plurality of wafer slices; spray coating a photo resist layer on top of the wafer slice; applying a lithography process to form... Agent: Birch Stewart Kolasch & Birch

20070243660 - Method for fabricating white-light-emitting flip-chip diode having silicon quantum dots: The present invention is to fabricate a flip-chip diode which emits a white light. The diode has a film embedded with silicon quantum dots. And the white light is formed by mixing colorful lights through the film.... Agent: Troxell Law Office PLLC

20070243662 - Packaging of mems devices: The present invention is directed to a process for packaging a microelectrical, micromechanical, microelectromechanical (MEMS) or microfluidic component on a substrate by forming cavities made from crosslinked photoresists on an easily removable second substrate, bonding the cavities to third substrates containing selected microdevices, then peeling off the removable second substrate.... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070243661 - Thin semiconductor device package: A thin semiconductor device package, comprising a thin substrate, at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate, a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface... Agent: Intel Corporation C/o Intellevate, LLC

20070243664 - Flip-chip mounting method and bump formation method: [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are... Agent: Mcdermott Will & Emery LLP

20070243665 - Palladium-spot leadframes for high adhesion semiconductor devices and method of fabrication: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said... Agent: Texas Instruments Incorporated

20070243667 - Pop semiconductor device manufacturing method: The objective of the invention is to prevent electrostatic destruction of semiconductor chips during resin molding. With the semiconductor device manufacturing method, a substrate 400 that includes on the surface multiple semiconductor chips 410 and liquid resin 434 supplied to multiple semiconductor devices is supported by an electrically insulated lower... Agent: Texas Instruments Incorporated

20070243666 - Semiconductor package, array arranged substrate structure for the semiconductor package and fabrication method of the semiconductor package: A semiconductor package, an array arranged substrate structure for the semiconductor package, and fabrication method of the semiconductor package are disclosed. First, a substrate having a plurality of array arranged substrate units is provided, and electroplating buses are formed between the substrate units. Each substrate unit has a plurality of... Agent: Edwards Angell Palmer & Dodge LLP

20070243668 - Normally-off integrated jfet power switches in wide bandgap semiconductors and methods of making: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant... Agent: Merchant & Gould PC

20070243669 - Method for manufacturing solid-state image pickup element and solid-state image pickup element: The present invention provides a method for manufacturing a solid-state image pickup element in which an intralayer lens is formed above a solid-state image pickup element by: a first step of forming a film using an intralayer lens forming material; a second step of reducing an aspect ratio which is... Agent: Sughrue Mion, PLLC

20070243670 - Thin film transistor (tft) and method for fabricating the same: A method for fabricating a thin film transistor (“TFT”) device includes providing a substrate, forming a patterned amorphous silicon layer over the substrate including a pair of first regions, a second region disposed between the pair of first regions, and at least one third region, each of which being disposed... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070243671 - Butted source contact and well strap: A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a... Agent: Tung & Associates

20070243672 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a semiconductor layer 18 formed on an insulation layer 16, a gate electrode 22 formed on the semiconductor layer with a gate insulation film 20 formed therebetween, a source/drain region 24 formed on the semiconductor layer on both sides of the gate electrode, and a semiconductor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070243673 - Thin-film transistor array for lcd and the method for manufacturing the same: The present invention provides a thin-film transistor array, of which the units provide with a storage capacitor disposed in the thin-film transistor array and a protective layer of transparent conductive material covering the source/drain metal of the thin-film transistor array. The present invention also provides a method for manufacturing the... Agent: Lowe Hauptman Ham & Berner, LLP

20070243674 - Polytype hetero-interface high electron mobility device and method of making: A high electron mobility device and method of making is provided whereby a two-dimensional electron gas is formed at a hetero-junction or hetero-interface between different polytypes of a semiconductor material. The different crystal forms or polytypes of the semiconductor material having different electronic bandgaps are used to provide the bandgap... Agent: Volentine & Whitt PLLC

20070243675 - Use of silicon block process step to camouflage a false transistor: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.... Agent: Robert Popa C/o Ladas & Parry

20070243676 - Image sensor device and manufacturing method thereof: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS)... Agent: North America Intellectual Property Corporation

20070243677 - Semiconductor device having a schottky source/drain transistor: A semiconductor device comprises an island shaped channel layer formed on a substrate, the channel later being composed of a semiconductor material, a gate insulation film formed on the channel layer, a gate electrode formed on the gate insulation film, an insulation film formed on both side faces opposite to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070243678 - Inkjet printing of cross point passive matrix devices: A method of manufacturing a cross-point device, comprises: providing at least one first electrode on a substrate; providing first regions of an electrically functional material over the at least one first electrode; and providing at least one second electrode over the at least one first electrode and the plurality of... Agent: Oliff & Berridge, PLC

20070243679 - Process for manufacturing a non-volatile memory structure via soft lithography: A process for manufacturing a non-volatile memory structure, in particular of a cross-point type provided with an array of memory cells, including forming bottom electrodes on a substrate; forming areas of active material on the bottom electrodes; and forming top electrodes on the areas of active material. The memory cells... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070243680 - Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element: Methods of fabricating a dual control gate non-volatile memory array are described. Parallel strips of floating gate material are formed over the substrate in a first direction but separated from it by a tunnel dielectric. In the gaps between these strips control gate material is formed forming a second set... Agent: Davis Wright Tremaine LLP

20070243681 - Method of fabricating flash memory device using sidewall process: A method of fabricating a flash memory device includes depositing and etching an insulating layer on a substrate having STI structures, depositing a first polysilicon layer over the insulating layer and the substrate, etching the first polysilicon layer to form floating gates and removing the insulating layer. The method also... Agent: Sherr & Nourse, PLLC

20070243682 - Flash memory device having a graded composition, high dielectric constant gate insulator: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator is comprised of amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070243683 - A method for forming multi gate devices using a silicon oxide masking layer: The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate... Agent: Texas Instruments Incorporated

20070243684 - Semiconductor device and method of manufaturing the same: The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A... Agent: Young & Thompson

20070243685 - Method and structure for self aligned formation of a gate polysilicon layer: A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon... Agent: Townsend And Townsend And Crew, LLP

20070243686 - Method of forming compressive nitride film and method of manufacturing metal oxide semiconductor: A method of forming compressive nitride film is provided. The method includes performing a chemical vapor deposition (CVD) process to form a nitride film on a substrate, and the method is characterized by adding a certain gas, selected from among Ar, N2, Kr, Xe, and mixtures thereof. Due to the... Agent: Jianq Chyun Intellectual Property Office

20070243687 - Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulting film: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070243688 - Method for forming strained semiconductor device and method for forming source/drain region: A method for forming a strained semiconductor device is described. A substrate including a first semiconductor material and having a first conductivity type is provided. A semiconductor layer of a second conductivity type is formed contacting with the substrate, wherein the semiconductor layer includes the first semiconductor material and a... Agent: Jianq Chyun Intellectual Property Office

20070243689 - Semiconductor device having semiconductor and base contact pad mesa portions: A semiconductor device, able to be produced while suppressing the occurrence of mesa shaped abnormalities without restriction as to the pattern layout, the type of etchant used, etc., provided with a semiconductor mesa portion including a stack of a collector layer, a base layer, and an emitter layer on a... Agent: Rader Fishman & Grauer PLLC

20070243691 - Manufacturing method of semiconductor device: Even in the case of manufacturing a fine ferroelectric memory, deterioration of a ferroelectric film can be prevented. An aluminum oxide film is formed by an ALD method to cover a ferroelectric capacitor formed above a semiconductor substrate, and after the aluminum oxide film is formed, annealing treatment is performed... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070243690 - Methods for fabricating a capacitor: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to... Agent: Quintero Law Office, PC

20070243692 - Methods of filling isolation trenches for semiconductor devices and resulting structures: The invention relates to a method and resulting structure that can substantially minimize and/or eliminate void formation during an isolation trench isolation fill process for typical trench shaped and goal-post shaped isolation regions. First, a thin thermal oxidation layer is grown on the sidewall of each trench and then a... Agent: Dickstein Shapiro LLP

20070243693 - Integrated process modulation (ipm) a novel solution for gapfill with hdp-cvd: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of... Agent: Townsend And Townsend And Crew LLP / Amat

20070243694 - Bonded wafer and method of producing the same: A bonded wafer is produced by bonding an ion-implanted wafer for an active layer onto a wafer for a supporting substrate, and thereafter exfoliating the wafer for the active layer at the ion-implanted position through a heat treatment and then polishing a terrace portion of the resulting active layer with... Agent: Sughrue Mion, PLLC

20070243695 - Method for producing semiconductor wafers and a system for determining a cut position in a semiconductor ingot: A method for producing semiconductor wafers, from a semiconductor ingot, wherein an oxygen concentration distribution in the growth axis direction is measured in the ingot state (F2), a position at which the oxygen concentration is maximum or minimum in a range of a predetermined length is determined as a cut... Agent: Oliff & Berridge, PLC

20070243696 - Laser beam processing machine: A laser beam processing machine comprising a path distribution means for distributing a pulse laser beam oscillated by pulse laser beam oscillation means to a first path and a second path alternately, and one laser beam that passes through one of the paths and is converged by one condensing lens... Agent: Smith, Gambrell & Russell

20070243697 - Lithographic apparatus and device manufacturing method: An immersion lithographic exposure apparatus in which the pH of the top coat of the immersion liquid is chosen so as to maximize the relative speed at which a part of the liquid supply system and the substrate W can be moved relative to each other without collapse of a... Agent: Pillsbury Winthrop Shaw Pittman, LLP Eric S. Cherry - Docketing Supervisor

20070243698 - Polysilicon film having smooth surface and method of forming the same: A method of forming a polysilicon film having smooth surface using a lateral growth and a step-and-repeat laser process. Amorphous silicon formed in a first irradiation region of a substrate is crystallized to form a first polysilicon region by a first laser shot. Then, the substrate is moved a predetermined... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070243699 - Method of manufacturing silicon epitaxial wafer: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 Ω·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1,... Agent: Snider & Associates

20070243700 - Method of photoresist strip for plasma doping process of semiconductor manufacturing: A method of forming an intermediate semiconductor device is disclosed that comprises providing a semiconductor substrate, forming a photoresist layer on the semiconductor substrate, implanting a dopant into the semiconductor substrate, and removing a dopant-containing layer from the photoresist layer. The dopant-containing layer includes dopant residuals and a carbon-rich crust... Agent: Trask Britt, P.C./ Micron Technology

20070243701 - Semiconductor device fabrication method using ultra-rapid thermal annealing: An impurity is ion-implanted into the major surface of an Si substrate having a bulk microdefect density of 5×106 to 5×107 cm−3, a bulk microdefect size smaller than 100 nm, and a dissolved oxygen concentration of 1.1×1018 to 1.2×1018 cm−3. The Si substrate then undergoes ultra-rapid thermal annealing whose heating/cooling... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070243702 - Dual-side epitaxy processes for production of nitride semiconductor structures: Methods are provided of fabricating a nitride semiconductor structure. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over one side of the substrate with a thermal chemical-vapor-deposition process. A second layer is similarly deposited over an opposite side of the... Agent: Townsend And Townsend And Crew LLP / Amat

20070243703 - Processes and structures for epitaxial growth on laminate substrates: A method of making a semiconductor device includes providing a laminate substrate made by bonding a II-VI or III-V semiconductor laminate film to a support substrate, and preparing the laminate film to enable growth of a II-VI or III-V semiconductor device layer on the laminate substrate.... Agent: Foley And Lardner LLP Suite 500

20070243704 - Substrate structure having a solder mask and a process for making the same: The present invention relates to a substrate structure having a solder mask and a process for making the same. The process comprises: (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on... Agent: Volentine & Whitt PLLC

20070243705 - Methods and apparatus for sensor having capacitor on chip: A magnetic sensor comprises a plurality of layers including a substrate having circuitry, at least one conductive layer to interconnect the circuitry, and an insulator layer to electrically insulate the at least one conductive layer. First and second conductive layers are disposed above the substrate with a dielectric layer disposed... Agent: Daly, Crowley, Mofford & Durkee, LLP

20070243706 - Method of manufacturing a through electrode: A through electrode that offers excellent performance and can be manufactured through a simple process is to be provided. In a silicon spacer including a silicon substrate, an insulative thick film is provided so as to be in contact with a surface of the silicon substrate and a side wall... Agent: Young & Thompson

20070243707 - Hard mask layer stack and a method of patterning: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer... Agent: Dicke, Billig & Czaja

20070243708 - Manufacturing method for an integrated semiconductor contact structure having an improved aluminum fill: The present invention provides a manufacturing method for an integrated semiconductor contact structure having an improved Aluminum fill comprising the steps of: forming contact holes in an insulation layer provided on a wafer, said contact holes having a respective bottom and respective sidewalls, said bottoms including a respective conductive area;... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070243710 - Adjuvant for cmp slurry: Disclosed is an adjuvant in use for a process of polishing a cationically charged material and an anionically charged material at the same time with abrasive particles, which is absorbed onto the cationically charged material thereby to restrain the cationically charged material from being polished, resulting in raising a polishing... Agent: Mckenna Long & Aldridge LLP

20070243709 - Planarization of substrates at a high polishing rate using electrochemical mechanical polishing: A method and apparatus for removing conductive material from a substrate surface are provided. In one embodiment, a method is provided for electrochemical mechanical polishing of a substrate. A substrate comprising dielectric feature definitions, a barrier material disposed on the feature definitions, and a bulk conductive material in an amount... Agent: Patterson & Sheridan, LLP

20070243711 - Substrate treatment method and substrate treatment apparatus: To improve the etch resistance of a resist pattern corresponding to an exposure light source with a short wavelength. After a resist film on a substrate is exposed to light and developed to form a resist pattern, a treatment step of supplying a fluorine-based liquid to the surface of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070243712 - Mask profile control for controlling feature profile: A method for etching features into a dielectric layer over a substrate and existent below a polymeric hard mask is provided. The substrate is placed in a plasma processing chamber. Mask features are etched into the polymeric hard mask and necks are formed inadvertently. A plasma treatment process performed before... Agent: Beyer Weaver LLP

20070243713 - Apparatus and method for generating activated hydrogen for plasma stripping: A microwave source is used to create activated hydrogen in its ground state. An electron gun is used to boost the activated hydrogen into a metastable state by electron bombardment. The metastable activated hydrogen may then be used in a plasma etch to remove residue from a low k material.... Agent: Womble Carlyle Sandridge & Rice, PLLC

20070243714 - Method of controlling silicon-containing polymer build up during etching by using a periodic cleaning step: A method of removing a silicon-containing hard polymeric material from an opening leading to a recessed feature during the plasma etching of said recessed feature into a carbon-containing layer in a semiconductor substrate. The method comprises the intermittent use of a cleaning step within a continuous etching process, where at... Agent: Shirley L. Church, Esq.

20070243715 - Cleaning solution and method for selectively removing layer in a silicidation process: A cleaning solution selectively removes a titanium nitride layer and a non-reacting metal layer. The cleaning solution includes an acid solution and an oxidation agent with iodine. The cleaning solution also effectively removes a photoresist layer and organic materials. Moreover, the cleaning solution can be employed in tungsten gate electrode... Agent: F. Chau & Associates, LLC

20070243717 - Carbon nanotube apparatus and method of carbon nanotube modification: Carbon nanotube apparatus, and methods of carbon nanotube modification, include carbon nanotubes having locally modified properties with the positioning of the modifications being controlled. More specifically, the positioning of nanotubes on a substrate with a deposited substance, and partially vaporizing part of the deposited substance etches the nanotubes. The modifications... Agent: Naval Surface Warfare Center Dahlgren Division Office Of Counsel, Code Xdc1

20070243718 - Dye sensitive metal oxide semiconductor electrode, method for manufacturing the same, and dye sensitized solar cell: Provided are a dye sensitized metal oxide semiconductor electrode having a metal oxide semiconductor film that can adsorb a sufficient amount of dye due to a high specific surface area and exhibits high electrical conductivity due to tight contact of metal oxide particles, and a dye sensitized solar cell that... Agent: Sughrue Mion, PLLC

20070243716 - Selection and deposition of nanoparticles using co2-expanded liquids: A method for size selection of nanostructures comprising utilizing a gas-expanded liquids (GEL) and controlled pressure to precipitate desired size populations of nanostructures, e.g., monodisperse. The GEL can comprise CO2 antisolvent and an organic solvent. The method can be carried out in an apparatus comprising a first open vessel configured... Agent: Gardner Groff Greenwald & Villanueva. PC

20070243719 - Shadow mask deposition of materials using reconfigurable shadow masks: A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are... Agent: The Webb Law Firm, P.C.

20070243721 - Absorber layer for dsa processing: A method of processing a substrate comprising depositing a layer comprising amorphous carbon on the substrate and then exposing the substrate to electromagnetic radiation have one or more wavelengths between about 600 nm and about 1000 nm under conditions sufficient to heat the layer to a temperature of at least... Agent: Patterson & Sheridan, LLP

20070243720 - Uv treatment for low-k dielectric layer in damascene structure: An UV treatment for making a low-k dielectric layer having improved properties in a damascene structure. A low-k dielectric layer in a damascene structure is subjected to an UV treatment with He gas or H2 gas to eliminate etching damage to the exposed surfaces of the low-k dielectric layer.... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070243722 - Silicon carbide semiconductor device and manufacturing method thereof: A method of manufacturing a device on a silicon carbide substrate is disclosed. The device includes an oxide layer which has silicon oxide as a main component on the silicon carbide semiconductor substrate. The method includes depositing and oxide layer on a surface of the silicon carbide semiconductor substrate; raising... Agent: Rossi, Kimms & Mcdowell LLP.

20070238200 - Method of nbti prediction: A method includes measuring a gate leakage current of a plurality of transistors. A single stress bias voltage is applied to the plurality of transistors. The stress bias voltage causes a 10% degradation in a drive current of each transistor within a respective stress period t. One or more relationships... Agent: Duane Morris LLPIPDepartment (tsmc)

20070238204 - Manufacturing method of semiconductor device: The present invention provides a manufacturing technique of a semiconductor device that reduces fluctuation of electric characteristic and a working size of a semiconductor device and can manufacture semiconductor devices at high quality and at high yield. In a semiconductor device manufacturing system, a control method for a manufacturing process... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070238208 - Optical device and method for manufacturing optical device: A method for manufacturing an optical device, the method comprising the steps of: (a) laminating, above a substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer that functions as an active layer, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer... Agent: Harness, Dickey & Pierce, P.L.C

20070238209 - Modulation of step function phenomena by varying nanoparticle size: The present invention is directed to methods and systems of modulating step function phenomena by varying nanoparticle size—particularly wherein a plurality of such nanoparticles are employed, and wherein said nanoparticles comprise a size distribution favorable for collectively smoothing the step function. Such methods and systems are particularly favorable for hydrogen... Agent: Fish & Richardson P.C.

20070238214 - Substrate structure with patterned layer and method for manufacturing same: A substrate structure includes a substrate, a number of banks formed on the substrate, and a patterned layer. The banks and the substrate cooperatively define a number of accommodating rooms. The accommodating rooms are configured for accommodating ink. The patterned layer covers the bank between at least two adjacent accommodating... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070238216 - Solar cell and its method of manufacture: A solar cell having improved efficiency and its method of manufacture includes: forming a porous layer on a surface of a semiconductor substrate; spraying a compound containing a dopant on the porous layer; and forming an emitter layer on the surface of the semiconductor substrate by diffusing the dopant.... Agent: Robert E. Bushnell Suite 300

20070238217 - manufacturing method for a liquid crystal display: A method for manufacturing a liquid crystal display includes the following steps. First, source/drain and a bottom electrode are formed over a color filter substrate with a color filter layer. The next step forms source/drain junction regions over the source/drain. A channel region is also formed between the source/drain in... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070238198 - Three terminal magnetic sensing devices having base lead layers in-plane with collector substrate materials and methods of making the same: Three terminal magnetic sensing devices (TTMs) having base lead layers in-plane with collector substrate materials, and methods of making the same, are disclosed. In one illustrative example, a collector substrate having an elevated region and a recessed region adjacent the elevated region is provided. An insulator layer is formed in... Agent: John J. Oskorep, Esq. One Magnificent Mile Center

20070238199 - Method for conditioning a process chamber: A method of conditioning a processing chamber for a production process includes performing a conditioning step at a conditioning process recipe substantially different than a process recipe of the production process, and performing a warm-up process at a warm-up process recipe substantially the same as the process recipe of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070238202 - Adaptive control method for rapid thermal processing of a substrate: The present invention generally relates to methods for the rapid thermal processing (RTP) of a substrate. Embodiments of the invention include controlling a thermal process using either a real-time adaptive control algorithm or by using a control algorithm that is selected from a suite of fixed control algorithms designed for... Agent: Patterson & Sheridan, LLP

20070238201 - Dynamic metrology sampling with wafer uniformity control: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, bi-layer mask data, and BARC... Agent: Dla Piper US LLP

20070238203 - Method of monitoring pcmo precursor synthesis: A method of monitoring synthesis of PCMO precursor solutions includes preparing a PCMO precursor solution and withdrawing samples of the precursor solution at intervals during a reaction phase of the PCMO precursor solution synthesis. The samples of the PCMO precursor solution are analyzed by UV spectroscopy to determine UV transmissivity... Agent: Robert D. Varitz

20070238205 - Lead frame based, over-molded semiconductor package with integrated through hole technology (tht) heat spreader pin(s) and associated method of manufacturing: A method and apparatus are provided for manufacturing a lead frame based, over-molded semiconductor package (7) with an exposed pad or power die flag (70) having multiple integrated THT heat spreader pins (71) configured for insertion into one or more vias (77) formed in a printed circuit board (78). The... Agent: Hamilton & Terrile, LLP

20070238206 - System and apparatus for using test structures inside of a chip during the fabrication of the chip: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known... Agent: Shemwell Mahamedi LLP

20070238207 - Semiconductor constructions: In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material... Agent: Wells St. John P.s.

20070238210 - Method for producing an optoelectronic component: A method for producing an optoelectronic component is disclosed. The method includes the steps of providing a substrate, applying a semiconductor layer sequence to the substrate, applying at least two current expansion layers to the semiconductor layer sequence, applying and patterning a mask layer, patterning the second current expansion layer... Agent: Cohen, Pontani, Lieberman & Pavane

20070238211 - Growing lower defect semiconductor crystals on highly lattice-mismatched substrates: A heterosystem of two different materials, mismatched in terms of lattice constant or symmetry, may be formed with reduced defects by using a two step approach proposed in this invention. Nanowires are first grown on a semiconductor substrate, and then a thin film of the disparate crystallographically inconsistent material is... Agent: Trop Pruner & Hu, PC

20070238212 - Micro-electromechanical structure with self-compensation of the thermal drifts caused by thermomechanical stress: In a micro-electromechanical structure of semiconductor material, a detection structure is formed by a stator and by a rotor, which are mobile with respect to one another in presence of an external stress and are subject to thermal stress; a compensation structure of a micro-electromechanical type, subject to thermal stress... Agent: Seed Intellectual Property Law Group PLLC

20070238213 - Microstructure and manufacturing method thereof and microelectromechanical system: An object is to provide a microstructure in which shear stress of a structural layer is increased, a manufacturing method thereof, and a microelectromechanical system. A sacrificial layer is formed over a substrate. A metal film is formed over the sacrificial layer. The metal film is irradiated with a laser... Agent: Fish & Richardson P.C.

20070238215 - Pressure transducer with increased sensitivity: Silicon piezoresistor low pressure transducers can not be made cost effectively with a full scale output large enough to interface to control electronics. The size of the diaphragm, and therefore the size of the die required to produce a sufficient span make the die cost prohibitive. Simultaneously forming transistors and... Agent: Bryan Anderson Honeywell International Inc.

20070238218 - Method for fabricating active matrix organic light emitting diode display device and structure of such device: A method for fabricating an AMOLED display device is provided. A substrate is provided. A device layer having multiple active devices is formed on the substrate. A flat layer is configured on the device layer. A first, a second and a third color photoresistant layers are respectively configured on the... Agent: Jianq Chyun Intellectual Property Office

20070238221 - Method and apparatus for automatically shaping traces on surface of substrate of semiconductor package by using computation: A method and an apparatus for automatically shaping traces by using computation comprises: setting means that sets an equiangular octagon circumscribing a clearance circle indicating a position where clearance can be secured from vias so that one side of such equiangular octagon is in parallel with a reference line; setting... Agent: Staas & Halsey LLP

20070238219 - Low stress optics mount using thermally conductive liquid metal or gel: An optical assembly with mounting provided to effectively transfer heat away from an optic, such as a slab or waveguide amplifier or laser disk, while limiting internal stresses. The assembly includes an optic with a planar surface. A heat sink is positioned in the assembly with an upper surface next... Agent: Mcdermott Will & Emery LLP

20070238220 - Stratified underfill in an ic package: A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of... Agent: Duane Morris LLPIPDepartment (tsmc)

20070238223 - Apparatus and method for signal bus line layout in semiconductor device: A device and method for layout and fabrication of power supply bus lines in an integrated circuit such as a memory circuit are described. In accordance with the present invention, power bus lines and bonding pads of the circuit are not necessarily formed in both edge regions and center regions... Agent: Mills & Onello LLP

20070238222 - Apparatuses and methods to enhance passivation and ild reliability: Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.... Agent: Intel Corporation C/o Intellevate, LLC

20070238224 - Printed circuit board: A printed circuit board includes a signal layer, a pair of signal lines, and a plurality of conductive pads arranged on the signal layer. The conductive pads are located between the two signal lines for reducing crosstalk.... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070238225 - Phase change memory with improved temperature stability: A phase change memory may be formed using a chalcogenide material that includes selenium. The inclusion of selenium improves the heat stability of the resulting memory device. The chalcogenide may also be a lean germanium composition.... Agent: Trop Pruner & Hu, PC

20070238226 - Three dimensional programmable device and method for fabricating the same: A three-dimensional memory device having polycrystalline silicon diode isolation elements for phase change memory cells and method for fabricating the same. The memory device includes a plurality of stacked memory cells to form a three-dimensional memory array. The polycrystalline silicon diode element selects the phase change memory cell. The memory... Agent: Trop Pruner & Hu, PC

20070238227 - Thin film transistor panel, method of fabricating the same, and organic light emitting display device including the same: Provided are a thin film transistor (TFT) panel, a method of fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT panel has a TFT region and a capacitor region. A TFT is formed in the TFT region and a capacitor is formed in... Agent: Robert E. Bushnell Suite 300

20070238229 - Fabrication methods for self-aligned ldd thin-film transistor: A self-aligned LDD TFT and a fabrication method thereof. The method includes providing a semiconductor layer. A first masking layer is provided over a first region of the semiconductor layer, said first masking layer comprising a material that provide a permeable barrier to a dopant. The semiconductor layer is exposed,... Agent: Liu & Liu

20070238228 - Manufacturing method for thin film transistor: A manufacturing method for a thin film transistor (TFT) is provided. In the manufactured TFT, after a source structure, a drain structure and a channel structure are formed, a first photoresist layer is not removed and a second photoresist is formed on the first photoresist layer through which a semiconductor... Agent: Apex Juris, PLLC Tracy M Heims

20070238230 - Method for forming thin film transistor: A method for forming a pattern is provided. First, a substrate is provided. Then, a discontinuous film is formed on the substrate so as to reduce the stress of the film. After that, the discontinuous film is patterned to form a pattern. Besides, a method for manufacturing a thin film... Agent: Jianq Chyun Intellectual Property Office

20070238231 - Thin film devices for flat panel displays and methods for forming the same: Methods of forming thin film devices with different electrical characteristics on a substrate comprising a driver circuit region and a pixel region. A first and a second polysilicon pattern layers are formed on the driving circuit region and the pixel region of the substrate, respectively. A first ion implantation is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070238232 - Transistor or semiconductor device and method of fabricating the same: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive... Agent: Ladas & Parry LLP

20070238233 - Method of making a multiple crystal orientation semiconductor device: A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer... Agent: Freescale Semiconductor, Inc. Law Department

20070238234 - Method of forming a mos transistor: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region,... Agent: North America Intellectual Property Corporation

20070238235 - Semiconductor device and fabricating method thereof: A method for fabricating a semiconductor device is provided. First, a substrate is provided, and a first-type MOS (metallic oxide semiconductor) transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor are formed on the substrate. Then, a first stress layer is formed to overlay the substrate,... Agent: Jianq Chyun Intellectual Property Office

20070238236 - Structure and fabrication method of a selectively deposited capping layer on an epitaxially grown source drain: A method and apparatus to improve the contact formation of salicide and reduce the external resistance of a transistor is disclosed. A gate electrode is formed on a surface of a substrate. A source region and a drain region are isotropically etched in the substrate. A Silicon Germanium alloy is... Agent: Blakely Sokoloff Taylor & Zafman

20070238237 - Structure and method for a sidewall sonos non-volatile memory device: A non-volatile semiconductor memory device includes a gate stack formed on a substrate, semiconductor spacers, an oxide-nitride-oxide stack, and a contact pad. The semiconductor spacers are adjacent to sides of the gate stack and over the substrate. The oxide-nitride-oxide stack is located between the spacers and the gate stack, and... Agent: Slater & Matsil, L.L.P.

20070238238 - Cmos device and fabricating method thereof: A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the... Agent: J.c. Patents, Inc.

20070238240 - Method of forming a transistor in a non-volatile memory device: A field-effect transistor is formed that has spacers formed by etching openings into a conductive layer and filling the openings with spacer material. The openings are formed together with a gate web in the conductive layer, wherein the gate web is surrounded by the openings on at least two sides.... Agent: Slater & Matsil LLP

20070238239 - Rare earth element-doped oxide precursor with silicon nanocrystals: A method is provided for forming a rare earth element-doped silicon oxide (SiO2) precursor with nanocrystalline (nc) Si particles. In one aspect the method comprises: mixing Si particles into a first organic solvent, forming a first solution with a first boiling point; filtering the first solution to remove large Si... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070238241 - Semiconductor structure and fabricating method thereof: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor... Agent: J.c. Patents Suite 250

20070238242 - Semiconductor structure and fabrication thereof: A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and... Agent: J.c. Patents, Inc.

20070238243 - Fabrication method: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second... Agent: Agere Lerner, David Et Al.

20070238245 - Transfer tape strap process: A method for efficiently producing a plurality of EAS or RFID tags or inlays that form a label ready for use. The process utilizes a first web of RFID chip straps or capacitor straps that are releasably secured to a liner using only a low tack adhesive and utilizes a... Agent: Caesar, Rivise, Bernstein, Cohen & Pokotilow, Ltd.

20070238244 - Trench-capacitor dram device and manufacture method thereof: A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on... Agent: North America Intellectual Property Corporation

20070238247 - Method of fabricating active layer thin film by metal chalcogenide precursor solution: A method of fabricating an active layer thin film by a metal-chalcogenide precursor solution is provided, including the steps of: synthesizing a metal-chalcogenide precursor containing benzyl or benzyl derivative; dissolving the precursor in a solvent to produce a precursor solution, wherein a chalcogen element or compound can be added to... Agent: Rabin & Berdo, P.C.

20070238248 - Manufacturing method of semiconductor device and semiconductor device: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070238246 - Resistance random access memory devices and method of fabrication: A method of fabricating a RRAM includes preparing a substrate and forming a bottom electrode ori the substrate. A PCMO layer is deposited on the bottom electrode using MOCVD or liquid MOCVD, followed by a post-annealing process. The deposited PCMO thin film has a crystallized PCMO structure or a nano-size... Agent: Robert D. Varitz

20070238249 - Programmable structure including control gate overlying select gate formed in a trench: A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by... Agent: Freescale Semiconductor, Inc.

20070238250 - Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor: A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors... Agent: Freescale Semiconductor, Inc.

20070238251 - Method of forming sub-100nm narrow trenches in semiconductor substrates: A method to form a narrow trench within a semiconductor substrate includes exemplary steps of: (a) A CVD layer such as SiO2 represented as “CVD1” is deposited on top of a semiconductor surface followed by a different type of CVD layer such as SiON or Si3N4 (represented by “CVD2” deposited... Agent: Bo-in Lin

20070238252 - Cosmic particle ignition of artificially ionized plasma patterns in the atmosphere: This invention is a method and apparatus for creating artificially ionized regions in the atmosphere utilizing ionization trails of cosmic rays and micro-meteors to ignite plasma patterns in electric field patterns formed by ground based electromagnetic wave radiators. The applications are useful for telecommunications, weather control, lightening protection and defense... Agent: Bernard Eastlund

20070238253 - Semiconductor transistors having reduced channel widths and methods of fabricating same: A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a first type of ions in the portion... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20070238255 - Semiconductor device and manufacturing method of the same: A semiconductor device includes: a layer provided on or above a semiconductor substrate, having an opening, and containing Si and Ge; and a gate provided at a position corresponding to the opening. It is possible to provide a semiconductor device and a manufacturing method of the same which realize easy... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070238254 - Method of etching low dielectric constant films: A method for etching a low dielectric material to form sidewall spacers including forming a gate electrode on a substrate, forming a source region and a drain region disposed in a substrate, forming a low dielectric constant film over the gate electrode, source region, and drain region, and etching the... Agent: Patterson & Sheridan, LLP

20070238256 - Catalytic flow-through fast light off ceramic substrate and method of manufacture: A fast light off flow-through ceramic substrate is provided that is particularly adapted for use as a catalytic converter. The substrate is formed from a body of ceramic material having axially opposing inlet and outlet ends for receiving and expelling the flow of automotive exhaust gas, respectively. The body contains... Agent: Corning Incorporated

20070238257 - Method for coating metal surfaces: A composition for producing a protective coat against scaling on metallic surfaces. The composition includes, as binders, hydrolysates/condensates of at least one silane or a silicone resin binder and also, further, at least one metallic filler.... Agent: Lerner Greenberg Stemer LLP

20070238258 - Selective links in silicon hetero-junction bipolar transistors using carbon doping and method of forming same: Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a... Agent: Schmeiser, Olsen & Watts

20070238259 - Methods of forming a plurality of capacitors: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive... Agent: Wells St. John P.s.

20070238260 - Method for forming shallow trench isolation region: A method for forming a shallow trench isolation (STI) structure is provided. A pad oxide layer and a nitride silicon layer are formed on a provided substrate sequentially. The pad oxide layer, the nitride silicon layer and the substrate are then etched to form a trench. An oxide liner and... Agent: Baker & Mckenzie LLP Patent Department

20070238261 - Device, lithographic apparatus and device manufacturing method: A device for locally treating a substrate is disclosed. The device includes an enclosure for forming an enclosed environment at a location on the substrate, a seal for sealing the enclosed environment between the enclosure and the substrate, a supply channel for supplying a chemical reactant to the location, and... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070238263 - Method for bonding a semiconductor substrate to a metal substrate: A method of bonding a semiconductor substrate to a metal substrate is disclosed. In some embodiments the method includes forming a semiconductor device in a semiconductor substrate, the semiconductor device comprising a first surface. The method further includes obtaining a metal substrate. The metal substrate is bonded to the first... Agent: Townsend And Townsend And Crew, LLP

20070238262 - Wafer bonding material with embedded rigid particles: A material for bonding a lid wafer to a device wafer, which includes an adhesive substance with rigid particles embedded in the adhesive substance. The rigid particles may be particles or spheres of alumina, silica, or diamond, for example. The adhesive substance may be glass frit, epoxy, glue, cement or... Agent: Jaquelin K. Spong

20070238264 - Method and apparatus for supporting wafer: To support a wafer integrally with a ring frame via an adhesive tape without damaging the wafer, and preventing a bubble from entering between the wafer and the adhesive tape, a surface side of the wafer is held on a chuck table; a central portion of an adhesive surface of... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070238265 - Plating apparatus and plating method: A plating apparatus can form a plated film having a more uniform thickness over an entire surface of a substrate and can securely fill interconnect recesses with the metal without forming voids in the embedded metal even when the substrate has a high sheet resistance in the surface. The plating... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070238266 - Non-uniform minority carrier lifetime distributions in high performance silicon power devices: This invention is directed to a process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment... Agent: Senniger Powers

20070238267 - Epitaxy of silicon-carbon substitutional solid solutions by ultra-fast annealing of amorphous material: Expitaxial substitutional solid solutions of silicon carbon can be obtained by an ultrafast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature... Agent: International Business Machines Corporation Dept. 18g

20070238268 - Low-temperature dielectric formation for devices with strained germanium-containing channels: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and generating a soft plasma... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070238269 - Method for manufacturing simox wafer and simox wafer obtained by this method: It is an object of the present invention to provide a method for manufacturing SIMOX wafer, wherein roughness Rms of a measurement area of 10 square micrometers in a surface of an SOI layer and roughness Rms of a measurement area of 10 square micrometers in an interface between the... Agent: Reed Smith, LLP Attn: Patent Records Department

20070238270 - Method for forming polycrystalline film: Disclosed is a method for forming a polycrystalline film. The method for forming a polycrystalline film from a film deposited on a glass substrate while a buffer layer is interposed between the deposited film and the glass substrate, which includes the steps of: preparing a mask including a transparent region... Agent: Seyfarth Shaw LLP

20070238271 - Method of manufacturing semiconductor device: A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting... Agent: Posz Law Group, PLC

20070238272 - Method of aligning carbon nanotubes and method of manufacturing field emission device using the same: A method of aligning carbon nanotubes (CNTs) and a method of manufacturing a field emission device (FED) using the same, wherein a mold having an intaglio pattern is prepared, an aqueous solution containing an amphiphilic organic material and the CNTs are coated on a surface of a substrate, the mold... Agent: Robert E. Bushnell

20070238273 - Method of ion implanting for tri-gate devices: A method for ion implanting a tip source and drain region and halo region for a tri-gate field-effect transistor is described. A silicon body is implanted, in one embodiment, from six different angles to obtain ideal regions.... Agent: Blakely Sokoloff Taylor & Zafman

20070238274 - Methods of making spintronic devices with constrained spintronic dopant: A method is for making a spintronic device and may include forming at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070238275 - Catalyst-aided chemical processing method: A catalyst-aided chemical processing method is a novel processing method having a high processing efficiency and suited for processing in a space wavelength range of not less than several tens of μm. The catalyst-aided chemical processing method comprises: immersing a workpiece in a processing solution in which a halogen-containing molecule... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070238276 - Control of poly-si depletion in cmos via gas phase doping: A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are... Agent: Scully Scott Murphy & Presser, PC

20070238277 - Method of fabricating semiconductor device employing selectivity poly deposition: A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070238278 - Method of separating a structure in a semiconductor device: Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher portion. A second material is then... Agent: Freescale Semiconductor, Inc. Law Department

20070238280 - Semiconductor device having contact plug and method for fabricating the same: An improved method of fabricating a contact plug is described herein. The method includes forming a first insulation layer including a first contact hole over a substrate, forming protection layers on both sidewalls of the first contact hole, filling the first contact hole with a conductive material to form a... Agent: Lowe Hauptman Ham & Berner, LLP

20070238279 - Barrier deposition using ionized physical vapor deposition (ipvd): An iPVD system uses a high density inductively coupled plasma (ICP) at high pressure of at least 50 mTorr to deposit uniform ultra-thin layer of a tantalum nitride material barrier material onto the sidewalls of high aspect ratio nano-size features on semiconductor substrates, preferably less than 2 nm thick with... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070238281 - Depositing polar materials on non-polar semiconductor substrates: Lattice mismatch and polar to non-polar issues may lead to dislocations and other defects between silicon or germanium substrates and group III-V materials such as indium antimonide. The provision of lattice matching layers and buffer layers may enable these defects to be reduced.... Agent: Trop Pruner & Hu, PC

20070238282 - Method and apparatus for deploying a liquid metal thermal interface for chip cooling: In one embodiment, the present invention is a method and apparatus for chip cooling. One embodiment of an inventive method for bonding a liquid metal to an interface surface (e.g., a surface of an integrated circuit chip or an opposing surface of a heat sink) includes applying an adhesive to... Agent: Patterson & Sheridan LLP IBM Corporation

20070238283 - Novel under-bump metallization for bond pad soldering: An under bump metallurgy (UBM) structure formed over a bond pad and for use in conjunction with a solder ball, provides an upper copper layer over a subjacent composite film that includes a nickel film over a further copper film over a titanium film. One or more reflow operations are... Agent: Duane Morris LLPIPDepartment (tsmc)

20070238285 - Method for making an improved thin film solar cell interconnect using etch and deposition process: The present invention provides a method of forming interconnects in a photovoltaic module. According to one aspect, a method according to the invention includes processing steps that are similar to those performed in conventional integrated circuit fabrication. For example, the method can include masks and etches to form isolation grooves... Agent: Applied Materials, Inc.

20070238284 - Touch panel fabrication method: A touch panel fabrication method includes the steps of (a) preparing a first substrate and a second substrate, (b) disposing a seal frame having an opening on the first substrate, (c) coupling the first substrate and the second substrate together by the seal frame such that a vacancy is defined... Agent: Bacon & Thomas, PLLC

20070238286 - Method of manufacturing semiconductor device: A method of manufacturing semiconductor devices, including the steps of forming an insulating layer on a semiconductor substrate in which predetermined structures are formed, and etching the insulating layer to expose a predetermined region of the semiconductor substrate, thereby forming a contact hole, forming an insulating layer on the sides... Agent: Marshall, Gerstein & Borun LLP

20070238287 - Methods of forming semiconductor constructions, and methods of selectively removing metal-containing materials relative to oxide: The invention includes methods of selectively removing metal-containing copper barrier materials (such as tantalum-containing materials, titanium-containing materials and tungsten-containing materials) relative to oxide (such as silicon dioxide) and/or copper. The selective removal can utilize etchant solutions containing hydrofluoric acid and one or more carboxylic acids. The etchant solutions can contain... Agent: Wells St. John P.s.

20070238288 - Method for integrating a conformal ruthenium layer into copper metallization of high aspect ratio features: A method of integrated processing of a patterned substrate for copper metallization. The method includes providing the patterned substrate containing a via and a trench in a vacuum processing tool, and performing an integrated process on the patterned substrate in the vacuum processing tool by depositing a first metal-containing layer... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070238289 - Semiconductor device and method of producing the same: A method of producing a semiconductor device includes the steps of forming a protrusion electrode on a semiconductor chip; and sealing the protrusion electrode and a semiconductor substrate with a resin layer. The method further includes the steps of polishing the resin layer until an upper surface of the protrusion... Agent: Takeuchi & Kubotera, LLP

20070238290 - Semiconductor device and manufacturing method thereof: A semiconductor device manufacturing method including forming at least a first conductive film and a first insulting film above a semiconductor substrate, forming a plurality of first resist patterns above the first insulating film periodically at first intervals, patterning at least the first insulting film by use of the first... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070238291 - Method for fabricating nanoscale features: One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon layer exposed at the bottom of the troughs and trough segments is then... Agent: Hewlett Packard Company

20070238292 - Semiconductor device manufacturing method and semiconductor manufacturing apparatus: A semiconductor device manufacturing method comprises a first step of forming, by a thermal chemical vapor deposition method, a silicon nitride film on an object disposed in a reaction container, with bis tertiary butyl amino silane and NH3 flowing into the reaction container, and a second step of removing silicon... Agent: Hogan & Hartson L.L.P.

20070238293 - Filling deep features with conductors in semiconductor manufacturing: A method of filling a conductive material in a three dimensional integration structure feature formed on a surface of a wafer is disclosed. The feature is filled with a dispersion containing a plurality of conductive particles and a solvent. Then, the solvent is removed from the feature, leaving the plurality... Agent: Knobbe Martens Olson & Bear LLP

20070238294 - Method to create super secondary grain growth in narrow trenches: The present invention relates to a method for obtaining enlarged Cu grains in small trenches. More specifically it related to a method for creating enlarged copper grains or inducing super secondary grain growth in electrochemically deposited copper in narrow trenches and/or vias to be used in semiconductor devices.... Agent: Knobbe Martens Olson & Bear LLP

20070238295 - Methods of forming semiconductor constructions: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The... Agent: Wells St. John P.s.

20070238296 - Substrate with recess portion for microlens, microlens substrate, transmissive screen, rear type projector, and method of manufacturing substrate with recess portion for microlens: A microlens substrate is provided having a plurality of first microlenses and a plurality of second microlenses which are located between the plurality of first microlenses. The second microlenses are smaller than the first microlenses.... Agent: Harness, Dickey & Pierce, P.L.C

20070238297 - Method of manufacture of constant groove depth pads: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a... Agent: Whyte Hirschboeck Dudek S.c.

20070238298 - Method and system for patterning a dielectric film: A method and system for patterning a dielectric film such as a low dielectric constant (low-k) material. A dry non-plasma etching process can be implemented to transfer a pattern from a photo-lithographic layer to a hard mask layer, while minimizing the evolution of surface roughness in the sidewall of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070238299 - Simplified pitch doubling process flow: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from... Agent: Knobbe Martens Olson & Bear LLP

20070238300 - Silicon-containing film-forming composition, silicon-containing film, silicon-containing film-bearing substrate, and patterning method: A silicon-containing film is formed from a heat curable composition comprising (A) a silicon-containing compound obtained by effecting hydrolytic condensation of a hydrolyzable silicon compound in the presence of an acid catalyst, and substantially removing the acid catalyst from the reaction mixture, (B) a hydroxide or organic acid salt of... Agent: Birch Stewart Kolasch & Birch

20070238301 - Batch processing system and method for performing chemical oxide removal: A batch processing system and method for chemical oxide removal (COR) is described. The batch processing system is configured to provide chemical treatment of a plurality of substrates, wherein each substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. Furthermore,... Agent: Dla Piper US LLP

20070238302 - Sequential oxide removal using fluorine and hydrogen: A method is provided for oxide removal from a substrate. The method includes providing the substrate in a process chamber where the substrate has an oxide layer formed thereon, and performing a sequential oxide removal process. The sequential oxide removal process includes exposing the substrate at a first substrate temperature... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070238303 - Terminal block for connecting electrical conductors: The invention relates to a terminal block for connecting electrical conductors, with a first clamping spring element (20) and a second clamping spring element (30) for clamping the electrical conductors, wherein the first and second clamping spring elements (20, 30) are vertically offset from each other, and with an operating... Agent: The Nath Law Group

20070238304 - Method of etching passivation layer: A method of etching passivation layer having an anti-reflection layer and an insulating layer subsequently disposed on a pad layer of a wafer. The method includes performing an etching process to etch the anti-reflection layer and the insulating layer. The etching process has a first-step etching performed under a first... Agent: North America Intellectual Property Corporation

20070238305 - Plasma dielectric etch process including ex-situ backside polymer removal for low-dielectric constant material: A plasma etch process for etching a porous carbon-doped silicon oxide dielectric layer using a photoresist mask is carried out first in an etch reactor by performing a fluorocarbon based etch process on the workpiece to etch exposed portions of the dielectric layer while depositing protective fluorocarbon polymer on the... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20070238306 - Method of forming dual damascene semiconductor device: A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness... Agent: Duane Morris LLPIPDepartment (tsmc)

20070238307 - Processing apparatus and lid opening/closing mechanism: A processing apparatus includes an openable/closable lid disposed on a process container, and an opening/closing mechanism configured to open/close the lid. The opening/closing mechanism includes a hinge structure swingably coupling the lid to one end of the process container, and a drive structure configured to swing the lid. The hinge... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070238308 - Simplified pitch doubling process flow: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a... Agent: Knobbe Martens Olson & Bear LLP

20070238310 - Method for manufacturing a semiconductor device having a silicon oxynitride film: A semiconductor device manufacturing method includes: a process of forming an isolation trench on the surface of a semiconductor substrate; a process of forming a thermally-oxidized film on the surface of the isolation trench; a process of depositing a silicon oxynitride film on the semiconductor substrate via the thermally-oxidized film;... Agent: Sughrue Mion, PLLC

20070238309 - Method of reducing interconnect line to line capacitance by using a low k spacer: A method is described of reducing the line to line capacitance within semiconductor devices and a device demonstrating the same. The device includes a spacer layer disposed between an etch stop material and a conductive layer. Separating the etch stop layer from the conductive layers by the spacer layer may... Agent: Intel Corporation C/o Intellevate, LLC

20070238311 - Process for atomic layer deposition: The present invention relates to a deposition process for thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising at least first, second, and third gaseous materials, wherein the first and second gaseous materials are reactive with each other such that when one of the first... Agent: Paul A. Leipold Patent Legal Staff

20070238312 - Method of producing simox wafer: A SIMOX wafer is produced by implanting an oxygen ion, in which a hydrogen ion is implanted at a dose of 1015−1017/cm2 before or after the step of the oxygen ion implantation.... Agent: Sughrue Mion, PLLC

20070238313 - Method for replacing a nitrous oxide based oxidation process with a nitric oxide based oxidation process for substrate processing: A method for performing an oxidation process on a plurality of substrates in a batch processing system. According to one embodiment, the method includes selecting a N2O-based oxidation process for the substrates including a first process gas containing N2O that thermally decomposes in a process chamber of the batch processing... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070238315 - Method for forming a group iii nitride material on a silicon substrate: Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least... Agent: Knobbe Martens Olson & Bear LLP

20070238316 - Method for manufacturing a semiconductor device having a nitrogen-containing gate insulating film: A method for manufacturing a semiconductor device includes the steps of: forming a SiO2 layer on a silicon substrate; forming on the SiO2 layer an SiN film having a N/Si composition ratio smaller than the stoichiometric composition ratio of SiN by using the ALD technique; and performing a plasma-nitriding process... Agent: Sughrue Mion, PLLC

20070238314 - System and process for producing nanowire composites and electronic substrates therefrom: The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally comprises separating the nanowire-material composite... Agent: Nanosys Inc.

20070238317 - Polyhedral oligomeric silsesquioxane based imprint materials and imprint process using polyhedral oligomeric silsesquioxane based imprint materials: A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, wherein each of the one or more polymerizable group is bound to a different silicon atom of the... Agent: Schmeiser, Olsen & Watts

20070238318 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises a substrate. A polyacrylonitrile (PAN) powder is dissolved in a solvent and the solvent is heated to form a PAN solution. The PAN solution is cooled down and the PAN solution is then... Agent: Quintero Law Office, PC

20070238319 - Mechanically actuated nanotube switches: Some embodiments of the present invention include apparatuses and methods relating to nanotube switches that are mechanically actuated.... Agent: Blakely Sokoloff Taylor & Zafman

20070238320 - Devices and methods to improve carrier mobility: Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the... Agent: Schwegman, Lundberg & Woessner, P.A.

20070238321 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070231928 - Substrate processing apparatus: A substrate processing apparatus of the present invention dilutes a sample gas by mixing the sample gas with nitrogen gas and measures the concentration of IPA gas contained in the diluted sample gas in a concentration measuring part. Then, the substrate processing apparatus calculates the concentration (C0) of IPA gas... Agent: Ostrolenk Faber Gerb & Soffen

20070231929 - Processing method for wafer: A processing method for a wafer includes: preparing a wafer which has a device region having plural devices formed on a surface of the wafer; and a peripheral reinforcing portion which is integrally formed around the device region and has a projection projecting outwardly on a rear surface of the... Agent: Brinks Hofer Gilson & Lione

20070231934 - Classification apparatus for semiconductor substrate, classification method of semiconductor substrate, and manufacturing method of semiconductor device: A classification apparatus for the semiconductor substrate is provided with a bow measuring section which accepts silicon substrates and measures respective bows thereof. The classification apparatus is also provided with a bow judging section which, based on one or more standard value(s) set in advance, checks a measurement result by... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070231931 - Method for fabricating a compound-material and method for choosing a wafer: The present invention provides improved methods for fabricating compound-material wafers, in particular a silicon on insulator type wafer. The improved methods lead to reduced numbers of deflects arising on or near the periphery of the wafers. In a first method, wafers are selected in dependence on edge roll off values... Agent: Winston & Strawn LLP Patent Department

20070231933 - Using reverse arrangement for trend test in statistical process control for manufacture of semiconductor integrated circuits: A method for manufacturing semiconductor devices or other types of devices and/or entities. The method includes providing a process (e.g., etching, deposition, implantation) associated with a manufacture of a semiconductor device/The method includes collecting a plurality information (e.g., data) having a non-monotonic trend of at least one parameter associated with... Agent: Townsend And Townsend And Crew, LLP

20070231935 - Novel critical dimension (cd) control by spectrum metrology: A method for patterning a substrate includes forming a material layer on the substrate; performing a first etching on the material layer to form a pattern; measuring the pattern of the material layer using an optical spectrum metrology tool; determining whether the measuring indicates that the etching step achieved a... Agent: Haynes And Boone, LLP

20070231937 - Electronic apparatus and method of manufacturing electronic apparatus: The present invention discloses a method of manufacturing an electronic apparatus for wireless communications in that the method includes the steps of arranging an antenna apparatus adjacent to the electronic apparatus formed on a substrate and testing the electronic apparatus by conducting the wireless communications between the electronic apparatus and... Agent: Staas & Halsey LLP

20070231939 - Manufacturing method of a transparent conductive film, a manufacturing method of a transparent electrode of an organic electroluminescence device, an organic electroluminescence device and the manufacturing method: In one embodiment of a manufacturing method of a transparent conductive film of the present invention, a grid having a magnet is placed between a target and a substrate, and a pattern shaped transparent conductive film comprising the target material is formed over the substrate through a mask by a... Agent: Squire, Sanders & Dempsey L.L.P.

20070231941 - Method of manufacturing organic device element: An organic device element including a high-quality protective film is manufactured. In a step of forming a protective film on an organic device substrate on which an organic device is formed, an electroconductive rear plate provided on a rear side of the organic device substrate is divided into a peripheral... Agent: Fitzpatrick Cella Harper & Scinto

20070231944 - Electromagnetic micro-generator and method for manufacturing the same: A micro-generator includes an integrated circuit (IC) wafer. A micro-electro mechanical system (MEMS) wafer, with a movable micromechanical element, is bonded to the IC wafer. A plurality of first metal coils associated with a plurality of trenches is arranged in one of the IC wafer and the MEMS wafer. A... Agent: Edell, Shapiro & Finnan, LLC

20070231927 - Semiconductor device and manufacturing method thereof: A manufacturing method of a semiconductor device of an embodiment of the present invention includes: forming a lower electrode film for a capacitor above a substrate; forming a ferroelectric film on the lower electrode film by deposition-simultaneous crystallization; forming a dummy film on the ferroelectric film; removing the dummy film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070231930 - Dynamic metrology sampling for a dual damascene process: A method of monitoring a dual damascene procedure that includes calculating a pre-processing confidence map for a damascene process, the pre-processing confidence map including confidence data for a first set of dies on the wafer. An expanded pre-processing measurement recipe is established for the damascene process when one or more... Agent: Dla Piper US LLP

20070231932 - Method of revealing crystalline defects in a bulk substrate: This invention provides methods for predictively revealing, in bulk silicon substrates, latent crystalline defects in bulk silicon substrates that become apparent only after subsequent processing, e.g., after processing during which multiple layers are split and lifted from the bulk substrates. Preferred predictive methods include a revealing heat treatment of bulk... Agent: Winston & Strawn LLP Patent Department

20070231936 - Fabrication method of semiconductor integrated circuit device: To prevent breakage of a membrane probe during a probe test using a probe card having the membrane probe, appearance of a main surface of a wafer as a test object is tested by an appearance tester 51, and results of bad appearance such as adhesion of a foreign substance... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070231938 - Manufacturing method: A method of making an article comprises a heat cured composition with at least one foil or sheet applied on one face of the cured composition. The article may be an electrode. The composition may comprise titanium suboxide.... Agent: Caesar, Rivise, Bernstein, Cohen & Pokotilow, Ltd.

20070231940 - Composition and method of dyeing keratin fibers comprising luminescent semiconductive nanoparticles: Composition and method for dyeing keratin materials, such as hair, comprising luminescent semiconductive nanoparticles capable of emitting, under the action of a light excitation, radiation with a wavelength ranging from 400 nm to 700 nm.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070231942 - Micromechanical flow sensor with tensile coating: A sensor integrated on a semiconductor device (1), in particular a flow sensor, comprises a measuring element (2) on a membrane (5). In order to prevent a buckling of the membrane (5) a tensile coating (9) is applied. The coating covers the membrane, but it preferably leaves all the active... Agent: Donald S. Dowden Cooper & Dunham LLP

20070231943 - Protection capsule for mems devices: A method of making a MEMS device is disclosed wherein anhydrous HF exposed silicon nitride is used as a temporary adhesion layer to permit the transfer of a layer from a carrier substrate to a receiving substrate.... Agent: Marks & Clerk

20070231945 - Fabrication method of complementary metal oxide semiconductor image sensor: A fabrication method of a CMOS image sensor including a light-receiving element, at least one transistor, a first dielectric layer, a reflective layer, a second dielectric layer, a protective layer, a material layer, a transparent material layer, an optical filter, and a converging element is provided. The light-receiving element and... Agent: Jianq Chyun Intellectual Property Office

20070231946 - Laterally grown nanotubes and method of formation: A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer... Agent: Freescale Semiconductor, Inc. Law Department

20070231947 - Method of forming a film of nanoparticles interlinked with each other using a polyfunctional linker: The present invention relates to a method of forming a film of nanoparticles interlinked with each other using a polyfunctional linker.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070231948 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device, including forming a capacitor above a semiconductor substrate, the capacitor including a dielectric film containing Pb, Zr, Ti and O. Forming the capacitor includes forming a crystallized film which contains Pb, Sr, Zr, Ti, Ru and O.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070231953 - Flexible interconnect pattern on semiconductor package: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the... Agent: Blakely Sokoloff Taylor & Zafman

20070231959 - Method for making a wedge wedge wire loop:

20070231958 - Method of manufacturing a composite electronic part, and composite electronic part: A method of manufacturing a composite electronic part includes: a part arrangement step of arranging a film circuit element and a chip-like electronic part on one substrate surface of a ceramic substrate; a protective layer disposition step of disposing a protective layer that protects the film circuit element and the... Agent: Harness, Dickey & Pierce, P.L.C

20070231957 - Method of manufacturing semiconductor device: The present invention provides a method for manufacturing a semiconductor device by which the yield of bumps will be increased. First, an insulation layer, a barrier layer, and a seed layer are sequentially formed on a principal surface of a semiconductor substrate. Then, a protection layer is formed to cover... Agent: GlobalIPCounselors, LLP

20070231956 - Mold for resin molding, resin molding apparatus, and semiconductor device manufacture method: A mold includes a pot for accommodating resin, a cavity for accommodating a semiconductor chip to be resin-molded and a runner as a resin passage for transporting the resin accommodated in the pot to the cavity. A foreign matter retention pocket is disposed which is a recess formed by digging... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070231960 - Process for fabricating a semiconductor package: A process for fabricating a semiconductor package which includes using an exothermically active nanoparticle paste to join an electrode of a semiconductor die to a support body.... Agent: Ostrolenk Faber Gerb & Soffen

20070231950 - Barrier for use in 3-d integration of circuits: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening.... Agent: Freescale Semiconductor, Inc. Law Department

20070231949 - Functional blocks for assembly and method of manufacture: A functional block for assembly includes at least one element and a patterned magnetic film comprising at least one magnetic region attached to the element. A wafer includes a host substrate comprising a number of elements. The wafer further includes a patterned magnetic film attached to the elements and comprising... Agent: General Electric Company Global Research

20070231954 - Gold/silicon eutectic die bonding method: A gold/silicon eutectic die bonding method is disclosed. The method includes the steps of 1) vacuum evaporating a layer of titanium to a silicon wafer backside, the titanium layer having a thickness less than 200 Å, 2) immediately vacuum evaporating a layer of gold onto the titanium layer, the gold... Agent: Fortune Law Group LLP

20070231955 - Method for packaging flash memory cards: A packaging method for flash memory card is provided, including the steps of placing a circuit substrate in a mold, injecting thermosetting plastic material into the mold, moving to press the circuit substrate into the thermosetting plastic material for even distribution of thermosetting plastic material on the circumference and one... Agent: Lin & Associates Intellectual Property

20070231952 - Method of forming a microelectronic package using control of die and substrate differential expansions and microelectronic package formed according to the method: Method of forming a microelectronic package using control of die and substrate differential expansions. The method includes: providing a die-substrate combination including a substrate, a die disposed on the substrate, and plurality of solder paste disposed between the die and the substrate; reflowing the solder paste by exposing the die-substrate... Agent: Intel Corporation C/o Intellevate, LLC

20070231951 - Reducing layer count in semiconductor packages: An embodiment of the present invention is a technique to fabricate a package. Signals are routed in a signal layer on top of a substrate. Contacts are formed between the routed signals. The contacts are connected to a ground layer. A conductive layer is deposited, by surface mounting, on the... Agent: Blakely Sokoloff Taylor & Zafman

20070231962 - Manufacturing method of wiring substrate and manufacturing method of semiconductor device: A multilayer wiring structural body 13 is formed on a surface 57A of a metal plate 57 used as a support plate in the case of forming the multilayer wiring structural body 13, and the metal plate 57 is patterned and a slot antenna 60 is formed.... Agent: Drinker Biddle & Reath (dc)

20070231961 - Semiconductor device manufacturing method: To provide a low-cost, efficient semiconductor device manufacturing method for connecting electrodes of a pair of bases (e.g., a pair of a semiconductor chip and a circuit board, or a pair of semiconductor chips) together in a short time. The method of the present invention includes: forming magnetic bumps 34... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070231963 - Method for handling a semiconductor wafer assembly: Systems and methods for fabricating a light emitting diode include forming a multilayer epitaxial structure above a carrier substrate; depositing at least one metal layer above the multilayer epitaxial structure; removing the carrier substrate.... Agent: Patterson & Sheridan, L.L.P.

20070231964 - Methods of forming semiconductor assemblies: Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the... Agent: Trask Britt, P.C./ Micron Technology

20070231965 - Capillary underfill of stacked wafers: A plurality of wafers are aligned and stacked on a thermally variable rotary table, the table and stack are rotated, and an underfill material is disposed and cured between wafers in the stack, bonding the wafers. Corresponding wafer portions of the plurality of wafers in the stack may be singulated... Agent: Intel Corporation C/o Intellevate, LLC

20070231966 - Semiconductor device fabricating method: To improve the fabrication yield of semiconductor devices. A semiconductor device where a desired number of semiconductor chips are laminated in the thickness direction thereof is fabricated by repeating, an arbitrary number of times such as one time or two or more times, a step of bonding and mounting another... Agent: Volentine & Whitt PLLC

20070231967 - Coated thermal interface in integrated circuit die: Some embodiments of the invention include a coated thermal interface to bond a die with a heat spreader. The coated thermal interface may be used to bond the die with the heat spreader without flux. Other embodiments are described and claimed.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070231968 - Method for producing an electronic circuit: The invention relates to a method for producing an electronic circuit. According to said method, two semiconductor chips (46) with essentially the same structure are mounted on a surface (13) pertaining to a first conductor carrier (10) and coated with strip conductors (16). Said two semiconductor chips (46) comprise a... Agent: Michael J. Striker

20070231969 - Covered devices in a semicoductor package: An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length... Agent: Blakely Sokoloff Taylor & Zafman

20070231970 - Cured mold compound spacer for stacked-die package: An embodiment of the present invention is a technique to fabricate a package. A lower die is attached to a substrate. A stacked-die assembly having a spacer made of a cured mold compound is formed between the lower die and an upper die. The stacked-die assembly is encapsulated using the... Agent: Blakely Sokoloff Taylor & Zafman

20070231971 - Methods of packaging using fluid resin: The present invention teaches fluid resin dispensing and packaging methods by which to package a bare object, such as a semiconductor chip, directly and neatly on a substrate. A peripheral boundary is lined out by solder mask on the substrate surface to be packaged so as to form a barrier... Agent: Matthias Scholl

20070231972 - Manufacture of programmable crossbar signal processor: A process including a first step of providing a semiconductor wafer doped of a first conductivity type on a first side and doped of a second conductivity type, opposite to the first conductivity type on the second side, a second step of forming a first array of parallel wires having... Agent: Blaise Mouttet

20070231973 - Reverse conducting igbt with vertical carrier lifetime adjustment: A reverse conducting insulated gate bipolar transistor (IGBT) includes a semiconductor substrate having a front side and a back side and a first conductivity region between the front and back sides. The first conductivity region includes a reduced lifetime zone, a first lifetime zone between the reduced lifetime zone and... Agent: Davidson, Davidson & Kappel, LLC

20070231974 - Thin film transistor having copper line and fabricating method thereof: A thin film transistor having a substrate, a bottom layer, a gate, a gate-insulating layer, a channel layer and a source/drain, is provided. The bottom layer is disposed on the substrate. The copper gate is disposed on the bottom layer. The gate-insulating layer covers the copper gate and the bottom... Agent: Jianq Chyun Intellectual Property Office

20070231976 - Method for fabricating a semiconductor device: A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a... Agent: Volentine & Whitt PLLC

20070231975 - Reflow method, pattern generating method, and fabrication method for tft for lcd: A to-be-processed object including an underlying layer and a resist film giving a pattern allowing formation of an exposure region in which the underlying layer is exposed at an upper layer to the underlying layer and a coverage region in which the underlying layer is covered is prepared. A reflow... Agent: Smith, Gambrell & Russell

20070231977 - Method of fabricating thin film transistor: A method of fabricating a thin film transistor includes forming an active layer on an insulating substrate; forming a gate insulation film on the insulating substrate; forming source, drain, and body contact regions which are separated by a channel region in the active layer; forming a gate on the gate... Agent: Stein, Mcewen & Bui, LLP

20070231978 - Nitride semiconductor device and manufacturing method thereof: A nitride semiconductor device and its manufacturing method are provided which are capable of achieving low-resistance ohmic properties and high adhesion. A nitride semiconductor device has an n-type GaN substrate over which a semiconductor element is formed and an n-electrode as a metal electrode formed over the back surface of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070231979 - Silicon device on si: c-oi and sgoi and method of manufacture: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal... Agent: Greenblum & Bernstein, P.L.C

20070231980 - Etched nanofin transistors: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin is formed from a crystalline substrate. A first source/drain region is formed in the substrate beneath the fin. A surrounding gate insulator is formed around the fin. A surrounding... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070231981 - Patterning a plurality of fields on a substrate to compensate for differing evaporation times: A method of patterning a substrate comprising a plurality of fields, including, inter alia, positioning a first volume of fluid on a first subset of the plurality of fields of the substrate, with the first volume of fluid being subjected to a first evaporation time; positioning a second volume of... Agent: Molecular Imprints

20070231982 - Thin film transistor substrate and manufacturing method thereof: A thin film transistor (TFT) substrate includes a glass substrate, a thin film transistor, an electrode pad, and a conductive bump. The TFT and the electrode pad are formed on the glass substrate, and the electrode pad is used for electrically connecting with the thin film transistor. The conductive bump... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070231986 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device is disclosed. A first oxide layer, a nitride layer, a second oxide layer, and a first polysilicon layer, which is a part of a polysilicon layer for a control gate, are formed to a predetermined thickness on a semiconductor substrate. A first... Agent: Townsend And Townsend And Crew, LLP

20070231983 - Epitaxial silicon germanium for reduced contact resistance in field-effect transistors: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.... Agent: Blakely Sokoloff Taylor & Zafman

20070231987 - Fin device with capacitor integrated under gate electrode: A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070231985 - Grown nanofin transistors: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallize the amorphous semiconductor material using the crystalline substrate... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070231984 - Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors: A method for fabricating a three-dimensional transistor is described. Atomic Layer Deposition of nickel, in one embodiment, is used to form a uniform silicide on all epitaxially grown source and drain regions, including those facing downwardly.... Agent: Blakely Sokoloff Taylor & Zafman

20070231988 - Method of fabricating nanowire memory device and system of controlling nanowire formation used in the same: A method of fabricating a nanowire memory device, and a system of controlling nanowire formation used in the same method are provided. In the method of fabricating a nanowire memory device which includes a substrate; an electrode formed on the substrate and insulated from the substrate; and a nanowire having... Agent: Sughrue Mion, PLLC

20070231989 - Methods of fabricating nonvolatile memory devices: A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in... Agent: Myers Bigel Sibley & Sajovec

20070231990 - Cmos (complementary metal oxide semiconductor) technology: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material... Agent: Schmeiser, Olsen & Watts

20070231991 - Semiconductor memory device and method of operating a semiconductor memory device: A semiconductor memory device includes a channel region, a gate electrode adjacent the channel region, and a charge-trapping layer between the channel region and the gate electrode. A voltage is applied between the gate electrode and the channel region to cause a first current of a first kind of charge... Agent: Slater & Matsil LLP

20070231992 - Method of removing residue from a substrate: A method of using a post-etch treatment system for removing photoresist and etch residue formed during an etching process is described. For example, the etch residue can include halogen containing material. The post-etch treatment system comprises a vacuum chamber, a radical generation system coupled to the vacuum chamber, a radical... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070231993 - Damascene interconnection having porous low k layer with a hard mask reduced in thickness: A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening. The capping layer and the dielectric layer... Agent: Mayer & Williams PC

20070231994 - Semiconductor device and fabrication method therefor: A semiconductor device has an interlayer insulating film formed on a substrate and a plurality of capacitors formed in directions of columns on the interlayer insulating film. Each of the capacitors has a lower electrode, a capacitor insulating film, and an upper electrode which are successively stacked in layers in... Agent: Mcdermott Will & Emery LLP

20070231995 - Terraced film stack: A process directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.... Agent: Dinsmore & Shohl LLP

20070231996 - Plasma display panel: A plasma display panel includes front and rear substrates parallel to one another, a plurality of discharge electrode pairs on the front substrate, a plurality of discharge cells between the front and rear substrates, a front dielectric layer having a plurality of grooves on the discharge electrode pairs, and a... Agent: Lee & Morse, P.C.

20070231998 - Method for preparing a capacitor structure of a semiconductor memory: A method for preparing a capacitor structure comprises forming an opening in a dielectric structure, and forming a cylindrical capacitor including a first conductive layer on the sidewall of the opening, a first dielectric layer on the surface of the first conductive layer, and a second conductive layer on the... Agent: Oliff & Berridge, PLC

20070231997 - Stacked multi-gate transistor design and method of fabrication: A multi-body thickness (MBT) field effect transistor (FET) comprises a silicon body formed on a substrate. The silicon body may comprise a wide section and a narrow section between the wide section and the substrate. The silicon body may comprise more than one pair of a wide section and a... Agent: Blakely Sokoloff Taylor & Zafman

20070232000 - Fabricating method of a non-volatile memory: A method of fabricating a non-volatile memory is provided. A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top... Agent: J C Patents, Inc.

20070231999 - High performance transistor with a highly stressed channel: A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice... Agent: Slater & Matsil, L.L.P.

20070232001 - Method for fabricating high voltage semiconductor device: A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising: forming a mask pattern on the semiconductor substrate; forming a first low-density impurity implanted region on... Agent: Rabin & Berdo, PC

20070232003 - Planar dual gate semiconductor device: A method of fabricating a dual-gate semiconductor device is provided in which wsilicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070232002 - Static random access memory using independent double gate transistors: A static random access memory may use independent double gate transistors to form the pull up transistors. The other transistors of the memory are not formed of independent double gate transistors. In some embodiments, a reduced layout size may be achieved. In addition, in some embodiments, it is not necessary... Agent: Trop Pruner & Hu, PC

20070232004 - Semiconductor device and manufacturing method thereof: A semiconductor device capable of suppressing a threshold shift and a manufacturing method of the semiconductor device. On a high dielectric constant insulating film, a diffusion barrier film for preventing the diffusion of metal elements from the high dielectric constant insulating film to an upper layer is formed. Therefore, the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232005 - Semiconductor device and manufacturing method thereof: A semiconductor device is provided, which comprises a semiconductor film, a gate insulating film, a gate electrode, an insulating film, and a source and drain electrodes. The semiconductor film includes at least a channel forming region, a region, a source and drain regions disposed between the channel forming region and... Agent: Fish & Richardson P.C.

20070232006 - Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process: By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis... Agent: Williams, Morgan & Amerson

20070232007 - Nanowire transistor with surrounding gate: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070232008 - Semiconductor device and hetero-junction bipolar transistor: In an npn-type HBT, each of an emitter layer and a collector layer is formed of AlGaN and a base layer is formed of GaN. The emitter layer is in contact with a nitrogen polarity surface of the base layer and the collector layer is in contact with a gallium... Agent: Mcdermott Will & Emery LLP

20070232009 - System and method for wafer handling in semiconductor process tools: By providing an additional detector system for detecting the actual substrate position during transfer from and to a load lock station, the reliability of the corresponding process tool may be significantly enhanced. For example, an invalid position of the substrate during transfer from and to the load lock station may... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070232010 - Method for fabricating a junction varactor with high q factor: A junction varactor includes a gate finger lying across an ion well of a semiconductor substrate; a gate dielectric situated between the gate finger and the ion well; a first ion diffusion region with first conductivity type located in the ion well at one side of the gate finger, the... Agent: North America Intellectual Property Corporation

20070232012 - Solid electrolytic capacitor: In a solid electrolytic capacitor provided with an anode, a cathode, and a dielectric layer formed by anodization of the anode, the anode includes a first metal layer and a second metal layer. The first metal layer is made of any of metal selected from niobium, aluminum and tantalum, or... Agent: Ndq&m Watchstone LLP

20070232011 - Method of forming an active semiconductor device over a passive device and semiconductor component thereof: A method of forming a semiconductor component (100) having an active semiconductor device (680) above a passive device (470) includes providing a semiconductor wafer (110) having an upper surface (115), forming a trench (216) in the upper surface of the semiconductor wafer, forming a cavity (317) in the semiconductor wafer... Agent: George C. Chen Bryan Cave LLP

20070232013 - Methods of forming semiconductor constructions: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some... Agent: Wells St. John P.s.

20070232014 - Method of fabricating a planar mim capacitor: A method of fabricating a Metal-Insulator-Metal (MIM) capacitor is presented. The method includes depositing a bottom plate of the MIM capacitor on a passivating dielectric layer which may be a pre-metal or post metal dielectric layer. A capacitor dielectric of the MIM capacitor is subsequently deposited on top of the... Agent: Honeywell International Inc.

20070232016 - Semiconductor device and manufacturing method of the same: After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232017 - Thin film capacitor and fabrication method thereof: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232015 - Contact for memory cell: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.... Agent: Dickstein Shapiro LLP

20070232018 - Method for manufacturing compound semiconductor substrated with pn junction: A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the... Agent: Birch Stewart Kolasch & Birch

20070232019 - Method for forming isolation structure in nonvolatile memory device: A method for forming an isolation structure in a nonvolatile memory device includes forming a gate insulation layer, a gate conductive layer, and a hard mask over a substrate, etching the hard mask, the gate conductive layer, the gate insulation layer, and a portion of the substrate to form a... Agent: Blakely Sokoloff Taylor & Zafman

20070232020 - Hybrid-orientation technology buried n-well design: A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes... Agent: Scully, Scott, Murphy & Presser, P.C.

20070232021 - Method for forming isolation layer in semiconductor device: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, forming a first liner nitride layer on an exposed surface of the trench, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills... Agent: Marshall, Gerstein & Borun LLP

20070232022 - Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species: A method for fabricating bonded substrate structures, e.g., silicon on silicon. In a specific embodiment, the method includes providing a thickness of single crystal silicon material transferred from a first silicon substrate coupled to a second silicon substrate. In a specific embodiment, the second silicon substrate has a second surface... Agent: Townsend And Townsend And Crew, LLP

20070232023 - Room temperature metal direct bonding: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070232025 - Process for the transfer of a thin film: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form... Agent: Brinks Hofer Gilson & Lione

20070232024 - Singulating surface-mountable semiconductor devices and fitting external contacts to said devices: Methods for singulating surface-mountable semiconductor devices and for fitting external contact areas to the devices are described herein. Semiconductor device components are applied to a metallic carrier in rows and columns in corresponding semiconductor device positions of the metallic carrier. Thereafter, a plurality of components, situated in the device positions,... Agent: Edell, Shapiro & Finnan, LLC

20070232027 - Lead cutter and method of fabricating semiconductor device: Aimed at stably forming sheared surfaces of leads of semiconductor devices, and at raising ratio of formation of plated layers onto the sheared surfaces of the leads, a lead cutter has a die 106, and a cutting punch 110 having a cutting edge at least on the surface facing the... Agent: Young & Thompson

20070232026 - Methods and materials useful for chip stacking, chip and wafer bonding: Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.... Agent: The Webb Law Firm, P.C.

20070232030 - Semiconductor-wafer processing method using fluid-like layer: In a method for processing a semiconductor wafer, having a plurality of solder bumps bonded on a front surface thereof, a fluid-like layer is formed on the front surface of the semiconductor wafer. A holder sheet is prepared, and has a support layer, and an adhesive layer formed on a... Agent: Young & Thompson

20070232028 - Method of manufacturing silicon nanowires using porous glass template and device comprising silicon nanowires formed by the same: A method of manufacturing silicon nanowires is characterized in that silicon nanowires are formed and grown through a solid-liquid-solid process or a vapor-liquid-solid process using a porous glass template having nanopores doped with erbium or an erbium precursor. In addition, a device including silicon nanowires formed using the above exemplary... Agent: Cantor Colburn, LLP

20070232029 - Method of three-dimensional microfabrication and high-density three-dimensional fine structure: Surface of a thin film formed on a surface of substrate of AlxGayIn1-x-yAszP1-z (0≦x<1, 0≦y and z≦1) including substances GaAs and InP is irradiated with electron beams controlled at any arbitrary electron beam diameter and current density so as to cause any natural oxide film formed on GaAs surface to... Agent: Young & Thompson

20070232031 - Uv assisted low temperature epitaxial growth of silicon-containing films: A method of preparing a clean substrate surface for blanket or selective epitaxial deposition of silicon-containing and/or germanium-containing films. In addition, a method of growing the silicon-containing and/or germanium-containing films, where both the substrate cleaning method and the film growth method are carried out at a temperature below 750° C.,... Agent: Shirley L. Church, Esq.

20070232032 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device whereby, even in cases where ions are implanted into a shallow region of a semiconductor substrate when a deep well is formed, the influence of the ions on a MOSFET can be removed, thereby eliminating the need for increasing the chip area. A... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232033 - Method for forming ultra-shallow high quality junctions by a combination of solid phase epitaxy and laser annealing: By using a combination of solid phase epitaxy re-growth and laser annealing, the present invention provides a low thermal budget method which allows the crystal lattice of a semiconductor surface to recover after the doping by ion implantation. The low thermal budget limits the out-diffusion of the dopants ions, thus... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070232034 - Method for manufacturing semiconductor device:

20070232035 - Electronic device: A technique for high-resolution surface energy assisted patterning of semiconductor active layer islands on top of an array of predefined source-drain electrodes without requiring an additional process step for surface energy patterning.... Agent: Sughrue Mion, PLLC

20070232036 - Method of producing product including silicon wires: Provided is a product including a group of a plurality of wires, in which longitudinal directions of the wires are arranged in one direction, and a method of producing the same. The longitudinal directions of a plurality of wires each covered with a polymer are arranged in one direction in... Agent: Morgan & Finnegan, L.L.P.

20070232037 - High capacitance low resistance electrode: Methods are provided for manufacturing an electrode. In one exemplary embodiment, the method includes the steps of contacting the silver layer with vanadium oxide, and heating the silver layer and vanadium oxide in an oxygen-containing atmosphere to form a silver vanadium oxide layer chemically bonded to the metal substrate.... Agent: Medtronic, Inc.

20070232038 - Method of manufacturing plasma display panel and photomask to be used in the method: Provided is a method of manufacturing a plasma display panel and a photomask to be used for manufacturing the plasma display panel. The method includes forming a conductive layer and a photoresist layer covering the conductive layer on a first substrate using a green sheet method, exposing and developing the... Agent: Knobbe Martens Olson & Bear LLP

20070232039 - Semiconductor device having shallow b-doped region and its manufacture: A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232040 - Method for reducing carbon monoxide poisoning in a thin film deposition system: A method for introducing a precursor vapor to a process chamber configured for forming a thin film on a substrate is described. The method includes transporting a process gas containing metal precursor vapor and a CO delivery gas to a process chamber, and introducing a CO saturation gas to the... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070232041 - Integrated circuit device gate structures having charge storing nano crystals in a metal oxide dielectric layer and methods of forming the same: Methods of forming a gate structure for an integrated circuit memory device include forming a metal oxide dielectric layer on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s)... Agent: Robert W. Glatz Myers Bigel Sibley & Sajovec, P.A.

20070232042 - Method for fabricating semiconductor device having bulb-shaped recess gate: A method for fabricating a semiconductor device includes etching a portion of a substrate to form a recess. A polymer layer fills a lower portion of the recess. Sidewall spacers are formed over the recess above the lower portion of the recess. The polymer layer is removed. The lower portion... Agent: Townsend And Townsend And Crew, LLP

20070232043 - Method for forming thermal stable silicide using surface plasma treatment: A method for forming a silicide layer on a substrate. A substrate with a silicon surface is provided. Nitrogen is incorporated into the silicon surface by a plasma treatment, to form a nitridized silicon surface. A metal layer is formed on the nitridized silicon surface. The substrate having the metal... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070232045 - Damage assessment of a wafer using optical metrology: A method of assessing damage of a dual damascene structure includes obtaining a wafer after the wafer has been processed using a dual damascene process. A first damage-assessment procedure is performed on the wafer using an optical metrology process to gather damage-assessment data for a first set of measurements sites... Agent: Morrison & Foerster LLP

20070232047 - Damage recovery method for low k layer in a damascene interconnection: A method of fabricating a damascene interconnection is provided. The method begins by forming on a substrate a low k dielectric layer and a resist pattern over the low k dielectric layer to define a first interconnect opening. The low k dielectric layer is etched through the resist pattern to... Agent: Mayer & Williams PC

20070232048 - Damascene interconnection having a sicoh low k layer: A method and apparatus is provided for fabricating a damascene interconnection. The method begins by forming on a substrate an organosilicate dielectric layer, a capping layer on the organosilicate dielectric layer, and a resist pattern over the capping layer to define a first interconnect opening. The capping layer is etched... Agent: Mayer & Williams PC

20070232046 - Damascene interconnection having porous low k layer with improved mechanical properties: A method is provided for fabricating a damascene interconnection. The method begins by forming on a substrate a porous dielectric layer and imparting a porogen material into an upper portion of the porous dielectric layer to define a less porous dielectric sublayer within the dielectric layer. A capping layer is... Agent: Mayer & Williams PC

20070232044 - Filling narrow and high aspect ratio openings with electroless deposition: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. A dual-function barrier layer is formed within the opening. The... Agent: Blakely Sokoloff Taylor & Zafman

20070232051 - Method for forming metal bumps: A method for forming metal bumps is disclosed, comprising: providing a substrate including a plurality of pads; forming a solder mask on the substrate, wherein the solder mask has first openings to expose the pads; forming a photoresist layer on the solder mask, wherein the photoresist layer has second openings... Agent: Rabin & Berdo, PC

20070232052 - Method for forming passivation layer: A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter, a first passivation layer is formed... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070232050 - Embedding device in substrate cavity: An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the... Agent: Blakely Sokoloff Taylor & Zafman

20070232049 - Method and structure for eliminating aluminum terminal pad material in semiconductor devices: A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so... Agent: Cantor Colburn LLP - IBM Fishkill

20070232053 - Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging: A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical... Agent: Megica Corporation

20070232054 - Semiconductor device and manufacturing method thereof: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led... Agent: Nixon & Vanderhye, PC

20070232055 - Methods and apparatuses for applying a protective material to an interconnect associated with a component: Methods and apparatuses for applying a protective material to an interconnect associated with a component. One such method involves placing a stencil in close proximity to an interconnect that extends over a cavity. An amount of protective material is placed on the stencil. A wiper is passed across the stencil.... Agent: Lexmark International, Inc. Intellectual Property Law Department

20070232056 - Semiconductor device and method for manufacturing the same: It is an object of the present invention to provide a semiconductor device with high performance and reliability, in which peeling off of interconnection layers or conductive layers due to thermal stress developed during packaging of a semiconductor substrate is suppressed, and thus electrical break down is prevented and an... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232058 - Composition for forming insulating film and method for fabricating semiconductor device: The method for fabricating a semiconductor device comprises the step of forming a first insulating film 38 of a porous material over a substrate 10; the step of forming on the first insulating film 38 a second insulating film 40 containing a silicon compound containing Si—CH3 bonds by 30-90%, and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232057 - Method for forming thin film photovoltaic interconnects using self-aligned process: Processing steps that are useful for forming interconnects in a photovoltaic module are described herein. According to one aspect, a method according to the invention includes processing steps that are similar to those performed in conventional integrated circuit fabrication. For example, the method can include etches to form a conductive... Agent: Applied Materials, Inc.

20070232059 - Multilayer interconnection substrate and method of manufacturing the same: A multilayer interconnection substrate is disclosed that includes a multilayer interconnection layer having at least a first interconnection layer and a second interconnection layer stacked with an insulating layer provided therebetween, and a connection via configured to electrically connect the first interconnection layer and the second interconnection layer. The connection... Agent: Kratz, Quintos & Hanson, LLP

20070232060 - Hybrid ionized physical vapor deposition of via and trench liners: A hybrid ionized physical vapor deposition technique to form liner films for vias, trenches, and other structures of integrated circuits. The techniques involves depositing liner materials within a via, hole, trench, or other structure in a neutral state, using, for example, physical vapor deposition. The liner materials deposited in this... Agent: Stmicroelectronics, Inc.

20070232061 - Semiconductor device having adhesion increasing film to prevent peeling: A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is provided on the one side of the base member around the... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070232062 - Damascene interconnection having porous low k layer followed by a nonporous low k layer: A method is provided for fabricating a damascene interconnection. The method begins by forming on a substrate a porous low k dielectric layer and forming a resist pattern over the low k dielectric layer to define a first interconnect opening. The porous low k dielectric layer is etched through the... Agent: Mayer & Williams PC

20070232063 - Method for reducing polish-induced damage in a contact structure by forming a capping layer: By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming conductive surface irregularities during the further processing. Consequently, yield loss effects caused by leakage paths or short circuits in... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070232064 - Method of manufacturing a semiconductor element: A method of manufacturing a semiconductor element, includes forming a lower metal wiring layer and an interlayer insulating film on a substrate, forming an opening through the interlayer insulating film, such that the opening is in communication with an upper surface of the lower metal wiring layer, cleaning the opening,... Agent: Lee & Morse, P.C.

20070232065 - Composition control for photovoltaic thin film manufacturing: The present invention relates to methods and apparatus for providing composition control to thin compound semiconductor films for radiation detector and photovoltaic applications. In one aspect of the invention, there is provided a method in which the molar ratio of the elements in a plurality of layers are detected so... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070232066 - Method and device for the plasma treatment of surfaces containing alkali and alkaline-earth metals: The invention relates to a method for the plasma treatment of glass surfaces, the metal component, in particular the alkali and/or alkaline-earth metal component in the superficial region of the substrate being reduced by a plasma treatment of a substrate.... Agent: Demont & Breyer, LLC

20070232067 - Semiconductor fabrication method and etching system: The invention provides a semiconductor fabrication method comprising a deposition step for depositing a laminated film on a semiconductor substrate having a region in which a mask pattern is formed sparsely and a region in which the mask pattern is formed densely, a lithography step s1 for forming a mask... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070232068 - Slurry for touch-up cmp and method of manufacturing semiconductor device: A slurry for touch-up CMP is provided, which includes water, colloidal silica having an average primary particle diameter of 5 to 60 nm, unsintered cerium oxide having an average primary particle diameter of 5 to 60 nm, a multivalent organic acid containing no nitrogen atoms, and a nitrogen-containing heterocyclic compound.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070232069 - Chemical mechanical polishing apparatus: A CMP apparatus therefor is provided. First, a substrate including a semiconductor structure, a liner layer over the semiconductor structure and a metal layer over the liner layer is provided. Next, a metal polishing step is performed to polish the metal layer until a portion of the liner layer is... Agent: Jianq Chyun Intellectual Property Office

20070232071 - Method to improve the step coverage and pattern loading for dielectric films: Methods of controlling the step coverage and pattern loading of a layer on a substrate are provided. The dielectric layer may be a silicon nitride, silicon oxide, or silicon oxynitride layer. The method comprises depositing a dielectric layer on a substrate having at least one formed feature across a surface... Agent: Patterson & Sheridan, LLP

20070232070 - Method and device for depositing a protective layer during an etching procedure: A device and method for depositing a protective layer on a material during a plasma etching procedure in the course of fabricating semiconductor components, in particular in the course of fabricating DRAM chips, characterized in that the plasma has at least one precursor which, during the plasma etching procedure, together... Agent: Slater & Matsil LLP

20070232072 - Formation of protection layer on wafer to prevent stain formation: Embodiments of the invention generally provide an apparatus and a method for cleaning the bevel edge of a semiconductor substrate, while simultaneously providing a protection layer over the production surface of the substrate. The method for forming the protection layer generally includes rotating the semiconductor substrate on a substrate support... Agent: Patterson & Sheridan, LLP

20070232073 - Cleaning apparatus of semiconductor substrate and method of manufacturing semiconductor device: After a liquid chemical treatment is finished, in parallel with a washing away treatment and/or a drying treatment, by spraying from a nozzle for a cleaning liquid supplied by a cleaning line to an outer surface of a nozzle for a liquid chemical, crystals and the like of components of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232075 - Roughness reducing film at interface, materials for forming roughness reducing film at interface, wiring layer and semiconductor device using the same, and method for manufacturing semiconductor device: Techniques for obtaining a wiring layer with a high TDDB resistance and little leakage current, and accordingly, for manufacturing a highly reliable semiconductor device with a small electric power consumption are provided, in which an interfacial roughness reducing film is formed which is in contact with an insulator film and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232076 - Method of repairing damaged film having low dielectric constant, semiconductor device fabricating system and storage medium: A damaged layer repairing method repairs a damaged layer formed in a surface of a SiOCH film having a low dielectric constant film, containing silicon, carbon, oxygen and hydrogen and formed on a substrate through the elimination of carbon atoms by the decarbonizing effect of plasmas used in an etching... Agent: Smith, Gambrell & Russell Suite 800

20070232074 - Techniques for the synthesis of dense, high-quality diamond films using a dual seeding approach: Embodiments of methods of forming a high thermal conductivity diamond film on a substrate using at least two different average particle sizes of diamond for nucleation and its associated structures.... Agent: Blakely Sokoloff Taylor & Zafman

20070232077 - Method for manufacturing semiconductor device: To provide a method for manufacturing a semiconductor device, which the method is capable of efficient mass production of high-performance semiconductor devices by, upon manufacture of a semiconductor device, eliminating unwanted features (e.g., side lobes) created together with a resist pattern by thickening the resist pattern, to reduce the burden... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070232078 - In situ processing for ultra-thin gate oxide scaling: A method including depositing a material for a gate electrode on a substrate over a dielectric material, the gate electrode material comprising a metal; depositing a capping material over the gate electrode material under processing conditions that will not promote any oxygen species associated with the gate electrode material to... Agent: Blakely Sokoloff Taylor & Zafman

20070232080 - Reflow method, pattern generating method, and fabrication method for tft for lcd: A reflow method includes preparing a to-be-processed object, which includes a first layer, a second layer formed in an upper layer to the first layer, and a resist film, which is directly on the second layer and has a pattern allowing formation of an exposure region in which the first... Agent: Smith, Gambrell & Russell

20070232079 - Semiconductor device made by multiple anneal of stress inducing layer: The invention provides a method of fabricating a semiconductor device. In one aspect, the method comprises forming a stress inducing layer over a semiconductor substrate, subjecting the stress inducing layer to a first temperature anneal, and subjecting the semiconductor substrate to a second temperature anneal subsequent to the first temperature... Agent: Texas Instruments Incorporated

20070232081 - Method for forming tetragonal zirconium oxide layer and method for fabricating capacitor having the same: A method for forming a zirconium oxide (ZrO2) layer on a substrate in a chamber includes controlling a temperature of the substrate; and repeating a unit cycle of an atomic layer deposition (ALD) method. The unit cycle includes supplying a zirconium (Zr) source into a chamber, parts of the Zr... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070232082 - Method to improve the step coverage and pattern loading for dielectric films: A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer... Agent: Patterson & Sheridan, LLP

20070232083 - Apparatus and method for manufacturing semiconductor devices: An apparatus for manufacturing a semiconductor device includes a treatment chamber in which a working substrate is disposed; a plurality of lamps provided above the treatment chamber; and a reflector provided behind the lamps relative to a direction towards the working substrate, spatially controlling an in-plane distribution of reflection rate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070232084 - Manufacturing method for semiconductor device: A manufacturing method for a semiconductor device according to the present invention includes the steps of: growing a p-type contact layer formed of a p-type GaN layer; forming an insulating film on a surface of the p-type contact layer, on which a p-side electrode is to be formed, by coating... Agent: Mcdermott Will & Emery LLP

20070232085 - Method and apparatus for plasma processing: The invention provides a plasma processing apparatus capable of minimizing the non-uniformity of potential distribution around wafer circumference, and providing a uniform process across the wafer surface. The apparatus is equipped with a focus ring formed of a dielectric, a conductor or a semiconductor and having RF applied thereto, the... Agent: Antonelli, Terry, Stout & Kraus, LLP