Semiconductor device manufacturing: process inventions 09/07

20070224706 - Method of producing semiconductor device and semiconductor device: In the production of a semiconductor device in which a ferroelectric capacitor is used as a memory, a method of producing the semiconductor device in which the oxidation of a tungsten film embedded in an alignment mark prepared in the form of a groove is prevented includes forming an oxidation-preventing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070224709 - Plasma processing method and apparatus, control program and storage medium: A plasma processing method for performing a plasma process by employing a plasma processing apparatus including a processing chamber for performing the plasma process on a target object, a mounting table for mounting thereon the target object in the processing chamber, a peripheral member disposed around a periphery of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224715 - Nitride semiconductor based light-emitting device and manufacturing method thereof: p

20070224720 - Manufacturing method of suspended microstructure: A manufacturing method of a suspended microstructure includes the steps of providing a substrate having a surface; forming a first depositing layer over a part of the surface; forming a second depositing layer over the first depositing layer and another part of the surface wherein an adhesion between the first... Agent: Birch Stewart Kolasch & Birch

20070224707 - Magnetic random access memory, magnetic random access memory manufacturing method, and magnetic random access memory write method: A magnetic random access memory includes first and second write wirings, the second write wiring having first and second crossing angles formed by crossing the first write wiring, a first magnetoresistive element having a first axis of easy magnetization directed to a side of the first crossing angle and having... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224708 - Mass pulse sensor and process-gas system and method: An improved valve device, a valved process-gas apparatus, and a method for confirming operations in a gas-process system are disclosed. The valve device includes an electronically controlled valve designed to cycle between closed and open conditions, with closed-to-open and open-to-closed response times less than about 250 ms, to control the... Agent: Perkins Coie LLP

20070224710 - Methods to shape the electric field in electron devices, passivate dislocations and point defects, and enhance the luminescence efficiency of optical devices: A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This... Agent: Gates & Cooper LLP Howard Hughes Center

20070224711 - Doping apparatus, doping method, and method for fabricating thin film transistor: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In... Agent: Nixon Peabody, LLP

20070224712 - Method of monitoring a semiconductor processing system using a wireless sensor network: A method and system for non-invasive sensing and monitoring of a processing system employed in semiconductor manufacturing. The method allows for detecting and diagnosing drift and failures in the processing system and taking the appropriate correcting measures. The method includes positioning at least one non-invasive sensor on an outer surface... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070224714 - Method of fabricating light emitting device and thus-fabricated light emitting device: A light emitting device chip is obtained by dicing a light emitting device wafer having a light emitting layer section 24 based on a double heterostructure in which a first-conductivity-type cladding layer 6, an active layer 5 and an second-conductivity-type cladding layer 4, each of which being composed of a... Agent: Snider & Associates

20070224713 - Method of manufacturing display device using led chips: A method for manufacturing a display device using light emitting diode chips contemplates manufacturing a plurality of light emitting diode (LED) chips using a porous template; forming a plurality of first electrodes on a substrate; attaching the LED chips to pixel sites on the first electrodes using fluidic self assembly... Agent: Robert E. Bushnell

20070224716 - Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension: Semiconductor light emitting devices are fabricated by placing a suspension including phosphor particles suspended in solvent on at least a portion of a light emitting surface of a semiconductor light emitting element, and evaporating at least some of the solvent to cause the phosphor particles to deposit on at least... Agent: Koppel, Patrick & Heybl

20070224717 - Apparatus and method for manufacturing a display device substrate: An apparatus and method for manufacturing a display device substrate are provided. In one embodiment, the apparatus comprises a clamp for clamping an edge of a plastic substrate, and a tension member applying tension along a surface of the plastic substrate by interacting with the clamp to strain the plastic... Agent: Macpherson Kwok Chen & Heid LLP

20070224718 - Mems fabrication method: A method for singulating a substrate such as a semiconductor wafer populated with a plurality of MEMS devices. A preferred embodiment of the present invention comprises mounting a glass cover onto the wafer, then orienting the wafer and removably mounting it on an adhesive tape. A partial cut or series... Agent: Texas Instruments Incorporated

20070224719 - Method of manufacturing mems device package: A micro electromechanical system (MEMS) device package and a method of manufacturing the same are provided. The MEMS device package includes: a device substrate with a MEMS active device being formed on the top surface thereof; internal electrode pads, each of which is positioned on the opposite side of the... Agent: Sughrue Mion, PLLC

20070224721 - Interband cascade detectors: A device for detecting radiation, typically in the infrared. Photons are absorbed in an active region of a semiconductor device such that the absorption induces an interband electronic transition and generates photo-excited charge carriers. The charge carriers are coupled into a carrier transport region having multiple quantum wells and characterized... Agent: Bromberg & Sunstein LLP

20070224722 - Indium features on multi-contact chips: A device comprising a pixilated semiconductor detector or VLSI chip having plurality of individual indium bumps arrayed on a surface of the detector, wherein the indium bumps are in electrical contact with the surface and are situated in defined locations on the surface is provided. Additionally, a hybrid detector comprising... Agent: Fish & Richardson, PC

20070224723 - Solid state imaging device and method for manufacturing solid state imaging device: A solid state imaging device and a method for manufacturing the same that prevents the reproduction characteristic of an optical image from being affected by diagonal light on a semiconductor substrate surface. A CCD image sensor includes a semiconductor substrate, light receiving pixels formed on the semiconductor substrate, and a... Agent: Sheridan Ross PC

20070224724 - Self aligned memory element and wordline: An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top of the electrode layer of... Agent: Amin, Turocy & Calvin, LLP

20070224725 - Substrate processing method and apparatus fabrication process of a semiconductor device: A method for processing a substrate having an insulation film and a metal layer thereon comprises the steps of supplying a carboxylic acid anhydride to the substrate, and heating the substrate during the step of supplying the carboxylic acid anhydride to the substrate.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224726 - Thin film plate phase change ram circuit and manufacturing method: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070224727 - Methods of forming a diamond micro-channel structure and resulting devices: A diamond micro-channel structure disposed on a die, as well as methods of forming the same, are disclosed. One or more walls of each channel may comprise diamond (or other diamond-like material). The micro-channel structure may form part of a fluid cooling system for the die. Other embodiments are described... Agent: Intel Corporation C/o Intellevate, LLC

20070224730 - Hillock-free aluminum layer and method of forming the same: A hillock-free conductive layer comprising at least two aluminum (Al) layers formed on a substrate, wherein said at least two Al layers comprise a barrier Al layer formed on the substrate, and a pure Al layer formed on the barrier Al layer. The barrier Al layer could be an aluminum... Agent: Rabin & Berdo, PC

20070224729 - Method for manufacturing a flip-chip package, substrate for manufacturing and flip-chip assembly: A method for manufacturing a flip-chip package, in particular to a method for filling the space between an active side of a chip and a contact side of a substrate is disclosed. Furthermore, a substrate for supporting the filling and a flip-chip assembly is disclosed. The substrate includes a feed... Agent: Slater & Matsil LLP

20070224728 - Method for wafer level package of sensor chip: A method for wafer level package (WLP) of sensor chips is provided, including the steps of: providing a wafer, the wafer including a plurality of die regions, each the die region on a first surface of the wafer comprising an active area and a pad surrounding the active area; bounding... Agent: Birch Stewart Kolasch & Birch

20070224731 - Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward,... Agent: Kratz, Quintos & Hanson, LLP

20070224732 - Manufacturing method of a package structure: A manufacturing method of a package structure is provided. Firstly, a substrate having a surface is provided. Next, a chip is disposed on the surface of the substrate. Then, a packing material layer is formed on the surface of the substrate. Next, a thin film is pasted on the packing... Agent: Birch Stewart Kolasch & Birch

20070224733 - Die bonding: A die bonding method and apparatus by which a wafer substrate 11 adhered to a carrier tape 13 by an adhesive layer 12 is laser machined through the wafer substrate and through the adhesive layer at most to scribe the carrier tape to form a singulated die 15 with an... Agent: Seyfarth Shaw LLP

20070224734 - Method for bonding heatsink and semiconductor device with heatsink: A simple method for bonding a heatsink for improving heat-radiating efficiency, comprising the steps of sticking a double-sided adhesive tape to an end portion on an adhesion surface of at least either the heatsink or the semiconductor device; applying an adhesive onto the adhesion surface of at least either the... Agent: Kratz, Quintos & Hanson, LLP

20070224735 - Optical transmission channel board, board with built-in optical transmission channel, and data processing apparatus: A fabrication method for an optical transmission channel board includes a first step of forming on a substrate a layer containing an electrically conductive material, and a second step of patterning said layer containing an electrically conductive material formed on said substrate, and thereby forming circuit patterns at least a... Agent: Ratnerprestia

20070224736 - Nonvolatile semiconductor memory and fabrication method therefor: A fabrication method for a nonvolatile semiconductor memory forming gate insulating films for a memory cell transistor and a select gate transistor on a semiconductor substrate, forming a floating gate for the memory cell transistor and a gate electrode for the select gate transistor, forming a cap insulating film for... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224737 - Method for creating and tuning electromagnetic bandgap structure and device: Tuned Electromagnetic Bandgap (EBG) devices, and a method for making and tuning tuned EBG devices are provided. The method includes the steps of providing first and second overlapping substrates, placing magnetically alignable conductive material between the substrates, and applying a magnetic field in the vicinity of the magnetically alignable conductive... Agent: Delphi Technologies, Inc.

20070224738 - Semiconductor device with a multi-plate isolation structure: A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench (62) formed therein. The isolation trench (62) may have first and second opposing inner walls (74, 76) and a floor (78). First and second conductive... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070224742 - E-ink display and method for repairing the same: An E-ink display and method for repairing the same is provided. The method is for repairing a thin film transistor array substrate of the E-ink display. The thin film transistor array substrate having a plurality of pixel units is provided initially. Each of the pixel unit includes a thin film... Agent: Sheehan Phinney Bass & Green, PA C/o Peter Nieves

20070224741 - Semiconductor element, semiconductor device, and method of manufacturing the same: A method of manufacturing a semiconductor element includes: (a) preparing a first substrate provided with a plurality of protruding sections formed on a surface of the first substrate and a second substrate provided with a semiconductor film formed on a surface of the second substrate; and (b) executing a heat... Agent: Oliff & Berridge, PLC

20070224740 - Thin-film transistor and method of fabricating the same: A conductive film is processed in a first etching step, and thinned by reprocessing using light ashing. An exposed portion of an insulating film is etched away in the film thickness direction, thereby forming a step on the insulating film. Impurity ions are implanted into a semiconductor layer.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224739 - Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s): A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.... Agent: Sonnenschein Nath & Rosenthal LLP

20070224743 - Thermal dissipation structures for finfets: A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070224744 - Thin film transistor, method of fabricating the same, and flat panel display using thin film transistor: A thin film transistor may include an active layer formed on an insulating substrate and formed with source/drain regions and a channel region; a gate insulating film formed on the active layer; and a gate electrode formed on the gate insulating film. The gate electrode may be formed of a... Agent: H.c. Park & Associates, PLC

20070224747 - System and method for producing a semiconductor circuit arrangement: Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed... Agent: Brinks Hofer Gilson & Lione Infineon

20070224746 - Method and apparatus providing different gate oxides for different transitors in an integrated circuit: An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide... Agent: Dickstein Shapiro LLP

20070224748 - Semiconductor body comprising a transistor structure and method for producing a transistor structure: A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried zone, a second zone having a second conductivity type that is different from the first conductivity type... Agent: Fish & Richardson PC

20070224745 - Semiconductor device and fabricating method thereof: A semiconductor device including a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer is disclosed. The gate dielectric layer is disposed on the substrate and the gate whose top area is larger than its bottom area is disposed on the gate dielectric... Agent: Jianq Chyun Intellectual Property Office

20070224749 - Semiconductor device fabrication method: According to the present invention, there is provided a semiconductor device fabrication method having: coating a semiconductor substrate with a silazane perhydride polymer solution prepared by dispersing a silazane perhydride polymer in a solvent containing carbon, thereby forming a coating film; forming a polysilazane film by volatilizing the solvent by... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070224750 - Covert transformation of transistor properties as a circuit protection method: A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are applied to the device.... Agent: Robert Popa C/o Ladas & Parry

20070224751 - Embedded non-volatile memory cell with charge-trapping sidewall spacers: An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells and the FETs are made up of a spacer material with local charge storage... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070224752 - Laterally diffused metal oxide semiconductor device and method of forming the same: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region... Agent: Slater & Matsil, L.L.P.

20070224753 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.... Agent: Dickstein Shapiro LLP

20070224754 - Structure and method of three dimensional hybrid orientation technology: A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. In use, the device includes a nFET... Agent: Greenblum & Bernstein, P.L.C

20070224755 - Semiconductor device manufacturing method including oblique ion implantation process and reticle pattern forming method: An active region and an opposite conductivity active region are formed in a semiconductor substrate. The opposite conductivity active region is covered with a resist pattern. Impurities are implanted into a surface layer of the active region. An angle θ0 is defined as a tilt angle obtained by tilting a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070224756 - Method for fabricating recessed gate mos transistor device: A method of fabricating self-aligned gate trench utilizing TTO spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. Trench capacitors are formed in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide... Agent: North America Intellectual Property Corporation

20070224757 - Offset vertical device: The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical... Agent: Scully, Scott, Murphy & Presser, P.C.

20070224758 - Semiconductor memory device and related fabrication method: Embodiments of the invention provide a semiconductor memory device and a method for fabricating the semiconductor memory device. The semiconductor memory device comprises a source region and a drain region disposed in a semiconductor substrate; a buried contact disposed on and electrically connected to the source region of the transistor;... Agent: Volentine & Whitt PLLC

20070224759 - Method for forming an integrated memory device and memory device: The invention in one of the embodiments refers to a method for forming an integrated memory device, the method including a forming a plurality of bitlines, wherein forming the plurality of bitlines includes forming diffusion lines in a substrate, forming an electrically conductive silicidation barrier layer on a substrate surface... Agent: Slater & Matsil LLP

20070224760 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate insulating film, forming a plurality of trenches in the first silicon film and in the mask film to a depth to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070224761 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a silicon substrate 10 having a device region 11, a transistor including a gate electrode 20 formed in the device region 11 with the gate insulation film 14 formed therebetween, and a dummy metal layer 52 formed over the gate electrode 20 with an inter-layer insulation... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070224762 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a recess with a device separating film and a first hard mask layer so that a pad nitride film for defining a recess gate region may remain with a conventional mask. The method additionally the recess gate region to facilitate a... Agent: Heller Ehrman LLP

20070224763 - Semiconductor device and method of manufacturing the same: In a method of manufacturing a semiconductor device, a trench is formed to have an upper quadrangular section and a lower circular section which is formed through a hydrogen annealing process, to extend in a depth direction of a semiconductor substrate. An insulating film is formed on a surface of... Agent: Young & Thompson

20070224764 - Method for manufacturing insulated-gate type field effect transistor: A poly-silicon layer is deposited on a surface of a substrate after forming a gate insulating film in an element hole of a field insulating film 12, and thereon a silicon oxide layer is formed by a thermal oxidation process. After patterning the silicon oxide layer in accordance with a... Agent: Dickstein Shapiro LLP

20070224765 - Methods of fabricating semiconductor devices having a double metal salicide layer: A semiconductor device is fabricated by forming a gate electrode structure, comprising a gate oxide layer pattern, a polysilicon layer pattern, and sidewall spacers on a silicon substrate, forming source/drain regions on both sides of the gate electrode structure in the silicon substrate, depositing a physical vapor deposition (PVD) cobalt... Agent: Myers Bigel Sibley & Sajovec

20070224766 - Selective etch for patterning a semiconductor film deposited non-selectively: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A... Agent: Intel/blakely

20070224767 - Semiconductor device with recessed trench and method of fabricating the same: A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and extends above the... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20070224768 - Method and apparatus for delivery of pulsed laser radiation: A method and apparatus delivers pulsed laser energy to a damage-sensitive surface. The pulse scanning method and apparatus allow for the deposition of a total dose of laser radiation that could not be attained by any conventional means without damaging the substrate being exposed. Using a solid-state diode pumped YAG... Agent: Mills & Onello LLP

20070224769 - Semiconductor device and manufacturing method thereof: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity... Agent: Rossi, Kimms & Mcdowell LLP.

20070224770 - Systems and methods for fabricating self-aligned memory cell: Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr1-XCaXMnO3 (PCMO) layer above the insulator and the metal... Agent: Tran & Associates

20070224771 - Semiconductor device having fuse and capacitor at the same level and method of fabricating the same: In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is placed on the fuse area, and a lower plate is placed on the... Agent: Volentine & Whitt PLLC

20070224773 - Method of producing simox wafer: A SIMOX wafer is produced at an oxygen ion implantation step and a high-temperature annealing step, wherein an oxide film is formed on a surface of a wafer prior to the oxygen ion implantation and then the oxygen ion implantation is conducted through the oxide film.... Agent: Sughrue Mion, PLLC

20070224772 - Method for forming a stressor structure: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer (224) disposed on a buried dielectric layer (222). A trench (229) is created in the semiconductor structure which exposes a portion of the buried... Agent: Fortkort & Houston P.C.

20070224774 - Method of producing simox wafer: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than... Agent: Sughrue Mion, PLLC

20070224775 - Trench isolation structure having an expanded portion thereof: Embodiments of the present invention relate to the fabrication of isolation structures within a microelectronic substrate for microelectronic devices, wherein the design of the isolation structures reduce or substantially eliminate the formation of surface voids within a dielectric material of the isolation structures. These surface voids are reduced or avoided... Agent: Intel Corporation C/o Intellevate, LLC

20070224776 - Method for forming a 3d interconnect and resulting structures: A method for forming three-dimensional (3D) integrated circuits includes providing a first wafer comprising a silicon layer on a top surface of the first wafer, providing a second wafer comprising a silicon oxide layer on a top surface of the second wafer, bonding the first and the second wafers by... Agent: Slater & Matsil, L.L.P.

20070224777 - Substrate holder having a fluid gap and method of fabricating the substrate holder: A substrate holder (20) for supporting a substrate (30). A heating component (50) is positioned adjacent to a supporting surface and between the supporting surface and a cooling component (60). A fluid gap is positioned between the cooling component and the heating component, the fluid gap configured to receive a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224778 - Method of producing simox wafer: A SIMOX wafer is produced by implanting oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which a SOI film having a thickness thicker than a target SOI film thickness is previously formed and a final adjustment of the SOI film thickness is... Agent: Sughrue Mion, PLLC

20070224780 - Method for dicing a wafer: A method for dicing a wafer is provided. A layer of adhesive material is applied to the back surface of the wafer so as to provide a sufficient mechanical strength for the wafer during dicing process thereby preventing the dice diced from the wafer from undue chipping on the back... Agent: Lowe Hauptman Berner, LLP

20070224781 - Separation method for cutting semiconductor package assemblage for separation into semiconductor packages: A separation method by which a semiconductor package assemblage is cut in a predetermined width W1 along streets arranged in a lattice pattern to separate the semiconductor package assemblage into a plurality of semiconductor packages, the semiconductor package assemblage including a metallic frame having metallic die pads of a predetermined... Agent: Smith, Gambrell & Russell

20070224779 - Method for fabricating a bga device and bga device: In a method chips are provided with solder balls as of a ball grid array directly without any substrate thereby forming a BGA device. The inventive BGA device is protected on its active side by a protective layer made of solder resist or other equivalent materials and the solder balls... Agent: Slater & Matsil LLP

20070224782 - Gettering method and a wafer using the same: It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for... Agent: Birch Stewart Kolasch & Birch

20070224783 - Process for forming low defect density, ideal oxygen precipitating silicon: The present invention is directed to a process for producing a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of... Agent: Senniger Powers

20070224786 - Epitaxial semiconductor deposition methods and structures: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between... Agent: Knobbe Martens Olson & Bear LLP

20070224784 - Semiconductor material having an epitaxial layer formed thereon and methods of making same: A semiconductor material having an epitaxial layer formed thereon and methods of forming an epitaxial layer on a semiconductor material are provided. The method includes disposing a masking layer and patterning the masking layer to form openings and growing an epitaxial layer through the openings and over the masking layer... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20070224785 - Strain-inducing film formation by liquid-phase epitaxial re-growth: A method to form a strain-inducing three-component epitaxial film is described. In an embodiment, a three-component epitaxial film comprises atoms from a parent film, charge-neutral lattice-substitution impurities and charge carrier dopant impurities. In one embodiment, the charge-neutral lattice-substitution impurities are smaller and present in greater concentration than the charge carrier... Agent: Intel/blakely

20070224787 - Relaxed heteroepitaxial layers: Some embodiments of the invention are related to manufacturing semiconductors. Methods and apparatuses are disclosed that provide thin and fully relaxed SiGe layers. In some embodiments, the presence of oxygen between a single crystal structure and a SiGe heteroepitaxial layer, and/or within the SiGe heteroepitaxial layer, allow the SiGe layer... Agent: Knobbe, Martens, Olsen & Bear LLP

20070224788 - Fabrication of large grain polycrystalline silicon film by nano aluminum-induced crystallization of amorphous silicon: One aspect of the present invention relates to a method for fabricating a polycrystalline silicon film. In one embodiment, the method includes the steps of providing a substrate having a thermally-grown silicon dioxide layer, forming an amorphous silicon film on the thermally-grown silicon dioxide layer of the substrate, forming an... Agent: Morris Manning Martin LLP

20070224789 - Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film: In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor substrate with an opening that exposes a portion of the defined... Agent: Myers Bigel Sibley & Sajovec

20070224790 - Zn ion implanting method of nitride semiconductor: A method of implanting a zinc (Zn)-ion into a nitride-based semiconductor substrate, the method includes: providing a homogeneous substrate on which a gallium nitride layer is grown; placing the homogeneous substrate in a crucible in which gallium nitride powders are coated; placing the crucible into a furnace; and performing a... Agent: Mcdermott Will & Emery LLP

20070224791 - Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof: By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature at 300° C. or less, setting the sputtering power from 1 kW to 9 kW, and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa,... Agent: Edward D. Manzo Cook, Alex, Mcfarron, Manzo,

20070224792 - Manufacturing method of semiconductor device and etching solution: This disclosure concerns a manufacturing method of a semiconductor device comprising an etching process using an etching solution having ozone dissolved by 10 ppm or more into a liquid containing H2SO4 by 86 wt % to 97.9 wt %, HF by 0.1 wt % to 10 wt %, and H2O... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070224797 - Method for manufacturing semiconductor device, method for forming alignment mark, and semiconductor device: A method for manufacturing a semiconductor device includes the steps of: forming a first dielectric film on a substrate; etching the first dielectric film in a plug forming region to form a first via hole; forming a first plug electrode in the first via hole; forming a conductive film on... Agent: Harness, Dickey & Pierce, P.L.C

20070224795 - Dummy vias for damascene process: A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein... Agent: Haynes And Boone, LLP

20070224796 - Method of forming a phase changeable structure: The present invention relates to a method of forming a phase changeable structure wherein an upper electrode is formed on a phase changeable layer. A material including fluorine can be provided to the phase changeable layer and the upper electrode. The phase changeable layer can be etched to form a... Agent: Marger Johnson & Mccollom, P.C.

20070224794 - Single passivation layer scheme for forming a fuse: An integrated circuit structure comprising a fuse and a method for forming the same are provided. The integrated circuit structure includes a substrate, an interconnection structure over the substrate, a fuse connected to the interconnection structure, and an anti-reflective coating (ARC) on the fuse. The ARC has an increased thickness... Agent: Slater & Matsil, L.L.P.

20070224793 - Temperature-controlled metallic dry-fill process: A method for performing ionized physical vapor deposition (iPVD) is described, whereby the substrate temperature can be rapidly changed to control a metal deposition process and increase the quality of the metal deposited. In one embodiment, a copper deposition process can be performed.... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070224798 - Semiconductor device and medium of fabricating the same: A highly-reliable semiconductor device and a method of fabricating the semiconductor device, while stably carrying out IC test, are proposed. A pad portion after an IC test using a probe is covered with a second passivation film. It is therefore made possible to protect the pad, which has partially been... Agent: Young & Thompson

20070224799 - System for making a semiconductor device using bump material including liquid: A system of making a semiconductor device by forming bumps on pads of a test piece which is a semiconductor wafer or chip is disclosed. The system includes a mask substrate having holding holes; a supply portion for supplying a bump material including liquid, which contains a plurality of individual... Agent: Cohen, Pontani, Lieberman & Pavane

20070224800 - Production method for semiconductor device: A method for producing a semiconductor device that uses a silicone-based die bonding material with high heat resistance and a low elastic modulus is provide. The method includes the steps of: applying a heat-curable silicone-based die bonding material to a substrate, placing a semiconductor element on the coated surface of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224803 - Methods for etching a dielectric barrier layer with high selectivity: Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing... Agent: Patterson & Sheridan, LLP

20070224802 - Semiconductor device and a manufacturing method of the same: A first BPSG film covering a transistor is formed. Next, a second BPSG film is formed on the first BPSG film. The B concentration in the first BPSG film is about five times higher than the B concentration in the second BPSG film. Next, the first BPSG film is separated... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070224804 - Carbon nanotube-based electronic devices made by electrolytic deposition and applications thereof: Carbon nanotube-based devices made by electrolytic deposition and applications thereof are provided. In a preferred embodiment, the present invention provides a device comprising at least one array of active carbon nanotube junctions deposited on at least one microelectronic substrate. In another preferred embodiment, the present invention provides a device comprising... Agent: Dickstein Shapiro LLP

20070224801 - Dielectric interconnect structures and methods for forming the same: Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In... Agent: Hoffman, Warnick & D'alessandro LLC

20070224805 - Semiconductor device and manufacturing method therefor: To provide a semiconductor device that enables high integration degree, and a manufacturing method therefor. A multi-chip module according to an embodiment of the present invention includes: a first semiconductor chip having a first bonding pad; a second semiconductor chip having a second bonding pad thinner than the first bonding... Agent: Mcginn Intellectual Property Law Group, PLLC

20070224806 - Metal polishing slurry:

20070224807 - Methods for etching a dielectric barrier layer with high selectivity: Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing... Agent: Patterson & Sheridan, LLP

20070224808 - Silicided gates for cmos devices: A silicided gate for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate. A first dielectric layer is formed over the gate electrode and the substrate, and a second dielectric layer is formed over the first dielectric layer. The second dielectric layer... Agent: Slater & Matsil, L.L.P.

20070224809 - Method of forming wiring: Resist films 19 for liftoff are formed on an insulating layer 12 corresponding to a wiring formation region A so as to expose the insulating layer 12 corresponding to formation positions of first seed layers 14 and thereafter, metal films 21 are formed. Then, the resist films 19 for liftoff... Agent: Drinker Biddle & Reath (dc)

20070224810 - Manufacturing method for an integrated semiconductor structure: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070224811 - Substrate processing method and substrate processing apparatus: A substrate processing method can completely remove a corrosion inhibitor and/or a metal complex from a surface of a substrate prior to catalyst application processing and/or electroless plating, and can form a protective film having a uniform thickness on the surface of interconnects. The substrate processing method includes preparing a... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070224812 - Pattern film forming method and pattern film forming apparatus: A pattern film forming method includes a step of producing a transfer sheet in which a thin film is formed on a surface of a sheet-shaped material and a step of pressing the thin film against a pattern film formation surface of the substrate with a pressing member having convex... Agent: Sughrue Mion, PLLC

20070224816 - Organosilane hardmask compositions and methods of producing semiconductor devices using the same: p

20070224818 - Substrate processing method and storage medium: A substrate processing method capable of preventing a substrate rear surface from being scratched when attracted onto an electrostatic chuck. In a coater/developer (11), a photocurable resin is coated onto a rear surface of a wafer (W), the resin is cured to form a resin protective film, and a resist... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224819 - Topography directed patterning: A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers which have been formed by a pitch multiplication process in which... Agent: Knobbe Martens Olson & Bear LLP

20070224813 - Device and method for etching flash memory gate stacks comprising high-k dielectric: In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching... Agent: Balzan Intellectual Property Law, PC

20070224814 - Integrated multi-wavelength fabry-perot filter and method of fabrication: A method is provided for forming a monolithically integrated optical filter, for example, a Fabry-Perot filter, over a substrate (10). The method comprises forming a first mirror (16) over the substrate (10). A plurality of etalon material layers (32, 34, 36, 38) are formed over the mirror (16), and a... Agent: Ingrassia Fisher & Lorenz, P.C.

20070224817 - Plasma processing apparatus, plasma processing method, and storage medium: A plasma processing apparatus having a substrate processing chamber, which enables leakage of plasma into an exhaust space to be prevented. The substrate processing chamber has therein a processing space in which plasma processing is carried out on a substrate, an exhaust space for exhausting gas out of the processing... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224815 - Substrate patterning for multi-gate transistors: Some embodiments of the present invention include apparatuses and methods relating to improved substrate patterning for multi-gate transistors.... Agent: Intel Corporation C/o Intellevate, LLC

20070224820 - Facility with multi-storied process chamber for cleaning substrates and method for cleaning substrates using the facility: A facility for cleaning substrates such as semiconductor wafers includes a loading/unloading part, an aligning part where wafers are repositioned from a horizontal state to a vertical state, a cleaning part performing etchant-treating, rinsing, and drying processes for wafers and having a plurality of process chamber stacked, and an interface... Agent: Harness, Dickey & Pierce, P.L.C

20070224821 - Method for manufacturing silicon wafers: This silicon wafer production process comprises in the order indicated a planarization step, in which the front surface and the rear surface of a wafer are ground or lapped, a single-wafer acid etching step, in which an acid etching liquid is supplied to the surface of the wafer while spinning... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070224822 - Halide anions for metal removal rate control: The inventive chemical-mechanical polishing system comprises a polishing component, a liquid carrier, an oxidizing agent, and a halogen anion. The inventive method comprises chemically-mechanically polishing a substrate with the polishing system.... Agent: Steven Weseman Associate General Counsel, I.p.

20070224823 - Topography directed patterning: A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers which have been formed by a pitch multiplication process in which... Agent: Knobbe Martens Olson & Bear LLP

20070224824 - Method of repairing process induced dielectric damage by the use of gcib surface treatment using gas clusters of organic molecular species: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method... Agent: International Business Machines Corporation Dept. 18g

20070224825 - Methods for etching a bottom anti-reflective coating layer in dual damascene application: Methods for two step etching a BARC layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having vias filled with a BARC layer disposed on the substrate in an etch reactor, supplying a first gas mixture into the reactor to etch a... Agent: Patterson & Sheridan, LLP

20070224827 - Methods for etching a bottom anti-reflective coating layer in dual damascene application: Methods for two step etching a BARC layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having vias filled with a BARC layer disposed on the substrate in an etch reactor, supplying a first gas mixture into the reactor to etch a... Agent: Patterson & Sheridan, LLP

20070224826 - Plasma dielectric etch process including in-situ backside polymer removal for low-dielectric constant material: A plasma etch process with in-situ backside polymer removal begins with a workpiece having a porous or non-porous carbon-doped silicon oxide dielectric layer and a photoresist mask on a surface of the workpiece. The workpiece is clamped onto an electrostatic chuck in an etch reactor chamber. The process includes introducing... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20070224828 - Plasma etching method: A plasma etching apparatus is arranged to perform main etching for etching a poly-crystalline silicon film by use of Cl2/SF6/N2 plasma obtained by exciting Cl2 gas, SF6 gas, and N2 gas, and over etching for etching the poly-crystalline silicon film by use of Cl2/HBr/CF4 plasma obtained by exciting Cl2 gas,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224829 - Use of hypofluorites, fluoroperoxides, and/or fluorotrioxides as oxidizing agent in fluorocarbon etch plasmas: A mixture and a method comprising same for etching a dielectric material from a layered substrate are disclosed herein. Specifically, in one embodiment, there is provided a mixture for etching a dielectric material in a layered substrate comprising: a fluorocarbon gas, a fluorine-containing oxidizer gas selected from the group consisting... Agent: Air Products And Chemicals, Inc. Patent Department

20070224830 - Low temperature etchant for treatment of silicon-containing surfaces: Embodiments provide a method for etching or smoothing a silicon material on a substrate. In one example, the method provides positioning a substrate containing a contaminant disposed on a silicon material within a process chamber, heating the substrate to a temperature of less than 800° C., and exposing the silicon... Agent: Patterson & Sheridan, LLP

20070224831 - Post structure, semiconductor device and light emitting device using the structure, and method for forming the same: A nanometer-scale post structure and a method for forming the same are disclosed. More particularly, a post structure, a light emitting device using the structure, and a method for forming the same, which is capable of forming a nanometer-scale post structure having a repetitive pattern by using an etching process,... Agent: Birch Stewart Kolasch & Birch

20070224834 - Dielectric material having carborane derivatives: Numerous embodiments of an apparatus and method of a dielectric material having a low dielectric constant and good mechanical strength are described. In one embodiment a dielectric material having multiple porous regions is disposed over a substrate. A caged structure is bridged within the plurality of pores. In one particular... Agent: Blakely Sokoloff Taylor & Zafman

20070224832 - Method for forming and sealing a cavity for an integrated mems device: A method is provided for constructing a microelectronic assembly. A semiconductor substrate having a MEMS device formed on a first portion thereof, a semiconductor device formed on a second portion thereof, and a build up layer having a first portion formed over the MEMS device and a second portion formed... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070224833 - Method of forming carbon polymer film using plasma cvd: A method of forming a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (CαHβXγ, wherein α and β are natural numbers of 5 or more; γ is an integer including zero; X is O,... Agent: Knobbe Martens Olson & Bear LLP

20070224835 - Semiconductor device and method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes: forming a first photosensitive material pattern having an opening hole on a work target layer formed on an active surface of a substrate; performing a first etching by performing an etching treatment to the work target layer using the first photosensitive materialpattern... Agent: Oliff & Berridge, PLC

20070224836 - Method for manufacturing semiconductor device and plasma oxidation method: A polysilicon electrode layer (103) (a first electrode layer) is formed by forming a polysilicon film on a gate oxide film (102) on a silicon wafer (101). A tungsten layer (105) (a second electrode layer) is formed on this polysilicon electrode layer (103). In addition, a barrier layer (104) is... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224837 - Method for producing material of electronic device: A process for producing electronic device (for example, high-performance MOS-type semiconductor device) structure having a good electric characteristic, wherein an SiO2 film or SiON film is used as an insulating film having an extremely thin (2.5 nm or less, for example) film thickness, and poly-silicon, amorphous-silicon, or SiGe is used... Agent: Crowell & Moring LLP Intellectual Property Group

20070224838 - Method of straining a silicon island for mobility improvement: A method for improving mobility by bending a silicon island. Oxygen diffuses and reacts down a first axis of a pFET or NFET. This results in a partial oxidation of a buried-oxide/silicon island interface. The partial oxidation produces a thickness variation in the silicon island that creates a stress along... Agent: Honeywell International Inc.

20070224839 - Heat treating apparatus, heat treating method and storage medium: A heat treating apparatus, which performs a specified heat treatment on a target object, includes a processing chamber accommodating therein the target object; a mounting table for mounting thereon the target object; a vacuum exhaust system for vacuum evacuating the processing chamber; an electromagnetic wave supply unit for irradiating an... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224840 - Method of plasma processing with in-situ monitoring and process parameter tuning: A method of selecting plasma doping process parameters includes determining a recipe parameter database for achieving at least one plasma doping condition. The initial recipe parameters are determined from the recipe parameter database. In-situ measurements of at least one plasma doping condition are performed. The in-situ measurements of the at... Agent: Rauschenbach Patent Law Group, LLC

20070218568 - Method for manufacturing ferroelectric memory device: A method for manufacturing a ferroelectric capacitor, includes the steps of: forming a ferroelectric capacitor layer having a lower electrode layer, a ferroelectric layer and an upper electrode layer on a base substrate; forming a titanium oxide layer on the ferroelectric capacitor layer; patterning the titanium oxide layer by high-temperature... Agent: Harness, Dickey & Pierce, P.L.C

20070218569 - Method of manufacturing ferroelectric memory device: A method of manufacturing a ferroelectric memory device includes: forming an active element on a substrate; forming an interlayer insulating layer on the substrate; forming an opening on the interlayer insulating layer and forming a contact plug inside the opening; forming a foundation layer above the substrate; and laminating, on... Agent: Harness, Dickey & Pierce, P.L.C

20070218571 - Disabling poorly testing rfid ics: Manufacturing methods, testing, and RFID integrated circuit wafers that have been so prepared. A function of an integrated circuit can be tested. If the test fails, a control function of the tested circuit is disabled.... Agent: Schwegman, Lundberg, Woessner & Kluth/impinj

20070218574 - Semiconductor laser manufacturing method: A method of manufacturing a semiconductor laser that has a ridge portion formed with a compound semiconductor layer containing Ga includes applying an electric current to the semiconductor laser until the characteristics of the semiconductor laser that have deteriorated due to the application of the electric current recover from the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070218581 - Photo-masking method for fabricating tft array substrate: An exemplary method for fabricating a TFT array substrate includes providing an insulating substrate (201); coating a gate metal layer (202) on the substrate; forming a plurality of gate electrodes (212) using a first photo-mask process; forming a gate insulating layer (203), a semiconducting layer (205), and a source/drain metal... Agent: Wei Te Chung Foxconn International, Inc.

20070218580 - Triple-junction filterless cmos imager cell: A triple-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is made from a bulk silicon (Si) substrate. A photodiode set including a first, second, and third photodiode are formed as a triple-junction structure in the Si substrate. A transistor set is connected to the photodiode... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070218582 - Process for making contained layers and devices made with same: t

20070218570 - Nitorgen doped silicon wafer and manufacturing method thereof: An epitaxial wafer and a high-temperature heat treatment wafer having an excellent gettering capability are obtained by performing epitaxial growth or a high-temperature heat treatment. A relational equation relating the density to the radius of an oxygen precipitate introduced in a silicon crystal doped with nitrogen at the time of... Agent: Fish & Richardson PC

20070218572 - Fabrication method of semiconductor integrated circuit device: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070218573 - Semiconductor component having test pads and method and apparatus for testing same: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is... Agent: Xilinx, Inc Attn: Legal Department

20070218575 - Method and apparatus for electroluminescence: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070218576 - Method for fabricating polysilicon liquid crystal display device: A method for fabricating a polysilicon liquid crystal display device includes: forming a first amorphous silicon layer on a substrate; forming a photoresist pattern on the first amorphous silicon layer; forming a second amorphous silicon layer over the photoresist pattern and the first amorphous silicon layer; defining a channel region... Agent: Mckenna Long & Aldridge LLP

20070218577 - Liquid crystal display panel and fabricating method thereof: A liquid crystal display (LCD) panel is fabricated with a reduced number of mask processes and includes a thin film transistor (TFT) array substrate and a color filter array substrate. The TFT array substrate includes gate and data lines insulatively crossing each other to define a pixel area, a TFT... Agent: Song K. Jung Mckenna Long& Aldridge LLP

20070218578 - Real-time cmos imager having stacked photodiodes fabricated on soi wafer: A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength;... Agent: Robert D. Varitz

20070218579 - Wide output swing cmos imager: A CMOS active pixel sensor (APS) imager cell is provided on a silicon-on-insulator (SOI) substrate. The APS imager cell is made from a SOI substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A pixel sensor cell including... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070218583 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a radiation sensitive component in and/or on a microelectronic device, placing a curable component in and/or on the microelectronic device, and forming a barrier in and/or on the microelectronic device to at... Agent: Perkins Coie LLP Patent-sea

20070218585 - Encapsulation in a hermetic cavity of a microelectronic composite, particularly of a mems: To produce a structure of a micro-electro-mechanical system (MEMS) in a hermetic cavity (38) of a microelectronic device (50), a prepared cover (30) and substrate (10) are bonded by means of silicon direct bonding (SDB). To optimise the preparation of surfaces by means of wet cleaning without impairing the properties... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218586 - Manufacturing method of semiconductor device: An adhesive layer of which thickness is over 25 μm and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070218584 - Method for wafer-level package: A method for wafer-level package. A cap wafer having cavities is bonded to a support wafer, and a portion of the cap wafer is etched through. The cap wafer is released from the support wafer, and bonded to a transparent wafer, and a portion of the cap wafer corresponding to... Agent: North America Intellectual Property Corporation

20070218587 - Soft conductive polymer processing pad and method for fabricating the same: Embodiments of the invention generally provide a conductive processing pad and a method for fabricating the same. In one embodiment the conductive processing pad includes a grid of conductive material disposed in a polymer layer. A plurality of perforations is formed through the polymer in the open area defined by... Agent: Patterson & Sheridan, LLP

20070218588 - Integrated circuit package having stacked integrated circuits and method therefor: Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed. These improved techniques allow greater stacking density of integrated circuit dies within an integrated circuit package. Additionally, the improved stacking techniques permit conventional bonding techniques for electrical connection of the various integrated circuit dies to each... Agent: Beyer Weaver LLP/ Sandisk

20070218589 - Manufacturing method of multilayer wiring substrate: A first multilayer wiring structural body 16 and a second multilayer wiring structural body 56 are simultaneously formed on both surfaces 101A, 101B of a substrate 101 and thereafter the portion of a structural body 120 corresponding to a third region C1 is folded so as to oppose a second... Agent: Drinker Biddle & Reath (dc)

20070218590 - Plating apparatus, plating method and manufacturing method for semiconductor device: A semiconductor device with plating film layers for semiconductor device leads is described. A first plating film layer that includes Sn as a main material is formed on a semiconductor device lead in which Cu or Fe—Ni is a main material. The outermost surface of the lead includes a plating... Agent: Fish & Richardson P.C.

20070218591 - Method for fabricating a metal protection layer on electrically connecting pad of circuit board: This invention discloses a method for electroplating nickel/gold on electrically connecting pads on a substrate for chip package and structure thereof. The method comprises: forming a conductive film on a substrate circuit-patterned and defined with a circuit layer; forming on the substrate a resist with an opening for exposing a... Agent: Sawyer Law Group LLP

20070218593 - Method for producing semiconductor package: A method for producing a semiconductor package including a main semiconductor chip having a semiconductor circuit formed on one surface thereof, at least one subsidiary semiconductor chip stacked on the other surface of the main semiconductor chip, and an encapsulation resin covering the subsidiary semiconductor chip. This method comprises a... Agent: Smith, Gambrell & Russell

20070218592 - Green sheet, production method of green sheet and production method of electronic device: A production method, comprising the steps of preparing a pre-compression green sheet including ceramic powder and a binder resin and compressing the pre-compression green sheet to obtain compressed green sheet: wherein a difference (Δρg) between a pre-compression sheet density (ρg1) of the pre-compression green sheet and a post-compression sheet density... Agent: Oliff & Berridge, PLC

20070218594 - Method of forming metal wiring and method of manufacturing active matrix substrate: A method of forming a metal wiring includes: forming a foundation layer on a substrate; applying a solution including fine metal particles and a dispersion stabilizer on the foundation layer; and heating the applied solution to form into a conductive layer, wherein after the applying of the solution, the conductive... Agent: Harness, Dickey & Pierce, P.L.C

20070218595 - Power electronics equipments: Power electronics equipment includes air-cored insulating transformers inserted between a control circuit grounded to a vehicle body and an upper arm biased at a high voltage, and air-cored insulating transformers between the control circuit grounded to the vehicle body and the lower arm biased at a high voltage. Each of... Agent: Kanesaka Berner And Partners LLP

20070218596 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode... Agent: Foley And Lardner LLP Suite 500

20070218597 - Structure and method for controlling the behavior of dislocations in strained semiconductor layers: A structure and method for controlling the behavior of dislocations in strained semiconductor layers is described incorporating a graded alloy region to provide a strain gradient to change the slope or curvature of a dislocation propagating upwards or gliding in the semiconductor layer in the proximity of the source and... Agent: Robert M. Trepp IBM Corporation

20070218598 - Method for forming ultra thin low leakage multi gate devices: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and... Agent: Texas Instruments Incorporated

20070218599 - Method for producing silicon wafer and silicon wafer: A method for producing a silicon wafer, comprising performing a reduction of an interface state by annealing of an SOI wafer having a buried oxide layer at a temperature of 250 to 900° C. for 3 minutes to 8 hours in an atmosphere composed of one or more gases selected... Agent: Kolisch Hartwell, P.C.

20070218600 - Method for making a field effect transistor with diamond-like carbon channel and resulting transistor: The field effect transistor comprises a source and a drain connected by a channel controlled by a gate electrode separated from the channel by a gate insulator. The channel is formed by a diamond-like carbon layer. The method for making the transistor successively comprises deposition of a diamond-like carbon layer... Agent: Oliff & Berridge, PLC

20070218602 - Thin film transistor and method for fabricating the same: The present invention relates to a thin film transistor for preventing short of circuit by step and a method for fabricating the thin film transistor and provides a thin film transistor including a buffer layer formed on glass substrate; an activation layer formed on the buffer layer; and a gate... Agent: Robert E. Bushnell

20070218601 - Thin film transistor substrate for liquid crystal display device and method of manufacturing the same: A thin film transistor substrate for a liquid crystal display device includes a substrate, a metal layer on the substrate, and an aluminum complex oxide layer on the metal layer. The aluminum complex oxide layer comprises at least one selected from the group consisting of zirconium, tungsten, chromium and molybdenum.... Agent: Macpherson Kwok Chen & Heid LLP

20070218603 - Improved soi substrates and soi devices, and methods for forming the same: An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried... Agent: Scully Scott Murphy & Presser, PC

20070218604 - Method of manufacturing a semiconductor device: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order... Agent: Fish & Richardson P.C.

20070218605 - Semiconductor device and method of manufacture thereof: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070218606 - Semiconductor device and method of manufacture thereof: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070218608 - Method of manufacturing a semiconductor device: By using lasers having different wavelengths in laser annealing of an amorphous semiconductor film, the amorphous semiconductor film can be crystallized and the crystallinity of the crystallized film is improved. A laser 126 to 370 nm in wavelength is used first to subject an amorphous semiconductor film to laser annealing,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070218607 - Methods of forming single crystalline layers and methods of manufacturing semiconductor devices having such layers: In a method of forming a single crystalline semiconductor layer, an amorphous layer may be formed on a seed layer that includes a single crystalline material. The single crystalline layer may be formed from the amorphous layer by irradiating a laser beam onto the amorphous layer using the seed layer... Agent: Myers Bigel Sibley & Sajovec

20070218609 - Manufacturing method of semiconductor device: A gate electrode is formed on a first conductivity type substrate. A second conductivity type implantation region is formed in the first conductivity type substrate. A first conductivity type implantation region is formed by implanting the first conductivity type impurities into the first conductivity type substrate to a depth deeper... Agent: Rabin & Berdo, PC

20070218610 - Methods of making a molecular detection chip having a metal oxide silicon field effect transistor on sidewalls of a micro-fluid channel: A molecular detection chip including a metal oxide silicon-field effect transistor (MOSFET) on sidewalls of a micro-fluid channel and a molecular detection device including the molecular detection chip are provided. A molecular detection method, particularly, qualification methods for the immobilization of molecular probes and the binding of a target sample... Agent: Myers Bigel Sibley & Sajovec

20070218613 - Fully isolated photodiode stack: An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070218612 - Method for fabricating a recessed-gate mos transistor device: A method for fabricating a recessed-gate transistor is disclosed. A trench is recessed into a substrate. A spacer is formed on sidewalls of the trench. A trench bottom oxide is formed. The spacer is then stripped off. A source/drain doping region is formed on the exposed sidewalls of the trench... Agent: North America Intellectual Property Corporation

20070218611 - Leakage barrier for gan based hemt active device: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is... Agent: Patent Administrator Katten Muchin Rosenman LLP

20070218614 - Semiconductor device and method of manufacturing the same, electronic device and method of manufacturing the same, and electronic instrument: A semiconductor device including: a semiconductor substrate in which an integrated circuit is formed; an insulating layer formed on the semiconductor substrate and having a first surface and a second surface which is higher than the first surface; a first electrode formed to avoid the second surface and electrically connected... Agent: Hogan & Hartson L.L.P.

20070218615 - Trench type mosgated device with strained layer on trench sidewall: A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is... Agent: Ostrolenk Faber Gerb & Soffen

20070218616 - Semiconductor constructions, and methods of forming semiconductor constructions: The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown over the dielectric material and within the gap. Subsequently, a transistor is... Agent: Wells St. John P.s.

20070218617 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate; forming a second semiconductor layer above the first semiconductor layer, the second semiconductor layer having a smaller selection ratio of wet-etching than the first semiconductor layer; forming a hole having the semiconductor substrate... Agent: Advantedge Law Group, LLC

20070218618 - Interlayer dielectric under stress for an integrated circuit: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD... Agent: Freescale Semiconductor, Inc. Law Department

20070218619 - Method of manufacturing nonvolatile semiconductor memory device: A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a... Agent: Lee & Morse, P.C.

20070218620 - Structures and methods for making strained mosfets: A method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few... Agent: Greenblum & Bernstein, P.L.C

20070218621 - Integration of strained ge into advanced cmos technology: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure... Agent: George Sai-halasz

20070218622 - Method of fabricating local interconnects on a silicon-germanium 3d cmos: A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS... Agent: Robert D. Varitz

20070218623 - Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a... Agent: Patterson & Sheridan, LLP

20070218624 - Semiconductor device and method of manufacturing the same: A method of manufacturing an MIS semiconductor device includes forming a high dielectric film as a gate insulator on a semiconductor substrate of a first conductivity type, heat-treating the semiconductor substrate in ambient with hydrogen and oxygen gases to form an interface layer between the semiconductor substrate and the high... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070218625 - Trench metal-insulator-metal (mim) capacitors integrated with middle-of-line metal contacts, and method of fabricating same: The present invention relates to a method of fabrication process which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET... Agent: International Business Machines Corporation Dept. 18g

20070218626 - Method for fabricating metal-insulator-metal capacitor: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the... Agent: J.c. Patents, Inc.

20070218627 - Device and a method and mask for forming a device: A method of forming a semiconductor device includes patterning a layer stack to form single conductive lines and single landing pads. Patterning of the layer stack includes two lithographic exposures using a set of two different photomasks. The landing pads are arranged at on side of an array region defined... Agent: Dicke, Billig & Czaja

20070218628 - Electronic device including a semiconductor fin and a process for forming the electronic device: An electronic device can include a base layer, a semiconductor layer, and a first semiconductor fin spaced apart from and overlying a semiconductor layer. In a particular embodiment, a second semiconductor fin can include a portion of the semiconductor layer. In another aspect, a process of forming an electronic device... Agent: Larson Newman Abel Polansky & White, LLP

20070218630 - Microstructure, semiconductor device, and manufacturing method of the microstructure: A microstructure includes a first structural layer and a second structural layer which faces the first structural layer with a space interposed therebetween and is partially fixed to the first structural layer. At least one of the first structural layer and the second structural layer can be displaced. Further, opposed... Agent: Fish & Richardson P.C.

20070218629 - Method of fabricating an integrated memory device: Method of fabricating an integrated memory device including the steps of providing a semiconductor substrate, including an array region and a support region; providing GC-lines in said array region and in said support region, wherein the GC-lines in said support region have a first height; providing in the array region... Agent: Morrison & Foerster LLP

20070218631 - Method for forming a non-volatile memory and a peripheral device on a semiconductor substrate: A method for forming a semiconductor device includes forming a first gate electrode over a semiconductor substrate, wherein the first gate electrode comprises silicon and forming a second gate electrode over the semiconductor substrate and adjacent the first gate electrode, wherein the second gate electrode comprises silicon. Nanoclusters are present... Agent: Freescale Semiconductor, Inc. Law Department

20070218632 - Split gate type flash memory device and method for manufacturing same: A split gate type flash memory device and a method of manufacturing the split gate type flash memory device are disclosed. The split gate type flash memory device includes a silicon epitaxial layer formed in an active region of a bulk silicon substrate and a disturbance-preventing insulating film formed in... Agent: Volentine & Whitt PLLC

20070218634 - Method of fabricating flash memory cell: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked... Agent: Jianq Chyun Intellectual Property Office

20070218633 - Silicided nonvolatile memory and method of making same: A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process... Agent: Freescale Semiconductor, Inc. Law Department

20070218635 - Fully-depleted castellated gate mosfet device and method of manufacture thereof: A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a... Agent: Law Office Of John L. Isaac

20070218637 - Method for forming silicon oxide film and for manufacturing capacitor and semiconductor device: After forming a silicon nitride film 14 on a silicon oxide film 12 covering one main surface of a semiconductor substrate 10 by a CVD method, argon ions Ar+ are doped to a part (where oxidation speed should be reduced) of the silicon nitride film 14 by an ion doping... Agent: Dickstein Shapiro LLP

20070218636 - Method for forming ultra thin low leakage multi gate devices using a masking layer over the semiconductor substrate: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a masking layer over a semiconductor substrate in a first active region and a second active region of a semiconductor device, patterning the masking layer to... Agent: Texas Instruments Incorporated

20070218638 - Recessed gate structure and method for preparing the same: A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-step structure in the recess. The thickness of the gate oxide... Agent: Oliff & Berridge, PLC

20070218639 - Formation of a smooth polysilicon layer: Embodiments of the invention provide a polysilicon layer on a high-k dielectric layer with a smooth upper surface. The polysilicon layer may be formed by pretreating a wafer with a substrate, the high-k dielectric layer on the substrate and a capping layer on the high-k dielectric layer at a first... Agent: Intel Corporation C/o Intellevate, LLC

20070218640 - Semiconductor device having a gate with a thin conductive layer: A semiconductor device having a gate with a thin conductive layer is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric... Agent: Freescale Semiconductor, Inc. Law Department

20070218641 - Fully silicided extrinsic base transistor: A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the... Agent: Greenblum & Bernstein, P.L.C

20070218642 - Method for producing a semiconductor component having a metallic control electrode, and semiconductor component: A method for producing a semiconductor component, and a semiconductor component, having a metallic gate electrode deposited onto a semiconductor layer, with the gate electrode having a gate foot and a gate head. The component is produced by depositing a first layer of aluminum on the semiconductor layer, depositing a... Agent: William Collard Collard & Roe, P.C.

20070218643 - Material for forming insulating film with low dielectric constant, low dielectric insulating film, method for forming low dielectric insulating film and semiconductor device: A material for forming an insulating film with low dielectric constant of this invention is a solution including a fine particle principally composed of a silicon atom and an oxygen atom and having a large number of pores, a resin and a solvent.... Agent: Jack Q. Lever, Jr. Mcdermott, Will & Emery

20070218644 - Method of thermal processing structures formed on a substrate: The present invention generally describes one or more apparatuses and various methods that are used to perform an annealing process on desired regions of a substrate. In one embodiment, an amount of energy is delivered to the surface of the substrate to preferentially melt certain desired regions of the substrate... Agent: Patterson & Sheridan, LLP

20070218645 - Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability: An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form... Agent: Dickstein Shapiro LLP

20070218646 - Process for producing electric conductor: A process for producing electric conductor comprising a step of forming on a surface of a substrate body 11 a precursor layer 12′ made of titanium oxide doped with one or at least two dopants selected from the group consisting of Nb, Ta, Mo, As, Sb, Al, Hf, Si, Ge,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218647 - Method of creating defect free high ge content (> 25%) sige-on-insulator (sgoi) substrates using wafer bonding techniques: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding... Agent: Scully, Scott, Murphy & Presser, P.C.

20070218648 - Method for producing a thin ic chip using negative pressure: The present invention relates to a method for bonding a first thin plate having a first adhesion surface and a first back surface and a second thin plate having a second adhesion surface and a second back surface by an adhesive, the adhesive being sandwiched between said first adhesion surface... Agent: Fitch, Even, Tabin & Flannery

20070218650 - Semiconductor device, method of manufacturing thereof, and method of manufacturing base material: It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective... Agent: Eric Robinson

20070218649 - Semiconductor wafer thinning: A method for processing a first semiconductor wafer having a first surface and a second surface, by placing, on the second surface of the first wafer, a second wafer with an interposed resist layer, and thinning down the first surface of the first semiconductor wafer.... Agent: Seed Intellectual Property Law Group PLLC

20070218651 - Manufacturing method of a semiconductor device: A semiconductor wafer is mounted onto a dicing tape, the dicing tape comprising a first tape easy to stretch and a second tape difficult to stretch and provided on the first tape. Thereafter, a ring-shaped jig is mounted onto the dicing tape along the outer periphery of the semiconductor wafer... Agent: Miles & Stockbridge PC

20070218652 - Semiconductor wafer coat layers and methods therefor: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps... Agent: Intel/blakely

20070218653 - Methods for drying semiconductor wafer surfaces using a plurality of inlets and outlets held in close proximity to the wafer surfaces: Methods for processing substrate through a head that is configured to be placed in close non-contact proximity to a surface of a substrate are provided. One method includes applying a first fluid onto the surface of the substrate from conduits in the head when the head is in close proximity... Agent: Martine Penilla & Gencarella, LLP

20070218656 - Substrate processing apparatus and substrate processing method: A substrate processing apparatus comprises an applying part which is a two-fluid nozzle for applying droplets of a cleaning solution onto a substrate, a cleaning solution supply part for supplying the cleaning solution into the applying part, and a ring-shaped induction electrode located close to an outlet of the applying... Agent: Ostrolenk Faber Gerb & Soffen

20070218655 - Method for enhancing growth of semipolar (a1,in,ga,b)n via metalorganic chemical vapor deposition: A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al,In,Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen... Agent: Gates & Cooper LLP Howard Hughes Center

20070218654 - Silicon deposition over dual surface orientation substrates to promote uniform polishing: A semiconductor process and apparatus provide a planarized hybrid substrate (16) by selectively depositing an epitaxial silicon layer (70) to fill a trench (96), and then blanket depositing silicon to cover the entire wafer with near uniform thickness of crystalline silicon (102) over the epi silicon layer (70) and polycrystalline... Agent: Hamilton & Terrile, LLP

20070218657 - Deposition of crystalline layers on polymer substrates using nanoparticles and laser nanoforming: A method of forming crystalline semiconducting layers on low melting or low softening point substrates includes the steps of providing an aqueous solution medium including a plurality of semiconductor nanoparticles dispersed therein having a median size less than 10 nm, and applying the solution medium to at least one region... Agent: Akerman Senterfitt

20070218658 - Crystallization pattern and method for crystallizing amorphous silicon using the same: Disclosed are a crystallization pattern, and a method for crystallizing amorphous silicon. The method includes the steps of forming an amorphous silicon film on a glass substrate, forming a crystallization pattern by patterning the amorphous silicon film, and crystallizing the crystallization pattern into polycrystalline silicon by irradiating a laser onto... Agent: Seyfarth Shaw LLP

20070218659 - Selective silicon deposition for planarized dual surface orientation integration: A semiconductor process and apparatus provide a planarized hybrid substrate (225) having a more uniform polish surface (300) by thickening an SOI semiconductor layer (210) in relation to a previously or subsequently formed epitaxial silicon layer (220) with a selective silicon deposition process that covers the SOI semiconductor layer (210)... Agent: Hamilton & Terrile, LLP

20070218660 - Diamond film formation method and film formation jig thereof: A diamond film formation method includes forming, in a composite of a metal material and a semiconductor material, diamond nuclei on a surface of the metal material at a temperature below 650° C. in a first mixed gas containing at least carbon and hydrogen, and growing the diamond nuclei formed... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218661 - Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26)... Agent: Hamilton & Terrile, LLP

20070218662 - Antimony ion implantation for semiconductor components: A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation... Agent: Texas Instruments Incorporated

20070218663 - Semiconductor device incorporating fluorine into gate dielectric: The invention provides, in one aspect, a method of fabricating a semiconductor device. This embodiment comprises depositing a gate layer over a gate dielectric layer located over a semiconductor substrate, and incorporating fluorine into the gate dielectric layer before doping the gate layer.... Agent: Texas Instruments Incorporated

20070218664 - Vapor-phase epitaxial growth method and vapor-phase epitaxy apparatus: A vapor phase epitaxial growth method using a vapor phase epitaxy apparatus having a chamber, a support structure holding thereon a substrate in the chamber, a first flow path supplying a reactant gas for film formation on the substrate and a second flow path for exhaust of the gas, said... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070218665 - Cross-point memory array: A phase-change memory (PCM) system comprises a PCM cell array that comprises a plurality of PCM cells. Each of the PCM cells includes diode arranged adjacent to a metallization layer; a heater element arranged adjacent to the diode, and a phase-change material arranged adjacent to the heater element.... Agent: Harness, Dickey & Pierce P.L.C

20070218666 - Method of manufacturing semiconductor device with regard to film thickness of gate oxide film: A method of manufacturing a semiconductor device includes steps (a) to (d). The step (a) is a step of forming a first insulating film and a nitride film on a semiconductor substrate in this order. The step (b) is a step of removing said first insulating film and said nitride... Agent: Young & Thompson

20070218667 - Reticle containing structures for sensing electric field exposure and a method for its use: A reticle includes an image area having one or more electrically conductive portions susceptible to damage by an electric field and an electric field sensor feature, the sensor feature adapted to be at least as susceptible to being altered by the electric field as the electrically conductive portions of the... Agent: Patton Boggs LLP

20070218668 - Controlled growth of highly uniform, oxide layers, especially ultrathin layers: The present invention relates to methods of making oxide layers, preferably ultrathin oxide layers, with a high level of uniformity. One such method includes the steps of forming a substantially saturated or saturated oxide layer directly or indirectly on a semiconductor surface of a semiconductor substrate, and etchingly reducing the... Agent: Kagan Binder, PLLC

20070218669 - Method of forming a semiconductor device and structure thereof: A method for forming a semiconductor device includes providing a semiconductor substrate comprising silicon, forming a layer of dielectric on the surface of the semiconductor substrate, forming a gate electrode comprising silicon over the layer of dielectric, recessing the layer of dielectric under the gate electrode, filling the recess with... Agent: Freescale Semiconductor, Inc. Law Department

20070218672 - Immersion plating treatment for metal-metal interconnects: The present disclosure provides a method for manufacturing an interconnect in a semiconductor device, a method for manufacturing a digital micromirror device, a digital micromirror device and a method for manufacturing a projection display system. The method for manufacturing the digital micromirror device, without limitation, may include forming a first... Agent: Texas Instruments Incorporated

20070218673 - Manufacturing method of semiconductor device, reticle correcting method, and reticle pattern data correcting method: A manufacturing method of a semiconductor device including a pattern forming method, a reticle correcting method, and a reticle pattern data correcting method are disclosed. According to one aspect of the present invention, there is provided a manufacturing method of a semiconductor device, comprising forming a pattern composed of photosensitive... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070218671 - Semiconductor device having wirings formed by damascene and its manufacture method: A via hole is formed in the interlayer insulating film on a semiconductor substrate, the via hole reaching the bottom of the interlayer insulating film. A filling member fills a lower partial space in the via hole. A wiring trench continuous with the via hole as viewed in plan is... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070218670 - Method of plasma enhanced atomic layer deposition of tac and tacn films having good adhesion to copper: A method for processing a substrate for forming TaC and TaCN films having good adhesion to Cu. The method includes disposing the substrate in a process chamber of a plasma enhanced atomic layer deposition (PEALD) system configured to perform a PEALD process, and depositing a TaC or TaCN film on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218674 - Methods for forming wiring and manufacturing thin film transistor and droplet discharging method: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070218675 - Method for manufacturing bump of wafer level package: A method for manufacturing a bump of wafer level package is provided. First, a wafer with multiple pads and a passivation layer exposing the pads is provided, wherein the passivation layer between the pads has scribe lines for dividing chips after the package process. Next, a conducting layer is formed... Agent: Rabin & Berdo, PC

20070218676 - Method for forming metal bumps: A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer... Agent: Rabin & Berdo, PC

20070218677 - Method of forming self-aligned air-gaps using self-aligned capping layer over interconnect lines: A method for forming self-aligned air-gaps as IMD wherein the interconnect lines are covered with self-aligned capping layer and wherein the process of forming the capping layer is a maskless process is provided.... Agent: Baker Botts, L.L.P.

20070218678 - Method of manufacturing wafer level stack package: To manufacture a wafer level stack package, first and second wafers having first and second via patterns are prepared. The second wafer is attached to the first wafer such that the front sides of the first and second wafers face each other and the first and second via patterns are... Agent: Ladas & Parry LLP

20070218679 - Organic barc etch process capable of use in the formation of low k dual damascene integrated circuits: In some implementations, a method is provided in a plasma reactor for etching a trench in an organic planarization layer of a resist structure comprising a photoresist mask structure over a hardmask masking the organic planarization layer. This may include introducing into the plasma reactor an etchant gas chemistry including... Agent: Balzan Intellectual Property Law, PC

20070218681 - Plasma etching method and computer-readable storage medium: A plasma etching method for forming a trench on a substrate or on a film formed on the substrate, includes an substrate arranging step of arranging the substrate on which the trench is to be formed in a processing chamber having therein a first and a second electrode disposed to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218680 - Method for fabricating semiconductor device and method for fabricating magnetic head: The method for fabricating a semiconductor device comprises the step of forming an interconnection trench 38 in an inter-layer insulation film 34, the step of forming an interconnection layer 44 of Cu as the main material in the interconnection trench 38, and the step of performing cloth-rubbing processing of rubbing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070218682 - Semiconductor device: Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to... Agent: Marger Johnson & Mccollom, P.C.

20070218683 - Method of integrating peald ta- containing films into cu metallization: A method for forming a modified TaC or TaCN film that may be utilized as a barrier film for Cu metallization. The method includes disposing a substrate in a process chamber of a plasma enhanced atomic layer deposition (PEALD) system configured to perform a PEALD process, depositing a TaC or... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218684 - Method for fabricating storage node contact plug of semiconductor device: A method for fabricating a storage node contact plug of a semiconductor device includes forming an insulation layer over a substrate, etching the insulation layer to form a contact hole, forming a first conductive layer to fill the contact hole, the first conductive layer including a void, etching the first... Agent: Mayer, Brown, Rowe & Maw LLP

20070218686 - Alluminum base conductor for via fill interconnect: A semiconductor device including a dielectric layer having a opening form therein having a cross-sectional area of less than 1 μm2 and a PVD aluminum base conductor filled in the opening.... Agent: Tung & Associates

20070218685 - Method of forming trench contacts for mos transistors: A method to form transistor contacts begins with providing a transistor that includes a gate stack and first and second diffusion regions formed on a substrate, and a dielectric layer formed atop the gate stack and the diffusion regions. A first photolithography process forms first and second diffusion trench openings... Agent: Intel Corporation C/o Intellevate, LLC

20070218687 - Process for producing materials for electronic device: A process for producing an electronic device material of a high quality MOS-type semiconductor comprising an insulating layer and a semiconductor layer excellent in the electrical characteristic. The process includes: a step of CVD-treating a substrate to be processed comprising single-crystal silicon as a main component, to thereby form an... Agent: Crowell & Moring LLP Intellectual Property Group

20070218688 - Method for depositing tungsten-containing layers by vapor deposition techniques: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten-containing layer by sequentially exposing a substrate to a processing gas and a tungsten-containing gas during an atomic layer deposition process, wherein the processing gas comprises a boron-containing gas and a... Agent: Patterson & Sheridan, LLP

20070218689 - Stacked integrated circuit package-in-package system: A stacked integrated circuit package-in-package system is provided forming a first integrated circuit package having a first encapsulation and a second integrated circuit package having a second encapsulation, stacking the first integrated package below the second integrated circuit package with the first encapsulation attached to the second encapsulation, forming a... Agent: Ishimaru & Zahrt LLP

20070218690 - Fabrication method for semiconductor interconnections: There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218691 - Plasma etching method, plasma etching apparatus and computer-readable storage medium: A plasma etching method includes the step of performing a plasma etching on a CFx film formed on a substrate to be processed by using a plasma of an etching gas. A gaseous mixture including CF4 and O2 is employed as the etching gas. The etching gas further includes a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218692 - Copper-based metal polishing compositions and polishing processes: A copper-based metal polishing composition includes abrasive particles, a borate, an oxidizing agent, and water. A process for polishing a semiconductor substrate includes positioning the semiconductor substrate; polishing the positioned semiconductor substrate with a first polishing composition including abrasive particles, an ammonium borate, an oxidizing agent, and water, and having... Agent: Oliff & Berridge, PLC

20070218693 - High selectivity slurry compositions for chemical mechanical polishing: A chemical-mechanical polishing composition that includes less than about 1% wt. abrasive, an additive, and water, where a weigh percent of the additive is greater than a weight percent of the abrasive. Also, a method of polishing a semiconductor substrate in a shallow trench isolation process, the method including contacting... Agent: Townsend And Townsend And Crew LLP / Amat

20070218695 - Metal pattern forming method: A method of forming a metal pattern comprising forming a metal film having a lower layer made of a metal and an upper layer made of a metal different from the metal of the lower layer, forming a resist film having a predetermined pattern on the upper layer, and patterning... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070218694 - Method of reducing particle count inside a furnace and method of operating the furnace: A method for reducing particle count inside a furnace for processing semiconductor devices is provided. The method includes performing a gas blowing step to feed a gas into the furnace and performing a continuous gas pumping step simultaneous with performing the gas blowing step for extracting the gas from the... Agent: J.c. Patents, Inc.

20070218696 - Dry etching method: The invention provides a method for processing vertical gate patterns while reducing the Si substrate recess dimension caused by overetching. The invention provides a dry etching method for processing a gate pattern by performing a main etching process (b) and then an overetching process on a gate pattern layer 12... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070218699 - Plasma etching method and computer-readable storage medium: In a plasma etching method for plasma-etching an etching stop film after plasma-etching a low-k film in a structure in which a wiring layer, the etching stop film made of an SiC-based material, the low-k film and an etching mask are formed in that order on a substrate, the method... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218698 - Plasma etching method, plasma etching apparatus, and computer-readable storage medium: A plasma etching method includes the step of performing a plasma etching on a SiCN layer, which is formed on a substrate to be processed having a SiOCH layer and the SiCN layer, by using a plasma of an etching gas. A gaseous mixture including CF4 and NF3 is employed... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218697 - Method for removing polymer from wafer and method for removing polymer in interconnect process: A method for removing polymer from a wafer is provided. The wafer has an opening already formed thereon and a patterned photoresist layer on the wafer for forming the opening has already been removed before performing the method. The method includes performing a plasma cleaning process to remove the polymer... Agent: J. C. Patents, Inc.

20070218700 - Etching solution comprising hydrofluoric acid: This invention relates to etching solutions which comprise hydrofluoric acid and organic solvents for use in the process for the production of integrated circuits. The etching solutions according to the invention are particularly suitable for the selective etching of doped silicate layers.... Agent: Millen, White, Zelano & Branigan, P.C.

20070218702 - Semiconductor-processing apparatus with rotating susceptor: An apparatus for depositing thin film on a processing target includes: a reaction space; a susceptor movable up and down and rotatable around its center axis; and isolation walls that divide the reaction space into multiple compartments including source gas compartments and purge gas compartments, wherein when the susceptor is... Agent: Knobbe Martens Olson & Bear LLP

20070218701 - Semiconductor-processing apparatus with rotating susceptor: An apparatus for depositing thin film on a processing target includes: a reaction space; a susceptor movable up and down and rotatable around its center axis; and isolation walls that divide the reaction space into multiple compartments including source gas compartments and purge gas compartments, wherein when the susceptor is... Agent: Knobbe Martens Olson & Bear LLP

20070218703 - Method for improved growth of semipolar (al,in,ga,b)n: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the... Agent: Gates & Cooper LLP Howard Hughes Center

20070218704 - Method of light enhanced atomic layer deposition: A method light enhanced atomic layer deposition for forming a film on a substrate. The method includes disposing the substrate in a process chamber of a light enhanced atomic layer deposition (LEALD) system configured to perform a LEALD process; and depositing a film on the substrate using the LEALD process,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218705 - Method of forming a carbon polymer film using plasma cvd: A method forms a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (CαHβXγ, wherein α and β are natural numbers of 5 or more; γ is an integer including zero; X is O, N... Agent: Knobbe Martens Olson & Bear LLP

20070218706 - Heat treating apparatus, heat treating method, and storage medium: A heat treating apparatus includes a heating plate for heating a substrate coated with a coating liquid, a cooling plate for cooling the substrate and a heat pipe provided in the cooling plate, a cooling chamber being moved together with the cooling plate by the drive mechanism and accommodating a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218707 - Electronic device including semiconductor islands of different thicknesses over an insulating layer and a process of forming the same: A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first surface and a second surface opposite the first surface, and the first... Agent: Larson Newman Abel Polansky & White, LLP

20070212796 - Method for manufacturing ferroelectric memory device and ferroelectric memory device: A method for manufacturing a ferroelectric capacitor includes the steps of: forming a ferroelectric capacitor having at least a lower electrode, a ferroelectric film and an upper electrode on a base substrate; and applying an anneal treatment to the ferroelectric capacitor in an oxygen atmosphere, wherein the step of forming... Agent: Harness, Dickey & Pierce, P.L.C

20070212797 - Method of forming a ferroelectric device: A method of forming a ferroelectric device includes forming a ferroelectric pattern on a substrate, the ferroelectric pattern including a ferroelectric material including titanium and oxygen, forming an insulating layer on the ferroelectric pattern, and planarizing the insulating layer using a slurry until the ferroelectric pattern is exposed, wherein the... Agent: Lee & Morse, P.C.

20070212806 - Method of forming fine particle pattern, and method of producing a device: A method of forming a fine particle pattern, includes: forming a layer containing a silane coupling agent having a thiol group, an amino group, a hydroxyl group, a carboxyl group, or a sulfo group, each of which is protected by a photolytic protective group on a top-most surface of a... Agent: Fitzpatrick Cella Harper & Scinto

20070212795 - Device and method for improving interface adhesion in thin film structures: A device and method for improving adhesion for thin film layers includes applying a diblock copolymer on a surface where adhesion to subsequent layers is needed and curing the diblock copolymer. Pores are formed in the diblock copolymer by treating the diblock copolymer with a solvent. The surface is etched... Agent: Keusey, Tutunjian & Bitetto, P.C.

20070212798 - Die loss estimation using universal in-line metric (uilm): A system predicts die loss for a semiconductor wafer by using a method referred to as universal in-line metric (UILM). A wafer inspection tool detects defects on the wafer and identifies the defects by various defect types. The UILM method applies to various ways of classification of the defect types... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070212799 - Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage: Disclosed is a method for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The method/circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within... Agent: Ibm Microelectronics Intellectual Property Law

20070212800 - Methods for detecting charge effects during semiconductor processing: A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A charge pump current can be used to detect the charging effect during various processing... Agent: Baker & Mckenzie LLP Patent Department

20070212801 - System for adjusting manufacturing equipment, method for adjusting manufacturing equipment, and method for manufacturing semiconductor device: A system for adjusting a manufacturing equipment includes a measurement equipment configured to measure a plurality of sizes of portions of a product on a plane, an approximation module configured to approximate a planar distribution of the plurality of sizes by an orthogonal polynomial. as a function of coordinates on... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070212803 - Iii-v group nitride system semiconductor self-standing substrate, method of making the same and iii-v group nitride system semiconductor wafer: A III-V group nitride system semiconductor self-standing substrate has: a first III-V group nitride system semiconductor crystal layer that has a region with dislocation lines gathered densely, the dislocation lines being gathered substantially perpendicular to a surface of the substrate, and a region with dislocation lines gathered thinly; and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070212802 - Method for manufacturing light emitting diode package: A method of manufacturing an LED package with improved light extraction efficiency. A light-emitting resin part of an LED package is formed and laser beam is irradiated on a surface of the light-transmitting resin part of the LED package to roughen the surface thereof.... Agent: Mcdermott Will & Emery LLP

20070212804 - Solid-state imaging device and method for manufacturing thereof: A solid-state imaging device is formed by laminating a photodiode on a surface of a Si semiconductor substrate, a gate electrode layer to read out or transfer electric charge stored on the photodiode, a first inter-layer insulating film made of SiO2, a first metallic wiring layer, a second inter-layer insulating... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070212805 - Thin-film microelectromechanical device fabrication process: Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, semiconductor mechanical devices. Processing is laser performed on selected semiconductor material whose internal crystalline structure becomes appropriately changed to establish the desired mechanical properties for a created device.... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070212807 - Method for producing an organic thin film transistor and an organic thin film transistor produced by the method: A method for producing an organic thin film transistor having, on a substrate, a source electrode, a gate electrode, a drain electrode, an insulating layer and an organic semiconductor layer. The method has a step of forming the source electrode and the drain electrode such that one of the source... Agent: Brinks Hofer Gilson & Lione

20070212808 - Method of selective removal of organophosphonic acid molecules from their self-assembled monolayer on si substrates: A scanning probe based method to selectively remove self-assembled organic molecules from their self-assembled monolayer (SAM) prepared on a conducting/semiconducting substrate having a hydrophilic surface. This technique involves the use of a conductive probe tip scanning a SAM with a thickness of not more than a few nanometers under an... Agent: Ralph A. Dowell Of Dowell & Dowell P.C.

20070212809 - Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.... Agent: Sughrue Mion, PLLC

20070212811 - Low temperature cvd process with selected stress of the cvd layer on cmos devices: Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out low temperature CVD steps with... Agent: Law Office Of Robert M. Wallace

20070212810 - Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells: Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers.... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070212813 - Perforated embedded plane package and method: Methods and apparatus are provided for an electronic assembly (57, 59, 67), comprising: providing multiple electronic devices (32) with primary faces (33) having electrical contacts (39), opposed rear faces (35) and edges (34) therebetween. The devices are mounted primary faces down on a temporary support (7) in openings (48) in... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070212812 - Wafer level chip scale package system with a thermal dissipation structure: A wafer level chip scale package system is provided forming a wafer having an interconnect provided on an active side, forming a thermal sheet having a first thermal interface material layer and a thermal conductive layer, and attaching the thermal sheet on a non-active side of the wafer.... Agent: Ishimaru & Zahrt LLP

20070212814 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes preparing a wiring board including a base board having a first surface and a second surface, a wiring pattern having a plurality of electrical connectors and formed on the first surface, a first resist layer having a first opening for exposing the... Agent: Harness, Dickey & Pierce, P.L.C

20070212815 - Sealed three dimensional metal bonded integrated circuits: The invention provides a sealing layer that seals metal bonding structures between three dimensional bonded integrated circuits from a surrounding environment. A material may be applied to fill a volume between the bonded integrated circuits or seal the perimeter of the volume between the bonded integrated circuits. The material may... Agent: Michael A. Bernadicou Blakely, Sokoloff, Taylor & Zafman LLP

20070212816 - Substrate processing system: A substrate processing system which enables scratching of the rear surface of a substrate to be prevented. An etching apparatus carries out plasma etching processing on a substrate. The etching apparatus having therein an electrostatic chuck that electrostatically attracts the substrate. The electrostatic chuck contacts a rear surface of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070212817 - Method and process of manufacturing robust high temperature solder joints: The principles described herein relate to methods for soldering electrode terminals, pins or lead-frames of commercial electric components for high temperature reliability. In one embodiment, prior to soldering the electric components, a pre-plated solder layer is removed from the lead frame or pins, and nickel and/or gold films are formed... Agent: Schlumberger K.k.

20070212818 - Multi-layer device: A multi-layer device is provided for connecting to an electrical unit enclosed within the multi-layer device. A first wafer has a first outer terminal and a second outer terminal with etch pits. A first insulator has a first surface bonded to the first wafer and a first inner terminal located... Agent: Heller Ehrman LLP

20070212820 - Method and device including reworkable alpha particle barrier and corrosion barrier: A method and device comprising an easily reworkable alpha particle barrier is provided. The easily reworkable alpha particle barrier is applied in the space between the surface of the chip and the surface of the substrate, and reduces soft error rate (SER). Further, the easily reworkable alpha particle barrier material... Agent: Greenblum & Bernstein, P.L.C

20070212819 - Silicone adhesive: The present invention provides a silicone adhesive not reducing wire bondability and not reducing the adhesion of the surface of a semiconductor pellet and a lead frame to sealing resin. Specifically, it provides a silicone adhesive for bonding a semiconductor pellet to a member for mounting the pellet, which comprises... Agent: Flynn Thiel Boutell & Tanis, P.C.

20070212821 - Method for manufacturing semiconductor device: A manufacturing method is for providing an excellent wire bonding property in the manufacturing of a semiconductor device using an organic resin wiring substrate. In the manufacturing of the semiconductor device, a thermosonic wire bonding apparatus is used when the electrodes of a semiconductor element fixed to the principal surface... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070212822 - Method for fabricating a semiconductor package: A method for fabricating an IC package that includes depositing conductive adhesive bodies on the leads, and then adhering the electrodes of an IC device to the so disposed conductive adhesive bodies.... Agent: Ostrolenk Faber Gerb & Soffen

20070212823 - Method for integrating dmos into sub-micron cmos process: This invention is forming the DMOS channel after CMOS active layer before gate poly layer to make the modular DMOS process step easily adding into the sub-micron CMOS or BiCMOS process. And DMOS source is formed by implant which is separated by a spacer self-aligned to the window for DMOS... Agent: Birch Stewart Kolasch & Birch

20070212824 - Method for manufacturing thin film transistor display array with dual-layer metal line: A method for manufacturing a thin film transistor (“TFT”) array includes providing a substrate, a patterned first metal layer on the substrate including a plurality of first conductive lines and a plurality of second conductive lines disposed orthogonal to the first conductive lines, an insulating layer over the patterned first... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070212826 - Laser processing method and laser processing apparatus: A display device is manufactured by forming a semiconductor film over a substrate and irradiating the film with laser light. The laser light is generated from an oscillator, passes through an attenuator that includes a filter, and passes through an optical system after passing through the attenuator. A first region... Agent: Fish & Richardson P.C.

20070212825 - Thin film semiconductor device and method for manufacturing same: A thin film semiconductor device is provided that includes a semiconductor thin film and a gate electrode. The semiconductor thin film has an active region turned into a polycrystalline region through irradiation with an energy beam. The gate electrode is provided to traverse the active region. In a channel part... Agent: Bell, Boyd & Lloyd, LLP

20070212828 - Method for manufacturing semiconductor device: An object of the present invention is to provide a method for manufacturing a semiconductor device of which manufacturing process is simplified by improving usage rate of a material. A method for manufacturing a semiconductor device of the invention comprises the steps of: forming gate electrodes with a droplet discharge... Agent: Eric Robinson

20070212827 - Method of forming a silicon layer and method of manufacturing a display substrate by using the same: A method of manufacturing a silicon layer includes pretreating a surface of a silicon nitride layer formed on a substrate through a plasma enhanced chemical vapor deposition method using a first reaction gas including at least one of silicone tetrafluoride (SiF4) gas, a nitrogen trifluoride (NF3) gas, SiF4—H2 gas and... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070212829 - Method of manufacturing a semiconductor device: A method of manufacturing an MIS semiconductor device includes forming a high dielectric film on a main surface of a semiconductor substrate, forming a silicon film on the high dielectric film, annealing the semiconductor substrate after the silicon film is formed, processing the high dielectric film and the silicon film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070212830 - Trench memory with monolithic conducting material and methods for forming same: A trench memory filled with a monolithic conducting material and methods for forming the same are disclosed. The trench memory includes a trench that has only a single, monolithic conducting material within the trench. The method includes forming a trench with a collar in the trench; forming a node dielectric... Agent: Hoffman, Warnick & D'alessandro LLC

20070212831 - Method for manufacturing semiconductor device having plural electroconductive plugs: The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the cell contact 9 is formed of the material, which is same as the material of cell contact 9. In... Agent: Young & Thompson

20070212832 - Method for making a multibit transistor: A method for making a transistor (301) is provided. In accordance with the method, a semiconductor substrate (201, 203) is provided, and a gate stack is formed on the substrate. The gate stack comprises first (205), second (207), and third (209) dielectric layers, wherein the second dielectric layer is disposed... Agent: Fortkort & Houston P.C.

20070212833 - Methods for making a nonvolatile memory device comprising a shunt silicon layer: A nitride read only memory comprises a selectively grown, epitaxial, shunt silicon layer (shunt layer) that reduces the bit line sheet resistance and increases bit line mobility. The shunt layer can be grown by a in situ, P-doped deposit at high temperature. A bit line interface without native oxide and... Agent: Baker & Mckenzie LLP Patent Department

20070212834 - Multiple-gate device with floating back gate: Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070212835 - Non-volatile semiconductor memory device and method of manufacturing the same: A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070212836 - Fabricating method of single electron transistor (set) by employing nano-lithographical technology in the semiconductor process: A fabricating method of Single Electron Transistor includes processing steps as follows: first, deposit the sealing material of gas molecule or atom state on the top-opening of the nano cylindrical pore, which having formed on the substrate, so that the diameter of said top-opening gradually reduce to become a reduced... Agent: Bacon & Thomas, PLLC

20070212837 - Method and apparatus of fabricating semiconductor device: An object is to provide a semiconductor device in which uniform properties are intended and high yields are provided. Process steps are provided in which variations are adjusted in doping and annealing process steps that are subsequent process steps so as to cancel in-plane variations in a substrate caused by... Agent: Mcdermott Will & Emery LLP

20070212838 - Methods of performance improvement of hvmos devices: Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed within the well regions. First and second back gate regions are formed... Agent: Texas Instruments Incorporated

20070212839 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate. A plurality of gate structures are formed on the gate dielectric layer. Each of the gate structures is composed of a stacked structure and a spacer. Each stacked structure includes a gate... Agent: Jianq Chyun Intellectual Property Office

20070212840 - Method for forming a self-aligned twin well region with simplified processing: A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a... Agent: Sawyer Law Group LLP

20070212841 - Structure and method for a sidewall sonos memory device: A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least... Agent: Slater & Matsil, L.L.P.

20070212842 - Manufacturing method of high-voltage mos transistor: In the manufacturing method of a high-voltage MOS, a structural body is prepared. The structural body includes a semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate via a gate insulation film, and first conductive layers of a second conductivity type extending from the... Agent: Rabin & Berdo, PC

20070212844 - Method for making a capacitor: A method for making a capacitor includes: forming an anode that has a main body and a lead; mounting securely an insulator washer on the lead such that the insulator washer is spaced apart from an upper end of the main body of the anode, the insulator washer dividing the... Agent: Rosenberg, Klein & Lee

20070212843 - Semiconductor apparatus and method of manufacturing said semiconductor apparatus: A semiconductor apparatus is proposed which is provided with a crystalline dielectric film having a perovskite structure, between electrodes. The semiconductor apparatus includes at least a discontinuous interface through which crystallinity becomes discontinuous, in a columnar crystal portion of the crystalline dielectric film.... Agent: Rader Fishman & Grauer PLLC

20070212845 - Mim capacitor structure and fabricating method thereof: A method for fabricating an MIM capacitor is disclosed. First, a substrate is provided having a first dielectric layer thereon. Next at least one first damascene conductor is formed within the first dielectric layer, and a second dielectric layer with a capacitor opening is formed on the first dielectric layer,... Agent: North America Intellectual Property Corporation

20070212846 - Substrate processing apparatus, method for examining substrate processing conditions, and storage medium: A substrate processing apparatus includes a substrate processing unit for performing a process on substrates; a recipe protection unit for prohibiting processing conditions for the process from being changed while the process is being performed on a specific number of substrates; a protection cancellation unit for canceling a prohibition of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070212847 - Multi-step anneal of thin films for film densification and improved gap-fill: A method of annealing a substrate that has a trench containing a dielectric material formed on a silicon nitride layer between the dielectric material and the substrate, where the method includes annealing the substrate at a first temperature of about 800° C. or more in a first atmosphere comprising an... Agent: Townsend And Townsend And Crew LLP / Amat

20070212849 - Method of fabricating a groove-like structure in a semiconductor device: The present invention relates to a method of fabricating a groove-like structure in a semiconductor device including etching a trench in a substrate, filling the trench with a spin-on-glass liquid forming a spin-on-glass liquid layer containing a solvent, baking the spin-on-glass liquid layer in order to remove the solvent and... Agent: Slater & Matsil LLP

20070212848 - Method of making an isolation trench and resulting isolation trench: A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on... Agent: Dickstein Shapiro LLP

20070212850 - Gap-fill depositions in the formation of silicon containing dielectric materials: A chemical vapor deposition method for forming a dielectric material in a trench formed on a substrate, where the method includes the steps of generating water vapor by contacting hydrogen gas and oxygen gas with a water vapor generation catalyst, and providing the water vapor to the process chamber. The... Agent: Townsend And Townsend And Crew LLP / Amat

20070212851 - In-place bonding of microstructures: A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the... Agent: Scully, Scott, Murphy & Presser, P.C.

20070212852 - Method of fabricating a thin film: A method of fabricating a thin film is disclosed. The method comprises: implanting ions by bombarding a face of a substrate comprising a semiconductor material to form a concentrated layer of the implanted ions at a predetermined mean depth in the substrate, the concentrated layer and the face of the... Agent: Winston & Strawn LLP Patent Department

20070212853 - Semiconductor device and method of manufacturing the same: A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device.... Agent: Fish & Richardson P.C.

20070212854 - Method of separating semiconductor dies: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed... Agent: Patterson & Sheridan, L.L.P.

20070212855 - Metal-induced crystallization of amorphous silicon in thin film transistors: The invention provides a method for forming thin film transistors including a polycrystalline semiconducting film. The method comprises depositing a first layer of amorphous semiconducting thin film on to a substrate; depositing a second layer of thin film on to the first layer of amorphous semiconducting thin film; patterning the... Agent: Cooper & Dunham, LLP

20070212856 - Determination of lithography misalignment based on curvature and stress mapping data of substrates: Provided are methods to be carried out prior to, while, and/or after performing a photolithographic process to a wafer that involve wafer misalignment assessment. The method involves obtaining curvature and/or deformation information of a surface of the wafer over a plurality of locations so as to obtain a curvature map... Agent: Allston L. Jones Peters Verny, LLP

20070212857 - Integrated circuit with bulk and soi devices connected with an epitaxial region: An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or... Agent: Whitham Curtis, & Christofferson, P.C.

20070212858 - Method for crystallizing a semiconductor thin film: A method for crystallizing a semiconductor thin film is provided. The method includes continuously irradiating an energy beam on a semiconductor thin film while scanning at a given speed. The energy beam is scanned in parallel lines while keeping pitches of not larger than an irradiation radius of the energy... Agent: Bell, Boyd & Lloyd, LLP

20070212859 - Method of thermal processing structures formed on a substrate: The present invention generally describes one ore more methods that are used to perform an annealing process on desired regions of a substrate. In one embodiment, an amount of energy is delivered to the surface of the substrate to preferentially melt certain desired regions of the substrate to remove unwanted... Agent: Patterson & Sheridan, LLP

20070212860 - Method for crystallizing a semiconductor thin film: A method for crystallizing a semiconductor thin film is provided. The method includes continuously irradiating an energy beam on a semiconductor thin film while scanning at a given speed, wherein the semiconductor thin film is completely melted and the irradiation conditions of the energy beam are so set that the... Agent: Bell, Boyd & Lloyd, LLP

20070212861 - Laser surface annealing of antimony doped amorphized semiconductor region: A sheet resistance stabilized recrystallized antimony doped region may be formed within a semiconductor substrate by annealing a corresponding antimony doped amorphized region at a temperature from about 1050° C. to about 1400° C. for a time period from about 0.1 to about 10 milliseconds. Preferably, a laser surface treatment... Agent: Scully Scott Murphy & Presser, PC

20070212862 - Process for forming schottky rectifier with ptni silicide schottky barrier: A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop... Agent: Vishay/siliconix C/o Murabito, Hao & Barnes LLP

20070212863 - Double exposure double resist layer process for forming gate patterns: A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a... Agent: International Business Machines Corporation Dept. 18g

20070212864 - Manufacturing a semiconductive device using a controlled atomic layer removal process: A method for manufacturing a semiconductive device comprising forming a mask for a semiconductive device structure over a layer of a semiconductor substrate and partially etching the layer to form lateral and vertical surfaces. Thicknesses of one to several atomic diameters of atoms that comprise said layer are removed from... Agent: Texas Instruments Incorporated

20070212866 - Method of manufacturing semiconductor device: In the present invention, a connection plug region where a connection plug is disposed has a long shape comprising a first length direction and a first width direction, an open region that is exposed by an open portion disposed in an insulation layer on the connection plug has a long... Agent: Volentine & Whitt PLLC

20070212865 - Method for planarizing vias formed in a substrate: A method for constructing an electronic assembly is provided. A substrate having first and second opposing surfaces and an integrated circuit formed therein is provided. A protective layer is formed over the first surface of the substrate. A via opening is formed through the protective layer and into the first... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070212867 - Method and structure for improving bonding reliability in bond pads: A method for fabricating a bond pad structure in an integrated circuit is provided. In one embodiment, a bond pad is formed above a substrate. A first passivation layer is deposited above the bond pad, the first passivation having an opening therein exposing a portion of the bond pad. A... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070212868 - Method, system, and apparatus for gravity assisted chip attachment: A method, system, and apparatus, the apparatus including a metal layer on silicon, photo-resist material disposed on the metal layer, a bump pad reservoir adjacent to the metal layer, a quantity of interconnect metal disposed in the bump pad reservoir, and a resist opening in resist material disposed on a... Agent: Buckley, Maschoff & Talwalkar LLC

20070212869 - Wire bonding method for preventing polymer cracking: This invention provides a wire bonding method, comprising providing an integrated circuit (IC) die having thereon a passivation layer and a plurality of first bonding pads exposed by respective openings in the passivation layer; forming a polymer layer on the passivation layer; forming an adhesive/barrier layer on the polymer layer;... Agent: North America Intellectual Property Corporation

20070212871 - Method of manufacturing interconnect substrate: A method of manufacturing an interconnect substrate by electroless plating, including: (a) forming a catalyst layer with a specific pattern on a substrate; (b) immersing the substrate in a first electroless plating solution including a first metal to deposit the first metal on the catalyst layer to form a first... Agent: Harness, Dickey & Pierce, P.L.C

20070212870 - Interconnect structure with a barrier-redundancy feature: An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect... Agent: Scully Scott Murphy & Presser, PC

20070212872 - Single mask process for variable thickness dual damascene structures, other grey-masking processes, and structures made using grey-masking: By using a multiple grey tone mask with at least two greys in semiconductor manufacture, multiple wiring thicknesses can now be made in a single level where previously only one wiring thickness could be provided. For example, power and signal wires of different thicknesses in a single layer can be... Agent: Whitham, Curtis, & Christofferson, P.C.,

20070212873 - Guard ring for improved matching: A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at... Agent: Hitt Gaines, PC Lsi Corporation

20070212876 - Method for manufacturing wiring substrate: A method for manufacturing a wiring substrate by an electroless plating method that precipitates metal without using a plating resist is provided. The method includes the steps of (a) providing a catalyst layer having a predetermined pattern on a substrate; (b) dipping the substrate in an electroless plating solution to... Agent: Harness, Dickey & Pierce, P.L.C

20070212874 - Method for filling shallow isolation trenches and other recesses during the formation of a semiconductor device and electronic systems including the semiconductor device: A method for filling a shallow isolation trench comprises partially filling the trench with a first material, then filling the trench the rest of the way with a second material. For the first material, a substance which flows more easily into narrow, deep trenches is selected, while for the second... Agent: Micron Technology, Inc.

20070212875 - Method for manufacturing thin film integrated circuit: An object of the present invention is to prevent a thin film integrate circuit from peeling off during the process of transferring to a base material. By a manufacturing method of the present invention, a separation layer is formed selectively on a surface of a substrate; thus, a first region... Agent: Fish & Richardson P.C.

20070212877 - Method of forming a dual damascene structure: An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070212878 - Variable width conductive lines having substantially constant impedance: A method of fabricating a conductive line provides a substrate having a blanket layer of conductive material disposed thereon, a removing of a first portion of the blanket layer of conductive material to form one or more gaps that define a first line, the gaps adjacent to the first line,... Agent: Marger Johnson & Mccollom, P.C.

20070212879 - Formation of lattice-tuning semiconductor substrates: A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining striped regions (16) on the surface of a silicon substrate (10) at which dislocations can preferentially form, growing a first SiGe layer (18) on the strips such that first dislocations (20) extend preferentially across the first SiGe... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20070212880 - Semiconductor device with charge storage pattern and method for fabricating the same: A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be... Agent: Marger Johnson & Mccollom, P.C.

20070212882 - Substrate polishing method and method of manufacturing semiconductor device: The substrate polishing method of the present invention can be used, in a substrate polishing apparatus having multiple carriers for one polishing pad, for determining a polishing time necessary to obtain a specific amount of polishing in polishing substrates using only some of the carriers among multiple carriers. In the... Agent: Mcdermott Will & Emery LLP

20070212881 - Chemical mechanical polishing apparatus and operating method thereof: The invention is directed to a chemical mechanical polishing process. The chemical mechanical polishing process comprises steps of providing a wafer disposed at a wafer handling region of a chemical mechanical polishing apparatus and then moving the wafer into a buffer region of the chemical mechanical polishing apparatus. A first... Agent: Jianq Chyun Intellectual Property Office

20070212884 - Coating and developing apparatus, coating film forming method, and storage medium storing program for performing the method: Disclosed is a technique for preventing a water-repellent protective film formed on a resist film from peeling off during immersion exposure. A resist film is formed on the front surface of a substrate and then the peripheral edge portion of the resist film is removed. Before forming a water-repellent protective... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070212885 - Method and composition for plasma etching of a self-aligned contact opening: A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer with at least one fluorocarbon and ammonia.... Agent: Dickstein Shapiro LLP

20070212883 - Method for forming surface graft, method for forming conductive film, method for forming method pattern, method for forming multilayer wiring board, surface graft material, and conductive material: The present invention provides a method for forming a surface graft, comprising the process of applying energy to the surface of a substrate containing polyimide having a polymerization initiating moiety in the skeleton thereof, to generate active points on the surface of the substrate and to generate a graft polymer... Agent: Sughrue Mion, PLLC

20070212886 - Organosilane polymers, hardmask compositions including the same and methods of producing semiconductor devices using organosilane hardmask compositions: e

20070212887 - Plasma etching method, plasma etching apparatus, control program and computer-readable storage medium: A plasma etching method includes the step of performing a plasma etching on a silicon-containing dielectric layer formed on a substrate to be processed by using a plasma, while using an organic layer as a mask. In addition, the plasma is generated from a processing gas at least including a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070212888 - Silicon substrate etching method: Silicon substrate etching methods to keep surface unevenness of a structured surface formed by etching to within a fixed value. After an etching mask is formed on its surface, a silicon substrate S is mounted on a base 3 in an etching device 1. An etching gas (SF6) and a... Agent: Judge & MurakamiIPAssociates

20070212889 - Trim process for critical dimension control for integrated circuits: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist... Agent: Knobbe Martens Olson & Bear LLP

20070212890 - Manufacturing method for ink jet recording head chip, and manufacturing method for ink jet recording head: A manufacturing method for a substrate for an ink jet head, including formation of an ink supply port in a silicon substrate, the method includes a step of forming, on one side of the substrate, an etching mask layer having an opening at a position corresponding ink supply port; a... Agent: Fitzpatrick Cella Harper & Scinto

20070212891 - Manufacturing method of substrate for ink jet head and manufacturing method of ink jet recording head: The present invention provides a manufacturing method of a substrate for an ink jet head including forming an ink supply opening to a silicon substrate, including (a) forming, at the back surface of the silicon substrate, an etching mask layer, which has an opening that is asymmetric with a center... Agent: Fitzpatrick Cella Harper & Scinto

20070212892 - Method of forming semiconductor device structures using hardmasks: A first hardmask layer is provided over a substrate, and a second hardmask layer is provided over the first hardmask layer. The second hardmask layer is patterned to form a second hardmask structure having sidewalls. A sacrificial layer of a sacrificial material is conformally deposited such that the deposited sacrificial... Agent: Edell, Shapiro & Finnan, LLC

20070212895 - Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a... Agent: Patterson & Sheridan, LLP

20070212898 - Method for depositing film and method for manufacturing semiconductor device: A method for depositing a film includes: (a) processing a wafer, including forming a high dielectric constant film on a first wafer; and achieving nitridation of the high dielectric constant film formed on the first wafer; and (b) performing coating process including forming a high dielectric constant film on a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070212894 - Method of manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided, which includes feeding a coating liquid comprising a silicon-containing compound dissolved in a solvent onto a semiconductor substrate, revolving the semiconductor substrate to form a coated film containing the silicon-containing compound, feeding a rinsing liquid at least partially comprising α-pinene onto... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070212897 - High-temperature attachment of organic molecules to substrates: This invention provides a new procedure for attaching molecules to semiconductor surfaces, in particular silicon. The molecules, which include, but are not limited to porphyrins and ferrocenes, have been previously shown to be attractive candidates for molecular-based information storage. The new attachment procedure is simple, can be completed in short... Agent: Beyer Weaver LLP

20070212896 - Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a... Agent: Patterson & Sheridan, LLP

20070212893 - System and method for sputtering a tensile silicon nitride film: There is provided a system and method for sputtering a tensile silicon nitride film. More specifically, in one embodiment, there is provided a method comprising introducing nitrogen gas into a process chamber, wherein the process chamber includes a target comprising silicon, placing the process chamber into a transition region between... Agent: Fletcher Yoder (micron Technology, Inc.)

20070212899 - Photosensitive resin composition and method for manufacturing semiconductor apparatus using the same: A photosensitive resin composition comprises: a polybenzoxazole precursor (A); a naphthoquinone diazide photosensitizer (B); and a specific phenolic hydroxyl group-containing compound (C).... Agent: Sughrue-265550

20070207561 - Inn/tio2 photosensitized electrode: The present invention is a photosensitized electrode which absorbs sun light to obtain pairs of separated electron and hole. The photosensitized electrode is fabricated with simple procedure and has low cost. The electrode has excellent chemical resistance and is fitted to be applied in a solar cell device with enhanced... Agent: Troxell Law Office PLLC

20070207562 - Method of forming a micromachined device using an assisted release: A method of forming a micromachined device embeds a first material within a sacrificial material, and then removes such first material to form a channel through the sacrificial material. The method then directs a sacrificial material removal fluid through the channel. The sacrificial material removal fluid removes at least a... Agent: Bromberg & Sunstein LLP

20070207564 - Method for manufacturing a semiconductor device: A step for etching a wiring-structure layer and the like on a light-receiving part of a light detector and forming an apertured part is simplified. A silicon nitride film 86 is formed on a semiconductor substrate 60 by CVD or the like, and a layered structure 88 that has the... Agent: Oliff & Berridge, PLC

20070207556 - Manufacturing method of non-volatile memory: A nonvolatile memory consisting of a substrate, a dielectric layer, word lines, word gates, conductive spacers, electron trapping layer, insulation layer and buried bit lines is provided. The dielectric layer is on the substrate and has several poly trenches thereon, and the word lines are disposed over the substrate across... Agent: Jianq Chyun Intellectual Property Office

20070207557 - Semiconductor chip mounting substrate, a method of producing the same, and a method of mounting a semiconductor chip: A chip mounting substrate for bonding a semiconductor chip to a substrate, comprises a solder layer on the substrate, the solder layer being connectable to a semiconductor chip, wherein the solder layer comprises a layer including δ-phase crystal grains of an Au—Sn alloy at a surface of the solder layer.... Agent: Crowell & Moring LLP Intellectual Property Group

20070207558 - Integrated circuit memory system with dummy active region: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a... Agent: Ishimaru & Zahrt LLP

20070207559 - Fabrication method of semiconductor integrated circuit device: Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070207560 - Components and methods for use in electro-optic displays: A front plane laminate useful in the manufacture of electro-optic displays comprises, in order, a light-transmissive electrically-conductive layer, a layer of an electro-optic medium in electrical contact with the electrically-conductive layer, an adhesive layer and a release sheet. This front plane laminate can be prepared as a continuous web, cut... Agent: David J Cole E Ink Corporation

20070207563 - Method for fabricating optical sensitive layer of solar cell having silicon quantum dots: A distribution layer of silicon quantum dots are fabricated. After the layer is exposed to sun light for a while, the layer absorbs energy and produces pairs of electron and hole. By limiting the movement of the electrons and their moving directions through the structure obtained, the efficiency of an... Agent: Troxell Law Office PLLC Suite 1404

20070207565 - Processes for forming photovoltaic features: Processes for forming photovoltaic features and in particular photovoltaic conductive features. In one aspect, the process comprises printing a primer material onto a substrate; etching the substrate with the primer material to form an etched substrate; printing a precursor composition onto the etched substrate, wherein the precursor composition comprises at... Agent: Patent Administrator Cabot Corporation

20070207566 - Method of fabricating backside illuminated image sensor: A method for fabricating a back-side illuminated image sensor includes providing a semiconductor substrate having a front surface and back surface, providing a plurality of transistors, metal interconnects, and metal pads on front surface of the substrate, bonding a supporting layer to the front surface of the substrate, thinning-down the... Agent: Haynes And Boone, LLP

20070207567 - Method of base formation in a bicmos process: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a... Agent: Ibm Microelectronics Intellectual Property Law

20070207569 - Biocompatible bonding method and electronics package suitable for implantation: The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain... Agent: Second Sight Medical Products, Inc.

20070207570 - Apparatuses and methods for forming identifying characters on semiconductor device and wafers: An apparatus for forming identifying characters on semiconductor devices includes a laser generation unit, a laser transmission unit, a stage and a control unit. The laser generation unit may generate a laser beam having a pulse duration shorter than a heat diffusion time of a wafer. The laser transmission unit... Agent: Harness, Dickey & Pierce, P.L.C

20070207568 - Sip module with a single sided lid: A single-lid flash memory card and methods of manufacturing same are disclosed. The single-sided lid flash memory card may be formed from a semiconductor package having two or more tapered, stepped or otherwise shaped edges capable of securing a single-sided lid thereon. The taper, step or other shape may be... Agent: Vierra Magen/sandisk Corporation

20070207571 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes: forming a photocatalytic layer and an organic compound layer in contact with the photocatalytic layer over a substrate having a light transmitting property; forming an element forming layer over the substrate having the light transmitting property with the photocatalytic layer and the... Agent: Eric Robinson

20070207572 - Cmos device having different amounts of nitrogen in the nmos gate dielectric layers and pmos gate dielectric layers: The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer... Agent: Texas Instruments Incorporated

20070207573 - Process for growing a dielectric layer on a silicon-containing surface using a mixture of n2o and o3: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O... Agent: Trask Britt, P.C./ Micron Technology

20070207574 - Double gate thin-film transistor and method for forming the same: A double-gate thin-film transistor and a method for forming the same, using low-temperature poly-silicon formed by direct deposition on a substrate so as to simplify the manufacturing process and improve the electrical characteristics. The double-gate thin-film transistor comprises: a first patterned electrode formed on a substrate; a first dielectric layer;... Agent: Birch Stewart Kolasch & Birch

20070207575 - Method of manufacturing a semiconductor device: Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching... Agent: Miles & Stockbridge PC

20070207576 - Method for manufacturing cmos circuits: A method of manufacturing transistors of a first and second type on a substrate includes producing doped semiconductor areas with a first conductivity type in eventual contact areas of a first type of transistors, depositing a first intrinsic semiconductor layer over an entire surface, activating dopants in the semiconductor areas... Agent: Striker, Striker & Stenby

20070207577 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes: (A) a wafer process; and (B) a bias application process after the wafer process. The wafer process includes: (a) forming a n-type well in a p-type semiconductor substrate; (b) forming a p-type well in the n-type well; and (c) forming a transistor... Agent: Sughrue Mion, PLLC

20070207578 - Method of manufacturing semiconductor device with offset sidewall structure: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070207579 - Semiconductor device with capacitor and fuse and its manufacture method: An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor.... Agent: Dickstein Shapiro LLP

20070207580 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive material, the first conductive material contacting... Agent: Townsend And Townsend And Crew, LLP

20070207581 - Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same: In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to... Agent: Miles & Stockbridge PC

20070207582 - Method of forming an mos transistor and structure therefor: In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070207583 - Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions: A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers... Agent: Williams, Morgan & Amerson

20070207584 - Method and apparatus for curing epoxy-based photoresist using a continuously varying temperature profile: A method for curing an epoxy-based photoresist uses a continuously varying temperature profile, to continuously raise the kinetic energy of the monomers involved in the curing process, allowing them to cross-link. By using the continuously varying temperature profile, the maximum temperature to achieve a more completely cured film is reduced,... Agent: Jaquelin K. Spong

20070207585 - Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication: A method for fabricating a BICMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type comprises the steps of depositing a dielectric layer (24) over a semiconductor layer (14), depositing a gate conductor layer (26) over the dielectric layer (24), defining base... Agent: Texas Instruments Incorporated

20070207586 - Methods of fabricating ferroelectric capacitors having oxidation barrier conductive layers and lower electrodes disposed in trenches defined by supporting insulating layers: Ferroelectric capacitors are provided that include an integrated circuit substrate and a supporting insulation layer on the integrated circuit substrate having a face and a trench in the face. An oxidation barrier conductive layer is provided in the trench and a lower electrode is provided on the oxidation barrier conductive... Agent: Myers Bigel Sibley & Sajovec

20070207587 - Integrated circuit devices including a capacitor and methods of forming the same: Methods of forming a capacitor of an integrated circuit device include forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode. A supporting conductor is formed coupling the lower electrode to the contact plug after forming... Agent: Myers Bigel Sibley & Sajovec

20070207588 - Structures and methods for enhancing capacitors in integrated circuits: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070207589 - Registration mark within an overlap of dopant regions: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO... Agent: Schneck & Schneck

20070207590 - Manufacturing method of semiconductor device: According to an aspect of the invention, there is provided a manufacturing method of a semiconductor device including forming an isolation trench in a semiconductor substrate, filling an insulating film in the isolation trench, and annealing the filled insulating film in a vacuum or an inert gas atmosphere at a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070207591 - Technique for efficiently and dynamically maintaining bidirectional forwarding detection on a bundle of links: A technique efficiently and dynamically maintains bidirectional forwarding detection (BFD) on a bundle of links in a computer network. According to the novel technique, one or more “standby” BFD sessions may be established on one or more corresponding line cards (LCs), the LCs having one or more links of the... Agent: Cesari And Mckenna, LLP

20070207593 - Glass-based soi structures: Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20) composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic... Agent: Corning Incorporated

20070207592 - Wafer bonding of damascene-patterned metal/adhesive redistribution layers: Wafer bonding of patterned metal/adhesive layers, and related components, processes, systems and methods are disclosed.... Agent: Fish & Richardson PC

20070207594 - Chip and method for dicing wafer into chips: A method for dicing a wafer including first and second layers is provided. A front surface of the first layer contacts a backside surface of the second layer. The method includes: forming a sealing film on the second layer; cutting the first layer from a backside surface along with a... Agent: Posz Law Group, PLC

20070207595 - Method for producing silicon wafer: A method for producing a silicon wafer, comprising performing an activation of metallic impurities by irradiating laser light on the metallic impurities constituting contaminants in the silicon wafer, changing the electric charge of the contaminants, and activating the contaminants to a state such that the contaminants easily react with oxygen... Agent: Kolisch Hartwell, P.C.

20070207596 - Selective epitaxy process with alternating gas supply: In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is... Agent: Patterson & Sheridan, LLP

20070207597 - Semiconductor device and method of manufacturing the semiconductor device: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to... Agent: Rossi, Kimms & Mcdowell LLP.

20070207598 - Method for producing a substrate by germanium condensation: The method for producing a substrate comprising a silicon and germanium compound of Si1-XfGeXf type on insulator, with Xf comprised between a first value that is not zero and 1, comprises formation of a layer of silicon and germanium of Si1-XiGeXi type, with Xi strictly comprised between 0 and Xf,... Agent: Oliff & Berridge, PLC

20070207599 - Image sensors for reducing dark current and methods of manufacturing the same: An image sensor includes a substrate region of a first conductivity type, a photodiode region of a second conductivity type located in the substrate, a hole accumulated device (HAD) region of the first conductivity type located at a surface of the substrate and over the photodiode region, and a transfer... Agent: Volentine & Whitt PLLC

20070207600 - Lateral double-diffused mosfet (ldmos) transistor and a method of fabricating the same: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.... Agent: Fish & Richardson P.C.

20070207601 - Exposure apparatus: In a stage member for use in an exposure apparatus, a honeycomb structural body has walls that are extended in a direction perpendicular to a longitudinal direction of the stage member and that surround square shaped prismatic spaces, so as to accomplish a high resistance and a high resonant frequency... Agent: Foley And Lardner LLP Suite 500

20070207602 - Mos transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufacture: A method for forming a self-aligned contact between two MOS transistors is described. The method supports the use of low-resistivity silicides for the formation of contacts in nanometer applications that employ polycide techniques. Silicon nitride and photoresist material act as dual masks in the formation of the self-aligned contact.... Agent: Stout, Uxa, Buyan & Mullins LLP

20070207603 - Metal gate with zirconium: A gate electrode (202) for a transistor including a metal gate structure (207) containing zirconium and a polycrystalline silicon cap (209) located there over. The metal gate structure (207) is located over a gate dielectric (205). The zirconium inhibits diffusion of silicon from the cap to the metal gate structure... Agent: Freescale Semiconductor, Inc. Law Department

20070207604 - Wiring paterns formed by selective metal plating: Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070207606 - Method for removing residual flux: A method for removing residual flux applied to a wafer process is disclosed by the present invention, the method comprises the steps of: providing a wafer; forming a plurality of bumps on the surface of the wafer; coating flux on the surfaces of the bumps; reflowing the bumps; immersing the... Agent: Birch Stewart Kolasch & Birch

20070207607 - Ball grid array substrate having window and method of fabricating same: Disclosed is a ball grid array substrate having a window formed on a core material instead of a thin core material, and wherein a semiconductor chip is mounted thereon, thereby reducing the thickness of a package, and a method of fabricating the same. The ball grid array substrate comprises a... Agent: Darby & Darby P.C.

20070207605 - Method for forming reinforced interconnects on a substrate: A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.... Agent: Freescale Semiconductor, Inc. Law Department

20070207608 - Semiconductor device and manufacturing process thereof: A semiconductor device including a circuit structure and a protective layer is provided. The circuit structure has multiple contacts. The protective layer is located on the circuit structure and has multiple openings and multiple protrusions, wherein the contacts are exposed by the openings and the protrusions are located on the... Agent: J.c. Patents, Inc.

20070207609 - Tungsten plug corrosion prevention method using water: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one... Agent: Eric A. Stephenson Campbell Stephenson Ascolese LLP

20070207610 - Semiconductor device, semiconductor wafer, and methods of producing same device and wafer: A method of forming a multi-layered insulation film includes forming a first insulation layer using a first feed gas, the first insulation layer including methyl silsesquioxane (MSQ), forming a second insulation layer using a second feed gas, the second insulation layer including a polysiloxane compound having an Si—H group such... Agent: Mcginn Intellectual Property Law Group, PLLC

20070207611 - Noble metal precursors for copper barrier and seed layer: A copper interconnect oh a semiconductor substrate comprises a dielectric layer having a trench, a noble metal layer on the dielectric layer within the trench, and a copper interconnect on the noble metal layer. The noble metal layer has a thickness that is between 3 Å and 100 Å and... Agent: Intel Corporation C/o Intellevate, LLC

20070207612 - Selective heating using flash anneal: A copper film is treated by applying light at short wavelengths, e.g., at less than 0.6 μm, to heat the copper film and generate a large temperature gradient from the surface of the copper to the interface between the copper and underlying silicon. As a result, grain growth in the... Agent: Macpherson Kwok Chen & Heid LLP

20070207614 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes: forming a mask layer on a layer that is to be subjected to etching and contains at least one of silicon carbonate, silicon oxide, sapphire, gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum nitride, the mask layer having an opening... Agent: Kratz, Quintos & Hanson, LLP

20070207613 - Methods for selective removal of material from wafer alignment marks: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.... Agent: Trask Britt, P.C./ Micron Technology

20070207615 - Hydrophilicity treatment method of a silicon wafer: In a hydrophilicity treatment method including the step of rotating, on a polishing cloth, a mirror surface of a silicon wafer subjected to mirror-polishing followed by rinsing treatment while the mirror surface is pushed onto the cloth under the application of a small load with the contact of the mirror... Agent: Foley And Lardner LLP Suite 500

20070207616 - Method for assaying copper in silicon wafers: This method for assaying copper in silicon wafers includes the steps of: forming a polysilicon layer on the surface of a p-type silicon wafer having the same characteristics as the silicon wafers being assayed; heat treating the p-type silicon wafer after it has been polished; dissolving the polysilicon layer on... Agent: Kolisch Hartwell, P.C.

20070207617 - Polishing agent: The invention relates to the use of gluconates in the production of semiconductor wafers, preferably in the polishing of the semiconductor wafers during the production process, and to a polishing agent based on an abrasive substance and/or colloid and a mixture of disuccinates or methylglycine diacetic acid (MGDA) and gluconates.... Agent: Connolly Bove Lodge & Hutz, LLP

20070207618 - Dry etching method: The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein the wiring process is performed without causing disconnection or deflection of the wiring. The invention provides a dry etching method for performing a wiring process on a semiconductor... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070207619 - Method of manufacturing self-ordered nanochannel-array and method of manufacturing nanodot using the nanochannel-array: A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina... Agent: Buchanan, Ingersoll & Rooney PC

20070207620 - Method of forming contacts for a memory device: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material,... Agent: Williams, Morgan & Amerson

20070207621 - Method for the production of mos transistors: The invention relates to a method for the production of both MOS transistors with extremely low leakage currents at the pn junctions and logic/switching transistors, whose gates are laterally defined by spacers in a p-substrate or a p-well in an n-substrate. The aim of the invention is to provide a... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070207623 - Method for flattening glass substrate: A method for flattening a glass substrate includes the steps of preparing plural kinds of etching liquids different from one another in an etching rate, preparing the glass substrate, and etching the glass substrate at least one time with each of the etching liquids and executing the etching a plurality... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070207622 - Highly selective doped oxide etchant: Etch solutions for selectively etching doped oxide materials in the presence of silicon nitride, titanium nitride, and silicon materials, and methods utilizing the etch solutions, for example, in the construction of container capacitor constructions are provided. The etch solutions are formulated as a mixture of hydrofluoric acid and an organic... Agent: Whyte Hirschboeck Dudek S.c.

20070207626 - Substrate processing method, semiconductor device and method for fabricating the semiconductor device: A method for processing semiconductor includes: forming a first insulation film containing silicon on a surface of a GaN-base semiconductor layer; and removing the first insulation film formed on the surface of the GaN-base semiconductor layer. The composition ratio of Ga and N on the surface of the GaN-base semiconductor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070207624 - Multiple nitrogen plasma treatments for thin sion dielectrics: A method for the deposition of a dielectric film including forming silicon nitride on the surface of the substrate, oxidizing the silicon nitride on the surface of the substrate, exposing the surface of the substrate to a hydrogen-free nitrogen source, and annealing the substrate. A method for the deposition of... Agent: Patterson & Sheridan, LLP

20070207625 - Semiconductor processing apparatus with multiple exhaust paths: An improved exhaust conductance system for a semiconductor process apparatus includes at least two parallel exhaust paths and a valve apparatus for controlling flow to the exhaust paths. The valve apparatus prevents the flow of process gases through one or more of the exhaust paths but simultaneously allows the flow... Agent: Knobbe, Martens, Olsen & Bear LLP

20070207628 - Method for forming silicon oxynitride materials: Embodiments of the invention provide methods for forming silicon oxynitride materials on a substrate. In one embodiment, a method for forming a dielectric material on a substrate is provided which includes positioning a substrate containing a native oxide surface within a processing system containing a plurality of process chambers, and... Agent: Patterson & Sheridan, LLP

20070207627 - Reducing nitrogen concentration with in-situ steam generation: In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas.... Agent: Macpherson Kwok Chen & Heid LLP

20070207629 - Surface protective film peeling method and surface protective film peeling apparatus: A surface protective film peeling method for peeling off a surface protective film (11) attached on the surface of a wafer (20) is disclosed. The wafer is supported on a movable table (31) with the surface protective film directed up, and an incision (15) is formed at one end (28)... Agent: Christie, Parker & Hale, LLP

20070207630 - Surface treatment method of compound semiconductor substrate, fabrication method of compound semiconductor, compound semiconductor substrate, and semiconductor wafer: A surface treatment method of a compound semiconductor substrate, a fabrication method of a compound semiconductor, a compound semiconductor substrate, and a semiconductor wafer are provided, directed to reducing the impurity concentration at a layer formed on a substrate by reducing the impurity concentration at the surface of the substrate... Agent: Mcdermott Will & Emery LLP