Semiconductor device manufacturing: process inventions 09/07

20070224706 - Method of producing semiconductor device and semiconductor device: In the production of a semiconductor device in which a ferroelectric capacitor is used as a memory, a method of producing the semiconductor device in which the oxidation of a tungsten film embedded in an alignment mark prepared in the form of a groove is prevented includes forming an oxidation-preventing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070224709 - Plasma processing method and apparatus, control program and storage medium: A plasma processing method for performing a plasma process by employing a plasma processing apparatus including a processing chamber for performing the plasma process on a target object, a mounting table for mounting thereon the target object in the processing chamber, a peripheral member disposed around a periphery of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224715 - Nitride semiconductor based light-emitting device and manufacturing method thereof: p

20070224720 - Manufacturing method of suspended microstructure: A manufacturing method of a suspended microstructure includes the steps of providing a substrate having a surface; forming a first depositing layer over a part of the surface; forming a second depositing layer over the first depositing layer and another part of the surface wherein an adhesion between the first... Agent: Birch Stewart Kolasch & Birch

20070224707 - Magnetic random access memory, magnetic random access memory manufacturing method, and magnetic random access memory write method: A magnetic random access memory includes first and second write wirings, the second write wiring having first and second crossing angles formed by crossing the first write wiring, a first magnetoresistive element having a first axis of easy magnetization directed to a side of the first crossing angle and having... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224708 - Mass pulse sensor and process-gas system and method: An improved valve device, a valved process-gas apparatus, and a method for confirming operations in a gas-process system are disclosed. The valve device includes an electronically controlled valve designed to cycle between closed and open conditions, with closed-to-open and open-to-closed response times less than about 250 ms, to control the... Agent: Perkins Coie LLP

20070224710 - Methods to shape the electric field in electron devices, passivate dislocations and point defects, and enhance the luminescence efficiency of optical devices: A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This... Agent: Gates & Cooper LLP Howard Hughes Center

20070224711 - Doping apparatus, doping method, and method for fabricating thin film transistor: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In... Agent: Nixon Peabody, LLP

20070224712 - Method of monitoring a semiconductor processing system using a wireless sensor network: A method and system for non-invasive sensing and monitoring of a processing system employed in semiconductor manufacturing. The method allows for detecting and diagnosing drift and failures in the processing system and taking the appropriate correcting measures. The method includes positioning at least one non-invasive sensor on an outer surface... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070224714 - Method of fabricating light emitting device and thus-fabricated light emitting device: A light emitting device chip is obtained by dicing a light emitting device wafer having a light emitting layer section 24 based on a double heterostructure in which a first-conductivity-type cladding layer 6, an active layer 5 and an second-conductivity-type cladding layer 4, each of which being composed of a... Agent: Snider & Associates

20070224713 - Method of manufacturing display device using led chips: A method for manufacturing a display device using light emitting diode chips contemplates manufacturing a plurality of light emitting diode (LED) chips using a porous template; forming a plurality of first electrodes on a substrate; attaching the LED chips to pixel sites on the first electrodes using fluidic self assembly... Agent: Robert E. Bushnell

20070224716 - Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension: Semiconductor light emitting devices are fabricated by placing a suspension including phosphor particles suspended in solvent on at least a portion of a light emitting surface of a semiconductor light emitting element, and evaporating at least some of the solvent to cause the phosphor particles to deposit on at least... Agent: Koppel, Patrick & Heybl

20070224717 - Apparatus and method for manufacturing a display device substrate: An apparatus and method for manufacturing a display device substrate are provided. In one embodiment, the apparatus comprises a clamp for clamping an edge of a plastic substrate, and a tension member applying tension along a surface of the plastic substrate by interacting with the clamp to strain the plastic... Agent: Macpherson Kwok Chen & Heid LLP

20070224718 - Mems fabrication method: A method for singulating a substrate such as a semiconductor wafer populated with a plurality of MEMS devices. A preferred embodiment of the present invention comprises mounting a glass cover onto the wafer, then orienting the wafer and removably mounting it on an adhesive tape. A partial cut or series... Agent: Texas Instruments Incorporated

20070224719 - Method of manufacturing mems device package: A micro electromechanical system (MEMS) device package and a method of manufacturing the same are provided. The MEMS device package includes: a device substrate with a MEMS active device being formed on the top surface thereof; internal electrode pads, each of which is positioned on the opposite side of the... Agent: Sughrue Mion, PLLC

20070224721 - Interband cascade detectors: A device for detecting radiation, typically in the infrared. Photons are absorbed in an active region of a semiconductor device such that the absorption induces an interband electronic transition and generates photo-excited charge carriers. The charge carriers are coupled into a carrier transport region having multiple quantum wells and characterized... Agent: Bromberg & Sunstein LLP

20070224722 - Indium features on multi-contact chips: A device comprising a pixilated semiconductor detector or VLSI chip having plurality of individual indium bumps arrayed on a surface of the detector, wherein the indium bumps are in electrical contact with the surface and are situated in defined locations on the surface is provided. Additionally, a hybrid detector comprising... Agent: Fish & Richardson, PC

20070224723 - Solid state imaging device and method for manufacturing solid state imaging device: A solid state imaging device and a method for manufacturing the same that prevents the reproduction characteristic of an optical image from being affected by diagonal light on a semiconductor substrate surface. A CCD image sensor includes a semiconductor substrate, light receiving pixels formed on the semiconductor substrate, and a... Agent: Sheridan Ross PC

20070224724 - Self aligned memory element and wordline: An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top of the electrode layer of... Agent: Amin, Turocy & Calvin, LLP

20070224725 - Substrate processing method and apparatus fabrication process of a semiconductor device: A method for processing a substrate having an insulation film and a metal layer thereon comprises the steps of supplying a carboxylic acid anhydride to the substrate, and heating the substrate during the step of supplying the carboxylic acid anhydride to the substrate.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224726 - Thin film plate phase change ram circuit and manufacturing method: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070224727 - Methods of forming a diamond micro-channel structure and resulting devices: A diamond micro-channel structure disposed on a die, as well as methods of forming the same, are disclosed. One or more walls of each channel may comprise diamond (or other diamond-like material). The micro-channel structure may form part of a fluid cooling system for the die. Other embodiments are described... Agent: Intel Corporation C/o Intellevate, LLC

20070224730 - Hillock-free aluminum layer and method of forming the same: A hillock-free conductive layer comprising at least two aluminum (Al) layers formed on a substrate, wherein said at least two Al layers comprise a barrier Al layer formed on the substrate, and a pure Al layer formed on the barrier Al layer. The barrier Al layer could be an aluminum... Agent: Rabin & Berdo, PC

20070224729 - Method for manufacturing a flip-chip package, substrate for manufacturing and flip-chip assembly: A method for manufacturing a flip-chip package, in particular to a method for filling the space between an active side of a chip and a contact side of a substrate is disclosed. Furthermore, a substrate for supporting the filling and a flip-chip assembly is disclosed. The substrate includes a feed... Agent: Slater & Matsil LLP

20070224728 - Method for wafer level package of sensor chip: A method for wafer level package (WLP) of sensor chips is provided, including the steps of: providing a wafer, the wafer including a plurality of die regions, each the die region on a first surface of the wafer comprising an active area and a pad surrounding the active area; bounding... Agent: Birch Stewart Kolasch & Birch

20070224731 - Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward,... Agent: Kratz, Quintos & Hanson, LLP

20070224732 - Manufacturing method of a package structure: A manufacturing method of a package structure is provided. Firstly, a substrate having a surface is provided. Next, a chip is disposed on the surface of the substrate. Then, a packing material layer is formed on the surface of the substrate. Next, a thin film is pasted on the packing... Agent: Birch Stewart Kolasch & Birch

20070224733 - Die bonding: A die bonding method and apparatus by which a wafer substrate 11 adhered to a carrier tape 13 by an adhesive layer 12 is laser machined through the wafer substrate and through the adhesive layer at most to scribe the carrier tape to form a singulated die 15 with an... Agent: Seyfarth Shaw LLP

20070224734 - Method for bonding heatsink and semiconductor device with heatsink: A simple method for bonding a heatsink for improving heat-radiating efficiency, comprising the steps of sticking a double-sided adhesive tape to an end portion on an adhesion surface of at least either the heatsink or the semiconductor device; applying an adhesive onto the adhesion surface of at least either the... Agent: Kratz, Quintos & Hanson, LLP

20070224735 - Optical transmission channel board, board with built-in optical transmission channel, and data processing apparatus: A fabrication method for an optical transmission channel board includes a first step of forming on a substrate a layer containing an electrically conductive material, and a second step of patterning said layer containing an electrically conductive material formed on said substrate, and thereby forming circuit patterns at least a... Agent: Ratnerprestia

20070224736 - Nonvolatile semiconductor memory and fabrication method therefor: A fabrication method for a nonvolatile semiconductor memory forming gate insulating films for a memory cell transistor and a select gate transistor on a semiconductor substrate, forming a floating gate for the memory cell transistor and a gate electrode for the select gate transistor, forming a cap insulating film for... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224737 - Method for creating and tuning electromagnetic bandgap structure and device: Tuned Electromagnetic Bandgap (EBG) devices, and a method for making and tuning tuned EBG devices are provided. The method includes the steps of providing first and second overlapping substrates, placing magnetically alignable conductive material between the substrates, and applying a magnetic field in the vicinity of the magnetically alignable conductive... Agent: Delphi Technologies, Inc.

20070224738 - Semiconductor device with a multi-plate isolation structure: A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench (62) formed therein. The isolation trench (62) may have first and second opposing inner walls (74, 76) and a floor (78). First and second conductive... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070224742 - E-ink display and method for repairing the same: An E-ink display and method for repairing the same is provided. The method is for repairing a thin film transistor array substrate of the E-ink display. The thin film transistor array substrate having a plurality of pixel units is provided initially. Each of the pixel unit includes a thin film... Agent: Sheehan Phinney Bass & Green, PA C/o Peter Nieves

20070224741 - Semiconductor element, semiconductor device, and method of manufacturing the same: A method of manufacturing a semiconductor element includes: (a) preparing a first substrate provided with a plurality of protruding sections formed on a surface of the first substrate and a second substrate provided with a semiconductor film formed on a surface of the second substrate; and (b) executing a heat... Agent: Oliff & Berridge, PLC

20070224740 - Thin-film transistor and method of fabricating the same: A conductive film is processed in a first etching step, and thinned by reprocessing using light ashing. An exposed portion of an insulating film is etched away in the film thickness direction, thereby forming a step on the insulating film. Impurity ions are implanted into a semiconductor layer.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224739 - Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s): A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.... Agent: Sonnenschein Nath & Rosenthal LLP

20070224743 - Thermal dissipation structures for finfets: A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070224744 - Thin film transistor, method of fabricating the same, and flat panel display using thin film transistor: A thin film transistor may include an active layer formed on an insulating substrate and formed with source/drain regions and a channel region; a gate insulating film formed on the active layer; and a gate electrode formed on the gate insulating film. The gate electrode may be formed of a... Agent: H.c. Park & Associates, PLC

20070224747 - System and method for producing a semiconductor circuit arrangement: Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed... Agent: Brinks Hofer Gilson & Lione Infineon

20070224746 - Method and apparatus providing different gate oxides for different transitors in an integrated circuit: An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide... Agent: Dickstein Shapiro LLP

20070224748 - Semiconductor body comprising a transistor structure and method for producing a transistor structure: A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried zone, a second zone having a second conductivity type that is different from the first conductivity type... Agent: Fish & Richardson PC

20070224745 - Semiconductor device and fabricating method thereof: A semiconductor device including a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer is disclosed. The gate dielectric layer is disposed on the substrate and the gate whose top area is larger than its bottom area is disposed on the gate dielectric... Agent: Jianq Chyun Intellectual Property Office

20070224749 - Semiconductor device fabrication method: According to the present invention, there is provided a semiconductor device fabrication method having: coating a semiconductor substrate with a silazane perhydride polymer solution prepared by dispersing a silazane perhydride polymer in a solvent containing carbon, thereby forming a coating film; forming a polysilazane film by volatilizing the solvent by... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070224750 - Covert transformation of transistor properties as a circuit protection method: A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are applied to the device.... Agent: Robert Popa C/o Ladas & Parry

20070224751 - Embedded non-volatile memory cell with charge-trapping sidewall spacers: An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells and the FETs are made up of a spacer material with local charge storage... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070224752 - Laterally diffused metal oxide semiconductor device and method of forming the same: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region... Agent: Slater & Matsil, L.L.P.

20070224753 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.... Agent: Dickstein Shapiro LLP

20070224754 - Structure and method of three dimensional hybrid orientation technology: A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. In use, the device includes a nFET... Agent: Greenblum & Bernstein, P.L.C

20070224755 - Semiconductor device manufacturing method including oblique ion implantation process and reticle pattern forming method: An active region and an opposite conductivity active region are formed in a semiconductor substrate. The opposite conductivity active region is covered with a resist pattern. Impurities are implanted into a surface layer of the active region. An angle θ0 is defined as a tilt angle obtained by tilting a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070224756 - Method for fabricating recessed gate mos transistor device: A method of fabricating self-aligned gate trench utilizing TTO spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. Trench capacitors are formed in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide... Agent: North America Intellectual Property Corporation

20070224757 - Offset vertical device: The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical... Agent: Scully, Scott, Murphy & Presser, P.C.

20070224758 - Semiconductor memory device and related fabrication method: Embodiments of the invention provide a semiconductor memory device and a method for fabricating the semiconductor memory device. The semiconductor memory device comprises a source region and a drain region disposed in a semiconductor substrate; a buried contact disposed on and electrically connected to the source region of the transistor;... Agent: Volentine & Whitt PLLC

20070224759 - Method for forming an integrated memory device and memory device: The invention in one of the embodiments refers to a method for forming an integrated memory device, the method including a forming a plurality of bitlines, wherein forming the plurality of bitlines includes forming diffusion lines in a substrate, forming an electrically conductive silicidation barrier layer on a substrate surface... Agent: Slater & Matsil LLP

20070224760 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate insulating film, forming a plurality of trenches in the first silicon film and in the mask film to a depth to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070224761 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a silicon substrate 10 having a device region 11, a transistor including a gate electrode 20 formed in the device region 11 with the gate insulation film 14 formed therebetween, and a dummy metal layer 52 formed over the gate electrode 20 with an inter-layer insulation... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070224762 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a recess with a device separating film and a first hard mask layer so that a pad nitride film for defining a recess gate region may remain with a conventional mask. The method additionally the recess gate region to facilitate a... Agent: Heller Ehrman LLP

20070224763 - Semiconductor device and method of manufacturing the same: In a method of manufacturing a semiconductor device, a trench is formed to have an upper quadrangular section and a lower circular section which is formed through a hydrogen annealing process, to extend in a depth direction of a semiconductor substrate. An insulating film is formed on a surface of... Agent: Young & Thompson

20070224764 - Method for manufacturing insulated-gate type field effect transistor: A poly-silicon layer is deposited on a surface of a substrate after forming a gate insulating film in an element hole of a field insulating film 12, and thereon a silicon oxide layer is formed by a thermal oxidation process. After patterning the silicon oxide layer in accordance with a... Agent: Dickstein Shapiro LLP

20070224765 - Methods of fabricating semiconductor devices having a double metal salicide layer: A semiconductor device is fabricated by forming a gate electrode structure, comprising a gate oxide layer pattern, a polysilicon layer pattern, and sidewall spacers on a silicon substrate, forming source/drain regions on both sides of the gate electrode structure in the silicon substrate, depositing a physical vapor deposition (PVD) cobalt... Agent: Myers Bigel Sibley & Sajovec

20070224766 - Selective etch for patterning a semiconductor film deposited non-selectively: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A... Agent: Intel/blakely

20070224767 - Semiconductor device with recessed trench and method of fabricating the same: A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and extends above the... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20070224768 - Method and apparatus for delivery of pulsed laser radiation: A method and apparatus delivers pulsed laser energy to a damage-sensitive surface. The pulse scanning method and apparatus allow for the deposition of a total dose of laser radiation that could not be attained by any conventional means without damaging the substrate being exposed. Using a solid-state diode pumped YAG... Agent: Mills & Onello LLP

20070224769 - Semiconductor device and manufacturing method thereof: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity... Agent: Rossi, Kimms & Mcdowell LLP.

20070224770 - Systems and methods for fabricating self-aligned memory cell: Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr1-XCaXMnO3 (PCMO) layer above the insulator and the metal... Agent: Tran & Associates

20070224771 - Semiconductor device having fuse and capacitor at the same level and method of fabricating the same: In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is placed on the fuse area, and a lower plate is placed on the... Agent: Volentine & Whitt PLLC

20070224773 - Method of producing simox wafer: A SIMOX wafer is produced at an oxygen ion implantation step and a high-temperature annealing step, wherein an oxide film is formed on a surface of a wafer prior to the oxygen ion implantation and then the oxygen ion implantation is conducted through the oxide film.... Agent: Sughrue Mion, PLLC

20070224772 - Method for forming a stressor structure: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer (224) disposed on a buried dielectric layer (222). A trench (229) is created in the semiconductor structure which exposes a portion of the buried... Agent: Fortkort & Houston P.C.

20070224774 - Method of producing simox wafer: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than... Agent: Sughrue Mion, PLLC

20070224775 - Trench isolation structure having an expanded portion thereof: Embodiments of the present invention relate to the fabrication of isolation structures within a microelectronic substrate for microelectronic devices, wherein the design of the isolation structures reduce or substantially eliminate the formation of surface voids within a dielectric material of the isolation structures. These surface voids are reduced or avoided... Agent: Intel Corporation C/o Intellevate, LLC

20070224776 - Method for forming a 3d interconnect and resulting structures: A method for forming three-dimensional (3D) integrated circuits includes providing a first wafer comprising a silicon layer on a top surface of the first wafer, providing a second wafer comprising a silicon oxide layer on a top surface of the second wafer, bonding the first and the second wafers by... Agent: Slater & Matsil, L.L.P.

20070224777 - Substrate holder having a fluid gap and method of fabricating the substrate holder: A substrate holder (20) for supporting a substrate (30). A heating component (50) is positioned adjacent to a supporting surface and between the supporting surface and a cooling component (60). A fluid gap is positioned between the cooling component and the heating component, the fluid gap configured to receive a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224778 - Method of producing simox wafer: A SIMOX wafer is produced by implanting oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which a SOI film having a thickness thicker than a target SOI film thickness is previously formed and a final adjustment of the SOI film thickness is... Agent: Sughrue Mion, PLLC

20070224780 - Method for dicing a wafer: A method for dicing a wafer is provided. A layer of adhesive material is applied to the back surface of the wafer so as to provide a sufficient mechanical strength for the wafer during dicing process thereby preventing the dice diced from the wafer from undue chipping on the back... Agent: Lowe Hauptman Berner, LLP

20070224781 - Separation method for cutting semiconductor package assemblage for separation into semiconductor packages: A separation method by which a semiconductor package assemblage is cut in a predetermined width W1 along streets arranged in a lattice pattern to separate the semiconductor package assemblage into a plurality of semiconductor packages, the semiconductor package assemblage including a metallic frame having metallic die pads of a predetermined... Agent: Smith, Gambrell & Russell

20070224779 - Method for fabricating a bga device and bga device: In a method chips are provided with solder balls as of a ball grid array directly without any substrate thereby forming a BGA device. The inventive BGA device is protected on its active side by a protective layer made of solder resist or other equivalent materials and the solder balls... Agent: Slater & Matsil LLP

20070224782 - Gettering method and a wafer using the same: It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for... Agent: Birch Stewart Kolasch & Birch

20070224783 - Process for forming low defect density, ideal oxygen precipitating silicon: The present invention is directed to a process for producing a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of... Agent: Senniger Powers

20070224786 - Epitaxial semiconductor deposition methods and structures: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between... Agent: Knobbe Martens Olson & Bear LLP

20070224784 - Semiconductor material having an epitaxial layer formed thereon and methods of making same: A semiconductor material having an epitaxial layer formed thereon and methods of forming an epitaxial layer on a semiconductor material are provided. The method includes disposing a masking layer and patterning the masking layer to form openings and growing an epitaxial layer through the openings and over the masking layer... Agent: General Electric Company (pcpi) C/o Fletcher Yoder

20070224785 - Strain-inducing film formation by liquid-phase epitaxial re-growth: A method to form a strain-inducing three-component epitaxial film is described. In an embodiment, a three-component epitaxial film comprises atoms from a parent film, charge-neutral lattice-substitution impurities and charge carrier dopant impurities. In one embodiment, the charge-neutral lattice-substitution impurities are smaller and present in greater concentration than the charge carrier... Agent: Intel/blakely

20070224787 - Relaxed heteroepitaxial layers: Some embodiments of the invention are related to manufacturing semiconductors. Methods and apparatuses are disclosed that provide thin and fully relaxed SiGe layers. In some embodiments, the presence of oxygen between a single crystal structure and a SiGe heteroepitaxial layer, and/or within the SiGe heteroepitaxial layer, allow the SiGe layer... Agent: Knobbe, Martens, Olsen & Bear LLP

20070224788 - Fabrication of large grain polycrystalline silicon film by nano aluminum-induced crystallization of amorphous silicon: One aspect of the present invention relates to a method for fabricating a polycrystalline silicon film. In one embodiment, the method includes the steps of providing a substrate having a thermally-grown silicon dioxide layer, forming an amorphous silicon film on the thermally-grown silicon dioxide layer of the substrate, forming an... Agent: Morris Manning Martin LLP

20070224789 - Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film: In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor substrate with an opening that exposes a portion of the defined... Agent: Myers Bigel Sibley & Sajovec

20070224790 - Zn ion implanting method of nitride semiconductor: A method of implanting a zinc (Zn)-ion into a nitride-based semiconductor substrate, the method includes: providing a homogeneous substrate on which a gallium nitride layer is grown; placing the homogeneous substrate in a crucible in which gallium nitride powders are coated; placing the crucible into a furnace; and performing a... Agent: Mcdermott Will & Emery LLP

20070224791 - Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof: By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature at 300° C. or less, setting the sputtering power from 1 kW to 9 kW, and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa,... Agent: Edward D. Manzo Cook, Alex, Mcfarron, Manzo,

20070224792 - Manufacturing method of semiconductor device and etching solution: This disclosure concerns a manufacturing method of a semiconductor device comprising an etching process using an etching solution having ozone dissolved by 10 ppm or more into a liquid containing H2SO4 by 86 wt % to 97.9 wt %, HF by 0.1 wt % to 10 wt %, and H2O... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070224797 - Method for manufacturing semiconductor device, method for forming alignment mark, and semiconductor device: A method for manufacturing a semiconductor device includes the steps of: forming a first dielectric film on a substrate; etching the first dielectric film in a plug forming region to form a first via hole; forming a first plug electrode in the first via hole; forming a conductive film on... Agent: Harness, Dickey & Pierce, P.L.C

20070224795 - Dummy vias for damascene process: A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein... Agent: Haynes And Boone, LLP

20070224796 - Method of forming a phase changeable structure: The present invention relates to a method of forming a phase changeable structure wherein an upper electrode is formed on a phase changeable layer. A material including fluorine can be provided to the phase changeable layer and the upper electrode. The phase changeable layer can be etched to form a... Agent: Marger Johnson & Mccollom, P.C.

20070224794 - Single passivation layer scheme for forming a fuse: An integrated circuit structure comprising a fuse and a method for forming the same are provided. The integrated circuit structure includes a substrate, an interconnection structure over the substrate, a fuse connected to the interconnection structure, and an anti-reflective coating (ARC) on the fuse. The ARC has an increased thickness... Agent: Slater & Matsil, L.L.P.

20070224793 - Temperature-controlled metallic dry-fill process: A method for performing ionized physical vapor deposition (iPVD) is described, whereby the substrate temperature can be rapidly changed to control a metal deposition process and increase the quality of the metal deposited. In one embodiment, a copper deposition process can be performed.... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070224798 - Semiconductor device and medium of fabricating the same: A highly-reliable semiconductor device and a method of fabricating the semiconductor device, while stably carrying out IC test, are proposed. A pad portion after an IC test using a probe is covered with a second passivation film. It is therefore made possible to protect the pad, which has partially been... Agent: Young & Thompson

20070224799 - System for making a semiconductor device using bump material including liquid: A system of making a semiconductor device by forming bumps on pads of a test piece which is a semiconductor wafer or chip is disclosed. The system includes a mask substrate having holding holes; a supply portion for supplying a bump material including liquid, which contains a plurality of individual... Agent: Cohen, Pontani, Lieberman & Pavane

20070224800 - Production method for semiconductor device: A method for producing a semiconductor device that uses a silicone-based die bonding material with high heat resistance and a low elastic modulus is provide. The method includes the steps of: applying a heat-curable silicone-based die bonding material to a substrate, placing a semiconductor element on the coated surface of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224803 - Methods for etching a dielectric barrier layer with high selectivity: Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing... Agent: Patterson & Sheridan, LLP

20070224802 - Semiconductor device and a manufacturing method of the same: A first BPSG film covering a transistor is formed. Next, a second BPSG film is formed on the first BPSG film. The B concentration in the first BPSG film is about five times higher than the B concentration in the second BPSG film. Next, the first BPSG film is separated... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070224804 - Carbon nanotube-based electronic devices made by electrolytic deposition and applications thereof: Carbon nanotube-based devices made by electrolytic deposition and applications thereof are provided. In a preferred embodiment, the present invention provides a device comprising at least one array of active carbon nanotube junctions deposited on at least one microelectronic substrate. In another preferred embodiment, the present invention provides a device comprising... Agent: Dickstein Shapiro LLP

20070224801 - Dielectric interconnect structures and methods for forming the same: Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In... Agent: Hoffman, Warnick & D'alessandro LLC

20070224805 - Semiconductor device and manufacturing method therefor: To provide a semiconductor device that enables high integration degree, and a manufacturing method therefor. A multi-chip module according to an embodiment of the present invention includes: a first semiconductor chip having a first bonding pad; a second semiconductor chip having a second bonding pad thinner than the first bonding... Agent: Mcginn Intellectual Property Law Group, PLLC

20070224806 - Metal polishing slurry:

20070224807 - Methods for etching a dielectric barrier layer with high selectivity: Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing... Agent: Patterson & Sheridan, LLP

20070224808 - Silicided gates for cmos devices: A silicided gate for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate. A first dielectric layer is formed over the gate electrode and the substrate, and a second dielectric layer is formed over the first dielectric layer. The second dielectric layer... Agent: Slater & Matsil, L.L.P.

20070224809 - Method of forming wiring: Resist films 19 for liftoff are formed on an insulating layer 12 corresponding to a wiring formation region A so as to expose the insulating layer 12 corresponding to formation positions of first seed layers 14 and thereafter, metal films 21 are formed. Then, the resist films 19 for liftoff... Agent: Drinker Biddle & Reath (dc)

20070224810 - Manufacturing method for an integrated semiconductor structure: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070224811 - Substrate processing method and substrate processing apparatus: A substrate processing method can completely remove a corrosion inhibitor and/or a metal complex from a surface of a substrate prior to catalyst application processing and/or electroless plating, and can form a protective film having a uniform thickness on the surface of interconnects. The substrate processing method includes preparing a... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070224812 - Pattern film forming method and pattern film forming apparatus: A pattern film forming method includes a step of producing a transfer sheet in which a thin film is formed on a surface of a sheet-shaped material and a step of pressing the thin film against a pattern film formation surface of the substrate with a pressing member having convex... Agent: Sughrue Mion, PLLC

20070224816 - Organosilane hardmask compositions and methods of producing semiconductor devices using the same: p

20070224818 - Substrate processing method and storage medium: A substrate processing method capable of preventing a substrate rear surface from being scratched when attracted onto an electrostatic chuck. In a coater/developer (11), a photocurable resin is coated onto a rear surface of a wafer (W), the resin is cured to form a resin protective film, and a resist... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224819 - Topography directed patterning: A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers which have been formed by a pitch multiplication process in which... Agent: Knobbe Martens Olson & Bear LLP

20070224813 - Device and method for etching flash memory gate stacks comprising high-k dielectric: In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching... Agent: Balzan Intellectual Property Law, PC

20070224814 - Integrated multi-wavelength fabry-perot filter and method of fabrication: A method is provided for forming a monolithically integrated optical filter, for example, a Fabry-Perot filter, over a substrate (10). The method comprises forming a first mirror (16) over the substrate (10). A plurality of etalon material layers (32, 34, 36, 38) are formed over the mirror (16), and a... Agent: Ingrassia Fisher & Lorenz, P.C.

20070224817 - Plasma processing apparatus, plasma processing method, and storage medium: A plasma processing apparatus having a substrate processing chamber, which enables leakage of plasma into an exhaust space to be prevented. The substrate processing chamber has therein a processing space in which plasma processing is carried out on a substrate, an exhaust space for exhausting gas out of the processing... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224815 - Substrate patterning for multi-gate transistors: Some embodiments of the present invention include apparatuses and methods relating to improved substrate patterning for multi-gate transistors.... Agent: Intel Corporation C/o Intellevate, LLC

20070224820 - Facility with multi-storied process chamber for cleaning substrates and method for cleaning substrates using the facility: A facility for cleaning substrates such as semiconductor wafers includes a loading/unloading part, an aligning part where wafers are repositioned from a horizontal state to a vertical state, a cleaning part performing etchant-treating, rinsing, and drying processes for wafers and having a plurality of process chamber stacked, and an interface... Agent: Harness, Dickey & Pierce, P.L.C

20070224821 - Method for manufacturing silicon wafers: This silicon wafer production process comprises in the order indicated a planarization step, in which the front surface and the rear surface of a wafer are ground or lapped, a single-wafer acid etching step, in which an acid etching liquid is supplied to the surface of the wafer while spinning... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070224822 - Halide anions for metal removal rate control: The inventive chemical-mechanical polishing system comprises a polishing component, a liquid carrier, an oxidizing agent, and a halogen anion. The inventive method comprises chemically-mechanically polishing a substrate with the polishing system.... Agent: Steven Weseman Associate General Counsel, I.p.

20070224823 - Topography directed patterning: A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers which have been formed by a pitch multiplication process in which... Agent: Knobbe Martens Olson & Bear LLP

20070224824 - Method of repairing process induced dielectric damage by the use of gcib surface treatment using gas clusters of organic molecular species: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method... Agent: International Business Machines Corporation Dept. 18g

20070224825 - Methods for etching a bottom anti-reflective coating layer in dual damascene application: Methods for two step etching a BARC layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having vias filled with a BARC layer disposed on the substrate in an etch reactor, supplying a first gas mixture into the reactor to etch a... Agent: Patterson & Sheridan, LLP

20070224827 - Methods for etching a bottom anti-reflective coating layer in dual damascene application: Methods for two step etching a BARC layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having vias filled with a BARC layer disposed on the substrate in an etch reactor, supplying a first gas mixture into the reactor to etch a... Agent: Patterson & Sheridan, LLP

20070224826 - Plasma dielectric etch process including in-situ backside polymer removal for low-dielectric constant material: A plasma etch process with in-situ backside polymer removal begins with a workpiece having a porous or non-porous carbon-doped silicon oxide dielectric layer and a photoresist mask on a surface of the workpiece. The workpiece is clamped onto an electrostatic chuck in an etch reactor chamber. The process includes introducing... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20070224828 - Plasma etching method: A plasma etching apparatus is arranged to perform main etching for etching a poly-crystalline silicon film by use of Cl2/SF6/N2 plasma obtained by exciting Cl2 gas, SF6 gas, and N2 gas, and over etching for etching the poly-crystalline silicon film by use of Cl2/HBr/CF4 plasma obtained by exciting Cl2 gas,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224829 - Use of hypofluorites, fluoroperoxides, and/or fluorotrioxides as oxidizing agent in fluorocarbon etch plasmas: A mixture and a method comprising same for etching a dielectric material from a layered substrate are disclosed herein. Specifically, in one embodiment, there is provided a mixture for etching a dielectric material in a layered substrate comprising: a fluorocarbon gas, a fluorine-containing oxidizer gas selected from the group consisting... Agent: Air Products And Chemicals, Inc. Patent Department

20070224830 - Low temperature etchant for treatment of silicon-containing surfaces: Embodiments provide a method for etching or smoothing a silicon material on a substrate. In one example, the method provides positioning a substrate containing a contaminant disposed on a silicon material within a process chamber, heating the substrate to a temperature of less than 800° C., and exposing the silicon... Agent: Patterson & Sheridan, LLP

20070224831 - Post structure, semiconductor device and light emitting device using the structure, and method for forming the same: A nanometer-scale post structure and a method for forming the same are disclosed. More particularly, a post structure, a light emitting device using the structure, and a method for forming the same, which is capable of forming a nanometer-scale post structure having a repetitive pattern by using an etching process,... Agent: Birch Stewart Kolasch & Birch

20070224834 - Dielectric material having carborane derivatives: Numerous embodiments of an apparatus and method of a dielectric material having a low dielectric constant and good mechanical strength are described. In one embodiment a dielectric material having multiple porous regions is disposed over a substrate. A caged structure is bridged within the plurality of pores. In one particular... Agent: Blakely Sokoloff Taylor & Zafman

20070224832 - Method for forming and sealing a cavity for an integrated mems device: A method is provided for constructing a microelectronic assembly. A semiconductor substrate having a MEMS device formed on a first portion thereof, a semiconductor device formed on a second portion thereof, and a build up layer having a first portion formed over the MEMS device and a second portion formed... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070224833 - Method of forming carbon polymer film using plasma cvd: A method of forming a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (CαHβXγ, wherein α and β are natural numbers of 5 or more; γ is an integer including zero; X is O,... Agent: Knobbe Martens Olson & Bear LLP

20070224835 - Semiconductor device and method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes: forming a first photosensitive material pattern having an opening hole on a work target layer formed on an active surface of a substrate; performing a first etching by performing an etching treatment to the work target layer using the first photosensitive materialpattern... Agent: Oliff & Berridge, PLC

20070224836 - Method for manufacturing semiconductor device and plasma oxidation method: A polysilicon electrode layer (103) (a first electrode layer) is formed by forming a polysilicon film on a gate oxide film (102) on a silicon wafer (101). A tungsten layer (105) (a second electrode layer) is formed on this polysilicon electrode layer (103). In addition, a barrier layer (104) is... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224837 - Method for producing material of electronic device: A process for producing electronic device (for example, high-performance MOS-type semiconductor device) structure having a good electric characteristic, wherein an SiO2 film or SiON film is used as an insulating film having an extremely thin (2.5 nm or less, for example) film thickness, and poly-silicon, amorphous-silicon, or SiGe is used... Agent: Crowell & Moring LLP Intellectual Property Group

20070224838 - Method of straining a silicon island for mobility improvement: A method for improving mobility by bending a silicon island. Oxygen diffuses and reacts down a first axis of a pFET or NFET. This results in a partial oxidation of a buried-oxide/silicon island interface. The partial oxidation produces a thickness variation in the silicon island that creates a stress along... Agent: Honeywell International Inc.

20070224839 - Heat treating apparatus, heat treating method and storage medium: A heat treating apparatus, which performs a specified heat treatment on a target object, includes a processing chamber accommodating therein the target object; a mounting table for mounting thereon the target object; a vacuum exhaust system for vacuum evacuating the processing chamber; an electromagnetic wave supply unit for irradiating an... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070224840 - Method of plasma processing with in-situ monitoring and process parameter tuning: A method of selecting plasma doping process parameters includes determining a recipe parameter database for achieving at least one plasma doping condition. The initial recipe parameters are determined from the recipe parameter database. In-situ measurements of at least one plasma doping condition are performed. The in-situ measurements of the at... Agent: Rauschenbach Patent Law Group, LLC

20070218568 - Method for manufacturing ferroelectric memory device: A method for manufacturing a ferroelectric capacitor, includes the steps of: forming a ferroelectric capacitor layer having a lower electrode layer, a ferroelectric layer and an upper electrode layer on a base substrate; forming a titanium oxide layer on the ferroelectric capacitor layer; patterning the titanium oxide layer by high-temperature... Agent: Harness, Dickey & Pierce, P.L.C

20070218569 - Method of manufacturing ferroelectric memory device: A method of manufacturing a ferroelectric memory device includes: forming an active element on a substrate; forming an interlayer insulating layer on the substrate; forming an opening on the interlayer insulating layer and forming a contact plug inside the opening; forming a foundation layer above the substrate; and laminating, on... Agent: Harness, Dickey & Pierce, P.L.C

20070218571 - Disabling poorly testing rfid ics: Manufacturing methods, testing, and RFID integrated circuit wafers that have been so prepared. A function of an integrated circuit can be tested. If the test fails, a control function of the tested circuit is disabled.... Agent: Schwegman, Lundberg, Woessner & Kluth/impinj

20070218574 - Semiconductor laser manufacturing method: A method of manufacturing a semiconductor laser that has a ridge portion formed with a compound semiconductor layer containing Ga includes applying an electric current to the semiconductor laser until the characteristics of the semiconductor laser that have deteriorated due to the application of the electric current recover from the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070218581 - Photo-masking method for fabricating tft array substrate: An exemplary method for fabricating a TFT array substrate includes providing an insulating substrate (201); coating a gate metal layer (202) on the substrate; forming a plurality of gate electrodes (212) using a first photo-mask process; forming a gate insulating layer (203), a semiconducting layer (205), and a source/drain metal... Agent: Wei Te Chung Foxconn International, Inc.

20070218580 - Triple-junction filterless cmos imager cell: A triple-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is made from a bulk silicon (Si) substrate. A photodiode set including a first, second, and third photodiode are formed as a triple-junction structure in the Si substrate. A transistor set is connected to the photodiode... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070218582 - Process for making contained layers and devices made with same: t

20070218570 - Nitorgen doped silicon wafer and manufacturing method thereof: An epitaxial wafer and a high-temperature heat treatment wafer having an excellent gettering capability are obtained by performing epitaxial growth or a high-temperature heat treatment. A relational equation relating the density to the radius of an oxygen precipitate introduced in a silicon crystal doped with nitrogen at the time of... Agent: Fish & Richardson PC

20070218572 - Fabrication method of semiconductor integrated circuit device: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070218573 - Semiconductor component having test pads and method and apparatus for testing same: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is... Agent: Xilinx, Inc Attn: Legal Department

20070218575 - Method and apparatus for electroluminescence: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070218576 - Method for fabricating polysilicon liquid crystal display device: A method for fabricating a polysilicon liquid crystal display device includes: forming a first amorphous silicon layer on a substrate; forming a photoresist pattern on the first amorphous silicon layer; forming a second amorphous silicon layer over the photoresist pattern and the first amorphous silicon layer; defining a channel region... Agent: Mckenna Long & Aldridge LLP

20070218577 - Liquid crystal display panel and fabricating method thereof: A liquid crystal display (LCD) panel is fabricated with a reduced number of mask processes and includes a thin film transistor (TFT) array substrate and a color filter array substrate. The TFT array substrate includes gate and data lines insulatively crossing each other to define a pixel area, a TFT... Agent: Song K. Jung Mckenna Long& Aldridge LLP

20070218578 - Real-time cmos imager having stacked photodiodes fabricated on soi wafer: A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength;... Agent: Robert D. Varitz

20070218579 - Wide output swing cmos imager: A CMOS active pixel sensor (APS) imager cell is provided on a silicon-on-insulator (SOI) substrate. The APS imager cell is made from a SOI substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A pixel sensor cell including... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070218583 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a radiation sensitive component in and/or on a microelectronic device, placing a curable component in and/or on the microelectronic device, and forming a barrier in and/or on the microelectronic device to at... Agent: Perkins Coie LLP Patent-sea

20070218585 - Encapsulation in a hermetic cavity of a microelectronic composite, particularly of a mems: To produce a structure of a micro-electro-mechanical system (MEMS) in a hermetic cavity (38) of a microelectronic device (50), a prepared cover (30) and substrate (10) are bonded by means of silicon direct bonding (SDB). To optimise the preparation of surfaces by means of wet cleaning without impairing the properties... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070218586 - Manufacturing method of semiconductor device: An adhesive layer of which thickness is over 25 μm and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070218584 - Method for wafer-level package: A method for wafer-level package. A cap wafer having cavities is bonded to a support wafer, and a portion of the cap wafer is etched through. The cap wafer is released from the support wafer, and bonded to a transparent wafer, and a portion of the cap wafer corresponding to... Agent: North America Intellectual Property Corporation

20070218587 - Soft conductive polymer processing pad and method for fabricating the same: Embodiments of the invention generally provide a conductive processing pad and a method for fabricating the same. In one embodiment the conductive processing pad includes a grid of conductive material disposed in a polymer layer. A plurality of perforations is formed through the polymer in the open area defined by... Agent: Patterson & Sheridan, LLP

20070218588 - Integrated circuit package having stacked integrated circuits and method therefor: Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed. These improved techniques allow greater stacking density of integrated circuit dies within an integrated circuit package. Additionally, the improved stacking techniques permit conventional bonding techniques for electrical connection of the various integrated circuit dies to each... Agent: Beyer Weaver LLP/ Sandisk

20070218589 - Manufacturing method of multilayer wiring substrate: A first multilayer wiring structural body 16 and a second multilayer wiring structural body 56 are simultaneously formed on both surfaces 101A, 101B of a substrate 101 and thereafter the portion of a structural body 120 corresponding to a third region C1 is folded so as to oppose a second... Agent: Drinker Biddle & Reath (dc)

20070218590 - Plating apparatus, plating method and manufacturing method for semiconductor device: A semiconductor device with plating film layers for semiconductor device leads is described. A first plating film layer that includes Sn as a main material is formed on a semiconductor device lead in which Cu or Fe—Ni is a main material. The outermost surface of the lead includes a plating... Agent: Fish & Richardson P.C.

20070218591 - Method for fabricating a metal protection layer on electrically connecting pad of circuit board: This invention discloses a method for electroplating nickel/gold on electrically connecting pads on a substrate for chip package and structure thereof. The method comprises: forming a conductive film on a substrate circuit-patterned and defined with a circuit layer; forming on the substrate a resist with an opening for exposing a... Agent: Sawyer Law Group LLP

20070218593 - Method for producing semiconductor package: A method for producing a semiconductor package including a main semiconductor chip having a semiconductor circuit formed on one surface thereof, at least one subsidiary semiconductor chip stacked on the other surface of the main semiconductor chip, and an encapsulation resin covering the subsidiary semiconductor chip. This method comprises a... Agent: Smith, Gambrell & Russell

20070218592 - Green sheet, production method of green sheet and production method of electronic device: A production method, comprising the steps of preparing a pre-compression green sheet including ceramic powder and a binder resin and compressing the pre-compression green sheet to obtain compressed green sheet: wherein a difference (Δρg) between a pre-compression sheet density (ρg1) of the pre-compression green sheet and a post-compression sheet density... Agent: Oliff & Berridge, PLC

20070218594 - Method of forming metal wiring and method of manufacturing active matrix substrate: A method of forming a metal wiring includes: forming a foundation layer on a substrate; applying a solution including fine metal particles and a dispersion stabilizer on the foundation layer; and heating the applied solution to form into a conductive layer, wherein after the applying of the solution, the conductive... Agent: Harness, Dickey & Pierce, P.L.C

20070218595 - Power electronics equipments: Power electronics equipment includes air-cored insulating transformers inserted between a control circuit grounded to a vehicle body and an upper arm biased at a high voltage, and air-cored insulating transformers between the control circuit grounded to the vehicle body and the lower arm biased at a high voltage. Each of... Agent: Kanesaka Berner And Partners LLP

20070218596 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode... Agent: Foley And Lardner LLP Suite 500

20070218597 - Structure and method for controlling the behavior of dislocations in strained semiconductor layers: A structure and method for controlling the behavior of dislocations in strained semiconductor layers is described incorporating a graded alloy region to provide a strain gradient to change the slope or curvature of a dislocation propagating upwards or gliding in the semiconductor layer in the proximity of the source and... Agent: Robert M. Trepp IBM Corporation

20070218598 - Method for forming ultra thin low leakage multi gate devices: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and... Agent: Texas Instruments Incorporated

20070218599 - Method for producing silicon wafer and silicon wafer: A method for producing a silicon wafer, comprising performing a reduction of an interface state by annealing of an SOI wafer having a buried oxide layer at a temperature of 250 to 900° C. for 3 minutes to 8 hours in an atmosphere composed of one or more gases selected... Agent: Kolisch Hartwell, P.C.

20070218600 - Method for making a field effect transistor with diamond-like carbon channel and resulting transistor: The field effect transistor comprises a source and a drain connected by a channel controlled by a gate electrode separated from the channel by a gate insulator. The channel is formed by a diamond-like carbon layer. The method for making the transistor successively comprises deposition of a diamond-like carbon layer... Agent: Oliff & Berridge, PLC

20070218602 - Thin film transistor and method for fabricating the same: The present invention relates to a thin film transistor for preventing short of circuit by step and a method for fabricating the thin film transistor and provides a thin film transistor including a buffer layer formed on glass substrate; an activation layer formed on the buffer layer; and a gate... Agent: Robert E. Bushnell

20070218601 - Thin film transistor substrate for liquid crystal display device and method of manufacturing the same: A thin film transistor substrate for a liquid crystal display device includes a substrate, a metal layer on the substrate, and an aluminum complex oxide layer on the metal layer. The aluminum complex oxide layer comprises at least one selected from the group consisting of zirconium, tungsten, chromium and molybdenum.... Agent: Macpherson Kwok Chen & Heid LLP

20070218603 - Improved soi substrates and soi devices, and methods for forming the same: An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried... Agent: Scully Scott Murphy & Presser, PC

20070218604 - Method of manufacturing a semiconductor device: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order... Agent: Fish & Richardson P.C.

20070218605 - Semiconductor device and method of manufacture thereof: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070218606 - Semiconductor device and method of manufacture thereof: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070218608 - Method of manufacturing a semiconductor device: By using lasers having different wavelengths in laser annealing of an amorphous semiconductor film, the amorphous semiconductor film can be crystallized and the crystallinity of the crystallized film is improved. A laser 126 to 370 nm in wavelength is used first to subject an amorphous semiconductor film to laser annealing,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070218607 - Methods of forming single crystalline layers and methods of manufacturing semiconductor devices having such layers: In a method of forming a single crystalline semiconductor layer, an amorphous layer may be formed on a seed layer that includes a single crystalline material. The single crystalline layer may be formed from the amorphous layer by irradiating a laser beam onto the amorphous layer using the seed layer... Agent: Myers Bigel Sibley & Sajovec

20070218609 - Manufacturing method of semiconductor device: A gate electrode is formed on a first conductivity type substrate. A second conductivity type implantation region is formed in the first conductivity type substrate. A first conductivity type implantation region is formed by implanting the first conductivity type impurities into the first conductivity type substrate to a depth deeper... Agent: Rabin & Berdo, PC

20070218610 - Methods of making a molecular detection chip having a metal oxide silicon field effect transistor on sidewalls of a micro-fluid channel: A molecular detection chip including a metal oxide silicon-field effect transistor (MOSFET) on sidewalls of a micro-fluid channel and a molecular detection device including the molecular detection chip are provided. A molecular detection method, particularly, qualification methods for the immobilization of molecular probes and the binding of a target sample... Agent: Myers Bigel Sibley & Sajovec

20070218613 - Fully isolated photodiode stack: An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070218612 - Method for fabricating a recessed-gate mos transistor device: A method for fabricating a recessed-gate transistor is disclosed. A trench is recessed into a substrate. A spacer is formed on sidewalls of the trench. A trench bottom oxide is formed. The spacer is then stripped off. A source/drain doping region is formed on the exposed sidewalls of the trench... Agent: North America Intellectual Property Corporation

20070218611 - Leakage barrier for gan based hemt active device: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is... Agent: Patent Administrator Katten Muchin Rosenman LLP

20070218614 - Semiconductor device and method of manufacturing the same, electronic device and method of manufacturing the same, and electronic instrume