Semiconductor device manufacturing: process inventions 08/07

20070202615 - Method of measuring critical dimension: In a method of measuring a critical dimension for conductive structures or openings exposing conductive structures formed on a substrate, a corona ion charge is deposited on the conductive structures and/or an insulating layer having the openings in a measurement region of the substrate. The critical dimension of the conductive... Agent: Volentine & Whitt PLLC

20070202621 - Method of manufacturing nitride semiconductor light emitting device: A method of manufacturing a nitride semiconductor light emitting device having high light emission output and allowing decrease in forward voltage (Vf) is provided. The invention is directed to a method of manufacturing a nitride semiconductor light emitting device including at least an n-type nitride semiconductor, a p-type nitride semiconductor... Agent: Morrison & Foerster LLP

20070202624 - Nitride-based semiconductor light-emitting device and method of manufacturing the same: A nitride-based semiconductor light-emitting device having an improved structure to enhance light extraction efficiency, and a method of manufacturing the same are provided. The method includes the operations of sequentially forming an n-clad layer, an active layer, and a p-clad layer on a substrate; forming a plurality of masking dots... Agent: Buchanan, Ingersoll & Rooney PC

20070202628 - Manufacturing process for integrated piezo elements: A method is provided for the production of integrated microelectromechanical elements, in which first a silicon layer is formed on an insulation layer, then a piezoresistive layer on or in the silicon layer, and then at least one etch opening for etching at least one cavity substantially within the silicon... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070202629 - Method for manufacturing integrated circuit: In a method for manufacturing a light detector that is provided with an apertured part for incident light on an upper structural layer stack laminated on a semiconductor substrate, a polyimide film, which is applied in order to protect a silicon-nitride film on an upper surface of the upper structural... Agent: Oliff & Berridge, PLC

20070202612 - Plasma-polymerisation of polycylic compounds: The present invention relates to a method for the preparation of a layer of a plasma-polymerised material on the surface of a substrate, e.g. a substrate of a glass, an organosiloxane-based or polysiloxane-based material, silicon, fluoro-polymer (e.g. Teflon®), etc. The present invention also relates to novel objects and microstructured or... Agent: Foley And Lardner LLP Suite 500

20070202614 - Method and apparatus for combinatorially varying materials, unit process and process sequence: A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit... Agent: Martine Penilla Gencarella, LLP

20070202613 - Plasma processing apparatus: A plasma processing apparatus is provided using a method of measuring the thickness of a processed material, by which the actual remaining thickness or etching depth of a processed layer can be correctly measured online. The plasma processing apparatus includes a detector 11 for detecting interference light of multiple wavelengths... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070202616 - Structure and method for reliability evaluation of fcpbga substrates for high power semiconductor packaging applications: There is provided a method for measuring thermal properties of a semiconductor packaging material. The method includes incorporating at least one conducting feature into a substrate that includes the semiconductor packaging material, applying an electric current to the feature, and measuring a change in temperature of a region of the... Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP

20070202617 - Method for fabricating stacked semiconductor components with through wire interconnects: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on... Agent: Stephen A. Gratton The Law Office Of Stephen A. Gratton

20070202620 - Fusing nanowires using in situ crystal growth: Crystal growth performed in situ facilitates interconnection of prefabricated nano-structures. The nano-structures are immersed in a growth solution having a controllable saturation condition. Changing the saturation condition of the solution modifies a size of the immersed nanowires. The solution includes a solute of a nano-structure precursor material. The saturation condition... Agent: Hewlett Packard Company

20070202619 - Laser processing apparatus and laser processing method: A laser processing apparatus has one laser light source that simultaneously radiates laser beams with two wavelengths. Depth positions of focusing points for laser beams are gradually changed in a wafer. Three sets of modifying region groups, i.e., six layers of modifying region groups, are successively formed. One set of... Agent: Posz Law Group, PLC

20070202618 - Method of manufacturing information display panel: In the method of manufacturing an information display panel, in which at least one group of display media having optical reflectance and charge characteristics and consisting of at least one or more groups of particles, are sealed in a cell formed by partition walls between two substrates, at least one... Agent: Sughrue Mion, PLLC

20070202622 - Method for manufacturing surface-emitting semiconductor laser: A method for manufacturing a surface-emitting semiconductor laser having a structure in which the single horizontal mode of high power is stably maintained is provided. A scattering-loss-structure portion composed of a low refractive-index region is disposed around a main current path in a surface-emitting semiconductor laser, namely around a cavity... Agent: Bell, Boyd & Lloyd, LLP

20070202623 - Wafer level package for very small footprint and low profile white led devices: A surface mount LED package having a tight footprint and small vertical image size is fabricated by a method comprising: forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing; forming electrical vias in a sub mount, the... Agent: Fay Sharpe LLP

20070202625 - Active matrix organic luminescence display device and manufacturing method for the same: An active matrix organic electro luminescent display (ELD) device comprises a substrate, first and second active layers formed of polycrystalline silicon on the substrate, first source and drain regions and second source and drain regions, the first source and drain regions neighboring the first active layer and the second source... Agent: Brinks Hofer Gilson & Lione

20070202626 - Piezoelectric mems switches and methods of making: MEMS piezoelectric switches 100 that provide advantages of compact structure ease of fabrication in a single unit, and that are free of high temperature-induced morphological changes of the contact materials and resultant adverse effects on properties. High temperature-induced morphological changes refer to changes that occur during fabrication when metallic contacts... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070202627 - Silicon condenser microphone and manufacturing method: A silicon condenser microphone package is disclosed. The silicon condenser microphone package comprises a transducer unit substrate, and a cover. The substrate includes an upper surface having a recess formed therein. The transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of... Agent: Marshall, Gerstein & Borun LLP

20070202630 - Method for manufacturing semiconductor device: An electronic circuit is formed on a semiconductor substrate and electrode pads are formed, which are formed by disposing electrode terminals of the electronic circuit through interconnections on a surface of the semiconductor substrate. After grinding a back surface of the semiconductor substrate, a first resin layer is formed on... Agent: Rabin & Berdo, PC

20070202631 - Semiconductor package: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.... Agent: Ostrolenk Faber Gerb & Soffen

20070202632 - Capacitor attachment method: A method of attaching a capacitor (112) to a substrate (100) includes applying a flux (108) to respective capacitor pads (104, 106) on the substrate (100). The capacitor (112) is placed on the fluxed capacitor pads (104, 106) and a reflow operation is performed on the capacitor (112) and the... Agent: Freescale Semiconductor, Inc. Law Department

20070202633 - Semiconductor package and method for fabricating the same: A semiconductor package and a method for fabricating the same are provided. The method includes providing a substrate having recognition points and a heat sink having openings, and placing the heat sink on the substrate with the recognition points being exposed through the openings; using a checking system to inspect... Agent: Edwards Angell Palmer & Dodge LLP

20070202634 - Method of manufacturing semiconductor device with offset sidewall structure: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070202637 - Body capacitor for soi memory: A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the... Agent: Scully, Scott, Murphy & Presser, P.C.

20070202636 - Method of controlling the film thickness uniformity of pecvd-deposited silicon-comprising thin films: A method which can be used to provide PECVD deposited silicon-comprising films of uniform thickness across large substrate surfaces, where the minimal dimension along an edge of the substrate or the minimum equivalent diameter is about 500 mm. Further, the uniform film can be produced under process conditions which provide... Agent: Shirley L. Church, Esq.

20070202635 - Multi-orientation semiconductor-on-insulator (soi) substrate, and method of fabricating same: The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that... Agent: Scully, Scott, Murphy & Presser, P.C.

20070202638 - Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070202639 - Dual stressed soi substrates: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a... Agent: Scully, Scott, Murphy & Presser, P.C.

20070202640 - Low-k spacer integration into cmos transistors: A method of forming source and drain regions in a semiconductor transistor. The method includes the steps of forming a first sidewall spacer on sidewall surfaces of a gate electrode that is formed on an underlying substrate, where the first sidewall spacer includes amorphous carbon. The method may also include... Agent: Townsend And Townsend And Crew LLP / Amat

20070202641 - Transistor device having an increased threshold stability without drive current degradation: By removing a portion of a halo region or by avoiding the formation of the halo region within the extension region, which may be subsequently formed on the basis of a re-grown semiconductor material, the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may... Agent: Williams, Morgan & Amerson

20070202643 - Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integration: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate (203), first and second gate electrodes (219) disposed over the substrate, each of said first and second gate electrodes having first and second sidewalls, and first... Agent: Fortkort & Houston P.C.

20070202644 - Schottky-barrier mos transistor on a fully-depleted semiconductor film and process for fabricating such a transistor: This process for manufacturing a Schottky-barrier MOS transistor on a fully depleted semiconductor film may include depositing a first layer of a first sacrificial material on an active zone of the substrate, forming a silicon layer on top of the first layer of sacrificial material, forming a gate region on... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070202642 - Thermally stable bicmos fabrication method and bipolar junction transistors formed according to the method: A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed... Agent: Hitt Gaines, PC Lsi Corporation

20070202645 - Method for forming a deposited oxide layer: An oxide layer formed by deposition is subject to a treatment process to repair bond defects of the oxide layer. In one embodiment, the layer is treated with nitric oxide. In one embodiment, a nitric oxide gas is flowed over the dielectric layer at an elevated temperature. In still another... Agent: Freescale Semiconductor, Inc. Law Department

20070202648 - Memory device and method of manufacturing the same: Provided is a memory device comprising a substrate, a source region, and a drain region that may be formed in the substrate and spaced apart from each other, a memory cell that may be formed on the surface of the substrate, connecting the source region and the drain region, and... Agent: Harness, Dickey & Pierce, P.L.C

20070202646 - Method for forming a flash memory floating gate: A flash memory cell with an improved floating gate electrode and method for forming the same, the method including providing a semiconductor substrate active area electrically isolated by STI structures; forming a gate dielectric over the semiconductors substrate; forming a nitride mask layer on the gate dielectric and forming an... Agent: Tung & Associates Suite 120

20070202647 - Method for manufacturing non volatile memory cells integrated on a semiconductor substrate: Non volatile memory cells are integrated on a semiconductor substrate, each cell comprising a floating gate electrode. These cells are made by depositing at least one protective layer on the semiconductor substrate, forming a first plurality of openings in the protective layer, etching the semiconductor substrate through the first plurality... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20070202650 - Low voltage power mosfet device and process for its manufacture: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are... Agent: Ostrolenk Faber Gerb & Soffen

20070202649 - Semiconductor device and method of manufacturing the same: In order to produce a MOS transistor having a gate electrode on a slope, patterning is first performed for a lower-layer gate electrode film near a lower end of the slope. A space between the lower-layer gate electrode films is filled with a filler so that the filler has the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070202652 - Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance: Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20070202651 - Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors: A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor... Agent: Freescale Semiconductor, Inc.

20070202653 - Technique for forming a strained transistor by a late amorphization and disposable spacers: By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may... Agent: Williams, Morgan & Amerson

20070202654 - Spacer and process to enhance the strain in the channel with stress liner: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide... Agent: Greenblum & Bernstein, P.L.C

20070202655 - Method of providing a via opening in a dielectric film of a thin film capacitor: An embedded passive structure, its method of formation, and its integration onto a substrate during fabrication are disclosed. A method comprises providing a thin film capacitor laminate that comprises: a high-k ceramic dielectric film; a conductive film disposed on one side of the high-k ceramic dielectric film; and a first... Agent: Intel Corporation C/o Intellevate, LLC

20070202656 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device includes forming a first electrode, sequentially forming a first dielectric film, a conductive film for a second electrode, a second dielectric film, and a conductive film for a third electrode above the first electrode, forming a first pattern on the conductive film for... Agent: Lee & Morse, P.C.

20070202657 - Method for fabricating capacitor in semiconductor device: A method for fabricating a capacitor in a semiconductor device includes forming a stack structure providing a plurality of open regions, the stack structure including an insulation layer and a hard mask pattern, forming a conductive layer over the stack structure and in the open regions, etching a portion of... Agent: Townsend And Townsend And Crew, LLP

20070202658 - Approach for fabricating cantilever probes for probe card assemblies: An approach for fabricating cantilever probes for a probe card assembly includes forming posts on conductive traces on a substrate. A beam panel having beam elements formed therein is aligned to the substrate so that the beam elements are in contact with the plurality of posts. Each beam element is... Agent: Hickman Palermo Truong & Becker, LLP

20070202659 - Finfet body contact structure: A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070202661 - Semiconductor substrate, production method thereof and semiconductor device: [ Solution ] Production method of a semiconductor substrate, constructed by laminating a support substrate 53, a buried insulating film 52 and an element formative layer 51 in this order and having a trench 56 in the element formative layer 51 for separating an element, comprises a process forming one... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070202660 - Method for producing mixed stacked structures, different insulating areas and/or localised vertical electrical conducting areas: S

20070202662 - Managing integrated circuit stress using dummy diffusion regions: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20070202663 - Managing integrated circuit stress using stress adjustment trenches: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20070202664 - Chip id applying method suitable for use in semiconductor integrated circuit: The present invention provides a chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, marks different every chip are formed in a transfer mask (hereinafter called “mark... Agent: Volentine & Whitt PLLC

20070202665 - Deposition pattern for eliminating backside metal peeling during die separation in semiconductor device fabrication: A semiconductor wafer that includes a plurality of groups of active devices or circuits on a first side of the wafer and a patterned electrical contact on the backside of the wafer. Each group consisting of an active device or circuit is intended to be diced into a discrete chip.... Agent: Emcore Corporation

20070202666 - Method for fabricating semiconductor device: After a fluid film is formed by supplying a material with fluidity to the surface of a substrate formed with a stepped layer, the fluid film is pressed against the substrate by a pressing member having a planar pressing surface so that the surface of the fluid film is planarized.... Agent: Mcdermott Will & Emery LLP

20070202667 - Method of manufacturing a semiconductor device: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070202668 - Methods for producing uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors using sequential laterial solidification: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homoginizing each modulated... Agent: Baker Botts L.L.P.

20070202669 - Epitaxial growth method and semiconductor device fabrication method: An epitaxial growth method and a semiconductor device fabrication method that improve selectivity in epitaxial growth. A gate electrode is formed over an Si substrate with a gate insulating film there between (step S1). An insulating layer is formed on the sides of the gate electrode (step S2). Portions in... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070202670 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes: forming a gate material over a substrate; etching the gate material to form gate patterns each including a portion of the gate material remaining over the substrate; performing a halo ion-implantation process on a portion of the substrate where a bit line... Agent: Mayer, Brown, Rowe & Maw LLP

20070202672 - Method and apparatus for using flex circuit technology to create a reference electrode channel: A method of creating a sensor that may include applying a first conductive material on a first portion of a substrate to form a reference electrode and depositing a first mask over the substrate, the first mask having an opening that exposes the reference electrode and a second portion of... Agent: Edwards Lifesciences Corporation

20070202671 - Method for forming fine pattern of semiconductor device: A method for forming a fine pattern of a semiconductor device include forming a stack structure including a 1st layer hard mask film to a nth layer hard mask film (n is an integer ranging from 2 or more) over an underlying layer formed over a semiconductor substrate. The nth... Agent: Townsend And Townsend And Crew, LLP

20070202673 - Article comprising metal oxide nanostructures and method for fabricating such nanostructures: This invention discloses novel field emitters which exhibit improved emission characteristics combined with improved emitter stability, in particular, new types of carbide or nitride based electron field emitters with desirable nanoscale, aligned and sharped-tip emitter structures.... Agent: Harness, Dickey & Pierce, P.L.C

20070202674 - Vertical fet with nanowire channels and a silicided bottom contact: A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.... Agent: Scully, Scott, Murphy & Presser, P.C.

20070202675 - Method for separately optimizing spacer width for two transistor groups using a recess spacer etch (rse) integration: A method for making a semiconductor device is provided. In accordance with the method, a semiconductor structure is provided which comprises (a) a substrate (203), (b) first (219) and second (220) gate electrodes disposed over the substrate, and (c) first (223) and second (225) sets of spacer structures disposed adjacent... Agent: Fortkort & Houston P.C.

20070202679 - Method for fabricating contact plug of semiconductor device: A method for fabricating a contact plug of a semiconductor device includes forming an insulation layer over a substrate, forming a hard mask over the insulation layer, etching the insulation layer to form a contact hole, removing the hard mask, forming a conductive layer to fill the contact hole, performing... Agent: Blakely Sokoloff Taylor & Zafman

20070202678 - Catalytically enhanced atomic layer deposition process: A method for carrying out a damascene process to form an interconnect comprises providing a semiconductor substrate having a trench etched into a dielectric layer, wherein the trench includes a barrier layer and an adhesion layer, depositing a copper seed layer onto the adhesion layer using an ALD process, depositing... Agent: Intel Corporation C/o Intellevate, LLC

20070202677 - Contact formation: The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of... Agent: Brooks, Cameron & Huebsch , PLLC

20070202676 - Integration scheme for cu/low-k interconnects: A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one... Agent: Slater & Matsil, L.L.P.

20070202681 - Bumping process: A bumping process including the following steps is provided. A main body with a plurality of contacts thereon is provided. A protective layer with a plurality of first openings is formed on the main body. The first openings in the protective layer expose the respective contacts. An under-bump-metallurgy layer is... Agent: J.c. Patents, Inc. Suite 250

20070202682 - Manufacturing method of semiconductor device: In the step which forms a plating film (for example, Ni film) by an electrolytic plating method on the surface of an electrode pad, the first layer is formed in the front surface of the electrode pad with the first current density, and the second layer is formed in the... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070202680 - Semiconductor packaging method: A method of packaging one or more semiconductor dice (10) includes providing a heat spreader (12) and attaching a first semiconductor die (10) to the heat spreader (12). A first set of bumps (14) is formed on respective die pads on a top surface (16) of the first die (10)... Agent: Freescale Semiconductor, Inc. Law Department

20070202683 - Stacked contact bump: A novel method for providing bump structures that can be formed by conventional stud bump bonding techniques is disclosed. The bumps can be arranged in a buttressed configuration that allows for substantial lateral and vertical contact loads, and substantial heights. A side-by-side configuration may be used to build a stacked... Agent: Manuel F. De La Cerra

20070202684 - High performance system-on-chip inductor using post passivation process: A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.... Agent: Megica Corporation

20070202685 - High performance system-on-chip inductor using post passivation process: A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.... Agent: Megica Corporation

20070202686 - Method of electro-depositing a conductive material in at least one through-hole via of a semiconductor substrate: A method of electro-depositing a conductive material in at least one through-hole via of a semiconductor substrate, said through-hole via having an effective aspect ratio, said method including supplying an initial pulse current cycle to the via, said pulse current cycle including a forward pulse current, and a reverse pulse... Agent: Crockett & Crockett

20070202687 - Method for fabricating capacitor: A method for fabricating a semiconductor device includes forming an insulation structure over a substrate structure including contact plugs, etching the insulation structure to form opening regions each of which has a lower opening portion having a critical dimension wider than an upper opening portion, and forming a conductive layer... Agent: Blakely Sokoloff Taylor & Zafman

20070202691 - Method for fabricating a semiconductor device with self-aligned contact: A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, planarizing the insulation layer until... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070202688 - Method for forming contact opening: A method for forming a contact opening is described. A substrate formed with a semiconductor device thereon is provided, and then an etch stop layer, a dielectric layer and a patterned photoresist layer are formed sequentially over the substrate. The exposed dielectric layer and 20% to 90% of the thickness... Agent: J.c. Patents, Inc.

20070202690 - Method of making openings in a layer of a semiconductor device: A method of making a semiconductor device including forming a first sacrificial layer over a first layer to be etched, the first sacrificial layer having a plurality of openings formed therethrough exposing a portion of the first layer; forming a first photoresist layer over the first sacrificial layer and filling... Agent: Tung & Associates Suite 120

20070202689 - Methods of forming copper vias with argon sputtering etching in dual damascene processes: A method of forming a via using a dual damascene process can be provided by forming a via in an insulating layer above a lower level copper interconnect and etching into a surface of the lower level copper interconnect in the via using Argon (Ar) sputtering. Then a trench is... Agent: Myers Bigel Sibley & Sajovec

20070202692 - Method for forming silicide and method for fabricating semiconductor device: A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrate); and after the introduction... Agent: Oliff & Berridge, PLC

20070202693 - Method of and apparatus for forming three-dimensional structures integral with semiconductor based circuitry: Enhanced Electrochemical fabrication processes are provided that can form three-dimensional multi-layer structures using semiconductor based circuitry as a substrate. Electrically functional portions of the structure are formed from structural material (e.g. nickel) that adheres to contact pads of the circuit. Aluminum contact pads and silicon structures are protected from copper... Agent: Microfabrica Inc. Att: Dennis R. Smalley

20070202694 - Method of forming a layer and method of removing reaction by-products: In a method of forming a layer, a titanium layer and a titanium nitride layer may be successively formed on a first wafer. By-products adhered to the inside of a chamber during the formation of the titanium nitride layer may be removed from the chamber. Processes of forming the titanium... Agent: Harness, Dickey & Pierce, P.L.C

20070202695 - Method for fabricating a semiconductor device: A semiconductor device fabrication method that prevents an increase in junction leakage current in a semiconductor device in which nickel silicide is used as a gate electrode, a source electrode, and a drain electrode. A native oxide film formed on the surface of a semiconductor substrate where a gate region,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070202696 - Method of manufacturing solid-state imaging device and solid-state imaging device: After electrode pads 20 formed on a silicon substrate 1 and an electrode 21 to be connected thereto are exposed, a photoelectric conversion layer 12 is formed via a first mask 23 which covers exposed surfaces of the electrode pads 20 and the electrode 21. Then, a second electrode 13... Agent: Sughrue-265550

20070202697 - Method for forming fine pattern of semiconductor device: A method for forming a fine pattern of a semiconductor device comprises the steps of: forming a first hard mask pattern having a width of W1 and a thickness of T1 over an underlying layer formed over a semiconductor substrate; forming a second hard mask film with a planar type... Agent: Townsend And Townsend And Crew, LLP

20070202698 - Methods for fabricating one or more metal damascene structures in a semiconductor wafer: Methods for fabricating one or more metal (e.g., copper) damascene structures in a semiconductor wafer use at least three polishing steps to reduce erosion topography in the resulting metal damascene structures and/or increase throughput. The polishing steps may be performed at four polishing units of a polishing apparatus, which may... Agent: Wilson & Ham

20070202699 - Electronic component fabrication method: A method for fabricating an electronic component, includes forming a seed film above a base body, cooling said seed film, and putting the cooled seed film into a plating solution to perform electro-plating with said seed film being as a cathode.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070202701 - Plasma etching apparatus and method: A plasma etching apparatus includes an evacuable processing chamber for performing a plasma etching process on a target object; a mounting table for mounting thereon the target object in the processing chamber; and a shower head facing the mounting table, for introducing a processing gas for generating a plasma to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070202700 - Etch methods to form anisotropic features for high aspect ratio applications: Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively... Agent: Patterson & Sheridan, LLP

20070202703 - Polishing composition and polishing method: A polishing composition contains silica abrasive grains and an iodine compound. The silica abrasive grains exhibit a negative zeta potential in the polishing composition. The silica abrasive grains have an average primary particle size of 30 nm or smaller, and the polishing composition has a pH of 4 or lower.... Agent: Vidas, Arrett & Steinkraus, P.A.

20070202702 - Chemical mechanical polishing process: A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to... Agent: Baker & Mckenzie LLP Patent Department

20070202704 - Method for etching platinum and method for fabricating capacitor using the same: A method for etching platinum (Pt) includes etching a platinum layer using a gas mixture including a fluorine (F) containing gas and an inert gas. A method for fabricating a capacitor having a bottom electrode, a dielectric layer, and an upper electrode includes forming the bottom electrode by etching a... Agent: Blakely Sokoloff Taylor & Zafman

20070202705 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a plurality of etch mask patterns over an etch target layer, each of the etch mask patterns including a first hard mask, a first pad layer, and a second pad layer, forming spacers on both sidewalls of the etch mask patterns,... Agent: Blakely Sokoloff Taylor & Zafman

20070202706 - Method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate: A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.... Agent: Patent Counsel Applied Materials, Inc.

20070202707 - Ion implantation for increasing etch rate differential between adjacent materials: Ion implantation is used to modify the chemical properties of portions of a material, such that the modified portions respond differently to a chemical etching operation than do the unmodified portions of the material. In a further aspect of the present invention, ion implants into a wafer are performed at... Agent: Raymond J. Werner

20070202709 - Mold and method of manufacturing display device: A mold for a display device, comprising a supporting frame; at least one pattern forming part provided on a surface of the supporting frame; and a protrusion projecting from the supporting frame and disposed along the circumference of the pattern forming part, an inside wall of the protrusion toward the... Agent: Macpherson Kwok Chen & Heid LLP

20070202708 - Method for forming a deposited oxide layer: An insulating layer formed by deposition is annealed in the presence of radical oxygen to reduce bond defects. A substrate is provided. An oxide layer is deposited overlying the substrate. The oxide layer has a plurality of bond defects. The oxide layer is annealed in the presence of radical oxygen... Agent: Freescale Semiconductor, Inc. Law Department

20070202710 - Method for fabricating semiconductor device using hard mask: A method for fabricating a semiconductor device includes forming a layer to be etched, forming a hard mask pattern over the layer, and etching the layer to form a pattern. The hard mask pattern has an atomic percentage of a silicon-hydrogen bond varying with a thickness of the hard mask... Agent: Blakely Sokoloff Taylor & Zafman

20070196939 - Method of manufacturing light emitting diode package: A method of manufacturing a light emitting diode package. A cup-shaped package structure with a recess formed therein and an electrode structure formed on a bottom of the recess is prepared. A light emitting diode chip is mounted on a bottom of the recess with a terminal of the chip... Agent: Mcdermott Will & Emery LLP

20070196940 - Mold and manufacturing method for display device: A mold for a display device, comprises a supporting frame; the supporting frame comprising at least one depressed pattern forming part on a first side of the supporting frame, and an organic layer removing part which is formed on a circumference of the pattern forming part, the pattern forming part... Agent: Macpherson Kwok Chen & Heid LLP

20070196938 - Nitride semiconductor device and method for fabricating the same: A nitride semiconductor device includes: a first nitride semiconductor whose surface is etched; and a second nitride semiconductor formed on the etched surface of the first nitride semiconductor. Of oxygen, carbon, and silicon contained in the interface between the first and second nitride semiconductors, at least silicon has a concentration... Agent: Mcdermott Will & Emery LLP

20070196941 - Method for manufacturing a bottom substrate of a liquid crystal display: A method for manufacturing a bottom substrate of a liquid crystal display device is disclosed. The method is achieved by proceeding two lithography processes cycles with a single mask. Therefore, the method of the present invention can manufacture a bottom substrate through five lithography processes cycles with only four masks.... Agent: Bacon & Thomas, PLLC

20070196946 - Method for forming thin film structure and thin film structure, oscillation sensor, pressure sensor, and acceleration sensor: A method for forming a thin film structure, which has small tensile stress due to controlled mechanical stress, and is made to be conductive, is provided. A lower film including polysilicon thin film is formed on a substrate such as Si substrate, then an impurity such as P is doped... Agent: Osha Liang L.L.P.

20070196947 - Methods of fabricating image sensors: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor... Agent: Harness, Dickey & Pierce, P.L.C

20070196949 - Method for packaging organic light emitting display with frit seal and reinforcing structure: Disclosed is a method for packaging an organic light emitting display having a reinforcing member between a first substrate and a second substrate by rolling a roll retaining a curable material on non-pixel regions of unit display panels. Organic light emitting pixel arrays are formed at a plurality of pixel... Agent: Knobbe Martens Olson & Bear LLP

20070196932 - Method for forming ferroelectric capacitor and method for fabricating semiconductor device: A ferroelectric capacitor formation method necessary for stably fabricating an FeRAM and a semiconductor device fabrication method. After a PZT film is deposited on a lower electrode layer, the PZT film is crystallized by performing heat treatment in an atmosphere of a mixed gas which contains O2 gas and Ar... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070196933 - Method for production of mram elements: Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied... Agent: Dickstein Shapiro LLP

20070196936 - Method of evaluating semiconductor device and method of manufacturing semiconductor device: The method of evaluating a semiconductor device having plural semiconductor elements comprised of an insulating film and an electrode on a semiconductor substrate including, dividing the surface of the semiconductor substrate into plural measurement regions comprising plural semiconductor elements, and in each of the measurement regions, applying current to the... Agent: Greenblum & Bernstein, P.L.C

20070196935 - Prediction of esl/ild remaining thickness: A method for determining a remaining thickness of a dielectric layer at the bottom of an opening in an integrated circuit is provided. The method includes providing a substrate, forming a dielectric layer over the substrate, forming an opening in the dielectric layer, grounding the substrate, scanning the substrate using... Agent: Slater & Matsil, L.L.P.

20070196934 - Predictions of leakage modes in integrated circuits: A method for determining leakage currents in integrated circuits is provided. The method includes providing a substrate comprising a target structure having a first region and a second region, grounding the second region, scanning the substrate using a scanning electron microscope to produce a voltage contrast (VC) image, determining a... Agent: Slater & Matsil, L.L.P.

20070196937 - Quantum dot manipulating method and quantum dot production/manipulation apparatus: m

20070196942 - Method for producing group iii nitride crystal, group iii nitride crystal obtained by such method, and group iii nitride substrate using the same: In a nitrogen-containing atmosphere, a Group III nitride crystal is grown in a flux that includes at least one Group III element selected from Ga, Al, and In, an alkali metal, and Mg, thereby forming a Group III nitride substrate. Since Mg is a p-type dopant for the Group III... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070196944 - Electrical conditioning of mems device and insulating layer thereof: A method of fabricating a MEMS device includes conditioning of an insulating layer by applying a voltage across the insulating layer via a conductive sacrificial layer for a period of time, prior to removal of the conductive sacrificial layer. This conditioning process may be used to saturate or stabilize charge... Agent: Knobbe Martens Olson & Bear LLP

20070196945 - Process for wafer level treatment to reduce stiction and passivate micromachined surfaces and compounds used therefor: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses... Agent: Weingarten, Schurgin, Gagnebin & Hayes LLP

20070196943 - Tightness test for disk bond connections and test structure for carrying out said method: A process and a test structure for testing the hermeticity of bond connections are described. Points are provided on the wafer pair to be connected, at which hermetically closed cavities are additionally formed upon the connection of the wafers, e.g., as they are customary in microelectromechanical systems (MEMS). A pressure... Agent: Stevens & Showalter LLP

20070196948 - Stacked chip-based system and method: A system has multiple discrete functional system subcomponents which, when interconnected form the system, each of the subcomponents being on a discrete substrate and being electrically interconnected to at least one of the other subcomponents by a through-chip via. A method of creating a system involves creating multiple discrete chips,... Agent: Morgan & Finnegan, L.L.P.

20070196951 - Method of manufacturing high power array type semiconductor laser device: A method of manufacturing an array type semiconductor laser device. The method includes forming first and second electrodes on lower and upper surfaces of a wafer comprising a plurality of semiconductor laser arrays having a plurality of laser emission regions, and forming a metal bonding layer on the second electrode... Agent: Mcdermott Will & Emery LLP

20070196950 - Semiconductor device and manufacturing the same: Disclosed is a semiconductor device which makes it easy to design a wiring pattern for a wiring substrate on which the semiconductor device is to be mounted. In manufacturing plural semiconductor devices for providing different amounts of output current, arrangements and numbers of leads to which semiconductor chips for power... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070196952 - Manufacturing method of semiconductor device: A substrate having an element mounting portion is placed on a suction stage having a suction hole. The suction hole is provided so as to suck a region excluding the element mounting portion of the substrate. Otherwise, the suction hole has a hole size of not less than 0.5 mm... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070196953 - Method and apparatus for forming stacked die and substrate structures for increased packing density: A stacked semiconductor apparatus has at least one die attached to a first side of a carrier substrate. A first circuitized substrate is attached to the first side of the carrier substrate and overlying the at least one die in a manner such that the first circuitized substrate serves as... Agent: Cantor Colburn LLP - IBM Fishkill

20070196954 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device, includes i) a step of providing a transparent member above a main surface of a semiconductor substrate where a plurality of semiconductor elements is formed; ii) a first dividing step of dividing the transparent member corresponding to a designated area of the semiconductor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070196955 - Manufacturing method of semiconductor device: The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070196956 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070196957 - Method of resin sealing electronic part: A method of resin sealing an electronic part, includes the steps of: providing a board where one or more of the electronic parts are mounted in an upper mold; melting a resin material received in a cavity forming part of a lower mold; and dipping the electronic part held by... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070196958 - Method for using partitioned masks to build a chip: A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom... Agent: Hoffman, Warnick & D'alessandro LLC

20070196959 - Thin film transistor circuit and display utilizing the same: There is provided a method of easily forming thin film transistors having the same characteristics in fabricating a differential circuit or a current mirror circuit utilizing two thin film transistors made of a polycrystalline silicon semiconductor. Four each thin film transistors are used in a differential circuit and a current... Agent: Fish & Richardson P.C.

20070196960 - Semiconductor device and method of manufacturing the same: The lip-type seal of the present invention is a lip-type seal with which the outer periphery of a rotational shaft (S) supported by a predetermined housing (H) is sealed. The lip-type seal is made up of a first annular reinforcing member (11) and a first sealing member (12). The first... Agent: Eric Robinson

20070196961 - Gate cd trimming beyond photolithography: A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a... Agent: Texas Instruments Incorporated

20070196962 - Method for manufacturing thin film transistor: An object of the invention is to provide a method for manufacturing a thin film transistor in a self-aligning manner by using the droplet discharging method regardless of the accuracy of a discharge position for a droplet discharging device. In view of the object, an organic resin film or the... Agent: Nixon Peabody, LLP

20070196963 - Poly filled substrate contact on soi structure: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070196964 - Thin film transistor array panel and method of manufacturing the same: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes... Agent: Cantor Colburn, LLP

20070196965 - Manufacturing method of semiconductor device: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom.... Agent: Mcdermott Will & Emery LLP

20070196967 - Laser beam micro-smoothing: The present invention provides laser beam micro-smoothing for laser annealing systems. Laser beam micro-smoothing comprises shifting a laser beam in the direction perpendicular to the scanning direction (y) of a laser annealing system, while holding the laser beam fixed in the direction of scanning (x). The shifting may be accomplished,... Agent: Stallman & Pollock LLP

20070196968 - Beam irradiation apparatus, beam irradiation method, and method for manufacturing semiconductor device: The speed of the laser scanned by the scanning means such as a galvanometer mirror or a polygon mirror is not constant in the center portion and in the end portion of the scanning width. As a result, the object, for example an amorphous semiconductor film, is irradiated with the... Agent: Eric Robinson

20070196966 - Method of manufacturing insulating film, method of manufacturing transistor, and method of manufacturing electronic device: A method of manufacturing an insulating film includes coating a first liquid material in which polysilazane is dissolved on a substrate; decreasing dangling bonds of silicon (Si) in the first liquid material; after decreasing the dangling bonds, coating a second liquid material which is similar to the first liquid material... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070196969 - Semiconductor device and method of manufacturing the same: The sizes of crystal masses are made to be a uniform in a crystalline silicon film obtained by a thermal crystallization method in which a metal element is used. An amorphous silicon film to be crystallized is doped with a metal element that accelerates crystallization, and then irradiated with laser... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070196970 - Method for manufacturing a semiconductor device using a nitrogen containing oxide layer: The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure over a substrate, the gate structure including a gate electrode located over a nitrided gate dielectric, and forming a... Agent: Texas Instruments Incorporated

20070196973 - Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels: Integrated circuit field effect transistors are manufactured by forming a pre-active pattern on a surface of a substrate, while refraining from doping the pre-active pattern with phosphorus. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the... Agent: Myers Bigel Sibley & Sajovec

20070196971 - Scalable embedded eeprom memory cell: The present invention includes a method and a resultant device that have components that may be formed below a limit of resolution of optical lithography by utilizing spacers to separate laterally displaced features (i.e., features that have spatial dimensions less than the limit of resolution in planes parallel to a... Agent: Schneck & Schneck

20070196972 - Semiconductor device having carrier mobility raised by generating strain in channel region and its manufacture method: A transistor is formed in the active region of a semiconductor substrate. A sidewall structure is disposed on the sidewalls of a gate electrode. A stress control film covers the semiconductor substrate. The sidewall structure includes a first portion extending along partial upper sidewalls of the gate electrode, a second... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070196974 - Semiconductor device including bipolar junction transistor with protected emitter-base junction: A method of manufacturing a CMOS-BJT semiconductor device comprises the steps of: forming a collector region of a first conductivity type and a first well of the first conductivity type, simultaneously in a semiconductor substrate; forming a second well of a second conductivity type opposite to said first conductivity type,... Agent: Dickstein Shapiro LLP

20070196975 - Metal-polishing liquid and polishing method using the same: The present invention provides a metal-polishing liquid, comprising polishing particles and a chemical component, wherein the polishing particles have charges of surface potential of the same polarity as the charges of surface potential on the reaction layer, adsorption layer or the mixed layer thereof formed by the chemical component on... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070196976 - Semiconductor device: A dose of arsenic for an extension region in an NMOS transistor is in a range from 5×1014 to 2×1015 ions/cm2 and preferably in a range from 1.1×1015 to 1.5×1015 ions/cm2. Also, in addition to arsenic, a low concentration of phosphorus is doped into the extension region by ion implantation.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070196977 - Capacitance dielectric layer, capacitor and forming method thereof: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits... Agent: J.c. Patents, Inc. Suite 250

20070196978 - Integrated circuitry comprising a pair of adjacent capacitors: The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically... Agent: Wells St. John P.s.

20070196981 - Active matrix type liquid crystal display device: An active matrix type liquid crystal display includes a first substrate, a second substrate, and a liquid crystal layer interposed between them. A plurality of common lines are provided on the second substrate, and a first dielectric layer provided with contact holes is fonned on the second substrate and covers... Agent: Birch Stewart Kolasch & Birch

20070196979 - Flip chip in package using flexible and removable leadframe: A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer... Agent: Conley Rose, P.C. David A. Rose

20070196980 - Line edge roughness reduction: A method for reducing line edge roughness comprises forming a masking structure on a substrate assembly, wherein the substrate assembly includes a number of layers. The method includes forming a layered masking structure by depositing a layer of material on the masking structure in order to reduce a line edge... Agent: Brooks, Cameron & Huebsh , PLLC

20070196983 - Method of manufacturing non-volatile memory device: A method of manufacturing a non-volatile memory device includes the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed in an active region, and an isolation layer is formed in an isolation region, forming a dielectric layer over the semiconductor... Agent: Marshall, Gerstein & Borun LLP

20070196984 - Nonvolatile memory device, layer deposition apparatus and method of fabricating a nonvolatile memory device using the same: Provided are a nonvolatile memory device, a layer deposition apparatus and a method of fabricating a nonvolatile memory device using the same. The apparatus may include a chamber capable of holding a substrate, a particle-discharging target discharging particles toward the substrate, and a first ion beam gun accelerating a first... Agent: Harness, Dickey & Pierce, P.L.C

20070196982 - Nrom non-volatile mode of operation: Programming a NVM memory cell such as an NROM cell by using hot hole injection (HHI), followed by channel hot electron (CHE) injection. CHE injection increases the threshold voltage (Vt) of bits of memory cells that were disturbed (unnecessarily programmed) in HHI programming step. Page Write may be performed using... Agent: Empk & Shiloh, LLP

20070196985 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070196986 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device including a substrate, a memory cell region including first pattern, first guard ring around the memory cell, second guard ring around the first guard ring, an isolation region between the first and second guard ring, and a peripheral circuit region around the second... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070196987 - Pseudomorphic si/sige/si body device with embedded sige source/drain: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the... Agent: Greenblum & Bernstein, P.L.C

20070196988 - Poly pre-doping anneals for improved gate profiles: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant... Agent: Hamilton & Terrile, LLP

20070196989 - Semiconductor device with strained transistors and its manufacture: A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070196990 - Method for fabricating metal-oxide semiconductor transistors: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer... Agent: North America Intellectual Property Corporation

20070196991 - Semiconductor device having a strain inducing sidewall spacer and a method of manufacture therefor: The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure over a substrate, and forming a strain inducing sidewall spacer proximate a sidewall of the gate structure, the strain inducing sidewall configured... Agent: Texas Instruments Incorporated

20070196992 - In-situ doped silicon germanium and silicon carbide source drain region for strained silicon cmos transistors: A method for forming a semiconductor integrated circuit device, e.g., MOS, CMOS. The method includes providing a semiconductor substrate, e.g., silicon substrate, silicon on insulator. The method includes forming a dielectric layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the semiconductor substrate. The method also includes forming a gate... Agent: Townsend And Townsend And Crew, LLP

20070196993 - Semiconductor element: A Schottky diode includes a substrate, a channel layer formed on the substrate and made of nitride-based compound semiconductor, an anode electrode and a cathode electrode which constitute an end portion of the current path of the semiconductor element, and a dummy electrode electrically connected to the substrate. The anode... Agent: Howard & Howard Attorneys, P.C.

20070196994 - Method of fabricating semiconductor device including planarizing conductive layer using parameters of pattern density and depth of trenches: A method of fabricating a semiconductor device includes forming a conductive layer on an insulating layer having a plurality of trenches on a semiconductor substrate, such that the conductive layer fills in the plurality of trenches formed in the insulating layer, and calculating a target eddy current value to measure... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070196995 - Method for manufacturing simox wafer: There is obtained an MLD-SIMOX wafer having a BOX layer with a thin film thickness that allows a reduction in SOI layer surface roughness and interface roughness of the BOX layer and the SOI layer and an improvement in breakdown voltage. In a method for manufacturing a SIMOX wafer comprising... Agent: Reed Smith, LLP Attn: Patent Records Department

20070196997 - Method of forming isolation structure of semiconductor device: A method for forming an isolation structure of a semiconductor device includes forming an isolation trench on a semiconductor substrate. A first insulating layer is formed over the isolation trench and the substrate. A spin-on-dielectric (SOD) insulating layer is formed over the first insulation layer, the SOD insulating layer filling... Agent: Townsend And Townsend And Crew, LLP

20070196996 - Semiconductor devices and methods of manufacturing thereof: Semiconductor devices and methods of manufacturing thereof are disclosed. Isolation regions are formed that include a stress-altering material at least partially lining a trench formed within a workpiece. The isolation regions include an insulating material disposed over the stress-altering material.... Agent: Slater & Matsil LLP

20070196998 - System and method for forming moveable features on a composite substrate: A method for forming moveable features suspended over a substrate is described, wherein a cavity beneath the moveable feature is first formed using a liquid etchant applied through one or more release holes. After formation of the cavity, the outline of the moveable feature is formed using a dry etch... Agent: Jaquelin K. Spong Apt. A1

20070197000 - Method of manufacturing chip resistors: A method of manufacturing chip resistors has steps of cutting grooves in a substrate, forming through holes, defining chip regions, forming main electrodes, forming resistor layers, forming first protective layers, forming stripped protective layers, forming inner electrodes, removing the stripped protective layers, plating outer electrodes and cutting the substrate. The... Agent: Hershkovitz & Associates

20070197001 - Method of manufacturing chip resistors: A method of manufacturing chip resistors has steps of cutting grooves on a substrate, forming through holes, defining chip regions, forming main electrodes, forming resistor layers, forming primary protective layers, dividing the substrate into multiple strips, forming inner electrodes, cutting the strips into multiple chip resistor units and plating outer... Agent: Charles E. Baxley, Esq.

20070196999 - Method for manufacturing semiconductor device: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at... Agent: Eric Robinson

20070197002 - Method of and mechanism for peeling adhesive tape bonded to segmented semiconductor wafer: An adhesive tape peeling mechanism has an adhering section and a porous member. The adhering section adheres to a segmented semiconductor wafer bonded to adhesive tape. The porous member is provided on the surface adhering to the semiconductor wafer of the adhering section. The porous member is divided into at... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070197004 - Nitride semiconductor component and process for its production: wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μm2 in a layer plane of the coalesced... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070197003 - Flow method and reactor for manufacturing nanocrystals: A population of nanocrystals having a narrow and controllable size distribution and can be prepared by a segmented-flow method.... Agent: Steptoe & Johnson LLP

20070197005 - Delamination resistant semiconductor film and method for forming the same: A method and structure for preventing film delamination provide for forming a thick film then partitioning the thick film into a plurality of discrete portions prior to subsequent thermal processing operations. The partitioning alleviates the effects of film stress at the interface between the film and the underlying material and... Agent: Duane Morris LLPIPDepartment (tsmc)

20070197006 - Method for making a semiconductor device comprising a lattice matching layer: A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070197007 - Method for forming silicon-containing film and method for decreasing number of particles: A method for forming a silicon-containing film is described. A substrate is placed in a reaction chamber, and then a silicon-containing gas is introduced into the reaction chamber to conduct a CVD process and deposit a silicon-containing film on the substrate. During the CVD process, the temperature of at least... Agent: J.c. Patents, Inc. Suite 250

20070197008 - Mirror-like input key: A mirror-like key (40) comprises a base portion (46), a sputtered layer (44) and a lightproof printed layer (42) with a light-pervious label (422). The base portion comprises an upper surface (462) and a lower surface (464) opposite to the upper surface. The sputtered layer is formed on one of... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070197009 - Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (asre) integration: A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor structure (201) is provided which comprises a semiconductor substrate (202), a gate (209) disposed on the semiconductor substrate, and a spacer (219) adjacent to the gate. The structure is subjected to a first... Agent: Fortkort & Houston P.C.

20070197010 - Integrated carbon nanotube sensors: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor,... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070197011 - Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integration: A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor substrate (202) is provided which has a gate (209) disposed thereon and which has a spacer (219) disposed adjacent to the gate. The spacer is subjected to a recess etch which exposes a... Agent: Fortkort & Houston P.C.

20070197014 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device includes forming an interlayer insulating layer on a semiconductor substrate, forming a hard mask layer on the interlayer insulating layer, forming a hard mask pattern in which a plurality of contact hole patterns are formed by patterning the hard mask layer at least... Agent: Mills & Onello LLP

20070197012 - Grain growth promotion layer for semiconductor interconnect structures: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a... Agent: Scully, Scott, Murphy & Presser, P.C.

20070197015 - Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact... Agent: Myers Bigel Sibley & Sajovec

20070197013 - Processed wafer via: An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive... Agent: Morgan & Finnegan, L.L.P.

20070197016 - Semiconductor device and manufacturing method for the same: To provide a low-cost, easy-to-use, and efficient method for manufacturing a semiconductor device, which eliminates the need for the formation or removal of barrier metals upon formation of bumps, and a high-performance semiconductor device with fine bumps arranged at a narrow pitch. The method includes: forming a plurality of electrode... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070197017 - Manufacturing method of semiconductor module: The present invention provides a manufacturing method of a semiconductor module which enables the joining at a low temperature within a short time and can obtain more reliable joining portions by performing the joining without using a solder joining medium. The manufacturing method of a semiconductor module includes a first... Agent: Rossi, Kimms & Mcdowell LLP.

20070197018 - Wafer-leveled chip packaging structure and method thereof: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first... Agent: Bacon & Thomas, PLLC

20070197019 - Liquid crystal display device and manufacturing method thereof: A liquid crystal display device comprises at least two insulating layers formed on a first conductive layer, a second conductive layer formed between the at least two insulating layers, a first contact hole penetrating an upper insulating layer of the at least two insulating layers on the second conductive layer,... Agent: F. Chau & Associates, LLC

20070197021 - Semiconductor device including spacer with nitride/nitride/oxide structure and method for fabricating the same: A method for fabricating a semiconductor device includes: forming a plurality of bit lines; forming an inter-layer insulation layer over the bit lines; etching the inter-layer insulation layer to form a storage node contact hole between the bit lines; forming spacers in a dual structure with different dielectric constants over... Agent: Blakely Sokoloff Taylor & Zafman

20070197020 - Inline method to detect and evaluate early failure rates of interconnects: A method of detecting interconnect defects in a semiconductor device. The method comprises positioning a portion of a semiconductor substrate, having a plurality of interconnects, in a field of view of an inspection tool. A voltage contrast image of the portion is produced. The voltage contrast image is obtained using... Agent: Texas Instruments Incorporated

20070197022 - Manufacture of cadmium mercury telluride: A method of manufacture of cadmium mercury telluride (CMT) is disclosed. The method involves growing one or more buffer layers on a substrate by molecular beam epitaxy (MBE). Subsequently at least one layer of cadmium mercury telluride, Hg1-xCdxTe where x is between 0 and 1 inclusive, is grown by metal... Agent: Nixon & Vanderhye, PC

20070197023 - Entire encapsulation of cu interconnects using self-aligned cusin film: A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer.... Agent: William Stoffel

20070197025 - Multi-chip device and method for manufacturing the same: A multi-chip device includes LED sensors for sensing light separated by a predetermined interval in a wafer, LEDs for emitting light formed over the wafer respectively corresponding to the LED sensors, a driving circuit formed between the LEDs over the wafer, an insulating film over the wafer, and trenches in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070197024 - Interconnect structure and method for semiconductor device: An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the... Agent: Banner & Witcoff, Ltd.

20070197026 - Synthetic resin containers with high gas-barrier property: A synthetic resin container possessing a higher gas barrier property, and having a coating film (2) possessing a higher gas barrier property and positioned on an inner surface and/or and outer surface of the container body, wherein at least the coating film (2) is constituted of: an organic silicon compound... Agent: Oliff & Berridge, PLC

20070197027 - Formation of boride barrier layers using chemisorption techniques: In one embodiment, a method for depositing a boride-containing barrier layer on a substrate is provided which includes exposing the substrate sequentially to a boron-containing compound and a metal precursor to form a first boride-containing layer during a first sequential chemisorption process and exposing the substrate to the boron-containing compound,... Agent: Patterson & Sheridan, LLP

20070197028 - Formation of boride barrier layers using chemisorption techniques: In one embodiment, a method for depositing a boride-containing barrier layer on a substrate is provided which includes exposing the substrate sequentially to a boron-containing compound and a tungsten precursor to form a first boride-containing layer during a first sequential chemisorption process, and exposing the substrate to the boron-containing compound,... Agent: Patterson & Sheridan, LLP

20070197029 - Method for the selective removal of an unsilicided metal: An integrated circuit is silicided by depositing at least one metal on a silicon-containing region and forming a metal silicide. Residue metal that has not been silicided during the formation of the metal silicide is then removed. The removal of the residue metal involves the conversion of the residue metal... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20070197030 - Center pad type ic chip with jumpers, method of processing the same and multi chip package: A center pad type integrated circuit chip and a method of forming the same is presented. The chip comprises an integrated circuit chip having chip pads formed on a center region thereof and a jumper. The jumper includes a buffer layer arranged adjacent to a side of the chip pads... Agent: Marger Johnson & Mccollom, P.C.

20070197031 - Methods for forming rhodium-containing layers such as platinum-rhodium barrier layers: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect... Agent: Mueting, Raasch & Gebhardt, P.A.

20070197032 - Semiconductor device and method for fabricating the same: A semiconductor device in which the diffusion of copper from a wire is prevented and a method for fabricating such a semiconductor device. For example, a via groove and a wire groove are formed in a multilayer structure including a UDC diffusion barrier film, a porous silica film, a middle... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070197034 - Semiconductor device having a sac through-hole: A process for manufacturing a semiconductor device includes the steps of: forming a gate oxide film and a gate electrode on a substrate; forming a SiCN protection film on the gate electrode; depositing an interlayer dielectric film for covering the SiCN protection film; etching the dielectric film in a self-alignment... Agent: Young & Thompson

20070197033 - High aspect ratio contacts: A process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by supplying a first gaseous etchant having at least fifty (50) percent He to a plasma etch reactor, and exposing the insulating layer to a plasma of the first gaseous etchant.... Agent: Brooks, Cameron & Huebsh , PLLC

20070197035 - Wafer and method of producing the same: A wafer is produced at a step of polishing a predetermined face of a wafer to flatten the predetermined face while supplying a polishing liquid onto a bonded abrasive cloth, wherein the bonded abrasive cloth comprises a urethane bonding material consisting of a soft segment having a polyfunctional isocyanate and... Agent: Sughrue Mion, PLLC

20070197036 - Method for manufacturing electro-optic device: A method for manufacturing an electro-optic device includes an electroconductive film forming step that forms an electroconductive film over surfaces of a substrate. A front electroconductive film removing step is also performed which removes the electroconductive film from the front surface of the substrate. A thin layer forming step is... Agent: Advantedge Law Group, LLC

20070197037 - Surface preparation for gate oxide formation that avoids chemical oxide formation: A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an... Agent: Duane Morris LLPIPDepartment (tsmc)

20070197039 - Anisotropic etching method: The present invention consists in a method for anisotropically etching a silicon substrate at very low temperature using a high-density fluorinated gas plasma, characterized in that the plasma is formed from a gas mixture comprising an etching gas containing fluorine, a passivating gas containing oxygen and a reaction gas comprising... Agent: Sughrue Mion, PLLC

20070197038 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a key open mask for coating a cell region in order to a gate polysilicon layer over an overlay vernier region formed in a gate forming process, and removing the gate polysilicon layer of the overlay vernier region while regulating an... Agent: Townsend And Townsend And Crew, LLP

20070197040 - Plasma etching method, plasma etching apparatus, control program and computer-readable storage medium: A plasma etching method includes the step of performing a plasma etching on a silicon-containing dielectric layer formed on a substrate to be processed by using a plasma, while using an organic layer as a mask. The plasma is generated from a processing gas at least including a C6F6 gas,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070197041 - Processing method and plasma etching method: A processing method includes a silicon oxide etching process of performing a plasma etching on a target layer mainly made up of silicon, a silicon oxide layer formed on the target layer and a target object having a previously patterned resist layer formed on the silicon oxide layer, the plasma... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070197042 - Method of varying etch selectivities of a film: A method of patterning a crystalline film. A crystalline film having a degenerate lattice comprising first atoms in a first region and a second region is provided. Dopants are substituted for said first atoms in said first region to form a non-degenerate crystalline film in said first region. The first... Agent: Intel/blakely

20070197043 - Method of manufacturing a semiconductor device and semiconductor device obtained by means of said method: According to the invention, the same dielectric layer (6) is chosen for the first and the second dielectric layer, a lateral size of the second cavity (5) and the thickness of the dielectric layer (6) are chosen such that the second cavity (5) becomes nearly completely filled by the dielectric... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070197045 - Process for the production of highly-textured, band-shaped, high-temperature superconductors: The formation of band-shaped HTSL on a metal substrate is disclosed. The HTSL includes at least one buffer layer comprising zirconates and/or rare-earth oxides. The HTSL layer is formed on the buffer layer. The buffer layer has a texturing that in the case of a RHEED measurement results in discrete... Agent: Edell, Shapiro & Finnan, LLC

20070197044 - Rapid patterning of nanostructures: A process for forming nanostructures comprises generating charged nanoparticles with an electrospray system in a vacuum chamber and introduction of the charged nanoparticles to a region proximate to a charge pattern, so that the particles adhere to the charge pattern in order to form the feature. Two- or three-dimensional nanostructures... Agent: Norma E Henderson Henderson Patent Law

20070197046 - Substrate processing method and substrate processing apparatus: An object of the present invention is to form an interlayer insulating film on a substrate and cure the interlayer insulating film in a time shorter than that in the prior art. The present invention is a substrate processing method in which the interlayer insulating film formed on the substrate... Agent: Rader Fishman & Grauer PLLC

20070197047 - Composition for forming insulation film, insulation film for semiconductor device, and fabrication method and semiconductor device thereof: It is an object of the present invention to provide, with good yields, a composition for forming an insulation film which allows obtaining an insulation film for a semiconductor device having a low dielectric constant, excellent stress resistance and excellent crack resistance; an insulation film for a semiconductor device formed... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070197048 - Semiconductor device and method of fabricating the same:

20070197049 - Method for manufacturing semiconductor device: To provide a method for manufacturing a semiconductor device using a method in which a desired position is rapidly subjected to laser irradiation while switching laser irradiation patterns. With respect to an organic memory element having a structure in which an organic compound layer is interposed between a pair of... Agent: Eric Robinson

20070197051 - High power liquid dielectric switch: Method and apparatus for switching high power at high repetition rates. The apparatus is preferably a switch utilizing a pressurized flowing dielectric. The pressurized dielectric suppresses growth of dielectric breakdown byproducts, such as large bubbles and breakdown contamination, enabling lower dielectric flow rates to remove the byproducts. In addition to... Agent: Peacock Myers, P.C.

20070197050 - Systems and methods for manipulating liquid films on semiconductor substrates: A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diameter defining a liquid-free void. The size... Agent: Trask Britt, P.C./ Micron Technology

20070190670 - Method of making ferroelectric and dielectric layered superlattice materials and memories utilizing same: A method of making a ferroelectric integrated circuit comprising: depositing a thin film of a layered superlattice material using atomic layer deposition (ALD); and completing the integrated circuit. The layered superlattice material is a ferroelectric material or a dielectric material. The method further comprises annealing the thin film using a... Agent: Patton Boggs LLP

20070190674 - Apparatus and method for manufacturing display device: An apparatus for manufacturing a display device includes a stage on which a lower substrate is mounted, the stage including a plurality of lift pins formed on an entire surface of the stage, a gripper that grips at least three point parts of an upper substrate to be positioned above... Agent: Cantor Colburn, LLP

20070190673 - Organic light emitting diode and method of manufacturing the same: An organic light emitting diode includes a plurality of bank portions and light emitting parts formed between the bank portions wherein the bank portions have stepwise portions at ends thereof extending to the light emitting parts. The exemplary embodiments of an organic light emitting diode according to the present invention... Agent: Cantor Colburn, LLP

20070190675 - Manufacturing method of display device: A highly functional and reliable display device with lower power consumption and higher light-emitting efficiency is provided. A light-emitting material is irradiated with light; the light-emitting material irradiated with light is dispersed in a solution containing a binder, and a solution containing the light-emitting material irradiated with light and the... Agent: Fish & Richardson P.C.

20070190679 - Image sensor and method of fabricating the same: An image sensor may include a semiconductor substrate having a pixel array region and a logic region. A first gate electrode may be formed on the pixel array region of the semiconductor substrate. A lower electrode may be formed on a portion of the logic region of the semiconductor substrate.... Agent: Harness, Dickey & Pierce, P.L.C

20070190680 - Mems device and manufacturing process thereof: MEMS devices require special cavity formation and sealing steps such as wafer bonding which reduce the yield and increase the cost. In addition, it is difficult to form a cavity of a large area by the LSI process owing to a residual stress of a sealing film which will be... Agent: Stanley P. Fisher Reed Smith LLP

20070190683 - Phase changeable structure and method of forming the same: The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop... Agent: Marger Johnson & Mccollom, P.C.

20070190669 - Method of manufacturing a magnetoelectronic device: A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating... Agent: Kenneth A. Nelson Bryan Cave LLP

20070190671 - Manufacturing method of semiconductor integrated circuit device and probe card: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070190672 - Electron-emitting device, electron source, image-forming apparatus, and method for producing electron-emitting device and electron-emitting apparatus: A method for producing a durable electron-emitting device having a uniform electron emission characteristic, an electron source, and an image-forming apparatus having a uniform display characteristic for a long period are provided. The method for producing an electron-emitting device according to the present invention includes the steps of: disposing a... Agent: Fitzpatrick Cella Harper & Scinto

20070190676 - Light emitting diodes (leds) with improved light extraction by roughening: Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.... Agent: Patterson & Sheridan, L.L.P.

20070190677 - Semiconductor light emitting element, manufacturing method thereof, integrated semiconductor light emitting device, manufacturing method thereof, image display device, manufacturing method thereof, illuminating device and manufacturing method thereof: A semiconductor light emitting element, manufacturing method thereof, integrated semiconductor light emitting device, manufacturing method thereof, illuminating device, and manufacturing method thereof are provided. An n-type GaN layer is grown on a sapphire substrate, and a growth mask of SiN, for example, is formed thereon. On the n-type GaN layer... Agent: Bell, Boyd & Lloyd, LLP

20070190678 - Nitride semiconductor thin film having fewer defects and method of growing the same: The present invention relates to a nitride semiconductor thin film having less defects and a method of growing the same. According to the present invention, the nitride semiconductor thin film with lower defect density can be manufactured by forming grooves on a substrate, sequentially forming a buffer layer and a... Agent: Birch Stewart Kolasch & Birch

20070190681 - Silicon-on-insulator near infrared active pixel sensor array: A method is provided for forming a near infrared (NIR) active pixel sensor array on a silicon-on-insulator (SOI) substrate. The method forms a first wafer comprising a high resistance first Si substrate and a moderately doped first Si layer, and forms a second wafer comprising a first silicon oxide layer... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070190682 - Patterning of electrodes in oled devices: An OLED device includes pillars, wherein the pillars serve to pattern a conductive layer during deposition. The profile of the pillars covers the edges of at least one functional layer to protect it from exposure to potentially deleterious substances.... Agent: Fish & Richardson P.C.

20070190684 - Precursors for deposition of metal oxide layers or films: Rare earth metal precursors, for use in MOCVD techniques have a ligand of the general formula OCR1(R2)CH2X, wherein R1 is H or an alkyl group, R2 is an optionally substituted alkyl group and X is selected from OR and NR2, wherein R is an alkyl group or a substituted alkyl... Agent: Thompson Coburn, LLP

20070190686 - Method of fabricating substrate with embedded component therein: A method of fabricating a substrate with an embedded component therein including the following steps is provided. First, a core layer having a first dielectric layer, a first patterned circuit layer, and a second patterned circuit layer is provided. The first patterned circuit layer and the second patterned circuit layer... Agent: Jianq Chyun Intellectual Property Office

20070190685 - Cooling facility and method for integrated circuit: An integrated circuit chip has a first part with active circuitry, and a second part with a major surface defining a chamber. The first part covers the second, to enclose the chamber. Inlet and outlet openings are provided in the edge or face of the chip, so that a cooling... Agent: Thomas F. Lenihan Tektronix, Inc.

20070190687 - Image sensor packaging structure and method of manufacturing the same: An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070190688 - Method for manufacturing semiconductor device with protection layer: A method for manufacturing a semiconductor device may comprise preparing a wafer having a front surface and a back surface. The wafer may have a plurality of semiconductor chips and scribe lines between the adjacent semiconductor chips. The wafer may be sawn along the scribe lines to form grooves between... Agent: Marger Johnson & Mccollom, P.C.

20070190689 - Method of manufacturing semiconductor device: A semiconductor substrate in a wafer state having one surface provided thereon a plurality of external connection electrodes is stacked onto a support film. The wafer-state semiconductor substrate stuck on the support film is cut into a plurality of chip size semiconductor substrates, whereby the adjacent semiconductor substrates are separated... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070190690 - Integrated circuit package system with exposed interconnects: An integrated circuit package system is provided including providing a substrate having a first surface and second surface; mounting interconnects to the first surface; mounting integrated circuit dies to the first surface; embedding the interconnects and the integrated circuit die within an encapsulant on the substrate and leaving top portions... Agent: Ishimaru & Zahrt LLP

20070190691 - Wafer level chip packaging: Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of... Agent: Tessera Lerner David Et Al.

20070190692 - Low resistance and inductance backside through vias and methods of fabricating same: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench... Agent: Schmeiser, Olsen & Watts

20070190693 - Semiconductor chip package having an adhesive tape attached on bonding wires: The invention provides a semiconductor chip package, and a means of forming such a semiconductor chip package, in which one or more semiconductor chips are electrically connected to a mounting substrate by wire bonding in which an adhesive tape is provided on the active surface of the semiconductor chips for... Agent: Harness, Dickey & Pierce, P.L.C

20070190694 - Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between... Agent: Ishimaru & Zahrt LLP

20070190695 - Apparatus and method integrating an electro-osmotic pump and microchannel assembly into a die package: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070190696 - Phase change memory cell with high read margin at low power operation: A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material... Agent: Dicke, Billig & Czaja

20070190697 - Electrically programmable fuse for silicon-on-insulator (soi) technology: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline... Agent: International Business Machines Corporation Dept. 18g

20070190698 - Method of edge bevel rinse: A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding the central region on the surface... Agent: North America Intellectual Property Corporation

20070190699 - Electronic device and method of manufacturing the same: An electronic device, in which a flat plate semiconductor and dumets connected to surface electrodes on the front and back surfaces of the semiconductor and to lead wires are encapsulated in a glass tube.... Agent: Miles & Stockbridge PC

20070190700 - Power system inhibit method and device and structure therefor: A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two... Agent: James J. Stipanuk Semiconductor Components Industries, L.L.C.

20070190701 - Pixel structure and thin film transistor and fabrication method thereof: A method of fabricating a thin film transistor is disclosed. First, a substrate is provided and a patterned polysilicon layer is formed on the substrate. A metal layer is formed on the patterned polysilicon layer. Then, a portion of the metal layer is removed so that the remaining metal layer... Agent: J C Patents, Inc.

20070190704 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a silicon substrate, a channel region formed in a surface of the silicon substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, first gate side walls formed on the gate insulating film to sandwich the gate... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070190702 - Strained silicon-on-insulator transistors with mesa isolation: A silicon-on-insulator semiconductor device which includes a substrate; and insulator layer overlying the substrate; a plurality of strained silicon islands overlying the insulator layer, the strained silicon islands are isolated from each other by mesa isolation; and a plurality of transistors formed on the strained silicon islands. A method for... Agent: Randy W. Tung Tung & Associates

20070190703 - Thin film transistor array panel for liquid crystal display and method for manufacturing the same: In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a... Agent: Frank Chau, Esq. F. Chau & Associates, LLP

20070190705 - Method for forming poly-silicon thin-film device: A method for forming a poly-silicon thin-film device, comprising steps of: providing a substrate; forming a poly-silicon film on the substrate, the poly-silicon film comprising a plurality of poly-silicon grains oriented in a grain growth direction; and forming a plurality of thin-film transistors, each of the thin-film transistors including a... Agent: Birch Stewart Kolasch & Birch

20070190707 - Thin film transistor and method of manufacturing thin film transistor: A method of manufacturing a low-cost thin film transistor of minimized variations in performances, as well as the thin film transistor produced thereby. A thin film transistor manufacturing method including the steps of: forming a gate electrode on a substrate; forming a gate insulation layer on the gate electrode; forming... Agent: Brinks Hofer Gilson & Lione

20070190706 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming... Agent: Macpherson Kwok Chen & Heid LLP

20070190709 - Multiple-gate mos transistor and a method of manufacturing the same: Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a... Agent: Lowe Hauptman Berner, LLP

20070190708 - Semiconductor device and method manufacturing semiconductor device: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070190710 - Laser annealing method: In crystallizing an amorphous silicon film by illuminating it with linear pulse laser beams having a normal--distribution type beam profile or a similar beam profile, the linear pulse laser beams are applied in an overlapped manner. There can be obtained effects similar to those as obtained by a method in... Agent: Fish & Richardson P.C.

20070190712 - Semiconductor device having a trench gate and method of fabricating the same: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are... Agent: Quintero Law Office, PC

20070190711 - Semiconductor device and method for incorporating a halogen in a dielectric: A method of forming a semiconductor device, the method includes forming a gate dielectric over the semiconductor substrate, exposing the gate dielectric to a halogen, and incorporating the halogen into the gate dielectric. In one embodiment, the halogen is fluorine. In one embodiment, the gate dielectric is also exposed to... Agent: Freescale Semiconductor, Inc. Law Department

20070190713 - Cmos gate structures fabricated by selective oxidation: A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with conventional resist and etched to form a sacrificial mandrel. The edges of... Agent: International Business Machines Corporation Dept. 18g

20070190714 - Trench transistor and method for fabricating a trench transistor with high-energy-implanted drain: A method is disclosed for fabricating a trench transistor, in which there are formed, within an epitaxial layer deposited above a substrate of a first conductivity type, a trench and, within the trench, a gate dielectric and a gate electrode and, in a body region of a second conductivity type... Agent: Maginot, Moore & Beck Chase Tower

20070190715 - Semiconductor device having sti without divot and its manufacture: The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film covering an inner surface of the isolation... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070190716 - Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same: Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation region and the sidewall of the gate... Agent: Marger Johnson & Mccollom, P.C.

20070190717 - Thin film transistor substrate and fabricating method thereof: A thin film transistor substrate and a fabricating method thereof wherein a contacting size between an electrode and an active layer can be reduced to provide a small and light panel. In the thin film transistor substrate, a conductive layer is formed on the substrate. A first insulating layer for... Agent: Brinks Hofer Gilson & Lione

20070190718 - Dual-damascene process to fabricate thick wire structure: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch... Agent: Greenblum & Bernstein, P.L.C

20070190719 - Method of forming a contact on a semiconductor device: A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are... Agent: Jianq Chyun Intellectual Property Office

20070190721 - Semiconductor memory device having an alloy metal gate electrode and method of manufacturing the same: A semiconductor memory device having an alloy gate electrode layer and method of manufacturing the same are provided. The semiconductor memory device may include a semiconductor substrate having a first impurity region and a second impurity region. The semiconductor memory device may include a gate structure formed on the semiconductor... Agent: Harness, Dickey & Pierce, P.L.C

20070190720 - Method for making an integrated circuit having an embedded non-volatile memory: A method for forming a portion of a semiconductor device includes: patterning gate stack layers overlying a substrate into a gate stack; implanting dopant ions to form shallow source/drain extension implant regions in the substrate adjacent to the gate stack; oxidizing the gate stack at first oxidation conditions to form... Agent: Freescale Semiconductor, Inc. Law Department

20070190723 - Method of fabricating transistor of dram semiconductor device: Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a... Agent: Marger Johnson & Mccollom, P.C.

20070190722 - Method to form upward pointing p-i-n diodes having large and uniform current: A method is disclosed to form an upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic,... Agent: Vierra Magen/sandisk Corporation

20070190725 - Methods of manufacturing semiconductor devices having buried bit lines: A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the... Agent: Myers Bigel Sibley & Sajovec

20070190724 - Semiconductor device: It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070190726 - Semiconductor device and related fabrication method: Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor... Agent: Volentine & Whitt PLLC

20070190727 - Nonvolatile semiconductor memory device and manufacturing method therefor: A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070190728 - Low resistance gate for power mosfet applications and method of manufacture: A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the... Agent: Townsend And Townsend And Crew, LLP

20070190729 - Apparatus and method for reflowing photoresist: A method of and an apparatus for reflowing photoresist ensure that the photoresist is heated uniformly when it reaches a desired temperature at which the photoresist is to reflow. The photoresist reflowing apparatus includes a chamber, a plate disposed within the chamber and on which a substrate having a photoresist... Agent: Volentine & Whitt PLLC

20070190731 - Diffusion layer for semiconductor devices: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A... Agent: Slater & Matsil, L.L.P.

20070190732 - Methods of forming semiconductor devices including fin structures: A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend a greater distance from the substrate than the channel... Agent: Myers Bigel Sibley & Sajovec

20070190730 - Resolving pattern-loading issues of sige stressor: A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielectric, forming a recess in the... Agent: Slater & Matsil, L.L.P.

20070190733 - Transistors of semiconductor devices and methods of fabricating the same: Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070190734 - Asymmetric source/drain transistor employing selective epitaxial growth (seg) layer and method of fabricating same: According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate... Agent: Marger Johnson & Mccollom, P.C.

20070190735 - Method to restore hydrophobicity in dielectric films and materials: Silica dielectric films, whether nanoporous foamed silica dielectrics or nonporous silica dielectrics are readily damaged by fabrication methods and reagents that reduce or remove hydrophobic properties from the dielectric surface. The invention provides for methods of imparting hydrophobic properties to such damaged silica dielectric films present on a substrate. The... Agent: Richard S. Roberts Roberts & Mercanti, LLP

20070190736 - Overlay alignment mark and alignment method for the fabrication of trench-capacitor dram devices: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and... Agent: North America Intellectual Property Corporation

20070190737 - Process for producing soi wafer: There is provided a process for producing an SOI wafer in which, when producing an SOI wafer using Smart Cut technology, the surface can be smoothed after cleaving, the thickness of the SOI layer can be reduced, and the film thickness of the SOI wafer can be made uniform. In... Agent: Kolisch Hartwell, P.C.

20070190738 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a... Agent: Marshall, Gerstein & Borun LLP

20070190739 - Semiconductor having optimized insulation structure and process for producing the semiconductor: A semiconductor having an optimized insulation structure which is simple and inexpensive to produce and can be made smaller than LOCOS insulation structures is disclosed. An implantation mask on a surface of a semiconductor substrate is used to implant elements into the semiconductor substrate, which elements, on thermal activation, form... Agent: Dicke, Billig & Czaja

20070190740 - Enhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistors: Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070190744 - Method for fabricating semiconductor devices: According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon... Agent: Miles & Stockbridge PC

20070190743 - Process for digging a deep trench in a semiconductor body and semiconductor body so obtained: A process for digging deep trenches in a body of semiconductor material includes forming a mask having an opening, above a surface of a semiconductor body. A passivating layer is conformally formed on the mask and on the semiconductor body within the opening. A directional etch is extended to first... Agent: Graybeal, Jackson, Haley LLP

20070190742 - Semiconductor device including shallow trench isolator and method of forming same: A semiconductor device and method of manufacturing include an STI trench having a low-k dielectric material as a liner oxide layer and a bulk oxide trench fill layer.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070190741 - Strained semiconductor device and method of making same: A method of making a semiconductor device is disclosed. An upper surface of a semiconductor body is amorphized and a liner is formed over the amorphized upper surface. The upper surface can then be annealed. A transistor is formed at the upper surface.... Agent: Slater & Matsil LLP

20070190745 - Method to selectively form regions having differing properties and structure: A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate... Agent: Freescale Semiconductor, Inc. Law Department

20070190746 - Substrate processing apparatus: An SOI substrate which has a thick SOI layer is first prepared. Then, the SOI layer is thinned to a target film thickness using as a unit a predetermined thickness not more than that of one lattice. This thinning is performed by repeating a unit thinning step which includes an... Agent: Fitzpatrick Cella Harper & Scinto

20070190749 - Method for producing semiconductor chip: A method for producing many semiconductor chips, each having a semiconductor circuit disposed on the face thereof and a die bonding film stuck to the back thereof, from a semiconductor wafer in which many rectangular regions are defined on its face by streets arranged in a lattice pattern, and the... Agent: Smith, Gambrell & Russell

20070190748 - Wafer dividing method: A method of dividing a wafer which is partitioned by a plurality of first dividing lines extending in a predetermined direction and a plurality of second dividing, lines formed in a direction perpendicular to the plurality of first dividing lines, along the first dividing lines and the second dividing lines,... Agent: Smith, Gambrell & Russell

20070190747 - Wafer level packaging to lidded chips: Methods are provided for making a plurality of lidded microelectronic elements. In an exemplary embodiment, a lid wafer is assembled with a device wafer. Desirably, the lid wafer is severed into a plurality of lid elements to remove portions of the lid wafer overlying contacts at a front face of... Agent: Tessera Lerner David Et Al.

20070190750 - Laser dicing apparatus for a gallium arsenide wafer and method thereof: The present invention discloses a laser dicing apparatus for a gallium arsenide wafer and a method thereof, wherein firstly, a gallium arsenide wafer is stuck onto a holding film; next, the gallium arsenide wafer together with the holding film is disposed on a working table; the gallium arsenide wafer has... Agent: Rosenberg, Klein & Lee

20070190751 - Semiconductor fuses and methods for fabricating and programming the same: A fuse for use in semiconductor devices, semiconductor devices including the fuse, methods of fabricating the fuse, and methods of using the fuse. The fuse includes terminals and a programmable region between the terminals. The programmable region may have less mass than the terminals. The programmable region may include metal... Agent: Trask Britt, P.C./ Micron Technology

20070190752 - Si ribbon, sio2 ribbon and ultra pure ribbons of other substances: A method of purifying substances is described herein, particularly suitable for purifying silica and forming it into silicon oxide sheets or ribbons, or silicon sheets or ribbons. The method includes ion sweeping a sheet of a substance containing ionic impurities by providing an ionic driving force and a thermal driving... Agent: Reveo, Inc.

20070190754 - Forming of a single-crystal semiconductor layer portion separated from a substrate: A method for forming a single-crystal semiconductor layer portion above a hollowed area, including growing by selective epitaxy on an active single-crystal semiconductor region a sacrificial single-crystal semiconductor layer and a single-crystal semiconductor layer, and removing the sacrificial layer. The epitaxial growth is performed while the active region is surrounded... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070190753 - Method for the production of a plurality of opto-electronic semiconductor chips and opto-electronic semiconductor chip: A method for the production of a plurality of optoelectronic semiconductor chips each having a plurality of structural elements with respectively at least one semiconductor layer. The method involves providing a chip composite base having a substrate and a growth surface. A non-closed mask material layer is grown onto the... Agent: Cohen, Pontani, Lieberman & Pavane

20070190755 - Substrate for growing pendeo epitaxy and method of forming the same: A Pendeo-epitaxy growth substrate and a method of manufacturing the same are provided. The Pendeo-epitaxy growth substrate includes a substrate, a plurality of pattern areas formed on the substrate in a first direction for Pendeo-epitaxy growth, and at least one solution blocking layer contacting the plurality of pattern areas and... Agent: Buchanan, Ingersoll & Rooney PC

20070190756 - Semiconductor wafer and manufacturing method thereof: The present invention provides a semiconductor wafer comprising an insulated board of sapphire or the like having translucency, which is provided with a positioning orientation flat at a peripheral portion thereof, and a silicon thin film formed over the entire one surface of the insulated board. In the semiconductor wafer,... Agent: Rabin & Berdo, PC

20070190757 - Vapor phase growth method: It is to provide a vapor phase growth method in which an epitaxial layer consisting of a compound semiconductor such as InAlAs, can be grown, with superior reproducibility, on a semiconductor substrate such as Fe-doped InP. In vapor phase growth method for growing an epitaxial layer on a semiconductor substrate,... Agent: Birch Stewart Kolasch & Birch

20070190758 - Method for conductivity control of (al,in,ga,b)n: A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 11} GaN films deposited on {100} MgAl2O4 spinel substrate miscut in the <011> direction. Mg atoms may be intentionally incorporated in the growing semipolar nitride thin film to introduce available electronic states in the band structure of... Agent: Gates & Cooper LLP Howard Hughes Center

20070190759 - Plasma doping method: A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved. It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a dose of boron is made substantially... Agent: Mcdermott Will & Emery LLP

20070190760 - Integrated parallel plate capacitors: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same... Agent: Ibm Microelectronics Intellectual Property Law

20070190761 - Material and method of fabrication therefor: The present invention concerns new methods of fabricating a silicon material comprising phosphorus. The methods allow high levels of phosphorus to be combined with the silicon. In one aspect of the invention a sample of phosphorus is surrounded with a sample of silicon. At least some of the phosphorus is... Agent: Nixon & Vanderhye, PC

20070190762 - Device manufacturing method and computer program product: A method of forming features, e.g. contact holes, at a higher density than is possible with conventional lithographic techniques involves forming an array of sacrificial positive features, conformally depositing a sacrificial layer so that negative features are formed interleaved with the positive features, directionally etching the sacrificial layer and removing... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070190763 - Method of manufacturing semiconductor device and semiconductor memory device: A method of manufacturing a semiconductor device includes: (A) forming a gate electrode of a transistor on a substrate, a top layer of the gate electrode being a first metal film; (B) blanket depositing an interlayer insulating film; and (C) forming a first contact hole contacting the gate electrode and... Agent: Young & Thompson

20070190764 - Method for manufacturing a substrate with cavity: An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the-upper seed layer where a cavity is to be formed;... Agent: Staas & Halsey LLP

20070190766 - Semiconductor devices having a vertical channel transistor and methods of forming the same: Methods of manufacturing a semiconductor device include forming a matrix of active pillars including a channel part on a substrate. Channel dopant regions are formed in the channel parts of the active pillars. Gate electrodes are formed on an outer surface of the channel parts that surround the channel dopant... Agent: Myers Bigel Sibley & Sajovec

20070190765 - Quaternary oxides and catalysts containing quaternary oxides: A quaternary oxide includes a dopant metal, a dopant nonmetal, titanium, and oxygen. The atomic ratio of titanium, oxygen and dopant nonmetal may be 1:0.5-1.99:0.01-1.5. Quaternary oxides may be used in catalytic compositions, in coatings for disinfecting surfaces and in coatings for self-cleaning surfaces. A method of making a quaternary... Agent: Evan Law Group LLC

20070190767 - Semiconductor device and manufacturing method thereof: In a method for manufacturing a semiconductor device, an insulating film is formed on an entire surface of a substrate having a device isolation region and a first and a second conductive region. Then, a semiconductor device structure having a gate electrode forming region is formed on each of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070190768 - Manufacturing method of semiconductor device: A method of manufacturing a semiconductor device, includes forming a gate insulating film on a semiconductor substrate, and forming a gate electrode on the gate insulting film, wherein forming the gate insulating film includes forming a metal silicate film, and a silicon source used for forming the metal silicate film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070190770 - Post-cmp treating liquid and manufacturing method of semiconductor device using the same: A post CMP treating liquid is provided, which includes water, resin particles having, on their surfaces, carboxylic group and sulfonyl group, and a primary particle diameter ranging from 10 to 60 nm, a first surfactant having carboxylic group, a second surfactant having sulfonyl group, and tetramethyl ammonium hydroxide. The resin... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070190769 - Method for forming low dielectric constant fluorine-doped layers: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric... Agent: Townsend And Townsend And Crew, LLP

20070190771 - System and method for stress free conductor removal: A system and method for forming a planar dielectric layer includes identifying a non-planarity in the dielectric layer, forming one or more additional dielectric layers over the dielectric layer and planarizing at least one of the additional dielectric layers wherein the one or more additional dielectric layers include at least... Agent: Martine Penilla & Gencarella, LLP

20070190772 - Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070190773 - Method of fabricating a semiconductor device: According to the invention, the method comprises the steps of: fabricating a first conductive layer including a first contact pad and covering the first conductive layer with a first protection layer at least on top of the first contact pad such that a first protective cap is formed thereon; fabricating... Agent: Slater & Matsil LLP

20070190775 - Low selectivity deposition methods: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of... Agent: Wells St. John P.s.

20070190774 - Method for fabricating a metal-insulator-metal capacitor: A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening... Agent: Lowe Hauptman Berner, LLP

20070190776 - Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric... Agent: Fish & Richardson, PC

20070190777 - Method of making dense, conformal, ultra-thin cap layers for nanoporous low-k ild by plasma assisted atomic layer deposition: Barrier layers and methods for forming barrier layers on a porous layer are provided. The methods can include chemically adsorbing a plurality of first molecules on a surface of the porous layer in a chamber and forming a first layer of the first molecules on the surface of the porous... Agent: Mh2 Technology Law Group

20070190778 - Via plug formation in dual damascene process: A method for forming a dual damascene structure in a semiconductor device manufacturing process where via plugs which may include a thickness portion of a plug filling material overlying the process surface is formed by diffusing an acid into a plug filling material layer followed by reacting the acid with... Agent: Tung & Associates

20070190779 - Diffusion barrier layers and methods comprising for depositing metal films by cvd or ald processes: A process is described for depositing a metal film on a substrate surface having a diffusion barrier layer deposited thereupon. In one embodiment of the present invention, the process includes: providing a surface of the diffusion barrier layer that is substantially free of an elemental metal and forming the metal... Agent: Air Products And Chemicals, Inc. Patent Department

20070190780 - Atomic layer deposition of barrier materials: Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate including depositing a metal nitride barrier layer on at least a portion of a substrate surface by alternately introducing... Agent: Patterson & Sheridan, LLP

20070190781 - Methods of forming metal-containing films over surfaces of semiconductor substrates: The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H2, at least one H2-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the... Agent: Wells St. John P.s.

20070190782 - Method of depositing ru films having high density: A ruthenium film deposition method is disclosed. In one embodiment of the method, a first ruthenium film is deposited by using a PEALD process until a substrate is substantially entirely covered with the first ruthenium film. Then, a second ruthenium film is deposited on the first ruthenium film by using... Agent: Knobbe Martens Olson & Bear LLP

20070190784 - Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer... Agent: Lsi Logic Corporation

20070190783 - Patterning crystalline compounds on surfaces: A method of patterning the surface of a substrate with at least one organic semiconducting compound, comprising the steps of: (a) providing a stamp having a surface including a plurality of indentations formed therein defining an indentation pattern, said indentations being contiguous with a stamping surface and defining a stamping... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070190787 - Method for etching silicon-germanium in the presence of silicon: A method for selectively etching single-crystal silicon-germanium in the presence of single-crystal silicon, including a chemical etch based on hydrochloric acid in gaseous phase at a temperature lower than approximately 700° C.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070190786 - Site-selectively modified micro-and nanostructures and the methods of their fabrication: It is an object of the present invention to provide a method which can easily and selectively modify specific sites on indentations or protrusions of indentation/protrusion structures fabricated by nano-imprinting. Pressing a mold having indentation/protrusion structures onto a polymer substrate comprising at least two layers of different chemical composition exposes... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070190785 - Methods, apparatus, and systems for causing fluid to flow through or into via holes, vents, and other openings or recesses that communicate with surfaces of substrates of semiconductor device components: A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or at least one... Agent: Trask Britt, P.C./ Micron Technology

20070190789 - Compositions and methods for cmp of indium tin oxide surfaces: The present invention provides chemical-mechanical polishing (CMP) compositions and methods for polishing an ITO surface. The compositions of the invention comprise a particulate zirconium oxide or colloidal silica abrasive, which has a mean particle size of not more than about 150 nm, suspended in an aqueous carrier, which preferably has... Agent: Steven Weseman Associate General Counsel, I.p.

20070190790 - Fine grinding a low-k dielectric layer off a wafer: A low-k dielectric layer is removed from a wafer to refresh the wafer. The low-k dielectric layer has a k value of less than about 3 and comprises silicon, oxygen and carbon. The method comprises fine grinding the low-k dielectric layer with a grinding surface comprising bonded particles of abrasive... Agent: Janah & Associates, P.C.

20070190791 - Removing a low-k dielectric layer from a wafer by chemical mechanical polishing: A low-k dielectric layer having a k value of less than about 3 and comprising silicon, oxygen and carbon, is removed from a wafer. In the method, the wafer is chemical mechanical polished by rotating the surface of the wafer against a polishing pad having a hardness of at least... Agent: Janah & Associates, P.C.

20070190788 - Wafer removing force reduction on cmp tool: Reduction of a wafer removing force on a chemical mechanical planarization (CMP) tool that includes planarizing a wafer on a platen at a wafer/platen interface; applying carbonated water to the wafer/platen interface so as to reduce the removing force; and removing the wafer from the platen.... Agent: Hoffman, Warnick & D'alessandro LLC

20070190792 - Method and system for selectively etching a dielectric material relative to silicon: A method and system for selectively and uniformly etching a dielectric layer with respect to silicon and polysilicon in a dry plasma etching system are described. The etch chemistry comprises the use of fluorohydrocarbons, such as CH2F2 and CHF3. High etch selectivity and acceptable uniformity can be achieved by selecting... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070190793 - Dual trench alternating phase shift mask fabrication: Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a mask layer, which is over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer is dry etched according to deep trenches of a PSM design. The quartz layer... Agent: Randy W. Tung Tung & Associates

20070190794 - Conductive polymers for the electroplating: A process to produce ultra-small structures of between ones of nanometers to hundreds of micrometers in size, in which the structures are compact, nonporous and exhibit smooth vertical surfaces. Such processing is accomplished using a non-conductive or semi-conductive substrate on which a layer of a conductive material, such as a... Agent: Davidson Berquist Jackson & Gowdey LLP

20070190795 - Method for fabricating a semiconductor device with a high-k dielectric: Method for fabricating semiconductor devices with high-K materials without the presence of undesired formations of the high-K material. A preferred embodiment comprises forming a layer of material over a layer of a high-K material, etching the layer of material to expose a portion of the high-K material, performing a CDE... Agent: Slater & Matsil LLP

20070190796 - Method and apparatus for manufacturing a functional layer consisting of at least two components: A method for manufacturing a functional layer includes introducing a substrate into a process chamber; generating a plasma by a DC plasma cascade source; depositing a first deposition material on the substrate under the influence of the plasma. At the same time, a second deposition material is applied to the... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070190797 - Cleaning method for use in semiconductor device fabrication: A novel cleaning method for preventing defects and particles resulting from post tungsten etch back or tungsten chemical mechanical polish is provided. The cleaning method comprises providing a stack structure of a semiconductor device including a tungsten plug in a dielectric layer. The tungsten plug has a top excess portion.... Agent: Baker & Mckenzie LLP Patent Department

20070190799 - Refurbishing a wafer having a low-k dielectric layer: A wafer comprising a low-k dielectric layer is refurbished for reuse. Initially, a removable layer is provided on the wafer. The low-k dielectric layer is formed over the removable layer. The overlying low-k dielectric layer is removed from the wafer by etching away the removable layer by at least partially... Agent: Janah & Associates, P.C.

20070190798 - Removing a low-k dielectric layer from a wafer: A low-k dielectric layer having a composition of silicon, oxygen and carbon, and optionally hydrogen, is removed from a test or production wafer to refresh the wafer. The low-k dielectric layer is removed by immersing a surface of the low-k dielectric layer in a first etching solution having a first... Agent: Janah & Associates, P.C.

20070190803 - Device and method to eliminate shorting induced by via to metal misalignment: The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and... Agent: Hitt Gaines, PC Lsi Corporation

20070190800 - Low-k dielectric material: Method for forming a low dielectric constant structure on a semiconductor substrate by CVD processing. The method comprises using a precursor containing chemical compound having the formula of (R1—R2)n-Si—(X1)4-n, wherein X1 is hydrogen, halogen, acyloxy, alkoxy or OH group, R2 is an optional group and comprises an aromatic group having... Agent: Kubovcik & Kubovcik

20070190801 - Method and apparatus for forming oxynitride film and nitride film, oxynitride film, nitride film, and substrate: Uniform oxynitride and nitride films can be formed by low-temperature and high-speed nitriding reaction not dependent on the nitriding time or nitriding temperature. A solid dielectric is provided on at least one of opposed surfaces of a pair of electrodes opposed to each other under a pressure of 300 (Torr)... Agent: Sughrue Mion, PLLC

20070190802 - Method for manufacturing semiconductor device, substrate treater, and substrate treatment system: A radical source is movably provided in a processing vessel holding a substrate, and the location or driving energy of the radical source is set such that the film formed on the substrate has a uniform thickness. Further, a radical source is provided at a first side of the substrate... Agent: Crowell & Moring LLP Intellectual Property Group

20070190804 - Minimizing low-k dielectric damage during plasma processing: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (≦2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD... Agent: Slater & Matsil LLP

20070190805 - Method for improving the alignment accuracy of semiconductor process and method of forming opening: A method of improving the alignment accuracy of the semiconductor devices is described. The method is used for photolithography process, and the photolithography process is aimed at the dielectric layer covered by a hard mask layer, wherein alignment marks are formed under the dielectric layer. The hard mask layer has... Agent: Jianq Chyun Intellectual Property Office

20070190806 - Uv blocking and crack protecting passivation layer fabricating method: A method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a patterned metal conductor layer. To provide UV blocking, an overlying separation layer is formed over the substrate, and a UV blocking layer of silicon enriched oxide is formed over the separation layer. The UV blocking layer... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070190807 - Method for forming dielectric or metallic films: Method for producing a metal silicon (oxy)nitride by introducing a carbon-free silicon source (for example, (SiH3)3N), a metal precursor with the general formula MXn (for example, Hf(NEt2)4), and an oxidizing agent (for example, O2) into a CVD chamber and reacting same at the surface of a substrate. MsiN, MSIo and/or... Agent: Air Liquide Intellectual Property

20070190808 - Low-k dielectric layers for large substrates: A system and method for producing a film is described. One embodiment of the process includes the following processes: providing a substrate comprising a glass plate, electrodes; and bus bars; heating the substrate to an approximate critical temperature; initiating the chemical vapor deposition process when the substrate is near the... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20070190810 - Laser irradiation method and method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device is provided which uses a laser crystallization method capable of increasing substrate processing efficiency. An island-like semiconductor film including one or more islands is formed by patterning (sub-island). The sub-island is then irradiated with laser light to improve its crystallinity, and thereafter patterned... Agent: Nixon Peabody, LLP

20070190809 - Wafer processing method, semiconductor device manufacturing method, and wafer processing apparatus: A wafer processing method is provided that includes the steps of heating a silicon wafer containing oxygen and irradiating an infrared ray having a wavelength within a range of 7-25 μm on the silicon wafer, and controlling formation of oxygen precipitates within the silicon wafer by selectively setting a heating... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070190811 - Method of forming patterns and/or pattern data for controlling pattern density of semiconductor devices and pattern density controlled semiconductor devices: A method of forming a pattern for a semiconductor device includes forming first pattern data, forming second pattern data, forming third pattern data, forming pattern density measurement data including the first, second, and third pattern data, measuring a pattern density of the pattern density measurement data, adjusting shapes of patterns... Agent: Lee & Morse, P.C.

20070190812 - Semiconductor device having sufficient process margin and method of forming same: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed... Agent: Marger Johnson & Mccollom, P.C.

20070184564 - Die attaching method: A die attaching method for attaching semiconductor dies on wafers, each wafer having a first center point and a first radius may comprise expanding a wafer carrier tape so that the wafer has a second center point and a second radius, measuring the second center point and second radius of... Agent: Marger Johnson & Mccollom, P.C.

20070184565 - Test pattern and method for measuring silicon etching depth: Embodiments of a test pattern and a method for measuring silicon etching depth are provided. After a contact-hole forming process, an optical critical dimension (OCD) is measured with respect to a test pattern formed on a semiconductor chip, so that the silicon etching depth may be analyzed in real time.... Agent: Marger Johnson & Mccollom, P.C.

20070184568 - Method of manufacturing gallium nitride based light emitting diode: Provided a method of manufacturing a GaN-based LED comprising forming an n-type GaN layer on a substrate; forming an active layer on the n-type GaN layer; forming a p-type GaN layer on the active layer; mesa-etching portions of the p-type GaN layer and the active layer so as to expose... Agent: Mcdermott Will & Emery LLP

20070184560 - Process for conveying solid particles: A process for conveying solid particles of irregular geometry, preferably polygonal geometry, through a pipe system, where the solid particles are conveyed by a gas. In order to enable metering through fragments or other solid particles of irregular geometry in desired quantities without any risk of the particles becoming trapped... Agent: Dennison, Schultz & Macdonald

20070184561 - Magnetic random access memory array with free layer locking mechanism and method of its use: A method of using an MTJ MRAM cell element having two magnetization states of greater and lesser stability. During switching, the free layer is first placed in the less stable state by a word line current, so that a small bit line current can switch its magnetization direction. After switching,... Agent: Saile Ackerman LLC

20070184563 - Apparatus and method for plasma etching: A plasma etching method for a plasma etching apparatus including: a processing chamber for performing plasma etching on an object to be processed; a first gas supply source; a second gas supply source; a first gas inlet for introducing a processing gas into the processing chamber; a second gas inlet... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070184562 - Plasma processing method and plasma processing apparatus: A plasma processing method for processing a sample by applying a high-frequency bias power periodically for each one period (T) which is divided along a time axis into a first sub-period (T1) for which feedback control of a CD gain is executed, a second sub-period (T2) for which feedback control... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070184566 - Neutrino receiver: Velocity (energy) modulated neutrino receiver devices consist of barium titanate bodies, feedback circuits to prevent front circuits from picking up acoustic energy from neutrino modulators, and spaces to permit modulated neutrinos to pass through said bodies from front to back forming a modulated neutrino receiver device. One or more such... Agent: Leo J. Aubel

20070184567 - Method for material growth of gan-based nitride layer: The present invention relates to a method for forming a GaN-based nitride layer comprising a first step of forming a first layer comprising SiaCbNc (c,fc>0, a≧0) on a sapphire substrate and a second step for forming a nitride layer comprising a GaN component on the first layer comprising SiaCbNc (c,b>0,... Agent: Darby & Darby P.C.

20070184569 - Silicon nitride sintered material method for manufacturing the same molten-metal-resistant member and wear resistant member formed from the same: A silicon nitride sintered material includes a silicon nitride crystal and a grain boundary layer that contains at least two of a first metal silicide (a metal silicide having, as a first metal element, at least one selected from the group consisting of Fe, Cr, Mn and Cu), a second... Agent: Hogan & Hartson L.L.P.

20070184571 - Cmos image sensor integrated with 1-t sram and fabrication method thereof: A CMOS image sensor integrated with 1T-SRAM is provided on a substrate having a pixel array part, a logic circuit part, and a memory part by adding only one photoresist process. There are a plurality of CMOS image sensor devices in the pixel array part, a logic circuit in the... Agent: North America Intellectual Property Corporation

20070184570 - Solid-state imaging apparatus and method for producing the same: A solid-state imaging apparatus includes a plurality of photosensitive cells, and a driving unit provided for driving the plurality of photosensitive cells. Each photosensitive cell includes a photodiode formed to be exposed on a surface of a semiconductor substrate for the purpose of accumulating signal charge obtained by subjecting incident... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070184572 - Semiconductive device fabricated using a raised layer to silicide the gate: In one aspect, the invention provides a method of fabricating a semiconductive device 200 that comprises forming a raised layer [510] adjacent a gate [340] and over a source/drain [415], depositing a silicidation layer [915] over the gate [340] and the raised layer [510], and moving at least a portion... Agent: Texas Instruments Incorporated

20070184573 - Method of making a thermally treated coated article with transparent conductive oxide (tco) coating for use in a semiconductor device: A method of making a coated article including a transparent conductive oxide (TCO) film supported by a glass substrate is provided. Initially, an amorphous metal oxide film is sputter-deposited onto a glass substrate, either directly or indirectly. The glass substrate with the amorphous film and a semiconductor film thereon is... Agent: Nixon & Vanderhye, PC

20070184574 - Condensed polycyclic aromatic compound thin film and method for preparing condensed polycyclic aromatic compound thin film: An organic semiconductor thin film exhibiting high mobility and a method for preparing the same, and a material for preparing the organic semiconductor thin film by a wet process and a method for preparing the same are provided. Further, an organic semiconductor device excellent in electronic characteristics is provided. A... Agent: Birch Stewart Kolasch & Birch

20070184575 - Organic photoelectric device with improved electron transport efficiency: An opto-electronic device, such as an OLED or organic solar cell, having an electrode structure for use as a cathode. The electrode structure includes an electrically conductive layer and an inorganic layer, wherein the inorganic layer is made of at least one oxide-based alkali or alkaline earth metal intercalation compound.... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070184576 - Solution deposition of inorganic materials and electronic devices made comprising the inorganic materials: Disclosed embodiments concern solution deposition of at least a first inorganic compound on a substrate, typically for production of electronic devices, such as solution deposition of metal salts, including halides, carbonyls, acetates, sulfates, phosphates, carbonates, and mixtures thereof. Solutions may be deposited using any suitable process, particularly inkjet printing or... Agent: Klarquist Sparkman, LLP

20070184577 - Method of fabricating wafer level package: A method of fabricating a wafer level package may include providing semiconductor substrate having a bonding pad; forming a passivation layer on the semiconductor substrate and partially exposing the boding pad, forming a first insulating layer on the passivation layer; forming a seed metal layer on the first insulating layer... Agent: Harness, Dickey & Pierce, P.L.C

20070184579 - Method of fabrication on high coplanarity of copper pillar for flip chip packaging application: This invention is characteristic of combining an electroplating process with a polishing process to uniformly fabricate multi-layer flip chip copper pillar. All kinds of flip chip copper pillar with varied shapes and sizes are able to be defined by using multi-layer photolithography process commonly utilized in the semiconductor processes. After... Agent: Jung-tang Huang

20070184578 - Solder bump confinement system for an integrated circuit package: A solder bump confinement system is provided including providing a substrate, patterning a contact material on the substrate, depositing an inner passivation layer over the contact material and the substrate, forming an under bump material defining layer over the contact material by sputtering, and forming a system interconnect over the... Agent: Ishimaru & Zahrt LLP

20070184580 - Method of making a small substrate compatible for processing: A method of making a comparatively small substrate (12) compatible with manufacturing equipment for a larger-size standard substrate is disclosed. The standard substrate (1) has a surface (10) in which a depression (8) is formed, in which depression the small substrate is connected by means of a layer of a... Agent: Philips Intellectual Property & Standards

20070184582 - Method of flip-chip mounting: A method of flip-chip mounting can reliably and stably mount a semiconductor chip to a mounting substrate while avoiding problems such as damage to the semiconductor chip due to a difference in thermal expansion coefficients between the semiconductor chip and the mounting substrate. The method of flip-chip mounting a semiconductor... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070184581 - Semiconductor constructions and semiconductor device fabrication methods: A method of fabricating a semiconductor device includes etching a substrate to form a recess, the substrate being formed on a backside of a semiconductor wafer, forming pores in the substrate in an area of the recess, and forming in the recess a material having a thermal conductivity which is... Agent: Mcginn Intellectual Property Law Group, PLLC

20070184583 - Method for fabricating semiconductor package: According to this invention, a method for fabricating a semiconductor package, in which a plurality of semiconductor chips having a through electrode is layered on a semiconductor interposer, comprising: mounting and layering a plurality of semiconductor chips on a first surface of a semiconductor wafer, which is to be used... Agent: Rabin & Berdo, PC

20070184584 - Method for manufacturing physical quantity sensor: A method for manufacturing a physical quantity sensor includes the steps of: preparing a lead frame comprising a rectangular frame portion, a plurality of leads protruding out from this rectangular frame portion in the inward direction, and a stage portion that is connected to the rectangular frame portion by connecting... Agent: Dickstein Shapiro LLP

20070184587 - Thin film transistor panel and manufacturing method thereof: A thin film transistor (TFT) array panel includes a substrate, a first signal line formed on the substrate, a gate insulating layer formed on the first signal line and having a first contact hole exposing a portion of the first signal line, a first semiconductor formed on the gate insulating... Agent: Frank Chau, Esq. F Chau & Associates, LLC

20070184586 - Thin film transistor panel and method of manufacturing the same: A thin film transistor panel and a method of manufacturing the same are disclosed. The thin film transistor panel includes a thin film transistor including a drain electrode with an opening, and a transparent electrode contacts a portion of the opening.... Agent: H.c. Park & Associates, PLC

20070184585 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. The method includes the steps of: (1) coating a solution containing an organic semiconductor material on a water-repellent surface of a water-repellent stamp substrate; (2) drying the thus coated organic semiconductor material-containing solution on the water-repellent surface to crystallize the organic... Agent: Bell, Boyd & Lloyd, LLP

20070184588 - Wrap-around gate field effect transistor: A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070184589 - Silicon on insulator device and method of manufacturing the same: An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070184591 - Nitride semiconductor laser element and method for manufacturing the same: A nitride semiconductor laser element, has: a nitride semiconductor layer comprising a first nitride semiconductor layer, an active layer, and a second nitride semiconductor layer laminated in that order; and resonator end faces formed mutually opposing at the end of said nitride semiconductor layers, wherein an impurity is contained in... Agent: GlobalIPCounselors, LLP

20070184590 - Method for manufacturing a semiconductor device and laser irradiation method and laser irradiation apparatus: [Object]When the CW laser is employed for annealing the semiconductor film, a device having a high characteristic can be expected. On the other hand, when the beam shaped to be elliptical is scanned on the semiconductor film, a proportion of excimer-like crystal grain region becomes large and this is a... Agent: Eric Robinson

20070184592 - Method for manufacturing semiconductor device: A gate insulating film is formed on a silicon substrate, a conductor film constituting a gate electrode is formed on the gate insulating film by a formation method using an organic material, and the silicon substrate, on which the conductor film is formed, is heated in a mixed atmosphere of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070184593 - Semiconductor device and manufacturing method thereof: In a crystallization process of an amorphous semiconductor film, a first polycrystalline semiconductor film, in which amorphous regions are dotted within the continuous crystal region, is obtained by performing heat treatment after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. At this point, the amorphous regions... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070184594 - Schottky barrier diode and method of forming a schottky barrier diode: Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070184595 - Semiconductor device and manufacturing method thereof: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070184596 - Ion beam irradiation apparatus and ion beam irradiation method: The ion beam irradiation apparatus has a vacuum chamber 10, an ion source 2, a substrate driving mechanism 30, rotation shafts 14, arms 12, and a motor. The ion source 2 is disposed inside the vacuum chamber 10, and emits an ion beam 4 which is larger in width than... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070184598 - Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors: Shorting bars are provided for electrostatic discharge protection as a portion of trace deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers having traces in contact... Agent: Felix L. Fischer, Attorney At Law

20070184599 - Mos transistor and method for producing a mos transistor structure: A MOS transistor, and a method for producing the same, is provided with a source region, a gate-region, a drain region, and a drift region in an SOI wafer. The SOI-wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070184597 - Stress liner for integrated circuits: In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This... Agent: Okamoto & Benedicto, LLP

20070184602 - Chevron cmos trigate structure: Disclosed herein is a structure with two different type tri-gate MOSFETs formed on the same substrate. Each MOSFET comprises a fin with optimal mobility for the particular type of MOSFET. Due to the processes used to form fins with different crystalline orientations on the same substrate, one of the MOSFETs... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070184603 - Method of fabricating semiconductor integrated circuit device: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070184601 - Method of forming a semiconductor device: A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of... Agent: Freescale Semiconductor, Inc. Law Department

20070184600 - Stressed-channel cmos transistors: Methods for forming portions of source and drain (S/D) regions of a first ensuing transistor (40) to include a semiconductor material (47) having a different composition of non-dopant elements than portions of S/D regions (35) of a second ensuing transistor (30) of opposite conductivity type are provided. The methods additionally... Agent: Larson Newman Abel Polansky & White, LLP

20070184604 - Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board: In accordance with the present invention, during formation of the interconnection board, the interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than the interconnection board for suppressing the interconnection board from being bent.... Agent: Young & Thompson

20070184606 - Method of forming semiconductor device: Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low... Agent: Marger Johnson & Mccollom, P.C.

20070184605 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device. An etch process for controlling the effective field height of isolation layers is performed using a dry etch process on condition that an excessive amount of polymer is generated, thus forming first spacers on sidewalls of a floating gate pattern. The first... Agent: Marshall, Gerstein & Borun LLP

20070184607 - Methods of forming integrated circuitry, and methods of forming dynamic random access memory cells: The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having... Agent: Wells St. John P.s.

20070184608 - Method of fabricating bipolar junction transistor: A method of fabricating a bipolar junction transistor is provided herein. An isolation structure is formed on a first conductive type substrate. A second conductive type deep well is formed in the first conductive type substrate to serve as a collector. Thereafter, a second conductive type well is formed in... Agent: Jianq Chyun Intellectual Property Office

20070184610 - Integrated circuit capacitor structure: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first... Agent: Marger Johnson & Mccollom, P.C.

20070184609 - Multivoltage thin film capacitor: An apparatus, and a method for forming, a split thin film capacitor for providing multiple power and reference supply voltage levels to electrical devices such as integrated circuits, may be useful in space restricted applications, and in applications that require very close electrical connections between the power consumer and the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070184611 - Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same: According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower... Agent: Marger Johnson & Mccollom, P.C.

20070184612 - Method for assembling a panel for an lcd: A method for assembling a liquid crystal display includes providing a thin-film-transistor substrate and a color-filter substrate having an active area and a non-active area, wherein plural spacers are formed in the in the active area of the color-filter substrate. At least two spacing-pads are individually formed in the surrounding... Agent: Bacon & Thomas, PLLC

20070184613 - Phase change ram including resistance element having diode function and methods of fabricating and operating the same: A phase change RAM (PRAM) including a resistance element having a diode function, and methods of fabricating and operating the same are provided. The PRAM may include a substrate, a phase change diode layer formed on the substrate and an upper electrode formed on the phase change diode layer. The... Agent: Harness, Dickey & Pierce, P.L.C

20070184614 - Recessed gate for a cmos image sensor: A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type... Agent: Scully, Scott, Murphy & Presser, P.C.

20070184616 - Nonvolatile memory device and method of forming the same: In a method of forming a nonvolatile memory device, and in devices formed according to the method, a hard mask used in patterning a stacked structure constituting a memory cell is simultaneously removed when a device isolation region is removed from a region of the substrate where a common source... Agent: Mills & Onello LLP

20070184615 - Process for manufacturing a non-volatile memory electronic device integrated on a semiconductor substrate and corresponding device: A non-volatile memory electronic device integrated on a semiconductor substrate includes non-volatile memory cells organized in a matrix, and circuitry associated therewith. Each memory cell includes a gate electrode projecting from the semiconductor substrate. Source and drain regions are formed in the semiconductor substrate and aligned with the gate electrodes.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070184617 - Method for manufacturing semiconductor device: There is provided a semiconductor device having a high breakdown voltage and a high reliability in which a gate insulating film having a film thickness of good uniformity is formed inside a trench. An HTO is formed on an inner wall of a trench in an Si substrate by a... Agent: Rossi, Kimms & Mcdowell LLP.

20070184618 - Process for producing semiconductor integrated circuit device and semiconductor integrated circuit device: In order to provide a light oxidation process technique for use in a CMOS LSI employing a polymetal gate structure and a dual gate structure, so that both oxidation of a refractory metal film constituting a part of a gate electrode and diffusion of boron contained in a p-type polycrystalline... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070184619 - Selective incorporation of charge for transistor channels: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions... Agent: Keusey, Tutunjian & Bitetto, P.C.

20070184620 - Field effect transistor and method of manufacturing a field effect transistor: The invention relates to a method of manufacturing a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type, which regions are both provided with extensions (2A,... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070184622 - High voltage transistor and method of manufacturing the same: The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region... Agent: Mills & Onello LLP

20070184621 - Mosfet wth high angle sidewall gate and contacts for reduced miller capacitance: The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such... Agent: Scully, Scott, Murphy & Presser, P.C.

20070184623 - Semiconductor device comprising buried channel region and method for manufacturing the same: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070184624 - Micromechanical device and method for manufacturing a micromechanical device: In a method for manufacturing a micromechanical device having a region for forming an integrated circuit, at first a first layer is produced on a deeper-lying part in the substrate. Subsequently, a membrane layer is produced on the first layer and at least one channel completely penetrating the membrane layer... Agent: Baker Botts, L.L.P.

20070184625 - Semiconductor device including an improved capacitor and method for manufacturing the same: In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage... Agent: Marger Johnson & Mccollom, P.C.

20070184626 - Method of manufacturing ferroelectric capacitor and method of manufacturing semiconductor memory device: A method of manufacturing a semiconductor device includes the steps of preparing a substrate having a semiconductor element; forming an insulation film on a surface of the substrate; forming a first film on the insulation film, the first film being a film which does not allow oxygen atoms to pass... Agent: Rabin & Berdo, PC

20070184627 - Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same: Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided.... Agent: Myers Bigel Sibley & Sajovec

20070184628 - Method for determining an overlay correlation set: The invention is directed to a method for determining an overlay correlation set between two successive patterned material layers on a substrate. The method comprises steps of providing a first material layer having a first overlay mark formed therein over the substrate and then using an exposure tool with a... Agent: J.c. Patents, Inc.

20070184629 - Method for producing a surface-mountable semiconductor component: Presented is a method for simultaneously producing a multiplicity of surface-mountable semiconductor components each having at least one semiconductor chip, at least two external electrical connections, which are electrically conductively connected to at least two electrical contacts of the semiconductor chip, and an encapsulation material.... Agent: Cohen, Pontani, Lieberman & Pavane

20070184630 - Method of bonding a semiconductor wafer to a support substrate: A method of bonding a semiconductor wafer to a support substrate comprising the steps of: providing a semiconductor wafer; coating at least part of one face of the wafer with a water soluble coating layer; providing a double sided adhesive tape, at least one side of the adhesive tape comprising... Agent: Howard & Howard Attorneys, P.C.

20070184631 - Method of manufacturing bonded wafer: The method of manufacturing a bonded wafer including, implanting hydrogen ions, rare gas ions, or a mixture of hydrogen ions and rare gas ions into a bond wafer to form an ion implantation layer in the bond wafer, bonding the bond wafer in which the ion implantation layer has been... Agent: Greenblum & Bernstein, P.L.C

20070184632 - Method of fabricating a semiconductor device: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070184634 - Method of manufacturing a semiconductor device: A semiconductor device manufacturing method is disclosed wherein a semiconductor integrated circuit is formed in each of plural semiconductor chip regions of a semiconductor wafer which regions are to become semiconductor chips later and then the semiconductor wafer is cut along scribing regions each provided between adjacent semiconductor chip regions.... Agent: Miles & Stockbridge PC

20070184633 - Method of segmenting wafer: A wafer is provided and a front scribe line pattern is defined on a front surface of the wafer. A back scribe line pattern corresponding to the front scribe line pattern is defined on a back surface of the wafer. Then the wafer is attached to an extendable film and... Agent: North America Intellectual Property Corporation

20070184635 - Integrated circuit wafer with inter-die metal interconnect lines traversing scribe-line boundaries: A metal interconnect structure formed over a substrate in an integrated circuit that traverses a scribe-line boundary between a first die and a second die includes at least one metal interconnect line that traverses the scribe-line boundary. A switch is coupled between the at least one metal interconnect line and... Agent: Sierra Patent Group, Ltd.

20070184636 - Substrate processing apparatus: Substrate processing with return processing is carried out efficiently by a substrate processing apparatus that continuously processes a plurality of substrates. It is equipped with a conveyor chamber constituting a substrate convey space, a plurality of process chambers in which substrate processing is carried out, substrate convey means provided in... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070184637 - Growth of planar reduced dislocation density m-plane gallium nitride by hydride vapor phase epitaxy: A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.... Agent: Gates & Cooper LLP Howard Hughes Center

20070184639 - Manufacturing method of memory element, laser irradiation apparatus, and laser irradiation method: A method for rapidly performing laser irradiation in a desired position as laser irradiation patterns are switched is proposed. A laser beam emitted from a laser oscillator is entered into a deflector, and a laser beam which has passed through the deflector is entered into a diffractive optical element to... Agent: Eric Robinson

20070184638 - Mask for silicon crystallization, method for crystallizing silicon using the same and display device: A mask for silicon crystallization capable of minimizing the number of grain boundaries in crystallized silicon, a method for crystallizing silicon using the mask, and a display device are presented. The mask includes a group of slits that are inclined at a predetermined angle with respect to a scan direction... Agent: Macpherson Kwok Chen & Heid LLP

20070184640 - Method for producing solid element plasma and its plasma source: There is provided a method for producing a solid element plasma from a solid lump and a plasma source used in the method. The method of the present invention comprises colliding a solid lump with accelerated particles or lasers to detach solid atoms from the solid lump within a first... Agent: Hoffmann & Baron, LLP

20070184641 - Process and system for laser annealing and laser-annealed semiconductor film: In a laser annealing process: a bandlike area of a nonmonocrystalline semiconductor film is scanned and irradiated with continuous-wave laser light so as to produced fused regions in the first to third sections of the bandlike area as follows, where the third section contains a portion required to have higher... Agent: Sughrue Mion, PLLC

20070184642 - Recessed poly extension t-gate: A method is provided for making a silicided gate in a semiconductor device. In accordance with the method, a gate (213) is provided which comprises a first portion (214) and a second portion (213). The first portion of the gate has a width w1 and the second portion of the... Agent: Fortkort & Houston P.C.

20070184643 - Methods of forming metal layers using multi-layer lift-off patterns: Methods of forming interconnections for an electronic device including a substrate may be provided. For example, first and second patterned layers may be formed on the substrate wherein an opening in the first and second patterned layers exposes portions of the substrate, wherein the first and second patterned layers have... Agent: Myers Bigel Sibley & Sajovec

20070184644 - Ball grid array copper balancing: A ball grid array device includes a substrate having a first major surface and a second major surface. The first major surface includes leads for electrical connections. The second major surface is devoid of leads. The ball grid array device also includes a first land having a solder mask opening... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070184645 - Active area bonding compatible high current structures: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form... Agent: Fogg & Powers LLC

20070184647 - Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes: A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, depositing a conventional dielectric on the surface surrounding the carbon... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070184646 - Semiconductor device, wiring substrate forming method, and substrate processing apparatus: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070184648 - Composition for forming a photosensitive organic anti-reflective layer and method of forming a pattern using the same: A composition for forming a photosensitive organic anti-reflective layer includes about 0.5 to about 5 percent by weight of an acid-labile thermal cross-linking agent that is decomposed by an epoxy group and a photo-acid generator, about 10 to about 22 percent by weight of a copolymer resin that includes an... Agent: Volentine & Whitt PLLC

20070184650 - Copper interconnect systems which use conductive, metal-based cap layers: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least... Agent: Woodcock Washburn LLP

20070184651 - Copper interconnect systems which use conductive, metal-based cap layers: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least... Agent: Woodcock Washburn LLP

20070184649 - Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics: Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating... Agent: Myers Bigel Sibley & Sajovec

20070184652 - Method for preparing a metal feature surface prior to electroless metal deposition: The present invention provides a method for manufacturing an interconnect and an integrated circuit. The method for manufacturing the interconnect, in one embodiment, includes forming a first metal feature (310) over a substrate, subjecting the first metal feature (310) to a hydrogen containing plasma (410), the hydrogen containing plasma (410)... Agent: Texas Instruments Incorporated

20070184653 - Integrated circuit with a very small-sized reading diode: The invention relates to integrated circuits comprising both conductive gates deposited above a semiconductor substrate and a diode is formed between two electrodes. In order to achieve a diode of very small dimensions, the following procedure is adopted: producing the electrodes (ELn, GRST, then thermally oxidizing the electrodes, then exposing... Agent: Lowe Hauptman & Berner, LLP

20070184654 - Methods for fabricating and filling conductive vias and conductive vias so formed: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during... Agent: Trask Britt, P.C./ Micron Technology

20070184655 - Copper interconnect wiring and method and apparatus for forming thereof: Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods and apparatus for forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and... Agent: Burns & Levinson, LLP

20070184656 - Gcib cluster tool apparatus and method of operation: A wafer processing cluster tool and method of operation provides one or more gas cluster ion beam processing chambers in possible combination with a deposition chamber and/or a cleaning chamber for performing sequential processing steps including, GCIB processing in a reduced pressure atmosphere.... Agent: Burns & Levinson, LLP

20070184657 - Etching method: An etching method includes the step of forming recesses by performing a plasma etching on a target layer of a target object in a processing chamber of a plasma processing apparatus. The plasma etching is performed by using a mask, which is formed on the target layer and is provided... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070184658 - Etching liquid for controlling silicon wafer surface shape: A method for manufacturing a silicon wafer includes a planarizing process 13 for polishing or lapping the upperside and lowerside surfaces of a thin disk-shaped silicon wafer obtained by slicing a silicon single crystal ingot, an etching process for dipping the silicon wafer into the etching liquid wherein silica powder... Agent: Reed Smith, LLP Attn: Patent Records Department

20070184659 - Method for cleaning a semiconductor wafer: Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which... Agent: Edell, Shapiro & Finnan, LLC

20070184660 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device in which, when a polyimide resin film is formed as a protective film on a front surface of a semiconductor chip, the polyimide resin film disposed on scribe lines is removed and the polyimide resin film disposed on a circumferential portion... Agent: Bruce L. Adams, Esq.

20070184663 - Method of planarizing a semiconductor device: Example embodiments are directed to a method of planarizing a semiconductor device. A first CMP process may be performed on an insulating layer to remove a stepped structure of the insulating layer. A second CMP process may be performed to planarize the insulating layer with the stepped structure removed until... Agent: Harness, Dickey & Pierce, P.L.C

20070184662 - Double-side polishing carrier and fabrication method thereof: The carrier (10) for double-side polishing has a base material 10a the material of which is stainless steel (SUS) , for example, as is before, and the base material 10a is coated with a coating layer 10b of a material having a hardness higher than that of the base material... Agent: Welsh & Katz, Ltd

20070184661 - Multi-component barrier polishing solution: The polishing solution is useful for removing barrier materials in the presence of at least one nonferrous interconnect metal with limited erosion of dielectrics. The solution contains 0 to 20 weight percent oxidizer, at least 0.001 weight percent inhibitor for reducing removal rate of the nonferrous interconnect metals, 1 ppm... Agent: Rohm And Haas Electronic Materials Cmp Holdings, Inc.

20070184664 - Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region: A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming... Agent: Blakely Sokoloff Taylor & Zafman

20070184665 - Semiconductor device and manufacturing method thereof: The aperture ratio of a pixel of a reflecting type display device is improved without increasing the number of masks and without using a black mask. Locations for light shielding between pixels are arranged such that a pixel electrode overlaps with a portion of a gate wiring and a source... Agent: Fish & Richardson P.C.

20070184667 - Insulating layer patterning method, insulating layer formed by the insulating layer patterning method, display device having the insulating layer: Provided is an insulation layer patterning method employing a flowable oxide, which does not use a photo-resist. Also, an insulation layer pattern and display devices including the insulation layer are disclosed.... Agent: Sughrue Mion, PLLC

20070184666 - Method for removing residue containing an embedded metal: The present invention provides a method for removing residue from a cavity during the formation of an interconnect structure, a method for manufacturing an interconnect structure using the same, and a method for manufacturing an integrated circuit using the same. The method for removing residue from a cavity during the... Agent: Texas Instruments Incorporated

20070184668 - Poly silicon gate doping method and structure for strained silicon mos transistors: A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surface of the gate structure, including the... Agent: Townsend And Townsend And Crew, LLP

20070184669 - Via structures and trench structures and dual damascene structures: Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the... Agent: Mark J. Marcelli Duane Morris LLP

20070184670 - Manufacturing method of semiconductor device, and ic card, ic tag, rfid, transponder, bill, securities, passport, electronic apparatus, bag, and garment: The present invention provides a manufacturing method of a semiconductor device used as an ID chip, by which data can be written with improved throughput. According to the manufacturing method of a semiconductor device having a modulation circuit, a demodulation circuit, a logic circuit, a memory circuit, and an antenna... Agent: Eric Robinson

20070184671 - Method for production of group lll nitride semiconductor device: A method for producing a Group III nitride semiconductor device includes forming on a substrate or a surface of a Group III nitride semiconductor crystal a mask of a SiO2 or SiNx film partially covering the substrate or the surface of the Group III nitride semiconductor crystal and subsequently forming... Agent: Sughrue Mion, PLLC

20070184672 - Fluidic device containing 3d structures: A micro fluidic device comprises a laminate structure, comprising a plurality of individual layers. At least one layer comprises a micro fluidic channel structure and at least on one side of said layer a further layer is arranged comprising a three-dimensional (3D) micro structure such that the 3D micro structure... Agent: Dinsmore & Shohl, LLP One Dayton Centre

20070178613 - Method of manufacturing semiconductor device and cleaning apparatus: The disclosure concerns a manufacturing method of a semiconductor device includes dry-etching a semiconductor substrate or a structure formed on the semiconductor substrate; supplying a solution onto the semiconductor substrate; measuring a specific resistance or a conductivity of the supplied solution; and supplying a removal solution for removing the etching... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070178608 - Magnetic tunnel junction device with improved barrier layer: Methods and apparatus are provided for magnetic tunnel junction (MTJ) devices and arrays, comprising metal-insulator-metal (M-I-M) structures with opposed first and second ferro-magnetic electrodes with alterable relative magnetization direction. The insulator is formed by depositing an oxidizable material (e.g., Al) on the first electrode, naturally oxidizing it, e.g., at about... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070178609 - Magnetoresistive element manufacturing method and magnetic memory device manufacturing method: A magnetoresistive element manufacturing method includes forming a material layer on a substrate, the material layer including a fixed layer, a recording layer, and a first nonmagnetic layer sandwiched between the fixed layer and the recording layer; forming a mask material on the material layer, forming a first mask with... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070178610 - Semiconductor production apparatus: A semiconductor production apparatus and method for etching a semiconductor wafer arranged in a container and having a film on the surface thereof, by use of a plasma generated in the container. A temporal change of a quantity of an interference light is detected for at least two wavelengths obtained... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070178611 - Semiconductor wafer having measurement area feature for determining dielectric layer thickness: A semiconductor wafer includes a first dielectric layer, a second dielectric layer contacting the first dielectric layer, and a measurement area feature. The measurement area feature is laterally enclosed by the second dielectric layer. The measurement area feature is adapted to be used for determining a thickness of the first... Agent: Dicke, Billig & Czaja

20070178612 - Semiconductor wafer with rear side identification and method: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns... Agent: Dicke, Billig & Czaja

20070178614 - Semiconductor device: An object of the invention is to manage variation of electrical characteristics of an element in a semiconductor device due to a vapor deposition process by measuring electrical characteristics of a TEG. A substrate 100 of an active matrix EL panel includes a vapor deposition region 101 having a film... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070178616 - Manufacturing method of semiconductor device having organic semiconductor film: A method of manufacturing a semiconductor device having an organic semiconductor film comprises a step of preparing a transparent substrate at least having an opaque gate electrode and a gate insulator thereover, a step of forming a layer containing metal-nano-particles as a conductive layer for a source electrode and a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070178615 - Semiconductor nanocrystal-based optical devices and method of preparing such devices: A method and optical device produced by such method are presented. The method consists of processing a structure formed by a nanocrystals solution on a surface of a substrate, to thereby produce a film of said nanocrystals on said surface, and create within an interface between said film and said... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20070178618 - Method for manufacturing liquid crystal display panel: A method for manufacturing a liquid crystal display (LCD) panel, comprising providing a first substrate and a second substrate, dripping a plurality of liquid crystal (LC) drops on the first substrate and the second substrate, wherein the plurality of LC drops form a LC drop area having at least a... Agent: Morris Manning Martin LLP

20070178617 - Pixel structure of thin film transistor liquid crystal display: A pixel structure of a thin film transistor liquid crystal display employs a design of three metal layers and includes an organic insulating layer between a data signal line and a common electrode for reducing a parasitic capacitance, while a passivation layer included between the common electrode and a pixel... Agent: Hdsl

20070178619 - Low resistance thin film organic solar cell electrodes: A method which lower the series resistance of photosensitive devices includes providing a transparent film of a first electrically conductive material arranged on a transparent substrate; depositing and patterning a mask over the first electrically conductive material, such that openings in the mask have sloping sides which narrow approaching the... Agent: Kenyon & Kenyon LLP

20070178620 - Method of forming copper indium gallium containing precursors and semiconductor compound layers: The present invention relates to methods of preparing polycrystalline thin films of semiconductors for radiation detectors and solar cells and the films resulting therefrom. In one aspect, the present invention provides a first type of particles and a second type of particles, wherein the first type of particles have a... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070178621 - Apparatus and semiconductor co-crystal: The invention provides a method to enforce face-to-face stacking of organic semiconductors in the solid state that employs semiconductor co-crystal formers (SCCFs), to align semiconductor building blocks (SBBs). Single-crystal X-ray analysis reveals π-orbital overlap optimal for organic semiconductor device applications.... Agent: Viksnins Harris & Padys Pllp

20070178623 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes a bonding step of bonding a chip on a wiring board by means of a bonding layer, and a wire bonding step of bonding a wire to a pad on the chip while applying ultrasonic vibration after the bonding step. A material... Agent: Mcdermott Will & Emery LLP

20070178622 - Thermal enhanced package: A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die... Agent: Townsend And Townsend And Crew LLP

20070178624 - Semiconductor arrangement: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk... Agent: Dicke, Billig & Czaja

20070178627 - Flip-chip semiconductor device and method for fabricating the same: A flip-chip semiconductor device and a method for fabricating the same are provided. A first underfill material with a low Young's modulus is applied to corners of a chip mounting area defined on a substrate. A chip is mounted on and electrically connected to the chip mounting area by a... Agent: Edwards Angell Palmer & Dodge LLP

20070178625 - Composite interconnect structure using injection molded solder technique: Composite interconnect structure forming methods using injection molded solder are disclosed. The methods provide a mold having at least one opening formed therein with each opening including a member of a material dissimilar to a solder to be used to fill the opening, and then fill the remainder of each... Agent: Hoffman, Warnick & D'alessandro LLC

20070178626 - Method of packaging semiconductor die: A method of packaging a semiconductor die (10) includes providing a flip-chip die (10) with bump connections (12) on its bottom surface (14). An adhesive tape (18) is attached to a plate surface (16) and lead fingers (20) are formed on the tape (18). The die (10) is placed on... Agent: Freescale Semiconductor, Inc. Law Department

20070178628 - Fabrication of an integrated circuit package: A QFN integrated circuit is mounted on a leadframe having multiple lead lands and resin material encapsulates the integrated circuit leaving the lead lands exposed. Subsequently a sawing operation divides the lead lands into multiple leads, and the leadframe and resin material are partitioned to form packages. The pitch of... Agent: Slater & Matsil LLP

20070178629 - Method for manufacturing a surface mount device: A surface mount electronic device manufacturing method can produce surface mount devices at a high yield rate and high productivity by reducing warp of a circuit board. The reduced warp avoids problems in processes for dicing the circuit board. Surface mount LED devices made in accordance with the method can... Agent: Cermak & Kenealy, LLP

20070178630 - Method for fabricating a photosensitive semiconductor package: A photosensitive semiconductor package, a method for fabricating the same, and a lead frame thereof are proposed. The lead frame has a die pad and a plurality of leads, wherein at least one recessed portion is formed at an end of each lead close to the die pad, and at... Agent: Edwards Angell Palmer & Dodge LLP

20070178631 - Crystallization method for semiconductor film, manufacturing method for semiconductor device, and laser irradiation apparatus: A semiconductor film formed over a substrate is irradiated by a first laser beam which is incident on a bottom surface of the substrate at an angle and by a second laser beam which is incident on the bottom surface of the substrate at an angle opposite that of the... Agent: Nixon Peabody, LLP

20070178632 - Manufacturing a semiconductor device including sidewall floating gates: A semiconductor device and a fabricating method thereof are disclosed. The semiconductor device includes polysilicon gate electrodes, a gate oxide layer, sidewall floating gates, a block oxide layer, source/drain areas, and sidewall spacers. In addition, the method includes the steps of: forming a block dielectric layer and a sacrificial layer... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070178634 - Cmos semiconductor devices having dual work function metal gate stacks: CMOS semiconductor devices having dual work function metal gate structures that are formed using fabrication techniques that enable independent work function control for PMOS and NMOS device and which significantly reduce or otherwise eliminate impact on gate dielectric reliability.... Agent: F. Chau & Associates, LLC

20070178633 - Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same: A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from... Agent: Freescale Semiconductor, Inc. Law Department

20070178635 - Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. Attn: Edward J. Brooks, Iii

20070178636 - Method of manufacturing semiconductor device: The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is... Agent: Morrison & Foerster LLP

20070178637 - Method of fabricating gate of semiconductor device using oxygen-free ashing process: A method of fabricating a gate of a semiconductor device using an oxygen-free ashing process is disclosed. The method includes forming a high-k dielectric film, having a dielectric constant higher than a silicon oxide film, on a semiconductor substrate including an NMOS region and a PMOS region, forming an etching... Agent: Myers Bigel Sibley & Sajovec

20070178638 - Semiconductor device and fabrication method thereof: A semiconductor device includes a first insulating layer and a second insulating layer in a trench. The first insulating layer insulates two MOSFETs from each other, and the second insulating layer has a true stress opposite to a true stress of the first insulating layer. The second insulating layer includes... Agent: Nixon & Vanderhye, PC

20070178639 - Triple-well cmos devices with increased latch-up immunity and methods of fabricating same: A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in... Agent: Schmeiser, Olsen & Watts

20070178640 - Capacitor fabrication methods and capacitor constructions: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at... Agent: Wells St. John P.s.

20070178641 - Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuit: The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded... Agent: Wells St. John P.s.

20070178642 - Methods for fabricating dram semiconductor devices including silicon epitaxial and metal silicide layers: Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in... Agent: Myers Bigel Sibley & Sajovec

20070178643 - Memory utilizing oxide-conductor nanolaminates: Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070178644 - Semiconductor device having an insulating layer and method of fabricating the same: A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be... Agent: Harness, Dickey & Pierce, P.L.C

20070178645 - Method for manufacturing semiconductor device: The present invention provides a method for manufacturing semiconductor device. An element isolation structural portion is formed in a semiconductor substrate, an element isolation gate insulating film is deposited, a floating gate film is deposited, a spacer film is deposited, and an etching resistant mask pattern is formed on the... Agent: Volentine & Whitt PLLC

20070178646 - Method of forming a layer comprising epitaxial silicon: The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material... Agent: Wells St. John P.s.

20070178647 - Semiconductor devices having recessed structures and methods of forming the same: A method for forming a semiconductor device is provided. The method includes providing a substrate having a plurality of protrusions projecting from the substrate; forming a silicon layer over the substrate and each protrusion; performing an anisotropic etching to transfer the silicon layer into a silicon spacer positioned on a... Agent: Ingrassia Fisher & Lorenz, P.C.

20070178648 - Different-voltage device manufactured by a cmos compatible process and high-voltage device used in the different-voltage device: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate.... Agent: J C Patents, Inc.

20070178649 - Double-gated non-volatile memory and methods for forming thereof: A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between... Agent: Freescale Semiconductor, Inc. Law Department

20070178650 - Heterojunction tunneling field effect transistors, and methods for fabricating the same: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species... Agent: Scully Scott Murphy & Presser, PC

20070178651 - Method for preparing a source material for ion implantation: The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method includes providing (110) a deliquescent ion implantation source material and mixing (110) the deliquescent ion implantation source material with an organic liquid to form a paste.... Agent: Texas Instruments Incorporated

20070178652 - Structure and method to form source and drain regions over doped depletion regions: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as... Agent: William Stoffel

20070178653 - Apparatus and method for manufacturing flat display panel: Disclosed are an apparatus and method for manufacturing a flat display panel. In forming sustain electrodes and address electrodes, to which electricity is supplied to discharge, on front and rear panels, electrode material, which resides in electrode forming grooves formed on the surface of an electrode roll and each having... Agent: Ked & Associates, LLP

20070178654 - Metal capacitor including lower metal electrode having hemispherical metal grains: Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, a dielectric layer formed on the lower metal electrode containing Ti and... Agent: Marger Johnson & Mccollom, P.C.

20070178655 - Method for fabricating micrometer or nanometer channels: Thin films, which are deposited on a sacrificial film on a substrate, are released and bonded back on a substrate surface. This technology provides open and closed 2D confined micro-/nano-channels and channel networks on a substrate surface. The geometry, size and complexity of the channels and channel networks can be... Agent: Straub & Pokotylo

20070178656 - Structure and method for hyper-abrupt junction varactors: Method of fabricating a varactor that includes providing a semiconductor substrate, doping a lower region of the semiconductor substrate with a first dopant at a first energy level, doping a middle region of the semiconductor substrate with a second dopant at a second energy level lower than the first energy... Agent: Greenblum & Bernstein, P.L.C

20070178657 - Method of manufacturing a semiconductor device: A semiconductor device manufacturing method whereby a capacitor protective layer for ferroelectric capacitors of FeRAM can be prevented from peeling off. A lower electrode layer, a ferroelectric layer and an upper electrode layer are successively formed one upon another. The upper electrode layer is etched to form an upper electrode... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070178658 - Patterning and aligning semiconducting nanoparticles: A method is provided for making a device comprising aligned semiconducting nanoparticles and a receptor substrate comprising the steps of: a) aligning a plurality of first semiconducting nanoparticles; b) depositing the aligned first semiconducting nanoparticles on a first donor sheet; and c) transferring at least a portion of the aligned... Agent: 3m Innovative Properties Company

20070178659 - Process monitor mark and the method for using the same: The invention is directed to a mark pattern for forming a process monitor mark in a patterned underlayer to monitor a patterning result of a photoresist layer over the patterned underlayer around the boundary between a peripheral region and a device region of a die, wherein the patterned underlayer is... Agent: J.c. Patents, Inc.

20070178663 - Methods of forming a trench having side surfaces including a uniform slope: Provided herein are methods of forming a trench including forming a mask layer on a substrate, forming a mask pattern to expose the substrate, using plasma to at least partially remove by-products produced during formation of the mask pattern; and etching the exposed substrate to form a trench having side... Agent: Myers Bigel Sibley & Sajovec

20070178661 - Method of forming a semiconductor isolation trench: A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a... Agent: Freescale Semiconductor, Inc. Law Department

20070178662 - Method of forming isolation structures in a semiconductor manufacturing process: A method for forming shallow trench isolation structures is disclosed. The methods include providing a substrate having an upper surface and having an opening extending down from said upper surface, providing a first dielectric layer over at least a portion of the upper surface of the substrate and filling the... Agent: Baker & Mckenzie LLP Patent Department

20070178660 - Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation: A method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for example a lower-quality silicon dioxide to be used to fill the deep trench... Agent: Schneck & Schneck

20070178664 - Shallow trench isolation structure and method of fabricating the same: A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP) oxide layer substantially filling the trench.... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070178665 - Systems and methods for forming integrated circuit components having precise characteristics: A method of forming integrated circuit components is provided. A photomask is provided that includes a first mask feature having a mask feature geometry corresponding to a first type of integrated circuit (IC) component. A first lithography process is performed to transfer the first mask feature geometry to a semiconductor... Agent: Baker Botts L.L.P. Patent Department

20070178666 - Integrated circuit system with waferscale spacer system: An integrated circuit system is provided including forming integrated circuits on a wafer using a semiconductor manufacturing process; forming a waferscale spacer system on the integrated circuits on the wafer using the semiconductor manufacturing process; and singulating the wafer to have portions of the waferscale spacer system on the integrated... Agent: Ishimaru & Zahrt LLP

20070178667 - Wafer level chip scale package system: A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the... Agent: Ishimaru & Zahrt LLP

20070178668 - Epitaxial wafer and method for producing epitaxial wafers: A method for the production of an epitaxial wafer, characterized by using as a substrate a base plate of nitrogen- and carbon-added silicon single crystal having a nitrogen concentration of 5×1014 to 5×1015 atoms/cm3 and a carbon concentration of 1×1016 to 1×1018 atoms/cm3, having a crystal growth condition during the... Agent: Kolisch Hartwell, P.C.

20070178669 - Method of manufacturing semiconductor device and apparatus for processing substrate: A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant... Agent: Oliff & Berridge, PLC

20070178670 - Methods for preparing crystalline films: Methods of forming crystalline films on a substrate are provided. The crystalline films may be formed using amorphous nanoparticles. Methods of forming dispersions of amorphous nanoparticles are also provided.... Agent: Calfee Halter & Griswold, LLP

20070178671 - Gan bulk growth by ga vapor transport: GaN is grown by creating a Ga vapor from a powder, and using an inert purge gas from a source to transport the vapor to a growth site where the GaN growth takes place. In one embodiment, the inert gas is N2, and the powder source is GaN powder that... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070178674 - Laser annealing device and method for producing thin-film transistor: A laser annealing device (10) includes a laser oscillator (12), radiating a pulsed laser light beam of a preset period, and an illuminating optical system (15) for illuminating a pulsed laser light beam to an amorphous silicon film (1). The illuminating optical system (15) manages control for moving a laser... Agent: Sonnenschein Nath & Rosenthal LLP

20070178672 - Laser irradiation method, laser irradiation apparatus and method for manufacturing semiconductor device: In conducting laser annealing using a CW laser or a quasi-CW laser, productivity is not high as compared with an excimer laser and thus, it is necessary to further enhance productivity. According to the present invention, a fundamental wave is used without putting laser light into a non linear optical... Agent: Eric Robinson

20070178673 - Silicon based nanospheres and nanowires: A nanowire, nanosphere, metallized nanosphere, and methods for their fabrication are outlined. The method of fabricating nanowires includes fabricating the nanowire under thermal and non-catalytic conditions. The nanowires can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the method of fabricating nanospheres includes fabricating... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070178675 - Sintered semiconductor material: The invention relates to a method for forming a semiconductor material obtained by sintering powders and to a semiconductor material. The method comprises a compression and heat treatment stage such that one part of the powder is melted or becomes viscous. The material can be used in the photovoltaic field.... Agent: Plevy, Howard & Darcy, P.C.

20070178676 - Method of forming semiconductor multi-layered structure: Disclosed herein is a method of forming a single crystal SiC on a Si Substrate wherein a SiGe layer lower in melting point than Si and SiC and an amorphous SiC are formed on the Si layer and this structure is annealed at a temperature higher than the melting point... Agent: Miles & Stockbridge PC

20070178677 - Locos self-aligned twin well with a co-planar silicon surface: A method and system for providing a twin well in a semiconductor device is described. The method and system include masking a first portion of the device such that a second portion of the device is exposed. A sacrificial layer has a first portion on the first portion of the... Agent: Sawyer Law Group LLP

20070178678 - Methods of implanting ions and ion sources used for same: Methods of ion implantation and ion sources used for the same are provided. The methods involve generating ions from a source feed gas that comprises multiple elements. For example, the source feed gas may comprise boron and at least two other elements (e.g., XaBbYc). The use of such source feed... Agent: Mark Superko Varian Semiconductor Equipment Associates, Inc.

20070178679 - Methods of implanting ions and ion sources used for same: A method of implanting ions comprising generating C2B10Hx, ions from C2B10H12 and implanting the C2B10Hx, ions in a material. In some embodiments, the molecular weight of the C2B10Hx, ions is greater than 100 amu. In other embodiments, the molecular weight of the C2B10Hx, ions is approximately 132 to 144 amu... Agent: Varian Semiconductor Equipment Assc., Inc.

20070178680 - Method for manufacturing simox wafer: A SIMOX wafer having a BOX layer with a thin film thickness is obtained without a reduction in productivity or deterioration in quality. In a method for manufacturing a SIMOX wafer comprising: a step of forming a first ion-implanted layer in a silicon wafer; a step of forming a second... Agent: Reed Smith, LLP Attn: Patent Records Department

20070178681 - Semiconductor device having a plurality of metal layers deposited thereon: A semiconductor device has a plurality of stacked metal layers. The semiconductor device includes a substrate, a gate oxide layer deposited on the substrate and formed from a high-k dielectric material, a first metal layer deposited on the gate oxide layer and formed from a nitride of a metal of... Agent: Cantor Colburn, LLP

20070178682 - Damage-free sculptured coating deposition: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of:... Agent: Kenyon & Kenyon LLP

20070178683 - Semiconductive device fabricated using a two step approach to silicide a gate and source/drains: In one aspect, the invention provides a method of fabricating a semiconductive device [200], comprising siliciding a gate [340] with a first silicidation layer [710], removing a protective layer [510] to expose source/drains [415], and siliciding the gate [340] and the source/drains [415] with a second silicidation layer.... Agent: Texas Instruments Incorporated

20070178686 - Interconnect substrate, semiconductor device, and method of manufacturing the same: An interconnect substrate includes an interconnect, an insulating layer, a non-photosensitive resin layer, a photosensitive resin layer, a first electrode pad, and a second electrode pad. The non-photosensitive resin layer is constructed with a non-photosensitive insulating material. Also, the non-photosensitive resin layer has a first opening. The photosensitive resin layer... Agent: Young & Thompson

20070178685 - Method of increasing the etch selectivity in a contact structure of semiconductor devices: By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectivity of the contact structure may be increased by a modification... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070178684 - Method for producing conductor arrays on semiconductor devices: A periodic pattern of conductor tracks with broader interspaces is produced by the application of a totally periodic pattern and subsequent removal of individual conductor tracks. An alternative method comprises the formation of a completely periodic hardmask, from which individual parts are removed. The modified hardmask is then used to... Agent: Slater & Matsil LLP

20070178687 - Method of manufacturing semiconductor device and display device: To provide a method of forming a wiring for the purpose of providing a semiconductor device, which is superior in reliability and cost performance. Further, to provide methods of manufacturing a semiconductor device and a display device by using the method of forming the wiring according to the present invention.... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070178688 - Method for forming multi-layer bumps on a substrate: A method for forming multi-layer bumps on a substrate includes depositing an adhesive or a flux on the substrate, depositing a first metal powder on the adhesive, and melting or reflowing the adhesive and first metal powder to form first bumps. An adhesive or a flux and a second metal... Agent: Freescale Semiconductor, Inc. Law Department

20070178689 - Gallium nitride based iii-v group compund semiconductor device and method of producing the same: A gallium nitride-based III-V Group compound semi-conductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.... Agent: Nixon & Vanderhye, PC

20070178690 - Semiconductor device comprising a metallization layer stack with a porous low-k material having an enhanced integrity: By using a patterned sacrificial layer for forming highly conductive metal regions, the formation of a reliable conductive barrier layer may be accomplished prior to the actual deposition of a low-k dielectric material. Hence, even highly porous dielectrics may be used in combination with highly conductive metals, substantially without compromising... Agent: J. Mike Amerson, Williams, Morgan & Amerson, P.C.

20070178691 - Technique for non-destructive metal delamination monitoring in semiconductor devices: By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of... Agent: Williams, Morgan & Amerson

20070178692 - Multi-step process for forming a barrier film for use in copper layer formation: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer... Agent: Lsi Logic Corporation

20070178693 - Interlayer interconnect of three-dimensional memory and method for manufacturing the same: An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection transistors, because of special arrangement of lines and first plugs as well as line layouts. The line layouts involve disposing a plurality of lines... Agent: Ishimaru & Zahrt LLP

20070178694 - Pass through via technology for use during the manufacture of a semiconductor device: A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coupled to the wafer, while the other... Agent: Micron Technology, Inc.

20070178695 - Methods of forming electrically conductive plugs and method of forming resistance variable elements: A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An electrically conductive material is formed within the opening and elevationally over the insulative material. Some of the conductive material is removed effective to recess an outermost... Agent: Wells St. John P.s.

20070178696 - Method for silicide formation on semiconductor devices: A method for forming nickel silicide includes degassing a semiconductor substrate that includes a silicon surface. After the degassing operation, the substrate is cooled prior to a metal deposition process, during a metal deposition process, or both. The cooling suppresses the temperature of the substrate to a temperature less than... Agent: Duane Morris LLPIPDepartment (tsmc)

20070178697 - Copper electrodeposition in microelectronics: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves rapid bottom-up deposition at a superfill speed by which Cu deposition in... Agent: Senniger Powers

20070178700 - Compositions and methods for cmp of phase change alloys: The present invention provides a chemical-mechanical polishing (CMP) composition suitable for polishing a substrate comprising a phase change alloy (PCA), such as a germanium-antimony-tellurium (GST) alloy. The composition comprises not more than about 6 percent by weight of a particulate abrasive material in combination with an optional oxidizing agent, at... Agent: Steven Weseman Associate General Counsel, I.p.

20070178699 - Method and system for advanced process control in an etch system by gas flow control on the basis of cd measurements: By controlling the flow rate of one or more gaseous components of an etch ambient during the formation of metal lines and vias on the basis of feedback measurement data from critical dimensions, process variations may be reduced, thereby enhancing performance and reliability of the respective metallization structure.... Agent: J. Mike Amerson Williams Morgan & Amerson, P.C.

20070178698 - Substrate processing apparatus and fabrication process of a semiconductor device: A substrate processing apparatus includes a processing vessel evacuated by an evacuation system and including therein a stage for holding thereon a substrate to be processed, the processing vessel defining therein a processing space, a processing gas supply path that introduces an etching gas into the processing vessel, a plasma... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070178701 - Method of processing a substrate: There is disclosed a method of processing a substrate, which comprises applying a surfactant or a water soluble polymer agent onto a surface of a substrate to be processed, and sliding a circumferential portion of the substrate and a polishing member against each other to polish the circumferential portion of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070178702 - Residue treatment system, residue treatment method, and method of manufacturing semiconductor device: This disclosure concerns a residue treatment system including a treatment tank which treats residue with etching fluid, the residue being generated in a trench formed in an insulating film by dry etching; a measurement unit which measures a characteristic amount of the etching fluid; and a control unit which calculates... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070178703 - Method for release of surface micromachined structures in an epitaxial reactor: A method for releasing from underlying substrate material micromachined structures or devices without application of chemically aggressive substances or excessive forces. The method starts with the step of providing a partially formed device, comprising a substrate layer, a sacrificial layer deposited on the substrate, and a function layer deposited on... Agent: Kenyon & Kenyon

20070178704 - Lithographic apparatus and device manufacturing method: The invention provides a lithographic apparatus including an illumination system configured to condition a radiation beam, a patterning device support constructed to support a transmissive patterning device, the patterning device being capable of imparting the radiation beam with a pattern in its cross-section to form a patterned radiation beam, a... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070178705 - Poly etch without separate oxide decap: The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon (poly) etch process, results in a single step rapid poly etch process having uniform etch initiation and a high etch selectivity, that may... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070178706 - Cleaning solution for silicon surface and methods of fabricating semiconductor device using the same: A cleaning solution and methods of fabricating semiconductor devices using the same are provided. A cleaning solution used for cleaning a silicon surface and methods of fabricating a semiconductor device using the same are also provided. The cleaning solution may include 0.01 to 1 wt % of fluoric acid, 20... Agent: Harness, Dickey & Pierce, P.L.C

20070178708 - Vapor deposition system and vapor deposition method for an organic compound: There is provided a vapor deposition system including a vapor depositing source, holding means for holding a substrate, moving means, and an opening member having an opening, the moving means moving at least one of the substrate, and, the vapor depositing source and the opening member, in one direction in... Agent: Fitzpatrick Cella Harper & Scinto

20070178707 - Device manufacturing method and device: A method for patterning a polished silicon surface is disclosed, the method including steps leading to an organic monolayer on at least a part of the silicon surface, the monolayer being functionalized in specific desired locations. The method can be used to produce a device comprising one or more FET... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070178709 - Method of forming nanowires with a narrow diameter distribution: The growth of nanowires with a narrow diameter distribution is provided. The growth comprises: providing a substrate; providing a plurality of nanoparticles having a distribution of particle sizes on the substrate; initiating growth of nanowires by a vapor-liquid-solid technique; and terminating growth of the nanowires.... Agent: Hewlett Packard Company

20070178710 - Method for sealing thin film transistors: A method for sealing thin film transistors comprises providing a thin film transistor comprising a gate electrode, a gate dielectric, a source and a drain electrode, and an semiconductor layer; and vapor depositing a sealing material on at least a portion of the semiconductor layer through a pattern of an... Agent: 3m Innovative Properties Company

20070178711 - Semiconductor constructions, methods of patterning photoresist, and methods of forming semiconductor constructions: The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relative to one another. The invention also includes methods of patterning photoresist in which a saturable absorption... Agent: Wells St. John P.s.

20070178712 - Planarization for integrated circuits: A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion techniques.... Agent: Texas Instruments Incorporated

20070178713 - Method for forming a dielectric layer with an air gap, and a structure including the dielectric layer with the air gap: A method of forming a semiconductor structure includes providing a first dielectric layer with an opening above a substrate. An exposed surface portion of the first dielectric layer in the opening is transformed. A protective dielectric layer is formed along the transformed portion of the first dielectric layer. The opening... Agent: Duane Morris LLPIPDepartment (tsmc)

20070178714 - Method and system for high-speed precise laser trimming and scan lens for use therein: A method, system and scan lens for use therein are provided for high-speed, laser-based, precise laser trimming at least one electrical element along a trim path. The method includes generating a pulsed laser output with a laser, the output having one or more laser pulses at a repetition rate. A... Agent: Brooks Kushman P.C.