Semiconductor device manufacturing: process inventions 07/07

20070172967 - Pattern forming method and pattern forming system: Method of forming a pattern by a nanoimprint technique starts with preparing a mold with nanostructures on its surface. The mold is pressed against a substrate or plate coated with a resin film. The positions of alignment marks formed on the rear surface of the plate coated with the resin... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070172976 - Wafer encapsulated microelectromechanical structure and method of manufacturing same: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or... Agent: Neil A. Steinberg

20070172979 - Method of manufacturing electronic device using ink-jet method: The present invention relates to a manufacturing method which uses an ink jet method for forming various kinds of thin films in an electronic device such as an organic EL panel or an organic thin film transistor and ink suitably used in the method. The manufacturing method manufactures an electronic... Agent: Reed Smith LLP

20070172964 - Method of forming self-aligned contact via for magnetic random access memory: A method of forming a self-aligned contact via for a MRAM is disclosed. A first conductive layer, a pinned layer, a tunneling barrier layer, a free layer, a capping layer and a first dielectric layer are formed sequentially over a substrate has formed lots of transistors and interconects. A portion... Agent: Jianq Chyun Intellectual Property Office

20070172966 - Automatic on-die defect isolation: Microcircuits may include polysilicon features that are vulnerable to defects due to undesirable phenomena during manufacturing processes such as, inter alia, over-etching. The same phenomena that may cause defects can be exploited to automatically isolate the affected circuit and thus limit the harm caused by defects or incipient defects.... Agent: Robert O'rourke Blakely, Sokoloff, Taylor & Zafman LLP

20070172968 - Method of processing semiconductor substrate: A method of processing a semiconductor substrate for manufacturing a semiconductor device includes: obtaining pattern density information of the semiconductor product; applying the pattern density information to a previously determined relation between pattern densities and etch parameters so as to obtain process conditions for the semiconductor product; and etching the... Agent: Mills & Onello LLP

20070172965 - Non-destructive trench volume determination and trench capacitance projection: Methods of determining trench volume are disclosed. In one embodiment, the method includes providing a semiconductor substrate with at least one trench in a trench area; filling each trench with a filling material; measuring a step height between the trench area and a trench free area; and determining the trench... Agent: Hoffman, Warnick & D'alessandro LLC

20070172969 - Additive printed mask process and structures produced thereby: A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask... Agent: Jonathan A. Small JasIPConsulting

20070172970 - Method of manufacturing a solid-state imaging device: A method of manufacturing a solid-state imaging device, wherein the solid-state imaging device comprising: a semiconductor substrate; a plurality of photodiodes that are formed on a surface of the semiconductor substrate so as to be arranged in an array form; and a light shielding film, provided on or above the... Agent: Birch Stewart Kolasch & Birch

20070172971 - Desiccant sealing arrangement for oled devices: A method of encapsulating an OLED device, comprising: providing a substrate; forming an OLED device over the substrate, and a cover over the OLED device; and providing a desiccant sealing arrangement between the cover and the substrate, with the desiccant sealing arrangement provided by forming a perimeter seal and a... Agent: Pamela R. Crocker Patent Legal Staff

20070172972 - Manufacture method of display device: It is an object of the present invention to reduce the consumption of materials for manufacturing a display device, simplify the manufacturing process and the apparatus used for it, and lower the manufacturing costs. The present invention provides a technique to manufacture a display device, applying a means to form... Agent: Nixon Peabody, LLP

20070172973 - Method of making diode having reflective layer: A method of forming a light emitting diode includes forming a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A... Agent: Mckenna Long & Aldridge LLP

20070172974 - Fabrication method of cmos image sensor: Disclosed herein is a method of a method of fabricating a CMOS image sensor, in which process margin of a micro lens is secured to prevent defects from occurring in the micro lens to thereby improve the quality of image sensor products. An interlayer insulation layer is formed on a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070172975 - Semiconductor device and fabrication method thereof: A method of forming a MEMS structure over active circuitry in a semiconductor body includes forming active circuitry in a semiconductor body, and forming the MEMS structure over the active circuitry, wherein at least a portion of the MEMS structure spatially overlaps the active circuitry.... Agent: Texas Instruments Incorporated

20070172977 - Methods for forming alignment marks on semiconductor devices: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the... Agent: Myers Bigel Sibley & Sajovec

20070172978 - Manufacture of a polymer device: A method of forming a polymer device including the steps of: (i) depositing on a substrate a solution comprising a polymer or oligomer and a crosslinking moiety, to form a layer; (ii) curing the layer formed in step (i) under conditions to form an insoluble crosslinked polymer, characterized in that... Agent: Marshall, Gerstein & Borun LLP

20070172980 - Semiconductor apparatus manufacturing method: The semiconductor apparatus includes a semiconductor chip, and a source electrode and a gate electrode which are formed on the semiconductor chip and electrically connected with a lead frame. The source electrode is electrically connected with the lead frame by being laser-welded with a thin-film shaped connecting portion formed at... Agent: Foley And Lardner LLP Suite 500

20070172981 - Method for making flip chip on leadframe package: The present invention relates to a flip chip on leadframe package and the method for making the same. The method comprises: (a) providing a leadframe having a plurality of inner leads; (b) providing a chip having an active surface; (c) forming a plurality of first bumps and at least one... Agent: Volentine & Whitt PLLC

20070172982 - Three-dimensional package and method of making the same: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a... Agent: Volentine & Whitt PLLC

20070172983 - Three-dimensional package and method of making the same: The present invention relates to a three-dimensional package and a method of making the same. The three-dimensional package comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first solder, a second wafer, at least one second hole, a second isolation layer,... Agent: Volentine & Whitt PLLC

20070172984 - Three-dimensional package and method of making the same: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer... Agent: Volentine & Whitt PLLC

20070172985 - Three-dimensional package and method of making the same: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer... Agent: Volentine & Whitt PLLC

20070172986 - Three-dimensional package and method of making the same: The present invention relates to a three-dimensional package and a method of making the same. The three-dimensional package structure comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first metal, a first solder, a second wafer, at least one second hole,... Agent: Volentine & Whitt PLLC

20070172987 - Membrane-based chip tooling: A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at... Agent: Morgan & Finnegan, L.L.P.

20070172988 - Microstructure manufacturing method and microstructure: A microstructure, suitable for avoiding sticking phenomena, includes a base, a first structural portion joined to the base, and a second structural portion opposed to the base and having a fixed end fixed to the first structural portion. Such a microstructure is made by a method including the step of... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070172989 - Polymerization initiator systems containing aluminum compounds as curing inhibitors and polymerizable compositions made therewith: The invention is directed to a composition comprising an organoborane/amine complex and an effective amount of an aluminum compound to inhibit curing of the organoborane/amine complex when used as part of a polymerization initiator system in a polymerizable composition containing one or more monomers, oligomers or polymers having olefinic unsaturation.... Agent: Louis A Morris Akzo Nobel Inc

20070172990 - Method of packaging a semiconductor die and package thereof: A method of packaging a semiconductor die includes the steps of providing a flange (110), coupling one or more active die (341) to the flange with a lead-free die attach material (350), staking a leadframe (120) to the flange after coupling the one or more active die to the flange,... Agent: George C. Chen Bryan Cave LLP

20070172991 - Microstructure sealing tool and methods of using the same: A method of packing electronic devices and an apparatus thereof are disclosed herein. The method allows for usage of solder materials with a melting temperature of 180° C. or higher, such as from 210° C. to 300° C., and from 230° C. to 260° C., so as to provide reliable... Agent: Texas Instruments Incorporated

20070172992 - Methods for fabricating stiffeners for flexible substrates: Methods for fabricating stiffeners for flexible substrates, including, but not limited to, tapes, films, or other connective structures, which are configured to be secured to other semiconductor device components, are fabricated under control of a program. The stiffeners may be formed by selectively depositing or consolidating unconsolidated material. They may... Agent: Trask Britt, P.C./ Micron Technology

20070172993 - Flow cell and methods for using the same: A method of uniformly draining liquid from a patterned surface using a flow cell is provided. The method may be employed in a variety of applications, including in chemical array fabrication. In an exemplary embodiment, the invention provides an apparatus for fabricating a chemical array that employs a flow cell.... Agent: Agilent Technologies Inc.

20070172994 - Read-only memory device coded with selectively insulated gate electrodes: During fabrication of a mask read-only memory (ROM) device, a dielectric layer is grown on a substrate. Strip-stacked layers are formed on the dielectric layer, with each strip-stacked layer including a polysilicon and a silicon nitride layer. Source/drain regions are formed in the substrate between the strip-stacked layers, and spacers... Agent: Stout, Uxa, Buyan & Mullins LLP

20070172995 - Method for forming fuse of semiconductor device: A method for forming a fuse of a semiconductor device by forming a plate layer wherein a predetermined portion of the plate layer is cut by etching; forming an interlayer insulating film over the plate layer; forming a plate layer contact which is connected to the plate layer through the... Agent: Heller Ehrman LLP

20070172996 - Method of forming a semiconductor device with decreased undercutting of semiconductor material: A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer. A spacer is formed adjacent the vertical active region and over... Agent: Freescale Semiconductor, Inc. Law Department

20070172997 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070172998 - Thin film transistor substrate, method of manufacturing the same and liquid crystal display having the same: A thin film transistor substrate and method of manufacturing a thin film transistor substrate through a 3-sheet mask process includes forming a first conductive film on a substrate; forming a gate line including a gate electrode using a first photoresist film pattern formed on the first conductive film through a... Agent: Cantor Colburn, LLP

20070172999 - Method for manufacturing electronic device using thin film transistor with protective cap over flexible substrate: In a thin film semiconductor device realized on a flexible substrate, an electronic device using the same, and a manufacturing method thereof, the thin film semiconductor device and an electronic device include a flexible substrate, a semiconductor chip, which is formed on the flexible substrate, and a protective cap, which... Agent: Lee & Morse, P.C.

20070173000 - Method of manufacturing a semiconductor device: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the... Agent: Eric Robinson

20070173001 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes expanding an active region and a recess region by an epitaxial growth process. As a result, a margin is sufficiently secured in processes for forming a device isolation film that defines the active region and for expanding a recess region to form... Agent: Heller Ehrman LLP

20070173002 - Spacer t-gate structure for cosi2 extendibility: A semiconductor process and apparatus provide a T-shaped structure (84) formed from a polysilicon structure (10) and polysilicon spacers (80, 82) and having a narrower bottom dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may... Agent: Hamilton & Terrile, LLP

20070173003 - Methods of manufacturing semiconductor devices with rotated substrates: Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by... Agent: Slater & Matsil LLP

20070173004 - Epi t-gate structure for cosi2 extendibility: A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that... Agent: Hamilton & Terrile, LLP

20070173005 - Method for fabricating semiconductor device: A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention provides a channel region formed over a device isolation structure to form a semiconductor device including a SOI (Silicon-on-Insulator) channel structure, thereby decreasing ion implanting concentration of a channel region and improving tWR (Write... Agent: Townsend And Townsend And Crew, LLP

20070173006 - Semiconductor memory device and a method of manufacturing the same: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070173007 - Semiconductor device and method for fabricating the same: The semiconductor device includes an active region, a recess channel region, a storage node junction region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate, wherein a lower part of sidewalls of the active region is... Agent: Townsend And Townsend And Crew, LLP

20070173008 - Introduction of metal impurity to change workfunction of conductive electrodes: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice... Agent: Scully Scott Murphy & Presser, PC

20070173009 - Method of fabricating a dual-gate structure that prevents cut-through and lowered mobility: A method of fabricating a dual-gate semiconductor device, including forming a first PMOS transistor on a semiconductor substrate, the first PMOS transistor having a first gate electrode and a first gate insulation layer; and forming a first NMOS transistor on the semiconductor substrate, the first NMOS transistor having a second... Agent: Volentine & Whitt PLLC

20070173010 - Embedded phase-change memory and method of fabricating the same: An embedded memory required for a high performance, multifunction SOC, and a method of fabricating the same are provided. The memory includes a bipolar transistor, a phase-change memory device and a MOS transistor, adjacent and electrically connected, on a substrate. The bipolar transistor includes a base composed of SiGe disposed... Agent: Ladas & Parry LLP

20070173012 - Semiconductor device featuring common capacitor electrode layer, and method for manufacturing such semiconductor device: In a semiconductor device, a semiconductor substrate is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the substrate, and a conductive structure... Agent: Mcginn Intellectual Property Law Group, PLLC

20070173011 - Semiconductor device and method of manufacturing the same: Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of: forming a hydrogen diffusion preventing insulating film covering capacitors; forming a capacitor protecting insulating film on the hydrogen diffusion preventing insulating film; and forming a first insulating film on the capacitor protecting insulating film by a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070173013 - Semiconductor fabrication that includes surface tension control: In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a surface tension lowering agent.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070173014 - Method for forming memory cell and device: A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the access transistors selects which adjacent memory... Agent: Trask Britt, P.C./ Micron Technology

20070173015 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first and third device structures are device isolation... Agent: Townsend And Townsend And Crew, LLP

20070173016 - Integrated circuit system with dummy region: An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first region and the third region... Agent: Ishimaru & Zahrt LLP

20070173020 - Semiconductor device and method of manufacturing the same: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate containing silicon, the first insulating film having a first dielectric constant and constituting a part of a tunnel insulating film, forming a floating gate electrode film on the first insulating film, the floating gate electrode... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070173017 - Advanced non-volatile memory array and method of fabrication thereof: A method for creating a non-volatile memory array includes generating removable mask columns to define bit lines, implanting bit lines into the substrate at least between the columns, depositing oxide filler over the bit lines, removing the mask columns, depositing a polysilicon layer over the array and etching the polysilicon... Agent: Empk & Shiloh, LLP

20070173018 - Memory device fabrication: The invention provides methods of fabricating memory devices. One embodiment forms a bulk insulation layer overlying a plurality of source/drain regions formed in a substrate, removes a cap layer formed on each of a plurality of gate stacks formed on the substrate to expose an upper surface of each of... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20070173019 - Programmable resistive ram and manufacturing method: Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070173021 - Self-aligned trench mosfet structure and method of manufacture: PATENT A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided... Agent: Townsend And Townsend And Crew, LLP

20070173022 - Defect-free sige source/drain formation by epitaxy-free process: MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an... Agent: Slater & Matsil, L.L.P.

20070173023 - Semiconductor device manufacturing method: After gate insulating film formation films are formed in an element formation region of a semiconductor substrate, a gate electrode formation film is formed on the gate insulating film formation films. A fluorine-containing insulting film is formed on the gate electrode formation film. Then, thermal treatment is performed to diffuse... Agent: Mcdermott Will & Emery LLP

20070173024 - Method for producing two gates controlling the same channel: A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate... Agent: Hamilton & Terrile, LLP

20070173025 - Semiconductor device and method for fabricating the same: First and second gate portions each made of a gate insulating film, a silicon film, and a protective film are formed on a semiconductor substrate. Then, a first sidewall insulating film is formed on each of the side surfaces of the first and second gate portions. Subsequently, the protective film... Agent: Mcdermott Will & Emery LLP

20070173026 - Method for fabricating bipolar integrated circuits: The present invention discloses a method for fabricating bipolar integrated circuits, wherein LOCOS technology is used to define the active regions needed by all elements so that the self-alignment of the associated layers can be realized, and implant resistor regions are also directly defined in the active regions by local... Agent: Birch Stewart Kolasch & Birch

20070173027 - Semiconductor device and method of manufacturing the same: In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first... Agent: Mills & Onello LLP

20070173028 - Method of forming dielectric film and capacitor manufacturing method using the same: In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which the semiconductor substrate... Agent: Mcginn Intellectual Property Law Group, PLLC

20070173029 - Method for fabricating high performance metal-insulator-metal capacitor (mimcap): A method of fabricating a high performance metal-insulator-metal capacitor (MIMCAP) includes providing a first inter-level dielectric (ILD) layer over an isolation region; forming a MIMCAP pattern in the first ILD layer over the isolation region; depositing a conformal conductive liner over the MIMCAP pattern and the first ILD layer; depositing... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070173030 - Methods of forming a plurality of capacitors: The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor electrode openings are bounded on a first pair of opposing sides by a first capacitor electrode-forming material at one elevation and on... Agent: Wells St. John P.s.

20070173031 - Thin-film circuit device, method for manufacturing thin-film circuit device, and electronic apparatus: A thin-film circuit device includes a substrate and a thin-film circuit layer, disposed on the substrate, having an element region and a low-strength region. The element region includes thin-film elements. The low-strength region extends between an end portion of the thin-film circuit layer and the element region and has a... Agent: Harness, Dickey & Pierce, P.L.C

20070173033 - Method of fabricating a composite substrate with improved electrical properties: The invention concerns a method of fabricating a composite substrate comprising at least one thin insulating layer interposed between a support substrate and an active layer of semiconductor material. The method comprises: providing a source substrate that comprises a semiconductor material and a support substrate; forming or depositing an insulating... Agent: Winston & Strawn LLP Patent Department

20070173032 - Wafer dicing by channels and saw: In a silicon wafer two channels are etched in each street separated enough to bracket the saw. The channels may be shallow. The saw blade is positioned within the two channels so that the outer wall of each of the channels is beyond the outer edge of the saw. Cracks... Agent: Lexmark International, Inc. Intellectual Property Law Department

20070173034 - Method for manufacturing integrated circuit: A method for separating an integrated circuit formed by a thin film having a novel structure or a method for transfer-ring the integrated circuit to another substrate, that is, so-called transposing method, has not been proposed. According to the present invention, in the case that an integrated circuit having a... Agent: Eric Robinson

20070173035 - Manufacturing method of semiconductor device: When cutting a wafer, cutting is performed so that the portion of a V character-shaped shoulder may enter below the front surface of a wafer (depth Z2 from a substrate front surface) using the metal-bond blade which includes the abrasive particle whose fineness number is more than #3000, and whose... Agent: Mcdermott Will & Emery LLP

20070173036 - Production method of compound semiconductor light-emitting device wafer: The inventive production method of a compound semiconductor light-emitting device (LED)s wafer comprises a step of forming a protective film on the top and/or bottom surface of a compound semiconductor LEDs wafer, where the devices being regularly and periodically arranged with separation zones being disposed; a step of forming separation... Agent: Sughrue Mion, PLLC

20070173037 - Method of transferring strained semiconductor structures: The transfer of strained semiconductor layers from one substrate to another substrate involves depositing a multilayer structure on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse... Agent: Los Alamos National Security, LLC

20070173038 - Method for manufacturing semiconductor device: A method forming a semiconductor device includes forming a domed gate oxide film to relieve stress resulting from a thermal expansion rate difference of an oxide film and silicon film during a subsequent thermal process and preventing leakage current between source/drain regions through thickness regulation of the gate oxide film... Agent: Heller Ehrman LLP

20070173039 - Method for fabricating a semiconductor device and apparatus for inspecting a semiconductor: In a method for fabricating a semiconductor device and an apparatus for inspecting a semiconductor, laser processing is performed at different laser powers at different positions on a monitor substrate from a plurality of substrates having undergone an SPC step, to form polycrystalline silicon film over the entire area of... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20070173040 - Method of reducing an inter-atomic bond strength in a substance: A method of reducing an inter-atomic bond strength in a substance includes the steps of: providing a target material (110, 910, 1210, 1260, 1410, 1460); exposing the target material to a particle flood (140); and annealing the target material while exposing the target material to the particle flood. As an... Agent: Kenneth A. Nelson Bryan Cave LLP

20070173043 - Ion implantation system having variable screen aperture and ion implantation method using the same: An ion implantation system includes a source portion, a beam line portion, a target chamber having a platen, and a Faraday portion having a dose cup and a first variable screen aperture, wherein the platen is capable of moving in a second direction and supporting a semiconductor substrate, and the... Agent: Lee & Morse, P.C.

20070173042 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a gate structure comprising a stacked structure of a gate electrode and a gate hard mask layer over a semiconductor substrate having a device isolation structure. An insulating film filling up the gate structure is formed. A predetermined region of the... Agent: Heller Ehrman LLP

20070173041 - Method of manufacturing a semiconductor device and semiconductor device obtained with such a method: The invention relates to a method of manufacturing a semiconductor device (10) in which a semiconductor body (1) of silicon is provided, at a surface thereof, with a semiconductor region (4) of a first conductivity type, in which region a second semiconductor region (2A, 3A) of a second conductivity type,... Agent: Philips Intellectual Property & Standards

20070173044 - Wafer handler method and system: Systems and methods for handling wafers include retrieving a first wafer from a wafer cassette using a first arm, transferring the first wafer from the first transfer arm to a second arm, delivering the first wafer for processing to a process chamber using the second arm, removing the first wafer... Agent: Foley Hoag, LLP Patent Group, World Trade Center West

20070173045 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device having a back surface electrode, including: a step of preparing a semiconductor wafer having a front surface and a back surface; a thermal processing step of forming a first metal layer on the back surface of the semiconductor wafer and executing thermal processing,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070173046 - Substrate processing apparatus and method and a manufacturing method of a thin film semiconductor device: A substrate processing apparatus includes a plurality of evacuable treatment chambers connected to one another via an evacuable common chamber, and the common chamber is provided with means for transporting a substrate between each treatment chamber. More specifically, a substrate processing apparatus includes a plurality of evacuable treatment chambers, at... Agent: Eric Robinson

20070173047 - Fusi integration method using sog as a sacrificial planarization layer: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer... Agent: Texas Instruments Incorporated

20070173049 - Capacitor and method for fabricating the same: There is provided a capacitor and a method for fabricating the same. The method may include forming an interlayer insulation layer on a semiconductor substrate, patterning the interlayer insulation layer to form a contact hole exposing a region of the semiconductor substrate and forming a contact plug by filling the... Agent: Harness, Dickey & Pierce, P.L.C

20070173050 - Semiconductor device and method of manufacturing the same: A barrier metal film such as a TiN film is formed in a contact hole or a via hole. Then, a W nucleation film is formed on the barrier metal film by CVD that reduces WF6 gas with B2H6 gas. Subsequently, a W plug is formed as a contact plug... Agent: Mcdermott Will & Emery LLP

20070173048 - Method of manufacturing an electrical component: There is disclosed a method of manufacturing an electrical component, involving bonding a thin metal foil to an insulating substrate and thereby forming a component blank, and laser machining at least the metal foil of said component blank to produce at least one trench for defining one or more foil... Agent: Stites & Harbison PLLC

20070173051 - Method and/or system for forming a thin film: Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film are described.... Agent: Hewlett Packard Company

20070173052 - Electroplating method by transmitting electric current from a ball side: An electroplating method by transmitting electric current from a ball side is provided. In the electroplating method, the circuit layer is firstly formed on the bump side of the IC board, and the electric current is transmitted to the portion of the circuit layer uncovered by the insulating layer formed... Agent: Lin & Associates Intellectual Property

20070173053 - Method for manufacturing wiring and method for manufacturing semiconductor device: The present invention provides a method for manufacturing a wiring and a method for manufacturing a semiconductor device, which do not require a photolithography step in connecting a pattern of an upper layer and a pattern of a lower layer. According to the present invention, a composition including a conductive... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070173054 - Insulating film forming method capable of enhancing adhesion of silicon carbide film, etc. and semiconductor device: A first film made of silicon carbide is formed over a substrate. The surface of the first film is exposed to an oxidizing atmosphere to oxidize the surface layer of the first film. The surface of the first film is made in contact with chemical which makes the surface hydrophilic.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070173055 - Fabrication method of semiconductor device: A method for fabricating a semiconductor device includes the steps of forming an opening defined by an inner wall surface in an insulation film, forming a Cu—Mn alloy layer in the opening, depositing a Cu layer on the Cu—Mn alloy layer and filling the opening with the Cu layer, and... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070173056 - Semiconductor device fabrication method and polishing apparatus: A method for fabricating a semiconductor device includes forming a barrier metal film on a substrate with an opening defined therein, forming a copper-containing film on said barrier metal film after having formed said barrier metal film on a surface of said substrate and an inner wall of said opening,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070173057 - Method for fabricating storage node contact in semiconductor device: A method for fabricating a storage node contact in a semiconductor device includes forming a plurality of bit line patterns, each bit line pattern including a bit line hard mask formed over a bit line conductive layer, forming an inter-layer insulation layer filled between the bit line patterns, planarizing the... Agent: Townsend And Townsend And Crew, LLP

20070173058 - Semiconductor device: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be... Agent: Fish & Richardson P.C.

20070173059 - Process kit components for titanium sputtering chamber: A process kit for a sputtering chamber comprises a deposition ring, cover ring, and a shield assembly, for placement about a substrate support in a sputtering chamber. The deposition ring comprising an annular band with an inner lip extending transversely, a raised ridge substantially parallel to the substrate support, an... Agent: Janah & Associates, P.C.

20070173060 - Methods of forming electrically conductive plugs and method of forming resistance variable elements: A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An electrically conductive material is formed within the opening and elevationally over the insulative material. Some of the conductive material is removed effective to recess an outermost... Agent: Wells St. John P.s.

20070173061 - Copper metal interconnection with a local barrier metal layer: Embodiments relate to a method of forming a copper metal interconnection in a semiconductor device using a damascene process. In embodiments, the method may include forming a damascene pattern in an interlayer dielectric layer on a semiconductor substrate, burying a copper plating layer in the damascene pattern using an ECP... Agent: Sherr & Nourse, PLLC

20070173062 - Method of cleaning a surface of a cobalt-containing material, method of forming an opening to a cobalt-containing material, semiconductor processing method of forming an integrated circuit comprising a copper-containing conductive line, and a cobalt-conta: The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material, semiconductor processing methods of forming an integrated circuit comprising a copper-containing conductive line, and cobalt-containing film cleaning solutions. In one implementation, a method of cleaning a surface of a... Agent: Wells St. John P.s.

20070173063 - Self-aligned manufacturing method, and manufacturing method for thin film fuse phase change ram: A method for manufacturing a self aligned narrow structure over a wider structure based on mask trimming. A method for manufacturing a memory device comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures. The electrode layer includes a first electrode and a second electrode,... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070173064 - Manufacturing process for a transistor made of thin layers: m

20070173065 - Method for manufacturing semiconductor device: The invention is directed to a method for manufacturing semiconductor device. The method comprises steps of providing a substrate and then forming a dielectric material-containing device over the substrate. A plasma vapor deposition process is performed to form a dielectric layer over the substrate. A first baking process is performed.... Agent: Jianq Chyun Intellectual Property Office

20070173066 - Manufacturing method of electronic device: A manufacturing method of an electronic device, includes the steps of: implanting P (phosphorous) ions into a substrate semiconductor region made of Si or SiGe by using a resist as a mask; ashing the resist while it is heated in a vacuum environment; and taking out the substrate, the substrate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070173067 - Opening hard mask and soi substrate in single process chamber: Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon... Agent: Hoffman, Warnick & D'alessandro LLC

20070173068 - Etching of substrates of light emitting devices: Fabrication of a light emitting device includes etching of a substrate of the light emitting device. The etch may be an aqueous etch sufficient to increase an amount of light extracted through the substrate. The etch may be a direct aqueous etch of a silicon carbide substrate. The etch may... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070173069 - Method of forming insulating layer of semiconductor device: A method of forming an insulating layer on a silicon substrate in a process chamber is disclosed. The method comprises forming a nitride layer on the silicon substrate, and thereafter performing a thermal oxidation process on the silicon substrate and nitride layer, wherein the thermal oxidation process generates energized oxygen... Agent: Volentine & Whitt PLLC

20070173070 - Porous low-k dielectric film and fabrication method thereof: A method for fabricating a porous low-k dielectric film includes providing a substrate, performing a first CVD process by providing a back-bone precursor to form an interface dielectric layer, performing a second CVD process by providing a porogen precursor to form a back-bone layer, and removing the porogens in the... Agent: North America Intellectual Property Corporation

20070173071 - Sicoh dielectric: A porous composite material useful in semiconductor device manufacturing, in which the diameter (or characteristic dimension) of the pores and the pore size distribution (PSD) is controlled in a nanoscale manner and which exhibits improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water... Agent: Scully Scott Murphy & Presser, PC

20070173072 - Method for producing silicon oxide film: p

20070173073 - Porous silicon dielectric: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A manufacturing method comprises forming a layer of silicon over a substrate, forming an opening through the layer of silicon, filling the opening with a conductor; and anodically etching the layer of silicon so... Agent: Slater & Matsil LLP

20070173074 - Semiconductor interlayer dielectric material and a semiconductor device using the same: The present invention relates to low a dielectric material essential for a next generation semiconductor with high density and high performance, and more particularly to a low dielectric material that is thermally stable and has good film-forming properties and excellent mechanical properties, a dielectric film comprising the low dielectric material,... Agent: Mckenna Long & Aldridge LLP

20070173075 - Laser-based method and system for processing a multi-material device having conductive link structures: A laser-based method and system for selectively processing a multi-material device having a target link structure formed on a substrate while avoiding undesirable change to an adjacent link structure also formed on the substrate are disclosed. The method includes applying at least one focused laser pulse having a wavelength into... Agent: Brooks Kushman P.C.

20070173076 - Equipment for sensing malfunctioning roughing valves in an ion implantation apparatus: A system for detecting a malfunction of a roughing valve in an ion implantation apparatus, including a valve driving controller, at least one roughing valve having an open-state and a closed-state, at least one solenoid driver electrically connected to the valve driving controller and capable of operating the roughing valve,... Agent: Lee & Morse, P.C.

20070166849 - Method of manufacturing member with concave portions, member with concave portions, lens substrate, transmission type screen and rear projection: A method of manufacturing a member with concave portions includes preparing a base material, forming a mask formation film on the base material, forming a number of openings in the mask formation film by laser irradiation treatments using a branching filter, and etching the base material to form the concave... Agent: Harness, Dickey & Pierce, P.L.C

20070166858 - Method of manufacturing vertical inorganic alignment layer and liquid crystal display having the vertical inorganic alignment layer: In a method of manufacturing a vertical inorganic alignment layer and a liquid crystal display having the vertical inorganic alignment layer, a plasma power is applied to a plasma generating member attached to an outside of a reactor. When a process substrate to which a back-bias voltage and heat are... Agent: F. Chau & Associates, LLC

20070166857 - Rubbing system for alignment layer of lcd and method thereof: A rubbing system for an alignment layer of a liquid crystal display (LCD) device, comprises: a rubbing table on which a substrate having an alignment layer thereon is positioned; a rubbing roll on which a rubbing material is wound, substantially positioned on the rubbing table thus to substantially contact the... Agent: Mckenna Long & Aldridge LLP

20070166863 - Method for forming mirror devices for a digital light process apparatus: A method for forming mirror devices for a DLP apparatus. The method includes: forming a lower metal layer as wiring for driving a micromirror that perform light switching operation on a screen sensor; forming a lower inter-metal dielectric layer over the lower metal layer; forming a light path blocking plate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070166865 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same are provided. The method includes: preparing a semiconductor substrate in which a device isolation region and an active region are defined; forming a gate pattern including a gate oxide layer and a gate electrode on the semiconductor substrate; implanting... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070166870 - Method of forming a phase-changeable structure: In one embodiment, a phase-changeable structure can be formed by forming a phase-changeable layer on the lower electrode, forming a conductive layer on the phase-changeable layer, etching the conductive layer using a first etching material to form an upper electrode and etching the phase-changeable layer using a second etching material... Agent: Marger Johnson & Mccollom, P.C.

20070166871 - Npn-type low molecular aromatic ring compounds and organic semiconductors and electronic devices incorporating such compounds: Disclosed herein are NPN-type low molecular aromatic ring compounds, organic semiconductor layers formed from such compounds that exhibit improved electrical stability and methods of forming such layers using solution-based processes, for example, spin coating processes performed at or near room temperature. These NPN-type compounds may be used, either singly or... Agent: Harness, Dickey & Pierce, P.L.C

20070166839 - Method for fabricating magnetoresistance multi-layer: A fabrication method of a magnetoresistance multi-layer is provided. The method includes forming a multi-layer with at least an antiferromagnetic layer and performing an ion irradiation process to the multi-layer to transform a disordered structure of the antiferromagnetic layer to an ordered structure. Accordingly, the process time can be reduced... Agent: Jianq Chyun Intellectual Property Office

20070166838 - Method for patterning a ferroelectric polymer layer: Ferroelectric polymers such as for example copolymers of vinylidenedifluoride (VDF) and trifluoroethylene (TrFE) may be patterned by spincoating the ferroelectric polymer layer from a ferroelectric spincoating solution, which comprises a photosensitive crosslinker, onto a substrate followed by irradiating the ferroelectric polymer layer through a mask and removing the unexposed parts... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070166841 - Spin transistor and manufacturing method thereof: A spin transistor and a manufacturing method thereof are provided. The method includes defining a required area on a substrate by lithography; forming a doping area by ion-implantation, and forming a magnetoresistive film on the substrate. Finally, the method produces a spin transistor with the emitter, the base, and the... Agent: Rabin & Berdo, PC

20070166840 - Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit: Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition... Agent: Ryan, Mason & Lewis, LLP

20070166842 - Method for modifying circuit within substrate: The present invention relates to a method for modifying a circuit within a substrate, and the circuit includes a plurality of electrodes. The method includes: (a) selecting at least two from the plurality of electrodes for making connection; (b) removing materials covering said selected electrodes with a focused ion beam... Agent: Rosenberg, Klein & Lee

20070166843 - Method of repairing a light-emitting device and method of manufacturing a light-emitting device: A method of repairing a light-emitting device capable of performing high quality image display even if pinholes are formed when forming an organic compound layer is provided. Device contamination can be prevented during repair. By applying a reverse bias voltage to an organic light emitting element during fixed periods of... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070166844 - Ethcing method and system: An etching method and an etching system are adapted to produce a high etch selectivity for a mask, an excellent anisotropic profile and a large etching depth. An etching system according to the invention comprises a floating electrode arranged vis-à-vis a substrate electrode in a vacuum chamber and held in... Agent: Stites & Harbison PLLC

20070166845 - Method for measuring an amount of strain of a bonded strained wafer: The present invention is a method for measuring an amount of strain of a bonded strained wafer in which at least one strained layer is formed on a single crystal substrate by a bonding method, wherein at least, the bonded strained wafer is measured with respect to two asymmetric diffraction... Agent: Oliff & Berridge, PLC

20070166846 - Plasma doping method: It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a dose of boron is made substantially uniform, and the saturation time is comparatively long and ease to stably use, compared with a time at which... Agent: Mcdermott Will & Emery LLP

20070166847 - Boxes for soft error rate calculation: Memory and logic error rates are predicted by breaking each transistor into theoretical “boxes” with differing sensitivities to ionizing radiation. The box dimensions and critical charge are determined using physics-based equations. The box dimensions and critical charge are used to calculate soft error rate (SER). This box method may be... Agent: Honeywell International Inc.

20070166848 - Method and structure to prevent circuit network charging during fabrication of integrated circuits: An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the... Agent: Schmeiser, Olsen & Watts

20070166851 - Light emitting diodes (leds) with improved light extraction by roughening: Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.... Agent: Patterson & Sheridan, L.L.P.

20070166850 - Pattern forming apparatus and manufacturing apparatus using the same: A pattern forming apparatus 20 comprises a surface treatment system 13 and an ink jet system 14. A solvent is sprayed from a solvent spray nozzle 24 of the surface treatment system 13 to surface of a glass substrate 21 where a bus line pattern groove is formed. The ink... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070166852 - Diode-pumped microlasers including resonator microchips and methods for producing the same: A patent foramen ovale closure device, method of delivering and a delivery system are provided. The device may include a closure device releasably connectable to an actuator The device may include a proximal segment (206), an intermediate segment (210) and a distal segment (208). When delivered, the proximal segment and... Agent: Brown & Michaels, PC 400 M & T Bank Building

20070166853 - Led arrangement: The invention concerns an LED arrangement with at least one LED chip comprising a radiation decoupling surface through which the bulk of the electromagnetic radiation generated in the LED chip is decoupled. Arranged on the radiation decoupling surface is at least one phosphor layer for converting the electromagnetic radiation generated... Agent: Fish & Richardson PC

20070166854 - Passivation planarization: A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is subjected to a planarization process such as chemical mechanical polishing, mechanical abrasion, or etching. A spin-on-glass layer may be deposited over the non-uniform passivation layer... Agent: Dickstein Shapiro LLP

20070166855 - Display device and method of manufacturing the same: A display device comprises an insulating substrate, an organic semiconductor layer formed on the insulating substrate, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are interposed between the insulating substrate and the organic semiconductor layer, and spaced away from each other to define... Agent: Cantor Colburn, LLP

20070166860 - Active matrix type semicondcutor display device: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving... Agent: Eric Robinson

20070166859 - Array substrate for liquid crystal display device and manufacturing method thereof: An array substrate for an LCD device and a manufacturing method thereof. The array substrate includes: a gate line, a gate electrode, a gate pad, and a pixel electrode formed on the substrate; a gate insulation layer formed on the substrate to expose the gate line and the pixel electrode;... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20070166856 - Liquid crystal display device and method of fabricating the same: The present invention provides a liquid crystal display device and a method of fabricating the same capable of reducing the number of mask processes. The liquid crystal display device and the method of fabricating the sane includes: forming a gate electrode and a common electrode on a substrate; forming a... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20070166861 - Gallium nitride based light emitting diode and method of manufacturing the same: A GaN-based LED comprises a substrate; an an-type GaN layer formed on the substrate; an active layer formed on a predetermined region of the n-type GaN layer; a p-type GaN layer formed on the active layer; a transparent electrode formed on the p-type GaN layer; a p-electrode formed on the... Agent: Mcdermott Will & Emery LLP

20070166862 - Method for fabricating substrate with nano structures, light emitting device and manufacturing method thereof: A method of fabricating a substrate with nano structures, light emitting device using the substrate and a manufacturing method thereof, wherein a substrate for growing a light emitting device is formed with nano agglomerations, and the substrate is etched by using the agglomerations as a mask to allow nano structures... Agent: Mckenna Long & Aldridge LLP

20070166864 - Mirror package and method of manufacturing the mirror package: A mirror package is provided which can reflect a laser to an external screen according to a video signal when the laser enters from outside, and a method of manufacturing the mirror package. The mirror is packaged with a glass to protect from external contamination, an inlet and an outlet... Agent: Sughrue Mion, PLLC

20070166866 - Overmolded optical package: An optical semiconductor package includes a substrate, a chip, a plurality of bonding wires, a window, a supporter, and an encapsulant. The chip is disposed on the substrate and has an optical element. The bonding wires are used for electrically connecting the chip to the substrate. The window is supported... Agent: Lowe Hauptman Berner, LLP

20070166867 - Integrated circuit package system with image sensor system: An integrated circuit package system is provided including providing a wafer including image sensor systems having interconnects connected thereto and encapsulating the image sensor systems and interconnects in a transparent encapsulant. The system includes removing a portion of the transparent encapsulant to expose portions of the interconnects and singulating the... Agent: Ishimaru & Zahrt LLP

20070166868 - Method of fabricating an image sensor: A method of fabricating an image sensor on a semiconductor substrate having a sensor array region is described. A first planar layer is formed on a semiconductor substrate. Then, a color filter array (CFA) is formed on the first planar layer. A second planar layer is formed on the color... Agent: J.c. Patents, Inc.

20070166869 - Method for driving pixels of an organic light emitting display: A circuit and a method for driving pixels of an organic light-emitting display are provided. The circuit comprises a thin-film transistor having a source terminal connected to a voltage source, a storage capacitor having a first terminal connected to a gate terminal of the thin-film transistor, and an organic light-emitting... Agent: Jianq Chyun Intellectual Property Office

20070166873 - Organic electro luminescent display and manufacturing method thereof: A method for manufacturing an organic light emitting diode includes a lower substrate, a luminous element provided with upper and lower electrodes, and disposed on the lower substrate, a shielding layer disposed on the luminous element for shielding outer moisture, the shielding layer being formed of at least one layer,... Agent: Knobbe Martens Olson & Bear LLP

20070166872 - Process for producing thin photosensitized semiconducting films: The invention relates to a process for producing thin, semiconducting films photosensitized by one or more chromophores, which comprises at least one cycle comprising, in succession, the following steps: a) a step of depositing, on a support, at least one film of a solution obtained by sol-gel polymerization of one... Agent: Mckenna Long & Aldridge LLP

20070166874 - Fabrication method of nanoimprint mold core: A method for fabricating a nanoimprint mold core is disclosed. The method includes providing a substrate; forming on the substrate an amorphous thin film, which is transformed into a crystalline thin film upon receipt of energy, the crystalline thin film having physical and chemical characteristics different from those of the... Agent: Shoemaker And Mattare, Ltd

20070166877 - Electronic component and method for its assembly: An electronic component and method for its assembly is disclosed. In one embodiment, the electronic component comprises at least two semiconductor components and a circuit carrier comprising a die pad and a rewiring structure. At least one semiconductor component is a vertical semiconductor power switch having an upper surface comprising... Agent: Dicke, Billig & Czaja

20070166878 - Package structure and method for fabricating the same: A method for forming a package structure is disclosed. First, a wafer is provided, in which the front surface of the wafer includes a plurality of die areas and a plurality of scribe lines. Next, a plurality of cavities is formed on a back surface of the wafer with respect... Agent: North America Intellectual Property Corporation

20070166876 - Components, methods and assemblies for multi-chip packages: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used... Agent: Tessera Lerner David Et Al.

20070166875 - Method of forming a microelectronic package and microelectronic package formed according to the method: A microelectronic package, a substrate adapted to be used in forming the package, a method of forming the package, and a system including the package. The package includes a substrate; a die bonded to the substrate; a plurality of joint structures electrically bonding the die to the substrate. At least... Agent: Intel Corporation C/o Intellevate, LLC

20070166880 - Methods of fabrication of lead frame-based semiconductor device packages incorporating at least one land grid array package: Methods of fabrication of lead frame-based semiconductor device packages including at least one land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads of the interposer substrate. The terminal pads of the interposer substrate... Agent: Trask Britt

20070166879 - Multi-chip stack package and fabricating method thereof: A multi-chip stack package includes a substrate, a first chip, a second chip, a plurality of bumps, a plurality ofjunction interface bumps, a plurality of conductive wires, a filler material and an encapsulating material. The substrate has a plurality of first contacts and a plurality of second contacts thereon. The... Agent: Jianq Chyun Intellectual Property Office

20070166881 - Package structure and method for manufacturing the same: In the present invention, a package structure and the method for manufacturing the same are provided. The package structure includes a substrate and a chip flip-chip bonded to the substrate. The chip has central connecting pads and surrounding connecting pads surrounding the central connecting pads. A plurality of first bumps... Agent: Lowe Hauptman Berner, LLP

20070166882 - Methods for fabricating chip-scale packages having carrier bonds: A chip-scale package and method for making same. A pattern of conductive traces in the form of lead fingers is adhered to the active surface of a semiconductor die, preferably using a dielectric tape. The conductive traces are wire bonded to bond pads of the semiconductor die to establish electrical... Agent: Trask Britt, P.C./ Micron Technology

20070166884 - Circuit board and package structure thereof: A circuit board and a package structure thereof are proposed. The circuit board includes a main body and a solder mask layer covered on a surface of the main body. The circuit board is formed with a cutting path to define a plurality of array-arranged circuit board units, wherein the... Agent: Edwards Angell Palmer & Dodge LLP

20070166883 - Method of wafer level packaging and cutting: A packaging wafer has a plurality of cavities and a plurality of trenches on a front surface thereof. The packaging wafer is bonded to the element wafer, and a first cutting method is performed. Afterward a piece of tape is provided and is attached to the packaging wafer. Moreover, a... Agent: North America Intellectual Property Corporation

20070166885 - Electrode line structure having fine line width and method of forming the same: In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long axis direction. The electrode lines each include a... Agent: Mills & Onello LLP

20070166886 - Method for manufacturing an electronic module: This publication discloses a method for manufacturing an electronic module, in which manufacture commences from an insulating-material sheet (1). At least one recess (2) is made in the sheet (1) and extends through the insulating-material layer (1) as far as the conductive layer on the opposite surface (1a). A component... Agent: Baker & Daniels LLP

20070166887 - Semiconductor device structure and methods of manufacturing the same: A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070166889 - Method of forming a well of a nand flash memory device: Disclosed herein are a NAND flash memory device and a method of forming a well of the NAND flash memory device. Triple wells of a NAND flash memory device are formed within a cell region in plural. A cell block including flash memory cells is formed on the triple wells.... Agent: Marshall, Gerstein & Borun LLP

20070166888 - Semiconductor devices having improved field plates: A field effect transistor device and method, such device having source and drain electrodes in ohmic contact a semiconductor. A gate electrode-field plate structure is disposed between the source and drain electrodes. The gate electrode-field plate structure comprises: a dielectric; a first metal in Schottky contact the semiconductor; and a... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20070166891 - Method of fabricating a fin field effect transistor in a semiconductor device: A method for fabricating a fin FET in a semiconductor device. The method includes sequentially depositing first and second insulation films on a semiconductor substrate, etching the first and second insulation films using a first mask to form a trench, and depositing a first conductor in the trench.... Agent: Sherr & Nourse, PLLC

20070166890 - Pfets and methods of manufacturing the same: In a first aspect, a first method of manufacturing a PFET on a substrate is provided. The first method includes the steps of (1) forming a gate channel region of the PFET having a first thickness on the substrate; and (2) forming at least one composite source/drain diffusion region of... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20070166894 - Fabricating method for thin film transistor array substrate and thin film transistor array substrate using the same: A method of fabricating a thin film transistor array substrate and a thin film transistor array substrate using the same is disclosed. Picture quality deterioration may be prevented.... Agent: Mckenna Long & Aldridge LLP

20070166893 - Fabrication method for thin film transistor array substrate: Scan lines are formed on a substrate. A patterned dielectric layer and a patterned semiconductor layer are formed to cover portions of the scan lines. A patterned transparent conductive layer and a patterned metal layer are sequentially formed to define data lines, source/drain electrodes, pixel electrodes and etching protecting layers.... Agent: Jianq Chyun Intellectual Property Office

20070166895 - Display substrate and method of manufacturing the same: A three mask process for forming an LCD substrate includes, depositing in sequence on a base substrate a gate metallic layer, a gate insulation layer and a channel layer. A first photoresist pattern is used to form a gate electrode of a switching device, a channel pattern and a gate... Agent: Macpherson Kwok Chen & Heid LLP

20070166892 - Method and apparatus of fabricating semiconductor device: An underlying film forming section forming an underlying film on a semiconductor substrate is provided to an apparatus of fabricating a semiconductor device. The apparatus is further provided with a cooling section cooling the semiconductor substrate and a plasma nitriding section introducing active nitrogen into the underlying film while keeping... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070166896 - Method of fabricating a lateral double-diffused mosfet: A method of monolithically fabricating an LDMOS transistor with a fabrication process that is compatible with a sub-micron CMOS fabrication process. The specification further describes an LDMOS transistor. The LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a... Agent: Fish & Richardson P.C.

20070166897 - Strained si on multiple materials for bulk or soi substrates: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a... Agent: Scully, Scott, Murphy & Presser, P.C.

20070166898 - Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same: A method for forming a polysilicon structure is provided. An amorphous silicon structure with a first amorphous silicon region and a second amorphous silicon region is formed in a first region and a second region of a substrate, respectively. The first amorphous silicon region is thinner than the second amorphous... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070166899 - Method of synthesizing silicon wires: A method of synthesizing silicon wires generally includes the steps of: providing a substrate; forming a copper catalyst particle layer on a top surface of the substrate; heating the reactive device at a temperature of above 450° C. in a flowing protective gas; and introducing a mixture of a protective... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070166900 - Device fabrication by anisotropic wet etch: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes... Agent: Innovation Interface, LLC

20070166901 - Method for fabricating soi device: A semiconductor-on-insulator (SOI) device is described, including a substrate, a first insulating layer and a second insulating layer on the substrate, a semiconductor layer covering the first and the second insulating layers, a gate dielectric layer and a gate on the semiconductor layer, and two doped regions as source/drain regions... Agent: Jianq Chyun Intellectual Property Office

20070166905 - Method of manufacturing semiconductor device with trench: In an embodiment of the present invention, after trenches, a gate oxide film and gate electrodes are formed, a channel layer is formed by plural high-acceleration ion implantations where acceleration voltages are different with one another. The channel layer is an impurity implanted layer on which diffusion by a heat... Agent: Morrison & Foerster LLP

20070166902 - Method to control the gate sidewall profile by graded material composition: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition... Agent: Hamilton & Terrile, LLP

20070166904 - Pre-gate dielectric process using hydrogen annealing: The preferred embodiment of the present invention provides a novel method of forming MOS devices using hydrogen annealing. The method includes providing a semiconductor substrate including a first region and a second region, forming at least a portion of a first MOS device covering at least a portion of the... Agent: Slater & Matsil, L.L.P.

20070166903 - Semiconductor structures formed by stepperless manufacturing: A manufacturing method for an array of polysilicon fins built up into fin blocks that are aligned in a comb-like array occupying a wafer surface. By subsurface and supersurface contact, fin blocks can be arranged into components or even systems. The method involves wafer area masking and etching over the... Agent: Schneck & Schneck

20070166906 - Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon: The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one... Agent: Texas Instruments Incorporated

20070166907 - Semiconductor device and manufacturing method of the same: In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070166908 - Non-volatile memory device having dual gate and method of forming the same: A non-volatile memory device including a control gate pattern having a tunnel insulation pattern, a trap-insulation pattern, a blocking insulation pattern and a control gate electrode, which are stacked on a semiconductor substrate. A selection gate pattern is disposed on the semiconductor substrate at one side of the control gate... Agent: F. Chau & Associates, LLC

20070166913 - Semiconductor device and method of forming the same: There is provided a method of forming a semiconductor device. A dielectric layer including a metal (e.g., a gate insulating layer and/or a tunnel insulating layer) may be formed on a substrate, and a metal nitride layer containing more metal component than nitrogen may be formed on the dielectric layer... Agent: Harness, Dickey & Pierce, P.L.C

20070166911 - Bottom electrode of metal-insulator-metal capacitor and method of fabricating the same: A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal... Agent: Jianq Chyun Intellectual Property Office

20070166909 - Integrated thin-film resistor with direct contact: A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness... Agent: Ibm Microelectronics Intellectual Property Law

20070166910 - Memory structure, memory device and manufacturing method thereof: A memory structure, a memory device and a manufacturing method thereof are provided. First, a substrate is provided and a dielectric layer is formed over the substrate. Then, a pattern is formed in the dielectric layer. An amorphous silicon layer is formed in the pattern and over the dielectric layer.... Agent: Jianq Chyun Intellectual Property Office

20070166912 - Three-dimensional control-gate architecture for single poly eprom memory devices fabricated in planar cmos technology: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070166914 - Memory device and fabrication method thereof: A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower... Agent: Quintero Law Office, PC

20070166915 - Method for forming a storage cell capacitor compatible with high dielectric constant materials: Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion of the electrode in the opening and overlying the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070166917 - Non-volatile memory device and fabricating method therefor: A non-volatile memory device and fabricating method therefor are provided. The non-volatile memory device includes a substrate, a first insulating layer, a conductor layer, a second insulating layer, and charge storage units. Herein, the substrate, the first insulating layer, and the conductor layer are formed, respectively. Then, the second insulating... Agent: Morris Manning Martin LLP

20070166916 - Nanostructures-based optoelectronics device: A materials structure is presented which is based on the insertion of preformed nanocrystals of arbitrary shape on or into a non-crystalline, non-hydrocarbon barrier layer. Embodiments of the structure include a variety of barrier layers and contacts, which can be layered. When the structure is used as a detector or... Agent: Rodney T. Hodgson, Ph.d.

20070166918 - Non-volatile memory device, and manufacturing method and programming method thereof: A non-volatile memory device includes a plurality of select lines and a plurality of word lines formed over a semiconductor substrate, a contact plug formed between the select lines, and a conductive interference shielding line formed between the select line and a word line adjacent to the select line and... Agent: Townsend And Townsend And Crew, LLP

20070166919 - Nonvolatile semiconductor memory device and its manufacturing method: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070166920 - Transistor gate forming methods and transistor structures: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within... Agent: Wells St. John P.s.

20070166921 - Flash memory device and method of manufacturing the same: A non-volatile memory device has a gate dielectric film formed between a floating gate and a control gate. The gate dielectric film is formed by forming an oxide film and a ZrO2/Al2O3/ZrO2 (ZAZ) film. Accordingly, the reliability of non-volatile memory devices can be improved while securing a high coupling ratio.... Agent: Townsend And Townsend And Crew, LLP

20070166922 - Method of fabrication a double gate field effect transistor device and such a double gate field transistor device: The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the second gate. Then the substrate is bonded to a... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070166923 - Method for nitridation of the interface between a dielectric and a substrate in a mos device: A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon-nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top... Agent: Baker & Mckenzie LLP Patent Department

20070166924 - Memory cell and method for fabricating a memory device: When fabricating a memory cell with an organic storage layer which stores a digital information item, processing of polycrystalline and monocrystalline semiconductor structures in which high temperatures are employed is concluded prior to application of the organic storage layer.... Agent: Dicke, Billig & Czaja

20070166926 - Mos transistor with elevated source and drain structures and method of fabrication thereof: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In... Agent: Mills & Onello LLP

20070166925 - Semiconductor device: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the... Agent: Ditthavong Mori & Steiner, P.C.

20070166927 - Nrom flash memory devices on ultrathin silicon: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on... Agent: Leffert Jay & Polglaze, P.A.

20070166929 - Method of producing semiconductor wafer: A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is... Agent: Sughrue Mion, PLLC

20070166928 - Method for making an electronic device including a selectively polable superlattice: A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070166930 - Transistor of semiconductor device and method for fabricating the same: A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentration of implanted impurity ions on a semiconductor substrate; a channel... Agent: Sherr & Nourse, PLLC

20070166931 - Methods of manufacturing a semiconductor device for improving the electrical characteristics of a dielectric film: A method of manufacturing a semiconductor device includes depositing a high-dielectric film on a semiconductor substrate and performing an oxygen plasma treatment on the high-dielectric film deposited on the semiconductor substrate. The method further includes forming an electrode on the oxygen-plasma treated high-dielectric film.... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070166932 - Semiconductor device and method for fabricating the same: A method of fabricating a semiconductor device consistent with the present invention, the method comprising: forming an insulation film on a substrate; forming a mono-atomic layer of barrier ions at the insulation film; forming a gate insulation film in which the barrier ions are stabilized by an annealing process; forming... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070166933 - Methods of forming field effect transistors and capacitor-free dynamic random access memory cells: Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding the channel region protrusion by an electrical isolation region. A portion of a backside of the first semiconductor wafer is then removed to... Agent: Myers Bigel Sibley & Sajovec

20070166934 - Method for forming isolation layer of semiconductor device: A method for forming an isolation layer of a semiconductor device using a shallow trench isolation method is provided. The method includes: vertically etching a region of an insulating layer and a part of a semiconductor substrate corresponding thereto to form a trench; depositing an oxide layer on an entire... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070166935 - Method of fabricating nonvolatile memory device: Provided is a method of fabricating a nonvolatile memory device. According to the method, in a semiconductor substrate where a cell region and a logic region are defined, an isolation region and an active region are defined in each of the cell region and the logic region, and a low... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070166936 - Pre-amorphization implantation process and salicide process: A salicide process is described, wherein a substrate with an NMOS transistor and a PMOS transistor thereon is provided. A mask layer is formed over the substrate covering the PMOS transistor but exposing the NMOS transistor, and then a pre-amorphization implantation (PAI) step is conducted to the substrate using the... Agent: Jianq Chyun Intellectual Property Office

20070166937 - Dual metal silicide scheme using a dual spacer process: A semiconductor process and apparatus provide a polysilicon structure (10) and source/drain regions (12, 14) formed adjacent thereto in which a dual silicide scheme is used to form first silicide regions in the polysilicon, source and drain regions (30, 32, 34) using a first metal (e.g., cobalt). After forming sidewall... Agent: Hamilton & Terrile, LLP

20070166938 - Semiconductor device with high conductivity region using shallow trench: A structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity... Agent: Ishimaru & Zahrt LLP

20070166939 - Semiconductor device with bipolar transistor and method of fabricating the same: Disclosed is a semiconductor device with a bipolar transistor and method of fabricating the same. The device may include a collector region in a semiconductor substrate. A base pattern may be disposed on the collector region. A hard mask pattern may be disposed on the base pattern. The hard mask... Agent: Harness, Dickey & Pierce, P.L.C

20070166940 - Integrated semiconductor cascode circuit for high-frequency applications: An integrated semiconductor cascode circuit is provided that comprises an emitter layer, a first base area, a second base area, an intermediate area and a collector area. The first base area is arranged between the emitter layer and the intermediate area, and the second base area is arranged between the... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070166941 - Method of manufacturing a transistor of a semiconductor device: A method of manufacturing a transistor in which gate resistance is lowered and short channel effects are controlled by forming a trench-type gate. The threshold voltage can also be more tightly controlled.... Agent: Sherr & Nourse, PLLC

20070166942 - Circuit protection method using diode with improved energy impulse rating: A method for protecting a circuit from a high energy pulse includes placing a PPTC resistive element in series with the circuit and placing an energy pulse clamping semiconductor diode in shunt across the circuit and further includes forming the diode to have: a substrate with carriers of a first... Agent: Tyco Electronics Corporation

20070166943 - Method of fabricating semiconductor device having storage capacitor and higher voltage resistance capacitor and semiconductor device fabricated using the same: Provided are a method of fabricating a semiconductor device having different kinds of capacitors, and a semiconductor device formed using the same. In a fabrication process, after preparing a substrate including a storage capacitor region and a higher voltage resistance capacitor region, a lower electrode layer may be formed on... Agent: Harness, Dickey & Pierce, P.L.C

20070166944 - Method of making circuitized substrate: A method of making a circuitized substrate and an electrical assembly utilizing same in which the substrate is comprised of at least two sub-composites in which the dielectric material of at least one of these sub-composites is heated during bonding (e.g., lamination) to the other sufficiently to cause the dielectric... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20070166946 - Method of reducing film stress on overlay mark: An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not... Agent: Stout, Uxa, Buyan & Mullins LLP

20070166945 - Semiconductor thin film forming system: In a semiconductor thin film forming system for modifying a predetermined region of a semiconductor thin film by exposing the semiconductor thin film to a projected light patterned through a pattern formed on a photo mask, the system includes a mechanism (opt20′) for uniformizing the light for exposure in a... Agent: Hayes Soloway P.C.

20070166947 - Germanium on glass and glass-ceramic structures: A semiconductor-on-insulator structure including first and second layers which are attached to one another either directly or through one or more intermediate layers. The first layer includes a substantially single crystal germanium semiconductor material while the second layer comprises a glass or a glass-ceramic material having a linear coefficient thermal... Agent: Corning Incorporated

20070166948 - Buried silicon dioxide / silicon nitride bi-layer insulators and methods of fabricating the same: Embodiments of the present invention relate to the fabrication of a buried bi-layer insulator of silicon oxide and silicon nitride in a microelectronic substrate, and to the buried silicon oxide/silicon nitride bi-layer insulator itself. The buried silicon oxide/silicon nitride bi-layer insulator may be formed by implanting oxygen ions and nitrogen... Agent: Intel Corporation C/o Intellevate, LLC

20070166949 - Method for forming isolation layer in semiconductor devices: A method for forming an isolation layer for a semiconductor device is provided. The preferred method is capable of securing a gap fill margin during formation of an isolation layer. A device isolation layer formed according to a preferred method includes a trench formed in a device separation area of... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070166950 - Semiconductor device fabrication method for improving capability for burying a conductive film in the trenches of trench gates: A method of fabricating a semiconductor device includes: forming element isolation parts that enclose a plurality of active regions in which transistors are formed and that have profiles perpendicular to the substrate surface that are reverse tapered shapes; after forming the element isolation parts, forming an oxidation-resistant insulation mask that... Agent: Young & Thompson

20070166951 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device, includes preparing a work piece having a trench on its main surface side, forming a polymer film containing a polymer containing silicon, hydrogen and nitrogen on the main surface of the work piece, holding the work piece with the polymer film in a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070166952 - Dual isolation structure of semiconductor device and method of forming the same: There are provided an isolation structure of a semiconductor device for suppressing the generation of leakage current by preventing two adjacent well regions below an isolation oxide layer from being electrically connected to each other, and a method of forming the same. The dual isolation structure of a semiconductor device... Agent: Mayer, Brown, Rowe & Maw LLP

20070166953 - Semiconductor device and method of fabricating the same: A method of fabricating a transistor of a semiconductor device comprises forming first and second trenches for gates in a substrate; forming a liner layer on innerwalls of the first and second trenches; forming first and second epitaxial gate electrodes by performing an epitaxial growth on the first and second... Agent: Mayer, Brown, Rowe & Maw LLP

20070166954 - Method for manufacturing thin film integrated circuit device, noncontact thin film integrated circuit device and method for manufacturing the same, and idtag and coin including the noncontact thin film integrated circuit device: To provide a thin film integrated circuit which is mass produced at low cost, a method for manufacturing a thin film integrated circuit according to the invention includes the steps of: forming a peel-off layer over a substrate; forming a base film over the peel-off layer, forming a plurality of... Agent: Eric Robinson

20070166955 - Semiconductor device, method of manufacturing the same, and camera module: The invention provides a package type semiconductor device and a method of manufacturing the same where reliability and yield are enhanced without making a manufacturing process complex. A resin layer and a supporting body are formed on a front surface of a semiconductor substrate formed with a pad electrode. Then,... Agent: Morrison & Foerster LLP

20070166956 - Method for producing electronic chips consisting of thinned silicon: The sensor is fabricated from a semiconductor wafer (10) comprising, on its front face, a thin active layer (12) of semiconductor material, and for this purpose etched layers are formed on the active layer, the wafer is bonded by its front face onto a support substrate (40), the semiconductor wafer... Agent: Lowe Hauptman Gilman & Berner, LLP

20070166957 - Method of manufacturing semiconductor device: The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and... Agent: Morrison & Foerster LLP

20070166958 - Method of wafer level packaging and cutting: A packaging wafer having a plurality of cavities on an upper surface thereof is provided. A plurality of trenches is formed between the cavities, wherein the packaging wafer has a thickness greater than a depth of the trenches. The packaging wafer is bonded to an element wafer and a hermetical... Agent: North America Intellectual Property Corporation

20070166959 - Process for producing a photoelectric conversion device: A catalyst element remaining in a first semiconductor film subjected to a first heat treatment (crystallization) is moved and concentrated/collected by subjecting a second semiconductor film which is formed on the first semiconductor film and contains a rare gas element to a second heat treatment. That is, the rare gas... Agent: Eric Robinson

20070166961 - Fabrication method of semiconductor luminescent device: A fabrication method of a semiconductor luminescent device includes forming a compound semiconductor layer having a structure in which a first conductivity-type clad layer, an active layer, a second conductivity-type clad layer are layered in order on a substrate, the second conductivity-type being different from the first conductivity-type and forming... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070166960 - Method for forming a strained si-channel in a mosfet structure: Method for forming a strained Si layer on a substrate (1), including formation of: an epitaxial SiGe layer (4) on a Si surface, and of: the strained Si layer by epitaxial growth of the Si layer on top of the epitaxial SiGe layer (4), the Si layer being strained due... Agent: Philips Intellectual Property & Standards

20070166962 - Methods of forming layers comprising epitaxial silicon: The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing sidewalls of the opening are lined with a second material, with monocrystalline material being exposed at a base of the second material-lined opening.... Agent: Wells St. John P.s.

20070166963 - Method of forming a semiconductor thin film: A method of fabricating a semiconductor thin film is provided, comprising: forming an insulation layer on a semiconductor substrate; etching the insulation layer to form a plurality of openings exposing the substrate at the bottom of the openings; filling the openings with a semiconductor seed layer; forming an amorphous layer... Agent: F. Chau & Associates, LLC

20070166964 - Precursor containing copper indium and gallium for selenide (sulfide) compound formation: The present invention relates to systems and methods for preparing metallic precursor thin films for the growth of semiconductor compounds to be used for radiation detector and solar cell fabrication. In one aspect, there is provided a method of efficiently using expensive materials necessary for the making of solar cells.... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070166965 - Laser irradiation method, laser irradiation apparatus, and method for manufacturing semiconductor device: The present invention is to provide a technique that can increase productivity with high output power by combining a plurality of laser beams on an irradiation surface without any difficulties in optical alignment According to this technique, laser beams having different wavelengths are combined using a plurality of laser oscillators... Agent: Eric Robinson

20070166966 - Deposition from liquid sources: A liquid injector is used to vaporize and inject a silicon precursor into a process chamber to form silicon-containing layers during a semiconductor fabrication process. The injector is connected to a source of silicon precursor, which preferably comprises liquid trisilane in a mixture with one or more dopant precursors. The... Agent: Knobbe Martens Olson & Bear LLP

20070166967 - Method for controlling conductivity of ga2o3 single crystal: The light emitting element includes an n-type β-Ga2O3 substrate, and an n-type β-AlGaO3 cladding layer, an active layer, a p-type β-AlGaO3 cladding layer and a p-type β-Ga2O3 contact layer which are formed in order on the n-type β-Ga2O3 substrate. A resistivity is controlled to fall within the range of 2.0×10−3... Agent: Mcginn Intellectual Property Law Group, PLLC

20070166968 - Process for adjusting the strain on the surface or inside a substrate made of a semiconductor material: This invention relates to a process for adjusting the strain in a strained layer on a substrate. The process steps include identifying one or more regions of the strained layer wherein the strain is to be adjusted; implanting elements into at least one of the regions thus identified in the... Agent: Winston & Strawn LLP Patent Department

20070166969 - Semiconductor device and method for manufacturing the same: The invention provides a semiconductor device capable of protecting a low-concentration implantation region from contamination, and a method for manufacturing the same. A photoresist is formed on a TEOS film which is formed all over a substrate, and removed by photo engraving so as to be partially left. This photo... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070166971 - Manufacturing of silicon structures smaller than optical resolution limits: Method for forming silicon structures, such as upright gates or fins on a wafer substrate, particularly for use as a building block for semiconductor devices. The structures are smaller than can be resolved by conventional optical lithography. A plan of the area-wise dimensions of the fin or gate structure is... Agent: Schneck & Schneck

20070166970 - Ald gate electrode: A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (22) over a gate dielectric layer (11), forming a transition layer (32) over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition... Agent: Hamilton & Terrile, LLP

20070166972 - Semiconductor device and manufacturing method: A semiconductor substrate includes a plurality of isolation regions formed therein and having a trench in a region between the isolation wells, a gate insulating layer formed within the trench, a gate electrode formed on the gate insulating layer filling the trench, and source and drain electrodes formed on the... Agent: Sherr & Nourse, PLLC

20070166976 - Method of fabricating a semiconductor device: Embodiments relate to a method of fabricating a semiconductor device. In embodiments, a gate pattern may be formed on a semiconductor substrate, and sidewalls having a lower height than a height of the gate pattern may be formed at both sides of the gate pattern using a photoresist pattern. A... Agent: Sherr & Nourse, PLLC

20070166974 - Fabrication process of a semiconductor device: A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nickel film on a silicon substrate on which the insulation... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070166975 - Fabrication process of a semiconductor device: A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing the silicon substrate in a silane gas... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070166973 - Method for removing metal foot during high-k dielectric/metal gate etching: A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface... Agent: Hamilton & Terrile, LLP

20070166977 - Method of manufacture of semiconductor device: A semiconductor device manufacturing method is disclosed. A silicon-containing gate electrode is first formed above the surface of a silicon-containing semiconductor substrate. Then, a sidewall insulating film is formed on the sidewall of the gate electrode and a film of metal is formed on the semiconductor substrate to cover the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070166985 - Fabrication method of thin film and metal line in semiconductor device: A method for fabricating a thin layer in a semiconductor device is provided. The method can include: forming a preliminary layer, in which Ta and F are mixed, on a semiconductor substate by performing an Atomic Layer Deposition (ALD) method; forming a Ta layer by reacting the preliminary layer with... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070166982 - Method of forming a metal layer over a patterned dielectric by wet chemical deposition including an electroless and a powered phase: By performing an electroless deposition and an electro deposition process in situ, highly reliable metallizations may be provided, wherein limitations with respect to contaminations and device scaling, encountered by conventional chemical vapor deposition (CVD), atomic layer deposition (ALD) and physical vapor deposition (PVD) techniques for the formation of seed layers... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070166984 - Method of forming an insulating layer in a semiconductor device: Embodiments relate to semiconductor device and a method of forming an insulating layer with a low dielectric constant in a semiconductor device. The method may include forming a plurality of metal patterns on a semiconductor substrate, depositing a first insulating layer on the entire surface of the semiconductor substrate having... Agent: Sherr & Nourse, PLLC

20070166986 - Semiconductor device and metal line fabrication method of the same: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern... Agent: Sherr & Nourse, PLLC

20070166988 - Aluminum metal line of a semiconductor device and method of fabricating the same: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070166980 - Chemical vapor deposition chamber for depositing titanium silicon nitride films for forming phase change memory devices: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times.... Agent: Seed Intellectual Property Law Group PLLC

20070166979 - Metal etching process and rework method thereof: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the... Agent: Jianq Chyun Intellectual Property Office

20070166987 - Method for forming metal line in a semiconductor device: A method for forming a metal line of a semiconductor device includes forming an interlayer insulation film over a semiconductor substrate, forming a trench for exposing at least a portion of the semiconductor substrate by using a selective etching process, and forming a diffusion barrier layer over the interlayer film... Agent: Sherr & Nourse, PLLC

20070166991 - Methods for forming conductive vias in semiconductor device components: A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of... Agent: Trask Britt, P.C./ Micron Technology

20070166981 - Methods for forming uniform lithographic features: Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the overhang and... Agent: Keusey, Tutunjian & Bitetto, P.C.

20070166978 - Microelectronic interconnect device comprising localised conductive pins: A method producing conductive rods localized on conductive blocks of an electronic component.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070166983 - Small electrode for resistance variable devices: A memory element comprising first and second electrodes is provided. The first electrode is tapered such that a first end of the first electrode is larger than a second end of the first electrode. A resistance variable material layer is located between the first and second electrodes, and the second... Agent: Dickstein Shapiro LLP

20070166989 - Substrate processing including a masking layer: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics... Agent: Intermolecular, Inc. C/o Courtney Staniford & Gregory, LLP

20070166992 - Methods for forming conductive vias in semiconductor device components: The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises... Agent: Scully Scott Murphy & Presser, PC

20070166993 - Method for fabricating circuit component: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a... Agent: Megica Corporation

20070166994 - Prevention and control of intermetallic alloy inclusions that form during reflow of pb free, sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless ni(p) metallization is present: In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of... Agent: The Law Offices Of Robert J. Eichelburg Hodafel Building, Suite 200

20070166995 - Method for direct electroplating of copper onto a non-copper plateable layer: A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein the second barrier layer is selected from... Agent: International Business Machines Corporation Dept. 18g

20070166996 - Method of making a semiconductor structure with a plating enhancement layer: Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and... Agent: International Business Machines Corporation Dept. 18g

20070166997 - Semiconductor devices and methods of manufacture thereof: Vertically stacked integrated circuits and methods of fabrication thereof are disclosed. Deep vias that provide vertical electrical connection for vertically stacked integrated circuits are formed early in the manufacturing process, before integrated circuits are bonded together to form a three dimensional integrated circuit (3D-IC).... Agent: Slater & Matsil LLP

20070166998 - Interconnecting process and method for fabricating complex dielectric barrier alyer: An interconnecting process is described. First, a dielectric layer with a plurality of openings is provided. Then, a metallic layer is formed to fill up the openings. A first dielectric barrier layer is formed to cover the dielectric layer and the metallic layer. Thereafter, a second dielectric barrier layer is... Agent: J C Patents, Inc.

20070166999 - Systems and methods of forming refractory metal nitride layers using disilazanes: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound.... Agent: Mueting, Raasch & Gebhardt, P.A.

20070167000 - Methods and systems for fabricating semiconductor components with through wire interconnects (twi): A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20070167002 - Method and apparatus for dielectric etching during integrated circuit fabrication: A method for multi-step dielectric etching includes discharge steps between each of the etching steps in order to help release accumulated charge on the wafer produced by the previous etching step. The discharge steps stabilize the plasma discharge in each transition between etching steps. Charge elimination occurs because the negative... Agent: Baker & Mckenzie LLP Patent Department

20070167001 - Method of manufacturing a semiconductor device and method of etching an insulating film: During etching of a contact hole, not only the energy of ion irradiation but also the gas composition are altered to change the etching from a high-rate etching to a low-rate etching, thereby reducing the damage. In the low-rate etching where the gas composition is also altered, a firm fluorocarbon... Agent: Foley And Lardner LLP Suite 500

20070167003 - Adhesive film and method for forming metal film using same: The present invention relates to an adhesive film capable of preventing damage to a non-metal-film-formed surface when forming a metal film on a semiconductor wafer and further capable of reducing contamination on the wafer surface. The adhesive film comprises a base film laminated with at least one film layer having... Agent: Buchanan, Ingersoll & Rooney PC

20070167004 - Triaxial through-chip connection: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive,... Agent: Morgan & Finnegan, L.L.P.

20070167005 - Selective electroless-plated copper metallization: Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate to a thickness of less than 15 nanometers... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070167006 - Methods of forming metal layers using oxygen gas as a reaction source and methods of fabricating capacitors using such metal layers: When a metal layer formed by reaction of a metal source and an oxygen (O2) source is deposited, oxidization of a conductive layer disposed under or on the metal layer can be reduced and/or prevented by a method of forming the metal layer and a method of fabricating a capacitor... Agent: Myers Bigel Sibley & Sajovec

20070167007 - Methods for symmetric deposition of a metal layer in the fabrication of a semiconductor device: A method for symmetric deposition of metal layer over a metal layer registration key comprises using MOCVD to form the metal layer. Once the symmetric metal layer is formed, a metal layer registration key can be accurately detected and the metal layer registration key overlay shift can be improved.... Agent: Baker & Mckenzie LLP Patent Department

20070167008 - Nanotip electrode non-volatile memory resistor cell: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070167009 - Method of fabricating nickel silicide: A semiconductor device having nickel suicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the... Agent: North America Intellectual Property Corporation

20070167010 - Semiconductor device and manufacturing method of semiconductor device: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070167011 - Etching method: In an etching method of the present invention, a first etching step for etching a silicon semiconductor region at a first etching rate with use of a first etching gas is first performed. Then, after the first etching step, a second etching step is performed in order to etch the... Agent: Rabin & Berdo, PC

20070167012 - Fabrication method of semiconductor device: An insulating film for forming sidewall insulating films of a gate electrode is deposited on the main surface of a semiconductor wafer and then, subjected to the treatment for equalizing the film thickness distribution. In this treatment, the semiconductor wafer is fixed onto a spin stage of an etching apparatus... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070167013 - Method for performing a cmp process on a wafer formed with a conductive layer: A CMP method for performing a chemical mechanical polishing process wherein an edge of a wafer formed with a conductive layer is uniformly polished is provided. The CMP method includes preparing a wafer, forming a chip pattern in effective dies of the wafer and ineffective dies on edges of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070167014 - Cmp method providing reduced thickness variations: A chemical mechanical polishing (CMP) method is disclosed for use in the fabrication of a semiconductor device having dense and sparse regions. The method uses an abrasive stop layer formed on the dense and sparse regions to control polishing of a material layer formed on the abrasive stop layer by... Agent: Volentine & Whitt PLLC

20070167017 - Materials for polishing liquid for metal, polishing liquid for metal, method for preparation thereof and polishing method using the same: Provided are a metal-polishing liquid that comprises an oxidizing agent, an oxidized-metal etchant, a protective film-forming agent, a dissolution promoter for the protective film-forming agent, and water; a method for producing it; and a polishing method of using it. Also provided are materials for the metal-polishing liquid, which include an... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070167016 - Metal-polishing liquid and chemical-mechanical polishing method using the same: o

20070167015 - Polishing method: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070167018 - Method for planarization: A method of planarizing a dielectric insulating layer including providing a substrate including forming a first dielectric insulating layer having a concave and convex portion on the substrate; forming an organic resinous layer on the first dielectric insulating layer and exposing the convex portion of the first dielectric insulating layer;... Agent: Tung & Associates

20070167019 - Nanoparticles and method for making the same: A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanoparticles and a metal oxide matrix. The nanoparticles are then isolated... Agent: Attn: Thomas B. Haverstock Haverstock & Owens LLP

20070167020 - Method of fabricating semiconductor device: After low dielectric constant films are formed on a wiring, hardmasks are formed on the low dielectric constant films. A resistmask is formed on the hardmasks. Via holes are formed in the low dielectric constant films using the resistmask. Ashing the resistmask is performed. During this process, a protection film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070167021 - Method of manufacturing nitride substrate for semiconductors: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, warp will be a large ±40 μm to ±100 μm. Since with that warp device... Agent: Judge & MurakamiIPAssociates

20070167022 - Method of fabricating vertical probe head: The present invention relates to a method of fabricating a vertical probe head, whereas the vertical probe head is formed by the combination of at least a probe, a bottom guide plate and a top guide plate having at least a hole matching the probe. The probe is fabricated by... Agent: Bruce H. Troxell

20070167023 - Manufacturing method for wiring: In the case in which a film for a resist is formed by spin coating, there is a resist material to be wasted, and the process of edge cleaning is added as required. Further, when a thin film is formed on a substrate using a vacuum apparatus, a special apparatus... Agent: Nixon Peabody, LLP

20070167024 - Corner clipping for field effect devices: A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with... Agent: Innovation Interface, LLC

20070167025 - Etchant and method for fabricating liquid crystal display using the same: Provided are an etchant used for a transparent conductive oxide layer and a method for fabricating a liquid crystal display (LCD) using the etchant. The etchant includes 2-5 wt % sulfuric acid, 0.02-10 wt % hydrogen sulfate of alkali metal, and deionized water as the remainder.... Agent: Macpherson Kwok Chen & Heid LLP

20070167028 - Film formation method and apparatus for semiconductor process: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding gas, and a third process gas containing a carbon hydride gas. This method includes... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070167026 - Production method for semiconductor device: In a production process for a semiconductor device employing an SiC semiconductor substrate (1), the SiC semiconductor substrate (1) is mounted on a susceptor (23), and a C heating member (3) of carbon is placed on a surface of the SiC semiconductor substrate (1). An annealing process is performed to... Agent: Rabin & Berdo, PC

20070167027 - System and method for uniform multi-plane silicon oxide layer formation for optical applications: Methods and systems for growing uniform oxide layers include an example method including growing a first layer of oxide on first and second facets of the substrate, with the first facet having a faster oxide growth rate. The oxide is removed from the first facet and a second oxide layer... Agent: Honeywell International Inc.

20070167030 - Method of forming an insulation structure and method of manufacturing a semiconductor device using the same: In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure... Agent: Harness, Dickey & Pierce, P.L.C

20070167029 - Thermal processing system, components, and methods: Thermal treatment is an important process in the manufacture of integrated circuits. As integrated circuits evolve to become smaller and faster, there is an increasing need to for higher precision thermal treatment systems that can efficiently and uniformly heat these circuits without damaging them. Accordingly, the present inventors devised, among... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070167031 - Semiconductor device and fabrication method of the same: A fabrication method of a semiconductor device includes forming a silicon nitride layer on a compound semiconductor layer with a plasma CVD method and selectively treating the compound semiconductor layer with use of the silicon nitride layer for a mask. The silicon nitride layer has a refraction index of less... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070161126 - Ferroelectric capacitor and method for fabricating the same: In a ferroelectric capacitor comprising: a lower electrode; a ferroelectric film formed on the lower electrode; and an upper electrode formed on the ferroelectric film, the coercive voltage of the ferroelectric film is 1.5 V or less and the polarization switching time of the ferroelectric film is 200 ns or... Agent: Mcdermott Will & Emery LLP

20070161143 - Method of manufacturing a complementary metal oxide silicon image sensor: A method for manufacturing a CMOS image sensor increases the performance of the CMOS image sensor by reducing a peeling phenomenon near a wafer edge and a preventing a circle defect in a pixel region. The method reduces defects in the external appearance of the pad. In order to accomplish... Agent: Sherr & Nourse, PLLC

20070161146 - Method for manufacturing image sensor: A method of manufacturing an image sensor using a microlens mold is provided. The method includes: forming an interlayer dielectric layer on a semiconductor substrate having photodiodes; forming color filter layers on the interlayer dielectric layer; forming a planarization layer on the color filter layers; coating photoresist on the planarization... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070161149 - Method of fabricating organic electronic device: A fabricating method of organic electronic device is provided. The method comprises: providing a flexible substrate; fabricating a plurality of organic elements on the flexible substrate; fabricating a patterned spacing layer on the flexible substrate; and arranging a cover substrate on the patterned spacing layer, and sealing the edges of... Agent: Jianq Chyun Intellectual Property Office

20070161127 - Method for forming mram bit having a bottom sense layer utilizing electroless plating: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer... Agent: Dickstein Shapiro LLP

20070161128 - Semiconductor device manufacturing apparatus and semiconductor device manufacturing method: A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode... Agent: Hayes, Soloway P.C.

20070161129 - Semiconductor device and manufacturing process thereof: One of the aspects of the present invention is to provide a semiconductor device, which includes a circuit board, a first semiconductor chip mounted on the circuit board, a built-in semiconductor package on the first semiconductor chip, and a first molded resin encompassing the first semiconductor chip and the built-in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070161131 - Measurement method for low-k material: Disclosed is a method for measuring a low-k material. A surface of the low-k material is changed into oxide by an oxygen plasma used in an ashing process (e.g., to remove a photoresist film after an etching process). A thickness of the low-k material is measured using an optical measurement... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070161130 - Method for manufacturing semiconductor device, semiconductor inspection device, and program: A manufacturing method of a semiconductor device capable of efficiently inspecting whether a metal silicide layer is sufficiently formed is provided. The manufacturing method is provided with the steps of forming a metal layer over a semiconductor layer containing silicon; forming a metal silicide layer over a surface of the... Agent: Fish & Richardson P.C.

20070161132 - System and method for detection of spatial signature yield loss: A system for identifying systematic yield losses comprises a device configured to test produced products using a test sequence that produces yield data related to a wafer. The wafer is divided into multiple zones. Series of yield data may be collected and stored for each zone. A first data series... Agent: Harness, Dickey, & Pierce, P.l.c

20070161133 - Method for implanting carbon nanotube: The present invention relates to a method of implanting carbon nanotube (CNT), which is especially being adopted for forming CNTs in carbon nanotube field emitting displays (CNT-FEDs). The method comprises steps of: transferring a medium by an electromagnetic wave generating means for forming a media layer of adhesive and conductive... Agent: Bruce H. Troxell

20070161134 - Method of using nanoparticles to fabricate an emitting layer of an optical communication light source on a substrate: A method of using nanoparticles to fabricate an emitting layer of an optical communication light source on a substrate is proposed, in which a host capable of reacting with unstable ions on the surface of a rare earth ions nanomaterial is used as a carrier of nanoparticles to make the... Agent: Rosenberg, Klein & Lee

20070161135 - Method for coating semiconductor device using droplet deposition: Methods and systems for coating of semiconductor devices using droplets of wavelength conversion or phosphor particles in a liquid medium. A plurality of nozzles delivers a controlled amount of the matrix material to the surface of the semiconductor device, with each of said nozzles having an opening for the matrix... Agent: Koppel, Patrick & Heybl

20070161136 - Pixel structure and the fabricating method thereof: A method for fabricating a pixel structure is provided. First, a gate, a scan line, and a first terminal are formed on a substrate. A gate insulating layer is formed over the substrate to cover the gate, the scan line, and the first terminal. After defining the semiconductor layer, the... Agent: Jianq Chyun Intellectual Property Office

20070161137 - Methods of manufacturing light emitting diodes including barrier layers/sublayers: Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070161138 - Method for making an electronic device including a poled superlattice having a net electrical dipole moment: A method for making an electronic device may include forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070161140 - Image sensor and method of manufacturing the same: Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning... Agent: Harness, Dickey & Pierce, P.L.C

20070161139 - Method for singulating a released microelectromechanical system wafer: A plurality of MEMS structures is formed on a wafer. The wafer is mounted on a dicing frame assembly having a dicing frame and a dicing tape attached to the dicing frame. A protective layer is applied to cover the entire surface of the wafer or may be limited to... Agent: Marshall, Gerstein & Borun LLP

20070161141 - Shielding layer outside the pixel regions of optical device and method for making the same: A shielding layer outside a sensing region I of a CMOS image sensor includes a stack of a first monochromatic color filter layer and a second monochromatic color filter layer. Such a two-layered monochromatic color filter acts as a shielding layer, and the amount of black photoresist needed is decreased.... Agent: North America Intellectual Property Corporation

20070161142 - Method and apparatus for providing an integrated circuit having p and n doped gates: A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and nitrogen concentrations and gate electrodes with differing conductivity types and active dopant concentrations.... Agent: Dickstein Shapiro LLP

20070161144 - Method for manufacturing cmos image sensor: Provided is a method for manufacturing a CMOS image sensor. In the method, a mask layer is formed on a semiconductor substrate to define a device isolation region. The semiconductor substrate is selectively removed by wet etching using the mask layer as a mask to form a trench to a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070161145 - Device for subtracting or adding charge in a charge-coupled device: The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across... Agent: Daly, Crowley, Mofford & Durkee, LLP

20070161147 - Method of manufacturing cmos image sensor: Disclosed is a method of manufacturing a CMOS image sensor. The method includes the steps of forming a dielectric layer on a semiconductor substrate having a photodiode therein; forming a color filter array having a plurality of color filters on the dielectric layer; forming a plurality of micro-lenses on the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070161148 - Manufacturing ccds in a conventional cmos process: A technique for forming Charge-Coupled Devices (CCDS) in a conventional Complementary Metal Oxide Semiconductor (CMOS) process. A number of single-layer polysilicon gates are formed on an as-grown, native doped silicon substrate, with gaps between them. Masking is used to selectively dope the gates while preventing doping of the silicon in... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070161150 - Forming ultra dense 3-d interconnect structures: Methods of forming a microelectronic structure are described. Embodiments of those methods include bonding at least one bond pad of a device side of a first substrate to at least one bond pad of a device side of a second substrate, forming at least one via to connect to at... Agent: Intel Corporation C/o Intellevate, LLC

20070161151 - Packaged semiconductor device with dual exposed surfaces and method of manufacturing: The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and... Agent: Hiscock & Barclay, LLP

20070161152 - Method for fabricating semiconductor device and apparatus for fabricating the same: In a semiconductor-device fabrication method, a plurality of recessed portions are first formed in the principal surface of a substrate. Then, a through hole, passing through the substrate in the front-to-back direction of the substrate, is formed under a portion of the bottom of each recessed portion in the substrate.... Agent: Mcdermott Will & Emery LLP

20070161153 - Method for fabricating a flip chip system in package: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first... Agent: Volentine Francos, & Whitt PLLC

20070161154 - Manufacturing method for electronic device: A method of manufacturing an electronic device comprising IC elements 10, on a set of opposite faces of which a first electrode 12 and a second electrode 13 are formed, a first circuit layer 20 where an antenna circuit 21 having a slit 1 is formed, and a second circuit... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070161155 - Wafer level chip scale packaging structure: The present invention provides a Wafer Level Chip Scale Packaging structure including a die, at least one passive component, a combining layer, an isolating layer, at least one connecting wire, an internal pad and a passivation layer. The die includes a shallow connecting pad, an internal pad and an electrical... Agent: John Chen

20070161156 - Semiconductor device and method of manufacturing the same: There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second interconnect insulating film 216 constituted of a ladder-type hydrogen siloxane formed on the semiconductor substrate; a second protection film 217 provided on the second... Agent: Sughrue Mion, PLLC

20070161157 - Semiconductor device package and method for manufacturing same: A lead frame (52, 100, 112) for a semiconductor device (die) package (50, 102, 110) is described. Each of the leads (60) in the lead frame (52, 100, 112) includes an interposer (64) having one end (66) disposed proximate the outer face (58) of the package (50, 102, 110) and... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070161158 - Method for wafer level packaging and fabricating cap structures: A cap wafer with cavities is etched through areas not covered by a patterned photoresist to form a plurality of openings. The cap wafer is bonded to a transparent wafer at the surface having the cavities and is segmented around the cavities to form a plurality of cap structures. The... Agent: North America Intellectual Property Corporation

20070161160 - Structure of thin film transistor array and method for fabricating the same: A substrate having a gate electrode layer, a gate insulating layer, and a silicon layer thereon is provided. These layers are patterned into a gate area, a gate line and a gate line wiring area. A passivation layer is formed on the entire substrate and patterned to form two contact... Agent: Jianq Chyun Intellectual Property Office

20070161162 - Three-dimensional tft nanocrystal memory device: A vertically-stacked three-dimensional nanocrystal memory device and a method for manufacturing the same is proposed. Each of the two vertically overlapping memory cells of the vertically-stacked three-dimensional nanocrystal memory device includes a thin-film transistor and nanocrystals embedded in a gate dielectric layer of the thin-film transistor. With the two vertically... Agent: Birch Stewart Kolasch & Birch

20070161163 - Manufacturing method of thin-film transistor, thin-film transistor sheet, and electric circuit: A thin-film transistor, a thin-film transistor sheet, an electric circuit, and a manufacturing method thereof are disclosed, the method comprising the steps of forming a semiconductor layer by providing a semiconductive material on a substrate, b) forming an insulating area, which is electrode material-repellent, by providing an electrode material-repellent material... Agent: Cantor Colburn, LLP

20070161159 - Method for manufacturing thin film integrated circuit, and element substrate: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In... Agent: Eric Robinson

20070161164 - Method of manufacturing semiconductor device: A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask.... Agent: Fish & Richardson P.C.

20070161161 - Staggered source/drain and thin-channel tft structure and fabrication method thereof: This invention relates to a process for fabricating a staggered source/drain and thin-channel TFT structure, which simplifies the conventional process for fabricating the structure by decreasing the number of mask steps and achieving better results at suppressing the electric field near the drain junction and reducing the leakage current. The... Agent: Bucknam And Archer

20070161166 - Method for manufacturing a semiconductor device: Embodiments relate to a method for manufacturing a semiconductor device that may be capable of obtaining a stable device characteristic by securing an optimal CD of a gate. In embodiments, a method may include forming a gate oxide layer on a semiconductor substrate, forming a photoresist pattern at a first... Agent: Sherr & Nourse, PLLC

20070161165 - Systems and methods involving thin film transistors: Systems and methods for enhancing performance of a hydrogenation treatment are provided. A representative system comprises a thin film transistor (TFT) comprising a substrate, a diffusion barrier layer positioned on the substrate, a pad layer positioned on the diffusion barrier layer, and a polysilicon layer positioned on the pad layer,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070161167 - Fabrication method of display device: Non-uniformity of the sheet resistance associated with ion implantation into a polysilicon semiconductor layer using a ribbon-shaped beam is minimized to prevent variations in the characteristics of fabricated thin film transistors. When the implanted ions are of a first element, a second element that is heavy and has no influence... Agent: Stanley P. Fisher Reed Smith LLP

20070161168 - Method for fabricating a semiconductor device having a multi-bridge-channel: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side... Agent: Lee & Morse, P.C.

20070161169 - Field effect transistors with dielectric source drain halo regions and reduced miller capacitance: A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed... Agent: Cantor Colburn LLP - IBM Fishkill

20070161172 - Method for fabricating a recessed-gate mos transistor device: A method for fabricating a recessed-gate transistor is disclosed. A trench is recessed into a substrate. A poly/nitride spacer is formed on sidewalls of the trench. A trench bottom oxide is formed. The spacer is then stripped off. A source/drain doping region is formed on the exposed sidewalls of the... Agent: North America Intellectual Property Corporation

20070161171 - Process for forming an electronic device including a fin-type structure: A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can... Agent: Larson Newman Abel Polansky & White, LLP

20070161173 - Process to integrate fabrication of bipolar devices into a cmos process flow: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the... Agent: Mendelsohn & Associates, P.C.

20070161170 - Transistor with immersed contacts and methods of forming thereof: A method includes forming a semiconductor structure, the semiconductor structure includes a first current electrode region, a second current electrode region, and a channel region, the channel region is located between the first current electrode region and the second current electrode region, wherein the channel region is located in a... Agent: Freescale Semiconductor, Inc. Law Department

20070161174 - Manufacturing of memory array and periphery: Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over... Agent: Slater & Matsil, L.L.P.

20070161175 - Method for forming a gate insulating layer of a semiconductor device: Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing... Agent: Sherr & Nourse, PLLC

20070161176 - Method for producing a planar spacer, an associated bipolar transistor and an associated bicmos circuit arrangement: Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement. The invention relates to a method for production of a planar spacer, of an associated bipolar transistor and of an associated BiCMOS circuit arrangement, in which first and second spacer layers are formed after... Agent: Brinks Hofer Gilson & Lione

20070161177 - Semiconductor device having increased capacitance of capacitor for data storage and method of manufacturing semiconductor device: A semiconductor device of the present invention comprises a memory cell area having memory cells arranged in an array form, each of which includes a capacitor for storing data and a peripheral circuit area for accessing the memory cell area. The peripheral circuit area is provided with a plurality of... Agent: Mcginn Intellectual Property Law Group, PLLC

20070161181 - Capacitorless dram with cylindrical auxiliary gate and fabrication method thereof: Provided are a capacitorless DRAM (dynamic random access memory) and a fabrication method thereof. In a capacitorless DRAM, a pair of cylindrical auxiliary gates is formed within a bulk substrate. Thus, a volume of a channel body formed at a region where the cylindrical auxiliary gates contact with each other... Agent: Mills & Onello LLP

20070161180 - Automatic layer deposition process: The atomic layer deposition process according to the invention provides the following steps for the production of homogeneous layers on a substrate. The substrate is introduced into a reaction chamber. A first precursor is introduced into the reaction chamber, which first precursor reacts on the surface of the substrate to... Agent: Morrison & Foerster LLP

20070161178 - Cylindrical capacitor and method of fabricating the same: A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds... Agent: Jianq Chyun Intellectual Property Office

20070161179 - Semiconductor device and method for making the same: A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and... Agent: Quintero Law Office, PC

20070161183 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a plurality of bit line patterns, each bit line pattern having a double-layer hard mask including a nitride-based layer and an amorphous carbon-based layer, forming a planarized insulation layer filled between the bit line patterns, the planarized insulation layer flush with... Agent: Blakely Sokoloff Taylor & Zafman

20070161182 - Method for fabricating storage node contact hole of semiconductor device: A method for fabricating a storage node contact hole of a semiconductor device includes: forming an inter-layer insulation layer over a substrate; forming a hard mask over the inter-layer insulation layer; etching the inter-layer insulation layer to form a storage node contact hole; forming a passivation layer to fill the... Agent: Blakely Sokoloff Taylor & Zafman

20070161184 - Liquid crystal display array board and method of fabricating the same: A liquid crystal display array board includes a plurality of gate wiring lines formed on a substrate and a plurality of data wiring lines crossing the plurality of gate wiring lines, a plurality of thin film transistors formed in areas defined by crossings of the gate wiring lines and the... Agent: Christie, Parker & Hale, LLP

20070161187 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacture process of high-integrated semiconductor devices. It... Agent: Marshall, Gerstein & Borun LLP

20070161188 - Method of manufacturing nonvolatile semiconductor memory device: A method of manufacturing a nonvolatile semiconductor memory device includes the steps of preparing a wafer having multiple memory cells, each memory cell having a gate electrode formed on a semiconductor substrate, charge storage units formed on both sides of the gate electrode, lightly doped regions formed beneath the charge... Agent: GlobalIPCounselors, LLP

20070161190 - Split-gate-type nonvolatile memory device and method of fabricating the same: Provided are a split-gate-type nonvolatile memory device and method of fabricating the same. The method includes forming isolation patterns defining active regions in a predetermined region of a semiconductor substrate. A first conductive layer is formed on the resultant structure having the isolation patterns. The first conductive layer has openings... Agent: Mills & Onello LLP

20070161189 - Method of fabricating the floating gate of flash memory device: There is provided a method of forming a floating gate of a flash memory device, including forming a tunnel insulating layer over a semiconductor substrate; forming a floating gate conductive layer over the tunnel insulating layer; forming a hard mask layer pattern over the floating gate conductive layer; forming a... Agent: Sherr & Nourse, PLLC

20070161185 - Method of manufacturing charge storage device: A method of manufacturing a charge storage device is provided. Utilizing the capacity for a precise control of the thickness and the silicon content of a deposited film in an atomic layer deposition process, a stacked gradual material layer such as a hafnium silicon oxide (HfxSiyOz) layer is formed. The... Agent: J.c. Patents, Inc.

20070161186 - Programmable resistive ram and manufacturing method: Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the programmable resistive elements from previous fabrication steps.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070161191 - Scalable self-aligned dual floating gate memory cell array and methods of forming the array: An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070161192 - Method of fabricating non-volatile memory structure: A substrate having a first dielectric layer, a first conductive layer and a second dielectric layer thereon is provided. A part of the second dielectric layer is removed to form a first opening having both ends with a select gate region respectively. The select gate region is constituted by a... Agent: Jianq Chyun Intellectual Property Office

20070161193 - Systems and methods for a high density, compact memory array: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to... Agent: Baker & Mckenzie LLP Patent Department

20070161194 - Method of measuring an effective channel length and an overlap length in a metal-oxide semiconductor field effect transistor: In a method of measuring an effective channel length and an overlap length, first to third metal-oxide semiconductor field effect transistors (MOSFETs) including first to third gate patterns, respectively, are formed on a substrate. A parasitic capacitance between the gate patterns and the substrate in the MOSFETs is determined based... Agent: Mills & Onello LLP

20070161196 - Methods for preserving strained semiconductor substrate layers during cmos processing: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad... Agent: Goodwin Procter LLP Patent Administrator

20070161195 - Structure and method for a sidewall sonos memory device: A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to... Agent: Slater & Matsil, L.L.P.

20070161197 - Method of manufacturing semiconductor device: A junction leak current of a transistor including a silicide layer provided on a source/drain region is to be suppressed. After forming a gate electrode over a chip-side surface of a silicon substrate, an insulating layer is formed over the gate electrode. The insulating layer is etched back so as... Agent: Mcginn Intellectual Property Law Group, PLLC

20070161198 - Transistors with gate stacks having metal electrodes: A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of... Agent: Schmeiser, Olsen & Watts

20070161199 - Method for manufacturing soi wafer: A method for manufacturing SOI wafers is provided which allows the obtaining of a thin SOI layer having uniform in-plane thickness. In this manufacturing method, an oxygen ion implanted layer is first formed on an active layer wafer. This is then laminated to a base wafer with a embedded oxide... Agent: Kolisch Hartwell, P.C.

20070161200 - Method for fabricating capacitor in semiconductor device: A method for fabricating a capacitor in a semiconductor device includes forming a first insulation layer over a substrate, forming storage node contact plugs in the first insulation layer, contacting predetermined portions of the substrate, forming a second insulation layer over the first insulation layer and the storage node contact... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070161201 - Liquid spraying method, liquid spraying system and liquid spraying execute program: A semiconductor device is provided which has a capacitor insulating film made up of zirconium aliminate being an amorphous film obtained by having crystalline dielectric contain amorphous aluminum oxide and having its composition of AlXZr(1−X)OY (0.05≦X≦0.3), hereby being capable of preventing, in a process of forming a capacitor of MIM... Agent: Sughrue Mion, PLLC

20070161202 - Methods of forming a plurality of capacitors: The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor electrode openings are bounded on a first pair of opposing sides by a first capacitor electrode-forming material at one elevation and on... Agent: Wells St. John P.s.

20070161203 - Method with high gapfill capability and resulting device structure: A method for filling a trench includes forming a first layer in a trench in order to partially fill the trench, removing at least a potion of the first layer from the trench; and forming a second layer on the first layer, wherein the forming a second layer is performed... Agent: Townsend And Townsend And Crew, LLP

20070161204 - Methods for metal arc layer formation: A process for forming an ARC layer in the fabrication of a semiconductor device comprises forming a modified ARC layer that increases the resistance to crown defects and bridging and also provides better adhesion for the ARC layer with the underlying metal layer. The modified ARC layer can comprise two... Agent: Baker & Mckenzie LLP Patent Department

20070161205 - Electrical device and method for fabricating the same: A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top... Agent: North America Intellectual Property Corporation

20070161206 - Isolation structure for strained channel transistors: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the... Agent: Duane Morris, LLPIPDepartment

20070161207 - Method for manufacturing semiconductor device: Provided is a method for manufacturing a semiconductor device. The method includes: sequentially depositing a buried oxide layer, an insulating layer, a pad oxide layer and a pad nitride layer on a silicon substrate; etching a predetermined region of the silicon substrate using a photoresist pattern as an etch mask... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070161208 - Semiconductor device and fabrication method thereof: To prevent cracks in an insulator buried in a trench and fill the insulator completely in a place to be filled up. A process comprises: forming a trench 1a extending to an embedded insulation film 3 at a determined position on a first silicon substrate 1 of an SOI substrate... Agent: Sughrue Mion, PLLC

20070161211 - Method for manufacturing semiconductor device: A disclosed method for manufacturing a semiconductor device having a structure where a semiconductor element is mounted on a first substrate includes the steps of: bonding the first substrate on which the semiconductor element is mounted and a second substrate made of a material different from a material of the... Agent: Ladas & Parry LLP

20070161209 - Method for producing a strong bond between two layers of a multilayer system, and multilayer system: In a multilayer system, for example a sensor, in order to bond together strongly two layers (2, 6) that adhere together only to a degree without restricting the functionality of the multilayer system, an intermediate layer (1), preferably a dielectric that does not impair the functionality but does adhere well,... Agent: O'shea, Getz & Kosakowski, P.C.

20070161210 - Method for wafer level packaging and fabricating cap structures: A cap wafer with patterned film formed thereon is etched through areas not covered by the patterned film to form a plurality of openings. Then, the cap wafer is bonded to a transparent wafer, and the cap wafer around the pattern film is segmented to form a plurality of cap... Agent: North America Intellectual Property Corporation

20070161212 - Method for manufacturing mosfet on semiconductor device: A method for manufacturing a semiconductor device having a fuse area and a pad area. An inter-layer dielectric layer is deposited over a semiconductor substrate having a metal interconnection. A protection layer is deposited over the inter-layer dielectric layer. A photoresist mask is used to define areas to be etched... Agent: Sherr & Nourse, PLLC

20070161213 - Semiconductor device and method of manufacturing the same: A self-aligned/self-limited processing is carried out on a nanowire material typified by a carbon nanotube or on the vicinity of the nanowire material alone in the following manner. External energy is applied to the nanowire material. Joule heat, light, or a thermoelectron is thereby locally formed and acts as minute... Agent: Young & Thompson

20070161214 - High k gate stack on iii-v compound semiconductors: A method of forming a high k gate stack (dielectric constant of greater than that of silicon dioxide) on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface... Agent: Scully Scott Murphy & Presser, PC

20070161215 - External storage and data recovery method for external storage as well as program: The data is automatically recovered to a desired arbitrary point in an external storage without imposing a burden on the host computer. An application on a host computer instructs data recovery control processing of a disk control apparatus to set a recovery opportunity. It is possible to register arbitrary plural... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070161216 - Epitaxial deposition of doped semiconductor materials: A method for depositing a carbon doped epitaxial semiconductor layer comprises maintaining a pressure of greater than about 700 torr in a process chamber housing a patterned substrate having exposed single crystal material. The method further comprises providing a flow of a silicon source gas to the process chamber. The... Agent: Knobbe Martens Olson & Bear LLP

20070161217 - Process for manufacturing a large-scale integration mos device and corresponding mos device: A process for manufacturing a MOS device and the MOS device manufactured thereby are disclosed. The process includes in a semiconductor layer forming a gate structure above the semiconductor layer; forming a first doped region within a first surface portion of the semiconductor layer; and irradiating the first doped region... Agent: Graybeal, Jackson, Haley LLP

20070161218 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070161219 - Method of producing a semiconductor element and semiconductor element: In a method for fabricating a semiconductor element in a substrate, micro-cavities are formed in the substrate. Furthermore, doping atoms are implanted into the substrate, whereby crystal defects are produced in the substrate. The substrate is heated, so that at least some of the crystal defects are eliminated using the... Agent: Dickstein Shapiro LLP

20070161220 - Semiconductor device with mushroom electrode and manufacture method thereof: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070161221 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask as well as... Agent: Townsend And Townsend And Crew, LLP

20070161222 - Method of forming pad of semiconductor device: A method of manufacturing a pad of a semiconductor device. A method may include at least one of the following steps: sequentially depositing a metal layer and an interlayer dielectric layer over a semiconductor substrate; forming a plurality of via holes that expose a metal layer through an interlayer dielectric... Agent: Sherr & Nourse, PLLC

20070161223 - Conductive structures for electrically conductive pads of circuit board and fabrication method thereof: Conductive structures for electrically conductive pads of a circuit board and fabrication method thereof are proposed. The fabrication method includes: providing a circuit board with a plurality of first, second and third electrically conductive pads; forming first and second conductive layers on the circuit board; forming first and second resist... Agent: Sawyer Law Group LLP

20070161224 - Semiconductor module and method of forming a semiconductor module: In one embodiment, a semiconductor module includes at least one semiconductor chip package, a board having functional pads and dummy pads, and at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the board. Furthermore, at least one supporting solder bump is... Agent: Harness, Dickey & Pierce, P.L.C

20070161225 - Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region... Agent: Williams, Morgan & Amerson

20070161226 - Dual damascene process flow enabling minimal ulk film modification and enhanced stack integrity: Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the... Agent: Scully Scott Murphy & Presser, PC

20070161227 - Self-encapsulated silver alloys for interconnects: Alloys of silver and an alloying element that diffuses to the surface of the high conductivity metal and is oxidizable to form an alloying element oxide such as beryllium are provided along with electronic structures employing the alloys and methods of fabrication.... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20070161228 - Wiring substrate and semiconductor device, and method of manufacturing wiring substrate: A wiring substrate (1) comprises an insulating base (10) with connection holes (11), buried conductors (12) provided in the connection holes (11) without reaching a rear surface of the insulating base (10), and wiring layers 14 connected to the buried conductors (12). The buried conductors (12) thicken the wiring layers... Agent: Greenblum & Bernstein, P.L.C

20070161229 - Dual plasma treatment barrier film to reduce low-k damage: A method is provided for creating a barrier layer (217) on a substrate comprising a dielectric layer (203) and a metal interconnect (211). In accordance with the method, the substrate is treated with a first plasma comprising helium, thereby forming a treated substrate. The treated substrate is then exposed to... Agent: Fortkort & Houston P.C.

20070161231 - Method for forming metal wiring in a semiconductor device: Provided is a method for forming a metal wiring through a damascene process in a semiconductor device. The method includes: forming a metal diffusion barrier on a semiconductor substrate having a via hole and a trench therein; depositing a metal on the metal diffusion barrier, and filling the via hole... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070161230 - Uv curing of low-k porous dielectrics: A method of manufacturing a semiconductor device having a low-k dielectric layer is provided. An embodiment comprises forming a dielectric layer on a substrate, wherein the layer comprises a pore generating material dispersed in an uncured matrix. A second step comprises forming pores in the uncured matrix by irradiating the... Agent: Slater & Matsil, L.L.P.

20070161232 - Method for forming metal interconnection in semicondutor damascene process: A method for forming metal interconnections in a semiconductor damascene process, in which a selective deposition of an etch stop layer formed above a lower metal interconnection by the damascene process prevents an etch attack against the lower metal interconnection. The method includes forming a first conductive layer over a... Agent: Sherr & Nourse, PLLC

20070161233 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a titanium layer, a first titanium nitride layer, a second titanium nitride layer, and a via plug. The substrate includes an interlayer insulating layer formed thereon. The interlayer insulating layer can... Agent: Jeff Lloyd Saliwanchik, Lloyd & Saliwanchik

20070161234 - Methods of forming back side layers for thinned wafers and related structures: A method of processing a wafer including a plurality of integrated circuit devices on a front side of the wafer, may include thinning the wafer from a back side opposite the front side. After thinning the wafer, a back side layer may be provided on the back side of the... Agent: Myers Bigel Sibley & Sajovec

20070161235 - Back-to-front via process: A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a... Agent: Morgan & Finnegan, L.L.P.

20070161236 - Semiconductor device and process for producing the same: A semiconductor device and a process for producing the same, the semiconductor device comprising two conductive layers provided as separate layers, and an insulating layer sandwiched by the two conductive layers, in which the two conductive layers are electrically connected to each other with an embedded conductive layer or an... Agent: Eric Robinson

20070161238 - Method of microminiaturizing a nano-structure: The present invention provides a “microminiaturizing method of nano-structure” with fabricating process steps as follows: First deposit the material of molecule or atom state on the top-opening of the nano cylindrical pore, which having formed on the substrate, so that the diameter of said top-opening gradually reduce to become a... Agent: Bacon & Thomas, PLLC

20070161237 - Nanoscopic wired-based devices and arrays: Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used... Agent: Wolf Greenfield & Sacks, P.C.

20070161239 - Structure for optimizing fill in semiconductor features deposited by electroplating: A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20070161240 - Air break for improved silicide formation with composite caps: Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070161241 - Method for fabricating a thin film and metal line of semiconductor device: A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate, and converting a portion of the TaN film into a Ta film by reacting the TaN film with NO2. The Ta film is formed to have... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070161242 - Semiconductor device having copper wiring: A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of copper or alloy mainly consisting of copper is filled in the via hole. A second interlayer insulating film made... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070161244 - Method and apparatus for post silicide spacer removal: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070161243 - Aqueous solution for removing post-etch residue: The present invention relates to a novel solution for the removal of post-etch residues having improved properties and to the use thereof in the production of semiconductors. The invention relates, in particular, to an aqueous solution having a reduced etching rate on metallisations and on surfaces which have to be... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070161247 - Etching method of single wafer: Local shape collapse of a wafer end portion is suppressed to the minimum level, and a wafer front surface as well as a wafer end portion is uniformly etched while preventing an etchant from flowing to a wafer rear surface. There is provided an etching method of a single wafer... Agent: Reed Smith, LLP Attn: Patent Records Department

20070161249 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the steps of forming a gate electrode on a semiconductor substrate, forming a drift area in the semiconductor substrate by implanting a dopant using the gate electrode as a mask, forming a sidewall... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070161248 - Process for removing material from substrates: A method of removing materials, and preferably photoresist, from a substrate comprises dispensing a liquid sulfuric acid composition comprising sulfuric acid and/or its desiccating species and precursors and having a water/sulfuiric acid molar ratio of no greater than 5:1 onto an material coated substrate in an amount effective to substantially... Agent: Kagan Binder, PLLC

20070161246 - Process for selectively removing dielectric material in the presence of metal silicide: A method for removing dielectric material 50 from a semiconductor wafer 20 that contains metal silicide 60 or 90. The method includes performing a selective etch 202 of the semiconductor wafer 20 using an organic semi-aqueous solvent-based etchant until the dielectric material 50 is substantially removed and then rinsing 204... Agent: Texas Instruments Incorporated

20070161245 - Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch using a two-print-two-etch approach: In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can comprise forming a first layer over a semiconductor substrate, forming a first mask layer over the semiconductor substrate, and using the first mask layer to... Agent: Texas Instruments Incorporated

20070161250 - Method for electrochemically mechanically polishing a conductive material on a substrate: Aspects of the present invention include a method and an apparatus that may be utilized to reduce dishing and improve cleaning efficiency of a material layer residue (e.g., copper residual) by varying a substrate potential in a substrate processing system. For example, by utilizing multiple polishing steps and applying different... Agent: Patterson & Sheridan, LLP

20070161251 - Pitch reduced patterns relative to photolithography features: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the... Agent: Knobbe Martens Olson & Bear LLP

20070161252 - Method of manufacturing flash memory and flash memory manufactured from the method: Method of manufacturing flash memories comprise forming a floating gate, a control gate, and a dielectric layer in the same etching apparatus. In some embodiments, Cl2, Ar, HBr, HeO2, He, CF4, and CHF3 gases are used for etching and forming layers. The flash memories manufactured from the method are disclosed.... Agent: Mayer, Brown, Rowe & Maw LLP

20070161253 - Method of fabricating a trench isolation layer in a semiconductor device: A method of fabricating a trench isolation layer in a semiconductor device. A method of fabricating a trench isolation layer in a semiconductor device, which may remove particles (e.g. in the form of an oxide layer) that are formed during a moat wet etch process.... Agent: Sherr & Nourse, PLLC

20070161255 - Method for etching with hardmask: Methods are provided for processing a substrate by depositing a hardmask material on a surface of the substrate, depositing an anti-reflective coating on the hardmask material, depositing a resist material on the anti-reflective coating, patterning the resist material to form a first resist features having a first width to expose... Agent: Patterson & Sheridan, LLP

20070161254 - Method of forming a passivation layer of a semiconductor device: Lowering the temperature at which an oxide layer is formed produces a passivation layer with improved adhesion characteristics and crack resistance. The method of forming the passivation layer includes first forming an intermetal dielectric layer over a lower metal layer of a semiconductor device. A via is formed in the... Agent: Sherr & Nourse, PLLC

20070161257 - Method for forming porous insulation film: A method of forming a porous film on a processing target includes: forming fine organic particles by polymerizing an organic compound in a gaseous phase; mixing the fine organic particles with a silicon compound containing a Si—O bond in a gaseous phase, thereby depositing a film containing the fine particles... Agent: Knobbe Martens Olson & Bear LLP

20070161256 - Sicoh film preparation using precursors with built-in porogen functionality: A method of fabricating a dielectric material that has an ultra low dielectric constant (or ultra low k) using at least one organosilicon precursor is described. The organosilicon precursor employed in the present invention includes a molecule containing both an Si—O structure and a sacrificial organic group, as a leaving... Agent: Scully Scott Murphy & Presser, PC

20070161258 - Method of fabricating a semiconductor device having a hydrogen source layer: In an embodiment, a method of fabricating a semiconductor device having a hydrogen source layer includes forming an interlayer insulating layer on a semiconductor substrate. A hydrogen source layer is formed on the substrate having the interlayer insulating layer. A thermal annealing process is performed on the substrate having the... Agent: Marger Johnson & Mccollom, P.C.

20070161259 - Two dimensional nanostructure fabrication method and two dimensional nanostructure fabricated therefrom: Disclosed herein is a method of fabricating a two dimensional (2D) nanostructure. The method includes heating a substrate within a vacuum chamber, injecting a metallic material into the vacuum chamber, adsorbing the metallic material on a surface of the substrate, and cooling the substrate to fabricate the 2D nanostructure on... Agent: Cantor Colburn, LLP

20070161260 - Methods of forming a phosphorus doped silicon dioxide-comprising layer: This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. First and second... Agent: Wells St. John P.s.

20070161261 - Methods for fabricating carbon nano-tube powders and field emission display devices: Methods for fabricating carbon nano-tube (CNT) powders and field emission display devices. Carbon nano-tube powders are deposited and gathered in a vacuum chamber. A physical surface treatment is performed on the carbon nano-tube powders. The carbon nano-tube powders are mixed into a paste and screen printed on a substrate, wherein... Agent: Quintero Law Office, PC

20070155028 - Semiconductor process evaluation methods including variable ion implanting conditions: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.... Agent: Myers Bigel Sibley & Sajovec

20070155034 - Method for manufacturing a bottom substrate of a liquid crystal display device: A method for manufacturing a bottom substrate of a liquid crystal display device by using only three masks is disclosed. The method includes the following steps. First, a patterned first metal layer, an insulating layer, a semiconductor layer and a second metal layer are formed subsequently on a substrate. Afterwards,... Agent: Bacon & Thomas, PLLC

20070155036 - Method for manufacturing cmos image sensor: A method for manufacturing a CMOS image sensor capable of improving a low illumination characteristic is provided. The method includes: forming a photodiode and a gate poly of a transfer transistor on a semiconductor substrate; depositing a spacer material on the semiconductor substrate including the photodiode and the gate poly... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070155037 - Reference ph sensor, preparation and application thereof: A reference pH sensor, the preparation and application thereof. The reference pH sensor is an extended gate field effect transistor (EGFET) structure and comprises a metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor substrate, a sensing unit comprising a substrate, a solid-state conductive sensing layer on the substrate,... Agent: Quintero Law Office, PC

20070155039 - Method for manufacturing cmos image sensor: A method for manufacturing a CIS reduces or prevents dark current in a photodiode region. In the method, a plurality of gates are formed on a semiconductor substrate, and impurities are implanted in side portions of a predetermined gate to form a photodiode region. Subsequently, a spacer nitride layer is... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070155038 - Method of manufacturing complementary metal oxide semiconductor image sensor: A method of manufacturing a complementary metal oxide semiconductor (CMOS) image sensor is provided. The method can include the steps of: providing a semiconductor substrate having an active region and an isolation region defined thereon; forming a photodiode at a photodiode area of the active region; forming first and second... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070155044 - Method for manufacturing cmos image sensor: A method for manufacturing CMOS image sensor is provided. The method includes: forming an interlayer dielectric on a semiconductor substrate on which a plurality of photodiodes are formed; forming a plurality of color filters at regular intervals on the interlayer dielectric; forming a planarization layer on an entire surface of... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070155027 - Dry etch stop process for eliminating electrical shorting in mram device structures: The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.... Agent: Tue Nguyen

20070155026 - Method for manufacturing a semiconductor device, method for manufacturing magnetic memory, and the magnetic memory thereof: A method for manufacturing a semiconductor device is provided. First, a first metal conductive line is formed, and then a semiconductor device is formed on the first metal conductive line. A dielectric layer is formed on the semiconductor device. A contact window is formed at a position in the dielectric... Agent: Rabin & Berdo, PC

20070155025 - Nanowire structures and devices for use in large-area electronics and methods of making the same: A nanowire structure and device for use in large area electronics and methods of making the same is provided. The nanowire structure includes a nanowire defining an axis, where the nanowire includes a first end and a second end. The first end is axially spaced from the second end. Further,... Agent: General Electric Company Global Research

20070155029 - Methods for processing semiconductor devices in a singulated form: Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to enable testing... Agent: Trask Britt, P.C./ Micron Technology

20070155030 - Method for making red-light emitting diode having silicon quantum dots: The present invention provides a method for making a light emitting diode (LED) through a silica film growth, an annealing treatment and a surface treatment so that the LED whose spectrum covers the whole red-light zone of a white-light spectrum is obtained with stability, economy, environmental protection and high efficiency.... Agent: Troxell Law Office PLLC Suite 1404

20070155031 - Method for producing semiconductor optical device: The present invention is to provide a method for manufacturing a semiconductor optical device, in which the unevenness of the burying of the mesa structure may be reduced. The process is configured to form a mask extending along [011] direction on the cap layer, to form a mesa structure by... Agent: Smith, Gambrell & Russell

20070155032 - Method of fabricating vertical structure nitrede semiconductor light emitting device: A method of fabricating a vertical structure nitride semiconductor light emitting device having a cross-sectional shape of a polygon having five or more sides or a circle. A light emitting structure is formed on a sapphire substrate. A metal layer having a plurality of patterns is formed on the light... Agent: Mcdermott Will & Emery LLP

20070155033 - Method of manufacturing light emitting diode package: A method of manufacturing an LED package. The method includes dispensing a transparent resilient resin on an LED package body and overturning an entire structure to form an LED lens integrally provided to the LED package body. This prevents extra processes and costs incurring from forming intermediate layers and obviates... Agent: Mcdermott Will & Emery LLP

20070155035 - Method of fabricating a thin film transistor and manufacturing equipment: A method of forming a thin film transistor includes forming a gate electrode on a substrate, forming an organic layer over the substrate having the gate electrode, curing the organic layer in a first chamber, transferring the substrate having the organic layer from the first chamber to a second chamber... Agent: Mckenna Long & Aldridge LLP

20070155040 - Photodiode with self-aligned implants for high quantum efficiency and method of formation: A pinned photodiode with a pinned surface layer formed by a self-aligned angled implant is disclosed. The angle of the implant may be tailored to provide an adequate offset between the pinned surface layer and an electrically active area of a transfer gate of the pixel sensor cell. The pinned... Agent: Dickstein Shapiro LLP

20070155041 - Method for manufacturing cmos image sensor: Disclosed is a method for manufacturing a CMOS image sensor, capable of preventing dopants implanted with high energy from penetrating into a lower part of a gate electrode when a photodiode is formed, thereby preventing current leakage of a transistor and variation of a threshold voltage. The method includes the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070155042 - Solid-state imaging device, production method and drive method thereof, and camera: A solid-state imaging device capable of reducing an eclipse (blocking) of an incident light at a circumferential portion of a light receiving portion and realizing a larger angle of view and high-speed driving. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20070155043 - Photoelectric conversion apparatus, producing method therefor, image pickup module and image pickup system: A photoelectric conversion apparatus has a plurality of photoelectric conversion elements arranged on a semiconductor substrate, a plurality of wiring layers arranged on the semiconductor substrate through the first and second insulation layers, and a high refractive index region which is arranged in an opening part that is arranged in... Agent: Fitzpatrick Cella Harper & Scinto

20070155045 - Method of fabricating thin film transistor including organic semiconductor layer and substrate including the same: Disclosed is a display device including a thin film transistor. A method for forming the display device includes forming an organic semiconductor pattern in the presence of a magnetic field or an electric field. Due to the presence of a magnetic field or an electric field, the molecules of the... Agent: Mckenna Long & Aldridge LLP

20070155049 - Method for manufacturing chip package structures: A wafer-level method for manufacturing a chip package structure is disclosed. A wafer comprises a first surface and a second surface opposite thereto. The first surface has chip units disposed thereon to define scribe lines. An adhesive material is disposed between the first surface and the transparent glass for adhering... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070155050 - Electronic device and method of manufacturing the same, circuit board, and electronic instrument: An electronic device includes: a substrate on which an interconnect pattern is formed; a chip component having a first surface on which an electrode is formed and a second surface opposite to the first surface, the chip component being mounted in such a manner that the second surface faces the... Agent: Oliff & Berridge, PLC

20070155046 - Leadframe based flash memory cards: A leadframe design and methods for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting... Agent: Vierra Magen/sandisk Corporation

20070155048 - Methods for packaging microelectronic devices and microelectronic devices formed using such methods: Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is directed toward a method for packaging a microelectronic device that includes coupling an active side of a microelectronic die to a surface of a support member. The microelectronic die... Agent: Perkins Coie LLP Patent-sea

20070155047 - Wafer-level processing of chip-packaging compositions including bis-maleimides: A process of packaging a microelectronic chip includes wafer-level application of a chip-packaging composition that includes a polymer of a bis-maleimide. A process includes wafer-level addition of the chip-packaging compositions that include adding particulate fillers to achieve a coefficient of thermal expansion of about 20 ppm/K. A computing system is... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070155051 - Method of creating mems device cavities by a non-etching process: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming... Agent: Knobbe Martens Olson & Bear LLP

20070155052 - Method of fabricating a semiconductor integrated circuit that includes patterning a semiconductor substrate with a first photomask that uses metal for blocking light and patterning the same substrate with a second photomask that uses organic resin for blo: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.... Agent: Reed Smith LLP

20070155053 - Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages: A semiconductor multi-package module having a second package stacked over a lower ball grid array first package, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing... Agent: Haynes Beffel & Wolfeld LLP

20070155055 - Method of dicing wafer and die: Provided are a method of dicing a wafer, which reduces sectional cracking and chipping, and a die. According to the method, a DAF (die attach film) may be attached on a grinded backside of a wafer, and the DAF and the backside of the wafer may be sawed to a... Agent: Harness, Dickey & Pierce, P.L.C

20070155054 - Wafer-level chip package process: A wafer-level chip package process is provided. First, a transparent substrate having a chip sealing layer and a transparent layer is provided. Then, the chip sealing layer is cut to form a first groove of a predetermined depth, and an adhesive is formed on the chip sealing layer. Next, a... Agent: J C Patents, Inc.

20070155056 - Silicon direct bonding method: A silicon direct bonding (SDB) method by which void formation caused by gases is suppressed. The SDB method includes: preparing two silicon substrates having corresponding bonding surfaces; forming trenches having a predetermined depth in at least one bonding surface of the two silicon substrates; forming gas discharge outlets connected to... Agent: Stanzione & Kim, LLP

20070155057 - Thermally enhanced coreless thin substrate with embedded chip and method for manufacturing the same: A thermally enhanced coreless thin substrate with embedded chips, which mainly includes a patterned carrier metal layer, at least one chip, at least one dielectric layer and at least one wiring layer, is disclosed. The chip is attached to a heat sink portion of the patterned carrier metal layer. The... Agent: Jianq Chyun Intellectual Property Office

20070155058 - Clipless and wireless semiconductor die package and method for making the same: A method for making a semiconductor die package is disclosed. In some embodiments, the method includes using a leadframe structure including at least one lead structure having a lead surface. A semiconductor die having a first surface and a second surface is attached to the leadframe structure. The first surface... Agent: Townsend And Townsend And Crew, LLP

20070155060 - Method for manufacturing high-frequency module device: This invention is a method for manufacturing a high-frequency module device. A high-frequency circuit unit (2) in which first to third unit wiring layers (5) to (7), each having a capacitor (12) or the like at a part, are stacked and formed on flattened one surface of a dummy board... Agent: Robert J. Depke Lewis T. Steadman

20070155059 - Package warpage control: A method of packaging includes placing a restrainer on a package during processing. The method includes clipping the restrainer in place and then exposing the package to high temperatures. After processing the restrainer is removed. An alternative process attaches a component die to a substrate having a cavity in a... Agent: Marger Johnson & Mccollom, P.C.

20070155061 - Method and device for producing layout patterns of a semiconductor device having an even wafer surface: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element... Agent: Mcginn Intellectual Property Law Group, PLLC

20070155062 - Method and apparatus for controlling a circuit with a high voltage sense device: A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of... Agent: Blakely Sokoloff Taylor & Zafman

20070155064 - Method for manufacturing carbon nano-tube fet: A method for manufacturing a carbon nano-tube field-effect transistor (CNT-FET), comprising steps of: forming a patterned conductive layer on a substrate; forming a dielectric layer covering the conductive layer and the substrate; forming a carbon nano-tube layer between a pair of electrodes on the dielectric layer; and performing a treatment... Agent: Birch Stewart Kolasch & Birch

20070155063 - Tensile strained nmos transistor using group iii-n source/drain regions: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.... Agent: Blakely Sokoloff Taylor & Zafman

20070155068 - Method for fabricating thin film transistor substrate: This invention provides method for fabricating a thin film transistor substrate that is adaptive for forming a good pattern design and also removing a stepped difference using a three-mask process.... Agent: Mckenna Long & Aldridge LLP

20070155067 - Method of fabricating polycrystalline silicon film and method of fabricating thin film transistor using the same: Disclosed herein are methods of fabricating a polycrystalline silicon film and methods of fabricating a thin film transistor (TFT) using the same. The method of fabricating a polycrystalline silicon film includes forming an electrically insulating thermally conductive layer using a material selected from the group consisting of aluminum-containing ceramics, cobalt-containing... Agent: Cantor Colburn, LLP

20070155066 - Hemi-spherical structure and method for fabricating the same: Hemi-spherical structure and method for fabricating the same. A device includes discrete pillar regions on a substrate, and a pattern layer on the discrete support structures and the substrate. The pattern layer has hemi-spherical film regions on the discrete support structures respectively, and planarized portions on the substrate between the... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070155069 - Laser level: A laser level includes: a covering; a stand on which the covering is mounted; a laser unit provided in a space surrounded by the covering and the stand; and a radiation window, provided in the covering, through which a laser beam emitted from the laser unit is radiated to an... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070155065 - Statistical circuit design with carbon nanotubes: Methods and associated structures of forming a microelectronic device are described. Those methods comprise forming a plurality of substantially randomly oriented CNT's on a substrate, and forming at least one source/drain pair, wherein the at least one source/drain pair is coupled to the plurality of substantially randomly oriented CNT's.... Agent: Intel Corporation C/o Intellevate, LLC

20070155070 - Semiconductor device and method for manufacturing the same: An image display device capable of high-resolution and smooth moving image display, equipped with TFTs in an n-type (or p-type) semiconductor layer with a high on-off ratio and a low resistance. In polysilicon crystallization by laser annealing, an n-type (or p-type) semiconductor layer with a low resistance is produced by... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070155071 - Method of reducing edge height at the overlap of a layer deposited on a stepped substrate: A system and method for preparing a stepped substrate and an apparatus are disclosed. The method comprises depositing photoresist on a stepped substrate, removing a first portion of the photoresist, reflowing the remaining portion of the photoresist; and etching a portion of the reflowed remaining photoresist and a portion of... Agent: Reed Smith LLP

20070155072 - Method for fabricating a mesfet: A MESFET and method for fabricating a MESFET are provided. The method includes forming an n-type channel portion in a substrate and forming a p-type channel portion in the substrate. A boundary of the n-type channel portion and a boundary of the p-type channel portion define an intrinsic region in... Agent: Brian C. Oakes Tyco Electronics

20070155078 - Semiconductor device and method for manufacturing the same: A semiconductor device including at least one of: lightly doped drain regions over a semiconductor substrate; a gate insulating layer over a semiconductor substrate between lightly doped drain regions; and/or a gate formed at an upper side of a gate insulating layer. A lower width of a gate may be... Agent: Sherr & Nourse, PLLC

20070155079 - Gate structure of semiconductor device and method of manufacturing the same: A semiconductor gate structure may be manufactured by forming an oxide layer over a silicon substrate before forming a gate insulating layer. The oxide is etched to form an opening that exposes a channel region. After forming a gate insulating layer in the opening, a gate conductor layer is deposited... Agent: Sherr & Nourse, PLLC

20070155077 - Memory cell array: A memory cell array is formed by providing a plurality of memory cells along a substrate, where each of the memory cells includes a storage element and an access transistor. A plurality of bit lines are formed that extend along a first direction of the substrate. A plurality of active... Agent: Edell, Shapiro & Finnan, LLC

20070155076 - Method for fabricating saddle type fin transistor: A method for fabricating a saddle type fin transistor includes: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and performing an etching process using the hard... Agent: Blakely Sokoloff Taylor & Zafman

20070155074 - Method for fabricating semiconductor device to lower source/drain sheet resistance: A method for fabricating a semiconductor device to lower source/drain sheet resistance is provided. A dielectric layer with a plurality of contact windows is formed on a semiconductor device. Next, selective epitaxial growth (SEG) is implemented, and then a metal layer is sputtered. After that, a silicide is formed by... Agent: Rabin & Berdo, PC

20070155075 - Method for forming fin transistor: A method for forming a fin transistor includes forming a fin active region, depositing a thin layer doped with impurities over a semiconductor substrate, and forming a channel by diffusing the impurities into the fin active region of the fin transistor. In detail of the fin transistor formation, a fin... Agent: Blakely Sokoloff Taylor & Zafman

20070155073 - Method of forming device having a raised extension region: A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate... Agent: Larson Newman Abel Polansky & White, LLP

20070155080 - Thim film transistor substrate and manufacturing method thereof: A TFT substrate and manufacturing method thereof disclose a simplified manufacturing process wherein an undercut phenomenon of an active layer can be prevented. A method of manufacturing a TFT substrate includes a first mask process of forming a gate metal pattern including a gate line and a gate electrode connected... Agent: Cantor Colburn, LLP

20070155083 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same are provided. The CMOS image sensor enlarges an area of a real image and prevents interference between adjacent pixels by forming a plurality of microlenses on a convex surface and forming a light blocking layer in the space between... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070155082 - Method for fabricating cmos image sensor: Provided is a method for fabricating CMOS image sensor. One method includes: preparing a semiconductor substrate in which a photodiode region and a transistor region are defined; sequentially forming an insulating layer and a conductive layer on an entire surface of the semiconductor substrate; forming a photoresist pattern for a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070155081 - Method for manufacturing cmos image sensor: A method for manufacturing a CMOS image sensor that independently forms a poly routing line connected to a gate poly of a reset transistor is provided. In an embodiment, a semiconductor substrate is prepared defining a device isolation region and an active region. Subsequently, a plurality of gate polys are... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070155084 - Cmos image sensor and method of manufacturing the same: Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a cell area and a scribe area; masking the cell area, and then removing the first USG... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070155085 - Methods of fabricating static random access memories (srams) having vertical transistors: Unit cells of a static random access memory (SRAM) are provided including an integrated circuit substrate and first and second active regions. The first active region is provided on the integrated circuit substrate and has a first portion and a second portion. The second portion is shorter than the first... Agent: Myers Bigel Sibley & Sajovec

20070155086 - Cmos image sensor and method for manufacturing the same: A complementary metal oxide silicon (CMOS) image sensor includes a pad protection layer having a dual-layer structure including a plasma enhanced-tetra ethyl ortho silicate (PE-TEOS) layer as a lower layer and a thermo-setting resin layer as an upper layer. The thermo-setting resin layer is removed before a micro-lens process and... Agent: Sherr & Nourse, PLLC

20070155087 - Method of manufacturing split gate flash memory: A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling... Agent: Jianq Chyun Intellectual Property Office

20070155088 - Semiconductor device and method of manufacturing the same: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070155089 - Method of manufacturing a capacitor deep trench and of etching a deep trench opening: A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens the deep trench opening. Then, a conductive layer is... Agent: North America Intellectual Property Corporation

20070155090 - Corresponding capacitor arrangement and method for making the same: The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using... Agent: Brinks Hofer Gilson & Lione Infineon

20070155091 - Semiconductor device with capacitor and method for fabricating the same: A method of fabricating a semiconductor device having a capacitor is provided. The method includes forming second, third, fourth, and fifth insulating layers on a first conductive layer formed in a first insulating layer. The fourth insulating layer is patterned into a first pattern before forming the fifth insulating layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070155097 - Method for fabricating flash memory device: A method for fabricating a flash memory device includes the steps of forming a buffer film on a semiconductor substrate having a defined active region; controlling a threshold voltage of a memory cell by ion-implanting dopants into the active region of the substrate under the buffer film; removing the buffer... Agent: Mayer, Brown, Rowe & Maw LLP

20070155095 - Method for manufacturing flash memory cell: A method for manufacturing a flash memory cell with a floating gate and a control gate having an increased coupling ratio due to an increase in gate capacitance. The gate size is increased by reducing a groove width in a photoresist pattern used to define the gate region. The groove... Agent: Sherr & Nourse, PLLC

20070155094 - Method of manufacturing a semiconductor device: Embodiments relate to a method of manufacturing a semiconductor device that may simplify a manufacturing process and may reduce process costs. According to embodiments, the method may include simultaneously forming a first gate of a first device area and a second gate of a second device area, patterning a PMD... Agent: Sherr & Nourse, PLLC

20070155093 - Multi-bit phase-change random access memory (pram) with diameter-controlled contacts and methods of fabricating and programming the same: A phase-change random-access memory (PRAM) device includes a chalcogenide element, the chalcogenide element comprising a material which can assume a crystalline state or an amorphous state upon application of a heating current. A first contact is connected to a first region of the chalcogenide element and has a first cross-sectional... Agent: Mills & Onello LLP

20070155092 - Method for forming a tip: A method for forming a tip is disclosed. A layer is formed overlying a substrate. A mask layer is formed overlying the layer. The mask is patterned to form a mask pattern comprising an inner portion and an outer portion, wherein the inner portion is surrounded by the outer portion.... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070155098 - Method of manufacturing nand flash memory device: A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can... Agent: Marshall, Gerstein & Borun LLP

20070155100 - Non-volatile memory device having a nitride barrier to reduce the fast erase effect: A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are... Agent: Stout, Uxa, Buyan & Mullins LLP

20070155096 - Nonvolatile semiconductor memory and method of manufacturing the same: A nonvolatile semiconductor memory includes a first and a second diffusion layer regions, a floating gate electrode disposed, with a gate insulating film interposed therebetween, on a channel region between the first and second diffusion layer regions, and a control gate electrode serving as a word line and disposed on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070155099 - Nonvolatile semiconductor memory device having excellent charge retention and manufacturing process of the same: There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070155101 - Method for forming a semiconductor device having recess channel: A method for forming a semiconductor device having recess channel includes forming a hard mask film pattern for exposing first regions for forming the trenches on a semiconductor substrate; forming first trenches by a first etching process using the hard mask film pattern as a mask, and removing the hard... Agent: Townsend And Townsend And Crew, LLP

20070155102 - Method of fabricating an integrated circuit: Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer,... Agent: Morrison & Foerster LLP

20070155103 - Semiconductor integrated circuit device and a method of manufacturing the same: Manufacturing technique for an IC device which includes forming the first conductor film over a memory cell forming region and over a peripheral circuit forming region of a semiconductor substrate, patterning the first conductive film lying over the memory cell forming region to form a first conductive pattern which serves... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070155104 - Power device utilizing chemical mechanical planarization: A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than... Agent: Townsend And Townsend And Crew, LLP

20070155105 - Method for forming transistor of semiconductor device: A method for forming transistors of a semiconductor device includes forming a plurality of gate stacks on a semiconductor substrate; and forming a spacer oxide film on the semiconductor substrate having the plurality of gate stacks formed thereon using a single-type radical-assisted CVD apparatus. The method further includes oxidizing the... Agent: Townsend And Townsend And Crew, LLP

20070155106 - Method of manufacturing cmos image sensor: Disclosed is a method of manufacturing a CMOS image sensor. The method reduces a difference in the height of the interconnection layers over the logic area and pixel array area. At the same time, the method also provides a closer proximity between the micro-lenses and the pixel array. A semiconductor... Agent: Sherr & Nourse, PLLC

20070155107 - High-voltage semiconductor device and method of manufacturing the same: A high-voltage semiconductor device and a method for making the same are provided. A high-voltage semiconductor device and a low-voltage semiconductor device are formed in a single substrate, a photolithography process that is required to form a high-voltage well region is omitted, and the well region of the high-voltage semiconductor... Agent: Mayer, Brown, Rowe & Maw LLP

20070155108 - Doping mask and methods of manufacturing charge transfer image and microelectronic device using the same: Provided are a doping mask and methods of manufacturing a charge transfer image device and a microelectronic device using the same. The method includes forming a photoresist film on an entire surface of a substrate or sub-substrate having a peripheral circuit region and a pixel region, removing the photoresist film... Agent: Mills & Onello LLP

20070155109 - Method for fabricating a semiconductor device: Embodiments relate to a method for fabricating a semiconductor device. In embodiments, the method may include forming a gate insulating layer and a gate on a semiconductor substrate, performing a rapid thermal process, in which a sidewall oxidation process and a gate conductance annealing process are combined as a single... Agent: Sherr & Nourse, PLLC

20070155110 - Method for manufacturing semiconductor device: Embodiments relate to a method for manufacturing a semiconductor device that may improve a formation of a drain and a source of a transistor. According to embodiments, a method for manufacturing a semiconductor device may include forming a gate electrode on a semiconductor substrate, forming a first spacer at a... Agent: Sherr & Nourse, PLLC

20070155111 - Method of fabricating a semiconductor device having a pre metal dielectric liner: A method of fabricating a semiconductor device including forming a pre metal dielectric liner over a semiconductor substrate on which a transistor is formed. The pre metal dielectric liner is sputter etched to form an unstable interface at the surface. The boron is trapped in an interface in an unstable... Agent: Sherr & Nourse, PLLC

20070155112 - Mom capacitor: A method of manufacturing a capacitor, which uses metal as a top electrode and a bottom electrode. A plurality of first electrodes may be formed with a plurality of first conductive lines and a plurality of plugs. A plurality of second electrodes may be formed with a plurality of second... Agent: Sherr & Nourse, PLLC

20070155114 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a sacrificial layer for forming a lower electrode as an amorphous carbon layer in order to prevent collapsing of a cylindrical lower electrode. When an alignment process is not normally performed to arrange photoresist mask pattern for storage electrode and lower... Agent: Townsend And Townsend And Crew, LLP

20070155115 - Semiconductor device having capacitor large in capacitance and high in reliability and method of manufacturing the same: A method according to the present invention includes forming a silicon nitride film on a lower electrode, oxidizing the silicon nitride film, and forming a dielectric film including aluminum on the oxidized silicon nitride film.... Agent: Young & Thompson

20070155113 - Thin-film capacitor with a field modification layer and methods for forming the same: A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode.... Agent: Freescale Semiconductor, Inc. Law Department

20070155116 - Method of measuring shifted epitaxy layer by buried layer: A method of measuring a shifted extent of a shifted epitaxy layer by an N+ buried layer using difference between contact resistances is described. An N-type buried layer comprising a stepped portion is formed at a P-type substrate. An epitaxy layer is formed, comprising a stepped portion, on the N-type... Agent: Mayer, Brown, Rowe & Maw LLP

20070155117 - Phase change memory and method therefor: Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include a memory material and a first tapered contact adjacent to the memory material. The phase change memory may further include... Agent: Trop Pruner & Hu, PC

20070155118 - Method for forming a notched gate insulator for advanced mis semiconductor devices and devices thus obtained: Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode... Agent: Knobbe Martens Olson & Bear LLP

20070155127 - Image sensor and method of fabricating the same: The image sensor includes a substrate, having a photodiode region and a device separation region; a trench formed in the device separation region; and a nitride film formed on the inner surface of the trench. The nitride film may comprise one formed using a gas selected from among N2, NO,... Agent: Mayer, Brown, Rowe & Maw LLP

20070155128 - Method for forming trench: Provided is a method for forming a trench, capable of rounding a top corner without adding a separate mask or process. In the method, first and second insulating layers are stacked on a substrate having an isolation region and an active region. Subsequently, a photoresist pattern is formed on the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070155126 - Method for manufacturing semiconductor device with overlay vernier: A method for manufacturing a semiconductor device comprising dishing a part of a center of an isolation oxide film to form an overlay vernier having a step difference, prevents an attack in a CMP process of a gate polysilicon layer and improves an overlay characteristic due to the right-and-left symmetrical... Agent: Heller Ehrman LLP

20070155124 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device wherein a gate insulating layer and a polysilicon layer are formed over a semiconductor substrate in which a cell region and a peri region are defined. Portions of the polysilicon layer, the gate insulating layer, and the semiconductor substrate of the peri region... Agent: Marshall, Gerstein & Borun LLP

20070155121 - Technique for forming an isolation trench as a stress source for strain engineering: By forming a non-oxidizable liner in an isolation trench and selectively modifying the liner within the isolation trench, the stress characteristics of the isolation trench may be adjusted. In one embodiment, a high compressive stress may be obtained by treating the liner with an ion bombardment and subsequently exposing the... Agent: Williams, Morgan & Amerson

20070155120 - Trench isolation structure for a semiconductor device with reduced sidewall stress and a method of manufacturing the same: By forming a non-oxidizable liner in isolation trenches, the creation of compressive stress may be significantly reduced, wherein, in illustrative embodiments, silicon nitride may be used as liner material. For this purpose, the etch behavior of the silicon nitride may be efficiently modified on the basis of an appropriate surface... Agent: Williams, Morgan & Amerson

20070155122 - Trench isolation structure having different stress: By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative embodiments, the different anneal temperature may be achieved on the basis of an appropriate mask layer, which may provide a patterned optical response for a... Agent: Williams, Morgan & Amerson

20070155125 - Method for forming shallow trench isolation of semiconductor device: A shallow trench isolation well is formed to be very thin in a highly integrated semiconductor device. When critical dimension (CD) is small, it is difficult to reduce the width of the photosensitive layer pattern for forming a trench to no more than a predetermined value due to limitations on... Agent: Sherr & Nourse, PLLC

20070155119 - Method of manufacturing a field effect transistor device with recessed channel and corner gate device: Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in... Agent: Edell, Shapiro & Finnan, LLC

20070155123 - Method of manufacturing semiconductor device: Disclosed are embodiments relating to a method of manufacturing a semiconductor device that may improve the yield rate of the semiconductor device. In embodiments, the method may include preparing a substrate including a plurality of conductive patterns, forming first and second insulating layers on the substrate, forming a plurality of... Agent: Sherr & Nourse, PLLC

20070155129 - Combination of a substrate and a wafer: The invention pertains to a combination of a substrate (6) and a wafer (15), wherein the substrate (6) and the wafer (15) are arranged parallel to one another and bonded together with the aid of an adhesive layer (8) situated between the substrate (6) and the wafer (15), and wherein... Agent: Kusner & Jaffe Highland Place Suite 310

20070155130 - Strained si mosfet on tensile-strained sige-on-insulator (sgoi): A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer... Agent: Scully, Scott, Murphy & Presser, P.C.

20070155131 - Method of singulating a microelectronic wafer: A method of singulating a microelectronic wafer. The method comprises: providing a microelectronic wafer; focusing a laser beam in an interior region of the wafer from the backside of the wafer to form a modified region extending along the severance lines of the wafer dividing the wafer IC chips, the... Agent: Intel Corporation C/o Intellevate, LLC

20070155132 - Method of manufacture for a component including at least one single-crystal layer on a substrate: The invention refers to a method of manufacture for a component including a single-crystal substrate on which is deposed at least one single-crystal layer, the method including one or several steps for single-crystal layers' deposit by pulverisation of a metal or of semi-conductors inside a plasma of gas, and the... Agent: Ratnerprestia

20070155133 - Method of reducing contamination by providing an etch stop layer at the substrate edge: By providing an etch stop layer selectively at the bevel, at least one additional wet chemical bevel etch process may be performed prior to or during the formation of a metallization layer without affecting the substrate material. Hence, the dielectric material, especially the low-k dielectric material, may be reliably removed... Agent: Williams, Morgan & Amerson

20070155134 - Annealed wafer and manufacturing method of annealed wafer: An annealed wafer in which oxygen precipitation is uniform in the substrate plane and a manufacturing method thereof are provided. A nitrogen-doped silicon single crystal substrate pulled at the cooling rate of 4° C./minute or more during crystal growth between 1100 and 1000° C. wherein the nitrogen concentration is 1×1014... Agent: Kolisch Hartwell, P.C.

20070155136 - Carbon nanotube and metal thermal interface material, process of making same, packages containing same, and systems containing same: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070155137 - High density plasma non-stoichiometric sioxny films: A high-density plasma method is provided for forming a SiOXNY thin-film. The method provides a substrate and introduces a silicon (Si) precursor. A thin-film is deposited overlying the substrate, using a high density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, a SiOXNY thin-film is formed, where (X+Y<2... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070155135 - Method of fabricating a polysilicon layer and a thin film transistor: A method of fabricating a polysilicon layer is provided. A substrate having a front surface and a back surface is provided. A buffer layer, an amorphous layer and a cap layer are sequentially formed on the front surface of the substrate. The cap layer is patterned to form a patterned... Agent: Jianq Chyun Intellectual Property Office

20070155138 - Apparatus and method for depositing silicon germanium films: A new model is provided for the CVD growth of silicon germanium from silicon-containing and germanium-containing precursors. According to the new model, the germanium concentration x is related to the gas phase ratio according to the equation [x/(1−x)]2=mPGe/PSi, and m=Ae−E/(RT), where PSi is the partial pressure of the silicon-containing precursor,... Agent: Knobbe Martens Olson & Bear LLP

20070155139 - Method for fabricating an integrated circuit on a semiconductor substrate: Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate... Agent: Morrison & Foerster LLP

20070155140 - Manufacturing method of semiconductor film and image display device: A semiconductor thin film is manufactured by scanning laser light or a substrate onto an arbitrary region of the semiconductor thin film and irradiating a laser thereon. The semiconductor thin film is formed by the substantially belt-shaped crystal being crystallized such that crystalline grains grow in the scanning direction, on... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070155141 - Semiconductor device and method for fabricating the same: A semiconductor device and method for manufacturing the same. A cobalt silicide layer is placed on a silicon germanium layer through an MOCVD process, by forming a silicon germanium thin film on a first conductive type silicon substrate, implanting second conductive type impurities onto the silicon germanium thin film, and... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070155142 - Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers: A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first... Agent: Blakely Sokoloff Taylor & Zafman

20070155143 - High voltage semiconductor transistor device: Embodiments relate to a high voltage semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor transistor device may include a substrate made of impurities of a first conductivity, an LDD region made of low concentration impurities of a second conductivity doped in the substrate to... Agent: Sherr & Nourse, PLLC

20070155144 - Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion... Agent: Rossi, Kimms & Mcdowell LLP.

20070155145 - Method for forming a copper metal interconnection of a semiconductor device using two seed layers: A method for forming a copper metal interconnection of a semiconductor device using two seed layers is provided. The method includes forming an inter-layer dielectric layer on a substrate, forming a damascene pattern on the inter-layer dielectric layer, forming a barrier metal layer in the damascene pattern and on an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070155146 - Method for forming semiconductor wafer having insulator: Provided is a method for forming a semiconductor wafer having an insulator. According to the method, an insulating layer pattern and a silicon germanium layer are formed on a wafer, and a structure similar to a SOI wafer is formed. Accordingly, since the thin insulating layer pattern exists between the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070155147 - Semiconductor device and method for fabricating the same: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive... Agent: Mcdermott Will & Emery LLP

20070155148 - Method for forming semiconductor device having fin structure: A method for forming a semiconductor device having a fin structure includes (a) forming a device isolation film over a silicon substrate to define an active area, (b) etching silicon substrate of gate forming region to form a trench, (c) selectively etching the device isolation film of a trench boundary,... Agent: Heller Ehrman LLP

20070155150 - Method of forming a semiconductor device having an etch stop layer and related device: In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielectric layer. An etch stop layer is formed over the interconnection patterns.... Agent: Marger Johnson & Mccollom, P.C.

20070155151 - Semiconductor device and a manufacturing method: A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate, a via exposing the substrate, a plug filling the via, a metal wiring layer on the first interlayer insulating film contacting the plug, and a second interlayer insulating film supported by the metal wiring and being... Agent: Sherr & Nourse, PLLC

20070155152 - Method of manufacturing a copper inductor: An inductor can be integrated with other components in a device formed on one semiconductor chip. The integrated circuit inductor has reduced electric resistance in the conductor and minimized influence on other circuit elements. A method of manufacturing the inductor which minimizes the area occupied by the inductor in a... Agent: Sherr & Nourse, PLLC

20070155149 - Methods and structures for electrically coupling a conductor and a conductive element comprising a dissimilar material: Methods and structures are provided for electrically coupling a conductor and a conductive element comprising a dissimilar material. A method for electrically coupling a first element comprising a first conductive material to a conductor formed of a dissimilar second material comprises cladding a second conductive element with the conductor. The... Agent: Medtronic, Inc.

20070155153 - Semiconductor device having electrode and manufacturing method thereof: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating... Agent: Mcdermott Will & Emery LLP

20070155154 - System and method for solder bumping using a disposable mask and a barrier layer: According to some embodiments, a method, an apparatus, and a system are provided. In some embodiments, the method includes applying solder resist material on a surface of a substrate, applying a barrier layer on top of the solder resist material, applying at least one layer of mask material on top... Agent: Buckley, Maschoff & Talwalkar LLC Attorneys For Intel Corporation

20070155155 - Manufacturing method for semiconductor device and semiconductor device: A manufacturing method for a semiconductor device, including the steps of: forming a passivation film that covers a surface of a semiconductor substrate on which electrodes have been formed, in which an opening is formed so as to expose a predetermined electrode from among the electrodes; forming a diffusion prevention... Agent: Rabin & Berdo, P.C.

20070155156 - Bonding pad structure for a display device and fabrication method thereof: A bonding pad structure of a display device. A first conductive layer is formed overlying a substrate, a protection layer is formed overlying the substrate and the first conductive layer, and a second conductive layer is formed overlying the protection layer. An opening structure penetrates the second conductive layer and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070155158 - Carbon nanotube interconnect structures: A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a... Agent: Blakely Sokoloff Taylor & Zafman

20070155157 - Structure of metal interconnect and fabrication method thereof: A process and structure for a metal interconnect comprises providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and... Agent: North America Intellectual Property Corporation

20070155159 - Method for forming under a thin layer of a first material portions of another material and/ or empty areas: A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070155160 - Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design: A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive... Agent: Lsi Logic Corporation

20070155161 - Selective removal of sacrificial light absorbing material over porous dielectric: A method of forming a semiconductor device. The method comprises forming a conductive layer on a substrate, forming a porous dielectric layer on the conductive layer, and forming a first etched region by removing a first portion of the porous dielectric layer. The first etched region is then filled with... Agent: Blakely Sokoloff Taylor & Zafman

20070155162 - Method for forming a dual interlayer dielectric layer of a semiconductor device: A method for forming a dual interlayer dielectric layer, which is capable of preventing an interlayer delamination phenomenon generated between an etch stop layer and an interlayer dielectric layer is provided. An interlayer dielectric layer of a dual structure is formed such that a first interlayer dielectric layer and a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070155163 - Method for fabricating a thin film and a metal line of a semiconductor device: A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate by employing an atomic layer deposition method; and converting a part of the TaN film into a Ta by reacting the TaN film with NO2 to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070155164 - Metal seed layer deposition: A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation... Agent: Schmeiser, Olsen & Watts

20070155167 - Method for forming metal interconnection in image sensor: A method for forming a metal interconnection in an image sensor includes forming a first interlayer dielectric (ILD) layer having a contact plug over a substrate, forming a diffusion barrier layer over the first ILD layer, performing a forming gas annealing, forming a second ILD layer over the diffusion barrier... Agent: Morgan Lewis & Bockius LLP

20070155166 - Method and apparatus for depositing copper wiring: A method of depositing copper wiring that includes at least one of the following. Transporting a semiconductor substrate with a damascene pattern into a first chamber. Substantially concurrently performing a degassing process and a process of removing a Copper Oxide film on a semiconductor substrate located in a first chamber.... Agent: Sherr & Nourse, PLLC

20070155165 - Methods for forming damascene wiring structures having line and plug conductors formed from different materials: Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure comprising... Agent: F. Chau & Associates, LLC

20070155168 - Method for forming a conductive plug of a semiconductor device: Embodiments relate to a method for forming a conductive plug of a semiconductor device that may include preparing a semiconductor substrate having multilayer metal interconnections, forming interlayer insulating layers above the semiconductor substrate, etching part of each interlayer insulating layer such that each multilayer metal connection is exposed, and forming... Agent: Sherr & Nourse, PLLC

20070155170 - Method for forming a damascene pattern of a copper metallization layer: There is provided a method of forming a damascene pattern including a via and a trench in a damascene process of forming a copper metal interconnection. The method includes forming an interlayer dielectric layer on a substrate, forming a first photosensitive layer pattern including a first opening that exposes a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070155169 - Method of fabricating a thin film and metal wiring in a semiconductor device: A method for forming a thin film of a semiconductor device, which may include at least one of the following steps: Forming a Tantalum Nitride (TaN) film over a semiconductor substrate by atomic layer deposition. Forming a Tantalum (Ta) film by converting at least a portion of a Tantalum Nitride... Agent: Sherr & Nourse, PLLC

20070155171 - Metal interconnection of semiconductor device and method for forming the same: A metal interconnection of a semiconductor device and a method for forming the same include a diffusion barrier having favorable EM (electro migration) and SM (stress induced migration) properties, thereby preventing voids or other defects in copper interconnections. The diffusion barrier is made of two layers to better match coefficients... Agent: Sherr & Nourse, PLLC

20070155173 - Nanowires and method for making the same: A method for preparing nanowires is disclosed, which comprises the following steps: (a) providing a first precursor solution containing IIB group elements, and a second precursor solution containing VIA group elements; (b) mixing and heating the first precursor solution and the second precursor solution to form a mixed solution; and... Agent: Bacon & Thomas, PLLC

20070155172 - Manufacturing method for phase change ram with electrode layer process: A method for manufacturing a phase change memory device comprises forming an electrode layer. Electrodes are made in the electrode layer using conductor fill techniques that are also used inter-layer conductors for metallization layers, in order to improve process scaling with shrinking critical dimensions for metallization layers. The electrode layer... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070155174 - Circuit substrate and method for fabricating the same: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly,... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070155175 - Semiconductor device: Embodiments relate to a semiconductor device and a method of fabricating semiconductor device, that may uniformly form a barrier layer in a via hole to thus prevent layers from being broken. In embodiments, a method of fabricating a semiconductor device may include forming an interlayer dielectric layer on a substrate,... Agent: Sherr & Nourse, PLLC

20070155176 - Interconnect circuitry, multichip module, and methods of manufacturing thereof: Methods of electroless plating metal on a dielectric material includes dipping the dielectric in a solution containing attractive catalytic metal particles and a metal salt solution. A thicker metallic layer can be deposited on top of the resulting layer by electroplating. Electrical circuits and multichip modules including such circuits can... Agent: Burns & Levinson, LLP

20070155177 - Method for fabricating semiconductor device: Embodiments relate to a method of manufacturing a semiconductor device, wherein voids on a copper seed layer may be removed. According to embodiments, a method of manufacturing a semiconductor device may include forming at least one type of an insulating layer on the entire surface of a semiconductor substrate, forming... Agent: Sherr & Nourse, PLLC

20070155178 - Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same: A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed... Agent: Mills & Onello LLP

20070155179 - Method to define a pattern having shrunk critical dimension: The present invention provides a method for fabricating a trench opening in a semiconductor substrate. The patterned amorphous silicon layer is completely oxidized to form a silicon oxide mask having openings with shrunk critical dimensions. The silicon oxide mask is used as an etching hard mask in the subsequent trench... Agent: North America Intellectual Property Corporation

20070155180 - Thin film etching method: A thin film etching method is provided, which is used for manufacturing semiconductor device or thin film transistor (TFT) array and through which no undercut may be presented or a good after-etching shape may be achieved with respect to a thin film thus etched. The thin film etching method is... Agent: Venable LLP Raymond J. Ho

20070155181 - Method and system for etching high-k dielectric materials: A system and a method to remove a layer of high-k dielectric material during the manufacturing of an integrated circuit. In one embodiment of the invention, an etch reactant is employed to form volatile etch products when reacted with high-k layers. Alternately, high-k layers can be anisotropically etched of in... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070155182 - Manufacturing method of semiconductor device: In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070155183 - Process for manufacturing wafers usable in the semiconductor industry: To manufacture a layer of semiconductor material, a first wafer of semiconductor material is subjected to implantation to form a defect layer at a distance from a first face; the first wafer is bonded to a second wafer, by putting an insulating layer present on the second wafer in contact... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070155185 - Electrical sensor for real-time feedback control of plasma nitridation: A device (101) for controlling the treatment of a substrate (102) with a plasma (103) is provided which comprises (a) a plasma chamber (104) adapted to generate a plasma (103); (b) a sensor (113) equipped with first (115) and second (117) electrodes that are exposed to the plasma generated within... Agent: Fortkort & Houston P.C.

20070155184 - Method for producing a nanostructure such as a nanoscale cantilever: Producing a nanostructure, such as a nano-scale cantilever or a nanobridge, involves forming an elevational discontinuity, growing a nanowire that extends out from an upper surface of the elevational discontinuity, and then changing the orientation of the nanowire such that a portion of the nanowire extends above a lower surface... Agent: Agilent Technologies Inc.

20070155187 - Method for preparing a gate oxide layer: A method for preparing a gate oxide layer is described. First, a trench surrounding an active area is formed in a substrate, and a dielectric block is then formed in the trench such that an upper surface of the dielectric block is not aligned with that of the substrate. Subsequently,... Agent: Oliff & Berridge, PLC

20070155186 - Optimized sicn capping layer: A back-end-of-line (BEOL) interconnect structure and a method of forming an interconnect structure. The interconnect structure comprises a conductor, such as copper, embedded in a dielectric layer, and a low-k dielectric capping layer, which acts as a diffusion barrier, on the conductor. A method of forming the BEOL interconnect structure... Agent: International Business Machines Corporation Dept. 18g

20070155188 - Method of forming photoresist pattern and method of manufacturing perpendicular magnetic recording head: Provided is a method of forming a photoresist pattern enabling the three dimensional shape of a photoresist pattern to be controlled sufficiently. A photoresist pattern for forming a main magnetic pole layer can be formed by forming a preparatory photoresist pattern having a projected part at a position corresponding to... Agent: Oliff & Berridge, PLC

20070155189 - Use of teos oxides in integrated circuit fabrication processes: A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask.... Agent: Macpherson Kwok Chen & Heid LLP

20070155190 - Systems and methods for forming metal oxide layers: A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.... Agent: Mueting, Raasch & Gebhardt, P.A.