Semiconductor device manufacturing: process inventions 06/07

20070148792 - Wafer measurement system and apparatus: A method and apparatus for the measurement of wafer thickness, flatness and the trench depth of any trenches etched thereon using the back surface of the wafer to accurately measure the back side of a trench, rendering the trench an effective bump, capable of being measured on the top surface... Agent: Sandra Lee Lipkin A Law Corporation

20070148799 - Liquid crystal display and fabrication method thereof: A liquid crystal display and a fabricating method thereof are provided. The liquid crystal display includes a first substrate having a pixel portion and a pad portion; a gate line and a data line crossing each other to define the pixel portion at the pixel portion; a transistor adjacent to... Agent: Birch Stewart Kolasch & Birch

20070148786 - Mgo/nife mtj for high performance mram application: An improved tunneling barrier layer is formed for use in a MTJ device. This is accomplished by forming the tunneling barrier layer in two steps. First a layer of magnesium is deposited by DC sputtering and converted to magnesium oxide through radical oxidation. This is followed by a second, thinner,... Agent: Stephen B. Ackerman

20070148787 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device that prevents an etching residue left at the time of making a contact hole which connects with a ferroelectric capacitor from adhering to the surface of a wafer. In order to make a contact hole which connects with an upper electrode or a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070148789 - Methods of forming magnetic random access memory devices having titanium-rich lower electrodes with oxide layer and oriented tunneling barrier: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An... Agent: Myers Bigel Sibley & Sajovec

20070148788 - Semiconductor piezoresistive sensor and operation method thereof: A semiconductor piezoresistive sensor, which is electrically connected with a circuit, includes a semiconductor base, at least one piezoresistive element and a conductive layer. The semiconductor base includes a diaphragm and a base. The base is disposed adjacent to and around the diaphragm. The piezoresistive element is formed in the... Agent: Birch Stewart Kolasch & Birch

20070148795 - Insulator film characteristic measuring method and insulator film characteristic measuring apparatus: A method is for measuring the characteristics of an insulator film (inner charge amount, film thickness, relative dielectric constant, surface voltage change due to a surface adsorbed substance, etc.) formed on a surface of a semiconductor substrate in a non-contact manner. This method includes: a step of measuring a measured... Agent: Mcdermott Will & Emery LLP

20070148794 - Method for designing a semiconductor device capable of reflecting a time delay effect for dummy metal fill: Disclosed is a method for designing a semiconductor device. In an existing semiconductor design, a time delay effect caused by a dummy metal interconnection cannot be reflected. In order to address this disadvantage, a real metal fill pattern and a virtual metal fill pattern are employed for a layout parasitic... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148790 - Method for treatment of samples for auger electronic spectrometer (aes) in the manufacture of integrated circuits: A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The... Agent: Townsend And Townsend And Crew, LLP

20070148791 - Method of measuring film thickness and method of manufacturing semiconductor device: A method of measuring a film thickness is disclosed. The method includes a step of forming a ferroelectric capacitor on a substrate, a step of forming an insulating film to cover the ferroelectric capacitor, and a step of optically measuring the thickness of the insulating film on an electrode of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070148793 - Semiconductor device, display device, and electronic device: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing... Agent: Fish & Richardson P.C.

20070148796 - Zq calibration circuit and semiconductor device: AZQ calibration command internally generated from an external command different from a ZQ calbration command so as to automatically perform an additional ZQ calibration operation. A command interval between an imputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from... Agent: Sughrue Mion, PLLC

20070148797 - Forming electronic devices: A method of manufacturing a device, comprising printing an aqueous solution or dispersion comprising an electronically functional substance, for example a conducting polymer such as PEDOT-PSS, and a surface tension reducing agent onto predetermined portions of a hydrophobic surface, for example formed by a ferroelectric polymer layer. The conducting polymer... Agent: Oliff & Berridge, PLC

20070148798 - Fabrication method of transparent electrode on visible light-emitting diode: A method for forming a transparent electrode on a visible light-emitting diode is described. A visible light-emitting diode element is provided, and the visible light-emitting diode element has a substrate, an epitaxial structure and a metal electrode. The metal electrode and the epitaxial structure are located on the same side... Agent: Glenn Patent Group

20070148800 - Liquid crystal display device and fabrication method thereof: A liquid crystal display (LCD) device and its fabrication method includes providing a substrate divided into pixel part and pad parts; forming a gate electrode and a gate line at the pixel part through a first masking process; forming a first insulation film; forming an active pattern and source and... Agent: Birch Stewart Kolasch & Birch

20070148802 - Method for fabricating transflective liquid crystal display: An exemplary method for fabricating a transflective liquid crystal display is provided. The transflective liquid crystal display includes a substrate (200) having a transmission region (201) and a reflection region (202). The method includes: forming a transparent electrode layer (210), a buffer layer (220), and a reflective metal layer (230)... Agent: Wei Te Chung Foxconn International, Inc.

20070148801 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device includes the steps of: forming a gate on a semiconductor substrate; sequentially stacking a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate; forming a first photoresist layer pattern on the second oxide layer;... Agent: Mayer, Brown, Rowe & Maw LLP

20070148803 - Production method for semiconductor device: An object of the present invention is to provide a method of producing a Group III nitride semiconductor device having a chip form which is pentagonal or more highly polygonal maintaining good area efficiency and at a low cost. The inventive method of producing a Group III nitride semiconductor device... Agent: Sughrue Mion, PLLC

20070148804 - Method of making a multilayered device with ultra-thin freestanding metallic membranes using a peel off process: A micro electromechanical device includes a substrate having stacked films. Each of the films includes a first layer and a second layer. The second layer is metal of a predetermined thickness. The stacked films are formed by electroplating the second layer on the first layer and lifting off a third... Agent: Blakely Sokoloff Taylor & Zafman

20070148805 - Method for manufacturing cmos image sensor: A method for manufacturing a CMOS image sensor is disclosed. The method includes the steps of: forming a passivation oxide and a passivation nitride after forming a pad; performing a hydrogen anneal; selectively removing the passivation nitride and cleaning the passivation oxide; opening and cleaning the pad by removing the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148806 - Method of fabricating complementary metal oxide silicon image sensor: Provided is a method of fabricating a complementary metal oxide silicon image sensor. The method includes: applying a passivation oxide and a passivation nitride after forming a pad; selectively removing the passivation nitride in a pad region and a pixel region by a photolithography process, and performing a first cleaning... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148807 - Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers: Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including a first substrate and an image sensor on and/or in the first substrate. An embodiment of an optical device includes a stand-off having a compartment configured to contain the... Agent: Dickstein Shapiro LLP

20070148808 - Method of manufacturing cmos image sensor: Embodiments relate to a method of manufacturing a CMOS image sensor in which, when a buried photodiode is formed, a p-type impurity region may be formed simultaneously with a p-type LDD region in the photo diode region. Additionally, a p-type impurity region may be formed under side wall spacers, which... Agent: Sherr & Nourse, PLLC

20070148809 - Method of manufacturing image sensor: A method of manufacturing an image sensor, which avoids corroding a pad electrode with overexposure to corrosive chemicals, includes forming a pad electrode over a semiconductor substrate, forming a passivation layer over the pad electrode, applying a photoresist over the passivation layer, etching the photoresist and passivation layer to form... Agent: Sherr & Nourse, PLLC

20070148810 - Functional paste: [Aims] To provide functional paste with etching activity and good electrical properties. [Means] Functional paste comprising a metal powder, an etching agent, a binder and an organic solvent.... Agent: Millen, White, Zelano & Branigan, P.C.

20070148811 - Method for manufacturing cmos image sensor: A method for manufacturing a CMOS image sensor is provided. The method can include forming an interlayer dielectric layer on a semiconductor substrate including a gate electrode, photodiode area, and LDD region; selectively removing the interlayer dielectric layer such that the interlayer dielectric layer remains on the photodiode area; performing... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148813 - Electric device, method of manufacturing electric device and electric apparatus: An electric device includes: a pair of electrodes, an organic semiconductor film and an organic film formed on a surface of at least one of the electrodes, wherein the organic this film includes a nonconjugated organic compound having a plurality of coupling groups coupled with the electrodes.... Agent: Oliff & Berridge, PLC

20070148812 - Organic thin-film transistors: Methods are disclosed for improving organic thin-film transistor (OTFT) performance by acid doping of the semiconducting layer. The semiconducting polymer comprising the semiconductor layer is doped with an acid, especially a Lewis acid, either during or after polymerization of the polymer, but prior to application of the polymer onto the... Agent: Richard M. Klein, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070148814 - Process for manufacturing a phase change memory array in cu-damascene technology and phase change memory array thereby manufactured: A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively;... Agent: Seed Intellectual Property Law Group PLLC

20070148815 - Nano-array and fabrication method thereof: The invention provides a method for fabricating a nano-array comprising the following steps. A template with a plurality of nano-holes is provided. A polymer is embossed by the template to integrally form a plurality of nano-protrusions thereon, and demolding to reveal the nano-protrusions. The nano-protrusion has a concave or convex... Agent: Birch Stewart Kolasch & Birch

20070148816 - Attachment of a qfn to a pcb: Methods and arrangements to attach a QFN to a PCB, systems which include a QFN attached to a PCB, and apparatuses for controlling the deposit of solder upon a PCB are disclosed. Embodiments include transformations, code, state machines or other logic to calculate a total area for the QFN IO... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070148818 - Electrical connection methods employing corresponding, insulator-coated members of interconnection elements: A method of electrically connecting corresponding contact pads of semiconductor device components to each other includes interconnecting first and second members of an interconnection element. The first and second members respectively protrude from first and second semiconductor device components, with a conductive element of each member in communication with a... Agent: Trask Britt, P.C./ Micron Technology

20070148817 - Methods for fabricating reinforced, self-aligning conductive structures for semiconductor device components: A method for fabricating an electrical interconnection element, or conductive structure, includes disposing a jacket of a first member of the electrical interconnection element laterally around a contact of a semiconductor device structure and introducing conductive material into the jacket. The jacket, which may be electrically insulative, may include a... Agent: Trask Britt, P.C./ Micron Technology

20070148819 - Microelectronic assemblies having very fine pitch stacking: A microelectronic assembly includes two or more microelectronic packages stacked at a fine pitch, which is finer than the pitch that is possible when using solder balls for making the joint. Each stackable package desirably includes a substrate having pins projecting from one surface of the substrate and solder balls... Agent: Tessera Lerner David Et Al.

20070148820 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes attaching a first die to a support member, coupling a second die to the first die with the first die positioned between the second die and the support member, and placing the... Agent: Perkins Coie LLP Patent-sea

20070148821 - Thermally enhanced stacked die package and fabrication method: A substrate is provided. A first die is attached to the substrate. The first die is electrically connected to the substrate. A heat sink having an undercut around its periphery is attached to the first die. A second die is attached to the heat sink. The second die is electrically... Agent: Ishimaru & Zahrt LLP

20070148822 - Microelectronic packages and methods therefor: A method of making a microelectronic assembly includes providing a microelectronic package having a substrate, a microelectronic element overlying the substrate and at least two conductive elements projecting from a surface of the substrate, the at least two conductive elements having surfaces remote from the surface of the substrate. The... Agent: Tessera Lerner David Et Al.

20070148824 - Compliant terminal mountings with vented spaces and methods: A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The... Agent: Tessera Lerner David Et Al.

20070148823 - Method of manufacturing an electronic protection device: A method of manufacturing an electronic protection device comprises: providing a substrate mother board with a top surface and a bottom surface; forming a first conductive layer and a second conductive layer on the top surface and the bottom surface, respectively; cutting the substrate mother board into a plurality of... Agent: Volentine Francos, & Whitt PLLC

20070148826 - Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement: An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement.... Agent: Scully, Scott, Murphy & Presser, P.C.

20070148825 - Semiconductor device and manufacturing method for the same: A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second... Agent: Sughrue Mion, PLLC

20070148827 - Method of manufacturing wiring substrate, liquid ejection head and image forming apparatus: The method of manufacturing a wiring substrate includes the steps of: filling conductive material into a through hole and a non-through hole of a substrate; removing the conductive material filled into the through hole; and removing at least a portion of a rear side of the substrate which is opposite... Agent: Birch Stewart Kolasch & Birch

20070148828 - Substrate supporting frame: A substrate supporting frame, a substrate supporting frame assembly including the frame, a method of framing a substrate using the frame, a method of fabricating a donor substrate using the substrate supporting frame assembly, and a method of fabricating an Organic Light Emitting Display (OLED) using the donor substrate each... Agent: Robert E. Bushnell

20070148829 - Multi-layered flexible print circuit board and manufacturing method thereof: Provided is an FPC, which comprises an insulating layer 2, wiring layers 3 and 4 laminated above and under the insulating layer 2, and a layer connection for connecting the wiring layers 3 and 4 electrically. The layer connection is constituted to comprise: a conductor press-fit hole 5 of a... Agent: Greenblum & Bernstein, P.L.C

20070148830 - Nor-type flash memory cell array and method for manufacturing the same: Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148832 - Method for manufacturing a semiconductor substrate, method for manufacturing a semiconductor device, and the semiconductor device: A method for manufacturing a semiconductor substrate having a silicon-on-insulator (SOI) structure region isolated by a local oxidation of silicon (LOCOS) film and an SOI structure in the region includes forming the LOCOS film so as to make a height from an uppermost surface of a semiconductor member to a... Agent: Advantedge Law Group, LLC

20070148831 - Thin film transistor device, method for manufacturing the same and display apparatus having the same: A thin film transistor device includes: an island shaped semiconductor layer; a metal film that covers at least a part of a source region and a drain region of the semiconductor layer; a gate insulating film that covers the semiconductor layer and the metal film; an interlayer insulating film that... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070148833 - Thin film transistor and method of manufacturing the same: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of... Agent: H.c. Park & Associates, PLC

20070148834 - Laser irradiation apparatus and laser irradiation method: It is an object of the present invention to provide a laser irradiation apparatus which can manufacture a homogenously crystallized film by varying the energy intensity of an irradiation beam in forward and backward directions of the irradiation. A laser irradiation apparatus of the present invention comprises a laser oscillator... Agent: Eric Robinson

20070148835 - Semiconductor integrated circuit device and fabrication process thereof: A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070148836 - Reduced-resistance finfets and methods of manufacturing the same: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20070148837 - Method of fabricating a multi-cornered film: Embodiments of the present invention describe a method of forming a multi-cornered film. According to the embodiments of the present invention, a photoresist mask is formed on a hard mask film formed on a film. The hard mask film is then patterned in alignment with the photoresist mask to produce... Agent: Intel/blakely

20070148844 - Method for manufacturing semiconductor device: Disclosed is a method of manufacturing a semiconductor device, which includes the steps of: forming a high-voltage well region (e.g., by implanting impurity ions into a semiconductor substrate and then annealing); forming an isolation layer on the semiconductor substrate; implanting impurity ions into the high-voltage well region, thereby forming a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148840 - Method of forming fin transistor: A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG... Agent: Ladas & Parry LLP

20070148839 - Method of manufacturing semiconductor device, semiconductor device and electronic apparatus therefore: A method for manufacturing a semiconductor device includes: forming a lower gate electrode over a substrate; forming a sacrifice film over the substrate such that the lower gate electrode is overlapped with the sacrifice film; forming a semiconductor film over the sacrifice film such that the semiconductor film crosses over... Agent: Oliff & Berridge, PLC

20070148838 - Metal gate cmos with at least a single gate metal and dual gate dielectrics: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate... Agent: Scully Scott Murphy & Presser, PC

20070148841 - Method for forming transistor in semiconductor device: A method for forming a transistor in a semiconductor device with an elongated channel region. The method includes the steps of forming a polysilicon layer on a semiconductor substrate and patterning the polysilicon layer to form a dummy substrate, and forming a gate oxidation layer and a gate electrode on... Agent: Sherr & Nourse, PLLC

20070148842 - Method of manufacturing a transistor: Embodiments relate to a method of manufacturing a transistor having a metal silicide layer. In embodiments, the method may include sequentially forming a gate insulating layer pattern and a gate conductive layer pattern on a semiconductor substrate, forming a first metal silicide layer on the gate conductive layer pattern and... Agent: Sherr & Nourse, PLLC

20070148845 - Non-volatile memory device and method for fabricating the same: A method and non-volatile memory device are provided that are characterized by ion-implantation of impurities in the sidewalls of a first electrode. The inclusion of impurities in the sidewalls eliminates geometric abnormalities, referred to herein as a bird's beak, in the first electrode, which are caused by numerous oxidation processes... Agent: Mayer, Brown, Rowe & Maw LLP

20070148843 - Semiconductor device and method of manufacturing the same: This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148846 - Image sensor and method of manufacturing the same: A CMOS image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes a semiconductor substrate including a plurality of photodiodes and a plurality of transistors, a first interlayer dielectric formed on the semiconductor substrate, a metal wiring and a second interlayer dielectric formed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148849 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; removing the gate oxide layer on the p-type well;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148847 - Method of fabricating cmos image sensor: A method of fabricating a CMOS image sensor is provided. According to an embodiment, a device isolation layer is formed in a semiconductor substrate to define a device isolation region and an active region. A gate insulating layer and a polysilicon layer are formed on the semiconductor substrate. Impurity ions... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148848 - Methods of forming dual gate of semiconductor device: Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a... Agent: Townsend And Townsend And Crew, LLP

20070148850 - Method for forming a dram semiconductor device with a sense amplifier: A method for forming a sense amplifier of a semiconductor device prevents bit lines from being bridged to each other by a stepped portion created on an insulation interlayer due to irregular density of a P-type impurity, which is ion-implanted into an insulation interlayer in a P+ pickup region when... Agent: Ladas & Parry LLP

20070148851 - Method of programming eeprom having single gate structure: A method of programming an EEPROM including a first active region, a second active region and a third active region located separately in a semiconductor substrate, a common floating gate above and intersecting the active regions, first impurity regions located at both sides of the common floating gate in the... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070148852 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a gate oxide layer including an oxide layer containing a large amount of nitrogen on a semiconductor substrate on which an input/output (I/O) region including an NMOS region and a PMOS region are defined,... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148853 - Novel masked nitrogen enhanced gate oxide: A method for fabricating improved integrated circuit devices. The method enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the... Agent: James R. Duzan Trask Britt

20070148854 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device whose gate structure of a transistor other than a memory cell transistor has a same stacked gate structure as the memory cell transistor, the gate structure comprising a semiconductor substrate, a first insulation film provided on the semiconductor substrate, a first conductive film provided on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070148856 - Method of forming pip capacitor: A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor includes the steps of forming a lower electrode of a first polysilicon layer over a semiconductor substrate, forming a dielectric layer over the lower electrode, forming a second polysilicon layer over the dielectric layer, patterning the second polysilicon layer, implanting impurities into... Agent: Sherr & Nourse, PLLC

20070148855 - Phase change memory device and fabricating method therefor: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase... Agent: Morris Manning Martin LLP

20070148857 - Independently controlled, double gate nanowire memory cell with self-aligned contacts: A doubled gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.... Agent: Blakely Sokoloff Taylor & Zafman

20070148858 - Method for forming metal contact in semiconductor device: A method for forming a metal contact in a semiconductor device includes forming bit lines over a substrate defined into a cell region and a peripheral region, forming a first inter-layer dielectric (ILD) layer over the bit lines, forming a first etch stop layer over the first ILD layer, forming... Agent: Blakely Sokoloff Taylor & Zafman

20070148859 - Method for producing a chip card contact zone: A method for producing a contact zone for a chip card has the following steps. A sheet having a first surface and a second surface opposite the first surface. Forming at least one insulating trench, which extends from the first surface to the second surface. A cluster layer is applied... Agent: Dickstein Shapiro LLP

20070148860 - Method for selective epitaxial growth of source/drain areas: One inventive aspect relates to a method of selective epitaxial growth of source/drain (S/D) areas. The method comprises providing a substrate of semiconductor material, the substrate comprising a first substrate area and a second substrate area, the first area comprising at least one gate stack. The method further comprises applying... Agent: Knobbe Martens Olson & Bear LLP

20070148863 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate lines over a substrate, wherein the substrate is defined into a cell region and a peripheral region, forming a gate spacer layer over the gate lines, the gate spacer layer including a buffer... Agent: Blakely Sokoloff Taylor & Zafman

20070148870 - Method for forming common source line in nor-type flash memory device: Disclosed is a method for forming a common source line of a NOR-type flash memory. The method includes the steps of forming a photoresist pattern, which is used for exposing a common source area, on a plurality of stack gates formed on a semiconductor substrate, selectively etching a field oxide... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148866 - Method of manufacturing eeprom device: A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of the semiconductor substrate exposed through the mask pattern; forming... Agent: Sherr & Nourse, PLLC

20070148864 - Method of manufacturing flash memory device: According to yet another embodiment, a method for forming a non-volatile memory device includes etching a substrate to form first and second trenches. The first and second trenches are filled with an insulating material to form first and second isolation structures. A conductive layer is formed over the first and... Agent: Townsend And Townsend And Crew, LLP

20070148865 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device includes forming a first polysilicon layer over a semiconductor substrate to form a floating gate. A tunnel dielectric layer is formed over the first polysilicon layer. A second polysilicon layer and a tungsten silicide layer are formed over the tunnel dielectric film... Agent: Townsend And Townsend And Crew, LLP

20070148861 - Method of manufacturing non-volatile memory: The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure is lower than that of the... Agent: Jianq Chyun Intellectual Property Office

20070148868 - Method of manufacturing non-volatile memory device: A method of manufacturing a non-volatile memory device includes the steps of: defining an active region on a semiconductor substrate; forming a charge storage layer on the active region; forming a first conductive pattern on the charge storage layer, wherein the first conductive pattern has a bottom portion larger in... Agent: Mayer, Brown, Rowe & Maw LLP

20070148869 - Method of manufacturing phase-change memory element: Disclosed is a method of manufacturing a phase-change memory in which the lower electrode of the phase-change memory device is formed using barrier metal for forming a metal interconnection and a via in damascene and dual damascene processes. The method includes the steps of patterning an insulating layer on a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148867 - Nonvolatile memory devices having floating gates and method of fabricating the same: A nonvolatile memory device includes a liner covering a sidewall and bottom of a trench that defines an active field in a substrate and a field isolation film disposed on the liner which fills the trench. The nonvolatile memory device further includes a floating gate disposed on the active field... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070148862 - Phase-change memory layer and method of manufacturing the same and phase-change memory cell: A phase-change memory layer and method for manufacturing the same and a phase-change memory cell are provided. The phase-change memory layer is crystallized by adding one or more heterogeneous crystals that do not react with phase-change materials as the crystal nucleus, so as to reduce the time for transforming to... Agent: Rabin & Berdo, PC

20070148871 - Erasable and programmable read only memory (eprom) cell of an eprom device and method of manufacturing a semiconductor device having the eprom cell: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device... Agent: F. Chau & Associates, LLC

20070148872 - Method of forming floating gate array of flash memory device: The method of forming a floating gate array of a flash memory device includes: (a) forming a plurality of device isolations, which define active device regions, in a semiconductor substrate, the device isolations being formed such that upper portions thereof protrude from a surface of the substrate by a predetermined... Agent: Mayer, Brown, Rowe & Maw LLP

20070148873 - Method of forming transistors with ultra-short gate feature: A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of... Agent: Townsend And Townsend And Crew, LLP

20070148874 - Integrated semiconductor device and method of manufacturing thereof: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type... Agent: Mcdermott Will & Emery LLP

20070148875 - Common drain dual semiconductor chip scale package and method of fabricating same: A common drain dual MOSFET chip scale package and a method of fabricating same are provided. The method of fabricating a plurality of common drain dual MOSFET chip scale packages includes the steps of providing a wafer having a plurality of common drain dual MOSFET devices disposed thereon, insulating a... Agent: Fortune Law Group LLP

20070148876 - Method for fabricating semiconductor device with dual poly-recess gate: A method for fabricating a semiconductor device includes: forming a first polysilicon layer of a first conductive type over a substrate divided into a cell region and a peripheral region, the first polysilicon layer covering the peripheral region and opening predetermined recess portions of the cell region; etching the predetermined... Agent: Blakely Sokoloff Taylor & Zafman

20070148877 - Semiconductor device and method for fabricating the same: A semiconductor device capable of preventing a bridge generation during performing an etching process to form a plurality of gate structures on a substrate divided into an active region and a field region and an electrical short between a contact plug and the individual gate structure in the field region... Agent: Blakely Sokoloff Taylor & Zafman

20070148878 - Method of manufacturing split gate type non-volatile memory device: A method of manufacturing a split gate type non-volatile memory device includes the steps of defining an active region on a semiconductor substrate; forming a pair of first conductive film patterns, each having an electric charge storage layer interposed between the substrate and the first conductive film pattern, on the... Agent: Mayer, Brown, Rowe & Maw LLP

20070148879 - Iii-v compound semiconductor heterostructure mosfet with a high workfunction metal gate electrode and process of making the same: A method of forming a metal-insulator-compound semiconductor structure comprises providing an insulator layer overlying a compound semiconductor substrate, the insulator layer having a surface, and forming a metal layer on the surface of the insulator layer using metal organic chemical vapor deposition.... Agent: Freescale Semiconductor, Inc. Law Department

20070148880 - Method of manufacturing a sonos memory: A method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory is provided herein. In the method, a bottom silicon oxide layer is formed over a substrate. A patterned mask layer having a trench therein is formed over the bottom silicon oxide layer. A charge-trapping layer is formed over the substrate covering the... Agent: Jianq Chyun Intellectual Property Office

20070148881 - Hybrid sti stressor with selective re-oxidation anneal: A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI... Agent: Slater & Matsil, L.L.P.

20070148882 - Method for making pmc type memory cells: This invention relates to a microelectronic device provided with one or several cells or elements comprising at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode, said stack comprising: at least one doped chalcogenide... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070148883 - Method for manufacturing a semiconductor device: Embodiments relate to a method of manufacturing a semiconductor device. According to embodiments, the method may include forming a first and a second insulating layer on a semiconductor substrate of which an active area and an isolation region are defined, forming a first and a second insulating layer pattern by... Agent: Sherr & Nourse, PLLC

20070148884 - Method of forming a recess channel trench pattern, and fabricating a recess channel transistor: A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern.... Agent: Marger Johnson & Mccollom, P.C.

20070148885 - Method of fabricating semiconductor device with dual gate structure: A method for fabricating a semiconductor device with a dual gate structure is provided. The method includes: forming a gate oxide layer over a substrate; forming a gate conductive layer over the gate oxide layer; forming an amorphous carbon layer over the gate conductive layer; forming a photosensitive pattern over... Agent: Townsend And Townsend And Crew, LLP

20070148886 - Method for gate electrode height control: One inventive aspect relates to a method of controlling the gate electrode in a silicidation process. The method comprises applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor... Agent: Knobbe Martens Olson & Bear LLP

20070148887 - Method for manufacturing semiconductor device: Embodiments relate to a method for manufacturing a semiconductor device. According to embodiments, a gate insulating layer and a conductive layer may be formed on a semiconductor substrate. The conductive layer may be selectively etched to form a relatively thick portion of the conductive layer in a gate region and... Agent: Sherr & Nourse, PLLC

20070148888 - System and method for the manufacture of semiconductor devices by the implantation of carbon clusters: A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach:... Agent: Patent Administrator Katten Muchin Rosenman LLP

20070148889 - Method for manufacturing a bipolar transisstor: Disclosed is a method for manufacturing a bipolar transistor. The method includes the steps of forming a well area, which is doped with a first conductive type material, on a semiconductor substrate, forming a base area, which is doped with the first conductive type material, by performing an ion implantation... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148890 - Oxygen enhanced metastable silicon germanium film layer: A method for pseudomorphic growth and integration of a strain-compensated metastable and/or unstable compound base having incorporated oxygen and an electronic device incorporating the base is described. The strain-compensated base is doped by substitutional and/or interstitial placement of a strain-compensating atomic species. The electronic device may be, for example, a... Agent: Schneck & Schneck

20070148891 - Method for manufacturing bipolar transistor: A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148892 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers... Agent: Fish & Richardson P.C.

20070148893 - Method of forming a doped semiconductor portion: A method of forming a doped semiconductor portion includes providing a semiconductor substrate with a surface, and providing protruding portions of a covering layer on the substrate surface, where the portions are arranged in a pattern of lines or segments of lines extending in a first direction. Portions of a... Agent: Edell, Shapiro & Finnan, LLC

20070148894 - Semiconductor device and method for regional stress control: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried... Agent: Freescale Semiconductor, Inc. Law Department

20070148895 - Integrateable capacitors and microcoils and methods of making thereof: Methods for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A method for integrally forming a capacitor and a microcoil on a substrate may involve depositing and patterning a dielectric layer on the substrate, depositing and patterning a sacrificial layer on the substrate,... Agent: Oliff & Berridge, PLC

20070148896 - Memory with memory cells that include a mim type capacitor with a lower electrode made for reduced resistance at an interface with a metal film: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection... Agent: Sughrue Mion, PLLC

20070148897 - Method for fabricating capacitor in semiconductor device: A method for fabricating a capacitor in a semiconductor device is provided. The method includes forming an insulation layer over a substrate; flushing a metal source onto the insulation layer to change a characteristic of a surface of the insulation layer to improve adherence of a metal-based material to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148899 - Capacitor and manufacturing method thereof: A capacitor in a trench having a depth, the trench formed in an area on a silicon substrate; an insulation layer formed on a surface of the trench and the silicon substrate; a first polysilicon layer formed on the insulation layer; a first dielectric layer formed and patterned on the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148898 - Method for forming capacitor: A method for forming a capacitor is provided. In an embodiment of the method, a lower electrode of the capacitor is formed on a semiconductor substrate. An insulating layer and a metal layer are sequentially deposited on the lower electrode of the capacitor, and a photoresist pattern is formed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148900 - Surface-mount capacitor and method of producing the same: A surface-mount capacitor includes a multilayer capacitor structure formed by laminating plate-like capacitor elements each having anode lead portions at opposite ends thereof and a cathode portion at the center, an anode terminal connected to each anode lead portion via a strip-like plate, and a cathode terminal connected to the... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070148901 - Method for manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes the steps of forming a nitride film over a semiconductor substrate, forming at least one trench in the semiconductor substrate and forming an insulation film over the nitride film and in said at least one trench. The method further comprises the steps... Agent: Sherr & Nourse, PLLC

20070148904 - Device and method for controlling high density plasma chemical vapor deposition apparatus: An HDP-CVD apparatus includes a valve assembly, a pump, and a control unit for adjusting the supply of He gas to be within a preset range through control of the valve assembly and the pump so that an actual wafer temperature, which was previously determined, is maintained at a preset... Agent: Sherr & Nourse, PLLC

20070148903 - Method for fabricating sti gap fill oxide layer in semiconductor devices: A method for fabricating an STI gap fill oxide layer in a semiconductor device is provided. The method can include: forming a shallow trench for forming an STI on a semiconductor substrate; forming an STI liner oxide layer in the shallow trench for the STI; depositing an APCVD oxide layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148906 - Method of fabricating a semiconductor device: Embodiments relate to a semiconductor device and a method for fabricating a semiconductor device. In embodiments, the method may include forming a gate dielectric layer on an active region of a semiconductor substrate defined by an isolation region to form a gate conductive layer pattern, etching the isolation region of... Agent: Sherr & Nourse, PLLC

20070148905 - Method of forming a trench isolation layer in a semiconductor device: Embodiments relate to a method of forming a trench isolation layer in a semiconductor device. In embodiments, the method may include sequentially stacking a pad oxide layer and a pad nitride layer having a first thickness on a semiconductor substrate, forming a pad oxide pattern and a pad nitride pattern,... Agent: Sherr & Nourse, PLLC

20070148902 - Semiconductor device: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device, which may reduce damage due to stress of an STI bottom corner during an ion implantation and annealing being subsequent process of an STI in a semiconductor process are provided. According to embodiments, a method may... Agent: Sherr & Nourse, PLLC

20070148907 - Method of forming isolation layer of semiconductor device: There is provided a method of forming an isolation layer which prevents a failure from occurring depending on a difference in the area of the isolation layer during a planarization process of the isolation layer having a shallow trench isolation (STI) structure. The present invention implements a uniform isolation layer... Agent: Mayer, Brown, Rowe & Maw LLP

20070148908 - Method of forming trench isolation layer of semiconductor device: A trench isolation layer has rounded profiles on the top edges of a semiconductor substrate exposed by moats to prevent device characteristics from being degraded. The method of forming the trench isolation layer includes etching a device isolation trench in a semiconductor substrate using a hard mask layer pattern, forming... Agent: Sherr & Nourse, PLLC

20070148909 - Shallow trench isolation region in semiconductor device and method of manufacture: A method of forming a device isolation region in a semiconductor device is capable of completely removing an oxide layer for trench formation in a central region of the semiconductor device without forming a moat in an edge region. The method begins with forming a sacrificial oxide and sacrificial nitride... Agent: Sherr & Nourse, PLLC

20070148912 - Method for manufacturing direct bonded soi wafer and direct bonded soi wafer manufactured by the method: There are provided a method for manufacturing a direct bonded SOI wafer in which the entire buried oxide film layer is covered and not exposed and a direct bonded SOI wafer. This is the improvement of a method for manufacturing a direct bonded SOI wafer comprising the process of (A)... Agent: Reed Smith, LLP Attn: Patent Records Department

20070148910 - Process for simplification of a finishing sequence and structure obtained thereby: The invention relates to a process for the formation of a structure comprising a thin layer made of semiconductor material on a substrate, including the steps of providing a zone of weakness in a donor substrate; bonding the donor substrate to a support substrate; detaching a portion of the donor... Agent: Winston & Strawn LLP Patent Department

20070148911 - Wafer bonding method: A wafer bonding method, comprising steps of: coating a medium layer respectively on the surfaces of two wafers; removing impurities formed on the surface of each medium layer; laminating the two wafers while enabling the surface coated with the medium layer of one of the two wafers to face the... Agent: Bruce H. Troxell

20070148915 - Device and method for cutting an assembly: A method is presented for cutting an assembly that includes two layers of material having a first surface and a second surface. The method includes providing a weakened interface between the two layers that defines an interface ring about the periphery of the assembly, providing a high-pressure zone at the... Agent: Winston & Strawn LLP Patent Department

20070148913 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. In particular, a method for removing unwanted material layers from an edge and lower bevel region of a wafer is provided. The method includes performing a first etch of an edge region of a wafer having material layers formed thereon, coating... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148914 - Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer: A processing time required for regeneration of a layer transferred wafer is reduced and the regeneration cost is lowered, while a removal amount at the regeneration is decreased the number of regeneration times is increased. A main surface of a semiconductor wafer (13) has a main flat portion (13d) and... Agent: Reed Smith, LLP Attn: Patent Records Department

20070148917 - Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer: The regeneration cost is reduced when a layer transferred wafer is to be reused two times or more. Ions are implanted into a semiconductor wafer (13) to form an ion implanted area (13b) inside the semiconductor wafer (13), and a first laminated body (16) in which the wafer (13) is... Agent: Reed Smith, LLP Attn: Patent Records Department

20070148916 - Semiconductor surface protecting sheet and method: Provided are a semiconductor surface protecting method and surface protecting sheet employing a material having adequate conformability for irregularities on semiconductor wafer circuit sides and sufficient rigidity as a support during grinding, and which does not become fluid with repeated temperature increases. Also provided is a surface protecting sheet for... Agent: 3m Innovative Properties Company

20070148918 - Method for fabricating a chip scale package using wafer level processing: Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the... Agent: Trask Britt, P.C./ Micron Technology

20070148920 - Fabrication method and fabrication apparatus of group iii nitride crystal substance: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group... Agent: Mcdermott Will & Emery LLP

20070148919 - Multi-step epitaxial process for depositing si/sige: A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148921 - Mixed orientation semiconductor device and method: A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and... Agent: Slater & Matsil LLP

20070148922 - Method of fabricating semiconductor device: In a manufacturing process of a semiconductor device using a substrate having low heat resistance, such as a glass substrate, there is provided a method of efficiently carrying out crystallization of a semiconductor film and gettering treatment of a catalytic element used for the crystallization by a heating treatment in... Agent: Nixon Peabody, LLP

20070148923 - Nitride semiconductor device and method of manufacturing the same: The present invention provides a nitride semiconductor device. The nitride semiconductor device comprises an n-type nitride semiconductor layer formed on a nitride crystal growth substrate. An active layer is formed on the n-type nitride semiconductor layer. A first p-type nitride semiconductor layer is formed on the active layer. A micro-structured... Agent: Lowe Hauptman Berner, LLP

20070148924 - Mask pattern, method of fabricating thin film transistor, and method of fabricating organic light emitting display device using the same: A method of fabricating a polycrystalline silicon thin film for a thin film transistor (TFT), a mask pattern used for the method, and a method of fabricating a flat panel display device using the method and the mask pattern. In one embodiment, a mask pattern includes a plurality of regions,... Agent: Christie, Parker & Hale, LLP

20070148925 - Laser apparatus, laser annealing method, and manufacture method of a semiconductor device: To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser... Agent: Eric Robinson

20070148927 - Isolation structure of semiconductor device and method for forming the same: Embodiments of an isolation structure and method of forming the same are disclosed, and may include a shallow trench isolation region formed on a semiconductor substrate, and an isolation layer that may include a first oxide layer, a plurality of silicon nitride layers and silicon oxide layers, and a second... Agent: Sherr & Nourse, PLLC

20070148926 - Dual halo implant for improving short channel effect in three-dimensional tri-gate transistors: A method for providing halo implants in a tri-gate structure is described. Implantation is performed at two different angels to assure a halo for the top transistor and a halo for the side transistors.... Agent: Blakely Sokoloff Taylor & Zafman

20070148928 - Apparatus and method for manufacturing semiconductor device: Disclosed is an apparatus for manufacturing a semiconductor device. The apparatus includes a chamber in which a process is performed, a plasma supply supplying plasma above the chamber, a plate for placing a processing target at a lower portion of the chamber, and an ion capturer capturing ions introduced from... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148929 - Method for manufacturing cmos image sensor: A method of manufacturing a CMOS (complementary metal oxide semiconductor) image sensor is provided. The method can include: providing a semiconductor substrate having a PMOS region, and a photodiode region; forming a gate on the semiconductor substrate; implanting a low concentration of n-type impurities only in the NMOS region to... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148930 - Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device: A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. The rich dopant layer created by... Agent: Dinsmore & Shohl LLP

20070148931 - Semiconductor device and method of fabricating the same: The present invention provides a semiconductor device, which comprises a first semiconductor layer of the first conductivity type having a plurality of trenches formed therein. A second semiconductor layer of the second conductivity type composed of an epitaxial layer is buried in the trenches in the first semiconductor layer. The... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070148933 - Nonvolatile memory device and method of fabricating the same: A method of fabricating a phase-change random-access memory (RAM) device includes forming a chalcogenide material on a substrate. A bottom contact is formed under the chalcogenide material, the bottom contact comprising TiAlN. Forming the bottom contact includes performing an atomic layer deposition (ALD) process, the ALD process including introducing an... Agent: Mills & Onello LLP

20070148932 - Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition... Agent: Mueting, Raasch & Gebhardt, P.A.

20070148935 - Implantation of gate regions in semiconductor device fabrication: A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer... Agent: Schmeiser, Olsen & Watts

20070148936 - Manufacturing method of semiconductor device: To provide a manufacturing method of a semiconductor device with a reduced chip area by reducing the size of a pattern for forming an integrated circuit. For example, the size of an IC chip that is provided as an application of IC cards or IC tags can be reduced. The... Agent: Nixon Peabody, LLP

20070148934 - Method for fabricating semiconductor device with bulb shaped recess gate pattern: A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148937 - Semiconductor device and manufacturing method of semiconductor device: Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148938 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device is provided. The method includes: forming an isolation layer over a substrate to define a field region and an active region; forming a step coverage layer over the isolation layer; and forming a plurality of gate lines traversing the field region and the... Agent: Blakely Sokoloff Taylor & Zafman

20070148939 - Low leakage heterojunction vertical transistors and high performance devices thereof: A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source... Agent: Scully Scott Murphy & Presser, PC

20070148940 - Method for manufacturing a semiconductor device: Provided is a method for manufacturing a semiconductor device. In the method, a gate is formed in an active region of a substrate with a gate insulation layer interposed between the gate and the substrate. Spacers are formed on lateral sides of the gate. A first metal layer is deposited... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148943 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. This method includes the step of forming a diffusion barrier film, which is interposed between a silicon film and a metal film and functions to prevent diffusion between the silicon and metal films. The diffusion barrier film is formed of a... Agent: Ladas & Parry LLP

20070148944 - Interconnection of semiconductor device and method for manufacturing the same: A method for manufacturing an interconnection of a semiconductor device is provided. The method can include the steps of: forming an interlayer dielectric layer on a semiconductor substrate; forming a damascene pattern on the interlayer dielectric layer; depositing a seed layer on the interlayer dielectric layer; depositing a metal layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148942 - Method for fabricating contact hole of semiconductor device: A method for forming a contact hole of a semiconductor device includes: forming a lower pattern over a substrate; forming a spin-on-glass (SOG) layer over the lower pattern; performing a first curing process on the SOG layer; forming an opening exposing a portion of the SOG layer; performing a second... Agent: Blakely Sokoloff Taylor & Zafman

20070148945 - Method for forming a fine pattern of a semiconductor device: Embodiments relate to a method for forming a fine pattern of a semiconductor device. According to embodiments, the method for forming a fine pattern of a semiconductor device may include forming a first oxide layer on a semiconductor substrate, forming a photoresist pattern on the first oxide layer, forming a... Agent: Sherr & Nourse, PLLC

20070148941 - Microelectronic component with photo-imageable substrate: Methods for making a microelectronic component including a plurality of conductive posts extending and projecting away from a flexible substrate, wherein at least some of the conductive posts are electrically connected to a plurality of traces exposed on the flexible substrate.... Agent: Tessera Lerner David Et Al.

20070148946 - Multi-layered metal wiring structure of semiconductor device and manufacturing method thereof: A multi-layered metal wiring structure of a semiconductor device includes an interlayer insulating film including an oxide film, a titanium oxide film deposited on the interlayer insulating film, and an aluminum film deposited on the titanium oxide film. The interlayer insulating film includes a FSG film and a silicon oxide... Agent: Mayer, Brown, Rowe & Maw LLP

20070148947 - Semi-conductor device with inductive component and method of making: An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top... Agent: Robert A. Parsons

20070148948 - Image forming system, image forming apparatus and device, and recording medium: An image forming system including a first image forming apparatus and a second image forming apparatus that are connected to each other via a network, the first image forming apparatus, comprising: a transmitter unit transferring reproduced data of data for transfer to the second image forming apparatus via the network;... Agent: Buchanan, Ingersoll & Rooney PC

20070148949 - Nanostructure-based package interconnect: An embodiment of the present invention is an interconnect technique. A nanostructure bump is formed on a die. The nanostructure bump has a template defining nano-sized openings and metallic nano-wires extending from the nano-sized openings. The die is attached to a substrate via the nanostructure bump.... Agent: Blakely Sokoloff Taylor & Zafman

20070148950 - Object and bonding method thereof: A bonding method of an object having at least one pad on a surface of the object includes the steps of: putting a mask on the object, when the mask has at least one pattern corresponding to the pad; and printing to form a solder ball on the pad by... Agent: Birch Stewart Kolasch & Birch

20070148951 - System and method for flip chip substrate pad: According to some embodiments, a method, a system, and an apparatus to provide a flip chip conductive bump pad that has a dome shaped area. In some embodiments, the method includes providing a substrate having a conductive bump pad on a first surface of the substrate and forming a dome... Agent: Buckley, Maschoff & Talwalkar LLC

20070148952 - Conformal electroless deposition of barrier layer materials: Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof,... Agent: Intel Corporation C/o Intellevate, LLC

20070148953 - Method for fabricating semiconductor device and method for fabricating magnetic head: The method comprises the step of forming an interconnection trench 38 in an inter-layer insulation film 34, the step of forming an interconnection layer 44 of Cu as the main material in the interconnection trench 38, and the step of performing nitrogen-two-fluid processing of concurrently spraying pure water with ammonia... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070148955 - Method for forming metal lines in a semiconductor device: A method for forming metal lines in a semiconductor device includes forming a first insulating film having a via hole over a semiconductor substrate with a conductive layer, forming a via metal line for filling the via hole, forming, over the first insulating film, a second insulating film having a... Agent: Sherr & Nourse, PLLC

20070148956 - Method of forming fuse region in semiconductor damascene process: A method of forming a fuse region in a semiconductor damascene process in which a specific layer is formed to prevent corrosion and re-connection of a severed part of the fuse region to prevent malfunction. A first conductive layer is formed over a substrate and an interlayer dielectric layer is... Agent: Sherr & Nourse, PLLC

20070148957 - Method of manufacturing metal insulating layer in semiconductor device: A method of forming a metal insulating layer of a semiconductor device relieves stress due to differential thermal expansion between insulating sub-layers by rounding off sharp edges formed between the sub-layers. A first metal insulating sub-layer is formed over a metal interconnection layer pattern. The first metal insulating sub-layer has... Agent: Sherr & Nourse, PLLC

20070148954 - Method of manufacturing semiconductor device: A method of manufacturing semiconductor devices, including the steps of forming an interlayer insulating layer over a semiconductor substrate in which a predetermined structure including a drain is formed, etching a part of the interlayer insulating layer to form a contact hole, and then forming a first conductive film on... Agent: Marshall, Gerstein & Borun LLP

20070148959 - Method of manufacturing a semiconductor device having a pre-metal dielectric liner: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor device having a pre-metal dielectric liner. In embodiments, method for forming a semiconductor device may include forming a pre-metal dielectric liner, which has a multi-layer structure including a plurality of interfacial surfaces, on an entire surface of... Agent: Sherr & Nourse, PLLC

20070148960 - Semiconductor device and method for manufacturing the same: A method of manufacturing a metal wiring in a semiconductor device includes: forming a via hole by selectively etching an interlayer insulating layer formed on a first metal layer; sequentially forming a first barrier metal layer and a second metal layer on the interlayer insulating layer; etching the first barrier... Agent: Mayer, Brown, Rowe & Maw LLP

20070148958 - Structure to improve adhesion between top cvd low-k dielectric and dielectric capping layer: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion... Agent: Steven Fischman, Scully, Scott, Murphy & Presser

20070148961 - Semiconductor device and method for manufacturing the same: A semiconductor device and method with a dual damascene pattern uses buffer layers to prevent photoresist layer poisoning due to a reaction between an interlayer dielectric and a photoresist layer. Embodiments also relate to reducing the effects of plasma damage occurring during an etching or ashing process.... Agent: Sherr & Nourse, PLLC

20070148964 - Method for forming contact hole in semiconductor device: A method for forming a contact hole in a semiconductor device includes forming gate lines on a substrate, forming a bit line pattern by forming a bit line and a bit line hard mask in sequential order over the substrate, forming an inter-layer insulation layer having a multiple-layer structure including... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148965 - Method and composition for plasma etching of a self-aligned contact opening: A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer with at least one fluorocarbon and ammonia.... Agent: Dickstein Shapiro LLP

20070148963 - Semiconductor devices incorporating carbon nanotubes and composites thereof: Methods of utilizing carbon nanotubes or composites thereof as hole plugs in vias or in contact holes for connecting conductive layers in integrated circuits are disclosed. Integrated circuits and integrated circuit layers formed by the methods are also disclosed.... Agent: Heslin Rothenberg Farley & Mesiti PC

20070148962 - Single, multi-walled, functionalized and doped carbon nanotubes and composites thereof: The present invention relates to single walled and multi-walled carbon nanotubes (CNTs), functionalized CNTs and carbon nanotube composites with controlled properties, to a method for aerosol synthesis of single walled and multi-walled carbon nanotubes, functionalized CNTs and carbon nanotube composites with controlled properties from pre-made catalyst particles and a carbon... Agent: Young & Thompson

20070148967 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148966 - Method of forming an interconnect structure: A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and... Agent: Schmeiser, Olsen & Watts

20070148968 - Method of forming self-aligned double pattern: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the... Agent: Harness, Dickey & Pierce, P.L.C

20070148969 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device including providing a semiconductor substrate including a cell area formed with relatively high device element density and a scribe line area formed with a device element density lower than the device element density of the cell area. An insulating layer is deposited over... Agent: Sherr & Nourse, PLLC

20070148970 - Method of fabricating circuitry without conductive circle: A method of fabricating circuitry without conductive circles has steps of providing a plate with multiple apertures defined therein, the plate and inner walls of the apertures are coated with a copper layer; the copper layers are coated with a photoresist layer, which is then covered with a protective film;... Agent: Patenttm.us

20070148971 - Method of substrate manufacture that decreases the package resistance: A method includes forming a coating on a land contact of a package substrate, the coating including a first material disposed between a first layer and a second layer, each of the first layer and the second layer being made of a second material including gold. An apparatus includes a... Agent: Blakely Sokoloff Taylor & Zafman

20070148972 - Method of repairing seed layer for damascene interconnects: Disclosed is a method of repairing, before embedding a recess with copper, defects of a seed layer formed by sputtering, when forming damascene interconnects. After a copper (silver is also available) nanoparticle-containing sol, e.g., a copper ink is applied onto a substrate, an etch back process for removing the excessive... Agent: Smith, Gambrell & Russell

20070148974 - Hardmask compositions for resist underlayer films: s

20070148973 - Fabrication of semiconductor device for flash memory with increased select gate width: A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size... Agent: Vierra Magen/sandisk Corporation

20070148976 - Method for manufacturing image sensor: A method for manufacturing an image sensor is provided. The method includes forming a metal pad on a pad region of a semiconductor substrate having an active region and the pad region, forming a metal pad opening by forming a passivation layer on an entire surface of the semiconductor substrate... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148975 - Method for realizing a multispacer structure, use of said structure as a mold and circuital architectures obtained from said mold: A method realizes a multispacer structure including an array of spacers having same height. The method includes realizing, on a substrate, a sacrificial layer of a first material; b) realizing, on the sacrificial layer, a sequence of mask spacers obtained by SnPT, which are alternately obtained in at least two... Agent: Seed Intellectual Property Law Group PLLC

20070148977 - Method of forming thin insulating layer in mram device: A method of forming a thin insulating layer in an MRAM device makes it possible to effectively prevent the insulating layer from being locally thinned, creating a short circuit or other defect. The method includes forming lower patterns for the MRAM device on a semiconductor substrate. An insulating layer for... Agent: Sherr & Nourse, PLLC

20070148978 - Slurry compositions, methods of polishing polysilicon layers using the slurry compositions and methods of manufacturing semiconductor devices using the slurry compositions: A slurry composition, a method of polishing polysilicon layers using the slurry composition, and a method of manufacturing a semiconductor device using the same, wherein the slurry composition includes an abrasive in an amount of about 1 to about 20 percent by weight of the slurry composition, a non-ionic surfactant... Agent: Lee & Morse, P.C.

20070148981 - Electronic micromodule and method for manufacturing the same: A method for manufacturing a micromodule comprising an integrated circuit and an antenna coil electrically connected to the integrated circuit. The method includes manufacturing the integrated circuit and first contact pads of the integrated circuit on a first wafer of semiconductor material, making a conductive winding forming a coil and... Agent: Seed Intellectual Property Law Group PLLC

20070148979 - Method for fabricating semiconductor device having top round recess pattern: A method for forming a semiconductor device having a recess pattern with a rounded top corner is provided. The method includes forming an etch mask pattern including a patterned sacrificial layer and a patterned hard mask layer over a substrate; etching predetermined portions of exposed sidewalls of the patterned sacrificial... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148980 - Method for fabricating semiconductor device with bulb-shaped recess gate: A method for fabricating a semiconductor device with a bulb-shaped recess gate pattern is provided. The method includes forming a plurality of oxide layers over a substrate; forming a silicon layer to cover the oxide layers; forming a mask over the silicon layer; etching the silicon layer using the mask... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148982 - Methods of forming semiconductor constructions: The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH2F2. The silicon-containing layer can contain an n-type doped region and a p-type doped region.... Agent: Wells St. John P.s.

20070148983 - Method for manufacturing semiconductor device: Disclosed herein is a method for manufacturing a semiconductor device that includes performing an O2 plasma treatment step after forming a Si-containing photoresist film.... Agent: Marshall, Gerstein & Borun LLP

20070148984 - Method for integrated circuit fabrication using pitch multiplication: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of... Agent: Knobbe Martens Olson & Bear LLP

20070148985 - Method of manufacturing trench structure for device: A porous low-k film, a sacrificial film that can be dissolved in a pure water, an antireflection film and a resist film are successively formed on a dielectric film on a wafer and subsequently exposing the resist film to light in a prescribed pattern and developing the resist film so... Agent: Smith, Gambrell & Russell

20070148986 - Semiconductor device and method for manufacturing same: Embodiments relate to a semiconductor device and a manufacturing method thereof. In embodiments, the semiconductor device may include a semiconductor substrate formed thereon with a first metal line, a PMD (pre metal dielectric) layer formed on the semiconductor substrate and having first and second contact holes, a first metal layer... Agent: Sherr & Nourse, PLLC

20070148987 - Passivation layer for semiconductor device and manufacturing method thereof: Embodiments relate to a passivation layer for a semiconductor device that may be formed in a substrate having a plurality of semiconductor devices. The passivation layer may includes a first passivation layer, a second passivation layer, and a third passivation layer, and the passivation layer may have a laminated triple... Agent: Sherr & Nourse, PLLC

20070148988 - Fabrication method for alignment film: A fabrication method for an alignment film is proposed. A film is deposited on a substrate by an atmosphere plasma in a predetermined direction at a predetermined angle, while moving the substrate and the atmosphere plasma relative to each other. Thereby, a uniform isotropic alignment film with strong anchoring energy... Agent: Birch Stewart Kolasch & Birch

20070148989 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device. A first gate oxide layer is formed on a semiconductor substrate in which a core region and an input/output region are defined. The first gate oxide layer of the core region is selectively removed, and a second gate oxide layer is... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148990 - Methods and apparatus for forming a high dielectric film and the dielectric film formed thereby: A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 and includes... Agent: Mueting, Raasch & Gebhardt, P.A.

20070148991 - Method of fabricating nanodevices: A method of batch fabrication using established photolithographic techniques allowing nanoparticles or nanodevices to be fabricated and mounted into a macroscopic device in a repeatable, reliable manner suitable for large-scale mass production. Nanoparticles can be grown on macroscopic “modules” which can be easily manipulated and shaped to fit standard mounts... Agent: Michael O. Scheinberg

20070141729 - Apparatus and method for controlling plasma density profile: A number of RF power transmission paths are defined to extend from an RF power source through a matching network, through a transmit electrode, through a plasma to a number of return electrodes. A number of tuning elements are respectively disposed within the number of RF power transmission paths. Each... Agent: Martine Penilla & Gencarella, LLP

20070141730 - Substrate processing system, substrate processing method and computer-readable storage medium storing verification program: Disclosed is a method of verifying a recipe execution program. When a computer executes a recipe execution program, the computer sends instructions, which are issued based on a process recipe data defining specific operations to be performed by a substrate processing apparatus, to the substrate processing apparatus. When a computer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070141733 - Laser beam irradiation method and method of manufacturing a thin firm transistor: A laser beam irradiation method that achieves uniform crystallization, even if a film thickness of an a-Si film or the like fluctuates, is provided. The present invention provides a laser beam irradiation method in which a non-single crystal semiconductor film is formed on a substrate having an insulating surface and... Agent: Eric Robinson

20070141731 - Semiconductor memory with redundant replacement for elements posing future operability concern: Future operability predictor testing is incorporated into the fabrication of integrated circuits that utilize redundancy. Select reliability testing can be used to identify circuit elements such as memory cells that fail or become defective over time. Future operability tests and associated stress conditions are then developed for application during the... Agent: Vierra Magen/sandisk Corporation

20070141732 - Structural analysis method of deep trenches: A structural analysis method of deep trenches is provided. A substrate having a plurality of deep trenches is provided. A polishing process is performed on the substrate to form an incline in a partial region of the substrate to expose surface structures at different depths of the deep trenches. Then,... Agent: Birch Stewart Kolasch & Birch

20070141734 - Optical method for measuring thin film growth: A method of determining the rate of change of optical thickness of a thin-film during deposition comprising the steps of illuminating the thin-film with electromagnetic radiation having a range of wavelengths, measuring the transmission spectrum of the thin-film at least twice during the deposition process to determine the wavelength λt... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070141735 - Method of monitoring deposition temperature of a copper seed layer and method of forming a copper layer: A method for monitoring a deposition temperature of a Cu seed layer by measuring an optical reflectivity of the Cu seed layer deposited on a substrate; and estimating the deposition temperature of the Cu seed layer by comparing the measured optical reflectivity with a reference optical reflectivity of a reference... Agent: Sherr & Nourse, PLLC

20070141736 - Field emission device with self-aligned gate electrode structure, and method of manufacturing same: The invention relates to a field emission device, and a method of manufacturing same. The field emission device comprises a gate electrode (140, 340, 440) which is provided with a pattern of electron passing apertures (135, 335, 435). The gate electrode (140, 340, 440) is arranged near particles (110, 310,... Agent: Philips Intellectual Property & Standards

20070141737 - Antireflective coating: Device and method for an antireflective coating to improve image quality in an image display system. A preferred embodiment comprises a first high refractive index layer overlying a reflective surface of an integrated circuit, a first low refractive index layer overlying the first high refractive index layer, a second high... Agent: Texas Instruments Incorporated

20070141738 - Method of manufacturing a collection of separate variable focus lenses: A method of manufacturing a collection of variable focus lenses comprising two electrodes (21, 22) and a fluid chamber filled with two fluids which are separated by a meniscus, wherein the shape of the meniscus is variable under the influence of a voltage, comprises the following steps: providing an electrically... Agent: Philips Intellectual Property & Standards

20070141739 - Method of making light emitting device having a molded encapsulant: Disclosed herein is a method of making a light emitting device comprising an LED and a molded silicon-containing encapsulant. The method includes contacting the LED with a photopolymerizable composition containing a silicon-containing resin having silicon-bonded hydrogen and aliphatic unsaturation and two metal-containing catalysts. One catalyst may be activated by actinic... Agent: 3m Innovative Properties Company

20070141740 - Method for damage avoidance in transferring an ultra-thin layer of crystalline material with high crystalline quality: A method for damage avoidance in transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and transfer of the monocrystalline thin layer with the cleaving controlled... Agent: Freescale Semiconductor, Inc. Law Department

20070141741 - Semiconductor laminated structure and method of manufacturing nitirde semiconductor crystal substrate and nitirde semiconductor device: In a semiconductor laminated structure, a base substrate has a nitride semiconductor crystal plane in an upper surface thereof. A growth blocking film encloses a flow-through pattern which is extended horizontally on the base substrate at a predetermined interval. A nitride semiconductor crystal layer is formed on the base substrate... Agent: Mcdermott Will & Emery LLP

20070141742 - Structure and method for releasing stressy metal films: A method and structure for forming a spring structure that avoids undesirable kinks in the spring is described. The method converts a portion of a release layer such that the converted portion resists etching. The converted portion then serves as an anchor region for a spring structure deposited over the... Agent: Patent Documentation Center

20070141743 - Three dimensional microstructures and methods for making three dimensional microstructures: Systems and methods for depositing a plurality of droplets in a three-dimensional array are disclosed. The array can comprise a first type of droplets disposed to form a support structure and a second type of droplets forming a conductive seed layer on the support structure. A structure material can be... Agent: N. Kenneth Burraston Kirton & Mcconkie

20070141744 - Method of fabricating a low, dark-current germanium-on-silicon pin photo detector: A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an... Agent: Robert D. Varitz

20070141747 - Electronic device fabrication process: A process for fabricating an electronic device including: (a) forming a liquid composition using starting ingredients comprising an organic semiconductor and a stabilizer, wherein the stabilizer comprises a strong electron donor compound or a strong electron acceptor compound, wherein the organic semiconductor exhibits a high oxygen sensitivity in a comparison... Agent: Patent Documentation Center

20070141746 - Methods of nanotube films and articles: Nanotube films and articles and methods of making the same. A conductive article includes an aggregate of nanotube segments which contact other nanotube segments to define a plurality of conductive pathways along the article. Segments may have different lengths and may be shorter than the article. Conductive articles may be... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070141745 - Production method of a capacitor: A method for producing a capacitor having a good capacitance appearance factor and a low ESR comprising, as one electrode (anode), an electric conductor having pores and having formed on the surface thereof a dielectric layer and, as the other electrode (cathode), a semiconductor layer formed on the electric conductor... Agent: Sughrue Mion, PLLC

20070141748 - Extended mainframe designs for semiconductor device manufacturing equipment: In a first aspect, a first mainframe is provided for use during semiconductor device manufacturing. The first mainframe includes (1) a sidewall that defines a central transfer region adapted to house a robot; (2) a plurality of facets formed on the sidewall, each adapted to couple to a process chamber;... Agent: Dugan & Dugan, PC

20070141749 - Die attachment method for led chip and structure thereof: A die attachment method for LED chips and the structure thereof are disclosed. While attaching a LED chip to a substrate, surface of two bonding material is ionized by ultrasonic waves so as to make the attachment of a LED chip to a substrate is under low temperature operating condition... Agent: Rosenberg, Klein & Lee

20070141750 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes a first step of forming solder film on metal posts of a mother chip, a second step of forming solder balls after the first step by printing a solder paste on the mother chip and heating the mother chip so that the... Agent: Mcdermott Will & Emery LLP

20070141751 - Stackable molded packages and methods of making the same: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least... Agent: Freescale Semiconductor, Inc. Law Department

20070141753 - Group iii nitride based compound semiconductor device and producing method for the same: The present invention relates to method for producing a group III nitride based compound semiconductor device, including separating the device into individual chips by means of a dicing blade. A portion of an epitaxial layer where a dicing blade is to be positioned is partially or totally removed through etching,... Agent: Mcginn Intellectual Property Law Group, PLLC

20070141752 - Manufacturing method of semiconductor integrated circuit device: When making thin semiconductor wafer 1, the first crushing layer formed by grinding the back surface of semiconductor wafer 1 with the first and second abrasive which has fixed abrasive is removed. Thereby, the die strength after dividing or mostly dividing semiconductor wafer 1 and making a chip is secured.... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070141754 - Wire bonding system and method of use: A semiconductor package wire bonding system and method of use are provided. The wire bonding system includes a heating block that heats and supports a printed circuit board on which a multi-layered semiconductor chip structure having an overhang is mounted. A support inserted through an opening in the printed circuit... Agent: Marger Johnson & Mccollom, P.C.

20070141756 - Leadframe and method of manufacturing the same: A leadframe is plated with palladium only to a surface of a metal plate on which semiconductors elements are to be mounted and a surface of the metal plate to be placed on a substrate, and is not plated with palladium to lead portions, pad portions, other portions except for... Agent: Kenyon & Kenyon LLP

20070141755 - Ribbon bonding in an electronic package: A flexible conductive ribbon is ultrasonically bonded to the surface of a die and terminals from a lead frame of a package. Multiple ribbons and/or multiple bonded areas provide various benefits, such as high current capability, reduced spreading resistance, reliable bonds due to large contact areas, lower cost and higher... Agent: Macpherson Kwok Chen & Heid LLP

20070141757 - Method of manufacturing flexible wiring substrate and method of manufacturing electronic component mounting structure: A method of manufacturing a flexible wiring substrate of the present invention includes the steps of preparing a tape-like substrate composed of a resin layer and a reinforcing metal layer provided on its lower surface, then forming a via hole whose depth reaches the reinforcing metal layer by processing the... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070141758 - Method of manufacturing mounting substrate: A method for manufacturing a mounting substrate on which a semiconductor chip is mounted includes: forming a wiring section by electrolytic plating on a first face of a supporting substrate which is made of an insulating material, by supplying electric power from a first power supply layer through a via... Agent: Rankin, Hill, Porter & Clark LLP

20070141759 - Method for manufacturing ic-embedded substrate: A method for manufacturing an IC-embedded substrate comprises a first step for encapsulating at least an IC chip having a pad electrode in an insulating layer, a second step for forming a metal layer having at least a first aperture in a location directly above the pad electrode of the... Agent: Young Law Firm, P.C. Alan W. Young

20070141760 - Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film: An electrical device and method of making same is provided wherein a chip or other electrical component is embedded in a substrate. The substrate may be a thermoplastic material capable of deforming around the chip and at least partially encasing the chip when heat and/or pressure is applied to the... Agent: Renner, Otto, Boisselle & Sklar, LLP (avery)

20070141761 - Method for fabricating semiconductor packages, and structure and method for positioning semiconductor components: A method for fabricating semiconductor packages includes the steps of: providing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip (die) disposed thereon, length and width of the substrates are approximately equal to the predefined length and... Agent: Edwards Angell Palmer & Dodge LLP

20070141762 - Deletable nanotube circuit: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.... Agent: Searete LLC Clarence T. Tegreene

20070141765 - Array substrate and liquid crystal display apparatus having the same: In an array substrate and an LCD apparatus having the same, the array substrate includes a signal line, a first insulating layer formed on the signal line, and a pixel electrode formed on the first insulating layer and overlapped with the signal line. The pixel electrode is electrically connected with... Agent: F. Chau & Associates, LLC

20070141763 - Method for manufacturing field effect transistor having channel consisting of silicon fins and silicon body and transistor structure manufactured thereby: Discloses are a method for manufacturing a field effect transistor comprising a channel consisting of silicon fins and a silicon body, in which the silicon fins have an orientation different from the silicon body, as well as a transistor structure manufactured thereby. The method comprises the steps of: (a) forming... Agent: Klaus P. Stoffel Wolff & Samson, PC

20070141764 - Method of patterning multiple-layered resist film and method of manufacturing semiconductor device: A method of patterning a multiple-layered resist film and a method of manufacturing a semiconductor device, which can provide an improved reliability of the semiconductor devices and a reduced operation time for an etch process, are provided. A method of patterning a multiple-layered resist film according to the present invention... Agent: Young & Thompson

20070141766 - Semiconductor circuit device and design method therefor: In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance... Agent: Mcdermott Will & Emery LLP

20070141768 - Method of laser annealing using linear beam having quasi-trapezoidal energy profile for increased depth of focus: A linear pulse laser beam to be applied to an illumination surface is so formed as to have, at the focus, an energy profile in the width direction which satisfies inequalities 0.5L1≦L2≦L1 and 0.5L1≦L3≦L1 where assuming that a maximum energy is 1, L1 is a beam width of two points... Agent: Fish & Richardson P.C.

20070141767 - Thin film transistor and method of fabricating the same: The present invention discloses a thin film transistor and a method of fabricating the same. The thin film transistor includes an insulating substrate; and a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulator, and a source/drain electrode which are formed on the substrate, wherein the gate... Agent: H.c. Park & Associates, PLC

20070141769 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device, including the steps of sequentially forming a tunnel oxide film, a first polysilicon layer, a nitride film, and a hard mask film on a semiconductor substrate, etching the hard mask film, the nitride film, the first polysilicon layer, and a predetermined region... Agent: Marshall, Gerstein & Borun LLP

20070141770 - Semiconductor device having an organic anti-reflective coating (arc) and method therefor: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS... Agent: Freescale Semiconductor, Inc. Law Department

20070141771 - Integrated circuits and methods of forming a field effect transistor: Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and... Agent: Wells St. John P.s.

20070141772 - Semiconductor device, its manufacturing method and electronic apparatus thereof: The present invention proposes a semiconductor device, its manufacturing method and to an electronic apparatus thereof equipped with the semiconductor device where it becomes possible to make a CMOS type solid-state imaging device, an imager area formed with a MOS transistor of an LDD structure without having a metal silicide... Agent: Robert J. Depke Lewis T. Steadman

20070141773 - Structure of semiconductor device and method of fabricating the same: Disclosed are a structure of a semiconductor device and a method of manufacturing the same. The distance between gate electrodes and capacitor upper electrodes is reduced so that, when spacer insulating layers are etched to form sidewall spacers, spacer insulating layers remain between the gate electrodes and the capacitor upper... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070141774 - Method and apparatus for a deposited fill layer: A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070141775 - Modulation of stress in stress film through ion implantation and its application in stress memorization technique: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the... Agent: William Stoffel

20070141776 - Semiconductor device having capacitor and fabricating method thereof: A semiconductor device having a capacitor is provided. The semiconductor device includes a substrate, a capacitor and a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is located in a MOS transistor region of the substrate, and the MOS transistor region has a first bottom diffusion region. The capacitor is located in... Agent: Jianq Chyun Intellectual Property Office

20070141777 - Method of forming a contact using a sacrificial structure: A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over... Agent: Trask Britt, P.C./ Micron Technology

20070141778 - Metal-insulator-metal capacitor: A metal-insulator-metal (MIM) capacitor having a top electrode, a bottom electrode and a capacitor dielectric layer is provided. The top electrode is located over the bottom electrode and the capacitor dielectric layer is disposed between the top and the bottom electrode. The capacitor dielectric layer comprises several titanium oxide (TiO2)... Agent: J.c. Patents, Inc.

20070141779 - Methods for coating and filling high aspect ratio recessed features: The present invention provides methods for conformally or superconformally coating and/or uniformly filling structures with a continuous, conformal layer or superconformal layer. Methods of the present invention improve conformal or superconformal coverage of surfaces and improve fill in recessed features compared to conventional physical deposition and chemical deposition methods, thereby... Agent: Greenlee Winner And Sullivan P C

20070141782 - Method for manufacturing semiconductor memory: A method for manufacturing a semiconductor memory having a memory cell selection transistor and a capacitor, comprises a step of forming a polysilicon plug having a large-diameter portion on a side of the capacitor, a step of forming a hole reaching the large-diameter portion by etching an insulating film formed... Agent: Young & Thompson

20070141781 - Multi-bit non-volatile memory devices and methods of fabricating the same: A multi-bit non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins protruding above the body. A first insulation layer may be formed on the body between the at least one pair of fins. A plurality of pairs of control gate electrodes... Agent: Harness, Dickey & Pierce, P.L.C

20070141780 - Methods of forming flash devices with shared word lines: Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070141783 - Trench field effect transistor and method of making it: A method of manufacturing an insulated gate field effect transistor includes providing a substrate (2) having a low-doped region (4), forming insulated gate trenches (8) and implanting dopants of a first conductivity type at the base of the trenches (8). A body implant is implanted in the low-doped regions between... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070141784 - Transistor structures and methods for making the same: Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO or SnO2. A gate insulator layer comprising a substantially transparent material is located... Agent: Klarquist Sparkman, LLP

20070141785 - Method of forming floating gate array of flash memory device: The method of forming a floating gate array of a flash memory device includes: (a) sequentially forming a tunnel oxide film, a floating gate forming film, a capping oxide film and a first nitride film on a semiconductor substrate with an active device region defined by device isolation films; (b)... Agent: Mayer, Brown, Rowe & Maw LLP

20070141786 - Method of manufacturing non-volatile memory element: A method of manufacturing a non-volatile memory element in the present invention comprises a first step for forming an adhesion layer on an interlayer insulating film so that an electrical connection is established with a lower electrode, a second step for forming a recording layer containing a phase change material... Agent: Mcdermott Will & Emery LLP

20070141787 - Method for manufacturing a vertical-gate mos transistor with countersunk trench-gate: A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from... Agent: Seed Intellectual Property Law Group PLLC

20070141788 - Method for embedding non-volatile memory with logic circuitry: A method for embedding NROM process steps and HV CMOS devices into high-speed logic CMOS process steps, the method including forming isolation areas for NROM and high voltage CMOS elements, forming high thermal drive process elements of the NROM and the HV CMOS elements, forming mid thermal drive process elements... Agent: Empk & Shiloh, LLP

20070141789 - Semiconductor device having a surface conducting channel and method of forming: A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a method of forming... Agent: Marger Johnson & Mccollom/parc

20070141790 - Carbon nanotube energy well (cnew) field effect transistor: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped... Agent: Intel/blakely

20070141791 - Doped structure for finfet devices: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin... Agent: Harrity Snyder, LLP

20070141792 - Integrated circuit structure with improved ldmos design: A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between... Agent: Hiscock & Barclay, LLP

20070141793 - Transistor having a protruded drain: A field effect transistor includes a gate that is formed in a channel region of an active region defined on a substrate. A source is formed at a first surface portion of the active region that is adjacently disposed at a first side face of the gate. A drain is... Agent: Mills & Onello LLP

20070141795 - Method of forming compressive channel layer of pmos device using gate spacer and pmos device having a compressed channel layer: A method of forming a compressive channel layer in a PMOS device and a PMOS device having a compressive channel layer are provided. The method includes (a) forming a buffer oxide layer on a silicon semiconductor substrate having a gate oxide layer and a gate electrode thereon, (b) forming a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070141794 - Radiation hardened isolation structures and fabrication methods: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design... Agent: Campbell Stephenson Ascolese, LLP

20070141796 - Nonvolatile memory device and methods of forming the same: Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The... Agent: Harness, Dickey & Pierce, P.L.C

20070141797 - Semiconductor devices and methods of manufacture thereof: A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed over the workpiece in a second region. The second gate dielectric comprises a different material than the first gate dielectric. A first... Agent: Slater & Matsil LLP

20070141798 - Silicide layers in contacts for high-k/metal gate transistors: A method for forming metal silicide layers in a high-k/metal gate transistor comprises forming a transistor with a sacrificial gate on a substrate, depositing a first ILD layer on the substrate, removing the sacrificial gate to form a gate trench, depositing a high-k dielectric layer within the gate trench, annealing... Agent: Intel Corporation C/o Intellevate, LLC

20070141799 - Memory cell arrays and methods for producing memory cell arrays: A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed... Agent: Slater & Matsil LLP

20070141800 - Thin-film capacitor and method for fabricating the same, electronic device and circuit board: The thin-film capacitor comprises a capacitor part 20 formed over a base substrate 10 and including a first capacitor electrode 14, a capacitor dielectric film 16 formed over the first capacitor electrode 14, and a second capacitor electrode 18 formed over the capacitor dielectric film 16; leading-out electrodes 26a, 26b... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070141801 - Semiconductor devices, cmos image sensors, and methods of manufacturing same: A semiconductor device includes: a trench device isolating region formed in a substrate to define a photodiode active region; a channel stop impurity region formed in the substrate contacting the device isolating region, wherein the channel stop impurity region surrounds a bottom and a sidewall of the device isolating region;... Agent: F. Chau & Associates, LLC

20070141803 - Methods for making substrates and substrates formed therefrom: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the... Agent: Winston & Strawn LLP Patent Department

20070141804 - Method of forming through-wafer interconnects for vertical wafer level packaging: A substrate having target transfer regions thereon is provided. A sacrificial wafer is coated with a polymer layer with low adhesion to metals. A conductive layer is coated on the polymer layer and covered with a photoresist layer which is patterned to provide openings to the conductive layer. Thin film... Agent: Saile Ackerman LLC

20070141802 - Semiconductor on glass insulator made using improved ion implantation process: Methods and apparatus for producing a semiconductor on glass (SOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to multiple ion implantation processes to create an exfoliation layer in the donor semiconductor wafer, wherein at least one of: (i) the type of ion, (ii) the dose, and/or... Agent: Corning Incorporated

20070141805 - Method for bonding plastic micro chip: Disclosed is a method of bonding upper and lower substrates for manufacturing a plastic micro chip comprising the upper substrate, the lower substrate and a sample filling space having a predetermined height for filling a sample between the upper and lower substrates. According to the method, the upper and lower... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20070141806 - Method for producing group iii nitride based compound semiconductor device: The present invention relates to method for producing a group III nitride based compound semiconductor device. A plurality of group III nitride based compound semiconductor layers are epitaxially grown on a first substrate. An electrode is formed on the uppermost layer of the group III nitride based compound semiconductor layers,... Agent: Mcginn Intellectual Property Law Group, PLLC

20070141807 - Method for producing semiconductor device: The present invention contemplates preventing clogging of a dicer for forming separation trenches in a semiconductor wafer, and as well improving the yield of a semiconductor device cut out of the semiconductor wafer. A second adhesive to be charged into spaces contains an epoxy material as a base material. Silica... Agent: Mcginn Intellectual Property Law Group, PLLC

20070141808 - Microelectromechanical system pressure sensor and method for making and using: According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite... Agent: General Electric Company Global Research

20070141809 - Process for the singulation of integrated devices in thin semiconductor chips: A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer partially suspended above a semiconductor substrate and constrained to the substrate by temporary anchorages; dividing the layer into a plurality of portions laterally separated from one another; and removing the temporary anchorages,... Agent: Seed Intellectual Property Law Group PLLC

20070141810 - Wafer dividing method: A method of dividing a wafer having devices which are composed of a laminate formed on the front surface of a substrate, along a plurality of streets for sectioning the devices, comprising: a laminate dividing step for dividing the laminate formed at the streets of the wafer along the streets;... Agent: Smith, Gambrell & Russell

20070141811 - Wafer dividing method: A method of dividing a wafer having devices which are formed in a plurality of areas sectioned by a plurality of dividing lines formed in a lattice pattern on the front surface, into individual devices along the dividing lines, comprising: a deteriorated layer forming step for forming a deteriorated layer... Agent: Smith, Gambrell & Russell

20070141812 - Low temperature doped silicon layer formation: A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with... Agent: Knobbe Martens Olson & Bear LLP

20070141813 - Method of fabricating multi-freestanding gan wafer: A method of fabricating a plurality of freestanding GaN wafers includes mounting a GaN substrate in a reactor, forming a GaN crystal growth layer on the GaN substrate through crystal growth, performing surface processing of the GaN crystal growth layer to form a GaN porous layer having a predetermined thickness... Agent: Stein, Mcewen & Bui, LLP

20070141814 - Process for producing a free-standing iii-n layer, and free-standing iii-n substrate: A process for producing a free-standing III-N layer, where III denotes at least one element from group III of the periodic system, selected from Al, Ga and In, comprises depositing on a Li(Al,Ga)Ox substrate, where x is in a range between 1 and 3 inclusive, at least one first III-N... Agent: Foley And Lardner LLP Suite 500

20070141816 - Method of fabricating semiconductor device: The objective of the invention is to provide a method of fabricating semiconductor device using a laser crystallization method capable of preventing a grain boundary from being formed on the channel-forming region of a TFT and preventing the mobility of the TFT from extremely deteriorating, on-current from decreasing, or off-current... Agent: Eric Robinson

20070141815 - Processing method, processing apparatus, crystallization method and crystallization apparatus using pulsed laser beam: In a laser processing method and a laser processing apparatus which irradiate a processing target body with a laser beam pulse-oscillated from a laser beam source, a processing state is monitored by a photodetector, and the laser beam source is again subjected to oscillation control on the moment when erroneous... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070141817 - Non-thermal annealing of doped semiconductor material: A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a... Agent: Schneck & Schneck

20070141819 - Method for making crystalline composition: A method of making a metal nitride is provided. The method may include introducing a metal in a chamber. A nitrogen-containing material may be flowed into the chamber. Further, a hydrogen halide may be introduced. The nitrogen-containing material may react with the metal in the chamber to form the metal... Agent: General Electric Company Global Research

20070141818 - Method of depositing materials on full face of a wafer: Methods of forming conductive layers over a substrate include contacting a barrier layer with an electrical contact and establishing a relative motion between the electrical contact and the barrier layer for a predetermined period of time, thereby electrodepositing conductive material from a process solution onto the barrier layer. The methods... Agent: Knobbe Martens Olson & Bear LLP

20070141820 - Method of forming gate of semiconductor device: A method of forming a gate of a semiconductor device, including the steps of sequentially forming a tunnel oxide film, a nitride film, a dielectric layer, a polysilicon layer, a metal silicide film, and a hard mask film on a semiconductor substrate; sequentially etching the hard mask film, the metal... Agent: Marshall, Gerstein & Borun LLP

20070141821 - Method of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors: The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain... Agent: Wells St. John P.s.

20070141822 - Multi-step anneal method: A multi-step anneal method is provided. First, a substrate is provided. Then, a dielectric layer comprising a damascene structure is formed over the substrate, and a barrier/seed layer is formed over the damascene structure. Next, a metal layer is formed over the barrier layer, and performing a first anneal step... Agent: Jianq Chyun Intellectual Property Office

20070141823 - Inclusion-free uniform semi-insulating group iii nitride substrates and methods for making same: In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered... Agent: The Eclipse Group

20070141824 - Wafer structure and bumping process: A wafer structure including a semiconductor substrate, elastic elements, under bump metallurgic (UBM) layers and bumps is provided. The semiconductor substrate has an active surface, and it includes pads disposed on the active surface. The elastic elements are disposed on the pads respectively. Each elastic element has an opening, such... Agent: J.c. Patents, Inc.

20070141825 - Method of bonding flying leads: The method of bonding flying leads is capable of efficiently supersonic-bonding the flying leads to pads of a board and improving bonding reliability therebetween. The method comprises the steps of: mechanically processing the board so as to form projections, which act as margins for deformation, in boding faces of the... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070141826 - Filling narrow and high aspect ratio openings using electroless deposition: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. Various processing steps and structures may be utilized in the... Agent: Intel Corporation C/o Intellevate, LLC

20070141827 - Method for forming copper line: Embodiments relate to a method for forming a copper line. According to embodiments, the method may include forming an insulation layer on a semiconductor substrate, forming a copper line pattern on the insulation layer, and forming a copper line; removing a copper oxide layer through a reactive preclean process, the... Agent: Sherr & Nourse, PLLC

20070141828 - Multi-layered structure forming method, method of manufacturing wiring substrate, and method of manufacturing electronic apparatus: There is provided a multi-layered structure forming method comprising: (A) forming a first insulating material layer containing a first photo-curing material on a substrate; (B) semi-hardening the first insulating material layer by radiating light having a first wavelength to the first insulating material layer; (C) forming a conductive material layer... Agent: Oliff & Berridge, PLC

20070141829 - Semiconductive device fabricated using subliming materials to form interlevel dielectrics: The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the hydrocarbon layer [294], and removing the hydrocarbon layer [294] by sublimation.... Agent: Texas Instruments Incorporated

20070141830 - Methods for making integrated-circuit wiring from copper, silver, gold, and other metals: Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance... Agent: Schwegman, Lundberg, Woessner & Kluth. P.A. Attn: Eduardo E. Drake

20070141831 - Semiconductor device with a line and method of fabrication thereof: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070141832 - Integrated circuit insulators and related methods: A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit insulator. The method includes forming an insulating layer using a first structural material upon a substrate, the first structural material having... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070141833 - Method for manufacturing semiconductor device: Provided is a method for manufacturing a semiconductor device. An insulation layer is formed on a bottom structure of a semiconductor substrate. Then, a trench and a via hole are formed by selectively etching the insulation layer, and a copper layer is deposited to fill the via hole and the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070141834 - Local interconnection method and structure for use in semiconductor device: A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on... Agent: Marger Johnson & Mccollom, P.C.

20070141835 - Methods of fabricating interconnects for semiconductor components: In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal... Agent: Wells St. John P.s.

20070141836 - Semiconductor device and method of manufacturing the same: It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070141837 - Contact structure of semiconductor device and method for fabricating the same: A method for fabricating a contact of a semiconductor device includes the steps of forming a dielectric layer having a contact hole on a semiconductor substrate, forming an outgassing barrier layer comprising a poly-silicon layer to cover at least inner walls of the contact hole in order to prevent undesired... Agent: Marshall, Gerstein & Borun LLP

20070141838 - Direct patterning method for manufacturing a metal layer of a semiconductor device: A direct patterning method for manufacturing a metal layer of a semiconductor device is provided. The claimed method reduces the materials and hours required by prior methods such as the thin film depositing method for a substrate, and the photolithographic method for manufacturing a transistor. The preferred embodiment of the... Agent: Rabin & Berdo, P.C.

20070141839 - Method for fabricating fully silicided gate: A method for fabricating a fully silicided gate, including forming a gate dielectric layer on a semiconductor substrate, depositing an amorphous silicon layer on the gate dielectric layer, forming a metallic layer on the amorphous silicon layer, depositing a hard mask on the metallic layer, wherein the amorphous silicon layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070141840 - Nickel silicide including indium and a method of manufacture therefor: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide... Agent: Texas Instruments Incorporated

20070141841 - Method for fabricating a probing pad of an integrated circuit chip: A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film. A portion of the passivation dielectric film... Agent: North America Intellectual Property Corporation

20070141844 - Etch mask and method of forming a magnetic random access memory structure: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070141842 - Method of manufacturing semiconductor device: Disclosed herein is a method of manufacturing a semiconductor device. The method includes forming an etch-stop film on a semiconductor substrate in which a predetermined structure is formed, and then forming an interlayer insulating film. The method also includes etching a predetermined region of the interlayer insulating film, and then... Agent: Marshall, Gerstein & Borun LLP

20070141843 - Substrate peripheral film-removing apparatus and substrate peripheral film-removing method: A substrate peripheral film-removing apparatus which is capable of removing a film from a substrate periphery without complicating the construction of the apparatus. A wafer chamber receives a wafer having an SiO2 film formed on a periphery thereof. In a beveled portion-receiving chamber, film-removing chemical processing is carried out on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070141845 - Apparatus and method for supplying chemicals: A chemical supplying apparatus includes first and second mixing tanks for mixing and supplying chemical slurries used in a semiconductor fabrication process. The slurries are alternately provided from the first and second mixing tanks such that the slurry is continuously available to a precessing apparatus for maximum efficiency. While one... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070141846 - Rapid thermal processing system: Disclosed herein is a rapid thermal processing system. The rapid thermal processing system comprises a chamber having an inner surface with a cross-section in a multi-line shape consisting of a plurality of arcs separated from each other while having the same radius and the center, and a plurality of lines... Agent: Ipla P.A.

20070141847 - Notch stop pulsing process for plasma processing system: A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of... Agent: Ipsg, P.C.

20070141848 - Method for manufacturing high-stability resistors, such as high ohmic poly resistors, integrated on a semiconductor substrate: A method for protecting a circuit component on a semiconductor substrate from a plasma etching or other removal process includes forming a screening layer over an auxiliary layer to conceal at least an area of the auxiliary layer that overlays at least a portion of the circuit component, such as... Agent: Stmicroelectronics, Inc.

20070141849 - Two-fluid nozzle for cleaning substrate and substrate cleaning apparatus: An object of the present is to uniform particle diameters and speeds of liquid droplets in a two-fluid nozzle for cleaning substrates which mixes gas and liquid internally and injects liquid droplets with gas so as to clean a substrate. The two-fluid nozzle for cleaning substrates has a gas supply... Agent: Smith, Gambrell & Russell

20070141850 - Wet treatment of hafnium containing materials: A semiconductor product includes an exposed Hafnium-containing layer. The Hafnium-containing layer is treated with a solution that includes a low ionic strength organic substance.... Agent: Slater & Matsil LLP

20070141854 - Fabrication of nanoporous antireflection film: A nanoporous antireflection coating preparation method. A sol-gel precursor solution containing an organic template is coated onto a substrate. The sol-gel precursor solution containing the organic template is dried into a film. The organic template within the film is then removed to form a nanoporous antireflection coating. In preferred embodiments,... Agent: Birch Stewart Kolasch & Birch

20070141852 - Methods of fabricating isolation regions of semiconductor devices and structures thereof: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. A preferred embodiment includes forming at least one trench in a workpiece, and forming a thin nitride liner over sidewalls and a bottom surface of the at least one trench and over a top surface of the... Agent: Slater & Matsil LLP

20070141853 - Semiconductive device fabricated using a substantially disassociated chlorohydrocarbon: The invention provides a method of fabricating a semiconductive device. In one aspect, the method comprises heating a gas mixture [225] comprising chlorohydrocarbon having a general formula of CxHxClx, wherein x=2, 3, or 4. The chlorohydrocarbon is heated in a first chamber 210 to a first temperature that substantially disassociates... Agent: Texas Instruments Incorporated

20070141851 - System and method of reducing particle contamination of semiconductor substrates: Particle contamination of semiconductor substrates due to particles coming off of wafer boat rods is reduced. A gas flow is established with the boat rods downstream of the substrates, to blow particles from the boat rods away from the substrates. The boat rods can also be placed upstream of the... Agent: Knobbe Martens Olson & Bear LLP

20070141855 - Methods of modifying interlayer adhesion: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and... Agent: Patterson & Sheridan, LLP

20070141856 - Methods and apparatus for incorporating nitrogen in oxide films: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned... Agent: Dugan & Dugan, PC

20070141857 - Target designs and related methods for enhanced cooling and reduced deflection and deformation: A sputtering target is described herein that comprises: a) a target surface component comprising a target material; b) a core backing component having a coupling surface and a back surface, wherein the coupling surface is coupled to the target surface component; and c) at least one surface area feature coupled... Agent: Bingham Mccutchen LLP

20070141858 - Laser anneal of vertically oriented semiconductor structures while maintaining a dopant profile: A method to laser anneal a silicon stack (or a silicon-rich alloy) including a heavily doped region buried beneath an undoped or lightly doped region is disclosed. By F selecting laser energy at a wavelength that tends to be transmitted by crystalline silicon and absorbed by amorphous silicon, crystallization progresses... Agent: Patent Dept., Sandisk 3d LLC(matrix)

20070141859 - Laser processing apparatus and laser processing process: A laser processing process which comprises laser annealing a silicon film 2 μm or less in thickness by irradiating a laser beam 400 nm or less in wavelength and being operated in pulsed mode with a pulse width of 50 nsec or more, and preferably, 100 nsec or more. A... Agent: Eric Robinson

20070134816 - Atomic layer deposition using electron bombardment: Formation of a layer of material on a surface by atomic layer deposition methods and systems includes using electron bombardment of the chemisorbed precursor.... Agent: Mueting, Raasch & Gebhardt, P.A.

20070134817 - Method for manufacturing ferroelectric memory: A method for manufacturing a ferroelectric memory includes the steps of forming a driving transistor on a semiconductor substrate, forming a first interlayer dielectric film that covers the driving transistor on the semiconductor substrate, forming a first hydrogen barrier film on the first interlayer dielectric film, and forming a ferroelectric... Agent: Harness, Dickey & Pierce, P.L.C

20070134818 - Method of reducing the surface roughness of spin coated polymer films: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the... Agent: Intel/blakely

20070134820 - Semiconductor device and manufacturing method of the same: The present invention intends to provide a technique that can improve the capacitance density while securing the withstand voltage of a capacitor element. In order to achieve the above object, the present inventive manufacturing method of a semiconductor device includes forming a metal film on a silicon oxide film, forming... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070134819 - Semiconductor device and method of manufacturing the same: A method of manufacturing a through electrode. While using at least a first conductive film for a gate electrode as a mask, an inner trench and a peripheral trench is formed. The Inner trench is provided for an inner through electrode having a columnar semiconductor. The peripheral trench is provided... Agent: Mcginn Intellectual Property Law Group, PLLC

20070134821 - Cluster tool for advanced front-end processing: Aspects of the invention generally provide an apparatus and method for processing substrates using a multi-chamber processing system that is adapted to process substrates and analyze the results of the processes performed on the substrate. In one aspect of the invention, one or more analysis steps and/or precleaning steps are... Agent: Patterson & Sheridan, LLP

20070134823 - Atomic layer deposition equipment and method: An ALD (Atomic Layer Deposition) apparatus includes a chamber with a sample seated in the reaction space, a supply line providing a raw material gas, an exhaust line through which a reaction gas is exhausted, and a mass analyzer for detecting reaction gases generated within the chamber.... Agent: Sherr & Nourse, PLLC

20070134822 - Process system, process liquid supply method, and process liquid supply program: A process system produces a process liquid of a predetermined concentration in a blending tank by blending solutions respectively supplied from a plurality of solution supply sources, supplies the process liquid to a supply tank to store therein the process liquid, and supplies the process liquid from the supply tank... Agent: Smith, Gambrell & Russell

20070134824 - Probe card and method for manufacturing probe card: A probe card that is manufactured inexpensively. The probe card includes a base plate, a flexible substrate, and a contact probe. The contact probe is a flexible substrate formed from polyimide resin. The contact probe has a plurality of parallel wires. Each wire has a distal end that functions as... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070134825 - Non-mask micro-flow etching process: A non-mask micro-flow etching process, comprising steps of: moving a nozzle capable of inkjetting an etchant over a substrate capable of being dissolved by the etchant; and inkjetting the etchant on the substrate from the nozzle. Means such as polishing and grinding are used to planarize the substrate by removing... Agent: Bruce H. Troxell

20070134827 - Large aluminum nitride crystals with reduced defects and methods of making them: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and... Agent: Goodwin Procter LLP Patent Administrator

20070134826 - Method of manufacturing vertical nitride light emitting device: According to a method of manufacturing a vertical nitride light emitting device, a first conductivity type nitride layer, an active layer and a second conductivity type nitride layer are sequentially grown on a preliminary growth substrate to form a light emission structure. The light emission structure is cut according to... Agent: Mcdermott Will & Emery LLP

20070134828 - Method of producing semiconductor optical element: A production method of a semiconductor optical element includes: a step of forming an alignment mark on a laminate having an active layer comprised of a semiconductor; a step of forming a protective film on the alignment mark and forming an etching mask comprised of the same material as the... Agent: Smith, Gambrell & Russell

20070134829 - Wet etch processing: A method of wet etching produces high-precision microneedle arrays for use in medical applications. The method achieves precise process control over microneedle fabrication, at single wafer or batch-level, using wet etching of silicon with potassium hydroxide (KOH) solution by accurately identifying the etch time endpoint. Hence, microneedles of an exactly... Agent: Jacobson Holman PLLC

20070134830 - Drive film, drive package for organic light emitting diode display, method of manufacturing thereof, and organic light emitting diode display including the same: The present description relates to a drive film, a drive package for an organic light emitting diode display, a method of manufacturing thereof, and an organic light emitting diode display including the same. A drive package for an organic light emitting diode display includes a base film including a central... Agent: Cantor Colburn, LLP

20070134832 - Display device and manufacturing method therefor: An display device having a thin film transistor with improved characteristics comprising a gate conductor including a gate electrode formed on an insulating substrate; a gate insulating layer formed on the gate electrode; a conductive layer comprising a plurality of layers including a source electrode and a drain electrode formed... Agent: Macpherson Kwok Chen & Heid LLP

20070134831 - Programmable mask for fabricating biomolecule array or polymer array, apparatus for fabricating biomolecule array or polymer array including the programmable mask, and method of fabricating biomolecule array or polymer array using the programmable mask: Provided are a programmable mask for promptly fabricating a biomolecule or polymer array having high density, an apparatus for fabricating a biomolecule or polymer array including the mask, and a method of fabricating a biomolecule or polymer array using the programmable mask. The programmable mask for fabricating a biomolecule array... Agent: Ladas & Parry LLP

20070134833 - Semiconductor element and method of making same: A method of making a semiconductor element which has a substrate formed of gallium oxide and a semiconductor layer formed on the substrate. The method has: a first dividing step that the substrate with the semiconductor layer formed thereon is divided into a strip bar along a first cleaved surface... Agent: Mcginn Intellectual Property Law Group, PLLC

20070134834 - Method of manufacturing vertical gallium nitride based light emitting diode: A method of manufacturing a vertical GaN-based LED includes forming a nitride-based buffer layer on a silicon substrate; sequentially forming a p-type GaN layer, an active layer, and an n-type GaN layer on the nitride-based buffer layer; forming an n-electrode on the n-type GaN layer; forming a plating seed layer... Agent: Mcdermott Will & Emery LLP

20070134836 - Solid state image sensing device and manufacturing and driving methods thereof: A solid state image sensing device is composed of a second conductive type well area 33, a photoelectric conversion area 40, a ring shaped gate electrode 35, a transfer gate electrode 41, a second conductive type drain area 38, a second conductive type source area 36, and a first conductive... Agent: Connolly Bove Lodge & Hutz LLP

20070134837 - Surface shape recognition sensor and method of fabricating the same: A structure (113b) which includes an overhang and a support portion supporting substantially the center of the overhang, and in which the area of the support portion is smaller than the area of the overhang in the two-dimensional direction of an upper electrode (1110b) is formed on the upper electrode... Agent: Blakely Sokoloff Taylor & Zafman

20070134835 - Switch using micro electro mechanical system: A MEMS switch is provided with a substrate, a diaphragm which is disposed on the substrate with interposing a cavity therebetween and is elastically deformed by electrostatic force, a switch drive electrode disposed on the substrate, and a switch drive electrode disposed on the diaphragm. Further, a charge accumulation electrode... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070134838 - Semiconductor device with a resonator: The present invention relates to a method of manufacturing a resonator within a semiconductor device, said semiconductor device comprising a substrate, wherein said method comprises the steps of etching a hole in the substrate, creating a first doping zone (Z_DIFF1) for defining a first electrode, partitioning said first electrode into... Agent: Philips Intellectual Property & Standards

20070134839 - Method for making a diaphragm unit of a condenser microphone: A method for making a diaphragm unit of a condenser microphone includes the steps of: forming a liftoff layer on a substrate; forming an insulator diaphragm film on the liftoff layer; and removing the liftoff layer from the diaphragm film and the substrate so as to separate the diaphragm film... Agent: Trop Pruner & Hu, PC

20070134840 - Methods of making energy conversion devices with a substantially contiguous depletion regions: A method of making an energy conversion device includes forming a plurality of pores within a substrate and forming a junction region within each of the plurality of pores. Each of the junction regions has a depletion region and each of the plurality of pores defines an opening size in... Agent: Nixon Peabody LLP - Patent Group

20070134841 - Electrical and thermal contact for use in semiconductor devices and corresponding methods: A contact for use with a memory element of a semiconductor device structure includes a conductive element and a thermal insulator component. The conductive element establishes an electrical path to the memory element, while the thermal insulator component thermally insulates the memory element. The thermal insulator component may reduce an... Agent: Trask Britt, P.C./ Micron Technology

20070134842 - Manufacture method for zno based semiconductor crystal and light emitting device using same: A manufacture method for zinc oxide (ZnO) based semiconductor crystal includes providing a substrate having a Zn polarity plane; and reacting at least zinc (Zn) and oxygen (O) on the Zn polarity plane of said substrate to grow ZnO based semiconductor crystal on the Zn polarity plane of said substrate... Agent: Masao Yoshimura Chen Yoshimura LLP

20070134843 - Semiconductor device and method for fabricating the same: A semiconductor device with a WLP structure that enables the improvement of heat resistance. A dam layer which spreads over a PI film and an Si substrate for a chip is formed between the Si substrate and a sealing resin so as to surround the chip on all sides. A... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070134844 - Process for producing flip-chip type semiconductor device and semiconductor device produced by the process: The invention relates to a process for producing a semiconductor device in which a circuit substrate and a semiconductor chip are connected through a plurality of solder bump electrodes, said process comprising applying a non-cleaning type flux to at least a portion of a bonding pad in the circuit substrate... Agent: Birch Stewart Kolasch & Birch

20070134845 - Method of forming molded resin semiconductor device: A semiconductor chip and a wiring strip are placed on a flat side of a base sheet. The semiconductor chip has parallel first and second surfaces. Electrodes are connected to the first surface. The electrodes all terminate in the plane of the flat side of the base sheet and adhesively... Agent: Young & Thompson

20070134846 - Electronic member fabricating method and ic chip with adhesive material: The present invention includes: an adhesive material attaching process for attaching a wafer to a thermoseffing adhesive material provided on a base film; a dicing-film attaching process for attaching the base film to a dicing film; an IC-chip separating process for cutting the wafer and the thermosetting adhesive material to... Agent: Osha Liang L.L.P.

20070134847 - Die-attaching paste composition and method for hardening the same: Disclosed are a die-attaching paste composition and a method for hardening the same. The present invention provides the die-attaching paste composition applied at a thickness of 200 μm or less on a printed circuit board (PCB), including liquid or solid epoxy, acrylate, a flexing agent, an organic filler and a... Agent: Jones Day

20070134848 - Chip module and method for producing a chip module: A chip module comprises a chip with a chip contact, an insulating structure, which covers the chip and the chip contact at least partly, and a spare contact at an external surface of the insulating structure and a conductive trace for electrically connecting the chip contact to the spare contract.... Agent: Glenn Patent Group

20070134849 - Method for embedding dies: A method of manufacturing a semiconductor device is provided, involving forming a first flexible film on a rigid carrier substrate, attaching a die to the flexible film, so as to leave contacts on the die exposed, forming a wiring layer to contact the contacts of the die, and releasing the... Agent: Knobbe Martens Olson & Bear LLP

20070134850 - Method of manufacturing wiring board: A method of manufacturing a wiring board including: providing a substrate including a base substrate, a conductive film formed on a surface of the base substrate, and a plurality of leads formed on the conductive film; forming a resist layer which partially covers the conductive film in a region between... Agent: Harness, Dickey & Pierce, P.L.C

20070134851 - Space-efficient package for laterally conducting device: Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the... Agent: Townsend And Townsend And Crew, LLP

20070134852 - Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method: Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through... Agent: Ladas & Parry LLP

20070134855 - A stacked non-volatile memory device and methods for fabricating the same: A stacked non-volatile memory device comprises a plurality of bitline and word line layers stacked on top of each other. The bitline layers comprise a plurality of bitlines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured... Agent: Baker & Mckenzie LLP Patent Department

20070134853 - Power semiconductor device having reduced on-resistance and method of manufacturing the same: A power semiconductor device having reduced on-resistance (Ron) and a method of manufacturing the same is provided. The method is provided after forming the gate region for inclinedly implanting the dopant of the first conductivity type into the JFET region above the epitaxial layer. The gate region blocks the dopant... Agent: Birch Stewart Kolasch & Birch

20070134854 - Self-aligned vertical pnp transistor for high performance sige cbicmos process: A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for... Agent: William Stoffel

20070134856 - Method for fabricating reverse-staggered thin film transistor: Disclosed herein is a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor, and more specifically a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor wherein a phosphosilicate-spin-on-glass (P-SOG) is used for a gate insulating film. The method comprises the steps of: forming a buffer layer on... Agent: Morgan & Finnegan, L.L.P.

20070134857 - Method of preparing organic thin film transistor, organic thin film transistor, and organic light-emitting display device including the organic thin film transistor: A method of forming an organic thin film transistor is disclosed. The method includes forming source and drain electrodes on a substrate; forming an insulating layer covering the source and drain electrodes; first surface-treating the insulating layer so that the insulating layer has a hydrophobic surface; forming an opening that... Agent: Knobbe Martens Olson & Bear LLP

20070134858 - Thin film transistor array panel and manufacturing method thereof: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and... Agent: Frank Chau, Esq. F. Chau & Associates, LLP

20070134859 - Strained silicon mos device with box layer between the source and drain regions: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a... Agent: Intel Corporation C/o Intellevate, LLC

20070134860 - Methods and structures for planar and multiple-gate transistors formed on soi: A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness... Agent: Steven H. Slater Slater & Matsil, L.L.P.

20070134863 - Fabrication method for semiconductor device: In one embodiment of the present invention, a fabrication method for a semiconductor device includes a step of forming a gate insulating film on a semiconductor layer, and a step of forming a first gate electrode layer on the gate insulating film. The fabrication method also includes a step of... Agent: Volentine Francos, & Whitt PLLC

20070134864 - Method and structure to create multiple device widths in finfet technology in both bulk and soi: Disclosed is a structure and method for producing a fin-type field effect transistor (FinFET) that has a buried oxide layer over a substrate, at least one first fin structure and at least one second fin structure positioned on the buried oxide layer. First spacers are adjacent the first fin structure... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070134862 - Method of fabricating pseudomorphic high electron mobility transistor: Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer... Agent: Ladas & Parry LLP

20070134861 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece, forming a gate dielectric material over the workpiece, the gate dielectric material comprising an insulator and at least one metal element, and forming a conductive material over the gate dielectric material. The conductive material... Agent: Slater & Matsil LLP

20070134865 - Semiconductor integrated circuit device and its manufacturing method: A semiconductor integrated circuit device has a plurality of rows of pillars, each row being composed of semiconductor pillars and insulator pillars alternately arranged in one direction with no gap therebetween, a plurality of nonvolatile memory elements provided individually in said plurality of semiconductor pillars, said plurality of nonvolatile memory... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070134866 - Method for integrating carbon nanotube with cmos chip into array-type microsensor: The invention disclosed a method for integrating CMOS circuit chips with carbon nanotubes (CNTs) into array-type sensors with signal processors enclosed. The method provides low-temperature and wafer-level fabrication processes including dripped a drop of dispersed CNTs solution on the top of CMOS chip, use micro probe card to contact with... Agent: Jung-tang Huang

20070134867 - Floating gate non-volatile memory and method thereof: A method is provided which includes forming a first gate overlying a major surface of an electronic device substrate and forming a second gate overlying and spaced apart from the first gate. The method further includes forming a charge storage structure horizontally adjacent to, and continuous along, the first gate... Agent: Larson Newman Abel Polansky & White, LLP

20070134868 - Method of fabricating trap type nonvolatile memory device: A method of fabricating a floating trap type nonvolatile memory device includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequentially stacked; thermally annealing the cell gate... Agent: Marger Johnson & Mccollom, P.C.

20070134869 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes etching a predetermined portion of a substrate to form a device isolation region, forming a barrier layer over the substrate and the device isolation region, selectively etching the barrier layer to expose a bottom surface of the device isolation region, etching the... Agent: Blakely Sokoloff Taylor & Zafman

20070134870 - Method to enhance device performance with selective stress relief: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second... Agent: William Stoffel

20070134871 - Memory chip having a memory cell with low-temperature layers in the memory trench and fabrication method: Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor... Agent: Morrison & Foerster LLP

20070134872 - Methods of forming pluralities of capacitors: The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on a substrate. A patterned masking layer is formed over the metal. The patterned masking layer comprises openings therethrough to an outer surface of the metal. Individual of the... Agent: Wells St. John P.s.

20070134873 - Dram cylindrical capacitor and method of fabricating the same: A method of manufacturing dynamic random access memory (DRAM) cylindrical capacitor is provided. A substrate having a polysilicon plug formed therein is provided. A dielectric layer having an opening is disposed on the substrate, wherein the opening exposes the polysilicon plug. Thereafter, an amorphous silicon spacer is formed on the... Agent: Jianq Chyun Intellectual Property Office

20070134874 - Method of forming dielectric layer of flash memory device: A method of manufacturing a flash memory device, wherein according to one embodiment, when a high dielectric material is formed by a remote plasma atomic layer deposition method, first and second dielectric layers are formed by one process at the same time using silicate as the first dielectric layer and... Agent: Marshall, Gerstein & Borun LLP

20070134875 - Multi-level memory cell array with lateral floating spacers: An array of multi-level non-volatile memory transistors features a transistor construction with a conductive polysilicon control gate having opposed sidewalls insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the... Agent: Schneck & Schneck

20070134876 - Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same: A stacked non-volatile memory device comprises a plurality of bitline and wordline layers stacked on top of each other. The bitline layers comprise a plurality of bitlines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for... Agent: Baker & Mckenzie LLP Patent Department

20070134877 - Method of forming gate of flash memory device: A method of forming a gate of a flash memory device, including the steps of (a) forming a tunnel oxide film and a first polysilicon layer in an active region of a semiconductor substrate in which the active region and a field region are defined, and forming an isolation film... Agent: Marshall, Gerstein & Borun LLP

20070134878 - Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same: A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined... Agent: Intel Corporation C/o Intellevate, LLC

20070134880 - Field effect transistors having elevated source/drain regions and methods of manufacturing the same: Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG)... Agent: Myers Bigel Sibley & Sajovec

20070134879 - Semiconductor device and method of manufacturing the same: Provided are a semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a first silicon layer on a semiconductor substrate; patterning the first silicon layer formed on the semiconductor substrate, and exposing a channel region; forming a second silicon layer on the semiconductor... Agent: Ladas & Parry LLP

20070134881 - Image display device manufacturing method and image display: In a method of manufacturing an image display device, a molding die having a plurality of bottomed spacer forming holes is prepared, and the individual spacer forming holes of the molding die are filled with a spacer forming material consisting mainly of glass. The molding die filled with the spacer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070134882 - Method for fabicating trench metal-oxide-semiconductor field effect transistor: A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer on the surface of the epitaxy layer and the inner... Agent: Bacon & Thomas, PLLC

20070134883 - Display device and a method of driving the same: A display device which can suppress an afterimage phenomenon from occurring includes a first plate including a pixel electrode which is disposed in a transmitting region and a first impurity adsorption electrode which is disposed in a light-shielding region and is separated from the pixel electrode, a second plate facing... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070134884 - Isolation method of defining active fins, method of fabricating semiconductor device using the same and semiconductor device fabricated thereby: An isolation method of defining active fins, a method of fabricating a semiconductor device using the same, and a semiconductor device fabricated thereby are provided. The method of fabricating a semiconductor device includes: preparing a semiconductor substrate; and forming a plurality of active fins having major and minor axes and... Agent: Mills & Onello LLP

20070134885 - Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device: A method for manufacturing a semiconductor substrate, including: forming a first semiconductor layer on a semiconductive base; forming a second semiconductor layer, having a smaller etching selection ratio than that of the first semiconductor layer, on the first semiconductor layer; removing part of the first semiconductor layer and the second... Agent: Advantedge Law Group, LLC

20070134886 - Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication: The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench... Agent: Texas Instruments Incorporated

20070134887 - Method of manufacturing a silicon dioxide layer: The invention relates to a of manufacturing a silicon dioxide layer of low roughness, that includes depositing a layer of silicon dioxide over a substrate by a low pressure chemical vapour deposition (LPCVD) process, the deposition process employing simultaneously a flow of tetraethylorthosilicate (TEOS) as the source material for the... Agent: Winston & Strawn LLP Patent Department

20070134888 - Back-gated semiconductor device with a storage layer and methods for forming thereof: A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor... Agent: Freescale Semiconductor, Inc. Law Department

20070134889 - Cutting method for substrate: A cutting method for substrates includes: preparing a substrate having a predetermined circular cut line which is set thereon; chucking the substrate on a surface of a chuck table which is rotatably provided; and cutting the substrate along the predetermined circular cut line of the substrate by rotating a disc-shaped... Agent: Brinks Hofer Gilson & Lione

20070134890 - Cutting method for substrate and cutting apparatus therefor: A cutting method for substrates includes: preparing a substrate which has a predetermined circular cut line set thereon; chucking the substrate on a surface of a chuck table which is rotatably supported around a rotation axis of the chuck table such that the predetermined circular cut line of the substrate... Agent: Brinks Hofer Gilson & Lione

20070134891 - Soi active layer with different surface orientation: A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are... Agent: Freescale Semiconductor, Inc. Law Department

20070134892 - Method of fabricating a poly-silicon thin film: A silicon layer and a heat-retaining layer are formed on a substrate in turn, and a laser beam with a sharp energy density gradient is next utilized to perform a laser heating process for inducing super lateral growth crystallization occurred in part of the Si layer. The heat-retaining layer provides... Agent: Rabin & Berdo, P.C., Suite 500

20070134893 - Method for fabricating image display device: There is provided a method for fabricating an image display device having an active matrix substrate including high-performance transistor circuits operating with high mobility as drive circuits for driving pixel portions which are arranged as a matrix. The portion of a polysilicon film formed in a drive circuit region DAR1... Agent: Stanley P. Fisher Reed Smith LLP

20070134894 - Removable liners for charged particle beam systems: An improved performance charged beam apparatus and method of improving the performance of charged beam apparatus. The apparatus including: a chamber having an interior surface; a pump port for evacuating the chamber; a substrate holder within the chamber; a charged particle beam within the chamber, the charged beam generated by... Agent: Schmeiser, Olsen & Watts

20070134895 - Nitriding method of gate oxide film: A substrate processing method comprises the step of forming an oxide film on a silicon substrate surface, and introducing nitrogen atoms into the oxide film by exposing the oxide film to nitrogen radicals excited in plasma formed by a microwave introduced via a planar antenna.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070134896 - Method for fabricating a micro structure: A method for fabricating a micro structure includes depositing a first layer of a first material over a substrate; patterning a first hard mask over the first layer; depositing a second layer of a second material over the first layer and the first hard mask; patterning a second hard mask... Agent: Fish & Richardson P.C.

20070134897 - Process for producing schottky junction type semiconductor device: A process for producing a Schottky junction type semiconductor device includes the steps of forming a Schottky electrode on a surface of a silicon carbide epitaxial layer, wherein a Schottky electrode made of molybdenum, tungsten, or an alloy thereof is formed on the surface of the silicon carbide epitaxial layer... Agent: The Webb Law Firm, P.C.

20070134898 - Semiconductor device manufacturing method: After a Ni film is deposited on a substrate on which a gate silicon layer is formed, a mask is formed above the gate silicon layer. Then, the Ni film is etched so as to leave a part of the Ni film which is located on the gate silicon layer.... Agent: Mcdermott Will & Emery LLP

20070134899 - Manufacture method for semiconductor device using damascene method: (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c)... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070134900 - Method of improving adhesion strength of low dielectric constant layers: A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally, the method includes forming a dielectric layer overlying the surface region and forming... Agent: Townsend And Townsend And Crew, LLP

20070134901 - Growth of gaas expitaxial layers on si substrate by using a novel gesi buffer layer: Furthermore, a subsequent 0.8 μm Si0.05Ge0.95 layer, and/or optionally a further 0.8 μm Si0.02Ge0.98 layer, are grown. They form strained interfaces of said layers can bend and terminate the propagated upward dislocation very effectively. Therefore, a film of pure Ge is grown on the surface of said epitaixial layers. Finally,... Agent: Bacon & Thomas, PLLC

20070134902 - Patterning of substrates with metal-containing particles: The present invention relates to process for patterning metal-containing particles on or in a substrate. The present invention also relates to a non-etched substrate having metal-containing particles patterned thereon.... Agent: Polsinelli Shalton Flanigan Suelthaus PC

20070134904 - High precision die bonding apparatus: A die bonding apparatus and a bonding method are provided wherein the apparatus comprises a bond head movable between a supply of semiconductor dice and a die bonding site, a pick-up tool attached to the bond head for holding a die to be bonded at the die bonding site and... Agent: Ostrolenk Faber Gerb & Soffen

20070134903 - Integrated circuit having bond pad with improved thermal and mechanical properties: An integrated circuit includes active circuitry and at least one bond pad. The at least one bond pad, in turn, comprises a metallization layer and a capping layer having one or more grooves. The metallization layer is in electrical contact with at least a portion of the active circuitry. In... Agent: Ryan, Mason & Lewis, LLP

20070134905 - Method for mounting bumps on an under metallurgy layer: The present invention relates to a method for mounting bumps on an under bump metallurgy layer (UBM layer). The method comprises (a) providing a wafer, having a plurality of solder pads and a protection layer, and the protection layer covering a surface of the wafer and exposing parts of the... Agent: Volentine Francos, & Whitt PLLC

20070134906 - Pixel detector and method of manufacture and assembly thereof: A detector assembly (50) is formed by integrating the electronic processing circuits on a CMOS wafer by stitching a plurality of reticles of at least two different types so as to form an integrated circuit having an array of electronic processing circuits each having a respective sensor input disposed toward... Agent: Lowe Hauptman Berner, LLP

20070134907 - Substrate processing method and fabrication process of a semiconductor device: A method of fabricating a semiconductor device includes the steps of forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath the interlayer insulation film is exposed at a bottom of the via-hole, forming a conductive barrier film on the interlayer insulation film so... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070134908 - Fabrication of cooling and heat transfer systems by electroforming: A process for the fabrication of a metallic component, such as those used in energy generation and heat transfer systems (e.g., reactor vessels, combustion chambers), in propulsion systems (e.g., rocket engines), and communications (e.g., optical telescopes). The process comprises: providing an object (e.g. a shaped mandrel) having surface; performing a... Agent: NeifeldIPLaw, PC

20070134909 - Method of making a contact in a semiconductor device: To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the... Agent: Slater & Matsil LLP

20070134910 - High-dielectric sheet, a printed circuit board having the high-dielectric sheet and production methods thereof: A high-dielectric sheet for a printed circuit board includes a first electrode, a first sputter film formed on the first electrode, an intermediate layer formed on the first sputter film by calcining a sol-gel film, a second sputter film formed on the intermediate layer, and a second electrode provided on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070134911 - Dual damascene process and method for forming a copper interconnection layer using same: A method for forming a copper interconnection using a dual damascene process includes forming a second insulating layer on a first insulating layer, the first insulating layer including a lower metal interconnection layer formed therein; forming a photoresist film pattern on the second insulating layer; forming a dry film resist... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070134912 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device capable of preventing a device failure is provided. The method includes: forming an insulating layer with a contact hole on a semiconductor substrate; forming a seed layer on the contact hole through electroless plating process; and forming a metal interconnection in the contact... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070134913 - Method to eliminate cu dislocation for reliability and yield: Embodiments in accordance with the present invention provide methods of forming a metal interconnect structure which avoid defects arising from copper migration. In accordance with particular embodiments, an electroplated copper feature is subjected to a brief thermal anneal prior to chemical mechanical polishing and subsequent formation of an overlying barrier... Agent: Townsend And Townsend And Crew, LLP

20070134914 - Semiconductor memory device and method of fabricating the same: A semiconductor memory device and a method of fabricating the same are disclosed. The semiconductor memory device may include a conductive layer doped with impurities, a non-conductive layer on the conductive layer and undoped with impurities, an interlayer insulating film on the non-conductive layer and having a contact hole for... Agent: Harness, Dickey & Pierce, P.L.C

20070134915 - Method of fabricating a metal line in a semiconductor device: A method for forming a metal line of a semiconductor device may include cleaning a via and/or a trench with B2H6 gas to remove Fluorine. Cleaning step may be performed at a temperature between approximately 100° C. and approximately 500° C.... Agent: Sherr & Nourse, PLLC

20070134916 - Antireflection film composition, patterning process and substrate using the same: There is disclosed an antireflection film composition for forming an intermediate resist film of a multilayer resist film used in lithography comprising: at least a polymer obtained by reacting a chelating agent with a polymer having a repeating unit represented by the following general formula (1); an organic solvent; and... Agent: Oliff & Berridge, PLC

20070134918 - Bi-layer etch stop process for defect reduction and via stress migration improvement: A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer... Agent: Texas Instruments Incorporated

20070134917 - Partial-via-first dual-damascene process with tri-layer resist approach: A partial-via-first dual-damascene method using a tri-layer resist method forms a first via hole through partial thickness of a dielectric layer, and forms a tri-layer resist structure on the dielectric layer to fill the first via hole with the bottom photoresist layer. A dry development process is performed to transfer... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070134919 - Film forming method and apparatus: A film forming method, for depositing a thin film on a surface of a substrate mounted on a mounting table disposed in a vacuum processing chamber, includes an adsorption process for adsorbing a film forming material on the substrate by introducing a source gas into the processing chamber; and a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070134920 - Cu wiring formation method: A Cu wiring formation method comprises the steps of: forming a Cu film on a wafer by plating; subjecting the Cu film to anticorrosive treatment on the surface thereof after the plating; and annealing the Cu film after the anticorrosive treatment.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070134921 - Method of forming a semiconductor device having dummy features: A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near... Agent: Freescale Semiconductor, Inc. Law Department

20070134922 - Plasma etching method: An etching technique capable of applying etching at high selectivity to a transition metal element-containing electrode material layer which is formed on or above a dielectric material layer made of a high-dielectric-constant or “high-k” insulator is provided. To this end, place a workpiece on a lower electrode located within a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070134923 - Method to form topography in a deposited layer above a substrate: In the present invention a dummy structure is formed in a first deposited layer in order to create topography, generally a raised area, in a deposited layer formed above and later than the first deposited layer. This topography may be advantageous in later steps. In one embodiment, transferred topography allows... Agent: Patent Dept., Sandisk 3d LLC(matrix)

20070134924 - Semiconductor device fabrication method: The semiconductor device fabrication method comprises the step of forming a first insulation film 48 on a semiconductor substrate 10 and a ferroelectric capacitor 42; the step of forming first interconnections 56a-56c; the step of forming a second insulation film 60; the step of planarizing the surface of the second... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070134925 - Package using array capacitor core: An embodiment of the present invention is a technique to fabricate a package substrate. The package substrate includes top substrate layers, an array capacitor, and bottom substrate layers. The top substrate layers embed micro-vias. The micro-vias have a micro-via area and provide electrical connections between the top substrate layers. The... Agent: Blakely Sokoloff Taylor & Zafman

20070134926 - Method of etching for multi-layered structure of semiconductors in groups iii-v and method for manufacturing vertical cavity surface emitting laser device: Provided are an etching method for a multi-layered structure of semiconductors in groups III-V and a method of manufacturing a VCSEL using the etching method. According to the etching method, a stacked structure including a first semiconductor layer and a second semiconductor layer is exposed to a plasma of a... Agent: Ladas & Parry LLP

20070134927 - Method for removing residues formed during the manufacture of mems devices: A method of removing residues from an integrated device, in particular residues resulting from processing in HF vapor, is disclosed wherein the fabricated device is exposed to dry water vapor for a period of time sufficient to dissolve the residues in the dry water vapor.... Agent: Marks & Clerk

20070134928 - Silicon wet etching method using parylene mask and method of manufacturing nozzle plate of inkjet printhead using the same: A silicon wet etching method to form at least two elements having different shapes in a silicon substrate using at least two wet etching processes includes forming a first etch mask made of parylene on a surface of the silicon substrate, forming a first element in the substrate by wet... Agent: Stanzione & Kim, LLP

20070134929 - Etching method and etching apparatus: While a semiconductor substrate having a metal film formed thereover by electrolytic plating is rotated, an etching solution for the metal film is supplied to the peripheral portion of the metal film at a first flow rate and then the etching solution is continuously supplied at a second flow rate,... Agent: Mcdermott Will & Emery LLP

20070134931 - Lanthanide yttrium aluminum oxide dielectric films: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070134932 - Methods of forming metal layers in the fabrication of semiconductor devices: A metal deposition processing apparatus includes a first processing chamber configured for holding a semiconductor substrate therein. A second processing chamber is configured for holding the semiconductor substrate therein and for forming an upper metal layer thereon. A transfer chamber is connected to the first processing chamber and the second... Agent: Myers Bigel Sibley & Sajovec

20070134930 - Micro and nano scale fabrication and manufacture by spatially selective deposition: A method of fabrication or manufacture at micrometer and nanometer scale by spatially selective deposition of chemical substances so as to form a solid phase array on a substrate (10) which includes the steps of defining a region (15) on the substrate by forming an electrostatic charge on that region... Agent: Brinks Hofer Gilson & Lione One Indian Square

20070134933 - Semiconductor substrate surface protection method: A convenient method of depositing chemical protection material on the surface of a semiconductor substrate whereby deposition of contaminating substances after a clean surface has been obtained can be prevented and maintaining of this surface performed includes a process of depositing a high molecular straight-chain organic compound 3 onto a... Agent: Rabin & Berdo, PC

20070134934 - Methods of forming capacitor constructions: The invention includes atomic layer deposition (ALD) methods for forming crystalline materials. The crystalline materials can have a first atomic arrangement within one layer, and a second atomic arrangement within another layer; with the first and second atomic arrangements having different crystallographic orientations relative to one another. Alternatively, or additionally,... Agent: Wells St. John P.s.

20070134935 - Ultraviolet assisted pore sealing of porous low k dielectric films: Processes for sealing porous low k dielectric film generally comprises exposing the porous surface of the porous low k dielectric film to ultraviolet (UV) radiation at intensities, times, wavelengths and in an atmosphere effective to seal the porous dielectric surface by means of carbonization, oxidation, and/or film densification. The surface... Agent: Cantor Colburn LLP

20070134936 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes: providing a substrate structure in which a plurality of gate lines are already formed; forming a capping layer over the substrate structure; oxidizing the capping layer; and forming an insulation layer over the oxidized capping layer. The capping layer may include a... Agent: Blakely Sokoloff Taylor & Zafman

20070134937 - Inhibiting underfill flow using nanoparticles: A method and apparatus for inhibiting the flow of a flowable adhesive material disposed adjacent to a substrate. A chip component is disposed adjacent to a substrate and a plurality of nanoparticles are disposed and cured adjacent to the substrate and proximate to the chip component. The nanoparticles possess surface... Agent: Intel Corporation C/o Intellevate, LLC

20070134939 - Fabrication of enclosed nanochannels using silica nanoparticles: In accordance with the invention, there is a method of forming a nanochannel including depositing a photosensitive film stack over a substrate and forming a pattern on the film stack using interferometric lithography. The method can further include depositing a plurality of silica nanoparticles to form a structure over the... Agent: Mh2 Technology Law Group

20070134938 - Plasma processing method, storage medium storing program for implementing the method, and plasma processing apparatus: A plasma processing method, which enables the etching controllability for a high-dielectric-constant insulating film to be improved. A substrate having a high-dielectric-constant gate insulating film and a hard mask formed thereon is subjected to etching processing using a plasma of a processing gas containing a noble gas and a reducing... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070134940 - Substrate processing method, photomask manufacturing method, photomask, and device manufacturing method: A device linewidth characteristic is predicted based on a sharp-edged feature of a projected image of a predetermined pattern (steps 104 to 110), and an exposure condition of the pattern is adjusted based on the device linewidth characteristic that has been predicted (step 112). Then, exposure is performed under the... Agent: Oliff & Berridge, PLC

20070134941 - Structure and method to prevent charge damage from e-beam curing process: An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor... Agent: William Stoffel

20070134942 - Hafnium tantalum titanium oxide films: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070134943 - Subtractive - additive edge defined lithography: A subtractive-additive, differential lithography technique capable of generating sub-half micron geometries using a larger feature parent mask is described. The basic technique is defect tolerant with respect to electrical shorting, can fabricate T-shaped conductors of optimum geometry to minimize electrical RC time constant, and can be extended to very small,... Agent: Lawrence M. Nawrocki

20070128735 - Method of fabrication of re-ba-cu-o-based oxide superconductor: A method of fabrication of an RE-Ba-Cu—O-based oxide superconductor, characterized by using an RE-Ba-O-based compound (RE being one type or two types or more of rare earth elements) and a Ba-Cu-O-based material for liquid phase as a starting material, melting the material for liquid phase, then growing the crystal.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070128736 - Multi-metal-oxide high-k gate dielectrics: A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in... Agent: Slater & Matsil, L.L.P.

20070128737 - Microelectronic devices and methods for packaging microelectronic devices: Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality... Agent: Perkins Coie LLP Patent-sea

20070128738 - Pattern formed body and method for manufacturing same: A main object of the present invention is to provide a high quality pattern formed body, wherein only the target region is made liquid repellent with a high precision at the time of forming a pattern made of a lyophilic region and a liquid repellent region by use of plasma... Agent: Seyfarth Shaw LLP

20070128739 - Method for making tools for micro replication: A method includes electro-mechanical engraving a pattern of cavities with well defined shapes in a surface. The surface is configured to micro replicate according to the pattern. The surface may be a pattern roller. The cavities may have complex cross sections and may be cut by multiple cutters. The molding... Agent: Andrew J. Anderson Patent Legal Staff

20070128740 - Polysilicon conductor width measurement for 3-dimensional fets: An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070128742 - Method of forming silicon-on-insulator (soi) semiconductor substrate and soi semiconductor substrate formed thereby: A method of forming a silicon-on-insulator (SOI) semiconductor substrate includes implanting hydrogen ions into a support substrate to form a microbubble layer apart from a surface of the support substrate, forming an SOI layer on the microbubble layer, forming a diffusion barrier layer over the SOI layer, forming a buried... Agent: Frank Chau, Esq. F. Chau & Associates, LLP

20070128741 - System and method for using a split capacitive barrier edge sensor: A plurality of conductive members is disposed on an edge of a moveable barrier. The edge has a width and each of the conductive members is disposed along a portion of the width. A controller is coupled to each of the plurality of conductive members and is programmed to determine... Agent: Fitch Even Tabin And Flannery

20070128743 - Process of producing group iii nitride based reflectors: To solve the existing problems in distributed Bragg reflectors (DBR) used in the prior art, the present invention provides a fabrication method of group III nitride based distributed Bragg reflectors (DBR) for vertical cavity surface emitting lasers (VCSELs), which suppresses the generation of cracks, and a distributed Bragg reflector with... Agent: Bucknam And Archer

20070128746 - Group iii nitride crystal and manufacturing method thereof: A group III nitride crystal containing therein an alkali metal element comprises a base body, a first group III nitride crystal formed such that at least a part thereof makes a contact with the base body, the first group III nitride crystal deflecting threading dislocations in a direction different from... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070128747 - Method for manufacturing semiconductor device: First semiconductor integrated circuits and second semiconductor integrated circuits arranged over a first substrate so that each of the second semiconductor integrated circuits is adjacent to one of the first semiconductor integrated circuits are transferred to additional substrates through multiple transfer operations. After the first semiconductor integrated circuits and the... Agent: Nixon Peabody, LLP

20070128745 - Phosphor deposition method and apparatus for making light emitting diodes: A phosphor deposition process and apparatus that enables an efficient, consistent, and flexible white light LED light engine by spraying a conformal coating of phosphor matrix onto an array of LEDs to achieve high color uniformity, consistency, and efficiency. A predetermined ratio of one or more phosphor powders are mixed... Agent: Francis J. Caufield

20070128744 - Self-assembly of molecules and nanotubes and/or nanowires in nanocell computing devices, and methods for programming same: An assembly of a NanoCell comprising a disordered array of metallic islands interlinked with molecules between metallic input/output leads and with disordered arrays of molecules and Au islands is disclosed. The NanoCell may function both as a memory device that is programmable post-fabrication. The assembled NanoCells exhibit reproducible switching behavior... Agent: Winstead Sechrest & Minick P.C.

20070128748 - Microreplication of transitory-image relief pattern based optically variable devices: The invention concerns a method for the replication by hot-embossing, hot-stamping or plastic injection moulding of an optically variable transitory image relief pattern characterized by the use of a Silicon origination shim fabricated through a micromachining process. The invention also comprises objects and structures obtained according to said method.... Agent: Nixon & Vanderhye, PC

20070128749 - Multicore microstructured optical fibers for imaging: The present invention relates to the design and manufacture of microstructured optical fibres. The invention has particular application in the manufacture of microstructured optical fibres for imaging purposes such as, for example, endoscopy, ear-implants, and chip-to-chip interconnects. A first aspect of the invention provides a method of producing a microstructured... Agent: Miller, Matthias & Hull

20070128750 - Method for manufacturing high efficiency light-emitting diodes: A method for manufacturing a light-emitting device comprising the steps of cutting a light-emitting unit by a laser beam, and cleaning the light-emitting unit by an acid solution to remove by-products resulted from the laser cutting.... Agent: Bacon & Thomas, PLLC

20070128751 - Display device having uniform brightness: A display device having a uniform brightness and control method thereof are provided, which includes a circuit board having a light emitting diode mounting area, a light source unit comprising a plurality of light emitting diodes mounted to the light emitting diode mounting area so that light emitting characteristics can... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070128752 - Method of fabricating t-gate: A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating... Agent: Ladas & Parry LLP

20070128753 - Nitride-based semiconductor substrate and semiconductor device: A nitride-based semiconductor substrate has a diameter of 25 mm or more, a thickness of 250 micrometers or more, a n-type carrier concentration of 1.2×1018 cm−3 or more and 3×1019 cm−3 or less, and a thermal conductivity of 1.2 W/cmK or more and 3.5 W/cmK or less. Alternatively, the substrate... Agent: Mcginn Intellectual Property Law Group, PLLC

20070128755 - Micronozzle plate and manufacturing method: In the manufacture of at least one passage in a silicon wafer, in a first method step, starting from a first side of the wafer, a first recess is produced in the wafer, and in a second method step, starting from a second side of the wafer, a second recess... Agent: Kenyon & Kenyon LLP

20070128754 - Sensor component and panel used for the production thereof: A sensor component and a panel used for the production thereof is disclosed. The sensor component has, in addition to a sensor chip with a sensor region, a rear side and passive components. These are embedded jointly in a plastics composition, in such a way that their respective electrodes can... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070128756 - Method and apparatus for determining density of metal-inclusive components: A density evaluator for a metal-inclusive component includes a simulator and a meter. The simulator includes a receiving portion for receiving at least a portion of a metal-inclusive component. The meter is operatively connected with the simulator. The meter obtains an inductance value associated with the metal-inclusive component and the... Agent: Dykema Gossett PLLC

20070128757 - Method for forming comb electrodes using self-alignment etching: A method of forming comb electrodes using self alignment etching is provided. A method of forming a stationary comb electrode and a movable comb electrode in first and second silicon layers of a SOI (Silicon-on-Insulator) substrate, respectively, using etching. The method involves sequentially etching the first silicon layer, the insulating... Agent: Sughrue Mion, PLLC

20070128758 - Semiconductor device and method for fabricating the same: A semiconductor device has, on a single substrate, a semiconductor circuit portion and a hollow capacitor portion including a pair of counter electrodes and a hollow part located between the counter electrodes. The hollow part of the hollow capacitor portion is surrounded by an insulating film, and a through hole... Agent: Mcdermott Will & Emery LLP

20070128759 - Plasma discharge method and structure for verifying a hermetical seal: A method and structure use characteristics of a plasma discharge for verifying a hermetic seal. The plasma discharge is created in a hermetically sealed cavity by a pair of spaced electrodes that extend from tips inside the hermetically sealed cavity to contacts outside the sealed cavity. An electrical bias is... Agent: Delphi Technologies, Inc.

20070128760 - Process-variation tolerant diode, standard cells including the same, tags and sensors containing the same, and methods for manufacturing the same: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070128761 - Manufacturing method of solar cell element: A manufacturing method includes the steps of disposing a base substance for a solar cell element inside a first chamber and then supplying a first gas to etch one principal surface of the base substance, thereby roughening the one principal surface while attaching an etch residue thereto; and disposing the... Agent: Hogan & Hartson L.L.P.

20070128762 - Growing crystaline structures on demand: An apparatus comprising a substrate having a surface with at least one crystallization nucleation site located thereon. The apparatus further comprises a second substrate having a second surface. The second surface is configured to maintain a crystallization starting material in an amorphous state or an initial crystalline state. The crystallization... Agent: Hitt Gaines, PC Lucent Technologies Inc.

20070128763 - Method for forming an organic semiconductor layer, organic semiconductor structure and organic semiconductor apparatus: This invention is directed to the provision of a method for organic semiconductor layer formation that can easily form a uniform thin film, by coating, which has good charge mobility and a high level of alignment. The method for organic semiconductor layer formation is characterized by comprising the steps of:... Agent: Burr & Brown

20070128764 - Organic semiconductor material, organic semiconductor structure and organic semiconductor apparatus: i

20070128765 - Encapsulation of electroluminescent devices with shaped spacers: A method of encapsulating a device is disclosed. Spacer particles are randomly located in a device region to prevent a cap mounted on the substrate from contacting the active components when pressure is applied to the cap, thereby protecting the active components from damage. The spacer particles comprise a base... Agent: Fish & Richardson P.C.

20070128766 - Method of making exposed pad ball grid array package: A method of making an exposed-pad ball-grid array package (11) includes applying a conductive sheet (16) to an adhesive tape (18). Stamping the conductive sheet (16) to form a die pad (24) and separating the remainder (26) of the sheet from the adhesive tape (18) so that only the die... Agent: Freescale Semiconductor, Inc. Law Department

20070128767 - Wafer dividing method: A method of dividing a wafer having devices formed in a plurality of areas sectioned by a plurality of dividing lines, into individual chips along the dividing lines, comprising a deteriorated layer forming step for forming a deteriorated layer by applying a laser beam of a wavelength having permeability for... Agent: Smith, Gambrell & Russell

20070128768 - Embedded heat spreader: An embedded heat spreader includes a semiconductor die, an elastomer layer attached to the die, a tape lead attached to the elastomer, a portion of the tape lead exposed through the elastomer to connect with the die, a polymer resin attached to the tape lead, and a thermally conductive substrate... Agent: Marger Johnson & Mccollom, P.C.

20070128769 - Semiconductor device and manufacturing method thereof: A technology for easily forming a multi-layer wiring structure that is fine and reliable. In the multi-layer wiring structure, the lower-layer wiring and the upper-layer wiring that are formed to sandwich an insulating layer are electrically connected to each other in a projection formed in the lower-layer wiring. The projection... Agent: Eric Robinson

20070128770 - Microelectronic component assemblies having lead frames adapted to reduce package bow: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, the invention provides a microelectronic component assembly that includes spaced-apart first and second lead frame members. A packaged element is disposed between the lead frame members and attached thereto only... Agent: Perkins Coie LLP Patent-sea

20070128771 - Method and structure for forming an integrated spatial light modulator: A method of fabricating an integrated spatial light modulator. The method includes providing a first substrate including a bonding surface and processing a device substrate to form at least an electrode layer. The method also includes depositing a first portion of a multi-layer standoff layer on the electrode layer, depositing... Agent: Townsend And Townsend And Crew, LLP

20070128772 - Metal-base circuit board and its manufacturing method: A metal base circuit board to be used for a hybrid integrated circuit, including circuits provided on a metal plate via an insulating layer, a power semiconductor mounted on the circuit, and a control semiconductor to control the power semiconductor, provided on the circuit. A low capacitance portion is embedded... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070128773 - Forming a thin film thermoelectric cooler and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second plurality of openings substantially adjacent to the first plurality of... Agent: Intel Corporation C/o Intellevate, LLC

20070128776 - Isolated fully depleted silicon-on-insulator regions by selective etch: The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface... Agent: Scully, Scott, Murphy & Presser, P.C.

20070128774 - Manufacturing method of semiconductor device: A manufacturing method of a highly reliable semiconductor with a waterproof property. The method includes the steps of: sequentially forming a peeling layer, an inorganic insulating layer, and an element formation layer including an organic compound layer, over a substrate; separating the peeling layer and the inorganic insulating layer from... Agent: Fish & Richardson P.C.

20070128775 - Method of manufacturing a semiconductor device having a tungsten carbon nitride layer: A method of manufacturing a gate electrode of a MOS transistor including a tungsten carbon nitride layer is disclosed. After a high dielectric layer is formed on a substrate, a source gas including tungsten amine derivative flows onto the high dielectric layer. A tungsten carbon nitride layer is formed on... Agent: Mills & Onello LLP

20070128777 - Poly-si thin film transistor and organic light-emitting display having the same: A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and... Agent: Cantor Colburn, LLP

20070128778 - Nonvolatile semiconductor memory and manufacturing method thereof: A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070128779 - Semiconductor devices and methods of fabricating the same: Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.... Agent: Mills & Onello LLP

20070128780 - Method and system for deposition tuning in an epitaxial film growth apparatus: A method of calculating a process parameter for a deposition of an epitaxial layer on a substrate. The method includes the steps of measuring an effect of the process parameter on a thickness of the epitaxial layer to determine a gain curve for the process parameter, and calculating, using the... Agent: Townsend And Townsend And Crew LLP / Amat

20070128781 - Schottky barrier tunnel transistor and method of manufacturing the same: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same. The method includes the steps of: preparing a substrate; forming an active silicon layer on the substrate; forming a gate insulating layer on a region of the silicon layer; forming a gate electrode on the gate... Agent: Ladas & Parry LLP

20070128782 - Enhanced segmented channel mos transistor with narrowed base regions: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Silcon Valley Patent Group LLP

20070128785 - Method and apparatus for fabricating cmos field effect transistors: A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low... Agent: Moser, Patterson & Sheridan, LLP

20070128784 - Method and structure for buried circuits and devices: A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common device layer within a single-crystal semiconductor layer of an SOI substrate. A... Agent: International Business Machines Corporation Dept. 18g

20070128783 - Method for fabricating strained-silicon cmos transistors: A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is... Agent: North America Intellectual Property Corporation

20070128786 - Semiconductor device having high drive current and method of manufacture therefor: A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The... Agent: Haynes And Boone, LLP

20070128787 - Method of forming low resistance void-free contacts: A plug is formed by depositing a first material to partially fill an opening, leaving an unfilled portion with a lower aspect ratio than the original opening. A second material is then deposited to fill the remaining portion of the opening. The first material has good filling characteristics but has... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070128788 - High voltage metal oxide semiconductor device: A high voltage metal oxide semiconductor device including a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is... Agent: Jianq Chyun Intellectual Property Office

20070128789 - Methods of fabricating semiconductor devices with a source/drain formed on a recessed portion of an isolation layer: Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the... Agent: Myers Bigel Sibley & Sajovec

20070128791 - Method for manufacturing semiconductor device and semiconductor device: Method for manufacturing a semiconductor device, capable of providing a reduced variation in threshold electrical voltage by inhibiting a generation of Fermi level pinning, while achieving a stable long-term reliability of a product by inhibiting a generation of leakage current, and such semiconductor device. The method includes: forming a gate... Agent: Young & Thompson

20070128790 - Semiconductor device and fabrication process thereof: A semiconductor device includes a semiconductor substrate, a polysilicon pattern formed on the semiconductor substrate via an insulation film, an interlayer insulation film formed on the semiconductor substrate so as to cover the polysilicon pattern, and a metal interconnection layer pattern formed on the interlayer insulation film, wherein the metal... Agent: Dickstein Shapiro LLP

20070128792 - Multiple data state memory cell: A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a... Agent: Dickstein Shapiro LLP

20070128793 - Capacitor device of a semiconductor: Embodiments relate to a capacitor having a high capacitance, a semiconductor device having the same, and a method for manufacturing the semiconductor device. In embodiments, the capacitor may include a lower electrode having a predetermined pattern, a dielectric layer formed on the lower electrode, and an upper electrode formed on... Agent: Sherr & Nourse, PLLC

20070128794 - Monolithic ceramic capacitor and method for adjusting equivalent series resistance thereof: An external electrode structure for a monolithic ceramic capacitor provided with a function as a resistance element is capable of preventing a reduction of the external electrode due to baking in a reducing atmosphere, so that Ni or a Ni alloy can be used in an internal electrode and a... Agent: Murata Manufacturing Company, Ltd. C/o Keating & Bennett, LLP

20070128795 - Semiconductor memory device and method for fabricating the same: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed... Agent: Townsend And Townsend And Crew, LLP

20070128801 - Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer... Agent: J.c. Patents, Inc.

20070128797 - Flash memory device and method for fabricating the same: A flash memory device and a method for fabricating the same are provided. The method includes: preparing a semi-finished substrate where floating gates and an isolation layer isolating the floating gates are formed; recessing a predetermined portion of the isolation layer to make the floating gates protrude; etching another predetermined... Agent: Blakely Sokoloff Taylor & Zafman

20070128796 - Method for manufacturing non-volatile memory: A method for manufacturing a non-volatile memory is provided. First, a tunneling dielectric layer is formed over a substrate. A plurality of silicon nanocrystals is formed on the tunneling dielectric layer. A silicide process is performed on the silicon nanocrystals to form a plurality of salicide nanocrystals. A dielectric layer... Agent: Jianq Chyun Intellectual Property Office

20070128799 - Method of fabricating flash memory: A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The... Agent: Jianq Chyun Intellectual Property Office

20070128798 - Nonvolatile memory device and method for fabricating the same: Disclosed are nonvolatile memory devices and methods of fabricating the same. A nonvolatile memory device can include a field isolation film configured to define active regions in a substrate and a wordline configured to intersect the active regions. Devices can also include source and drain regions formed in each of... Agent: Myers Bigel Sibley & Sajovec

20070128802 - Nonvolatile semiconductor memory and manufacturing method thereof: A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070128803 - Nonvolatile semiconductor memory device: A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070128800 - Use of chlorine to fabricate trench dielectric in integrated circuits: Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon... Agent: Macpherson Kwok Chen & Heid LLP

20070128804 - Method for fabricating isolation structures for flash memory semiconductor devices: A method for fabricating integrated circuit devices, e.g., Flash memory devices, embedded Flash memory devices. The method includes providing a semiconductor substrate, e.g., silicon, silicon on insulator, epitaxial silicon. In a specific embodiment, the semiconductor substrate has a peripheral region and a cell region. The method includes forming a first... Agent: Townsend And Townsend And Crew, LLP

20070128805 - Semiconductor memory device and method for fabricating the same: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed... Agent: Townsend And Townsend And Crew, LLP

20070128806 - High performance cmos transistors using pmd liner stress: A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a... Agent: Texas Instruments Incorporated

20070128807 - Piston ring and method for the production thereof: A piston ring includes a running surface having a running surface profile, and an upper flank surface and a lower flank surface. At least the running surface is provided with a vapor-deposited layer such that part of the running surface is provided with a removable cover enabling an essentially sharp-edged... Agent: Robert L Stearns Dickinson Wright

20070128808 - Method for producing nanowires using a porous template: Disclosed herein is a method for producing nanowires. The method comprises the steps of providing a porous template with a plurality of holes in the form of tubes, filling the tubes with nanoparticles or nanoparticle precursors, and forming the filled nanoparticles or nanoparticle precursors into nanowires. According to the method,... Agent: Cantor Colburn, LLP

20070128809 - Methods of reducing floating body effect: Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into... Agent: Knobbe Martens Olson & Bear LLP

20070128811 - Method of forming a low capacitance semiconductor device and structure therefor: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L. L. C.

20070128810 - Ultra high voltage mos transistor device and method of making the same: An ultra high voltage MOS transistor device includes a gate laterally extending onto a first dielectric layer having a void under the gate edge, and a second dielectric layer covering the gate and the first dielectric layer while retaining the void. The first dielectric layer may be in a form... Agent: North America Intellectual Property Corporation

20070128812 - Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate... Agent: Marger Johnson & Mccollom, P.C.

20070128813 - Silicon-on-insulator (soi) read only memory (rom) array and method of making a soi rom: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface... Agent: Law Office Of Charles W. Peterson, Jr. Burlington

20070128815 - Nonvolatile semiconductor memory and fabrication method for the same: A nonvolatile semiconductor memory includes a plurality of active regions AA extending along the column direction isolated from each other by element isolating regions; a plurality of word lines/control gate lines extending along the row direction perpendicular to the plurality of active regions; and memory cell transistors each having a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070128814 - Semiconductor device: A semiconductor device of the present invention includes a source region, a drain region, a gate having a first sidewall, a first insulating sidewall structure disposed to contact the first sidewall of the gate, and a first conductive sidewall structure that is electrically isolated from the gate through the first... Agent: GlobalIPCounselors, LLP

20070128816 - Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070128817 - Method for the production of transistor structures with ldd: The substrate (1) is etched such that on the source side and on the drain side downward sloping sidewalls (5) are formed adjacent to the gate electrode (3) and sloping downward from it. Spacers (7) are positioned there. An implantation (9) of dopant is performed at a low angle relative... Agent: Fish & Richardson PC

20070128818 - Method and system for hermetically sealing packages for optics: A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined... Agent: Townsend And Townsend And Crew, LLP

20070128819 - Film forming method and method of manufacturing semiconductor device: A film forming method for forming an arsenic-doped silicon layer (epitaxially grown silicon layer) by epitaxial growth includes the step of supplying a gas containing arsenic as a dopant into the atmosphere for the epitaxial growth while keeping the epitaxial growth atmosphere at the atmospheric pressure.... Agent: Sonnenschein Nath & Rosenthal LLP

20070128820 - Apparatus and method of fabricating a mosfet transistor having a self-aligned implant: A method including introducing an implant of a dopant species into an active region of a device substrate, the dopant species comprising a conductivity type such that a conductivity of the implant is the same as a conductivity of a well of the active region wherein the introduction is aligned... Agent: Blakely Sokoloff Taylor & Zafman

20070128821 - System and method for implementing transformer on package substrate: A transformer system includes a package substrate having a surface. A plurality of electrically conductive pads are arranged in spaced apart relationship relative to each other on the substrate surface. A first winding is defined by a first electrically conductive path between a first input and a first output, the... Agent: Texas Instruments Incorporated

20070128822 - Varistor and production method: A varistor has a disc of ceramic material having opposed faces with face edges. There is an electrode on each face with a gap between each electrode and the edge of the face. Glass passivation is on at least one face in the gap, the passivation not extending from one... Agent: Bell, Boyd & Lloyd LLP

20070128823 - Method of fabricating semiconductor integrated circuit device: A method of fabricating a semiconductor integrated circuit device is disclosed. The method may include forming an etching target layer on a semiconductor substrate, forming a sacrificial mold layer on the etching target layer, forming a photoresist pattern of a first image on the sacrificial mold layer, patterning the sacrificial... Agent: Harness, Dickey & Pierce, P.L.C

20070128824 - Double-sided etching method using embedded alignment mark: A double-sided etching method using an embedded alignment mark includes: preparing a substrate having first and second alignment marks embedded in an intermediate portion thereof; etching an upper portion of the substrate so as to expose the first alignment mark from a first surface of the substrate; etching the upper... Agent: Sughrue Mion, PLLC

20070128826 - Article with multilayered coating and method for manufacturing same: An exemplary article with a multilayered coating includes a substrate, an adhesive layer, a silicon layer, a silicon carbide layer, a blended layer of silicon carbide and carbon, and a hydrogenated DLC layer. The adhesive layer is formed on the substrate. The silicon layer is formed on the adhesive layer.... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070128827 - Method and system for increasing yield of vertically integrated devices: A method for increasing the manufacturing yield for a vertically integrated device is disclosed. The devices are composed of one or more multiple layer die. The number of functioning layers of each multiple layer die is determined diagnostically. Each of said multiple layer die are sorted based on said number... Agent: Reveo, Inc.

20070128825 - Method for bonding substrates and device for bonding substrates: A method for bonding of substrates has a steps of irradiating surfaces of the substrates respectively in a vacuum with both an inert gas beam and a metal beam thereby forming island shaped thin metal films on the surfaces of the substrates, and surface-activated bonding of the substrates through the... Agent: Synnestvedt Lechner & Woodbridge LLP

20070128829 - Method for fabricating thin layer device: A method for producing a thin layer device such as a superconductive device excellent in mechanical strength and useful as a submillimeter band receiver is provided. The thin layer device is produced by forming a multilayer structure substance comprising an NbN/MgO/NbN-SIS junction on an MgO temporary substrate, then forming SiO2,... Agent: Birch Stewart Kolasch & Birch

20070128830 - Method for producing dislocation-free strained crystalline films: A method for forming dislocation-free strained silicon thin film includes the step of providing two curved silicon substrates. One substrate is curved by the presence of silicon dioxide on a back surface. The other substrate is curved by the presence of a silicon nitride layer. One of the substrates is... Agent: VistaIPLaw Group LLP

20070128828 - Micro electro-mechanical system packaging and interconnect: A micro electro-mechanical system (MEMS) device includes an electrical wafer, a mechanical wafer, a plasma treated oxide seal bonding the electrical wafer to the mechanical wafer, and an electrical interconnect between the electrical wafer and the mechanical wafer.... Agent: Hewlett Packard Company

20070128831 - Process for fabricating a micro-electro-mechanical system with movable components: A process for fabricating a micro-electro-mechanical system (MEMS) composed of fixed components fixedly supported on a lower substrate and movable components movably supported on the lower substrate. The process utilizes an upper substrate separate from the lower substrate. The upper substrate is selectively etched in its top layer to form... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070128832 - Supporting plate, and method for attaching supporting plate: A method for attaching a supporting plate which makes it possible to prevent the groove pattern of the supporting plate from being transferred to the substrate, and to prevent non-uniformity from occurring when the surface of the substrate is ground. One surface of the supporting plate is attached to the... Agent: Carrier Blackman And Associates

20070128833 - Manufacturing method of semiconductor device: It is an object to provide a manufacturing method of a semiconductor device with high reliability. A plurality of first semiconductor integrated circuits, a plurality of second semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits, a plurality of third... Agent: Nixon Peabody, LLP

20070128834 - Wafer dividing method: A method of dividing a wafer having devices which are formed in a plurality of areas sectioned by a plurality of dividing lines, along the dividing lines, comprising the steps of forming a deteriorated layer in the inside of the wafer along the dividing lines by applying a laser beam... Agent: Smith, Gambrell & Russell

20070128835 - Semiconductor package structure and method for separating package of wafer level package: The present invention provides a separating process of a semiconductor device package of wafer level package. The method comprises a step of etching a substrate to form recesses. Then a buffer layer is formed on the first surface of the substrate, wherein the buffer layer is filled with the corresponding... Agent: Birch Stewart Kolasch & Birch

20070128836 - Manufacturing method of semiconductor wafer and semiconductor wafer manufactured by this method: An epitaxial layer 17 is grown in a trench 16 of a semiconductor wafer 10 having a trench structure by gradually reducing a temperature in a temperature in the range of 400 to 1150° C. by a vapor growth method while supplying a silane gas as a raw material gas,... Agent: Reed Smith, LLP Attn: Patent Records Department

20070128837 - Semiconductor processing: Methods are disclosed for providing reduced particle generating silicon carbide. The silicon carbide articles may be used as component parts in apparatus used to process semiconductor wafers. The reduced particle generation during semiconductor processing reduces contamination on semiconductor wafers thus increasing their yield.... Agent: John J. Piskorski Rohm And Haas Electronic Materials LLC

20070128838 - Method for producing soi substrate and soi substrate: A method for producing an SOI substrate, comprising: implanting oxygen ions into a silicon substrate; heat treating the silicon substrate in an inert atmosphere containing oxygen; and forming a buried oxide film in the silicon substrate, wherein the inert gas contains argon and nitrogen.... Agent: Kolisch Hartwell, P.C.

20070128839 - Quantum dot laser diode and method of manufacturing the same: Provided are a quantum dot laser diode and a method of manufacturing the same. The method of manufacturing a quantum dot laser diode includes the steps of: forming a grating structure layer including a plurality of gratings on a substrate; forming a first lattice-matched layer on the grating structure layer;... Agent: Ladas & Parry LLP

20070128840 - Method of forming thin sgoi wafers with high relaxation and low stacking fault defect density: A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned... Agent: International Business Machines Corporation Dept. 18g

20070128841 - Solid-state image capturing device, manufacturing method for the same and electronic information device: A method for manufacturing a solid-state image capturing device according to the present invention, in which from a plurality of light receiving sections for photoelectrically converting incident light into signal electric charge, the signal electric charge is read to an electric charge detection section through transfer sections located under respective... Agent: Edwards Angell Palmer & Dodge LLP

20070128842 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes: forming a plurality of conductive patterns with regionally different densities over a substrate; forming a first insulation layer over the conductive patterns; forming a second insulation layer having substantially the same etch selectivity as the first insulation layer and a better step... Agent: Blakely Sokoloff Taylor & Zafman

20070128843 - Manufacturing method of workpiece: A fused coating material is injected from a nozzle onto a copper foil, the temperature of which is lower than a fusion start temperature of the coating material, and the thus injected coating material is coagulated so as to form a mask on the copper foil. According to a mask... Agent: Harness, Dickey & Pierce, P.L.C

20070128844 - Non-polar (a1,b,in,ga)n quantum wells: A method of fabricating non-polar a-plane GaN/(Al,B,In,Ga)N multiple quantum wells (MQWs). The a-plane MQWs are grown on the appropriate GaN/sapphire template layers via metalorganic chemical vapor deposition (MOCVD) with well widths ranging from 20 Å to 70 Å. The room temperature photoluminescence (PL) emission energy from the a-plane MQWs followed... Agent: Gates & Cooper LLP Howard Hughes Center

20070128846 - Integrated circuit device gate structures and methods of forming the same: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than... Agent: Robert W. Glatz Myers Bigel Sibley & Sajovec, P.A.

20070128845 - Interconnect structure of an integrated circuit and manufacturing method thereof: An interconnect structure of an integrated circuit and manufacturing method therefor are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With... Agent: Birch Stewart Kolasch & Birch

20070128848 - Dual damascene wiring and method: A structure and method of fabricating a dual damascene interconnect structure, the structure including a dual damascene wire in a dielectric layer, the dual damascene wires extending a distance into the dielectric layer less than the thickness of the dielectric layer and dual damascene via bars integral with and extending... Agent: Schmeiser, Olsen & Watts

20070128847 - Semiconductor device and a method for manufacturing the same: Disclosed are embodiments relating to a semiconductor device and a method of manufacturing a semiconductor device that may prevent an increase of a dielectric effective constant of the IMD. In embodiments, a semiconductor device may include a substrate having a source/drain area, a gate electrode formed on the semiconductor substrate,... Agent: Sherr & Nourse, PLLC

20070128849 - Waferless automatic cleaning after barrier removal: A method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the... Agent: Beyer Weaver LLP

20070128850 - Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole: A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first insulating film is prepared on a substrate, and a layer is disposed on the above-described first insulating... Agent: Fitzpatrick Cella Harper & Scinto

20070128851 - Fabrication of semiconductor interconnect structures: A system and a method of forming copper interconnect structures in a surface of a wafer is provided. The method includes a step of performing a planar electroplating process in an electrochemical mechanical deposition station for filling copper material into a plurality of cavities formed in the surface of the... Agent: Knobbe Martens Olson & Bear LLP

20070128853 - Method for forming inter-layer dielectric of low dielectric constant and method for forming copper wiring using the same: A method for forming a dielectric layer having a low dielectric constant and a method for forming copper wiring using the same are provided. In the method for forming a dielectric, an etch stop layer and a first dielectric are sequentially formed on a semiconductor substrate. Next, the first dielectric... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070128852 - Method for manufacturing semiconductor device having via holes: In a method for manufacturing a semiconductor device wherein via holes are formed in an SiC substrate, a stacked film consisting of a Ti film and an Au film is formed on the back face of the SiC substrate, and a Pd film is formed thereon. Then, an Ni film... Agent: Leydig Voit & Mayer, Ltd

20070128854 - Near-field optical probe based on soi substrate and fabrication method thereof: Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support portion having a through hole formed therein at a side of the lower silicon layer; and a cantilever arm forming of a... Agent: Ladas & Parry LLP

20070128856 - Pitch reduced patterns relative to photolithography features: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the... Agent: Knobbe Martens Olson & Bear LLP

20070128855 - Printed wiring board and method for manufacturing the same: Provided is a method for manufacturing a printed wiring board, which can enhance the peel strength between an insulating layer and a conductive pattern by a two-step process, that is, a semi-hardening and full-hardening of the insulating layer. In the method for manufacturing the printed wiring board having one or... Agent: Staas & Halsey LLP

20070128857 - Method for manufacturing copper wires on substrate of flat panel display device: A method for manufacturing copper wires on a substrate for a flat panel display device is disclosed. The method comprises following steps: providing a substrate; forming a seed layer on the surface; forming a patterned photoresist on the surface of the seed layer to expose a part of the seed... Agent: Bacon & Thomas, PLLC

20070128858 - Method of producing thin films: A process for producing metal nitride thin films comprising doping the metal nitride thin films by atomic layer deposition (ALD) with silicon or boron or a combination thereof. The work function of metal nitride thin films, which are used in metal electrode applications, can efficiently be tuned.... Agent: Knobbe Martens Olson & Bear LLP

20070128862 - Apparatus and process for plasma-enhanced atomic layer deposition: Embodiments of the invention provide an apparatus configured to form a material during an atomic layer deposition (ALD) process, such as a plasma-enhanced ALD (PE-ALD) process. In one embodiment, a showerhead assembly comprises a showerhead and a plasma baffle that are used to disperse process gases within a plasma-enhanced vapor... Agent: Patterson & Sheridan, L.L.P.

20070128863 - Apparatus and process for plasma-enhanced atomic layer deposition: Embodiments of the invention provide an apparatus configured to form a material during an atomic layer deposition (ALD) process, such as a plasma-enhanced ALD (PE-ALD) process. In one embodiment, a lid assembly for conducting a vapor deposition process within a process chamber is provided which includes an insulation cap and... Agent: Patterson & Sheridan, LLP

20070128864 - Apparatus and process for plasma-enhanced atomic layer deposition: Embodiments of the invention provide a method for forming a material on a substrate during an atomic layer deposition (ALD) process, such as a plasma-enhanced ALD (PE-ALD) process. In one embodiment, a method is provided which includes flowing at least one process gas through at least one conduit to form... Agent: Patterson & Sheridan, LLP

20070128866 - Apparatus for fabricating tungsten contacts with tungsten nitride barrier layers in semiconductor devices: A method forming a tungsten contact can include forming a contact hole in an interlayer dielectric layer to expose a portion of an underlying silicon based substrate and to form a side wall of the contact hole. A tungsten silicide layer can be formed on at least on the exposed... Agent: Myers Bigel Sibley & Sajovec

20070128859 - Combined stepper and deposition tool: A stepper is combined with hardware that deposits a layer of material in the course of forming an integrated circuit, thus performing the deposition, patterning and cleaning without exposing the wafer to a transfer between tools and combining the function of three tools in a composite tool. The pattern-defining material... Agent: International Business Machines Corporation Dept. 18g

20070128861 - Cvd apparatus for depositing polysilicon: Disclosed is a CVD apparatus for depositing polysilicon without a separate following annealing process, the CVD apparatus comprising: a chamber to form a thin film on a substrate; a showerhead placed in an upper part of the chamber to inject reaction gas onto the substrate; a distributor formed with distributing... Agent: Knobbe Martens Olson & Bear LLP

20070128860 - Method and apparatus for improving breakdown voltage of integrated circuits formed using a dielectric layer process: A method and apparatus for depositing a dielectric layer. The apparatus includes a semiconductor processing chamber configured for use in a dielectric layer deposition process, the semiconductor processing chamber being associated with at least a length, a width, a height, and a volume, one or more gas sources containing one... Agent: Townsend And Townsend And Crew, LLP

20070128865 - Method of forming insulating film, method of manufacturing semiconductor device and their controlling computer program: A semiconductor substrate with a groove is placed in a plasma generating reaction chamber. Silicon, oxygen and hydrogen containing gases are introduced into the reaction chamber as process gases. A ratio of a gas flow of the hydrogen containing gas except the silicon containing gas to a total gas flow... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070128867 - Method for enhanced uni-directional diffusion of metal and subsequent silicide formation: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is... Agent: Scully, Scott, Murphy & Presser, P.C.

20070128868 - Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby: A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated... Agent: Macpherson Kwok Chen & Heid LLP

20070128869 - Method and apparatus for annealing copper films: A method and apparatus for annealing copper. The method comprises forming a copper layer by electroplating on a substrate in an integrated processing system and annealing the copper layer in a chamber inside the integrated processing system.... Agent: Patterson & Sheridan, LLP

20070128871 - Etching apparatus and etching method: An etching apparatus includes a shield device provided on an electrode in a reaction chamber and surrounding an object to be etched. The shield device has a surface area according to an opening area ratio of the object to be etched.... Agent: Mcdermott Will & Emery LLP

20070128870 - Surface topology improvement method for plug surface areas: The surface topology of a plug surface area-containing surface of a semiconductor device can be improved by removing material to create a first planarized surface with at least one plug surface area, typically a tungsten or copper plug area, comprising a recessed region. A material is deposited onto the first... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070128872 - Polishing composition and polishing method: As a polishing composition which allows high-speed polishing while dishing and erosion are prevented and the flatness of metal film is maintained, there is provided a polishing composition for polishing a metal film provided on a substrate having trenches such that the metal film fills the trenches, so as to... Agent: Sughrue Mion, PLLC

20070128873 - Aqueous dispersion for cmp, polishing method and method for manufacturing semiconductor device: An aqueous dispersion for chemical mechanical polishing is provided, which includes water and a resin particle. The resin particles accompany with a projection having a curvature radius ranging from 10 nm to 1.65 μm on a surface. The maximum length of the resin particles is not more than 5 μm... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070128874 - Chemical mechanical polishing method and method of manufacturing semiconductor device: A chemical mechanical polishing method comprises polishing an organic film using a slurry including polymer particles having a surface functional group and a water-soluble polymer.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070128875 - Dry etch release method for micro-electro-mechanical systems (mems): The present invention provides a means for releasing semiconductor, micromachined and/or Micro-Electro-Mechanical Systems (MEMS) parts from a substrate. Semiconductor, micromachined or MEMS components built at the wafer level must be separated after fabrication. Through novel application of Deep Reactive Ion Etching (DRIE) or Bosch etching to etch through the substrate,... Agent: Pedersen & Company, PLLC

20070128876 - Chamber dry cleaning: An apparatus and method for improving the chamber dry cleaning of a PECVD system. The apparatus includes an annular gas ring with multiple outlets for introducing a cleaning gas into the process chamber, and the method includes using the gas ring to introduce a cleaning species from a remote plasma... Agent: Dla Piper US LLP

20070128877 - Polymer coating for vapor deposition tool: Described herein is an apparatus useful for depositing a material on a substrate. At least one component of the apparatus comprises a protective coating, which facilitates the cleaning and/or removal of the deposited material from the component. Also described are methods for depositing a material on a substrate using the... Agent: Knobbe Martens Olson & Bear LLP

20070128881 - Adhesion by plasma conditioning of semiconductor chip surfaces: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits,... Agent: Texas Instruments Incorporated

20070128882 - Advanced low dielectric constant organosilicon plasma chemical vapor deposition films: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and... Agent: Scully, Scott, Murphy & Presser, P.C.

20070128880 - Process and apparatus for forming oxide film, and electronic device material: An oxide film-forming apparatus, comprising: a process chamber for disposing an electronic device substrate at a predetermined position; water vapor supply means for supplying water vapor into the process chamber; and plasma exciting means for activating the water vapor with plasma, whereby the surface of the electronic device substrate can... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070128879 - Reactive cyclodextrin derivatives as pore-forming templates, and low dielectric materials prepared by using the same: This invention is related to a reactive nanoparticular cyclodextrin derivative useful as a porogen and a low dielectric matrix, with excellent mechanical properties and uniformly distributed nanopores, manufactured by sol-gel reaction of the above reactive cyclodextrin. Furthemore, this invention also is related to an ultralow dielectric film, with uniformly distributed... Agent: Frommer Lawrence & Haug

20070128878 - Substrate processing apparatus and method for producing a semiconductor device: A pyrogenic oxidation device (10) is comprised of a process gas supply line (38) connecting an external combustion device (39) and a supply pipe (37) connected to a processing chamber (13) and, a dilute gas supply line (45) connected to the process gas supply line (38) for supplying nitrogen gas... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070128883 - Carbon nanotube reinforced metallic layer: A method and apparatus including an interconnect structure having a surface, a plurality of nanotubes disposed adjacent to the surface, and a metallic layer disposed adjacent to the surface and substantially including the nanotubes. An assembly may include a first embodiment of an apparatus as described, and may further include... Agent: Intel Corporation C/o Intellevate, LLC

20070128884 - Metal oxynitride electrode catalyst: [Problems] Carbides and many other non-platinum-based compounds are activated and dissolved and cannot be stably present in an acidic electrolyte under conditions of an electrode potential as high as 0.4 V or above, and thus, the application range of these compounds as an electrode catalyst is limited to low electrode... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070128885 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device comprises the step of depositing an insulation film 32a with a first pressure set in a deposition chamber; the step of gradually decreasing the pressure in the deposition chamber to a second pressure which is lower than the first pressure; and the step... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070128886 - Substrate, method for producing the same, and patterning process using the same: There is disclosed a substrate comprising at least an organic film, an antireflection silicone resin film over the organic film, and a photoresist film over the antireflection silicone resin film, wherein the antireflection silicone resin film includes a lower silicone resin film and an upper silicone resin film which has... Agent: Oliff & Berridge, PLC

20070128887 - Spin-on glass passivation process: Integrated circuits and methods of making an integrated circuit are disclosed. The disclosed methods include providing a substrate having at least one device structure thereon; providing a first barrier layer over the substrate and the at least one device structure; providing a dielectric layer formed by a spin-on-glass process; and... Agent: Baker & Mckenzie LLP Patent Department

20070128888 - Substrate heat treatment apparatus: A heat-treating plate has support elements projecting from an upper surface thereof. The support elements are located at apexes of equilateral triangles arranged regularly and continually. The heat-treating plate and a substrate placed on the support elements form a minute space therebetween which is sealed by a sealer. The substrate... Agent: Ostrolenk Faber Gerb & Soffen

20070128889 - Substrate heat treatment apparatus: A heat-treating plate has, arranged on the upper surface thereof, support elements for supporting a substrate, and a first sealer for closing lateral areas of a first space formed between the heat-treating plate and the substrate supported. Further, second sealers ring-shaped in plan view are arranged around openings of perforations... Agent: Ostrolenk Faber Gerb & Soffen

20070128890 - Stacked annealing system: A process chamber includes an opening, two or more stacked cold plates adjacent the opening, two or more stacked hot plates adjacent the cold plates, and a rotatable wafer transport capable of moving a wafer between the cold plates and between the hot plates for processing of the wafer. The... Agent: Macpherson Kwok Chen & Heid LLP