Semiconductor device manufacturing: process inventions 06/07

20070148792 - Wafer measurement system and apparatus: A method and apparatus for the measurement of wafer thickness, flatness and the trench depth of any trenches etched thereon using the back surface of the wafer to accurately measure the back side of a trench, rendering the trench an effective bump, capable of being measured on the top surface... Agent: Sandra Lee Lipkin A Law Corporation

20070148799 - Liquid crystal display and fabrication method thereof: A liquid crystal display and a fabricating method thereof are provided. The liquid crystal display includes a first substrate having a pixel portion and a pad portion; a gate line and a data line crossing each other to define the pixel portion at the pixel portion; a transistor adjacent to... Agent: Birch Stewart Kolasch & Birch

20070148786 - Mgo/nife mtj for high performance mram application: An improved tunneling barrier layer is formed for use in a MTJ device. This is accomplished by forming the tunneling barrier layer in two steps. First a layer of magnesium is deposited by DC sputtering and converted to magnesium oxide through radical oxidation. This is followed by a second, thinner,... Agent: Stephen B. Ackerman

20070148787 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device that prevents an etching residue left at the time of making a contact hole which connects with a ferroelectric capacitor from adhering to the surface of a wafer. In order to make a contact hole which connects with an upper electrode or a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070148789 - Methods of forming magnetic random access memory devices having titanium-rich lower electrodes with oxide layer and oriented tunneling barrier: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An... Agent: Myers Bigel Sibley & Sajovec

20070148788 - Semiconductor piezoresistive sensor and operation method thereof: A semiconductor piezoresistive sensor, which is electrically connected with a circuit, includes a semiconductor base, at least one piezoresistive element and a conductive layer. The semiconductor base includes a diaphragm and a base. The base is disposed adjacent to and around the diaphragm. The piezoresistive element is formed in the... Agent: Birch Stewart Kolasch & Birch

20070148795 - Insulator film characteristic measuring method and insulator film characteristic measuring apparatus: A method is for measuring the characteristics of an insulator film (inner charge amount, film thickness, relative dielectric constant, surface voltage change due to a surface adsorbed substance, etc.) formed on a surface of a semiconductor substrate in a non-contact manner. This method includes: a step of measuring a measured... Agent: Mcdermott Will & Emery LLP

20070148794 - Method for designing a semiconductor device capable of reflecting a time delay effect for dummy metal fill: Disclosed is a method for designing a semiconductor device. In an existing semiconductor design, a time delay effect caused by a dummy metal interconnection cannot be reflected. In order to address this disadvantage, a real metal fill pattern and a virtual metal fill pattern are employed for a layout parasitic... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148790 - Method for treatment of samples for auger electronic spectrometer (aes) in the manufacture of integrated circuits: A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The... Agent: Townsend And Townsend And Crew, LLP

20070148791 - Method of measuring film thickness and method of manufacturing semiconductor device: A method of measuring a film thickness is disclosed. The method includes a step of forming a ferroelectric capacitor on a substrate, a step of forming an insulating film to cover the ferroelectric capacitor, and a step of optically measuring the thickness of the insulating film on an electrode of... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070148793 - Semiconductor device, display device, and electronic device: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing... Agent: Fish & Richardson P.C.

20070148796 - Zq calibration circuit and semiconductor device: AZQ calibration command internally generated from an external command different from a ZQ calbration command so as to automatically perform an additional ZQ calibration operation. A command interval between an imputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from... Agent: Sughrue Mion, PLLC

20070148797 - Forming electronic devices: A method of manufacturing a device, comprising printing an aqueous solution or dispersion comprising an electronically functional substance, for example a conducting polymer such as PEDOT-PSS, and a surface tension reducing agent onto predetermined portions of a hydrophobic surface, for example formed by a ferroelectric polymer layer. The conducting polymer... Agent: Oliff & Berridge, PLC

20070148798 - Fabrication method of transparent electrode on visible light-emitting diode: A method for forming a transparent electrode on a visible light-emitting diode is described. A visible light-emitting diode element is provided, and the visible light-emitting diode element has a substrate, an epitaxial structure and a metal electrode. The metal electrode and the epitaxial structure are located on the same side... Agent: Glenn Patent Group

20070148800 - Liquid crystal display device and fabrication method thereof: A liquid crystal display (LCD) device and its fabrication method includes providing a substrate divided into pixel part and pad parts; forming a gate electrode and a gate line at the pixel part through a first masking process; forming a first insulation film; forming an active pattern and source and... Agent: Birch Stewart Kolasch & Birch

20070148802 - Method for fabricating transflective liquid crystal display: An exemplary method for fabricating a transflective liquid crystal display is provided. The transflective liquid crystal display includes a substrate (200) having a transmission region (201) and a reflection region (202). The method includes: forming a transparent electrode layer (210), a buffer layer (220), and a reflective metal layer (230)... Agent: Wei Te Chung Foxconn International, Inc.

20070148801 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device includes the steps of: forming a gate on a semiconductor substrate; sequentially stacking a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate; forming a first photoresist layer pattern on the second oxide layer;... Agent: Mayer, Brown, Rowe & Maw LLP

20070148803 - Production method for semiconductor device: An object of the present invention is to provide a method of producing a Group III nitride semiconductor device having a chip form which is pentagonal or more highly polygonal maintaining good area efficiency and at a low cost. The inventive method of producing a Group III nitride semiconductor device... Agent: Sughrue Mion, PLLC

20070148804 - Method of making a multilayered device with ultra-thin freestanding metallic membranes using a peel off process: A micro electromechanical device includes a substrate having stacked films. Each of the films includes a first layer and a second layer. The second layer is metal of a predetermined thickness. The stacked films are formed by electroplating the second layer on the first layer and lifting off a third... Agent: Blakely Sokoloff Taylor & Zafman

20070148805 - Method for manufacturing cmos image sensor: A method for manufacturing a CMOS image sensor is disclosed. The method includes the steps of: forming a passivation oxide and a passivation nitride after forming a pad; performing a hydrogen anneal; selectively removing the passivation nitride and cleaning the passivation oxide; opening and cleaning the pad by removing the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148806 - Method of fabricating complementary metal oxide silicon image sensor: Provided is a method of fabricating a complementary metal oxide silicon image sensor. The method includes: applying a passivation oxide and a passivation nitride after forming a pad; selectively removing the passivation nitride in a pad region and a pixel region by a photolithography process, and performing a first cleaning... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148807 - Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers: Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including a first substrate and an image sensor on and/or in the first substrate. An embodiment of an optical device includes a stand-off having a compartment configured to contain the... Agent: Dickstein Shapiro LLP

20070148808 - Method of manufacturing cmos image sensor: Embodiments relate to a method of manufacturing a CMOS image sensor in which, when a buried photodiode is formed, a p-type impurity region may be formed simultaneously with a p-type LDD region in the photo diode region. Additionally, a p-type impurity region may be formed under side wall spacers, which... Agent: Sherr & Nourse, PLLC

20070148809 - Method of manufacturing image sensor: A method of manufacturing an image sensor, which avoids corroding a pad electrode with overexposure to corrosive chemicals, includes forming a pad electrode over a semiconductor substrate, forming a passivation layer over the pad electrode, applying a photoresist over the passivation layer, etching the photoresist and passivation layer to form... Agent: Sherr & Nourse, PLLC

20070148810 - Functional paste: [Aims] To provide functional paste with etching activity and good electrical properties. [Means] Functional paste comprising a metal powder, an etching agent, a binder and an organic solvent.... Agent: Millen, White, Zelano & Branigan, P.C.

20070148811 - Method for manufacturing cmos image sensor: A method for manufacturing a CMOS image sensor is provided. The method can include forming an interlayer dielectric layer on a semiconductor substrate including a gate electrode, photodiode area, and LDD region; selectively removing the interlayer dielectric layer such that the interlayer dielectric layer remains on the photodiode area; performing... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148813 - Electric device, method of manufacturing electric device and electric apparatus: An electric device includes: a pair of electrodes, an organic semiconductor film and an organic film formed on a surface of at least one of the electrodes, wherein the organic this film includes a nonconjugated organic compound having a plurality of coupling groups coupled with the electrodes.... Agent: Oliff & Berridge, PLC

20070148812 - Organic thin-film transistors: Methods are disclosed for improving organic thin-film transistor (OTFT) performance by acid doping of the semiconducting layer. The semiconducting polymer comprising the semiconductor layer is doped with an acid, especially a Lewis acid, either during or after polymerization of the polymer, but prior to application of the polymer onto the... Agent: Richard M. Klein, Esq. Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070148814 - Process for manufacturing a phase change memory array in cu-damascene technology and phase change memory array thereby manufactured: A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively;... Agent: Seed Intellectual Property Law Group PLLC

20070148815 - Nano-array and fabrication method thereof: The invention provides a method for fabricating a nano-array comprising the following steps. A template with a plurality of nano-holes is provided. A polymer is embossed by the template to integrally form a plurality of nano-protrusions thereon, and demolding to reveal the nano-protrusions. The nano-protrusion has a concave or convex... Agent: Birch Stewart Kolasch & Birch

20070148816 - Attachment of a qfn to a pcb: Methods and arrangements to attach a QFN to a PCB, systems which include a QFN attached to a PCB, and apparatuses for controlling the deposit of solder upon a PCB are disclosed. Embodiments include transformations, code, state machines or other logic to calculate a total area for the QFN IO... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070148818 - Electrical connection methods employing corresponding, insulator-coated members of interconnection elements: A method of electrically connecting corresponding contact pads of semiconductor device components to each other includes interconnecting first and second members of an interconnection element. The first and second members respectively protrude from first and second semiconductor device components, with a conductive element of each member in communication with a... Agent: Trask Britt, P.C./ Micron Technology

20070148817 - Methods for fabricating reinforced, self-aligning conductive structures for semiconductor device components: A method for fabricating an electrical interconnection element, or conductive structure, includes disposing a jacket of a first member of the electrical interconnection element laterally around a contact of a semiconductor device structure and introducing conductive material into the jacket. The jacket, which may be electrically insulative, may include a... Agent: Trask Britt, P.C./ Micron Technology

20070148819 - Microelectronic assemblies having very fine pitch stacking: A microelectronic assembly includes two or more microelectronic packages stacked at a fine pitch, which is finer than the pitch that is possible when using solder balls for making the joint. Each stackable package desirably includes a substrate having pins projecting from one surface of the substrate and solder balls... Agent: Tessera Lerner David Et Al.

20070148820 - Microelectronic devices and methods for manufacturing microelectronic devices: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes attaching a first die to a support member, coupling a second die to the first die with the first die positioned between the second die and the support member, and placing the... Agent: Perkins Coie LLP Patent-sea

20070148821 - Thermally enhanced stacked die package and fabrication method: A substrate is provided. A first die is attached to the substrate. The first die is electrically connected to the substrate. A heat sink having an undercut around its periphery is attached to the first die. A second die is attached to the heat sink. The second die is electrically... Agent: Ishimaru & Zahrt LLP

20070148822 - Microelectronic packages and methods therefor: A method of making a microelectronic assembly includes providing a microelectronic package having a substrate, a microelectronic element overlying the substrate and at least two conductive elements projecting from a surface of the substrate, the at least two conductive elements having surfaces remote from the surface of the substrate. The... Agent: Tessera Lerner David Et Al.

20070148824 - Compliant terminal mountings with vented spaces and methods: A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The... Agent: Tessera Lerner David Et Al.

20070148823 - Method of manufacturing an electronic protection device: A method of manufacturing an electronic protection device comprises: providing a substrate mother board with a top surface and a bottom surface; forming a first conductive layer and a second conductive layer on the top surface and the bottom surface, respectively; cutting the substrate mother board into a plurality of... Agent: Volentine Francos, & Whitt PLLC

20070148826 - Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement: An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement.... Agent: Scully, Scott, Murphy & Presser, P.C.

20070148825 - Semiconductor device and manufacturing method for the same: A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second... Agent: Sughrue Mion, PLLC

20070148827 - Method of manufacturing wiring substrate, liquid ejection head and image forming apparatus: The method of manufacturing a wiring substrate includes the steps of: filling conductive material into a through hole and a non-through hole of a substrate; removing the conductive material filled into the through hole; and removing at least a portion of a rear side of the substrate which is opposite... Agent: Birch Stewart Kolasch & Birch

20070148828 - Substrate supporting frame: A substrate supporting frame, a substrate supporting frame assembly including the frame, a method of framing a substrate using the frame, a method of fabricating a donor substrate using the substrate supporting frame assembly, and a method of fabricating an Organic Light Emitting Display (OLED) using the donor substrate each... Agent: Robert E. Bushnell

20070148829 - Multi-layered flexible print circuit board and manufacturing method thereof: Provided is an FPC, which comprises an insulating layer 2, wiring layers 3 and 4 laminated above and under the insulating layer 2, and a layer connection for connecting the wiring layers 3 and 4 electrically. The layer connection is constituted to comprise: a conductor press-fit hole 5 of a... Agent: Greenblum & Bernstein, P.L.C

20070148830 - Nor-type flash memory cell array and method for manufacturing the same: Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148832 - Method for manufacturing a semiconductor substrate, method for manufacturing a semiconductor device, and the semiconductor device: A method for manufacturing a semiconductor substrate having a silicon-on-insulator (SOI) structure region isolated by a local oxidation of silicon (LOCOS) film and an SOI structure in the region includes forming the LOCOS film so as to make a height from an uppermost surface of a semiconductor member to a... Agent: Advantedge Law Group, LLC

20070148831 - Thin film transistor device, method for manufacturing the same and display apparatus having the same: A thin film transistor device includes: an island shaped semiconductor layer; a metal film that covers at least a part of a source region and a drain region of the semiconductor layer; a gate insulating film that covers the semiconductor layer and the metal film; an interlayer insulating film that... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070148833 - Thin film transistor and method of manufacturing the same: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of... Agent: H.c. Park & Associates, PLC

20070148834 - Laser irradiation apparatus and laser irradiation method: It is an object of the present invention to provide a laser irradiation apparatus which can manufacture a homogenously crystallized film by varying the energy intensity of an irradiation beam in forward and backward directions of the irradiation. A laser irradiation apparatus of the present invention comprises a laser oscillator... Agent: Eric Robinson

20070148835 - Semiconductor integrated circuit device and fabrication process thereof: A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070148836 - Reduced-resistance finfets and methods of manufacturing the same: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20070148837 - Method of fabricating a multi-cornered film: Embodiments of the present invention describe a method of forming a multi-cornered film. According to the embodiments of the present invention, a photoresist mask is formed on a hard mask film formed on a film. The hard mask film is then patterned in alignment with the photoresist mask to produce... Agent: Intel/blakely

20070148844 - Method for manufacturing semiconductor device: Disclosed is a method of manufacturing a semiconductor device, which includes the steps of: forming a high-voltage well region (e.g., by implanting impurity ions into a semiconductor substrate and then annealing); forming an isolation layer on the semiconductor substrate; implanting impurity ions into the high-voltage well region, thereby forming a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148840 - Method of forming fin transistor: A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG... Agent: Ladas & Parry LLP

20070148839 - Method of manufacturing semiconductor device, semiconductor device and electronic apparatus therefore: A method for manufacturing a semiconductor device includes: forming a lower gate electrode over a substrate; forming a sacrifice film over the substrate such that the lower gate electrode is overlapped with the sacrifice film; forming a semiconductor film over the sacrifice film such that the semiconductor film crosses over... Agent: Oliff & Berridge, PLC

20070148838 - Metal gate cmos with at least a single gate metal and dual gate dielectrics: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate... Agent: Scully Scott Murphy & Presser, PC

20070148841 - Method for forming transistor in semiconductor device: A method for forming a transistor in a semiconductor device with an elongated channel region. The method includes the steps of forming a polysilicon layer on a semiconductor substrate and patterning the polysilicon layer to form a dummy substrate, and forming a gate oxidation layer and a gate electrode on... Agent: Sherr & Nourse, PLLC

20070148842 - Method of manufacturing a transistor: Embodiments relate to a method of manufacturing a transistor having a metal silicide layer. In embodiments, the method may include sequentially forming a gate insulating layer pattern and a gate conductive layer pattern on a semiconductor substrate, forming a first metal silicide layer on the gate conductive layer pattern and... Agent: Sherr & Nourse, PLLC

20070148845 - Non-volatile memory device and method for fabricating the same: A method and non-volatile memory device are provided that are characterized by ion-implantation of impurities in the sidewalls of a first electrode. The inclusion of impurities in the sidewalls eliminates geometric abnormalities, referred to herein as a bird's beak, in the first electrode, which are caused by numerous oxidation processes... Agent: Mayer, Brown, Rowe & Maw LLP

20070148843 - Semiconductor device and method of manufacturing the same: This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148846 - Image sensor and method of manufacturing the same: A CMOS image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes a semiconductor substrate including a plurality of photodiodes and a plurality of transistors, a first interlayer dielectric formed on the semiconductor substrate, a metal wiring and a second interlayer dielectric formed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148849 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; removing the gate oxide layer on the p-type well;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148847 - Method of fabricating cmos image sensor: A method of fabricating a CMOS image sensor is provided. According to an embodiment, a device isolation layer is formed in a semiconductor substrate to define a device isolation region and an active region. A gate insulating layer and a polysilicon layer are formed on the semiconductor substrate. Impurity ions... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148848 - Methods of forming dual gate of semiconductor device: Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a... Agent: Townsend And Townsend And Crew, LLP

20070148850 - Method for forming a dram semiconductor device with a sense amplifier: A method for forming a sense amplifier of a semiconductor device prevents bit lines from being bridged to each other by a stepped portion created on an insulation interlayer due to irregular density of a P-type impurity, which is ion-implanted into an insulation interlayer in a P+ pickup region when... Agent: Ladas & Parry LLP

20070148851 - Method of programming eeprom having single gate structure: A method of programming an EEPROM including a first active region, a second active region and a third active region located separately in a semiconductor substrate, a common floating gate above and intersecting the active regions, first impurity regions located at both sides of the common floating gate in the... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070148852 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a gate oxide layer including an oxide layer containing a large amount of nitrogen on a semiconductor substrate on which an input/output (I/O) region including an NMOS region and a PMOS region are defined,... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148853 - Novel masked nitrogen enhanced gate oxide: A method for fabricating improved integrated circuit devices. The method enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the... Agent: James R. Duzan Trask Britt

20070148854 - Nonvolatile semiconductor memory device and method of manufacturing the same: A nonvolatile semiconductor memory device whose gate structure of a transistor other than a memory cell transistor has a same stacked gate structure as the memory cell transistor, the gate structure comprising a semiconductor substrate, a first insulation film provided on the semiconductor substrate, a first conductive film provided on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070148856 - Method of forming pip capacitor: A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor includes the steps of forming a lower electrode of a first polysilicon layer over a semiconductor substrate, forming a dielectric layer over the lower electrode, forming a second polysilicon layer over the dielectric layer, patterning the second polysilicon layer, implanting impurities into... Agent: Sherr & Nourse, PLLC

20070148855 - Phase change memory device and fabricating method therefor: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase... Agent: Morris Manning Martin LLP

20070148857 - Independently controlled, double gate nanowire memory cell with self-aligned contacts: A doubled gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.... Agent: Blakely Sokoloff Taylor & Zafman

20070148858 - Method for forming metal contact in semiconductor device: A method for forming a metal contact in a semiconductor device includes forming bit lines over a substrate defined into a cell region and a peripheral region, forming a first inter-layer dielectric (ILD) layer over the bit lines, forming a first etch stop layer over the first ILD layer, forming... Agent: Blakely Sokoloff Taylor & Zafman

20070148859 - Method for producing a chip card contact zone: A method for producing a contact zone for a chip card has the following steps. A sheet having a first surface and a second surface opposite the first surface. Forming at least one insulating trench, which extends from the first surface to the second surface. A cluster layer is applied... Agent: Dickstein Shapiro LLP

20070148860 - Method for selective epitaxial growth of source/drain areas: One inventive aspect relates to a method of selective epitaxial growth of source/drain (S/D) areas. The method comprises providing a substrate of semiconductor material, the substrate comprising a first substrate area and a second substrate area, the first area comprising at least one gate stack. The method further comprises applying... Agent: Knobbe Martens Olson & Bear LLP

20070148863 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate lines over a substrate, wherein the substrate is defined into a cell region and a peripheral region, forming a gate spacer layer over the gate lines, the gate spacer layer including a buffer... Agent: Blakely Sokoloff Taylor & Zafman

20070148870 - Method for forming common source line in nor-type flash memory device: Disclosed is a method for forming a common source line of a NOR-type flash memory. The method includes the steps of forming a photoresist pattern, which is used for exposing a common source area, on a plurality of stack gates formed on a semiconductor substrate, selectively etching a field oxide... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148866 - Method of manufacturing eeprom device: A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of the semiconductor substrate exposed through the mask pattern; forming... Agent: Sherr & Nourse, PLLC

20070148864 - Method of manufacturing flash memory device: According to yet another embodiment, a method for forming a non-volatile memory device includes etching a substrate to form first and second trenches. The first and second trenches are filled with an insulating material to form first and second isolation structures. A conductive layer is formed over the first and... Agent: Townsend And Townsend And Crew, LLP

20070148865 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device includes forming a first polysilicon layer over a semiconductor substrate to form a floating gate. A tunnel dielectric layer is formed over the first polysilicon layer. A second polysilicon layer and a tungsten silicide layer are formed over the tunnel dielectric film... Agent: Townsend And Townsend And Crew, LLP

20070148861 - Method of manufacturing non-volatile memory: The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure is lower than that of the... Agent: Jianq Chyun Intellectual Property Office

20070148868 - Method of manufacturing non-volatile memory device: A method of manufacturing a non-volatile memory device includes the steps of: defining an active region on a semiconductor substrate; forming a charge storage layer on the active region; forming a first conductive pattern on the charge storage layer, wherein the first conductive pattern has a bottom portion larger in... Agent: Mayer, Brown, Rowe & Maw LLP

20070148869 - Method of manufacturing phase-change memory element: Disclosed is a method of manufacturing a phase-change memory in which the lower electrode of the phase-change memory device is formed using barrier metal for forming a metal interconnection and a via in damascene and dual damascene processes. The method includes the steps of patterning an insulating layer on a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148867 - Nonvolatile memory devices having floating gates and method of fabricating the same: A nonvolatile memory device includes a liner covering a sidewall and bottom of a trench that defines an active field in a substrate and a field isolation film disposed on the liner which fills the trench. The nonvolatile memory device further includes a floating gate disposed on the active field... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070148862 - Phase-change memory layer and method of manufacturing the same and phase-change memory cell: A phase-change memory layer and method for manufacturing the same and a phase-change memory cell are provided. The phase-change memory layer is crystallized by adding one or more heterogeneous crystals that do not react with phase-change materials as the crystal nucleus, so as to reduce the time for transforming to... Agent: Rabin & Berdo, PC

20070148871 - Erasable and programmable read only memory (eprom) cell of an eprom device and method of manufacturing a semiconductor device having the eprom cell: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device... Agent: F. Chau & Associates, LLC

20070148872 - Method of forming floating gate array of flash memory device: The method of forming a floating gate array of a flash memory device includes: (a) forming a plurality of device isolations, which define active device regions, in a semiconductor substrate, the device isolations being formed such that upper portions thereof protrude from a surface of the substrate by a predetermined... Agent: Mayer, Brown, Rowe & Maw LLP

20070148873 - Method of forming transistors with ultra-short gate feature: A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of... Agent: Townsend And Townsend And Crew, LLP

20070148874 - Integrated semiconductor device and method of manufacturing thereof: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type... Agent: Mcdermott Will & Emery LLP

20070148875 - Common drain dual semiconductor chip scale package and method of fabricating same: A common drain dual MOSFET chip scale package and a method of fabricating same are provided. The method of fabricating a plurality of common drain dual MOSFET chip scale packages includes the steps of providing a wafer having a plurality of common drain dual MOSFET devices disposed thereon, insulating a... Agent: Fortune Law Group LLP

20070148876 - Method for fabricating semiconductor device with dual poly-recess gate: A method for fabricating a semiconductor device includes: forming a first polysilicon layer of a first conductive type over a substrate divided into a cell region and a peripheral region, the first polysilicon layer covering the peripheral region and opening predetermined recess portions of the cell region; etching the predetermined... Agent: Blakely Sokoloff Taylor & Zafman

20070148877 - Semiconductor device and method for fabricating the same: A semiconductor device capable of preventing a bridge generation during performing an etching process to form a plurality of gate structures on a substrate divided into an active region and a field region and an electrical short between a contact plug and the individual gate structure in the field region... Agent: Blakely Sokoloff Taylor & Zafman

20070148878 - Method of manufacturing split gate type non-volatile memory device: A method of manufacturing a split gate type non-volatile memory device includes the steps of defining an active region on a semiconductor substrate; forming a pair of first conductive film patterns, each having an electric charge storage layer interposed between the substrate and the first conductive film pattern, on the... Agent: Mayer, Brown, Rowe & Maw LLP

20070148879 - Iii-v compound semiconductor heterostructure mosfet with a high workfunction metal gate electrode and process of making the same: A method of forming a metal-insulator-compound semiconductor structure comprises providing an insulator layer overlying a compound semiconductor substrate, the insulator layer having a surface, and forming a metal layer on the surface of the insulator layer using metal organic chemical vapor deposition.... Agent: Freescale Semiconductor, Inc. Law Department

20070148880 - Method of manufacturing a sonos memory: A method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory is provided herein. In the method, a bottom silicon oxide layer is formed over a substrate. A patterned mask layer having a trench therein is formed over the bottom silicon oxide layer. A charge-trapping layer is formed over the substrate covering the... Agent: Jianq Chyun Intellectual Property Office

20070148881 - Hybrid sti stressor with selective re-oxidation anneal: A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI... Agent: Slater & Matsil, L.L.P.

20070148882 - Method for making pmc type memory cells: This invention relates to a microelectronic device provided with one or several cells or elements comprising at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode, said stack comprising: at least one doped chalcogenide... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070148883 - Method for manufacturing a semiconductor device: Embodiments relate to a method of manufacturing a semiconductor device. According to embodiments, the method may include forming a first and a second insulating layer on a semiconductor substrate of which an active area and an isolation region are defined, forming a first and a second insulating layer pattern by... Agent: Sherr & Nourse, PLLC

20070148884 - Method of forming a recess channel trench pattern, and fabricating a recess channel transistor: A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern.... Agent: Marger Johnson & Mccollom, P.C.

20070148885 - Method of fabricating semiconductor device with dual gate structure: A method for fabricating a semiconductor device with a dual gate structure is provided. The method includes: forming a gate oxide layer over a substrate; forming a gate conductive layer over the gate oxide layer; forming an amorphous carbon layer over the gate conductive layer; forming a photosensitive pattern over... Agent: Townsend And Townsend And Crew, LLP

20070148886 - Method for gate electrode height control: One inventive aspect relates to a method of controlling the gate electrode in a silicidation process. The method comprises applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor... Agent: Knobbe Martens Olson & Bear LLP

20070148887 - Method for manufacturing semiconductor device: Embodiments relate to a method for manufacturing a semiconductor device. According to embodiments, a gate insulating layer and a conductive layer may be formed on a semiconductor substrate. The conductive layer may be selectively etched to form a relatively thick portion of the conductive layer in a gate region and... Agent: Sherr & Nourse, PLLC

20070148888 - System and method for the manufacture of semiconductor devices by the implantation of carbon clusters: A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach:... Agent: Patent Administrator Katten Muchin Rosenman LLP

20070148889 - Method for manufacturing a bipolar transisstor: Disclosed is a method for manufacturing a bipolar transistor. The method includes the steps of forming a well area, which is doped with a first conductive type material, on a semiconductor substrate, forming a base area, which is doped with the first conductive type material, by performing an ion implantation... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148890 - Oxygen enhanced metastable silicon germanium film layer: A method for pseudomorphic growth and integration of a strain-compensated metastable and/or unstable compound base having incorporated oxygen and an electronic device incorporating the base is described. The strain-compensated base is doped by substitutional and/or interstitial placement of a strain-compensating atomic species. The electronic device may be, for example, a... Agent: Schneck & Schneck

20070148891 - Method for manufacturing bipolar transistor: A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148892 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers... Agent: Fish & Richardson P.C.

20070148893 - Method of forming a doped semiconductor portion: A method of forming a doped semiconductor portion includes providing a semiconductor substrate with a surface, and providing protruding portions of a covering layer on the substrate surface, where the portions are arranged in a pattern of lines or segments of lines extending in a first direction. Portions of a... Agent: Edell, Shapiro & Finnan, LLC

20070148894 - Semiconductor device and method for regional stress control: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried... Agent: Freescale Semiconductor, Inc. Law Department

20070148895 - Integrateable capacitors and microcoils and methods of making thereof: Methods for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A method for integrally forming a capacitor and a microcoil on a substrate may involve depositing and patterning a dielectric layer on the substrate, depositing and patterning a sacrificial layer on the substrate,... Agent: Oliff & Berridge, PLC

20070148896 - Memory with memory cells that include a mim type capacitor with a lower electrode made for reduced resistance at an interface with a metal film: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection... Agent: Sughrue Mion, PLLC

20070148897 - Method for fabricating capacitor in semiconductor device: A method for fabricating a capacitor in a semiconductor device is provided. The method includes forming an insulation layer over a substrate; flushing a metal source onto the insulation layer to change a characteristic of a surface of the insulation layer to improve adherence of a metal-based material to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148899 - Capacitor and manufacturing method thereof: A capacitor in a trench having a depth, the trench formed in an area on a silicon substrate; an insulation layer formed on a surface of the trench and the silicon substrate; a first polysilicon layer formed on the insulation layer; a first dielectric layer formed and patterned on the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070148898 - Method for forming capacitor: A method for forming a capacitor is provided. In an embodiment of the method, a lower electrode of the capacitor is formed on a semiconductor substrate. An insulating layer and a metal layer are sequentially deposited on the lower electrode of the capacitor, and a photoresist pattern is formed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148900 - Surface-mount capacitor and method of producing the same: A surface-mount capacitor includes a multilayer capacitor structure formed by laminating plate-like capacitor elements each having anode lead portions at opposite ends thereof and a cathode portion at the center, an anode terminal connected to each anode lead portion via a strip-like plate, and a cathode terminal connected to the... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070148901 - Method for manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes the steps of forming a nitride film over a semiconductor substrate, forming at least one trench in the semiconductor substrate and forming an insulation film over the nitride film and in said at least one trench. The method further comprises the steps... Agent: Sherr & Nourse, PLLC

20070148904 - Device and method for controlling high density plasma chemical vapor deposition apparatus: An HDP-CVD apparatus includes a valve assembly, a pump, and a control unit for adjusting the supply of He gas to be within a preset range through control of the valve assembly and the pump so that an actual wafer temperature, which was previously determined, is maintained at a preset... Agent: Sherr & Nourse, PLLC

20070148903 - Method for fabricating sti gap fill oxide layer in semiconductor devices: A method for fabricating an STI gap fill oxide layer in a semiconductor device is provided. The method can include: forming a shallow trench for forming an STI on a semiconductor substrate; forming an STI liner oxide layer in the shallow trench for the STI; depositing an APCVD oxide layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148906 - Method of fabricating a semiconductor device: Embodiments relate to a semiconductor device and a method for fabricating a semiconductor device. In embodiments, the method may include forming a gate dielectric layer on an active region of a semiconductor substrate defined by an isolation region to form a gate conductive layer pattern, etching the isolation region of... Agent: Sherr & Nourse, PLLC

20070148905 - Method of forming a trench isolation layer in a semiconductor device: Embodiments relate to a method of forming a trench isolation layer in a semiconductor device. In embodiments, the method may include sequentially stacking a pad oxide layer and a pad nitride layer having a first thickness on a semiconductor substrate, forming a pad oxide pattern and a pad nitride pattern,... Agent: Sherr & Nourse, PLLC

20070148902 - Semiconductor device: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device, which may reduce damage due to stress of an STI bottom corner during an ion implantation and annealing being subsequent process of an STI in a semiconductor process are provided. According to embodiments, a method may... Agent: Sherr & Nourse, PLLC

20070148907 - Method of forming isolation layer of semiconductor device: There is provided a method of forming an isolation layer which prevents a failure from occurring depending on a difference in the area of the isolation layer during a planarization process of the isolation layer having a shallow trench isolation (STI) structure. The present invention implements a uniform isolation layer... Agent: Mayer, Brown, Rowe & Maw LLP

20070148908 - Method of forming trench isolation layer of semiconductor device: A trench isolation layer has rounded profiles on the top edges of a semiconductor substrate exposed by moats to prevent device characteristics from being degraded. The method of forming the trench isolation layer includes etching a device isolation trench in a semiconductor substrate using a hard mask layer pattern, forming... Agent: Sherr & Nourse, PLLC

20070148909 - Shallow trench isolation region in semiconductor device and method of manufacture: A method of forming a device isolation region in a semiconductor device is capable of completely removing an oxide layer for trench formation in a central region of the semiconductor device without forming a moat in an edge region. The method begins with forming a sacrificial oxide and sacrificial nitride... Agent: Sherr & Nourse, PLLC

20070148912 - Method for manufacturing direct bonded soi wafer and direct bonded soi wafer manufactured by the method: There are provided a method for manufacturing a direct bonded SOI wafer in which the entire buried oxide film layer is covered and not exposed and a direct bonded SOI wafer. This is the improvement of a method for manufacturing a direct bonded SOI wafer comprising the process of (A)... Agent: Reed Smith, LLP Attn: Patent Records Department

20070148910 - Process for simplification of a finishing sequence and structure obtained thereby: The invention relates to a process for the formation of a structure comprising a thin layer made of semiconductor material on a substrate, including the steps of providing a zone of weakness in a donor substrate; bonding the donor substrate to a support substrate; detaching a portion of the donor... Agent: Winston & Strawn LLP Patent Department

20070148911 - Wafer bonding method: A wafer bonding method, comprising steps of: coating a medium layer respectively on the surfaces of two wafers; removing impurities formed on the surface of each medium layer; laminating the two wafers while enabling the surface coated with the medium layer of one of the two wafers to face the... Agent: Bruce H. Troxell

20070148915 - Device and method for cutting an assembly: A method is presented for cutting an assembly that includes two layers of material having a first surface and a second surface. The method includes providing a weakened interface between the two layers that defines an interface ring about the periphery of the assembly, providing a high-pressure zone at the... Agent: Winston & Strawn LLP Patent Department

20070148913 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. In particular, a method for removing unwanted material layers from an edge and lower bevel region of a wafer is provided. The method includes performing a first etch of an edge region of a wafer having material layers formed thereon, coating... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148914 - Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer: A processing time required for regeneration of a layer transferred wafer is reduced and the regeneration cost is lowered, while a removal amount at the regeneration is decreased the number of regeneration times is increased. A main surface of a semiconductor wafer (13) has a main flat portion (13d) and... Agent: Reed Smith, LLP Attn: Patent Records Department

20070148917 - Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer: The regeneration cost is reduced when a layer transferred wafer is to be reused two times or more. Ions are implanted into a semiconductor wafer (13) to form an ion implanted area (13b) inside the semiconductor wafer (13), and a first laminated body (16) in which the wafer (13) is... Agent: Reed Smith, LLP Attn: Patent Records Department

20070148916 - Semiconductor surface protecting sheet and method: Provided are a semiconductor surface protecting method and surface protecting sheet employing a material having adequate conformability for irregularities on semiconductor wafer circuit sides and sufficient rigidity as a support during grinding, and which does not become fluid with repeated temperature increases. Also provided is a surface protecting sheet for... Agent: 3m Innovative Properties Company

20070148918 - Method for fabricating a chip scale package using wafer level processing: Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the... Agent: Trask Britt, P.C./ Micron Technology

20070148920 - Fabrication method and fabrication apparatus of group iii nitride crystal substance: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group... Agent: Mcdermott Will & Emery LLP

20070148919 - Multi-step epitaxial process for depositing si/sige: A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148921 - Mixed orientation semiconductor device and method: A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and... Agent: Slater & Matsil LLP

20070148922 - Method of fabricating semiconductor device: In a manufacturing process of a semiconductor device using a substrate having low heat resistance, such as a glass substrate, there is provided a method of efficiently carrying out crystallization of a semiconductor film and gettering treatment of a catalytic element used for the crystallization by a heating treatment in... Agent: Nixon Peabody, LLP

20070148923 - Nitride semiconductor device and method of manufacturing the same: The present invention provides a nitride semiconductor device. The nitride semiconductor device comprises an n-type nitride semiconductor layer formed on a nitride crystal growth substrate. An active layer is formed on the n-type nitride semiconductor layer. A first p-type nitride semiconductor layer is formed on the active layer. A micro-structured... Agent: Lowe Hauptman Berner, LLP

20070148924 - Mask pattern, method of fabricating thin film transistor, and method of fabricating organic light emitting display device using the same: A method of fabricating a polycrystalline silicon thin film for a thin film transistor (TFT), a mask pattern used for the method, and a method of fabricating a flat panel display device using the method and the mask pattern. In one embodiment, a mask pattern includes a plurality of regions,... Agent: Christie, Parker & Hale, LLP

20070148925 - Laser apparatus, laser annealing method, and manufacture method of a semiconductor device: To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser... Agent: Eric Robinson

20070148927 - Isolation structure of semiconductor device and method for forming the same: Embodiments of an isolation structure and method of forming the same are disclosed, and may include a shallow trench isolation region formed on a semiconductor substrate, and an isolation layer that may include a first oxide layer, a plurality of silicon nitride layers and silicon oxide layers, and a second... Agent: Sherr & Nourse, PLLC

20070148926 - Dual halo implant for improving short channel effect in three-dimensional tri-gate transistors: A method for providing halo implants in a tri-gate structure is described. Implantation is performed at two different angels to assure a halo for the top transistor and a halo for the side transistors.... Agent: Blakely Sokoloff Taylor & Zafman

20070148928 - Apparatus and method for manufacturing semiconductor device: Disclosed is an apparatus for manufacturing a semiconductor device. The apparatus includes a chamber in which a process is performed, a plasma supply supplying plasma above the chamber, a plate for placing a processing target at a lower portion of the chamber, and an ion capturer capturing ions introduced from... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148929 - Method for manufacturing cmos image sensor: A method of manufacturing a CMOS (complementary metal oxide semiconductor) image sensor is provided. The method can include: providing a semiconductor substrate having a PMOS region, and a photodiode region; forming a gate on the semiconductor substrate; implanting a low concentration of n-type impurities only in the NMOS region to... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148930 - Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device: A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. The rich dopant layer created by... Agent: Dinsmore & Shohl LLP

20070148931 - Semiconductor device and method of fabricating the same: The present invention provides a semiconductor device, which comprises a first semiconductor layer of the first conductivity type having a plurality of trenches formed therein. A second semiconductor layer of the second conductivity type composed of an epitaxial layer is buried in the trenches in the first semiconductor layer. The... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070148933 - Nonvolatile memory device and method of fabricating the same: A method of fabricating a phase-change random-access memory (RAM) device includes forming a chalcogenide material on a substrate. A bottom contact is formed under the chalcogenide material, the bottom contact comprising TiAlN. Forming the bottom contact includes performing an atomic layer deposition (ALD) process, the ALD process including introducing an... Agent: Mills & Onello LLP

20070148932 - Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition... Agent: Mueting, Raasch & Gebhardt, P.A.

20070148935 - Implantation of gate regions in semiconductor device fabrication: A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer... Agent: Schmeiser, Olsen & Watts

20070148936 - Manufacturing method of semiconductor device: To provide a manufacturing method of a semiconductor device with a reduced chip area by reducing the size of a pattern for forming an integrated circuit. For example, the size of an IC chip that is provided as an application of IC cards or IC tags can be reduced. The... Agent: Nixon Peabody, LLP

20070148934 - Method for fabricating semiconductor device with bulb shaped recess gate pattern: A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148937 - Semiconductor device and manufacturing method of semiconductor device: Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148938 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device is provided. The method includes: forming an isolation layer over a substrate to define a field region and an active region; forming a step coverage layer over the isolation layer; and forming a plurality of gate lines traversing the field region and the... Agent: Blakely Sokoloff Taylor & Zafman

20070148939 - Low leakage heterojunction vertical transistors and high performance devices thereof: A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source... Agent: Scully Scott Murphy & Presser, PC

20070148940 - Method for manufacturing a semiconductor device: Provided is a method for manufacturing a semiconductor device. In the method, a gate is formed in an active region of a substrate with a gate insulation layer interposed between the gate and the substrate. Spacers are formed on lateral sides of the gate. A first metal layer is deposited... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148943 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. This method includes the step of forming a diffusion barrier film, which is interposed between a silicon film and a metal film and functions to prevent diffusion between the silicon and metal films. The diffusion barrier film is formed of a... Agent: Ladas & Parry LLP

20070148944 - Interconnection of semiconductor device and method for manufacturing the same: A method for manufacturing an interconnection of a semiconductor device is provided. The method can include the steps of: forming an interlayer dielectric layer on a semiconductor substrate; forming a damascene pattern on the interlayer dielectric layer; depositing a seed layer on the interlayer dielectric layer; depositing a metal layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148942 - Method for fabricating contact hole of semiconductor device: A method for forming a contact hole of a semiconductor device includes: forming a lower pattern over a substrate; forming a spin-on-glass (SOG) layer over the lower pattern; performing a first curing process on the SOG layer; forming an opening exposing a portion of the SOG layer; performing a second... Agent: Blakely Sokoloff Taylor & Zafman

20070148945 - Method for forming a fine pattern of a semiconductor device: Embodiments relate to a method for forming a fine pattern of a semiconductor device. According to embodiments, the method for forming a fine pattern of a semiconductor device may include forming a first oxide layer on a semiconductor substrate, forming a photoresist pattern on the first oxide layer, forming a... Agent: Sherr & Nourse, PLLC

20070148941 - Microelectronic component with photo-imageable substrate: Methods for making a microelectronic component including a plurality of conductive posts extending and projecting away from a flexible substrate, wherein at least some of the conductive posts are electrically connected to a plurality of traces exposed on the flexible substrate.... Agent: Tessera Lerner David Et Al.

20070148946 - Multi-layered metal wiring structure of semiconductor device and manufacturing method thereof: A multi-layered metal wiring structure of a semiconductor device includes an interlayer insulating film including an oxide film, a titanium oxide film deposited on the interlayer insulating film, and an aluminum film deposited on the titanium oxide film. The interlayer insulating film includes a FSG film and a silicon oxide... Agent: Mayer, Brown, Rowe & Maw LLP

20070148947 - Semi-conductor device with inductive component and method of making: An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top... Agent: Robert A. Parsons

20070148948 - Image forming system, image forming apparatus and device, and recording medium: An image forming system including a first image forming apparatus and a second image forming apparatus that are connected to each other via a network, the first image forming apparatus, comprising: a transmitter unit transferring reproduced data of data for transfer to the second image forming apparatus via the network;... Agent: Buchanan, Ingersoll & Rooney PC

20070148949 - Nanostructure-based package interconnect: An embodiment of the present invention is an interconnect technique. A nanostructure bump is formed on a die. The nanostructure bump has a template defining nano-sized openings and metallic nano-wires extending from the nano-sized openings. The die is attached to a substrate via the nanostructure bump.... Agent: Blakely Sokoloff Taylor & Zafman

20070148950 - Object and bonding method thereof: A bonding method of an object having at least one pad on a surface of the object includes the steps of: putting a mask on the object, when the mask has at least one pattern corresponding to the pad; and printing to form a solder ball on the pad by... Agent: Birch Stewart Kolasch & Birch

20070148951 - System and method for flip chip substrate pad: According to some embodiments, a method, a system, and an apparatus to provide a flip chip conductive bump pad that has a dome shaped area. In some embodiments, the method includes providing a substrate having a conductive bump pad on a first surface of the substrate and forming a dome... Agent: Buckley, Maschoff & Talwalkar LLC

20070148952 - Conformal electroless deposition of barrier layer materials: Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof,... Agent: Intel Corporation C/o Intellevate, LLC

20070148953 - Method for fabricating semiconductor device and method for fabricating magnetic head: The method comprises the step of forming an interconnection trench 38 in an inter-layer insulation film 34, the step of forming an interconnection layer 44 of Cu as the main material in the interconnection trench 38, and the step of performing nitrogen-two-fluid processing of concurrently spraying pure water with ammonia... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070148955 - Method for forming metal lines in a semiconductor device: A method for forming metal lines in a semiconductor device includes forming a first insulating film having a via hole over a semiconductor substrate with a conductive layer, forming a via metal line for filling the via hole, forming, over the first insulating film, a second insulating film having a... Agent: Sherr & Nourse, PLLC

20070148956 - Method of forming fuse region in semiconductor damascene process: A method of forming a fuse region in a semiconductor damascene process in which a specific layer is formed to prevent corrosion and re-connection of a severed part of the fuse region to prevent malfunction. A first conductive layer is formed over a substrate and an interlayer dielectric layer is... Agent: Sherr & Nourse, PLLC

20070148957 - Method of manufacturing metal insulating layer in semiconductor device: A method of forming a metal insulating layer of a semiconductor device relieves stress due to differential thermal expansion between insulating sub-layers by rounding off sharp edges formed between the sub-layers. A first metal insulating sub-layer is formed over a metal interconnection layer pattern. The first metal insulating sub-layer has... Agent: Sherr & Nourse, PLLC

20070148954 - Method of manufacturing semiconductor device: A method of manufacturing semiconductor devices, including the steps of forming an interlayer insulating layer over a semiconductor substrate in which a predetermined structure including a drain is formed, etching a part of the interlayer insulating layer to form a contact hole, and then forming a first conductive film on... Agent: Marshall, Gerstein & Borun LLP

20070148959 - Method of manufacturing a semiconductor device having a pre-metal dielectric liner: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor device having a pre-metal dielectric liner. In embodiments, method for forming a semiconductor device may include forming a pre-metal dielectric liner, which has a multi-layer structure including a plurality of interfacial surfaces, on an entire surface of... Agent: Sherr & Nourse, PLLC

20070148960 - Semiconductor device and method for manufacturing the same: A method of manufacturing a metal wiring in a semiconductor device includes: forming a via hole by selectively etching an interlayer insulating layer formed on a first metal layer; sequentially forming a first barrier metal layer and a second metal layer on the interlayer insulating layer; etching the first barrier... Agent: Mayer, Brown, Rowe & Maw LLP

20070148958 - Structure to improve adhesion between top cvd low-k dielectric and dielectric capping layer: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion... Agent: Steven Fischman, Scully, Scott, Murphy & Presser

20070148961 - Semiconductor device and method for manufacturing the same: A semiconductor device and method with a dual damascene pattern uses buffer layers to prevent photoresist layer poisoning due to a reaction between an interlayer dielectric and a photoresist layer. Embodiments also relate to reducing the effects of plasma damage occurring during an etching or ashing process.... Agent: Sherr & Nourse, PLLC

20070148964 - Method for forming contact hole in semiconductor device: A method for forming a contact hole in a semiconductor device includes forming gate lines on a substrate, forming a bit line pattern by forming a bit line and a bit line hard mask in sequential order over the substrate, forming an inter-layer insulation layer having a multiple-layer structure including... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070148965 - Method and composition for plasma etching of a self-aligned contact opening: A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer with at least one fluorocarbon and ammonia.... Agent: Dickstein Shapiro LLP

20070148963 - Semiconductor devices incorporating carbon nanotubes and composites thereof: Methods of utilizing carbon nanotubes or composites thereof as hole plugs in vias or in contact holes for connecting conductive layers in integrated circuits are disclosed. Integrated circuits and integrated circuit layers formed by the methods are also disclosed.... Agent: Heslin Rothenberg Farley & Mesiti PC

20070148962 - Single, multi-walled, functionalized and doped carbon nanotubes and composites thereof: The present invention relates to single walled and multi-walled carbon nanotubes (CNTs), functionalized CNTs and carbon nanotube composites with controlled properties, to a method for aerosol synthesis of single walled and multi-walled carbon nanotubes, functionalized CNTs and carbon nanotube composites with controlled properties from pre-made catalyst particles and a carbon... Agent: Young & Thompson

20070148967 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070148966 - Method of forming an interconnect structure: A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and... Agent: Schmeiser, Olsen & Watts

20070148968 - Method of forming self-aligned double pattern: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the... Agent: Harness, Dickey & Pierce, P.L.C

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