Semiconductor device manufacturing: process inventions 05/07

20070122917 - Forming method of ferroelectric capacitor and manufacturing method of semiconductor device: Disclosed is a ferroelectric capacitor forming method of allowing a FeRAM to be stably mass-produced. In forming the ferroelectric capacitor for the FeRAM, a PZT layer is formed on a lower electrode layer by a sputtering method. Then, a first RTA treatment for crystallizing the PZT is performed in an... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070122918 - Method for fabricating microstructure and a microstructure formed using the method: A method for fabricating a microstructure includes forming a negative type photoresist film with a predetermined thickness on a substrate, removing solvent remaining in the photoresist film by a first heat treatment of the photoresist film, exposing the photoresist film with ultraviolet light having an energy of about 200 mJ/cm2... Agent: Cantor Colburn, LLP

20070122919 - Method of producing an integrated circuit arrangement with field-shaping electrical conductors: An integrated circuit arrangement includes at least one electrical conductor that, when a current flows through it, produces a magnetic field that acts on at least a further part of the circuit arrangement, wherein seen in cross section, the electrical conductor has at least one recess or depression, or a... Agent: Lerner Greenberg Stemer LLP

20070122920 - Method for improved control of critical dimensions of etched structures on semiconductor wafers: A system for real-time monitoring and control of critical dimensions during semiconductor wafer fabrication is provided. The system measures structures in situ, that is, as they are being etched onto a wafer layer.... Agent: Duke W. Yee Yee & Associates, P.C.

20070122921 - Copper wiring module control: Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially,... Agent: Fish & Richardson P.C.

20070122922 - Platform asic reliability: A method for monitoring a fabrication of a circuit is disclosed. The method generally includes a step of (A) fabricating a chip only up to and including a first metal layer such that (i) a core region of the chip may has an array of cells, (ii) each of the... Agent: Lsi Logic Corporation

20070122923 - Flat panel display and method for making the same: A flat panel display capable of preventing a chipping phenomenon of a pixel definition layer, and a method for making the same are disclosed. The flat panel display includes a thin film transistor formed on a substrate; a planarization layer formed on the thin film transistor; a first electrode layer... Agent: Knobbe Martens Olson & Bear LLP

20070122925 - Flip-chip nitride light emitting device and method of manufacturing thereof: A flip-chip light emitting device and a method of manufacturing thereof are provided. The flip-chip nitride light emitting device includes a substrate, an n type clad layer, an active layer, a p type clad layer, a multi ohmic contact layer, and a reflective layer, which are stacked in this order,... Agent: Buchanan, Ingersoll & Rooney PC

20070122924 - Method of fabricating metal oxide semiconductor transistor: A masking layer is formed over a substrate. The substrate and the masking layer are patterned to form trenches that partitions the substrate into first doping type semiconductor strips. An isolation layer is formed inside the trenches such that the surface of the isolation layer is below the upper surface... Agent: Jianq Chyun Intellectual Property Office

20070122926 - Substrate layer cutting device and method: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member... Agent: Winston & Strawn LLP Patent Department

20070122928 - Electro-optical device, method of manufacturing the same, and electronic apparatus: A method of manufacturing an electro-optical device, the electro-optical device having an electro-optical element formed by laminating a first electrode, an electro-optical layer, and a second electrode in sequence on a base body, the method of manufacturing the electro-optical device, including the steps of: forming an ultraviolet absorbing layer on... Agent: Oliff & Berridge, PLC

20070122927 - Electrochemical cell structure and method of fabrication: One limitation to the realisation of mass produced electrochemical cells is a lack of high resolution patterning techniques providing accurate-alignment. Accordingly a method of fabricating a patterned structure in the manufacture of an electrochemical cell comprising a soft-contact printing and ink-jet printing is provided.... Agent: Oliff & Berridge, PLC

20070122929 - Method and zone for sealing between two microstructure substrates: The invention concerns a sealing zone between two microstructure substrates. Said sealing zone comprises at least the following parts: on a first wafer level (20), a lower edging (22A) made of an adhesive material capable of causing the first substrate (20) to adhere to a sealing material, said sealing material... Agent: Brinks Hofer Gilson & Lione

20070122930 - Electrochemical cell structure and method of fabrication: An electrochemical cell and a method of manufacturing the same is provided. The electrochemical cell comprises a first conductive layer; a metal oxide layer formed on the first conductive layer, the metal oxide layer comprising a plurality of adjacent metal oxide cells, spaced from one another; a functional dye layer... Agent: Oliff & Berridge, PLC

20070122931 - Electrochemical cell structure and method of fabrication: An electrochemical cell and a method of manufacturing the same are provided. The electrochemical cell comprises a first conductive layer; a metal oxide layer formed on the first conductive layer, the metal oxide layer comprising a plurality of adjacent metal oxide cells, spaced from one another; a functional dye layer... Agent: Oliff & Berridge, PLC

20070122932 - Methods and compositions for the formation of recessed electrical features on a substrate: Precursor compositions having a low conversion temperature and methods for the fabrication of recessed electrical features from the precursor compositions. The electrical features can be conductors, resistors and dielectric features. The precursor compositions are deposited into recessed features, such as trenches, formed in a substrate and are reacted at a... Agent: Jaimes Sher, Esq. Cabot Corporation

20070122933 - Electrochemical cell structure and method of fabrication: An electrochemical cell and a method of manufacturing the same are provided. The electrochemical cell comprises: a first conductive layer; a metal oxide layer provided on the first conductive layer, the metal oxide layer comprising a plurality of adjacent metal oxide cells, spaced from one another; a functional dye layer... Agent: Oliff & Berridge, PLC

20070122934 - Silicon-based photodetector and method of fabricating the same: A method of fabricating a photodetector device includes preparing a silicon substrate, forming a patterned mesa on the silicon substrate, and forming a patterned conductive layer over the patterned mesa.... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070122935 - Manufacturing method of solid-state imaging device, solid-state imaging device, and camera: A manufacturing method of a solid-state imaging device prevents generation of a space due to insufficient filling of a conductive material. Materials constituting a multilayer film 41 are sequentially deposited on a semiconductor substrate, and portions respectively included in a plug formation intended region and a surrounding region that surrounds... Agent: Mcdermott Will & Emery LLP

20070122936 - System for heat treatment of semiconductor device: Disclosed is a heat treatment system for semiconductor devices. The heat treatment system is used in a heat treatment process for semiconductor devices, such as a crystallization process for an amorphous silicon thin film or a dopant activation process for a poly-crystalline silicon thin film formed on a surface of... Agent: Hyun Jong Park Tuchman & Park LLC

20070122937 - Method of manufacturing light emitting device: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070122938 - Organic electroluminescent display device: In order to solve the above problem, in an organic EL display 10 of the present invention having a plurality of display device 20 provided onto a substrate 30, the display devices includes: an anode electrode 31 arranged on the substrate, a cathode electrode 32 arranged adjacently to the anode... Agent: Hogan & Hartson L.L.P.

20070122939 - Organic light emitting device: The instant disclosure relates to an organic light emitting device with an improved blue light emitting efficiency. One embodiment of the organic light emitting device has an advantageous effect of increasing the blue light emitting efficiency remarkably without changing other elements' properties by forming organic layers including compounds having specific... Agent: Knobbe Martens Olson & Bear LLP

20070122940 - Method for packaging a semiconductor device: A method for packaging a semiconductor device includes forming through holes (12) in a base substrate (10) and depositing a conductive material (14) on a first side (16) of the base substrate (10) to form a conductive layer (18) such that the conductive material (14) fills the through holes (12).... Agent: Freescale Semiconductor, Inc. Law Department

20070122941 - Terminal device communicating with contact-less ic media, and a communication method performed in the terminal device: The terminal device of the present invention comprises a transmitting means for transmitting, to a contact-less IC medium, commands and carrier signals used for receiving responses, a receiving means for receiving responses from the contact-less IC medium, and a controlling means for controlling at least one of the transmitting means... Agent: Fish & Richardson P.C.

20070122942 - Conforming template for patterning liquids disposed on substrates: The present invention includes a conforming template for patterning liquids disposed on substrates. The template includes a body having opposed first and second surfaces. The first surface includes a plurality of recessed regions with a patterning region being disposed between adjacent recessed regions. Specifically, the recessed regions define flexure regions... Agent: Molecular Imprints

20070122943 - Method of making semiconductor package having exposed heat spreader: A method of making a semiconductor package (50) includes attaching a bottom surface (54) of an integrated circuit (IC) die (52) to a base carrier (56) and electrically connecting the die (52) to the base carrier (56). A first surface (66) of a heat spreader (60) is attached to a... Agent: Freescale Semiconductor, Inc. Law Department

20070122944 - Individualized low parasitic power distribution lines deposited over active integrated circuits: An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by... Agent: Texas Instruments Incorporated

20070122945 - Methods of fabricating integrated circuit devices having fuse structures including buffer layers: An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of... Agent: Myers Bigel Sibley & Sajovec

20070122946 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070122947 - Metal compound, material for thin film formation, and process of forming thin film: wherein R1, R2, R3, and R4 each represent an alkyl group having 1 to 4 carbon atoms; A represents an alkanediyl group having 1 to 8 carbon atoms; M represents a lead atom, a titanium atom or a zirconium atom; n represents 2 when M is a lead atom or... Agent: Young & Thompson

20070122949 - Manufacturing method of thin film transistor: A manufacturing method of a thin film transistor is provided. A buffer layer is formed on a substrate, and then a first and a second poly-silicon island are formed thereon. A gate-insulating layer is formed on the substrate, and a first and a second gate are formed thereon. A sacrificed... Agent: Jianq Chyun Intellectual Property Office

20070122950 - Method for manufacturing conductive layer and semiconductor device: To provide a method for manufacturing a wiring, a conductive layer, a display device, and a semiconductor device, each of which can meet a large sized substrate and which is manufactured with a higher throughput by using a material efficiently, the conductive layer is formed over the substrate having an... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070122948 - Thin-film transistor and diode array for an imager panel or the like: Briefly, in accordance with one or more embodiments, a detector panel of an imaging system may be produced from a photodiode array integrated with a thin-film transistor array. The thin film transistor array may have one or more vias formed for increasing the adhesion of the photodiode array to the... Agent: General Electric Company Global Research

20070122951 - Self-aligned silicon carbide semiconductor devices and methods of making the same: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases.... Agent: Merchant & Gould PC

20070122952 - Semiconductor device with a dummy gate and a method of manufacturing a semiconductor device with a dummy gate: A dummy gate may be formed over an isolation layer. A sidewall spacer may be formed next to the dummy gate. The dummy gate and the sidewall spacer may substantially cover or completely cover the edge of isolation layer that is adjacent to an active area of a silicon substrate.... Agent: Sherr & Nourse, PLLC

20070122953 - Enhanced segmented channel mos transistor with high-permittivity dielectric isolation material: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Silcon Valley Patent Group LLP

20070122954 - Sequential selective epitaxial growth: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Silcon Valley Patent Group LLP

20070122960 - Antenna and manufacturing method thereof, semiconductor device including antenna and manufacturing method thereof, and radio communication system: An antenna includes a first substrate, a first pattern, a second substrate, a second pattern, and an anisotropic conductive material. The first substrate has an insulating surface. The first pattern is formed over the insulating surface of the first substrate, and made of a conductive material. The second substrate is... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070122957 - Low-cost feol for ultra-low power, near sub-vth device structures: In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2... Agent: Whitham, Curtis & Christofferson, P.C.

20070122959 - Method of forming gate of flash memory device: A method of forming a gate of a flash memory device, including the steps of sequentially forming a tunnel oxide film, a first polysilicon layer for a floating gate, a dielectric layer, a second polysilicon layer for a control gate, a tungsten silicide film, and a hard mask film on... Agent: Marshall, Gerstein & Borun LLP

20070122955 - Method of manufacturing a semiconductor structure: There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive... Agent: Charles N. J. Ruggiero Ohlandt Greeley Ruggiero & Perle L.L.P.

20070122958 - Spacer barrier structure to prevent spacer voids and method for forming the same: A semiconductor device includes a spacer adjacent a gate structure. A protection layer covers oxide portions of the spacer surface such that subsequent manufacturing operations such as wet oxide etches and strips, do not produce voids in the spacers. A method for forming the semiconductor device provides forming a gate... Agent: Duane Morris LLPIPDepartment (tsmc)

20070122956 - Transistor with dielectric stressor element fully underlying the active semiconductor region: A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is disposed. In particular, the dielectric stressor element... Agent: International Business Machines Corporation Dept. 18g

20070122961 - Method and structure for enhancing both nmosfet and pmosfet performance with a stressed film: A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or... Agent: International Business Machines Corporation Dept. 18g

20070122962 - Semiconductor cmos devices and methods with nmos high-k dielectric present in core region that mitigate damage to dielectric materials: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device.... Agent: Texas Instruments Incorporated

20070122963 - Latch-up prevention in semiconductor circuits: This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first doping region, wherein one or more semiconductor devices are disposed therein and coupling to a first supply voltage, a second doping region adjacent to the first doping region, wherein the second doping... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070122964 - Semiconductor device equipped with a voltage step-up circuit: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type... Agent: Hogan & Hartson L.L.P.

20070122965 - Stress engineering using dual pad nitride with selective soi device architecture: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of... Agent: Scully, Scott, Murphy & Presser, P.C.

20070122966 - Technique for enhancing stress transfer into channel regions of nmos and pmos transistors: A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to... Agent: Williams, Morgan & Amerson

20070122967 - Method for fabricating capacitor in semiconductor device: A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component... Agent: Townsend And Townsend And Crew, LLP

20070122968 - Fabrication method and structure for providing a recessed channel in a nonvolatile memory device: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially... Agent: Volentine Francos, & Whitt PLLC

20070122969 - Contact structure of semiconductor devices and method of fabricating the same: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070122970 - Methods of fabricating memory devices with memory cell transistors having gate sidewall spacers with different dielectric properties: A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and second sidewall spacers are disposed on respective ones... Agent: Myers Bigel Sibley & Sajovec

20070122974 - Eeprom: An EEPROM having a nonvolatile memory cell is provided. The nonvolatile memory cell has a first MOS transistor and a second MOS transistor. The first MOS transistor and the second MOS transistor have a gate electrode in common, the gate electrode being a floating gate electrically isolated from a surrounding... Agent: Mcginn Intellectual Property Law Group, PLLC

20070122973 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device, wherein, when a first polysilicon layer is formed, a doped polysilicon layer and an amorphous polysilicon layer are formed so that they are laminated. A process of forming a sidewall oxide film and an oxide film and a thermal treatment process are... Agent: Marshall, Gerstein & Borun LLP

20070122972 - Method of manufacturing nand flash memory device: A method of manufacturing a NAND flash memory device, including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined; simultaneously forming a plurality of cell gates on the semiconductor substrate of the cell region and forming selection gates on the... Agent: Marshall, Gerstein & Borun LLP

20070122971 - Vertical soi trench sonos cell: A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench... Agent: Scully Scott Murphy & Presser, PC

20070122975 - Mos transistor manufacturing: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070122976 - Flash memory device having recessed floating gate and method for fabricating the same: A flash memory device and a method for fabricating the same are provided. The flash memory device includes: an active region having a plurality of surface regions and a plurality of recess regions formed lower than the surface regions; a tunnel oxide layer formed over the recess regions; a plurality... Agent: Blakely Sokoloff Taylor & Zafman

20070122978 - Non-volatile memory device and fabrication method thereof: A non-volatile memory device includes a buffer oxide film on a substrate; a polysilicon layer on the buffer oxide film; a silicon oxy-nitride (SiON) layer on the polysilicon layer, a first insulator layer on the SiON layer, a nitride film on the first insulator, a second insulator layer on the... Agent: Lee & Morse, P.C.

20070122977 - Self-aligned pitch reduction: A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features... Agent: Beyer Weaver LLP

20070122979 - Semiconductor devices and methods of fabricating the same: Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed... Agent: Mills & Onello LLP

20070122980 - Flash memory array with increased coupling between floating and control gates: Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070122982 - Method of applying stresses to pfet and nfet transistor channels for improved performance: A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having... Agent: International Business Machines Corporation Dept. 18g

20070122981 - Method of fabricating semiconductor device having multiple gate insulating layer: A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing... Agent: F. Chau & Associates, LLC

20070122983 - Multi-operational mode transistor with multiple-channel device structure: A multiple operating mode transistor is provided in which multiple channels having different respective operational characteristics are employed. Multiple channels have threshold voltages that are independently adjustable. The independent adjustment of the threshold voltage includes providing at least one of different respective doping concentrations in the different channels, different respective... Agent: Mcdermott Will & Emery LLP

20070122984 - Structure and method for manufacturing strained finfet: A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively... Agent: Scully, Scott, Murphy & Presser, P.C.

20070122985 - Formation of active area using semiconductor growth process without sti integration: A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body.... Agent: Slater & Matsil LLP

20070122986 - Carbon nanotube field effect transistor and methods for making same: A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. In one embodiment, a method for forming a carbon nanotube transistor starts with a substrate comprised of a bottom dielectric, a carbon nanotube layer, and a top dielectric. A pillar is formed on the top... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070122987 - Method for fabricating an nmos transistor: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the... Agent: North America Intellectual Property Corporation

20070122988 - Methods of forming semiconductor devices using embedded l-shape spacers: A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of... Agent: Charles N. J. Ruggiero Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20070122989 - Epitaxial and polycrystalline growth of si1-x-ygexcy and si1-ycy alloy layers on si by uhv-cvd: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is... Agent: Scully, Scott, Murphy & Presser, P.C.

20070122990 - Method for producing epitaxial wafer with buried diffusion layer and epitaxial wafer with buried diffusion layer: There is disclosed a method for producing an epitaxial wafer with a buried diffusion layer comprising: implanting an impurity into a silicon single crystal wafer; subsequently diffusing the impurity in the wafer to form a diffusion layer; at least removing an oxide film on the diffusion layer; and thereafter forming... Agent: Oliff & Berridge, PLC

20070122991 - Resistor element and manufacturing method thereof: A method of manufacturing a resistive element of present invention comprises; (A) forming on a substrate, a polysilicon structure whose top layer is a polysilicon layer; (B) forming a metal layer on the polysilicon layer; (C) forming an upper barrier layer on the metal layer; and (D) forming a silicide... Agent: Sughrue Mion, PLLC

20070122992 - Electronic component manufacturing method and electronic component: The electronic component includes a base material, a capacitor unit, and a wiring portion. The capacitor unit has a stacked structure including a first electrode portion provided on the base material, a second electrode portion including a first surface opposing the first electrode portion and a second surface opposite to... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070122993 - Method of simultaneously fabricating isolation structures having rounded and unrounded corners: A method facilitates generally simultaneously fabricating a number of shallow trench isolation structures such that some selected ones of the shallow trench isolation structures have rounded corners and other selected ones of the shallow trench isolation structures do not have rounded corners. The method includes forming patterned photoresist over a... Agent: Stout, Uxa, Buyan & Mullins LLP

20070122994 - Nitride semiconductor light emitting element: A nitride semiconductor light-emitting element suppresses leakage currents and non-radiative recombination centers by providing, as an underlying layer of the active layer, a pit formation layer that reliably generates pits, while maintaining a good film quality, so that the internal quantum efficiency is improved, and the light-emitting characteristics are also... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070122995 - Controlled process and resulting device: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define... Agent: Townsend And Townsend And Crew, LLP

20070122996 - Epitaxial semiconductor layer and method: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070122998 - Active silicon device on a cleaved silicon-on-insulator substrate: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070122997 - Controlled process and resulting device: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define... Agent: Townsend And Townsend And Crew, LLP

20070123000 - Dicing tape attaching apparatus and dicing tape attaching method: A dicing tape attaching apparatus (10) comprises a fixed table (38) for supporting a mount frame (36), a movable table (31) for supporting a wafer (20) with the reverse surface thereof ground, and a height adjusting unit (70) such as a screw jack for adjusting the height of the movable... Agent: Christie, Parker & Hale, LLP

20070122999 - Method and apparatus for fabricating and connecting a semiconductor power switching device: Fabrication processes for manufacturing and connecting a semiconductor switching device are disclosed, including an embodiment for dicing a wafer into individual circuit die by sawing the interface between adjacent die with a saw blade that has an angled configuration across its width, preferably in a generally V-shape so that the... Agent: Roger D. Greer Greer, Burns & Crain, Ltd.

20070123001 - System and method for separating and packaging integrated circuits: A method of separating an IC. The method includes dicing a semiconductor wafer. The semiconductor wafer includes multiple ICs. The diced wafer is secured to a stretchable substrate. The stretchable substrate can be stretched so as to form corresponding spaces between each of the ICs. The corresponding spaces are filled... Agent: Martine Penilla & Gencarella, LLP

20070123002 - Wafer dividing method: The present invention grinds the rear surface side of a device area to form a recessed portion and an annular reinforcement part on the outer periphery of the recessed portion, removes the annular reinforcement part by grinding or cutting the rear surface of the annular reinforcement part so as to... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070123003 - Dielectric interface for group iii-v semiconductor device: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.... Agent: Blakely Sokoloff Taylor & Zafman

20070123005 - Film formation apparatus, method for forming film, and method for manufacturing photoelectric conversion device: The present invention relates to a film formation apparatus including a first transfer chamber having a roller for sending a substrate, a film formation chamber having a discharging electrode, a buffer chamber provided between the transfer chamber and the film formation chamber or between the film formation chambers, a slit... Agent: Nixon Peabody, LLP

20070123007 - Film-forming method and film-forming equipment: A plurality of wafers are loaded on a susceptor installed in a reaction chamber, and the wafers are heated, and process gas is fed from a plurality of stages of openings formed in a gas feed nozzle installed so as to pass through the center of the susceptor, the process... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070123004 - Method and apparatus for forming a crystalline silicon thin film: A hydrogen gas is supplied into a deposition chamber accommodating a silicon sputter target and a deposition target object, a high-frequency power is applied to said gas to generate plasma exhibiting Hα/SiH* from 0.3 to 1.3 between an emission spectral intensity Hα of hydrogen atom radicals at a wavelength of... Agent: Rader Fishman & Grauer PLLC

20070123008 - Method for controlling dislocation positions in silicon germanium buffer layers: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent and depositing a strained silicon germanium layer on the substrate. The dislocation inducing agent may include ions, electrons,... Agent: VistaIPLaw Group LLP

20070123006 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. In the substrate and the epitaxial layer, an N type buried diffusion layer is formed on a P type buried diffusion layer. With this structure, an upward... Agent: Fish & Richardson P.C.

20070123009 - Technique for increasing adhesion of metallization layers by providing dummy vias: By providing dummy vias below electrically non-functional metal regions, the risk for metal delamination in subsequent processes may be significantly reduced. Moreover, in some embodiments, the mechanical strength of the resulting metallization layers may be even more enhanced by providing dummy metal regions, which may act as anchors for an... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070123010 - Technique for reducing crystal defects in strained transistors by tilted preamorphization: By performing a tilted amorphization implantation and a subsequent re-crystallization on the basis of a stressed overlying material, a highly efficient strain-inducing mechanism is provided. The tilted amorphization implantation may result in a significantly reduced defect rate during the re-crystallization process, thereby substantially reducing leakage currents in sophisticated transistor elements.... Agent: Williams, Morgan & Amerson

20070123011 - Production process for high purity polycrystal silicon and production apparatus for the same: In the production process of the present invention for high purity polycrystal silicon, using a vertical reactor having a silicon chloride gas-feeding nozzle and a reducing agent gas-feeding nozzle which are disposed at an upper part and a waste gas discharge pipe, a silicon chloride gas and a reducing agent... Agent: J C Patents, Inc.

20070123012 - Plasma implantation of deuterium for passivation of semiconductor-device interfaces: A method for fabricating a semiconductor-based device includes providing a substrate including a semiconductor layer, forming a gate dielectric layer on the semiconductor layer, forming a plasma including deuterium, plasma implanting deuterium from the plasma into the substrate, and annealing the substrate to promote passivation of the interface between the... Agent: Varian Semiconductor Equipment Assc., Inc.

20070123013 - Controlled process and resulting device: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define... Agent: Townsend And Townsend And Crew, LLP

20070123014 - Method for fabricating semiconductor device having flask type recess gate: A method for fabricating a semiconductor device having a flask type recess gate includes forming a hard mask pattern on a substrate, etching the substrate to a predetermined depth using the hard mask pattern to form a first recess pattern, forming a passivation layer on sidewalls of the first recess... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070123016 - Device with gaps for capacitance reduction: A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The... Agent: Beyer Weaver LLP

20070123017 - Device with self aligned gaps for capacitance reduction: A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of... Agent: Beyer Weaver LLP

20070123018 - Electrically rewritable non-volatile memory element and method of manufacturing the same: A non-volatile memory element includes a lower electrode, an upper electrode, a recording layer arranged between the lower electrode and the upper electrode and containing a phase change material, and a bit line directly arranged on the upper electrode. The bit line is formed to be offset to the recording... Agent: Mcdermott Will & Emery LLP

20070123015 - Passive components in the back end of integrated circuits: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set... Agent: Ibm Microelectronics Intellectual Property Law

20070123019 - Methods of forming carbon nanotubes in a wiring pattern and related devices: A method of forming a carbon nanotube includes forming a cavity between a substrate and a first layer on the substrate. The cavity extends in a wiring pattern and includes a metal catalyst pattern in the cavity. The carbon nanotube is formed from the metal catalyst pattern and extends inside... Agent: Myers Bigel Sibley & Sajovec

20070123021 - Circuit under pad structure and bonding pad process: A circuit under pad structure comprises a bonding pad to provide a bonding region and a probing region which are not overlapped to each other, so as to reduce the pounding to the structure under the bounding pad during the test and package process. A simple process for forming the... Agent: Rosenberg, Klein & Lee

20070123020 - Method for forming solder balls with a stable oxide layer by controlling the reflow ambient: By controlling the cooling rate during the oxidation process for forming an oxide layer on solder balls and by selecting an elevated temperature as an initial temperature of the oxidation process, a reliable yet easily removable oxide layer may be obtained. Consequently, yield losses during the flip chip assembly process... Agent: Williams, Morgan & Amerson

20070123022 - Semiconductor device manufacturing method: There is prepared a semiconductor construction in which a plurality of columnar electrodes are provided on an upper side of a semiconductor substrate and in which a sealing film is provided on the semiconductor substrate to cover outer peripheral surfaces of the columnar electrodes. Upper sides of the columnar electrodes... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070123024 - Eliminate imc cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during cu/low-k processing: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer... Agent: Lsi Logic Corporation

20070123025 - Forming a barrier layer in joint structures: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.... Agent: Intel Corporation C/o Intellevate, LLC

20070123023 - Method of forming dual interconnects in manufacturing mram cells: A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on... Agent: Edell, Shapiro & Finnan, LLC

20070123026 - Semiconductor device having high frequency components and manufacturing method thereof: A transistor is located on a GaAs substrate. An air bridge extends to provide a cavity above gate electrodes of the transistor. An opening is sealed by the end ball of a second wire. Further, the semiconductor device is wholly covered by sealing resin.... Agent: Leydig Voit & Mayer, Ltd

20070123028 - Methods of forming low-k dielectric layers containing carbon nanostructures: Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20070123029 - Semiconductor device and method for manufacturing the same: A semiconductor device including a multilevel wiring with a small interwiring capacitance is provided by comprising a wiring, a conductive film formed on an upper surface of the wiring to prevent diffusion of a wiring material, and an insulating film which is constituted of low dielectric constant insulating films stacked... Agent: Foley And Lardner LLP Suite 500

20070123027 - Wiring forming method, wiring forming apparatus, and wiring board: After performing one forming step of a first pattern forming step of forming a first patent on a substrate and a second pattern forming step of forming a second pattern on the substrate, the other forming step is performed to thereby form, a high-reliability wiring pattern on the substrate.... Agent: Morgan & Finnegan, L.L.P.

20070123030 - Semiconductor devices and methods of manufacturing semiconductor devices: Disclosed is a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an insulating layer and a metal interconnection. An insulating layer may include a first layer including fluorine and a second layer including SRO (silicon rich oxide) having a dangling bond. A metal... Agent: Sherr & Nourse, PLLC

20070123032 - Method for manufacturing a semiconductor device having a stepped through-hole: A DRAM device includes a contact plug in contact with a diffused region of a semiconductor substrate, and a via-plug in contact with top of the contact plug. The through-hole receiving the via-plug has stepped structure including a tapered upper portion formed by an anisotropic dry etching and a larger-diameter... Agent: Young & Thompson

20070123031 - Method for production of semiconductor device: A short circuit with an adjacent hole is prevented. By enlarging a hole diameter in the lower part of the hole, a stable storage node is formed without causing a decrease in capacitance. Provided is a method for production of a semiconductor device, comprising the steps of: forming the second... Agent: Sughrue Mion, PLLC

20070123033 - Method of forming a damascene structure with integrated planar dielectric layers: Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a barrier metal over the dielectric material and the exposed... Agent: Ingrassia Fisher & Lorenz, P.C.

20070123034 - Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layer: By forming a thin passivation layer after the formation of openings connecting to a highly reactive metal region, any queue time effects may be significantly reduced. Prior to the deposition of a barrier/adhesion layer, the passivation layer may be efficiently removed on the basis of a heat treatment so as... Agent: Williams, Morgan & Amerson

20070123036 - Method of filling structures for forming via-first dual damascene interconnects: A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating is partially cured by baking at a low temperature. Next, a solvent is dispensed... Agent: Hovey Williams LLP

20070123037 - Method of forming pattern using fine pitch hard mask: A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that... Agent: Volentine Francos, & Whitt PLLC

20070123035 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070123038 - Method for manufacturing semiconductor device: In embodiments, a method for manufacturing a semiconductor device may include forming a diffusion preventing layer on a semiconductor substrate having a conductive layer, forming an intermetallic insulating layer on the diffusion preventing layer, forming a trench photo resist layer formed above the intermetallic insulating layer of a first photo... Agent: Sherr & Nourse, PLLC

20070123039 - Electroless plating of metal caps for chalcogenide-based memory devices: A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer... Agent: Dinsmore & Shohl LLP

20070123040 - Method for forming storage node contact plug in semiconductor device: A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch... Agent: Townsend And Townsend And Crew, LLP

20070123041 - Apparatus and method for surface processing such as plasma processing: A plurality of electrode plates 11, 12 are arranged, in side-by-side relation, on a processor 1 of a plasma surface processing apparatus M. A slit-like hole-row 10a is formed between the adjacent electrode plates, and a hole-row group 100 is constituted by the side-by-side arranged hole-rows 10a. The object W... Agent: Sughrue Mion, PLLC

20070123042 - Methods to form heterogeneous silicides/germanides in cmos technology: Methods of fabricating a semiconductor structure including heterogeneous suicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous suicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the present invention, the inventive methods utilize a combination of... Agent: Scully Scott Murphy & Presser, PC

20070123043 - A semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer: By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070123044 - Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction: A new technique is disclosed in which a barrier/capping layer for a copper-based metal line is formed by using a thermal-chemical treatment with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma-based deposition of silicon nitride and/or silicon carbon nitride. The thermal-chemical treatment... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070123045 - Method for the treatment of material, in particular in the fabrication of semiconductor components: In a method for the treatment of material, in particular in the fabrication of semiconductor components, at least one partial region of the material is implanted with ions in a targeted manner. Afterward or in a later method step, a step of etching the material is performed, the etching rate... Agent: Slater & Matsil LLP

20070123046 - Continuous in-line monitoring and qualification of polishing rates: A CMP tool can be closed loop controlled by using data, for a first polished wafer, obtained by an in-line metrology station, an in-situ monitoring system, and/or an inter-platen monitoring system to continually monitor and qualify polishing rates for the processing of subsequent polished wafers.... Agent: Fish & Richardson P.C.

20070123047 - Polishing machine, workpiece supporting table pad, polishing method and manufacturing method of semiconductor device: A pedestal pad (workpiece supporting table pad) is arranged on the top of a pedestal (workpiece supporting table) for temporarily placing and holding a pre-polished or post-polished wafer (workpiece). This pedestal pad is formed of resin, and at least a surface of the pedestal pad which comes into contact with... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070123048 - Use of a plasma source to form a layer during the formation of a semiconductor device: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070123050 - Etch process used during the manufacture of a semiconductor device and systems including the semiconductor device: A carbon or carbon-containing underlayer, which is used as a mask, is patterned using a process comprising, in one specific embodiment, boron trichloride and oxygen under specified processing conditions to etch the underlayer. The underlayer is then used as a mask to etch a layer below the underlayer, such as... Agent: Micron Technology, Inc.

20070123049 - Semiconductor process and method for removing condensed gaseous etchant residues on wafer: A semiconductor process is provided. A substrate is provided and then a to-be-etched layer is formed on the substrate. A patterned photoresist layer is formed on the to-be-etched layer. The to-be-etching layer is etched using a gaseous etchant to form a patterned layer. In the meantime, some of the gaseous... Agent: Jianq Chyun Intellectual Property Office

20070123051 - Oxide etch with nh4-nf3 chemistry: The present invention generally provides apparatus and methods for selectively removing various oxides on a semiconductor substrate. One embodiment of the invention provides a method for selectively removing an oxide on a substrate at a desired removal rate using an etching gas mixture. The etching gas mixture comprises a first... Agent: Patterson & Sheridan, LLP

20070123052 - Process sequence for photoresist stripping and cleaning of photomasks for integrated circuit manufacturing: A method and system for cleaning and/or stripping photoresist from photomasks used in integrated circuit manufacturing comprising a process and means of introducing a mixture of sulfuric acid and ozone (or a mixture of sulfuric acid and hydrogen peroxide) to the surface of a photomask while applying megasonic energy. The... Agent: Wolf, Block, Schorr & Solis-cohen LLP

20070123053 - Self-aligned pitch reduction: A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first... Agent: Beyer Weaver LLP

20070123054 - Nanocoils, systems and methods for fabricating nanocoils: Improved nanocoils, systems and methods for fabricating nanocoils. Embodiments enable wet etching techniques for releasing coiling arm structures and forming nanocoils. A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer in which SOI wafer includes a buried oxide layer, patterning one or more devices onto a silicon device... Agent: Andrews Kurth LLP Intellectual Property Department

20070123055 - Insulating material: Disclosed is an insulating material containing an epoxy resin, a curing agent and a nano-filling material having an aspect ratio of not more than 40 at a thickness of not more than 2 nm. The nano-filling material comprises an organized clay dispersed in the epoxy resin. The organized clay is... Agent: Harness, Dickey & Pierce, P.L.C

20070123056 - Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer: A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of... Agent: Freescale Semiconductor, Inc. Law Department

20070123057 - Overvoltage protection materials and process for preparing same: The invention provides a process for preparing an overvoltage protection material comprising: (i) preparing a mixture comprising a polymer binder precursor and a conductive material; and (ii) heating the mixture to cause reaction of the polymer binder precursor and generate a polymer matrix having conductive material dispersed therein, wherein the... Agent: Berkeley Law & Technology Group, LLP

20070123058 - Semiconductor device structures that include sacrificial, readily removable materials: A semiconductor device structure includes a sacrificial element and at least one feature adjacent to and at least partially formed by the sacrificial element. The sacrificial element may include a plurality of adjacent, mutually adhered regions. A substrate, such as a semiconductor device or other semiconductor device component, may carry... Agent: Trask Britt, P.C./ Micron Technology

20070123060 - Method for the deposition of a film by cvd or ald: Methods and apparatus for deposition of a film on a substrate in a reaction chamber by an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process include providing one or more reactants, and providing a volatile neutral coordinating ligand capable of coordinating at least one selected from the following:... Agent: Knobbe Martens Olson & Bear LLP

20070123059 - Methods of internal stress reduction in dielectric films with chemical incorporation and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a porous dielectric layer comprising at least one active end group, and bonding at least one large atomic radii species to replace the at least one active end group, wherein a local swelling may be formed... Agent: Intel Corporation C/o Intellevate, LLC

20070123061 - Method of treating a substrate, method of processing a substrate using a laser beam, and arrangement: The present invention relates generally to a method of and arrangement treating a substrate processed using a laser beam, wherein said substrate comprises at least a body of semiconductor material. The method comprises a step of etching said substrate for removing from said body of semiconductor material recast material deposited... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070123062 - Semiconductor device and method of manufacturing the same: In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure... Agent: Mills & Onello LLP

20070123063 - Method of manufacturing a semiconductor integrated circuit device: Decreasing foreign materials adhering to a semiconductor substrate to improve a yield and decreasing handling errors for the semiconductor substrate to improve an operating ratio of the semiconductor manufacturing apparatus. A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070117230 - Computer readable storage medium for work-in-process schedules: A computer readable storage medium for work in progress (WIP) schedules in semiconductor manufacturing facility. After determining starting and ending dates of predetermined schedule periods for generating WIP schedules, remaining days are determined for completing at least one wafer lot associated with predetermined product from the starting date. A starting... Agent: Steven E. Koffs

20070117225 - Integrated inspection system and defect correction method: A system for the inspection of and a process for the correction of defects in a microreplicated optical display film manufacturing process. The process steps of manufacturing a master, a plurality of shims from the master, and a multiplicity of display films from each shim are integrated with a systemic... Agent: Cantor Colburn, LLP

20070117226 - Method and apparatus for processing timeout in dsg apparatus: A method and apparatus for processing a timeout in a device that complies with the DSG standard are provided. The method includes detecting whether a Tdsg4 timeout has occurred in the first device; and transmitting a Tdsg4 timeout message indicating that a Tdsg4 timeout has occurred in the first device... Agent: Sughrue Mion, PLLC

20070117227 - Method and system for iteratively, selectively tuning a parameter of a doped workpiece using a pulsed laser: A method and system for iteratively, selectively tuning a parameter of a doped workpiece, such as the impedance of an integrated semiconductor device, by modifying the dopant profile of a region of relatively low dopant concentration by controlled diffusion of dopants from one or more adjacent regions of relatively higher... Agent: Brooks Kushman P.C.

20070117229 - Methods for minimizing defects when transferring a semiconductor useful layer: A method for minimizing defects when transferring a useful layer from a donor wafer to a receptor wafer is described. The method includes providing a donor wafer having a surface below which a zone of weakness is present to define a useful layer to be transferred, molecularly bonding at a... Agent: Winston & Strawn LLP Patent Department

20070117231 - Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor: A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, includes an orthogonal wire having a first minimum wire width which is formed on a first wiring layer and extends horizontally or vertically; a diagonal wire having a second minimum... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070117228 - Teaching apparatus and teaching method: A teaching apparatus and a teaching method that facilitates accurately setting a retainer at a target position, and minimizes troublesome steps in the manufacturing process, are to be provided. The teaching apparatus includes a first member held by the retainer of the carrying apparatus, a second member attached to the... Agent: Young & Thompson

20070117232 - Method of studying interaction between immersion fluid and substrate: A method and measurement tools for studying interaction between an immersion fluid and a material in a substrate, such as, e.g., a photoresist or a topcoat or components thereof, are provided. The method comprises providing a spatially controlled contact between only part of the substrate and the immersion fluid. The... Agent: Knobbe Martens Olson & Bear LLP

20070117233 - Film pattern forming method, device, electro-optical apparatus, and electronic appliance: A method for forming a film pattern by disposing a functional fluid on a substrate, includes: forming a partition wall that includes a first opening that corresponds to a first film pattern and a second opening that corresponds to a second film pattern; and disposing a droplet of the functional... Agent: Harness, Dickey & Pierce, P.L.C

20070117234 - Sputtered spring films with low stress anisotropy: Methods are disclosed for fabricating spring structures that minimize helical twisting by reducing or eliminating stress anisotropy in the thin films from which the springs are formed through manipulation of the fabrication process parameters and/or spring material compositions. In one embodiment, isotropic internal stress is achieved by manipulating the fabrication... Agent: Bever, Hoffman & Harms, LLP

20070117235 - Method for producing an electrical contact for an optoelectronic semiconductor chip: A method for producing an electrical contact of an optoelectronic semiconductor chip (1), comprising providing a mirror layer (2), comprised of a metal or metal alloy, over the semiconductor chip; providing a protective layer (3) over said mirror layer; providing a layer sequence of a barrier layer and a coupling... Agent: Cohen Pontani Liberman & Pavane LLP

20070117236 - Method of manufacturing optical module: A method of manufacturing an optical module having an optical element includes: (a) providing a housing having a base portion and a frame portion provided on the base portion; (b) providing a spacer on the base portion of the housing; (c) pressing the spacer to plastically deform the spacer; (d)... Agent: Oliff & Berridge, PLC

20070117237 - Amorphous transparent conductive film, sputtering target as its raw material, amorphous transparent electrode substrate, process for producing the same and color filter for liquid crystal display: A transparent conductive film of low resistivity excelling in transparency and etching properties; a sputtering target as its raw material; an amorphous transparent electrode substrate having the transparent conductive film superimposed on a substrate; and a process for producing the same. In particular, an amorphous transparent conductive film comprising at... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070117239 - Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus: An electro-optical device includes, above a substrate, a plurality of data lines and a plurality of scanning lines that cross each other, a plurality of pixel electrodes that are provided so as to correspond to intersections between the plurality of data lines and the plurality of scanning lines, and transistors,... Agent: Advantedge Law Group, LLC

20070117238 - Liquid crystal display device and method for fabricating the same: A method for fabricating a liquid crystal display (LCD) device includes: forming a gate line, a gate electrode, and a gate pad electrode on a substrate; sequentially forming a gate insulating layer, a semiconductor layer and a metal layer on an entire surface of the substrate including the gate electrode;... Agent: Mckenna Long & Aldridge LLP

20070117240 - Liquid crystal display with positional marks for bonding drive ic: An exemplary liquid crystal display (2) includes a liquid crystal panel (20) and a drive integrated circuit (IC) (21). The liquid crystal panel includes a plurality of circuit pads (202), a first positional mark (2031), and a second positional mark (2032). The drive IC includes a plurality of metal bumps... Agent: Wei Te Chung Foxconn International, Inc.

20070117241 - Method for making a shadow mask for an apposed discharge plasm display panel: The present invention is to provide a method for making a shadow mask for an opposed discharge plasma display panel by etching one lateral surface of a metal slab to produce a plurality of parallel and equidistant barrier ribs along the vertical and horizontal directions on the lateral surface and... Agent: Bacon & Thomas, PLLC

20070117242 - Providing photonic control over wafer borne semiconductor devices: Disclosed are methods for providing wafer photonic flow control to a semiconductor wafer (1700) having a substrate (1720), at least one active layer (1765) and at least one surface layer (1710). Photonic flow control can be achieved through the formation of trenches (1725) and/or insulating implants (1730) formed in said... Agent: Honeywell International Inc.

20070117243 - Method of fabricating a biosensor: The present invention provides a method of fabricating a biosensor. The method includes providing a substrate which has a surface coating. The surface coating is deformable and the substrate includes a layered structure which has at least two electrically conductive layers separated by at least one electrically insulating layer. The... Agent: Hewlett Packard Company

20070117244 - Preferentially deposited lubricant to prevent anti-stiction in micromechanical systems: Embodiments of the present invention generally relate to a device that has an improved usable lifetime due to the presence of a lubricant that reduces the likelihood of stiction occurring between the various moving parts in an electromechanical device. Embodiments of the present invention also generally include a device, and... Agent: Patterson & Sheridan, L.L.P.

20070117245 - Wafer level package for micro device and manufacturing method thereof: A wafer level package includes a device wafer having a micro device, and bonding pads which are connected to the micro device, and formed at one surface of the device wafer, via connectors extending from the bonding pads to the other surface of the device wafer, external bonding pads formed... Agent: Lowe Hauptman Berner, LLP

20070117246 - Metal mems devices and methods of making same: Metal MEMS structures are fabricated from metal substrates, preferably titanium, utilizing micromachining processes with a new deep etching procedure to provide released microelectromechanical devices. The deep etch procedure includes metal anisotropic reactive ion etching utilizing repetitive alternating steps of etching and side wall protection. Variations in the timing of the... Agent: Gates & Cooper LLP Howard Hughes Center

20070117247 - Manufacturing method of microstructure: A manufacturing method of a microstructure includes the steps of: providing a substrate; forming a photoresist layer on the substrate; providing a first mask, which has at least one opaque area and at least one first lens, over the photoresist layer; providing a light source for illuminating the photoresist layer... Agent: Birch Stewart Kolasch & Birch

20070117248 - Method for the production of light-emitting semiconductor diodes: A method is disclosed for creating a light assembly including a light-emitting diode and a printed circuit board having conductors printed thereon. The method includes the steps of positioning the light-emitting diode on the printed circuit board. Once positioned, the light-emitting diode is connected to the printed circuit board. The... Agent: Clark Hill, P.C.

20070117250 - Method of increasing a free carrier concentration in a semiconductor substrate: A method of selectively heating a predetermined region of a semiconductor substrate includes providing a semiconductor substrate, selectively focusing a free carrier generation light on only a predetermined region of the semiconductor substrate, irradiating the free carrier generation light on the predetermined region of the semiconductor substrate to increase a... Agent: Lee & Morse, P.C.

20070117249 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units: Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality... Agent: Dickstein Shapiro LLP

20070117251 - Display device, flat lamp and method of fabricating the display device and flat lamp: A display device and a flat lamp that have simple structures and can be fabricated using simple fabricating processes, and a method of fabricating the display device and the flat lamp. The display device includes: a first substrate and a second substrate facing each other across a predetermined distance; barrier... Agent: Stein, Mcewen & Bui, LLP

20070117252 - Silicon-containing antireflective coating forming composition, silicon-containing antireflective coating, substrate processing intermediate, and substrate processing method: A composition for forming an antireflective coating for use in a photolithography process using exposure light of up to 200 nm comprises a silicon-containing polymer obtained through hydrolytic condensation of a silicon-silicon bond-containing silane compound having formula: R(6-m)Si2Xm wherein R is a monovalent hydrocarbon group, X is alkoxy, alkanoyloxy or... Agent: Birch Stewart Kolasch & Birch

20070117254 - Back-illuminated imager and method for making electrical and optical connections to same: Methods for bringing or exposing metal pads or traces to the backside of a backside-illuminated imager allow the pads or traces to reside on the illumination side for electrical connection. These methods provide a solution to a key packaging problem for backside thinned imagers. The methods also provide alignment marks... Agent: Ladas & Parry

20070117253 - Method for providing metal extension in backside illuminated sensor for wafer level testing: A method of providing metal extension in a backside illuminated image sensor is provided in the present disclosure. In one embodiment, a first set of pads and a second set of pads, and a metal layer are provided in a backside illuminated image sensor. The first set of pads are... Agent: Haynes And Boone, LLP

20070117255 - Formation of contacts on semiconductor substrates: Embodiments of the invention are concerned with a method of manufacturing a radiation detector having one or more conductive contacts on a semiconductor substrate, and comprise the steps of: applying a first conductive layer to a first surface of the semiconductor substrate: applying a second conductive layer to form a... Agent: Kenyon & Kenyon LLP

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