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Semiconductor device manufacturing: process May archived listing by USPTO class 05/07

20070122917 - Forming method of ferroelectric capacitor and manufacturing method of semiconductor device: Disclosed is a ferroelectric capacitor forming method of allowing a FeRAM to be stably mass-produced. In forming the ferroelectric capacitor for the FeRAM, a PZT layer is formed on a lower electrode layer by a sputtering method. Then, a first RTA treatment for crystallizing the PZT is performed in an... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070122918 - Method for fabricating microstructure and a microstructure formed using the method: A method for fabricating a microstructure includes forming a negative type photoresist film with a predetermined thickness on a substrate, removing solvent remaining in the photoresist film by a first heat treatment of the photoresist film, exposing the photoresist film with ultraviolet light having an energy of about 200 mJ/cm2... Agent: Cantor Colburn, LLP

20070122919 - Method of producing an integrated circuit arrangement with field-shaping electrical conductors: An integrated circuit arrangement includes at least one electrical conductor that, when a current flows through it, produces a magnetic field that acts on at least a further part of the circuit arrangement, wherein seen in cross section, the electrical conductor has at least one recess or depression, or a... Agent: Lerner Greenberg Stemer LLP

20070122920 - Method for improved control of critical dimensions of etched structures on semiconductor wafers: A system for real-time monitoring and control of critical dimensions during semiconductor wafer fabrication is provided. The system measures structures in situ, that is, as they are being etched onto a wafer layer.... Agent: Duke W. Yee Yee & Associates, P.C.

20070122921 - Copper wiring module control: Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially,... Agent: Fish & Richardson P.C.

20070122922 - Platform asic reliability: A method for monitoring a fabrication of a circuit is disclosed. The method generally includes a step of (A) fabricating a chip only up to and including a first metal layer such that (i) a core region of the chip may has an array of cells, (ii) each of the... Agent: Lsi Logic Corporation

20070122923 - Flat panel display and method for making the same: A flat panel display capable of preventing a chipping phenomenon of a pixel definition layer, and a method for making the same are disclosed. The flat panel display includes a thin film transistor formed on a substrate; a planarization layer formed on the thin film transistor; a first electrode layer... Agent: Knobbe Martens Olson & Bear LLP

20070122925 - Flip-chip nitride light emitting device and method of manufacturing thereof: A flip-chip light emitting device and a method of manufacturing thereof are provided. The flip-chip nitride light emitting device includes a substrate, an n type clad layer, an active layer, a p type clad layer, a multi ohmic contact layer, and a reflective layer, which are stacked in this order,... Agent: Buchanan, Ingersoll & Rooney PC

20070122924 - Method of fabricating metal oxide semiconductor transistor: A masking layer is formed over a substrate. The substrate and the masking layer are patterned to form trenches that partitions the substrate into first doping type semiconductor strips. An isolation layer is formed inside the trenches such that the surface of the isolation layer is below the upper surface... Agent: Jianq Chyun Intellectual Property Office

20070122926 - Substrate layer cutting device and method: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member... Agent: Winston & Strawn LLP Patent Department

20070122928 - Electro-optical device, method of manufacturing the same, and electronic apparatus: A method of manufacturing an electro-optical device, the electro-optical device having an electro-optical element formed by laminating a first electrode, an electro-optical layer, and a second electrode in sequence on a base body, the method of manufacturing the electro-optical device, including the steps of: forming an ultraviolet absorbing layer on... Agent: Oliff & Berridge, PLC

20070122927 - Electrochemical cell structure and method of fabrication: One limitation to the realisation of mass produced electrochemical cells is a lack of high resolution patterning techniques providing accurate-alignment. Accordingly a method of fabricating a patterned structure in the manufacture of an electrochemical cell comprising a soft-contact printing and ink-jet printing is provided.... Agent: Oliff & Berridge, PLC

20070122929 - Method and zone for sealing between two microstructure substrates: The invention concerns a sealing zone between two microstructure substrates. Said sealing zone comprises at least the following parts: on a first wafer level (20), a lower edging (22A) made of an adhesive material capable of causing the first substrate (20) to adhere to a sealing material, said sealing material... Agent: Brinks Hofer Gilson & Lione

20070122930 - Electrochemical cell structure and method of fabrication: An electrochemical cell and a method of manufacturing the same is provided. The electrochemical cell comprises a first conductive layer; a metal oxide layer formed on the first conductive layer, the metal oxide layer comprising a plurality of adjacent metal oxide cells, spaced from one another; a functional dye layer... Agent: Oliff & Berridge, PLC

20070122931 - Electrochemical cell structure and method of fabrication: An electrochemical cell and a method of manufacturing the same are provided. The electrochemical cell comprises a first conductive layer; a metal oxide layer formed on the first conductive layer, the metal oxide layer comprising a plurality of adjacent metal oxide cells, spaced from one another; a functional dye layer... Agent: Oliff & Berridge, PLC

20070122932 - Methods and compositions for the formation of recessed electrical features on a substrate: Precursor compositions having a low conversion temperature and methods for the fabrication of recessed electrical features from the precursor compositions. The electrical features can be conductors, resistors and dielectric features. The precursor compositions are deposited into recessed features, such as trenches, formed in a substrate and are reacted at a... Agent: Jaimes Sher, Esq. Cabot Corporation

20070122933 - Electrochemical cell structure and method of fabrication: An electrochemical cell and a method of manufacturing the same are provided. The electrochemical cell comprises: a first conductive layer; a metal oxide layer provided on the first conductive layer, the metal oxide layer comprising a plurality of adjacent metal oxide cells, spaced from one another; a functional dye layer... Agent: Oliff & Berridge, PLC

20070122934 - Silicon-based photodetector and method of fabricating the same: A method of fabricating a photodetector device includes preparing a silicon substrate, forming a patterned mesa on the silicon substrate, and forming a patterned conductive layer over the patterned mesa.... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070122935 - Manufacturing method of solid-state imaging device, solid-state imaging device, and camera: A manufacturing method of a solid-state imaging device prevents generation of a space due to insufficient filling of a conductive material. Materials constituting a multilayer film 41 are sequentially deposited on a semiconductor substrate, and portions respectively included in a plug formation intended region and a surrounding region that surrounds... Agent: Mcdermott Will & Emery LLP

20070122936 - System for heat treatment of semiconductor device: Disclosed is a heat treatment system for semiconductor devices. The heat treatment system is used in a heat treatment process for semiconductor devices, such as a crystallization process for an amorphous silicon thin film or a dopant activation process for a poly-crystalline silicon thin film formed on a surface of... Agent: Hyun Jong Park Tuchman & Park LLC

20070122937 - Method of manufacturing light emitting device: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070122938 - Organic electroluminescent display device: In order to solve the above problem, in an organic EL display 10 of the present invention having a plurality of display device 20 provided onto a substrate 30, the display devices includes: an anode electrode 31 arranged on the substrate, a cathode electrode 32 arranged adjacently to the anode... Agent: Hogan & Hartson L.L.P.

20070122939 - Organic light emitting device: The instant disclosure relates to an organic light emitting device with an improved blue light emitting efficiency. One embodiment of the organic light emitting device has an advantageous effect of increasing the blue light emitting efficiency remarkably without changing other elements' properties by forming organic layers including compounds having specific... Agent: Knobbe Martens Olson & Bear LLP

20070122940 - Method for packaging a semiconductor device: A method for packaging a semiconductor device includes forming through holes (12) in a base substrate (10) and depositing a conductive material (14) on a first side (16) of the base substrate (10) to form a conductive layer (18) such that the conductive material (14) fills the through holes (12).... Agent: Freescale Semiconductor, Inc. Law Department

20070122941 - Terminal device communicating with contact-less ic media, and a communication method performed in the terminal device: The terminal device of the present invention comprises a transmitting means for transmitting, to a contact-less IC medium, commands and carrier signals used for receiving responses, a receiving means for receiving responses from the contact-less IC medium, and a controlling means for controlling at least one of the transmitting means... Agent: Fish & Richardson P.C.

20070122942 - Conforming template for patterning liquids disposed on substrates: The present invention includes a conforming template for patterning liquids disposed on substrates. The template includes a body having opposed first and second surfaces. The first surface includes a plurality of recessed regions with a patterning region being disposed between adjacent recessed regions. Specifically, the recessed regions define flexure regions... Agent: Molecular Imprints

20070122943 - Method of making semiconductor package having exposed heat spreader: A method of making a semiconductor package (50) includes attaching a bottom surface (54) of an integrated circuit (IC) die (52) to a base carrier (56) and electrically connecting the die (52) to the base carrier (56). A first surface (66) of a heat spreader (60) is attached to a... Agent: Freescale Semiconductor, Inc. Law Department

20070122944 - Individualized low parasitic power distribution lines deposited over active integrated circuits: An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by... Agent: Texas Instruments Incorporated

20070122945 - Methods of fabricating integrated circuit devices having fuse structures including buffer layers: An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of... Agent: Myers Bigel Sibley & Sajovec

20070122946 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070122947 - Metal compound, material for thin film formation, and process of forming thin film: wherein R1, R2, R3, and R4 each represent an alkyl group having 1 to 4 carbon atoms; A represents an alkanediyl group having 1 to 8 carbon atoms; M represents a lead atom, a titanium atom or a zirconium atom; n represents 2 when M is a lead atom or... Agent: Young & Thompson

20070122949 - Manufacturing method of thin film transistor: A manufacturing method of a thin film transistor is provided. A buffer layer is formed on a substrate, and then a first and a second poly-silicon island are formed thereon. A gate-insulating layer is formed on the substrate, and a first and a second gate are formed thereon. A sacrificed... Agent: Jianq Chyun Intellectual Property Office

20070122950 - Method for manufacturing conductive layer and semiconductor device: To provide a method for manufacturing a wiring, a conductive layer, a display device, and a semiconductor device, each of which can meet a large sized substrate and which is manufactured with a higher throughput by using a material efficiently, the conductive layer is formed over the substrate having an... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070122948 - Thin-film transistor and diode array for an imager panel or the like: Briefly, in accordance with one or more embodiments, a detector panel of an imaging system may be produced from a photodiode array integrated with a thin-film transistor array. The thin film transistor array may have one or more vias formed for increasing the adhesion of the photodiode array to the... Agent: General Electric Company Global Research

20070122951 - Self-aligned silicon carbide semiconductor devices and methods of making the same: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases.... Agent: Merchant & Gould PC

20070122952 - Semiconductor device with a dummy gate and a method of manufacturing a semiconductor device with a dummy gate: A dummy gate may be formed over an isolation layer. A sidewall spacer may be formed next to the dummy gate. The dummy gate and the sidewall spacer may substantially cover or completely cover the edge of isolation layer that is adjacent to an active area of a silicon substrate.... Agent: Sherr & Nourse, PLLC

20070122953 - Enhanced segmented channel mos transistor with high-permittivity dielectric isolation material: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Silcon Valley Patent Group LLP

20070122954 - Sequential selective epitaxial growth: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Silcon Valley Patent Group LLP

20070122960 - Antenna and manufacturing method thereof, semiconductor device including antenna and manufacturing method thereof, and radio communication system: An antenna includes a first substrate, a first pattern, a second substrate, a second pattern, and an anisotropic conductive material. The first substrate has an insulating surface. The first pattern is formed over the insulating surface of the first substrate, and made of a conductive material. The second substrate is... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070122957 - Low-cost feol for ultra-low power, near sub-vth device structures: In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2... Agent: Whitham, Curtis & Christofferson, P.C.

20070122959 - Method of forming gate of flash memory device: A method of forming a gate of a flash memory device, including the steps of sequentially forming a tunnel oxide film, a first polysilicon layer for a floating gate, a dielectric layer, a second polysilicon layer for a control gate, a tungsten silicide film, and a hard mask film on... Agent: Marshall, Gerstein & Borun LLP

20070122955 - Method of manufacturing a semiconductor structure: There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive... Agent: Charles N. J. Ruggiero Ohlandt Greeley Ruggiero & Perle L.L.P.

20070122958 - Spacer barrier structure to prevent spacer voids and method for forming the same: A semiconductor device includes a spacer adjacent a gate structure. A protection layer covers oxide portions of the spacer surface such that subsequent manufacturing operations such as wet oxide etches and strips, do not produce voids in the spacers. A method for forming the semiconductor device provides forming a gate... Agent: Duane Morris LLPIPDepartment (tsmc)

20070122956 - Transistor with dielectric stressor element fully underlying the active semiconductor region: A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is disposed. In particular, the dielectric stressor element... Agent: International Business Machines Corporation Dept. 18g

20070122961 - Method and structure for enhancing both nmosfet and pmosfet performance with a stressed film: A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or... Agent: International Business Machines Corporation Dept. 18g

20070122962 - Semiconductor cmos devices and methods with nmos high-k dielectric present in core region that mitigate damage to dielectric materials: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device.... Agent: Texas Instruments Incorporated

20070122963 - Latch-up prevention in semiconductor circuits: This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first doping region, wherein one or more semiconductor devices are disposed therein and coupling to a first supply voltage, a second doping region adjacent to the first doping region, wherein the second doping... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070122964 - Semiconductor device equipped with a voltage step-up circuit: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type... Agent: Hogan & Hartson L.L.P.

20070122965 - Stress engineering using dual pad nitride with selective soi device architecture: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of... Agent: Scully, Scott, Murphy & Presser, P.C.

20070122966 - Technique for enhancing stress transfer into channel regions of nmos and pmos transistors: A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to... Agent: Williams, Morgan & Amerson

20070122967 - Method for fabricating capacitor in semiconductor device: A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component... Agent: Townsend And Townsend And Crew, LLP

20070122968 - Fabrication method and structure for providing a recessed channel in a nonvolatile memory device: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially... Agent: Volentine Francos, & Whitt PLLC

20070122969 - Contact structure of semiconductor devices and method of fabricating the same: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070122970 - Methods of fabricating memory devices with memory cell transistors having gate sidewall spacers with different dielectric properties: A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and second sidewall spacers are disposed on respective ones... Agent: Myers Bigel Sibley & Sajovec

20070122974 - Eeprom: An EEPROM having a nonvolatile memory cell is provided. The nonvolatile memory cell has a first MOS transistor and a second MOS transistor. The first MOS transistor and the second MOS transistor have a gate electrode in common, the gate electrode being a floating gate electrically isolated from a surrounding... Agent: Mcginn Intellectual Property Law Group, PLLC

20070122973 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device, wherein, when a first polysilicon layer is formed, a doped polysilicon layer and an amorphous polysilicon layer are formed so that they are laminated. A process of forming a sidewall oxide film and an oxide film and a thermal treatment process are... Agent: Marshall, Gerstein & Borun LLP

20070122972 - Method of manufacturing nand flash memory device: A method of manufacturing a NAND flash memory device, including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined; simultaneously forming a plurality of cell gates on the semiconductor substrate of the cell region and forming selection gates on the... Agent: Marshall, Gerstein & Borun LLP

20070122971 - Vertical soi trench sonos cell: A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench... Agent: Scully Scott Murphy & Presser, PC

20070122975 - Mos transistor manufacturing: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070122976 - Flash memory device having recessed floating gate and method for fabricating the same: A flash memory device and a method for fabricating the same are provided. The flash memory device includes: an active region having a plurality of surface regions and a plurality of recess regions formed lower than the surface regions; a tunnel oxide layer formed over the recess regions; a plurality... Agent: Blakely Sokoloff Taylor & Zafman

20070122978 - Non-volatile memory device and fabrication method thereof: A non-volatile memory device includes a buffer oxide film on a substrate; a polysilicon layer on the buffer oxide film; a silicon oxy-nitride (SiON) layer on the polysilicon layer, a first insulator layer on the SiON layer, a nitride film on the first insulator, a second insulator layer on the... Agent: Lee & Morse, P.C.

20070122977 - Self-aligned pitch reduction: A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features... Agent: Beyer Weaver LLP

20070122979 - Semiconductor devices and methods of fabricating the same: Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed... Agent: Mills & Onello LLP

20070122980 - Flash memory array with increased coupling between floating and control gates: Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070122982 - Method of applying stresses to pfet and nfet transistor channels for improved performance: A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having... Agent: International Business Machines Corporation Dept. 18g

20070122981 - Method of fabricating semiconductor device having multiple gate insulating layer: A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing... Agent: F. Chau & Associates, LLC

20070122983 - Multi-operational mode transistor with multiple-channel device structure: A multiple operating mode transistor is provided in which multiple channels having different respective operational characteristics are employed. Multiple channels have threshold voltages that are independently adjustable. The independent adjustment of the threshold voltage includes providing at least one of different respective doping concentrations in the different channels, different respective... Agent: Mcdermott Will & Emery LLP

20070122984 - Structure and method for manufacturing strained finfet: A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively... Agent: Scully, Scott, Murphy & Presser, P.C.

20070122985 - Formation of active area using semiconductor growth process without sti integration: A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body.... Agent: Slater & Matsil LLP

20070122986 - Carbon nanotube field effect transistor and methods for making same: A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. In one embodiment, a method for forming a carbon nanotube transistor starts with a substrate comprised of a bottom dielectric, a carbon nanotube layer, and a top dielectric. A pillar is formed on the top... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070122987 - Method for fabricating an nmos transistor: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the... Agent: North America Intellectual Property Corporation

20070122988 - Methods of forming semiconductor devices using embedded l-shape spacers: A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of... Agent: Charles N. J. Ruggiero Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20070122989 - Epitaxial and polycrystalline growth of si1-x-ygexcy and si1-ycy alloy layers on si by uhv-cvd: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is... Agent: Scully, Scott, Murphy & Presser, P.C.

20070122990 - Method for producing epitaxial wafer with buried diffusion layer and epitaxial wafer with buried diffusion layer: There is disclosed a method for producing an epitaxial wafer with a buried diffusion layer comprising: implanting an impurity into a silicon single crystal wafer; subsequently diffusing the impurity in the wafer to form a diffusion layer; at least removing an oxide film on the diffusion layer; and thereafter forming... Agent: Oliff & Berridge, PLC

20070122991 - Resistor element and manufacturing method thereof: A method of manufacturing a resistive element of present invention comprises; (A) forming on a substrate, a polysilicon structure whose top layer is a polysilicon layer; (B) forming a metal layer on the polysilicon layer; (C) forming an upper barrier layer on the metal layer; and (D) forming a silicide... Agent: Sughrue Mion, PLLC

20070122992 - Electronic component manufacturing method and electronic component: The electronic component includes a base material, a capacitor unit, and a wiring portion. The capacitor unit has a stacked structure including a first electrode portion provided on the base material, a second electrode portion including a first surface opposing the first electrode portion and a second surface opposite to... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070122993 - Method of simultaneously fabricating isolation structures having rounded and unrounded corners: A method facilitates generally simultaneously fabricating a number of shallow trench isolation structures such that some selected ones of the shallow trench isolation structures have rounded corners and other selected ones of the shallow trench isolation structures do not have rounded corners. The method includes forming patterned photoresist over a... Agent: Stout, Uxa, Buyan & Mullins LLP

20070122994 - Nitride semiconductor light emitting element: A nitride semiconductor light-emitting element suppresses leakage currents and non-radiative recombination centers by providing, as an underlying layer of the active layer, a pit formation layer that reliably generates pits, while maintaining a good film quality, so that the internal quantum efficiency is improved, and the light-emitting characteristics are also... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070122995 - Controlled process and resulting device: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define... Agent: Townsend And Townsend And Crew, LLP

20070122996 - Epitaxial semiconductor layer and method: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070122998 - Active silicon device on a cleaved silicon-on-insulator substrate: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070122997 - Controlled process and resulting device: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define... Agent: Townsend And Townsend And Crew, LLP

20070123000 - Dicing tape attaching apparatus and dicing tape attaching method: A dicing tape attaching apparatus (10) comprises a fixed table (38) for supporting a mount frame (36), a movable table (31) for supporting a wafer (20) with the reverse surface thereof ground, and a height adjusting unit (70) such as a screw jack for adjusting the height of the movable... Agent: Christie, Parker & Hale, LLP

20070122999 - Method and apparatus for fabricating and connecting a semiconductor power switching device: Fabrication processes for manufacturing and connecting a semiconductor switching device are disclosed, including an embodiment for dicing a wafer into individual circuit die by sawing the interface between adjacent die with a saw blade that has an angled configuration across its width, preferably in a generally V-shape so that the... Agent: Roger D. Greer Greer, Burns & Crain, Ltd.

20070123001 - System and method for separating and packaging integrated circuits: A method of separating an IC. The method includes dicing a semiconductor wafer. The semiconductor wafer includes multiple ICs. The diced wafer is secured to a stretchable substrate. The stretchable substrate can be stretched so as to form corresponding spaces between each of the ICs. The corresponding spaces are filled... Agent: Martine Penilla & Gencarella, LLP

20070123002 - Wafer dividing method: The present invention grinds the rear surface side of a device area to form a recessed portion and an annular reinforcement part on the outer periphery of the recessed portion, removes the annular reinforcement part by grinding or cutting the rear surface of the annular reinforcement part so as to... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070123003 - Dielectric interface for group iii-v semiconductor device: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.... Agent: Blakely Sokoloff Taylor & Zafman

20070123005 - Film formation apparatus, method for forming film, and method for manufacturing photoelectric conversion device: The present invention relates to a film formation apparatus including a first transfer chamber having a roller for sending a substrate, a film formation chamber having a discharging electrode, a buffer chamber provided between the transfer chamber and the film formation chamber or between the film formation chambers, a slit... Agent: Nixon Peabody, LLP

20070123007 - Film-forming method and film-forming equipment: A plurality of wafers are loaded on a susceptor installed in a reaction chamber, and the wafers are heated, and process gas is fed from a plurality of stages of openings formed in a gas feed nozzle installed so as to pass through the center of the susceptor, the process... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070123004 - Method and apparatus for forming a crystalline silicon thin film: A hydrogen gas is supplied into a deposition chamber accommodating a silicon sputter target and a deposition target object, a high-frequency power is applied to said gas to generate plasma exhibiting Hα/SiH* from 0.3 to 1.3 between an emission spectral intensity Hα of hydrogen atom radicals at a wavelength of... Agent: Rader Fishman & Grauer PLLC

20070123008 - Method for controlling dislocation positions in silicon germanium buffer layers: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent and depositing a strained silicon germanium layer on the substrate. The dislocation inducing agent may include ions, electrons,... Agent: VistaIPLaw Group LLP

20070123006 - Semiconductor device and method of manufacturing the same: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. In the substrate and the epitaxial layer, an N type buried diffusion layer is formed on a P type buried diffusion layer. With this structure, an upward... Agent: Fish & Richardson P.C.

20070123009 - Technique for increasing adhesion of metallization layers by providing dummy vias: By providing dummy vias below electrically non-functional metal regions, the risk for metal delamination in subsequent processes may be significantly reduced. Moreover, in some embodiments, the mechanical strength of the resulting metallization layers may be even more enhanced by providing dummy metal regions, which may act as anchors for an... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070123010 - Technique for reducing crystal defects in strained transistors by tilted preamorphization: By performing a tilted amorphization implantation and a subsequent re-crystallization on the basis of a stressed overlying material, a highly efficient strain-inducing mechanism is provided. The tilted amorphization implantation may result in a significantly reduced defect rate during the re-crystallization process, thereby substantially reducing leakage currents in sophisticated transistor elements.... Agent: Williams, Morgan & Amerson

20070123011 - Production process for high purity polycrystal silicon and production apparatus for the same: In the production process of the present invention for high purity polycrystal silicon, using a vertical reactor having a silicon chloride gas-feeding nozzle and a reducing agent gas-feeding nozzle which are disposed at an upper part and a waste gas discharge pipe, a silicon chloride gas and a reducing agent... Agent: J C Patents, Inc.

20070123012 - Plasma implantation of deuterium for passivation of semiconductor-device interfaces: A method for fabricating a semiconductor-based device includes providing a substrate including a semiconductor layer, forming a gate dielectric layer on the semiconductor layer, forming a plasma including deuterium, plasma implanting deuterium from the plasma into the substrate, and annealing the substrate to promote passivation of the interface between the... Agent: Varian Semiconductor Equipment Assc., Inc.

20070123013 - Controlled process and resulting device: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define... Agent: Townsend And Townsend And Crew, LLP

20070123014 - Method for fabricating semiconductor device having flask type recess gate: A method for fabricating a semiconductor device having a flask type recess gate includes forming a hard mask pattern on a substrate, etching the substrate to a predetermined depth using the hard mask pattern to form a first recess pattern, forming a passivation layer on sidewalls of the first recess... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070123016 - Device with gaps for capacitance reduction: A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The... Agent: Beyer Weaver LLP

20070123017 - Device with self aligned gaps for capacitance reduction: A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of... Agent: Beyer Weaver LLP

20070123018 - Electrically rewritable non-volatile memory element and method of manufacturing the same: A non-volatile memory element includes a lower electrode, an upper electrode, a recording layer arranged between the lower electrode and the upper electrode and containing a phase change material, and a bit line directly arranged on the upper electrode. The bit line is formed to be offset to the recording... Agent: Mcdermott Will & Emery LLP

20070123015 - Passive components in the back end of integrated circuits: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set... Agent: Ibm Microelectronics Intellectual Property Law

20070123019 - Methods of forming carbon nanotubes in a wiring pattern and related devices: A method of forming a carbon nanotube includes forming a cavity between a substrate and a first layer on the substrate. The cavity extends in a wiring pattern and includes a metal catalyst pattern in the cavity. The carbon nanotube is formed from the metal catalyst pattern and extends inside... Agent: Myers Bigel Sibley & Sajovec

20070123021 - Circuit under pad structure and bonding pad process: A circuit under pad structure comprises a bonding pad to provide a bonding region and a probing region which are not overlapped to each other, so as to reduce the pounding to the structure under the bounding pad during the test and package process. A simple process for forming the... Agent: Rosenberg, Klein & Lee

20070123020 - Method for forming solder balls with a stable oxide layer by controlling the reflow ambient: By controlling the cooling rate during the oxidation process for forming an oxide layer on solder balls and by selecting an elevated temperature as an initial temperature of the oxidation process, a reliable yet easily removable oxide layer may be obtained. Consequently, yield losses during the flip chip assembly process... Agent: Williams, Morgan & Amerson

20070123022 - Semiconductor device manufacturing method: There is prepared a semiconductor construction in which a plurality of columnar electrodes are provided on an upper side of a semiconductor substrate and in which a sealing film is provided on the semiconductor substrate to cover outer peripheral surfaces of the columnar electrodes. Upper sides of the columnar electrodes... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070123024 - Eliminate imc cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during cu/low-k processing: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer... Agent: Lsi Logic Corporation

20070123025 - Forming a barrier layer in joint structures: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.... Agent: Intel Corporation C/o Intellevate, LLC

20070123023 - Method of forming dual interconnects in manufacturing mram cells: A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on... Agent: Edell, Shapiro & Finnan, LLC

20070123026 - Semiconductor device having high frequency components and manufacturing method thereof: A transistor is located on a GaAs substrate. An air bridge extends to provide a cavity above gate electrodes of the transistor. An opening is sealed by the end ball of a second wire. Further, the semiconductor device is wholly covered by sealing resin.... Agent: Leydig Voit & Mayer, Ltd

20070123028 - Methods of forming low-k dielectric layers containing carbon nanostructures: Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20070123029 - Semiconductor device and method for manufacturing the same: A semiconductor device including a multilevel wiring with a small interwiring capacitance is provided by comprising a wiring, a conductive film formed on an upper surface of the wiring to prevent diffusion of a wiring material, and an insulating film which is constituted of low dielectric constant insulating films stacked... Agent: Foley And Lardner LLP Suite 500

20070123027 - Wiring forming method, wiring forming apparatus, and wiring board: After performing one forming step of a first pattern forming step of forming a first patent on a substrate and a second pattern forming step of forming a second pattern on the substrate, the other forming step is performed to thereby form, a high-reliability wiring pattern on the substrate.... Agent: Morgan & Finnegan, L.L.P.

20070123030 - Semiconductor devices and methods of manufacturing semiconductor devices: Disclosed is a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an insulating layer and a metal interconnection. An insulating layer may include a first layer including fluorine and a second layer including SRO (silicon rich oxide) having a dangling bond. A metal... Agent: Sherr & Nourse, PLLC

20070123032 - Method for manufacturing a semiconductor device having a stepped through-hole: A DRAM device includes a contact plug in contact with a diffused region of a semiconductor substrate, and a via-plug in contact with top of the contact plug. The through-hole receiving the via-plug has stepped structure including a tapered upper portion formed by an anisotropic dry etching and a larger-diameter... Agent: Young & Thompson

20070123031 - Method for production of semiconductor device: A short circuit with an adjacent hole is prevented. By enlarging a hole diameter in the lower part of the hole, a stable storage node is formed without causing a decrease in capacitance. Provided is a method for production of a semiconductor device, comprising the steps of: forming the second... Agent: Sughrue Mion, PLLC

20070123033 - Method of forming a damascene structure with integrated planar dielectric layers: Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a barrier metal over the dielectric material and the exposed... Agent: Ingrassia Fisher & Lorenz, P.C.

20070123034 - Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layer: By forming a thin passivation layer after the formation of openings connecting to a highly reactive metal region, any queue time effects may be significantly reduced. Prior to the deposition of a barrier/adhesion layer, the passivation layer may be efficiently removed on the basis of a heat treatment so as... Agent: Williams, Morgan & Amerson

20070123036 - Method of filling structures for forming via-first dual damascene interconnects: A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating is partially cured by baking at a low temperature. Next, a solvent is dispensed... Agent: Hovey Williams LLP

20070123037 - Method of forming pattern using fine pitch hard mask: A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that... Agent: Volentine Francos, & Whitt PLLC

20070123035 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070123038 - Method for manufacturing semiconductor device: In embodiments, a method for manufacturing a semiconductor device may include forming a diffusion preventing layer on a semiconductor substrate having a conductive layer, forming an intermetallic insulating layer on the diffusion preventing layer, forming a trench photo resist layer formed above the intermetallic insulating layer of a first photo... Agent: Sherr & Nourse, PLLC

20070123039 - Electroless plating of metal caps for chalcogenide-based memory devices: A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer... Agent: Dinsmore & Shohl LLP

20070123040 - Method for forming storage node contact plug in semiconductor device: A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch... Agent: Townsend And Townsend And Crew, LLP

20070123041 - Apparatus and method for surface processing such as plasma processing: A plurality of electrode plates 11, 12 are arranged, in side-by-side relation, on a processor 1 of a plasma surface processing apparatus M. A slit-like hole-row 10a is formed between the adjacent electrode plates, and a hole-row group 100 is constituted by the side-by-side arranged hole-rows 10a. The object W... Agent: Sughrue Mion, PLLC

20070123042 - Methods to form heterogeneous silicides/germanides in cmos technology: Methods of fabricating a semiconductor structure including heterogeneous suicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous suicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the present invention, the inventive methods utilize a combination of... Agent: Scully Scott Murphy & Presser, PC

20070123043 - A semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer: By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070123044 - Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction: A new technique is disclosed in which a barrier/capping layer for a copper-based metal line is formed by using a thermal-chemical treatment with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma-based deposition of silicon nitride and/or silicon carbon nitride. The thermal-chemical treatment... Agent: J. Mike Amerson Williams, Morgan & Amerson, P.C.

20070123045 - Method for the treatment of material, in particular in the fabrication of semiconductor components: In a method for the treatment of material, in particular in the fabrication of semiconductor components, at least one partial region of the material is implanted with ions in a targeted manner. Afterward or in a later method step, a step of etching the material is performed, the etching rate... Agent: Slater & Matsil LLP

20070123046 - Continuous in-line monitoring and qualification of polishing rates: A CMP tool can be closed loop controlled by using data, for a first polished wafer, obtained by an in-line metrology station, an in-situ monitoring system, and/or an inter-platen monitoring system to continually monitor and qualify polishing rates for the processing of subsequent polished wafers.... Agent: Fish & Richardson P.C.

20070123047 - Polishing machine, workpiece supporting table pad, polishing method and manufacturing method of semiconductor device: A pedestal pad (workpiece supporting table pad) is arranged on the top of a pedestal (workpiece supporting table) for temporarily placing and holding a pre-polished or post-polished wafer (workpiece). This pedestal pad is formed of resin, and at least a surface of the pedestal pad which comes into contact with... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070123048 - Use of a plasma source to form a layer during the formation of a semiconductor device: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070123050 - Etch process used during the manufacture of a semiconductor device and systems including the semiconductor device: A carbon or carbon-containing underlayer, which is used as a mask, is patterned using a process comprising, in one specific embodiment, boron trichloride and oxygen under specified processing conditions to etch the underlayer. The underlayer is then used as a mask to etch a layer below the underlayer, such as... Agent: Micron Technology, Inc.

20070123049 - Semiconductor process and method for removing condensed gaseous etchant residues on wafer: A semiconductor process is provided. A substrate is provided and then a to-be-etched layer is formed on the substrate. A patterned photoresist layer is formed on the to-be-etched layer. The to-be-etching layer is etched using a gaseous etchant to form a patterned layer. In the meantime, some of the gaseous... Agent: Jianq Chyun Intellectual Property Office

20070123051 - Oxide etch with nh4-nf3 chemistry: The present invention generally provides apparatus and methods for selectively removing various oxides on a semiconductor substrate. One embodiment of the invention provides a method for selectively removing an oxide on a substrate at a desired removal rate using an etching gas mixture. The etching gas mixture comprises a first... Agent: Patterson & Sheridan, LLP

20070123052 - Process sequence for photoresist stripping and cleaning of photomasks for integrated circuit manufacturing: A method and system for cleaning and/or stripping photoresist from photomasks used in integrated circuit manufacturing comprising a process and means of introducing a mixture of sulfuric acid and ozone (or a mixture of sulfuric acid and hydrogen peroxide) to the surface of a photomask while applying megasonic energy. The... Agent: Wolf, Block, Schorr & Solis-cohen LLP

20070123053 - Self-aligned pitch reduction: A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first... Agent: Beyer Weaver LLP

20070123054 - Nanocoils, systems and methods for fabricating nanocoils: Improved nanocoils, systems and methods for fabricating nanocoils. Embodiments enable wet etching techniques for releasing coiling arm structures and forming nanocoils. A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer in which SOI wafer includes a buried oxide layer, patterning one or more devices onto a silicon device... Agent: Andrews Kurth LLP Intellectual Property Department

20070123055 - Insulating material: Disclosed is an insulating material containing an epoxy resin, a curing agent and a nano-filling material having an aspect ratio of not more than 40 at a thickness of not more than 2 nm. The nano-filling material comprises an organized clay dispersed in the epoxy resin. The organized clay is... Agent: Harness, Dickey & Pierce, P.L.C

20070123056 - Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer: A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of... Agent: Freescale Semiconductor, Inc. Law Department

20070123057 - Overvoltage protection materials and process for preparing same: The invention provides a process for preparing an overvoltage protection material comprising: (i) preparing a mixture comprising a polymer binder precursor and a conductive material; and (ii) heating the mixture to cause reaction of the polymer binder precursor and generate a polymer matrix having conductive material dispersed therein, wherein the... Agent: Berkeley Law & Technology Group, LLP

20070123058 - Semiconductor device structures that include sacrificial, readily removable materials: A semiconductor device structure includes a sacrificial element and at least one feature adjacent to and at least partially formed by the sacrificial element. The sacrificial element may include a plurality of adjacent, mutually adhered regions. A substrate, such as a semiconductor device or other semiconductor device component, may carry... Agent: Trask Britt, P.C./ Micron Technology

20070123060 - Method for the deposition of a film by cvd or ald: Methods and apparatus for deposition of a film on a substrate in a reaction chamber by an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process include providing one or more reactants, and providing a volatile neutral coordinating ligand capable of coordinating at least one selected from the following:... Agent: Knobbe Martens Olson & Bear LLP

20070123059 - Methods of internal stress reduction in dielectric films with chemical incorporation and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a porous dielectric layer comprising at least one active end group, and bonding at least one large atomic radii species to replace the at least one active end group, wherein a local swelling may be formed... Agent: Intel Corporation C/o Intellevate, LLC

20070123061 - Method of treating a substrate, method of processing a substrate using a laser beam, and arrangement: The present invention relates generally to a method of and arrangement treating a substrate processed using a laser beam, wherein said substrate comprises at least a body of semiconductor material. The method comprises a step of etching said substrate for removing from said body of semiconductor material recast material deposited... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070123062 - Semiconductor device and method of manufacturing the same: In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure... Agent: Mills & Onello LLP

20070123063 - Method of manufacturing a semiconductor integrated circuit device: Decreasing foreign materials adhering to a semiconductor substrate to improve a yield and decreasing handling errors for the semiconductor substrate to improve an operating ratio of the semiconductor manufacturing apparatus. A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070117230 - Computer readable storage medium for work-in-process schedules: A computer readable storage medium for work in progress (WIP) schedules in semiconductor manufacturing facility. After determining starting and ending dates of predetermined schedule periods for generating WIP schedules, remaining days are determined for completing at least one wafer lot associated with predetermined product from the starting date. A starting... Agent: Steven E. Koffs

20070117225 - Integrated inspection system and defect correction method: A system for the inspection of and a process for the correction of defects in a microreplicated optical display film manufacturing process. The process steps of manufacturing a master, a plurality of shims from the master, and a multiplicity of display films from each shim are integrated with a systemic... Agent: Cantor Colburn, LLP

20070117226 - Method and apparatus for processing timeout in dsg apparatus: A method and apparatus for processing a timeout in a device that complies with the DSG standard are provided. The method includes detecting whether a Tdsg4 timeout has occurred in the first device; and transmitting a Tdsg4 timeout message indicating that a Tdsg4 timeout has occurred in the first device... Agent: Sughrue Mion, PLLC

20070117227 - Method and system for iteratively, selectively tuning a parameter of a doped workpiece using a pulsed laser: A method and system for iteratively, selectively tuning a parameter of a doped workpiece, such as the impedance of an integrated semiconductor device, by modifying the dopant profile of a region of relatively low dopant concentration by controlled diffusion of dopants from one or more adjacent regions of relatively higher... Agent: Brooks Kushman P.C.

20070117229 - Methods for minimizing defects when transferring a semiconductor useful layer: A method for minimizing defects when transferring a useful layer from a donor wafer to a receptor wafer is described. The method includes providing a donor wafer having a surface below which a zone of weakness is present to define a useful layer to be transferred, molecularly bonding at a... Agent: Winston & Strawn LLP Patent Department

20070117231 - Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor: A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, includes an orthogonal wire having a first minimum wire width which is formed on a first wiring layer and extends horizontally or vertically; a diagonal wire having a second minimum... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070117228 - Teaching apparatus and teaching method: A teaching apparatus and a teaching method that facilitates accurately setting a retainer at a target position, and minimizes troublesome steps in the manufacturing process, are to be provided. The teaching apparatus includes a first member held by the retainer of the carrying apparatus, a second member attached to the... Agent: Young & Thompson

20070117232 - Method of studying interaction between immersion fluid and substrate: A method and measurement tools for studying interaction between an immersion fluid and a material in a substrate, such as, e.g., a photoresist or a topcoat or components thereof, are provided. The method comprises providing a spatially controlled contact between only part of the substrate and the immersion fluid. The... Agent: Knobbe Martens Olson & Bear LLP

20070117233 - Film pattern forming method, device, electro-optical apparatus, and electronic appliance: A method for forming a film pattern by disposing a functional fluid on a substrate, includes: forming a partition wall that includes a first opening that corresponds to a first film pattern and a second opening that corresponds to a second film pattern; and disposing a droplet of the functional... Agent: Harness, Dickey & Pierce, P.L.C

20070117234 - Sputtered spring films with low stress anisotropy: Methods are disclosed for fabricating spring structures that minimize helical twisting by reducing or eliminating stress anisotropy in the thin films from which the springs are formed through manipulation of the fabrication process parameters and/or spring material compositions. In one embodiment, isotropic internal stress is achieved by manipulating the fabrication... Agent: Bever, Hoffman & Harms, LLP

20070117235 - Method for producing an electrical contact for an optoelectronic semiconductor chip: A method for producing an electrical contact of an optoelectronic semiconductor chip (1), comprising providing a mirror layer (2), comprised of a metal or metal alloy, over the semiconductor chip; providing a protective layer (3) over said mirror layer; providing a layer sequence of a barrier layer and a coupling... Agent: Cohen Pontani Liberman & Pavane LLP

20070117236 - Method of manufacturing optical module: A method of manufacturing an optical module having an optical element includes: (a) providing a housing having a base portion and a frame portion provided on the base portion; (b) providing a spacer on the base portion of the housing; (c) pressing the spacer to plastically deform the spacer; (d)... Agent: Oliff & Berridge, PLC

20070117237 - Amorphous transparent conductive film, sputtering target as its raw material, amorphous transparent electrode substrate, process for producing the same and color filter for liquid crystal display: A transparent conductive film of low resistivity excelling in transparency and etching properties; a sputtering target as its raw material; an amorphous transparent electrode substrate having the transparent conductive film superimposed on a substrate; and a process for producing the same. In particular, an amorphous transparent conductive film comprising at... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070117239 - Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus: An electro-optical device includes, above a substrate, a plurality of data lines and a plurality of scanning lines that cross each other, a plurality of pixel electrodes that are provided so as to correspond to intersections between the plurality of data lines and the plurality of scanning lines, and transistors,... Agent: Advantedge Law Group, LLC

20070117238 - Liquid crystal display device and method for fabricating the same: A method for fabricating a liquid crystal display (LCD) device includes: forming a gate line, a gate electrode, and a gate pad electrode on a substrate; sequentially forming a gate insulating layer, a semiconductor layer and a metal layer on an entire surface of the substrate including the gate electrode;... Agent: Mckenna Long & Aldridge LLP

20070117240 - Liquid crystal display with positional marks for bonding drive ic: An exemplary liquid crystal display (2) includes a liquid crystal panel (20) and a drive integrated circuit (IC) (21). The liquid crystal panel includes a plurality of circuit pads (202), a first positional mark (2031), and a second positional mark (2032). The drive IC includes a plurality of metal bumps... Agent: Wei Te Chung Foxconn International, Inc.

20070117241 - Method for making a shadow mask for an apposed discharge plasm display panel: The present invention is to provide a method for making a shadow mask for an opposed discharge plasma display panel by etching one lateral surface of a metal slab to produce a plurality of parallel and equidistant barrier ribs along the vertical and horizontal directions on the lateral surface and... Agent: Bacon & Thomas, PLLC

20070117242 - Providing photonic control over wafer borne semiconductor devices: Disclosed are methods for providing wafer photonic flow control to a semiconductor wafer (1700) having a substrate (1720), at least one active layer (1765) and at least one surface layer (1710). Photonic flow control can be achieved through the formation of trenches (1725) and/or insulating implants (1730) formed in said... Agent: Honeywell International Inc.

20070117243 - Method of fabricating a biosensor: The present invention provides a method of fabricating a biosensor. The method includes providing a substrate which has a surface coating. The surface coating is deformable and the substrate includes a layered structure which has at least two electrically conductive layers separated by at least one electrically insulating layer. The... Agent: Hewlett Packard Company

20070117244 - Preferentially deposited lubricant to prevent anti-stiction in micromechanical systems: Embodiments of the present invention generally relate to a device that has an improved usable lifetime due to the presence of a lubricant that reduces the likelihood of stiction occurring between the various moving parts in an electromechanical device. Embodiments of the present invention also generally include a device, and... Agent: Patterson & Sheridan, L.L.P.

20070117245 - Wafer level package for micro device and manufacturing method thereof: A wafer level package includes a device wafer having a micro device, and bonding pads which are connected to the micro device, and formed at one surface of the device wafer, via connectors extending from the bonding pads to the other surface of the device wafer, external bonding pads formed... Agent: Lowe Hauptman Berner, LLP

20070117246 - Metal mems devices and methods of making same: Metal MEMS structures are fabricated from metal substrates, preferably titanium, utilizing micromachining processes with a new deep etching procedure to provide released microelectromechanical devices. The deep etch procedure includes metal anisotropic reactive ion etching utilizing repetitive alternating steps of etching and side wall protection. Variations in the timing of the... Agent: Gates & Cooper LLP Howard Hughes Center

20070117247 - Manufacturing method of microstructure: A manufacturing method of a microstructure includes the steps of: providing a substrate; forming a photoresist layer on the substrate; providing a first mask, which has at least one opaque area and at least one first lens, over the photoresist layer; providing a light source for illuminating the photoresist layer... Agent: Birch Stewart Kolasch & Birch

20070117248 - Method for the production of light-emitting semiconductor diodes: A method is disclosed for creating a light assembly including a light-emitting diode and a printed circuit board having conductors printed thereon. The method includes the steps of positioning the light-emitting diode on the printed circuit board. Once positioned, the light-emitting diode is connected to the printed circuit board. The... Agent: Clark Hill, P.C.

20070117250 - Method of increasing a free carrier concentration in a semiconductor substrate: A method of selectively heating a predetermined region of a semiconductor substrate includes providing a semiconductor substrate, selectively focusing a free carrier generation light on only a predetermined region of the semiconductor substrate, irradiating the free carrier generation light on the predetermined region of the semiconductor substrate to increase a... Agent: Lee & Morse, P.C.

20070117249 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units: Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality... Agent: Dickstein Shapiro LLP

20070117251 - Display device, flat lamp and method of fabricating the display device and flat lamp: A display device and a flat lamp that have simple structures and can be fabricated using simple fabricating processes, and a method of fabricating the display device and the flat lamp. The display device includes: a first substrate and a second substrate facing each other across a predetermined distance; barrier... Agent: Stein, Mcewen & Bui, LLP

20070117252 - Silicon-containing antireflective coating forming composition, silicon-containing antireflective coating, substrate processing intermediate, and substrate processing method: A composition for forming an antireflective coating for use in a photolithography process using exposure light of up to 200 nm comprises a silicon-containing polymer obtained through hydrolytic condensation of a silicon-silicon bond-containing silane compound having formula: R(6-m)Si2Xm wherein R is a monovalent hydrocarbon group, X is alkoxy, alkanoyloxy or... Agent: Birch Stewart Kolasch & Birch

20070117254 - Back-illuminated imager and method for making electrical and optical connections to same: Methods for bringing or exposing metal pads or traces to the backside of a backside-illuminated imager allow the pads or traces to reside on the illumination side for electrical connection. These methods provide a solution to a key packaging problem for backside thinned imagers. The methods also provide alignment marks... Agent: Ladas & Parry

20070117253 - Method for providing metal extension in backside illuminated sensor for wafer level testing: A method of providing metal extension in a backside illuminated image sensor is provided in the present disclosure. In one embodiment, a first set of pads and a second set of pads, and a metal layer are provided in a backside illuminated image sensor. The first set of pads are... Agent: Haynes And Boone, LLP

20070117255 - Formation of contacts on semiconductor substrates: Embodiments of the invention are concerned with a method of manufacturing a radiation detector having one or more conductive contacts on a semiconductor substrate, and comprise the steps of: applying a first conductive layer to a first surface of the semiconductor substrate: applying a second conductive layer to form a... Agent: Kenyon & Kenyon LLP

20070117256 - Control layer for a nanoscale electronic switching device: A control layer for use in a junction of a nanoscale electronic switching device is disclosed. The control layer includes a material that is chemically compatible with a connecting layer and at least one electrode in the nanoscale switching device. The control layer is adapted to control at least one... Agent: Hewlett Packard Company

20070117257 - Organic light emitting diode display: An OLED display comprises a barrier layer to substantially block moisture from an organic material. For example, an OLED display includes a substrate, a first signal line formed on the substrate, a second signal line crossing the first signal line, a driving voltage line formed on the substrate to transfer... Agent: Macpherson Kwok Chen & Heid LLP

20070117262 - Low profile stacking system and method: The present invention provides a system and method that amounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is... Agent: Fish & Richardson P.C.

20070117258 - Method for the molecular bonding of microelectronic components to a polymer film: A method for direct molecular adhesion of an electronic compound (6) on a polymer (4) is described. The polymer (4) is coated with a bonding layer (5), for example silicon oxide, which enables the problems caused by the presence of hydrocarbons to be overcome. The method makes it possible to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070117260 - Method of manufacturing semiconductor sensor: A method of manufacturing a semiconductor sensor includes a forming step, a preparing step, a fixing step and a separating step. In the forming step, a plurality of caps made of resin is formed on a supporting substrate through a separable agent. Each of the caps has a cavity therein.... Agent: Posz Law Group, PLC

20070117263 - Microelectronic or optoelectronic package having a polybenzoxazine-based film as an underfill material: Microelectronic and optoelectronic packaging embodiments are described with underfill materials including polybenzoxazine, having the general formula:... Agent: Intel/blakely

20070117261 - Multilayer printed wiring board and method for producing the same: A multilayer printed wiring board includes a flexible portion that is constituted from a flexible base material in which an inner layer circuit pattern has been formed, and a hard portion that is constituted from a hard base material that is layered on a portion of the flexible base material... Agent: Birch Stewart Kolasch & Birch

20070117259 - Semiconductor component and method of manufacture: A circuit component having one or more encapsulated circuit elements that are not disposed on a rigid support substrate and a method for manufacturing the circuit component. A semiconductor wafer is disposed on a dicing film and singulated into individual semiconductor chips. The dicing film is stretched and a protective... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070117264 - flip-chip semiconductor device manufacturing method: The objective of the invention is to provide a semiconductor device manufacturing method that can suppress the formation of voids in the underfill resin and realize a highly reliable flip-chip assembly. The semiconductor device manufacturing method pertaining to the present invention comprises the following processing steps: a step of operation... Agent: Texas Instruments Incorporated

20070117266 - Method of fabricating a multi-die semiconductor package assembly: An apparatus and method for increasing integrated circuit density comprising an upper die and a lower die, the latter preferably a flip chip, which are connected to a conductor-carrying substrate or a leadframe. The upper die is attached back-to-back to the lower die with a layer of adhesive applied over... Agent: Trask Britt, P.C./ Micron Technology

20070117265 - Semiconductor device with improved stud bump: The objective of this invention is to provide a type of semiconductor device enabling highly reliable flip chip connection. Semiconductor chip for flip chip assembly has gold stud bumps on a principal surface having a semiconductor integrated circuit formed on it, and the gold stud bumps contain silver (Ag). It... Agent: Texas Instruments Incorporated

20070117267 - Semiconductor multi-package module having inverted land grid array (lga) package stacked over ball grid array (bga) package: A semiconductor multi-package module has a second package inverted and stacked over a first package, each of the packages having a die attached to a substrate, in which the second package substrate and the first package substrate are interconnected by wire bonding, and in which the first package includes a... Agent: Haynes Beffel & Wolfeld LLP

20070117268 - Ball grid attachment: A device and method employing an electrically conductive adhesive for electrically and mechanically connecting an electrical component to a board substrate. The electrical component can includes an integrated circuit and the board may include a printed circuit board. The possible adhesives include a silver conducting RTV, silver-conducting adhesive, as well... Agent: Gilbreth Roebuck Bynum Derrington Schmidt Walker & Tran, LLP

20070117269 - Method for packaging flash memory cards: A method for packaging flash memory cards is provided, including a step of forming a protective membrane. The purpose of the protective membrane is to protect the circuit from the movement and the heat of the subsequent insert molding process. An insert molding step is used to seal the substrate... Agent: Lin & Associates Intellectual Property

20070117270 - Integrated heat spreader with intermetallic layer and method for making: Integrated heat spreader and die coupled with solder in a manner forming an intermetallic compound having a higher liquidus temperature than the liquidus temperature of the solder used to create the intermetallic compound are described herein.... Agent: Schwabe, Williamson & Wyatt, P.C.

20070117272 - Method of making a semiconductor device with improved heat dissipation: A method of making a heat dissipation member comprising the steps of forming a resist on a substrate, removing a portion or portions of said resist formed on the substrate in places where posts are to be formed, forming the posts on the substrate in said places where the resist... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070117271 - Methods and compositions for the formation of recessed electrical features on a substrate: Precursor compositions having a low conversion temperature and methods for the fabrication of recessed electrical features from the precursor compositions. The electrical features can be conductors, resistors and dielectric features. The precursor compositions are deposited into recessed features, such as trenches, formed in a substrate and are reacted at a... Agent: Jaimes Sher, Esq. Cabot Corporation

20070117273 - Accurate alignment of an led assembly: An LED assembly includes a heat sink and a submount. The heat sink has a top mating surface that is solder wettable, and the submount has a bottom mating surface that is solder wettable. The top and the bottom mating surfaces have substantially the same shape and area. The submount... Agent: Patent Law Group LLP

20070117274 - Apparatus incorporating small-feature-size and large-feature-size components and method for making same: An apparatus incorporating small-feature size and large-feature-size components. The apparatus comprise a strap including a substrate with an integrated circuit contained therein. The integrated circuit coupling to a first conductor disposed on the substrate. The first conductor is made of a thermosetting or a thermoplastic material including conductive fillers. A... Agent: Blakely Sokoloff Taylor & Zafman

20070117275 - Mems device packaging methods: A method of packaging a MEMS device that includes, for example, the steps of providing a MEMS die that has a MEMS device, a seal ring and bond pads disposed thereon, providing a MEMS package that has a recess, a seal ring and bond pads disposed thereon, positioning the MEMS... Agent: Honeywell International Inc.

20070117277 - Methods for fabricating protective layers on semiconductor device components: Methods for packaging semiconductor device components include introducing a consolidatable material over a semiconductor device structure, and selectively consolidating the material so that contacts are exposed through the resulting package features. Selective consolidation may be effected in accordance with a program or as consolidating energy is directed toward the consolidated... Agent: Trask Britt, P.C./ Micron Technology

20070117276 - Small form factory molded memory card and a method thereof: A shape-molding structure of a memory card comprises a circuit substrate, at least one chip, and an encapsulant covering. The upper and lower surfaces of the circuit substrate have a circuit layer and a plurality of electric contacts, respectively. The chip is located on the upper surface of the circuit... Agent: Sawyer Law Group LLP

20070117278 - Formation of devices on a substrate: A method of forming a thin film device on a flexible substrate is disclosed. The method includes depositing an imprintable material over the flexible substrate. The imprintable are stamped material forming a three-dimensional pattern in the imprintable material. A sacrificial layer is formed over the three-dimensional pattern. A conductive layer... Agent: Hewlett Packard Company

20070117280 - Manufacturing liquid crystal display substrates: Methods and apparatus for manufacturing an LCD substrate include forming a gate electrode of a pixel switching element on a base substrate, forming a gate insulating layer on the base substrate, forming a source electrode and a drain electrode of the switching element on the gate insulating layer, forming a... Agent: Macpherson Kwok Chen & Heid LLP

20070117281 - Method for manufacturing bonded substrate and bonded substrate manufactured by the method: A high quality bonded substrate is obtained in which generation of microprotrusions and cracked particles are restricted on a surface of an active layer of the bonded substrate and the surface of the active layer is flattened. A laminated body is formed by overlapping a first semiconductor substrate serving as... Agent: Reed Smith, LLP Attn: Patent Records Department

20070117283 - Method for patching up thin-film transistor circuits on a display panel by local thin-film deposition: A method for patching up thin-film transistor (TFT) circuit patterns on a display panel comprises the following steps. Firstly, a mask having an opening is placed above the display panel and the opening corresponds to the location of the cracks of the circuits on the display panel. Subsequently, a plasma... Agent: Troxell Law Office PLLC

20070117279 - Semiconductor thin film using self-assembled monolayers and methods of production thereof: A semiconductor thin film using a self-assembled monolayer (SAM) and a method for producing the semiconductor thin film are provided. According to the semiconductor thin film, a uniform inorganic seed layer is formed by using the self-assembled monolayer so that the adhesion between an insulating layer and a semiconductor layer... Agent: Cantor Colburn, LLP

20070117282 - Thin film transistor and method for manufacturing the same: The present invention provides a thin-film transistor that is formed by using a patterning method capable of forming a semiconductor channel layer in sub-micron order and a method for manufacturing thereof that provides a thin-film transistor with a larger area, and suitable for mass production. These objects are achieved by... Agent: Ladas & Parry LLP

20070117289 - thin film apparatus, a manufacturing method of the thin film apparatus, an active matrix substrate, a manufacturing method of the active matrix substrate, and an electro-optical apparatus having the active matrix substrate: A manufacturing method of a thin film apparatus, includes: a first step for forming a separation layer on a heat resistant substrate; a second step for forming a thin film device on the separation layer; a third step for providing a surface layer on the thin film device; and a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070117287 - Laser irradiation apparatus: Since the size of a plate for issuing gas used for a conventional laser irradiation apparatus is large and the distance between an optical system through which a laser light lastly passes and the plate is not enough, it is difficult to check the state of laser light delivered from... Agent: Eric Robinson

20070117288 - Laser irradiation apparatus: Since the size of a plate for issuing gas used for a conventional laser irradiation apparatus is large and the distance between an optical system through which a laser light lastly passes and the plate is not enough, it is difficult to check the state of laser light delivered from... Agent: Eric Robinson

20070117285 - Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench (14), which reaches down to the insulator (11) and surrounds a region (13′) of the monocrystalline silicon (13) of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which... Agent: Baker Botts, L.L.P.

20070117286 - Polycrystalline silicon and crystallization method thereof: Disclosed are a polycrystalline silicon and a crystallization method thereof according to an exemplary embodiment of the present invention. The polycrystalline silicon comprises: an insulating substrate; and an optical portion formed on the insulating substrate for receiving a CW laser beam and varying the intensity of the beam in order... Agent: Birch Stewart Kolasch & Birch

20070117284 - Thin film transistor, method of manufacturing same, display device, method of modifying an oxide film, method of forming an oxide film, semiconductor device, method of manufacturing semiconductor device, and apparatus for manufacturing semiconductor devic: In a manufacturing method of a thin film transistor (1), the oxide film forming step is performed whereby: a process-target substrate (2) having a surface on which a gate oxide film (4) should be formed is immersed in an oxidizing solution containing an active oxidizing species; and a gate oxide... Agent: Nixon & Vanderhye, PC

20070117290 - Method of manufacturing a low temperature polysilicon film: A method of manufacturing a low temperature polysilicon film is provided. A first metal layer is formed on a substrate; and openings have been formed in the first metal layer. A second metal layer is formed on the first metal layer: and a hole corresponding to each of the openings... Agent: Jianq Chyun Intellectual Property Office

20070117292 - Display device and fabrication method thereof: The present invention provides a display-device-use substrate which is strip-crystallized while minimizing the generation of peeling of a semiconductor by suppressing the generation of aggregation at the time of crystallization due to the radiation of continuous oscillation laser beams. A silicon nitride film and a silicon oxide film which constitutes... Agent: Stanley P. Fisher Reed Smith LLP

20070117293 - Semiconductor device and method of manufacturing the same: There is provided a method in which a TFT with superior electrical characteristics is manufactured and a high performance semiconductor device is realized by assembling a circuit with the TFT. The method of manufacturing the semiconductor device includes: a step of forming a crystal-containing semiconductor film by carrying out a... Agent: Eric Robinson

20070117291 - Technique for film grain simulation using a database of film grain patterns: Individual pixels in an image block undergo blending with film grain from a film grain block randomly selected from among a pool of previously established film grain blocks in accordance with a luma characteristic of the image block. Prior to blending, the selected film grain block undergoes deblocking by a... Agent: Joseph J. Laks, Vice President Thomson Licensing LLC

20070117297 - Cmos integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same: CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained... Agent: Myers Bigel Sibley & Sajovec

20070117296 - Method for fabricating a field effect transistor, and field effect transistor: In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed... Agent: Dickstein Shapiro LLP

20070117294 - Method for fabricating semiconductor device with metal-polycide gate and recessed channel: A method for fabricating a semiconductor device with a metal-polycide gate and a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor substrate having the trenches; forming a gate conductive layer... Agent: Marshall, Gerstein & Borun LLP

20070117295 - Method for manufacturing semiconductor device having metal silicide layer: A method for manufacturing a semiconductor device having a metal silicide layer comprises forming a structure including a plurality of gate stacks formed on a semiconductor substrate, forming a gate spacer layer formed on an upper surface of the semiconductor substrate and around a sidewall of each gate stack, and... Agent: Townsend And Townsend And Crew, LLP

20070117298 - Field effect transistor and method of manufacturing the same: A TFT having a large mobility of carriers that are conducted through a channel as compared with a conventional organic TFT, and a method of manufacturing the TFT inexpensively and easily are provided. The channel is formed of a semiconductor organic molecular crystal thin film which is highly oriented, and... Agent: Reed Smith LLP

20070117299 - Memory cells having underlying source-line connections: Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed at regular intervals across a memory array. Such floating-gate memory cells have their drain regions and source regions formed in a first semiconductor region having a first conductivity... Agent: Leffert Jay & Polglaze, P.A.

20070117300 - Method of forming silicon-on-insulator (soi) semiconductor substrate and soi semiconductor substrate formed thereby: A silicon-on-insulator (SOI) semiconductor substrate includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrates an SOI layer formed on the buried oxide layer, and a diffusion barrier layer interposed between the buried oxide layer and the SOI layer, wherein the diffusion barrier layer is an insulating... Agent: F. Chau & Associates, LLC

20070117301 - Method for forming non-volatile memory with inlaid floating gate: A method for forming a non-volatile memory with inlaid floating gate is disclosed. The method comprises the following steps. A substrate having a pad dielectric layer and a first dielectric layer thereon is provided. Then a buried diffusion region is formed in the substrate. Next a second dielectric layer is... Agent: Birch Stewart Kolasch & Birch

20070117302 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device, including the steps of forming a gate on a semiconductor substrate in which a cell region, a source selection line region, and a drain selection line region are defined and then forming spacers on sidewalls of the gate; depositing a nitride film... Agent: Marshall, Gerstein & Borun LLP

20070117303 - Semiconductor memory device (as amended): A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070117304 - Method for patterning hfo2-containing dielectric: A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. An ion bombardment utilizing Ar, He, O2, CHF3... Agent: North America Intellectual Property Corporation

20070117305 - Semiconductor device having reduced gate charge and reduced on resistance and method: In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070117306 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate, a first diffusion region formed in the semiconductor substrate, a semiconductor element formed in the first diffusion region, and a channel formed in the first diffusion region to receive a cooling fluid.... Agent: Foley And Lardner LLP Suite 500

20070117308 - Semiconductor constructions, and methods of forming semiconductor constructions: The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion.... Agent: Wells St. John P.s.

20070117307 - Trench memory cells with buried isolation collars, and methods of fabricating same: The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrate, and it comprises inner and outer electrodes and a dielectric... Agent: Scully Scott Murphy & Presser, PC

20070117309 - Method for fabricating capacitor in semiconductor device: The present invention relates to a method for fabricating a capacitor in a semiconductor device through the use of hafnium-terbium oxide (Hf1-xTbxO) as a dielectric layer. The method includes the steps of: forming a lower electrode on a substrate; forming an amorphous hafnium-terbium oxide (Hf1-xTbxO) dielectric layer on the lower... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070117310 - Multiple deposition for integration of spacers in pitch multiplication process: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where... Agent: Knobbe Martens Olson & Bear LLP

20070117312 - Method for fabricating capacitor of semiconductor device: A method for fabricating a capacitor of a semiconductor device includes: forming a first insulation layer over a substrate; forming a plug in the first insulation layer to contact the substrate; forming an etch stop layer and a second insulation layer over a resultant structure obtained after forming the plug;... Agent: Blakely Sokoloff Taylor & Zafman

20070117313 - Mim capacitor and method of fabricating same: A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a... Agent: Schmeiser, Olsen & Watts

20070117311 - Three-dimensional single transistor semiconductor memory device and methods for making same: Single-transistor memory cell including a three-dimensional capacitor and methods for fabricating the cell are disclosed. The method includes steps for defining a source and drain, forming a channel between the source and drain, and forming a gate area of a transistor. The method also includes forming a first and second... Agent: Fulbright & Jaworski L.L.P.

20070117314 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, comprises forming a gate insulating film on a surface of a semiconductor substrate, forming a first group of at least one strip-like gate electrode and a second group of strip-like gate electrodes on a surface of the gate insulating film, each strip-like gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070117320 - Flash memory device and method for fabricating the same: A flash memory device includes a floating gate formed with a byproduct, such as a polymer, generated in an etching process. The flash memory device is configured to minimize the unstableness often caused by a floating gate that includes direct contact between polymer and polysilicon. Formation of the floating gate... Agent: Mckenna Long & Aldridge LLP

20070117321 - Flash memory device and method of manufacturing the same: A flash memory device and method of manufacturing the same. The flash memory device includes a semiconductor substrate in which a first region where a cell region is formed, a second region where a peripheral region is formed, and a third region formed in the peripheral region at the boundary... Agent: Mayer, Brown, Rowe & Maw LLP

20070117315 - Memory cell device and manufacturing method: A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a hole in the separation layer, a second material in the hole defining a void having a downwardly and inwardly tapering void... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070117322 - Method for fabricating nand type dual bit nitride read only memory: A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures... Agent: Rabin & Berdo, PC

20070117318 - Method of manufacturing nand flash memory device: A method of manufacturing a NAND flash memory device, consisting of the steps of consecutively etching a polysilicon layer, a tunnel oxidization layer, and a semiconductor substrate in a polysilicon layer chamber. Accordingly, an etch step and a cleaning step can be reduced, the Turn Around Time (TAT) can be... Agent: Marshall, Gerstein & Borun LLP

20070117319 - Programming and erasing structure for a floating gate memory cell and method of making: A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween.... Agent: Freescale Semiconductor, Inc. Law Department

20070117316 - Semiconductor device and method of manufacturing the same: A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are formed between the first and second... Agent: Marshall, Gerstein & Borun LLP

20070117317 - Stacked memory: In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement,... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070117323 - Method for manufacturing a multiple-gate charge trapping non-volatile memory: A method for manufacturing a multiple-gate memory cell which comprises a semiconductor body and a plurality of gates arranged in series and the semiconductor body includes first forming a plurality of gates spaced apart by about a gate width, forming an isolation layer on the sidewalls, and filling between the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070117325 - Semiconductor device and manufacturing method therefor: The gate electrode of a high-voltage transistor having a high breakdown voltage is formed from a polysilicon layer having a larger average grain size, so that depletion of the gate electrode easily occurs. By utilizing this depletion, the electrical effective film thickness required by the gate dielectric film of the... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20070117324 - Vertical mos transistor and fabrication process: The invention relates to a vertical field-effect transistor. It comprises an island (12) of doped single-crystal semiconductor material, comprising a drain region (15) and a drain contact region (17) placed laterally with respect to the drain region, and above the island, a source region (38) and several vertical parallel channels... Agent: Lowe Hauptman Gilman & Berner, LLP

20070117326 - Material architecture for the fabrication of low temperature transistor: A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example... Agent: William Stoffel

20070117327 - Methods of forming integrated circuit devices having a resistor pattern and plug pattern that are made from a same material: An integrated circuit device is formed by forming a resistor pattern on a substrate. An interlayer dielectric layer is formed on the resistor pattern. The interlayer dielectric layer is patterned to form at least one opening that exposes the resistor pattern. A plug pattern is formed that fills the at... Agent: D. Scott Moore Myers Bigel Sibley & Sajovec, P.A.

20070117328 - Vertical transistor with field region structure: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region... Agent: J.c. Patents

20070117329 - Insulated gate type semiconductor device and method for fabricating the same: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both... Agent: Miles & Stockbridge PC

20070117330 - Sensing amplifier: A sensing amplifier comprising a program cell current sensing circuit, an erase cell current sensing circuit and a latch circuit is provided. Each of the program and erase cell current sensing circuits further comprises a plurality of program/erase memory cells, a first NMOS transistor, a second NMOS transistor, a third... Agent: Jianq Chyun Intellectual Property Office

20070117331 - Reliable high voltage gate dielectric layers using a dual nitridation process: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate... Agent: Texas Instruments Incorporated

20070117332 - Semiconductor devices having a pocket line and methods of fabricating the same: In one embodiment, a semiconductor device comprises an active region isolated by a device isolation layer placed in a semiconductor substrate having a main surface. A molding hole is placed in the semiconductor substrate on the active region. A pocket insulating layer pattern conformally covers the molding hole. A pocket... Agent: Marger Johnson & Mccollom, P.C.

20070117333 - Semiconductor device having storage node electrode with protection film thereon and method of fabricating the same: A highly reliable semiconductor device and a method fabricating the same are provided, the semiconductor device having a low resistance electrode structure. The semiconductor device includes an interlayer insulation film formed on a semiconductor substrate. A storage node electrode is formed on the interlayer insulation film. A protection film is... Agent: Marger Johnson & Mccollom, P.C.

20070117334 - Structure and method for reducing miller capacitance in field effect transistors: A method for forming a field effect transistor (FET) device includes forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator... Agent: Cantor Colburn LLP - IBM Fishkill

20070117335 - Double-sided container capacitors using a sacrificial layer: Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer... Agent: Knobbe Martens Olson & Bear LLP

20070117336 - Minimizing degradation of sic bipolar semiconductor devices: A method of forming a bipolar device includes forming at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide on a substrate. Stacking faults that grow under forward operation of the device are segregated from at least one of... Agent: Summa, Allan & Additon, P.A.

20070117337 - Method for forming a trench capacitor: A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the first trench dielectric and along... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070117338 - Via array capacitor, wiring board incorporating a via array capacitor, and method of manufacturing the same: A via array capacitor comprising: a capacitor body including a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as... Agent: Sughrue-265550

20070117339 - Via including multiple electrical paths: A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070117340 - Integrated circuit arrangement with capacitor in an interconnect layer and method: An integrated circuit arrangement includes an undulating capacitor in a conductive structure layer. The surface area of the capacitor is enlarged in comparison with an even capacitor. The capacitor is interlinked with dielectric regions at its top side and/or its underside, so that it can be produced by methods which... Agent: Brinks Hofer Gilson & Lione

20070117341 - Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in... Agent: Texas Instruments Incorporated

20070117342 - Gcib liner and hardmask removal process: A method comprises depositing a dielectric film layer, a hard mask layer, and a patterned photo resist layer on a substrate. The method further includes selectively etching the dielectric film layer to form sub-lithographic features by reactive ion etch processing and depositing a barrier metal layer and a copper layer.... Agent: Greenblum & Bernstein, P.L.C

20070117343 - Semiconductor device having align mark layer and method of fabricating the same: A semiconductor device includes a pad electrode layer and an align mark layer, formed on the semiconductor substrate. A passivation layer is formed on the semiconductor substrate and exposes at least a portion of the top of the pad electrode layer and at least a portion of the top of... Agent: F. Chau & Associates, LLC

20070117344 - Semiconductor device including a crystal semiconductor layer, its fabrication and its operation: In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer... Agent: Marger Johnson & Mccollom, P.C.

20070117345 - Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the... Agent: Gates & Cooper LLP Howard Hughes Center

20070117346 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device can prevent a leakage current and the decrease of threshold voltage by rounding corners of a trench. The method may include the steps of forming a pad insulating layer in a semiconductor substrate defined with an active region and a device isolation region,... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070117347 - Semiconductor constructions: The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region... Agent: Wells St. John P.s.

20070117348 - 3d integrated circuits using thick metal for backside connections and offset bumps: Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first dielectric layer... Agent: Blakely Sokoloff Taylor & Zafman

20070117349 - Solid state imaging device and method for manufacturing the same: A solid state imaging device includes: a solid state imaging element including a light receiving element, a microlens formed above the light receiving element, a first transparent layer formed on the microlens and a second transparent layer formed on or above the microlens and harder than the first transparent layer;... Agent: Mcdermott Will & Emery LLP

20070117350 - Strained silicon on insulator (ssoi) with layer transfer from oxidized donor: This invention generally relates to a strained silicon on insulator (SSOI) structure, and to a process for making the same. The process includes forming a thin SiO2 layer on a strained silicon layer after it is formed on the donor wafer and before bonding to the handle wafer.... Agent: Senniger Powers

20070117352 - Method for dicing semiconductor wafers: A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction... Agent: Mark J. Marcelli Duane Morris LLP

20070117351 - Method for machining a workpiece on a workpiece support: A workpiece machining method includes attaching a workpiece to a workpiece support with the aid of joining means. The workpiece and the workpiece support are joined to one another by an annular joining means. The composite produced is machined. The machined workpiece is separated from the workpiece support.... Agent: Brinks Hofer Gilson & Lione

20070117353 - Method for forming oxide on ono structure: A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070117354 - Large area semiconductor on glass insulator: Methods and apparatus provide for contacting respective first surfaces of a plurality of donor semiconductor wafers with a glass substrate; bonding the first surfaces of the plurality of donor semiconductor wafers to the glass substrate using electrolysis; separating the plurality of donor semiconductor wafers from the glass substrate leaving respective... Agent: Corning Incorporated

20070117357 - Method of manufacturing a semiconductor light emitting device, semiconductor light emitting device, method of manufacturing a semiconductor device, semiconductor device, method of manufacturing a device, and device: When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III-V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III-V compound semiconductor substrate composed of a first region in form of a crystal having a... Agent: Sonnenschein Nath & Rosenthal LLP Sears Tower

20070117356 - Method of manufacturing single crystalline gallium nitride thick film: A method of manufacturing a single crystalline gallium nitride (GaN) thick film grown by loading a base substrate in a hydride vapor phase epitaxy (HVPE) reactor, the method including: growing a first GaN film at a first temperature, in the surface kinetics-controlled regime, where a growth rate is determined by... Agent: Mcdermott Will & Emery LLP

20070117355 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a first nitride semiconductor layer having at least one projection on an upper surface thereof; a second nitride semiconductor layer formed on a top surface of the projection of the first nitride semiconductor layer and having a higher carrier concentration than the first nitride semiconductor layer;... Agent: Mcdermott Will & Emery LLP

20070117358 - Epitaxy layer and method of forming the same: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070117359 - Deposition of amorphous silicon-containing films: Chemical vapor deposition methods are used to deposit amorphous silicon-containing films over various substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. Preferably, the deposited amorphous silicon-containing film is annealed to produce... Agent: Knobbe Martens Olson & Bear LLP

20070117360 - Isolated vertical power device structure with both n-doped and p-doped trenches: A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolation wall trenches are formed around the conduction region.... Agent: Stmicroelectronics, Inc

20070117361 - Method for manufacturing an soi substrate: A substrate surface serving as an SOI region and a substrate surface serving as a bulk region are made to form the same plane easily and highly accurately, a thickness of a buried oxide film is made uniform, and the buried oxide film is also prevented from being exposed on... Agent: Reed Smith, LLP Attn: Patent Records Department

20070117362 - Heat treatment apparatus and method of manufacturing a semiconductor device: A heat treatment apparatus which enables a heating process for a short time with high reproducibility in a manufacturing process of a MOS transistor manufactured using a semiconductor substrate and a method of manufacturing a semiconductor device using the heat treatment apparatus are provided. The heat treatment apparatus of the... Agent: Nixon Peabody, LLP

20070117363 - Barrier metal film production apparatus, barrier metal film production method, metal film production method, and metal film production apparatus: A Cl2 gas plasma is generated at a site within a chamber between a substrate and a metal member. The metal member is etched with the Cl2 gas plasma to form a precursor. A nitrogen gas is excited in a manner isolated from the chamber accommodating the substrate. A metal... Agent: Birch Stewart Kolasch & Birch

20070117364 - Method for fabricating semiconductor device with recessed channel: A method for fabricating a semiconductor device with a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor substrate having the trenches; forming a gate conductive layer on the entire surface... Agent: Marshall, Gerstein & Borun LLP

20070117366 - Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the, same conductivity type through an opening in a compound semiconductor material of the... Agent: Hiscock & Barclay, LLP

20070117367 - Fluid injection apparatus and fabrication method thereof: A fluid injection apparatus is disclosed. A chamber wall is disposed overlying the substrate to define an area. A nozzle plate comprising a nozzle is disposed overlying the chamber wall to form a chamber on the area, wherein the chamber wall and the nozzle plate are integrated into a structure... Agent: Quintero Law Office, PC

20070117365 - Plating method and apparatus: A plating method comprising applying an ultraviolet ray to a surface of a substrate or exposing a surface of a substrate to an ozone gas or bringing a surface to a substrate into contact with ozone water or bringing a surface of a substrate into contact with electrolytic ionized water... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070117368 - Structure of bumps forming on an under metallurgy layer and method for making the same: The present invention relates to a structure of bumps forming on an under bump metallurgy layer (UBM layer) and a method for making the same. The structure comprises a wafer, a UBM layer, a second photo resist and a bump. The wafer has a plurality of solder pads and a... Agent: Volentine Francos, & Whitt PLLC

20070117369 - Method for interconnecting active and passive components, and a resulting thin heterogeneous component: e

20070117370 - Method of forming contact and semiconductor device: A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate. The first stress... Agent: Jianq Chyun Intellectual Property Office

20070117372 - Fabricating method of an interconnect structure: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with... Agent: Jianq Chyun Intellectual Property Office

20070117371 - Integration of pore sealing liner into dual-damascene methods and devices: A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed... Agent: Texas Instruments Incorporated

20070117373 - Thin film magnetic head with a metal lamination part and method of manufacturing the same: A thin film magnetic head with a metal lamination part and method of manufacturing the same are provided. The thin film magnetic head including a metal lamination part in which an upper metal layer is laminated on a lower metal layer. The metal lamination part is formed in the laminated... Agent: Brinks Hofer Gilson & Lione

20070117374 - Method of forming via recess in underlying conductive line: A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about... Agent: Slater & Matsil, L.L.P.

20070117376 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device is disclosed. The method prevents line contact defects and overhangs associated with a barrier metal layer. The method includes forming a PMD layer on a semiconductor substrate including a terminal for the semiconductor device and forming a first contact hole by removing the... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070117375 - Method of forming contact: A method of forming a contact is provided. A substrate having at least two conductive devices is provided. A spacing is located between the two conductive devices. A first dielectric layer is formed over the substrate to cover the two conductive devices and the spacing. A seam is formed in... Agent: Jianq Chyun Intellectual Property Office

20070117377 - Conductor-dielectric structure and method for fabricating: A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the... Agent: Connolly Bove Lodge & Hutz LLP (for IBM Yorktown)

20070117378 - Method of forming a trench for use in manufacturing a semiconductor device: A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench... Agent: Volentine Francos, & Whitt PLLC

20070117379 - Multiple seed layers for interconnects: One embodiment of the present invention is a method for depositing two or more seed layers over a substrate, the substrate includes a patterned insulating layer which comprises at least one opening surrounded by a field, the at least one opening and the field being ready for depositing one or... Agent: Uri Cohen

20070117380 - Resin product, production method for the same, and deposition method for a metallic coating: The present invention provides a metallic coating having a sheen and having a discontinuous structure at high productivity and low cost by using sputtering. A resin product includes a resin base material, and a metallic coating having a sheen and a discontinuous structure that is deposited on the resin base... Agent: Posz Law Group, PLC

20070117381 - Silicon rich barrier layers for integrated circuit devices: Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and... Agent: Dinsmore & Shohl LLP

20070117382 - Method of forming a barrier layer of a semiconductor device: A method of cleaning a surface of a silicon wafer includes subjecting the surface of the silicon wafer to a hydrogen (H2) gas plasma containing at least one inert gas while biasing the hydrogen plasma with a RF bias power to direct the hydrogen (H2) plasma to clean the surface... Agent: Lee & Morse, P.C.

20070117384 - Chemical vapor deposition metallization processes and chemical vapor deposition apparatus used therein: CVD metallization processes and CVD apparatus used therein are provided. The processes include forming a barrier metal layer on a semiconductor substrate and cooling the semiconductor substrate having the barrier metal layer without breaking vacuum. An additional metal layer may be formed on the cooled barrier metal layer. The in-situ... Agent: Marger Johnson & Mccollom, P.C.

20070117383 - Precursor material delivery system with staging volume for atomic layer deposition: A precursor delivery system includes a flow path from a precursor container to a reaction space of a thin film deposition system, such as an atomic layer deposition (ALD) reactor. A staging volume is preferably established between the precursor container and the reaction space for receiving at least one dose... Agent: Stoel Rives LLP

20070117385 - Tantalum amide complexes for depositing tantalum-containing films, and method of making same: Tantalum precursors useful in depositing tantalum nitride or tantalum oxides materials on substrates, by processes such as chemical vapor deposition and atomic layer deposition. The precursors are useful in forming tantalum-based diffusion barrier layers on microelectronic device structures featuring copper metallization and/or ferroelectric thin films.... Agent: Intellectual Property / Technology Law

20070117388 - Fabrication of semiconductor devices: Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked layers having desired electrical characteristics is applied to... Agent: Goodwin Procter LLP Patent Administrator

20070117387 - Semiconductor device and manufacturing method thereof: The semiconductor device fabrication method of the present invention includes forming metal wirings on a semiconductor substrate, forming a first blocking layer on the semiconductor substrate and the metal wiring, forming a first FSG on the first blocking layer, forming a second blocking layer on the first FSG, forming a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070117386 - Substrate for evaluation: The CMP technology is provided of providing a damascene wiring structure having a plural-layer wiring that is excellent in flatness and removability of Cu residue. An evaluation substrate is provided for evaluating a condition of a CMP that is employed for configuring a semiconductor device having a plurality of wirings... Agent: Jordan And Hamburg LLP

20070117392 - Coiled circuit device with active circuitry and methods for making the same: A device includes a coiling layer, a circuit device layer and active microelectronic circuitry fabricated on the circuit device layer. The coiling layer is formed onto a surface of and coupled to the circuit device layer. The coiling layer having intrinsic stresses which cause coiling of the coiling layer and... Agent: Andrews Kurth LLP

20070117390 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming fuse lines over a substrate, forming a first insulation layer over the fuse lines, the first insulation layer including a silicon-rich oxynitride (SRON) layer at the top, forming a second insulation layer over the first insulation layer, the second insulation layer... Agent: Blakely Sokoloff Taylor & Zafman

20070117391 - Method for manufacturing multi-thickness gate dielectric layer of semiconductor device: In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion... Agent: Mills & Onello LLP

20070117389 - Pattern formation method using nanoimprinting and device for carrying out same: An object of the present invention is to provide a pattern forming method that solves the problems associated with thermal nanoimprinting lithography. The present invention discloses a method for forming a pattern in a resist film on a substrate by using a first mold provided with concave and convex portions,... Agent: Morgan Lewis & Bockius LLP

20070117393 - Hardened porous polymer chemical mechanical polishing (cmp) pad: A batch of porous polymer chemical-mechanical polishing (CMP) pads for shipment is described. The CMP pads within the batch are for or use in a semiconductor chip manufacturing process. The CMP pads within the batch exhibit an average dynamic modulus within a range of 65 MPa to 80 MPa inclusive... Agent: Blakely Sokoloff Taylor & Zafman

20070117394 - Polishing slurry for cmp and polishing method: The invention provides polishing slurry for CMP for suppressing corrosion of wiring lines of a conductive substance, or for suppressing bimetallic corrosion of a barrier conductor and conductive substance, by suppressing electrons from being transferred at near the boundaries between a barrier conductor and a conductive substance such as copper.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070117395 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device of the present invention includes: forming a first film, a second film and a third film in sequence on a silicon substrate; patterning a resist film formed on the third film by conducting an exposure and developing process for the resist film employing... Agent: Young & Thompson

20070117398 - Film formation apparatus and method of using the same: A method of using a film formation apparatus for a semiconductor process includes removing by a cleaning gas a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus, and then chemically planarizing the inner surface of the reaction chamber by a planarizing gas.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070117399 - Method to improve profile control and n/p loading in dual doped gate applications: A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing... Agent: Martine Penilla & Gencarella, LLP

20070117397 - Remote plasma pre-clean with low hydrogen pressure: A plasma cleaning method particularly useful for removing photoresist and oxide residue from a porous low-k dielectric with a high carbon content prior to sputter deposition. A remote plasma source produces a plasma primarily of hydrogen radicals. The hydrogen pressure may be kept relatively low, for example, at 30 milliTorr.... Agent: Applied Materials, Inc.

20070117396 - Selective etching of titanium nitride with xenon difluoride: This invention relates to an improved process for the selective etching of TiN from silicon dioxide (quartz) and SiN surfaces commonly found in semiconductor deposition chambers equipment and tools. In the process, an SiO2 or SiN surface having TiN thereon is contacted with XeF2 in a contact zone to selectively... Agent: Air Products And Chemicals, Inc. Patent Department

20070117401 - Carbon nanotube deposition with a stencil: Composition of carbon nanotubes (CNTs) are produced into inks that are dispensable via printing or stencil printing processes. The CNT ink is dispensed into wells formed in a cathode structure through a stencil.... Agent: Fish & Richardson P.C.

20070117403 - Method of fabricating an rf substrate with selected electrical properties: Method for fabricating a textured dielectric substrate (400) for an RF circuit. The method can include the step (104) of selecting a plurality of dielectric substrate materials, each having a distinct combination or set of electrical properties that is different from the combination of electrical properties of every other one... Agent: Sacco & Associates, Pa

20070117405 - Method of manufacturing a semiconductor device: A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC... Agent: Young & Thompson

20070117402 - Methods of forming silicon nano-crystals using plasma ion implantation and semiconductor devices using the same: In a method for forming silicon nano-crystals using plasma ion implantation and a semiconductor memory device using the same, silicon nano-crystals may be formed using plasma ion implantation. An insulating layer may be formed on a substrate, and ions may be implanted into the insulating layer using hydrogen and a... Agent: Harness, Dickey & Pierce, P.L.C

20070117404 - Modification of electrical properties for semiconductor wafers: A semiconductor wafer structure. The structure comprises a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer such that no additional wafers of the plurality of semiconductor wafers... Agent: Schmeiser, Olsen & Watts

20070117400 - Substrate treating apparatus: A substrate processing apparatus capable of readily addressing an increase/decrease in quantity of substrates to be processed and a change in type thereof. The substrate processing apparatus includes a carrier block having a first transfer device performing delivery of the substrate with respect to a substrate carrier on a carrier... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070117406 - Semiconductor element and method for manufacturing the same: A method by which generation of leak current can be suppressed and also a fine element can be formed by performing element isolation at a temperature at which a glass substrate can be used is provided. The method includes a first step of forming a base film over a glass... Agent: Cook, Alex, Mcfarron, Manzo Cummings & Mehler, Ltd.

20070117407 - Method for forming substrates for mos transistor components and its products: The present invention provides a method for forming substrates for MOS (metal oxide semiconductor) transistor, comprising the following steps: (A) In a reduced-pressure environment having a pressure lower than 1×10−6 Torr, a base for accomplishing the surface reconstruction and a solid-state metal oxide source is provided, wherein the solid-state metal... Agent: Bucknam And Archer

20070117409 - Aligner and semiconductor device manufacturing method using the aligner: A circuit pattern having a size finer than a half of a wavelength of an exposure beam is transferred on a semiconductor wafer plane with an excellent accuracy by means of a mask whereupon an integrated circuit pattern is formed and a reduction projection aligner. The accuracy of transferring the... Agent: Apex Juris, PLLC Tracy M Heims

20070117410 - Method for manufacturing semiconductor device using immersion lithography process: Disclosed is a method for manufacturing a semiconductor device using an immersion lithography process comprising pretreating a wafer with water of least about 40° C. after an exposure step and before a post-exposure baking step, thereby effectively reducing water mark defects.... Agent: Marshall, Gerstein & Borun LLP

20070117408 - Method for reducing film stress for sicoh low-k dielectric materials: A method for reducing the tensile stress of a low-k dielectric layer includes depositing an organosilicate layer on a substrate, the layer having an initial tensile stress value associated therewith. The layer is annealed in a reactive environment at a temperature and for a duration selected to result in the... Agent: Cantor Colburn LLP - IBM Fishkill

20070117411 - Rework process for photoresist film: There is disclosed a rework process for a photoresist film over a substrate having at least a first antireflection silicone resin film and the photoresist film over the first silicone resin film comprising: at least removing the photoresist film with a solvent while leaving the first silicone resin film unremoved;... Agent: Oliff & Berridge, PLC

20070117412 - Method for forming a silicon oxide layer using spin-on glass: A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants... Agent: Harness, Dickey & Pierce, P.L.C

20070117413 - Process for the production of a nitrogenous layer a semiconductor or metal surface: A first process for the production of a thin nitrogenous layer on a semiconductor surface by contacting at least a part of the surface with a nitrogenous liquid, by applying an electrical voltage between the surface, the liquid and an electrode according to a given voltage-time curve until a layer... Agent: Dority & Manning, P.A.

20070117414 - Methods and apparatus for epitaxial film formation: In a first aspect, a first system is provided for semiconductor device manufacturing. The first system includes (1) an epitaxial chamber adapted to form a material layer on a surface of a substrate; and (2) a plasma generator coupled to the epitaxial chamber and adapted to introduce plasma to the... Agent: Dugan & Dugan, PC

20070111335 - Ferroelectric memory device: A ferroelectric memory device has a high performance, includes no Pb, and can be directly mounted onto an Si substrate. The ferroelectric memory device includes a (001)-oriented BiFeO3 ferroelectric layer 5 with a tetragonal structure, which is formed on an electrode 4 made of a perovskite material formed on an... Agent: Oliff & Berridge, PLC

20070111332 - Low resistance tunneling magnetoresistive sensor with natural oxidized double mgo barrier: A high performance TMR sensor is fabricated by incorporating a tunnel barrier having a Mg/MgO/Mg configuration. The 4 to 14 Angstroms thick lower Mg layer and 2 to 8 Angstroms thick upper Mg layer are deposited by a DC sputtering method while the MgO layer is formed by a NOX... Agent: George O. Saile

20070111333 - Method for manufacturing a resistively switching memory cell and memory device based thereon: The invention relates to a method for manufacturing at least one phase change memory cell. The method at least fabricating at least one first lamellar spacer of conductive material, which is electrically coupled to the PCM material of the memory cell; fabricating at least one second lamellar spacer on top... Agent: Morrison & Foerster LLP

20070111334 - Semiconductor device and method of manufacturing the same: A semiconductor device according to the present invention comprises a semiconductor substrate, a capacitor including a lower electrode disposed above the semiconductor substrate, a dielectric film disposed above the lower electrode, and an upper electrode disposed above the dielectric film, the upper electrode including metal oxide formed of ABO.sub.3 perovskite... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070111336 - Semiconductor device and method of manufacturing the same: Two ferroelectric capacitors including a PZT film are connected to one MOS transistor. Electrodes of the ferroelectric capacitor are arranged above a main plane of a substrate parallel to the main plane. Therefore, high capacity can be obtained easily. Furthermore, a (001) direction of the PZT film is parallel to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070111337 - Laser decapsulation apparatus and method: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X, Y table 2. A hinged end 4 rotates the device to an acute... Agent: Moore Landrey

20070111338 - Method of controlling trimming of a gate electrode structure: A method and processing tool are provided for controlling trimming of a gate electrode structure containing a gate electrode layer with a first dimension by determining the first dimension of the gate electrode structure, choosing a target trimmed dimension, feeding forward the first dimension and the target trimmed dimension to... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070111339 - Apparatus for processing a substrate: An apparatus includes a plasma process chamber and a support element capable of supporting a substrate inside the plasma process chamber. At least one plasma control element is placed adjacent to a peripheral portion of the support element such that the plasma control element is capable of influencing a plasma... Agent: Slater & Matsil LLP

20070111342 - Chemical mechanical polishing test structures and methods for inspecting the same: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive... Agent: Beyer Weaver & Thomas LLP

20070111341 - Devices and methods for detecting current leakage between deep trench capacitors in dram devices: A test device for detecting current leakage between deep trench capacitors in DRAM devices. The test device is disposed in a scribe line region of a wafer. In the test device, a first trench capacitor pair has a first deep trench capacitor and a second deep trench capacitor connected in... Agent: Quintero Law Office, PC

20070111340 - Method for in-line testing of semiconductor wafers: A test circuit is fabricated in the device layer of the wafer. Metal contact is made between the test circuit and at least one metal layer, e.g., M2. The normal metal line fabrication process, e.g. Damascene process, is performed to fabricate contacts and pattern the trenches of the metal lines.... Agent: Sughrue Mion, PLLC

20070111343 - Capacitive bypass: An indirect connection to and across a photodiode array. The backside contact is used as one portion which connects to a capacitor. The capacitor forms a shunt across the bulk substrate, thus shunting across the series resistance of the substrate, and reducing the series resistance.... Agent: Fish & Richardson, PC

20070111348 - Beam homogenizer, laser irradiation apparatus, and method for manufacturing semiconductor device: The energy distribution of the beam spot on the irradiated surface changes due to the change in the oscillation condition of the laser or before and after the maintenance. The present invention provides an optical system for forming a rectangular beam spot on an irradiated surface including a beam homogenizer... Agent: Eric Robinson

20070111349 - Laser-irradiated thin films having variable thickness: A crystalline film includes a first crystalline region having a first film thickness and a first crystalline grain structure; and a second crystalline region having a second film thickness and a second crystalline grain structure. The first film thickness is greater than the second film thickness and the first and... Agent: Wilmerhale/columbia University

20070111346 - Laser-marking method for a wafer: The present invention relates to a laser-marking method for a wafer. The method of the invention comprises the steps of: (a) providing a wafer, the wafer having a first surface and a second surface, and a glue layer disposed on the first surface; (b) attaching the glue layer under a... Agent: Volentine Francos, & Whitt PLLC

20070111345 - Method for controlling the structure and surface qualities of a thin film and product produced thereby: A system and method for providing improved surface quality following removal of a substrate and template layers from a semiconductor structure provides an improved surface quality for a layer (such as a quantum well heterostructure active region) prior to bonding a heat sink/conductive substrate to the structure. Following the physical... Agent: Jonathan A. Small JasIPConsulting

20070111344 - Method for the production of white leds and white led light source: For the production of a white LED having a predetermined color temperature, a blue LED (2a-2d) or a UV LED is coated with a conversion layer (5) which absorbs the blue light or UV light and emits light of greater wavelength. In accordance with the invention, the exact wavelength of... Agent: Fitzpatrick Cella Harper & Scinto

20070111347 - Surface emitting device, manufacturing method thereof and projection display device using the same: There are provided a surface emitting device and a projection display device, in which high power output can be produced by configuring a large-scaled LED. The surface emitting device includes a plurality of stacked light emitting elements provided on one module. Each of the stacked light emitting elements includes n-type... Agent: Lee, Hong, Degerman, Kang & Schmadeka

20070111350 - Semiconductor nanocrystal probes for biological applications and process for making and using such probes: A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents,... Agent: Bozicevic, Field & Francis LLP

20070111351 - Led and led light source: An LED die (3) is arranged with an adhesive (4) on an LED PCB (6). The LED PCB (6) has on the side opposite to the LED die (3) rear side contacts (7). Through this a self-contained LED lamp is formed, which e.g. can be applied by means of SMT... Agent: Fitzpatrick Cella Harper & Scinto

20070111352 - Wafer with optical control modules in dicing paths: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and two control module fields (A1, A2, B1, B2,... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070111353 - Hybrid microfluidic chip and method for manufacturing same: The invention concerns an electrically active hybrid biochip equipped with a printed circuit wafer provided with a polymer support, whereof one surface at least comprises an electrically conductive layer with several electrodes. On the said electrically conductive layer are applied one or more acrylic polymer or resist layers of epoxy... Agent: Shumaker & Sieffert, P. A.

20070111354 - Nitride-based light emitting device and method of manufacturing the same: Provided are a nitride-based light emitting device and a method of manufacturing the same. The nitride-based light emitting device has a structure in which at least an n-cladding layer, an active layer, and a p-cladding layer are sequentially formed on a substrate. The light emitting device further includes an ohmic... Agent: Buchanan, Ingersoll & Rooney PC

20070111356 - Front lit pin/nip diode having a continuous anode/cathode: A photodetector includes a semiconductor substrate having first and second main surfaces opposite to each other. The photodetector includes at least one trench formed in the first main surface and a first anode/cathode region having a first conductivity formed proximate the first main surface and sidewalls of the at least... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070111361 - Image sensor having self-aligned and overlapped photodiode and method of making same: An image sensing device includes a gate dielectric layer formed on a substrate and a transfer gate formed on the gate dielectric layer. A masking layer is formed on the transfer gate, the masking layer having a width smaller than a width of the transfer gate, such that a portion... Agent: Mills & Onello LLP

20070111357 - Manufacturing method of a non-volatile memory: A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive... Agent: Jianq Chyun Intellectual Property Office

20070111355 - Method and structure of ion implanted elements for the optimization of resistance: A method of forming a piezo-resistive sensor, comprising a piezo-resistor, a leadout resistor, and an insulator structure is provided. A Silicon-On-Insulator (SOI) substrate is provided having an epitaxial layer, a dielectric layer, and a bulk substrate layer. A mask layer is formed on top of the epitaxial layer. The mask... Agent: Honeywell International Inc.

20070111360 - Method for producing micromechanical structures and a micromechanical structure: A method for producing micromechanical structures, in which a functional layer is deposited onto a sacrificial layer, and the sacrificial layer is removed again for the production of at least one mechanical functional element, which is characterized by a surface barrier layer, with which the functional layer begins on the... Agent: Kenyon & Kenyon LLP

20070111358 - Nuclear medicine imaging system and method thereof: A nuclear medicine imaging system is configured so that a semiconductor element and a metallic conductive member are bonded to one another with an electrically conductive adhesive composed of electric conductive particles and a resin binder, and a charge which is generated when radiation is incident on the semiconductor element... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070111359 - Solid-state image pickup device and method for manufacturing the same: Realized are a solid-state image pickup device whose element patterns are miniaturized and a method for manufacturing the solid-state image pickup device, in which furnace-annealing is employed without performing a process of nitriding a gate oxide film and a rapid thermal treatment in main heat treatment processes. The method for... Agent: Mcdermott Will & Emery LLP

20070111362 - Excitation in micromechanical devices: A resonant structure for a micromechanical device includes a crystalline silicon beam and at least one mass attached to the beam. An excitation plane of the resonant structure is defined by the predominant motion of the excited resonant structure. The beam includes crystal axes aligned such that none of the... Agent: Edell, Shapiro & Finnan, LLC

20070111363 - Excitation in micromechanical devices: A resonant structure for a micromechanical device includes a beam and at least one mass attached to the beam. The resonant structure is arranged to have a predominantly rotational excitation mode and an excitation plane in which motion of the excited resonant structure predominantly takes place, the at least one... Agent: Edell, Shapiro & Finnan, LLC

20070111364 - Laser generated stress waves for stiction repair: Methods and apparatus are presented to release stiction between suspended structures and the underlying surface in freestanding MEMS structures. A nanosecond rise time stress wave is launched on the backside of the Si substrate by impinging a 2.5 ns-duration Nd:YAG laser pulse onto a 3 mm-dia area. The compressive stress... Agent: John P. O'banion O'banion & Ritchey LLP

20070111365 - Manufacturing method of microstructure and microelectromechanical system: To reduce the number of photomasks which are used to form sacrificial layers for producing spaces of a microstructure, thereby reducing the manufacturing cost. Sacrificial layers are formed by using resist masks which are patterned with the same photomask. Specifically, after forming a first sacrificial layer by etching using a... Agent: Fish & Richardson P.C.

20070111366 - Mesoscale pyramids, arrays and methods of preparation: Ordered, two-dimensional arrays of pyramidal particulates and related methods of preparation.... Agent: Reinhart Boerner Van Deuren S.c. Attn: Linda Kasulke, Docket Coordinator

20070111367 - Method and apparatus for converting precursor layers into photovoltaic absorbers: The present invention relates to method and apparatus for preparing thin films of semiconductor films for radiation detector and photovoltaic applications. In one aspect, the present invention includes a series of chambers between the inlet and the outlet, with each chamber having a gap that allows a substrate to pass... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070111370 - Film formation method and manufacturing equipment for forming semiconductor layer: The present invention provides a film forming method of a uniform semiconductor layer having a large area at a low cost and equipment to form said semiconductor layer, by blowing gas against a coated layer to shorten the drying time and to decrease uneven drying. A film forming method of... Agent: Brinks Hofer Gilson & Lione

20070111369 - Organic light emitting display device and method of manufacturing the same: A method of manufacturing an organic light emitting display device and the organic light emitting display device which reduces generation of dark spots by particles are disclosed. The method of manufacturing an organic light emitting display device includes: preparing for a substrate including a pixel circuit; forming a pixel electrode... Agent: Knobbe Martens Olson & Bear LLP

20070111371 - Organic thin film transistor and method of fabricating the same: An organic thin film transistor (OTFT) and a method of fabricating the same are provided in which an organic layer and metal interconnections are formed to have certain linewidths and shapes such that a degradation of device characteristics is prevented. The method includes providing a substrate, forming a gate electrode... Agent: Christie, Parker & Hale, LLP

20070111368 - Photovoltaic structure with a conductive nanowire array electrode: A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070111372 - Methods of forming a p-type group ii-vi semiconductor crystal layer on a substrate: A disclosed method deposits a p-type magnesium-, cadmium- and/or zinc-oxide-based II-VI Group compound semiconductor crystal layer on a zinc oxide (ZnO) substrate having a (002) crystallographic orientation. The method uses a zinc-containing reaction gas supplied to a surface of a heated substrate. The p-type magnesium-, cadmium- and/or zinc-oxide-based II-VI Group... Agent: Alston & Bird LLP

20070111373 - Process for producing semiconductor integrated circuit device: Recently, with shortened wavelengths employed in aligners, it is now difficult to use a material containing a benzene ring as a photoresist material. Since resist has extremely low plasma resistance, formation of deep holes using a photoresist as a dry etching mask is difficult. Under such circumstances, in the present... Agent: Mcginn Intellectual Property Law Group, PLLC

20070111383 - Carbon-carbon and/or metal-carbon fiber composite heat spreader: A heat spreader, comprised of a plurality of carbon fibers oriented in a plurality of directions, with a carbon or metal matrix material dispersed about the fibers, is described. The carbon fibers facilitate the spreading of heat away from the smaller semiconductor device and up to a larger heat removal... Agent: Intel/blakely

20070111377 - Connector and method for making the same: A connector includes a terminal which includes a base with an arm extending inclinedly therefrom and a first contact portion protrudes from a top of a front end of the arm, The front end extends inclinedly from the first contact portion and has a sharp tip. A plastic frame has... Agent: Lin & Associates Intellectual Property

20070111375 - Enhancing shock resistance in semiconductor packages: A shock load applied to a solder ball may be cushioned by providing a viscoelastic material in association with the solder ball. The viscoelastic material dampens shock loads applied to the solder ball and reduces the rate of failure between the solder ball and the rest of the package.... Agent: Trop Pruner & Hu, PC

20070111380 - Fabricating method of printed circuit board having embedded component: A method of fabricating a printed circuit board having embedded components is disclosed. The method of fabricating a printed circuit board having embedded components according to an embodiment of the present invention comprises stacking a first conductive layer and a second conductive layer on a substrate in order, forming a... Agent: Staas & Halsey LLP

20070111376 - Integrated circuit package system: An integrated circuit package system is provided forming a first I/O cell having a first circuitry area and a first bond pad with the first circuitry area partitioned along a cell length and on opposing perimeter segment of the first bond pad, forming an I/O ring having the first I/O... Agent: Ishimaru & Zahrt LLP

20070111382 - Method for fabricating conductive bumps with non-conductive juxtaposed sidewalls: A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070111385 - Method of manufacture of silicon based package and devices manufactured thereby: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface... Agent: John A. Jordan, Esq.

20070111384 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070111378 - Method of protecting semiconductor chips from mechanical and esd damage during handling: A method and apparatus are provided for protecting a semiconductor device from damage. The method includes the steps of providing a active semiconductor device on a surface of the semiconductor substrate where the active device is surrounded by inactive semiconductor areas and providing a soft metallic guard ring only in... Agent: Casey Toohey

20070111379 - Pre-molded leadframe and method therefor: A method of manufacturing a pre-molded leadframe for use in a semiconductor package includes providing a leadframe having a die pad and a plurality of leads. A first molding material is formed in the leadframe to expose the upper surface of the die pad and the upper surfaces of the... Agent: Ishimaru & Zahrt LLP

20070111374 - Reversible leadless package and methods of making and using same: A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070111381 - Solder ball excellent in micro-adhesion preventing properties and wetting properties and method for preventing the micro-adhesion of solder balls: The present invention provides a solder ball that has solved the problem of micro-adhesion and, moreover, has solved both of the problems of micro-adhesion and wetting properties, and a method for preventing the micro-adhesion of solder balls. That is, the present invention provides a solder ball obtained by solidification and... Agent: Sughrue Mion, PLLC

20070111386 - Process of vertically stacking multiple wafers supporting different active integrated circuit (ic) devices: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and... Agent: Intel/blakely

20070111387 - Manufacturing method of wiring board and manufacturing method of semiconductor device: A method of manufacturing a wiring board, for mounting a semiconductor chip thereon, including coupling portions to be coupled to the semiconductor chip and a pattern wiring to be coupled to the semiconductor chip via the coupling portions, including: a feeding layer forming step of forming, on the pattern wiring,... Agent: Drinker Biddle & Reath (dc)

20070111388 - Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (bga) package: A semiconductor multi-package module has stacked first and second packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid... Agent: Haynes Beffel & Wolfeld LLP

20070111389 - Micro chip-scale-package system: A micro chip-scale-package system including providing a metal pattern on an adhesion material, attaching an integrated circuit die to the metal pattern, and molding an encapsulant over the integrated circuit die and the metal pattern.... Agent: Ishimaru & Zahrt LLP

20070111390 - Semiconductor device and method for processing wafer: A device separated from a wafer includes: a chip having a sidewall, which is provided by a dicing surface of the wafer in a case where the device is separated from the wafer; and a protection member disposed on the sidewall of the chip for protecting the chip from being... Agent: Posz Law Group, PLC

20070111391 - Layer having functionality, method for forming flexible substrate having the same, and method for manufacturing semiconductor device: It is an object of the present invention to provide a method for forming a layer having functionality including a conductive layer and a colored layer and a flexible substrate having a layer having functionality with a high yield. Further, it is an object of the present invention to provide... Agent: Eric Robinson

20070111392 - Method for thermally releasing chip cut piece from thermal release type pressure sensitive adhesive sheet, electronic component and circuit board: A method of overheating and releasing a chip cut piece from a thermal release type pressure sensitive adhesive sheet is a method by which a chip cut piece stuck onto a thermal release type pressure sensitive adhesive sheet having a base material, and a thermally expandable microsphere-containing thermally expandable pressure... Agent: Sughrue-265550

20070111396 - Electro-optical device, manufacturing method of the same, and electronic apparatus: To provide an electro-optical device having a buffer layer which planarizes a gas barrier layer so that stress-concentration in the gas barrier layer is reduced, the buffer layer being prevented from leaking out of a predetermined area, and to provide a method of producing the same and an electronic apparatus.... Agent: Oliff & Berridge, PLC

20070111394 - Integrated circuit package system: An integrated circuit package system comprised by providing a leadframe including leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to... Agent: Ishimaru & Zahrt LLP

20070111395 - Lead frame structure and semiconductor package integrated with the lead frame structure: A lead frame structure is provided, which includes a die pad having a first mounting portion and a second mounting portion separated from the first mounting portion by a gap. The first and second mounting portions are formed with corresponding blocking surfaces bordering the gap, so as to allow a... Agent: Birch Stewart Kolasch & Birch

20070111393 - Method of forming a leaded molded array package: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070111397 - Integrated circuit package system with heat sink: An integrated circuit package system includes providing a substrate. An integrated circuit is attached to the substrate. A plurality of support bars is formed on the substrate. A plurality of adhesive structures is formed. A heat sink is attached to the plurality of adhesive structures. The integrated circuit is encapsulated.... Agent: Ishimaru & Zahrt LLP

20070111398 - Micro-electronic package structure and method for fabricating the same: A micro-electronic package structure and a method for fabricating the same are proposed. A carrier is prepared and provided with a cavity for receiving at least one semiconductor chip having a plurality of electrical connection contacts. A dielectric layer is formed on the carrier, with the electrical connection contacts being... Agent: Clark & Brody

20070111400 - Dispensing device and mounting system: A dispensing device (4) for charging underfill agent into a gap between a substrate (K) and a chip (C) includes means for storing underfill agent (66, 67), a chamber (52) provided for containing substrate (K) to be charged with underfill agent and capable of being opened/closed, a dispenser (73) provided... Agent: Smith Patent Office

20070111399 - Method of fabricating an exposed die package: A method of fabricating an exposed die package. A feature on at least one side of the die is formed. The die is placed on a substrate and encapsulated. Then, the die is removed from the substrate to reveal an exposed die surface.... Agent: Iandiorio & Teska

20070111401 - Printed wiring board, its manufacturing method, and circuit device: A printed wiring board manufacturing process comprises forming a conductive metal layer on at least one surface of an insulating film with a sputtered metal layer in between, selectively etching the conductive metal layer and the sputtered metal layer to produce a wiring pattern, treating the laminated film with a... Agent: The Webb Law Firm, P.C.

20070111402 - Production and packaging control for repaired integrated circuits: A method for reducing the scrap rate of fuse structures after laser repairing is provided. The method includes providing a semiconductor wafer comprising integrated circuits, performing a yield test on the semiconductor wafer to determine defective circuits, predetermining a wavelength limit, and keeping the semiconductor wafer away from lights having... Agent: Slater & Matsil, L.L.P.

20070111403 - Polycide fuse with reduced programming time: In one embodiment, a polycide fuse is provided that includes: a polysilicon layer; a silicide layer formed on the polysilicon layer; and a silicon nitride layer formed on the silicide layer by RTCVD, the silicon nitride layer having a relatively low hydrogen concentration and relatively low mechanical stress.... Agent: Macpherson Kwok Chen & Heid LLP

20070111405 - Design method for semiconductor integrated circuit: In a standard cell in which an active area and a gate conductor are provided, the active area has a largest length in a gate width direction at an end thereof in a gate length direction.... Agent: Mcdermott Will & Emery LLP

20070111406 - Fet channel having a strained lattice structure along multiple surfaces: A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and... Agent: Ibm Corp,IPLaw

20070111404 - Method of manufacturing strained-silicon semiconductor device: A method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in epitaxial film thickness. The layout or component configuration for the proposed semiconductor device is evaluated to determine areas of relatively light or dense population in order to determine whether local-loading-effect defects are likely to occur. If a... Agent: Slater & Matsil, L.L.P.

20070111407 - Storage capacitor in oled pixels and driving circuits and method for forming the same: An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070111408 - Manufacturing method for field-effect transistor: To provide a manufacturing method for a field-effect transistor, such as a thin-film transistor, enabling reductions in the number patterning steps and the number of photomasks and improvements in the throughput and the yield. In the method, an oxide film is formed by processing the surface of a crystalline semiconductor... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070111409 - Semiconductor device: In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070111410 - High mobility plane finfets with equal drive strength: An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070111412 - Thin film transistor array panel and method of manufacturing the same: In one embodiment, a thin film transistor array display panel and method of manufacturing the same are provided. A method includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact layer on the gate line; forming a data layer on... Agent: Macpherson Kwok Chen & Heid LLP

20070111411 - Thin film transistor substrate and manufacturing method for the same: A thin film transistor substrate is provided whose structure allows for the formation of (i) a thick gate insulating film, (ii) a high pressure resistance TFT having a LDD region of a GOLD structure, and (iii) a low voltage TFT having a thin gate insulating film, with less number of... Agent: Sharp Kabushiki Kaisha C/o Keating & Bennett, LLP

20070111413 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device comprises forming a first recess in a semiconductor substrate having a device isolation structure defining an active region, forming a nitride film over an entire surface of the resultant including the first recess, etching the nitride film at the bottom of the first... Agent: Townsend And Townsend And Crew, LLP

20070111414 - A vertical replacement-gate silicon-on-insulator transistor: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises... Agent: Hitt Gaines, PC Agere Systems Inc.

20070111419 - Cmos devices with a single work function gate electrode and method of fabrication: Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed... Agent: Intel/blakely

20070111415 - High-voltage metal-oxide-semiconductor device and method of manufacturing the same: The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassing the first and second field layers with... Agent: North America Intellectual Property Corporation

20070111416 - Method of fabricating strained-silicon transistors: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the... Agent: North America Intellectual Property Corporation

20070111418 - Method of manufacturing pixel structure: A method of manufacturing a pixel structure controlled by a data line and a scan line is provided. A gate electrode electrically coupled to the scan line is formed on a substrate and a first dielectric layer covering the scan line and the gate electrode is formed. A first and... Agent: Jianq Chyun Intellectual Property Office

20070111417 - Strained-silicon cmos device and method: The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial... Agent: Scully, Scott, Murphy & Presser, P.C.

20070111420 - Cmos and mos device: A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first active region and a second active region. The first... Agent: Jianq Chyun Intellectual Property Office

20070111421 - Structure and method to generate local mechanical gate stress for mosfet channel mobility modification: A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack... Agent: Scully, Scott, Murphy & Presser, P.C.

20070111422 - Self aligned non-volatile memory cells and processes for fabrication: A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. A first process forms floating gates by... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070111423 - Method of fabricating semiconductor device: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070111425 - Composite gate structure in an integrated circuit: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal... Agent: Slater & Matsil, L.L.P.

20070111424 - Semiconductor device and manufacturing method thereof: There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are... Agent: Fish & Richardson P.C.

20070111426 - Layout design method and layout design tool: Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type,... Agent: Foley And Lardner LLP Suite 500

20070111427 - Semiconductor device and method of manufacturing the same: The semiconductor device which can apply the stress application technology to a channel part by a liner film to MISFET including a full silicidation gate electrode, and its manufacturing method are realized. The first liner silicon nitride film is formed on the semiconductor substrate MISFET formed. Insulating films, such as... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070111428 - Bandgap engineered mono-crystalline silicon cap layers for sige hbt performance enhancement: A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; forming a cap layer overlying the compound base region including doping the cap layer with a pre-determined percentage of at... Agent: Sawyer Law Group LLP

20070111429 - Method of manufacturing a pipe shaped phase change memory: A manufacturing method for a pipe-shaped memory cell device includes forming a bottom electrode having a top surface; forming a fill layer over the electrode, with a via having sides, extending from a top surface of the fill layer to the top surface of the bottom electrode; forming a conformal... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070111430 - High density mimcap with a unit repeatable structure: A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second... Agent: Greenblum & Bernstein, P.L.C

20070111434 - Method for manufacturing capacitor: A method for manufacturing a capacitor includes depositing an interlayer insulating film on or above a plug connected to a switching element, forming a hole in the interlayer insulating film such that the opening portion of the hole is surrounded by an overhang structure and that the plug is exposed... Agent: Mcginn Intellectual Property Law Group, PLLC

20070111436 - Method of manufacturing sidewall spacers on a memory device, and device comprising same: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit... Agent: Williams, Morgan & Amerson

20070111433 - Methods for manufacturing semiconductor devices: A method for manufacturing a semiconductor device comprises forming a first silicon layer above a semiconductor substrate; forming a stopper layer on said first silicon layer; partially removing said stopper layer and said first silicon layer above said semiconductor substrate to form a plurality of trenches; forming an insulating layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070111431 - Mim capacitor and associated production method: An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which... Agent: Brinks Hofer Gilson & Lione

20070111435 - Schottky barrier finfet device and fabrication method thereof: A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is... Agent: Mills & Onello LLP

20070111438 - Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (mis) capacitor: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070111432 - Semiconductor device having capacitor and method of fabricating the same: A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a... Agent: Harness, Dickey & Pierce, P.L.C

20070111437 - Semiconductor device including storage node and method of manufacturing the same: A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch... Agent: Marger Johnson & Mccollom, P.C.

20070111439 - Fin field effect transistors including epitaxial fins: A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a... Agent: Myers Bigel Sibley & Sajovec

20070111445 - Flash memories and methods of fabricating the same: The present disclosure relates to a flash memory including a common source line having a predetermined width formed on a semiconductor substrate, a common source in the semiconductor substrate below the common source line, and a couple of floating gates having a predetermined width formed on both outer side walls... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070111443 - Memory transistor and methods: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a... Agent: Wells St. John P.s.

20070111442 - Method of making a multi-bit nanocrystal memory: A manufacturing method for an improved memory cell having a pair of non-volatile memory transistors with each transistor using a nanocrystal gate structure, the transistor pair constructed between a pair of bit line polysilicon depositions. Between the pair of non-volatile memory transistors, a word line device is interposed, allowing serial... Agent: Schneck & Schneck

20070111444 - Method of manufacturing split gate type nonvolatile memory device: A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.... Agent: Volentine & Whitt, PLLC One Freedom Square

20070111441 - Nonvolatile memory device and method of manufacturing the same: Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken... Agent: Harness, Dickey & Pierce, P.L.C

20070111440 - Phase changeable memory cell array region and method of forming the same: A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating... Agent: Volentine Francos, & Whitt PLLC

20070111446 - Low temperature process and structures for polycide power mosfet with ultra-shallow source: A trench type power semiconductor device includes proud gate electrodes that extend out of the trenches and above the surface of the semiconductor body. These proud gate electrodes allow for making ultra-shallow source regions within the semiconductor body using, for example, a low temperature source drive. In addition, a method... Agent: Ostrolenk Faber Gerb & Soffen

20070111447 - Process for manufacturing a floating gate non-volatile memory cell, and memory cell thus obtained: A process for manufacturing a non-volatile memory cell including a floating gate MOS transistor, including the steps of: forming a gate dielectric over a surface of a semiconductor material layer; forming a conductive floating gate electrode insulated from the semiconductor material layer by the gate dielectric; forming at least one... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070111449 - Non-volatile memory cell and method for manufacturing the same: The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a stacked gate structure over a substrate, wherein the stacked gate structure is composed of, from the bottom to the top of the stacked gate structure, a first dielectric layer, a charge... Agent: J.c. Patents, Inc.

20070111450 - Semiconductor device fabrication method and electronic device fabrication method: The present invention provides a semiconductor device fabrication method capable of reducing the thermal load on the substrate. The present invention also provides a semiconductor device fabrication method capable of improving the characteristics of a semiconductor element. The semiconductor device fabrication method according to the present invention comprises a step... Agent: Oliff & Berridge, PLC

20070111448 - Semiconductor devices and methods of manufacture thereof: Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the... Agent: Slater & Matsil LLP

20070111451 - Flash memory device and method of manufacturing the same: A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating... Agent: F. Chau & Associates, LLC

20070111452 - fabricating method of cmos and mos device: A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first and a second active region. The first active region... Agent: Jianq Chyun Intellectual Property Office

20070111454 - Gate electrode for a semiconductor fin device: A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method... Agent: Mark J. Marcelli Duane Morris LLP

20070111453 - Semiconductor device with dual gates and method of manufacturing the same: In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer... Agent: Mills & Onello LLP

20070111455 - Fabrication of local damascene finfets using contact type nitride damascene mask: Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined... Agent: Harness, Dickey & Pierce, P.L.C

20070111456 - Power semiconductor device and method of fabricating the same: A power semiconductor device may include a substrate having a first conductivity type. A drift region having a first conductivity type may be formed on an upper surface of the substrate. A body region having a second conductivity type may be formed on a surface of the drift region. A... Agent: Harness, Dickey & Pierce, P.L.C

20070111457 - Method of fabricating a lateral double-diffused mosfet (ldmos) transistor and a conventional cmos transistor: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor.... Agent: Fish & Richardson P.C.

20070111458 - Methods and apparatus for incorporating nitrogen in oxide films: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned... Agent: Dugan & Dugan, PC

20070111459 - Manufacturing method for semiconductor device: A semiconductor device manufacturing method including forming a conductive layer and a silicon film on a semiconductor substrate including an active region, forming an emitter electrode containing a first impurity on the silicon film above the active region, partially etching the silicon film using the emitter electrode as a mask,... Agent: Mcdermott Will & Emery LLP

20070111460 - Capacitor with carbon nanotubes: In one embodiment, a capacitor comprises a substrate defining a first electrical terminal; a catalyst layer disposed on the substrate; a plurality of carbon nanotubes disposed on the catalyst layer; a dielectric layer disposed over the plurality of carbon nanotubes; and a conductive layer disposed on the dielectric layer and... Agent: Schwabe, Williamson & Wyatt, P.C.

20070111461 - Systems and methods for forming integrated circuit components having matching geometries: In a particular embodiment, a method of forming integrated circuit components is provided. A first photomask is formed, the first photomask including a first mask component having a first geometry corresponding to a first type of integrated circuit component. A first lithography process is performed to transfer the first geometry... Agent: Baker Botts L.L.P. Patent Department

20070111462 - Method of manufacturing a capacitor and method of manufacturing a semiconductor device using the same: Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the same. Other example embodiments relate to a method of manufacturing a capacitor having improved characteristics and a method of manufacturing a semiconductor device using the same. In a method of... Agent: Harness, Dickey & Pierce, P.L.C

20070111464 - Optical isolator device, and method of making same: The present invention is generally directed to an optical isolator device, and various methods of making same. In one illustrative embodiment, the method comprises obtaining a single SOI substrate, the SOI substrate having an active layer comprised of silicon and a buried insulation layer, forming a doped layer of silicon... Agent: Williams, Morgan & Amerson

20070111463 - Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting... Agent: Scully, Scott, Murphy & Presser, P.C.

20070111465 - Mask, mask blank, and methods of producing these: A mask decreased in warping and having a high positioning precision, provided with at least a substrate aperture formed at a portion of a silicon substrate, a first silicon oxide film formed at one surface of the silicon substrate, a single crystal silicon layer formed on the first silicon layer... Agent: Sonnenschein Nath & Rosenthal LLP

20070111468 - Method for fabricating dislocation-free stressed thin films: A method of forming a stressed thin film on a substrate includes the steps of depositing a thin film of silicon on a first substrate and transforming the first substrate into a porous substrate. The porous substrate containing the thin film of silicon is then transformed into a stressed state... Agent: VistaIPLaw Group LLP

20070111469 - Method for fabricating semiconductor device with bulb-shaped recess gate: A method for fabricating a semiconductor device includes: forming a pad oxide layer over a substrate; forming a hard mask pattern over the pad oxide layer; etching a predetermined portion of the pad oxide layer and the substrate using the hard mask pattern to form a first recess having sidewalls... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070111467 - Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same: Provided are a method for forming a trench using a hard mask with high selectivity and an isolation method for a semiconductor device using the same. The method includes: forming a first hard mask over a substrate, the first hard mask including an oxide layer and a nitride layer; forming... Agent: Blakely Sokoloff Taylor & Zafman

20070111466 - Reducing damage to ulk dielectric during cross-linked polymer removal: Methods are disclosed for reducing damage to an ultra-low dielectric constant (ULK) dielectric during removal of a planarizing layer such as a crosslinked polymer. The methods at least partially fill an opening with an at most lightly crosslinked polymer, followed by the planarizing layer. When the at most lightly crosslinked... Agent: Hoffman, Warnick & D'alessandro LLC

20070111470 - Trench insulation structures and methods: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited... Agent: Knobbe Martens Olson & Bear LLP

20070111471 - Bonding method, device produced by this method, and bonding device: Conventional heat bonding and anodic bonding require heating at high temperature and for a long time, leading to poor production efficiency and occurrence of a warp due to a difference in thermal expansion, resulting in a defective device. Such a problem is solved. An upper wafer 7 made of glass... Agent: Jagtiani + Guttag

20070111472 - Method of performing a double-sided process: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the... Agent: North America Intellectual Property Corporation

20070111473 - Process for preparing a bonding type semiconductor substrate: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1-yAly)1-xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.50, 0≦y≦1), an active layer 15, a p-type cladding layer 16 and a cover layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070111475 - Method for the structured application of a laminatable film to a substrate for a semiconductor module: A method for structured application of a laminatable intermediate layer (9) to a substrate (1) for a semiconductor module, wherein a separating layer is indirectly or directly applied to said substrate (1) over a large surface, the intermediate layer (9) is applied to the substrate (1), including the separating layer(s),... Agent: Baker Botts L.L.P. Patent Department

20070111474 - Treating a sige layer for selective etching: The invention relates to a method of lifting a layer of silicon-germanium of formula Si1-xGex (0≦x≦1) disposed on a layer of strained silicon. The layer of silicon-germanium is intended to be lifted by selective chemical etching to expose the strained silicon layer. Prior to selective etching step, the method includes... Agent: Winston & Strawn LLP Patent Department

20070111477 - Semiconductor wafer: A semiconductor wafer is disclosed for which irradiation of a laser beam forms a modified region due to multiphoton absorption to thereby facilitate dicing of the semiconductor wafer. The semiconductor wafer includes a formation member and a scribe groove located on the formation member according to an irradiation position of... Agent: Posz Law Group, PLC

20070111476 - Separating device for separating semiconductor substrate and method for separating the same: A separating device for separating a semiconductor substrate includes: a cutting element for cutting the semiconductor substrate into a plurality of chips along with a cutting line on the semiconductor substrate; an adsorbing element for adsorbing a dust on a surface of the semiconductor substrate by using electrostatic force; and... Agent: Posz Law Group, PLC

20070111479 - High-power-laser chip-fabrication apparatus and method thereof: The present invention discloses a high-power-laser chip-fabrication apparatus and a method thereof, wherein a substrate is fixed on a working table; a light-guide device is used to direct a high power laser to a scribed line on the substrate; a control device is used to position the working table and... Agent: Rosenberg, Klein & Lee

20070111478 - Semiconductor device and dicing method for semiconductor substrate: A method for dicing a semiconductor substrate includes: forming a reforming layer in the substrate by irradiating a laser beam on the substrate; forming a groove on the substrate along with a cutting line; and applying a force to the substrate in order to cutting the substrate at the reforming... Agent: Posz Law Group, PLC

20070111481 - Wafer and wafer cutting and dividing method: A laser beam is applied to an interior of a wafer through a top surface to form modified areas in a plurality of layers of modified area groups. Intervals of the modified areas in one of the layers of modified area groups differ from intervals of the modified areas in... Agent: Posz Law Group, PLC

20070111480 - Wafer product and processing method therefor: A semiconductor wafer has two faces, one of which is a laser light incident face. A dicing sheet is attached to the other face of the wafer, so that it is stretched to thereby apply tensile stress to a laser-reformed region and cause cutting with the reformed region taken as... Agent: Posz Law Group, PLC

20070111483 - Bonding method of semiconductor substrate and sheet, and manufacturing method of semiconductor chips using the same: A semiconductor substrate is bonded to a joining face of a sheet and is dividable along predetermined dividing lines of the semiconductor substrate by expanding the sheet so as to form semiconductor chips. A bonding layer for bonding a substrate face of the semiconductor substrate and the joining face of... Agent: Posz Law Group, PLC

20070111484 - Dicing sheet frame: A dicing sheet frame, which is used when a semiconductor wafer adhered to a dicing sheet is cut into chips, includes a plurality of frame parts and a connecting device. The plurality of frame parts supports the dicing sheet. The connecting device connects the plurality of frame parts such that... Agent: Posz Law Group, PLC

20070111482 - Method for dicing glass substrate: A method for dicing a sheet workpiece includes the following steps. A base (10) is provided. A water-soluble adhesive (20) is coated onto the base, and the workpiece is placed on the water-soluble adhesive. The water-soluble adhesive is hardened so as to, fix the workpiece on the base. The workpiece... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070111488 - Fabrication of nonpolar indium gallium nitride thin films, heterostructures and devices by metalorganic chemical vapor deposition: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.... Agent: Gates & Cooper LLP Howard Hughes Center

20070111487 - Highly integrated semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes sequentially forming a first pattern and a second pattern on a substrate, the second pattern being a non-single-crystalline semiconductor stacked on the first pattern, wherein a portion of the substrate is exposed adjacent to the first and second patterns, forming a non-single-crystalline... Agent: Lee & Morse, P.C.

20070111486 - Metal-free silicon-molecule-nanotube testbed and memory device: Work from several laboratories has shown that metal nanofilaments cause problems in some molecular electronics testbeds. A new testbed for exploring the electrical properties of single molecules has been developed to eliminate the possibility of metal nanofilament formation and to ensure that molecular effects are measured. This metal-free system uses... Agent: Hugh R. Kress Browning Bushman P.C.

20070111485 - Method to reduce seedlayer topography in bicmos process: A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack (14, 16) above the field isolation oxide region (12), wherein... Agent: Philips Intellectual Property & Standards

20070111489 - Methods of producing a semiconductor body and of producing a semiconductor device: A source melt is formed by melting a source material comprising a semiconductor material. A portion of the source melt is directionally recrystallized to form an intermediate crystal and a residue portion that includes impurities. The residue portion is disposed of. Subsequently, at least a portion of the intermediate crystal... Agent: Mcglew & Tuttle, PC

20070111490 - Mask blank, mask blank manufacturing method, transfer mask manufacturing method, and semiconductor device manufacturing method: In the photomask blank 100, which is an original plate of a transfer mask having a transfer pattern to be transferred to the body to be subjected to transfer on the substrate 10, the photomask blank 100 includes a light shielding film 20 becoming the transfer pattern and a resist... Agent: Oliff & Berridge, PLC

20070111491 - Process for electroplating metal layer without plating lines after the solder mask process: A process for electroplating a metal layer without the plating lines after the solder masking process is provided, which is characterized in that a ball pad which is on one side of the carrier board is connected to a anchor clamp of an electroplating device via a temporary conductor layer... Agent: Lin & Associates Intellectual Property

20070111492 - Structured, electrically-formed floating gate for flash memories: Semiconductor memory devices and methods to fabricate thereof are described. A first gate base is formed on a first insulating layer on a substrate. A first gate fin is formed on the first gate base. The first gate fin has a top and sidewalls. Next, a second insulating layer is... Agent: Blakely Sokoloff Taylor & Zafman

20070111495 - Contact hole structure of semiconductor device and method of forming the same: A method of forming a contact hole of a semiconductor device, the method comprising: forming a gate line and a source/drain region in a substrate; depositing an etch stopper layer on the substrate; depositing a first interlayer dielectric layer on the etch stopper layer and flattening the first interlayer dielectric... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070111494 - Handling of flexible planar material: A method of handling a length of flexible planar material, comprises conveying the material (1) past a first contacting point (2), and applying a flow of fluid (6) to the material thereby applying a drag force on the material which induces a tensile force in the material with respect to... Agent: Morgan Lewis & Bockius LLP

20070111493 - Nanowires comprising metal nanodots and method for producing the same: Nanowires methods for producing the nanowires are provided. The nanowires include a plurality of metal nanodots uniformly disposed therein, and a core portion, wherein each of the plurality of metal nanodots is coupled to the core portion. According to the method, metal nanodots can be uniformly disposed in the nanowires,... Agent: Cantor Colburn, LLP

20070111496 - Semiconductor device having dual stacked mim capacitor and method of fabricating the same: Semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same are disclosed. The semiconductor device includes a dual stacked MIM capacitor formed on the semiconductor substrate. The dual stacked MIM capacitor includes a lower plate positioned, an upper plate electrically connected to the lower plate and... Agent: Volentine Francos, & Whitt PLLC

20070111497 - Process for forming a redundant structure: Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in... Agent: Greenblum & Bernstein, P.L.C

20070111498 - Method of fabricating n-type semiconductor diamond, and semiconductor diamond: An n-type diamond epitaxial layer 20 is formed by processing a single-crystalline {100} diamond substrate 10 so as to form a {111} plane, and subsequently by causing diamond to epitaxially grow while n-doping the diamond {111} plane. Further, a combination of the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped... Agent: Mcdermott Will & Emery LLP

20070111500 - Method and apparatus for attaching solder balls to substrate: A method for attaching solder balls to solder pads on a circuit board, comprising distributing an approximately uniform flat layer of solder paste with distributed solder particles on top of a flat plate employing a squeegee, picking up the solder balls from a solder ball bin utilizing a vacuum tool,... Agent: Texas Instruments Incorporated

20070111501 - Processing method for semiconductor structure: A processing method for a semiconductor structure is described. First, a substrate is provided. The substrate has a pad region and a fuse region. The substrate has a bond pad already formed in the pad region and a fuse structure already formed in the fuse region. Then, a first testing... Agent: Jianq Chyun Intellectual Property Office

20070111499 - Wafer redistribution structure with metallic pillar and method for fabricating the same: A wafer structure and a method for fabricating the same are provided. The wafer structure comprises a substrate, a redistribution structure, a passivation layer, an under bump metallurgy (UBM) layer and a bump. The substrate has a solder pad. The redistribution structure is formed on the substrate and comprises a... Agent: Birch Stewart Kolasch & Birch

20070111502 - Damascene patterning of barrier layer metal for c4 solder bumps: A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A... Agent: Scully, Scott, Murphy & Presser, P.C.

20070111506 - Integrated circuit devices including metal-insulator-metal capacitors and methods of fabricating the same: Integrated circuit devices including metal-insulator-metal (MIM) capacitors are provided. The MIM capacitors may include an upper electrode having first and second layers. The first layer of the upper electrode includes a physical vapor deposition (PVD) upper electrode and the second layer of the upper electrode includes an ionized PVD (IPVD)... Agent: Myers Bigel Sibley & Sajovec

20070111505 - Method of manufacturing a semiconductor device: A semiconductor device manufacturing method forming an interconnection structure by a dual damascene process is disclosed that includes the steps of forming first and second interlayer insulating films successively over an interconnection layer, at least one of which includes a low dielectric constant material; forming a via hole through the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070111503 - Self-aligning nanowires and methods thereof: A self-aligning nanowire includes a nanowire portion and an aligning member attached to the nanowire portion. The aligning member interacts with another aligning member on an adjacent self-aligning nanowire to align the nanowires together. A method of aligning nanowires includes providing a plurality of the self-aligning nanowires, suspending the plurality... Agent: Hewlett Packard Company

20070111504 - Semiconductor device and manufacturing method thereof: A semiconductor device includes: a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed; a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070111507 - Active matrix substrate, manufacturing method thereof, electro-optical device, and electronic apparatus: A method for manufacturing an active matrix substrate, comprises forming a first conductive layer across a first wiring line forming area and a second wiring line forming area on a substrate including a first wiring line and a second wiring line having a width narrower than a width of the... Agent: Harness, Dickey & Pierce, P.L.C

20070111510 - Dual damascene multi-level metallization: An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side... Agent: Schmeiser, Olsen & Watts

20070111511 - Fabrication method of a semiconductor device: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulating film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to... Agent: Fish & Richardson P.C.

20070111509 - Polycarbosilane buried etch stops in interconnect structures: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3,... Agent: Scully, Scott, Murphy & Presser, P.C.

20070111508 - Process for producing semiconductor integrated circuit device: An object of the present invention is to prevent formation of a badly situated via metal in a Damascene wiring portion in multiple layers having an air-gap structure. In the present invention, a via is completely separated from an air-gap 45 by forming an interlayer insulating film 44 having the... Agent: Miles & Stockbridge PC

20070111512 - Semiconductor integrated circuit device and a method of manufacturing the same: For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070111514 - Dual damascene process utilizing teos-based silicon oxide cap layer having reduced carbon content: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is... Agent: North America Intellectual Property Corporation

20070111515 - Metal line stacking structure in semiconductor device and formation method thereof: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second... Agent: Fulbright And Jaworski LLP

20070111513 - Method of fabricating opening and plug: A method of fabricating an opening or plug. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the dielectric layer... Agent: Jianq Chyun Intellectual Property Office

20070111516 - Semiconductor assembly having substrate with electroplated contact pads: An apparatus comprising an insulating substrate having first and second surfaces and a plurality of metal-filled vias extending from the first to the second surface. The first and second surfaces have contact pads, each one comprising a connector stack to at least one of the vias. The stack comprises a... Agent: Texas Instruments Incorporated

20070111517 - Chemical mechanical polishing process: A copper/barrier CMP process includes (a) providing a substrate having a bulk metal layer and a barrier layer; (b) polishing the substrate with a first hard polishing pad on a first platen to substantially remove an upper portion of the bulk metal layer, wherein the first hard polishing pad has... Agent: North America Intellectual Property Corporation

20070111518 - Method and structure for sample preparation for scanning electron microscopes in integrated circuit manufacturing: A method for using a calibration standard. The method includes providing a calibration standard. In a specific embodiment, the calibration standard has a substrate, a thickness of material having an edge region; and a conformal material of uniform thickness disposed on the edge region. The standard also has an upper... Agent: Townsend And Townsend And Crew, LLP

20070111519 - Integrated electroless deposition system: Embodiments of the invention provide methods for depositing a material onto a surface of a substrate by using one or more electroless, electrochemical plating, CVD and/or ALD processes. Embodiments of the invention provide a method for depositing a seed layer on a substrate with an electroless process and to subsequently... Agent: Patterson & Sheridan, LLP

20070111520 - Chemical sensor using chemically induced electron-hole production at a schottky barrier: Electron-hole production at a Schottky barrier has recently been observed experimentally as a result of chemical processes. This conversion of chemical energy to electronic energy may serve as a basic link between chemistry and electronics and offers the potential for generation of unique electronic signatures for chemical reactions and the... Agent: Michael A. O'neil Michael A. O'neil, P.C.

20070111521 - Surface preparation prior to deposition on germanium: Methods are provided for treating germanium surfaces in preparation for subsequent deposition, particularly gate dielectric deposition by atomic layer deposition (ALD). Prior to depositing, the germanium surface is treated with plasma products or thermally reacted with vapor reactants. Examples of surface treatments leave oxygen bridges, nitrogen bridges, —OH, —NH and/or... Agent: Knobbe Martens Olson & Bear LLP

20070111522 - Formation of metal silicide layer over copper interconnect for reliability enhancement: A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form... Agent: William Stoffel

20070111523 - Process for conditioning conductive surfaces after electropolishing: A method of conditioning an electropolished conductive layer of a substrate is disclosed, the conductive layer having impurities thereon. The conductive layer may be formed on a thin conductive film or barrier layer that coats one or more cavities formed on the substrate surface. The method comprises applying a first... Agent: Knobbe Martens Olson & Bear LLP

20070111524 - Semiconductor device and method of fabricating same: Embodiments of a semiconductor device and a method of fabricating the same may include an insulating layer formed on a substrate and having a predetermined hole, a metal interconnection formed in the hole and protruding relative to the insulating layer, a first barrier extending in a lateral direction of the... Agent: Sherr & Nourse, PLLC

20070111525 - Method for converting electrical components: A method for removing an undesirable material from an electronic or electrical component and introducing a desirable material in place of the undesirable material. The method can include the replacement of a leaded material found on the component with a no-lead material to meet governmental directives including those of the... Agent: Intellectual Property Group Bose Mckinney & Evans LLP

20070111526 - Semiconductor processing methods of patterning materials: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material,... Agent: Wells St. John P.s.

20070111527 - Method for producing and cleaning surface-mountable bases with external contacts: In a method for producing bases with external contacts for surface mounting on circuit mounts, bases with external contacts are electrodeposited on semiconductor wafers or semiconductor chips. Subsequently, electrodeposited bases with external contacts are heat treated on the semiconductor wafers or the semiconductor chips at temperatures below the melting temperature... Agent: Baker Botts, L.L.P.

20070111530 - Method for etching an object to be processed: An object to be process has a structure having an SiC film 61 and an organic Si-low dielectric constant film 62 formed on the SiC film 61. The SiC film 61 is etched using a plasma produced from an etching gas and using the organic Si low-dielectric constant film 62... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070111528 - Method of cleaning semiconductor substrate conductive layer surface: A method of cleaning a semiconductor substrate conductive layer surface that can remove a residual organic material and a natural oxide satisfactorily and does not adversely affect a k value without damaging the side-wall insulation film of a via hole. A semiconductor device, including insulation films formed on the surface... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070111529 - Plasma etching method: In a plasma etching method for etching a target object by using a plasma of a processing gas in a processing chamber of a plasma processing apparatus, the target object includes an etching target film and a porous Low-k film formed above the etching target film. The processing gas contains... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070111531 - Technique for the growth of planar semi-polar gallium nitride: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in... Agent: Gates & Cooper LLP Howard Hughes Center

20070111534 - Method of removing silicon from a substrate: A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least 10, under conditions and for... Agent: Wells St. John P.s.

20070111532 - Paa-based etchant, methods of using same, and resultant structures: A wet-etch composition may include: peracetic acid (PAA); and a fluorinated acid; a relative amount of the PAA in the composition being sufficient to ensure an etch rate of (P-doped-SiGe):(P-doped-Si) that is substantially the same as an etch rate of (N-doped-SiGe):(N-doped-Si). Such a wet-etch composition is hereafter referred to as... Agent: Harness, Dickey & Pierce, P.L.C

20070111533 - Removal of mems sacrificial layers using supercritical fluid/chemical formulations: A method and composition for removing silicon-containing sacrificial layers from Micro Electro Mechanical System (MEMS) and other semiconductor substrates having such sacrificial layers is described. The etching compositions include a supercritical fluid (SCF), an etchant species, a co-solvent, and optionally a surfactant. Such etching compositions overcome the intrinsic deficiency of... Agent: Moore & Van Allen PLLC

20070111535 - Method to create damage-free porous low-k dielectric films and structures resulting therefrom: Low dielectric constant dielectric films having a high degree of porosity suffer from poor mechanical strength and can be damaged during processing steps. Damage can be substantially eliminated or minimized by stuffing the pores of the dielectric film with a material that substantially fills the pores. The stuffing material should... Agent: Slater & Matsil, L.L.P.

20070111536 - Substrate treatment apparatus and substrate treatment method: A substrate treatment apparatus is disclosed. The substrate treatment apparatus has an electrostatic chuck mechanism, a grounding mechanism, and an electron beam radiating mechanism. The electrostatic chuck mechanism electrostatically sucks and holds a substrate under treatment. The grounding mechanism freely contacts a predetermined film of a plurality of films formed... Agent: Rader Fishman & Grauer PLLC

20070111537 - Method and system for controllable deposition of nanoparticles on a substrate: In a method and system for controllable electrostatic-directed deposition of nanoparticles from the gas phase on a substrate patterned to have p-n junction(s), a bias electrical field is reversely applied to the p-n junction, so that uni-polarly charged nanoparticles are laterally confined on the substrate by a balance of electrostatic,... Agent: Rosenberg, Klein & Lee

20070111539 - Material for forming adhesion reinforcing layer, adhesion reinforcing layer, semiconductor device, and manufacturing method thereof: The present invention aims at providing: a material for forming an adhesion reinforcing layer which can reinforce the adhesion between a low dielectric constant film, especially a low dielectric constant film containing an inorganic material, and other members; an adhesion reinforcing layer formed by the said material and exhibits superior... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070111538 - Method of fabricating a silicon nitride stack: Embodiments of methods for fabricating a silicon nitride stack on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a silicon nitride stack on a semiconductor substrate includes depositing a base layer comprising silicon nitride on the substrate using a first set of process conditions that... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070111540 - Method of forming silicon-containing insulation film having low dielectric constant and low film stress: A method for forming a silicon-containing insulation film on a substrate by plasma polymerization includes: introducing a reaction gas comprising (i) a source gas comprising a silicon-containing hydrocarbon cyclic compound containing at least one vinyl group (Si-vinyl compound), and (ii) an additive gas, into a reaction chamber where a substrate... Agent: Knobbe Martens Olson & Bear LLP

20070111541 - Barrier film material and pattern formation method using the same: In a pattern formation method, a barrier film including a polymer and a cross-linking agent for thermally causing a cross-linking reaction of the polymer is formed on a resist film formed on a substrate. Subsequently, the barrier film is annealed for cross-linking the polymer, and pattern exposure is performed by... Agent: Mcdermott Will & Emery LLP

20070111542 - Substrate treatment apparatus and substrate treatment method: A substrate treatment apparatus is disclosed. The substrate treatment apparatus has an electrostatic chuck mechanism, a grounding mechanism, and an electron beam radiating mechanism. The electrostatic chuck mechanism electrostatically sucks and holds a substrate under treatment. The grounding mechanism freely contacts a predetermined film of a plurality of films formed... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070111543 - Methods for improving low k fsg film gap-fill characteristics: The present invention relates to fluorinated silicate glass (FSG) with low dielectric constant and improved gap-fill characteristics. In the present method, a fluorinated silicon source, an optional fluorine source, an optional carbon source, a hydrogen source, and an oxygenator are used as the reactant gases. Inert or carrier gas(es) may... Agent: Patent Counsel, M/s 2061 Applied Materials, Inc.

20070111544 - Systems with a gate dielectric having multiple lanthanide oxide layers: Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may be used in a variety of electronic system applications. A dielectric film having a layer of a lanthanide oxide and a layer of another lanthanide oxide provides a... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070111545 - Methods of forming silicon dioxide layers using atomic layer deposition: Provided herein are methods of forming a silicon dioxide layer on a substrate using an atomic layer deposition (ALD) method that include supplying a Si precursor to the substrate and forming on the substrate a Si layer including at least one Si atomic layer; and (b) supplying an oxygen radical... Agent: Myers Bigel Sibley & Sajovec

20070111546 - Method for fabricating controlled stress silicon nitride films: A method for fabricating a multiple layer silicon nitride film on a semiconductor substrate is provided herein. In one embodiment, a method for fabricating a multiple layer silicon nitride film on a semiconductor substrate includes providing a substrate over which the multiple layer silicon nitride film is to be formed;... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070111547 - Method for producing a semiconductor structure: In a method for producing a semiconductor structure a substrate is provided, a dielectric layer comprising at least one metal oxide is formed on the substrate, and a nitrided layer is formed from the dielectric layer. The nitrided layer comprises either at least one metal nitride corresponding to the metal... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070111549 - Laser irradiation apparatus: In annealing of a non-single crystal silicon film by a linear laser beam, it is performed so as irradiation tracks caused by the linear laser beam do not remain in the silicon film. Laser light is partitioned by an integrally formed cylindrical array lens, and is composed into a single... Agent: Nixon Peabody, LLP

20070111548 - Plasma doping method and plasma doping apparatus: Disclosed is a plasma doping method that, even though a plasma doping treatment is repeated, can make a dose from a film to a silicon substrate uniform for each time. According to an embodiment of the invention, there is provided a plasma doping method that places a sample on a... Agent: Mcdermott Will & Emery LLP

20070105239 - Method of forming vertical microelectrodes in a microchannel: A method for forming vertical electrodes in a microchannel includes providing a substrate having a cross-linked polymer layer thereon. A plurality of electrical contacts are then patterned on the cross-linked polymer. A photoresist is applied on the cross-linked polymer overtop the electrical contacts. Holes or vias are formed in the... Agent: VistaIPLaw Group LLP

20070105240 - Apparatus and methods for nanolithography using nanoscale optics: An apparatus and methods for nanolithography using nanoscale optics are disclosed herein. Submicron-scale structures may be obtained using standard photolithography systems with a de-magnifying lens. A de-magnifying lens for use in a standard photolithography system includes a film having a top surface, a bottom surface and a plurality of cylindrical... Agent: Greenberg Traurig, LLP

20070105241 - Ferromagnetic liner for conductive lines of magnetic memory cells: A method of forming a ferromagnetic liner on conductive lines of magnetic memory devices and a structure thereof. The ferromagnetic liner increases the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. The conductive lines are formed in... Agent: Slater & Matsil LLP

20070105242 - Substrate treatment method: There is provided a substrate treatment method for performing treatment by feeding a chemical liquid to a surface of a substrate, in which, before feeding the chemical liquid to a predetermined area of the substrate, a liquid substance having a resistivity lower than that of the chemical liquid is fed... Agent: Rader Fishman & Grauer PLLC

20070105244 - Analytical apparatus, processing apparatus, measuring and/or inspecting apparatus, exposure apparatus, substrate processing system, analytical method, and program: A line width of a pattern on a substrate that is exposed and developed in an exposure apparatus is measured by a measuring instrument. In the case the line width is judged to be abnormal (step 303), an analytical apparatus specifies an apparatus that causes a line width variation factor... Agent: Oliff & Berridge, PLC

20070105243 - Method and apparatus for semiconductor device production process monitoring and method and apparatus for estimating cross sectional shape of a pattern: In an exposure process or etching process, an image feature amount useful for estimating a cross-sectional shape of a target evaluation pattern, process conditions for the pattern, or device characteristics of the pattern is calculated from an SEM image. The image feature amount is compared with learning data that correlates... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070105246 - Method of manufacturing a material compound wafer: The invention relates to a device for use in a method for manufacturing a material compound wafer by forming a predetermined splitting area in a source substrate; attaching the source substrate to a handle substrate to form an assembly; heating the assembly for weakening the predetermined splitting area; and determining... Agent: Winston & Strawn LLP Patent Department

20070105245 - Wafer inspection data handling and defect review tool: A defect detected by a wafer inspection tool is reliably captured by a defect review tool. A defect review condition in the defect review tool is varied depending on defect attributes provided by the wafer inspection tool so as to optimize the review process. For example, review magnification is varied... Agent: Mcdermott Will & Emery LLP

20070105247 - Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation: A structure in a semiconductor device useful in determining an endpoint in a chemical-mechanical polishing process is provided. The structure comprises a dielectric layer, an anti-reflective coating, and a metal layer. The dielectric layer has an opening extending therein. The anti-reflective coating extends over at least a portion of the... Agent: Williams, Morgan & Amerson

20070105248 - Method of inspecting semiconductor device: An inspection method includes performing an inspection by applying a probe to pads of a contact check pattern located, together with a chip patterns on a wafer, and performing an inspection by applying the probe to pads of the chip pattern if a result of the inspection using the contact... Agent: Leydig Voit & Mayer, Ltd

20070105249 - Nano-based device and method: A nano-based device includes a support structure providing a support surface, a second structure providing a second surface angled with respect to the support surface, and at least one nano-emitter provided on the second surface.... Agent: Patent Counsel Schlumberger Reservoir Completions

20070105251 - Method and structure of germanium laser on silicon: A laser structure includes at least one active layer having doped Ge so as to produce light emissions at approximately 1550 nm from the direct band gap of Ge. A first confinement structure is positioned on a top region of the at least one active layer. A second confinement structure... Agent: Gauthier & Connors, LLP

20070105250 - Roll-to-roll fabricated light sheet and encapsulated semiconductor circuit devices: A method of making a light active sheet. A bottom substrate having an electrically conductive surface is provided. A hotmelt adhesive sheet is provided. Light active semiconductor elements, such as LED die, are embedded in the hotmelt adhesive sheet. The LED die each have a top electrode and a bottom... Agent: Michaud-duffy Group LLP

20070105252 - Method of manufacturing device having flexible substrate and device having flexible substrate manufactured using the same: The present invention relates to a method of manufacturing a device having a flexible substrate and a device having a flexible substrate manufactured using the method. According to the method of manufacturing a device having a flexible substrate of the invention, glass is used as a mother substrate, a polymer... Agent: Mckenna Long & Aldridge LLP

20070105254 - Method for making a multi-layer diffractive optics memory: The present invention comprises method for making a multi-layer diffractive optics memory to extend storage capacity. A first layer is made by laying down a thin layer of polypeptide on a substrate. The substrate may be a glass substrate or plastic film substrate. One or more interference patterns are recorded... Agent: Discovision Associates

20070105253 - Method of producing a plurality of bodies: In the described method of producing a plurality of bodies bearing equal imprints of a stamp as optical structures, a stamp (13) is initially produced, by attaching particles (14) to a surface (15) of an auxiliary body (16); than, the stamp (13) is used to produce an imprint (11) on... Agent: Philips Intellectual Property & Standards

20070105255 - Method of fabricating display device and display device: A method of fabricating a display device having a TFT substrate and an array of plural light-emitting devices arranged on the substrate, each of the light-emitting devices having a lower electrode, an upper electrode, and organic layers sandwiched between the lower and upper electrodes, includes the steps of: arraying the... Agent: Robert J. Depke Lewis T. Steadman

20070105256 - Monolithically integrated light emitting devices: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant... Agent: Wolf Greenfield & Sacks, PC

20070105257 - Methods of fabricating semiconductor devices: Disclosed are methods of fabricating semiconductor devices. A method may include forming a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer. The method may also include forming a mask layer on the third conductive layer, forming a photoresist... Agent: Harness, Dickey & Pierce, P.L.C

20070105258 - Group iii nitride semiconductor substrate: A GaN substrate 1, a group III nitride semiconductor substrate, is provided with an OF portion 2 for the periphery thereof. The bevel 7 on the periphery of the nitric polarity face 5 side of the GaN substrate 1 is provided throughout the entire periphery of the GaN substrate 1... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070105259 - Growth method of indium gallium nitride: A method for growing a high quality indium gallium nitride by metal organic chemical vapor deposition (MOCVD) is provided. In the method, the indium gallium nitride grows at a growth rate of at least about 1.5 nm/min at a temperature of at least about 800° C. while an internal pressure... Agent: Mcdermott Will & Emery LLP

20070105261 - Nitride semiconductor light emitting device and method for manufacturing the same: Disclosed herein is a nitride semiconductor light emitting device. The nitride semiconductor light emitting device comprises a substrate, an n-type nitride semiconductor layer formed on the substrate and provided with an electrode region of a predetermined area adjacent to a center of one lateral side of the top surface of... Agent: Lowe Hauptman Berner, LLP

20070105260 - Nitride-based semiconductor device and production method thereof: A method of producing a nitride-based semiconductor device includes the steps of forming a releasing layer on a substrate for facilitating separation of the substrate; and forming at least one nitride-based semiconductor layer on the releasing layer. As the releasing layer, or in place of the releasing layer, at least... Agent: Morrison & Foerster LLP

20070105262 - Method for fabricating an integrated circuit with a cmos manufacturing process: An integrated circuit, which is formed on a semiconductor substrate and which comprises front-end-of-line processed electronic elements and a back-end-of-line processed wiring on top of the electronic elements. The wiring interconnects the electronic elements. The integrated circuit further comprises a highly UV-absorbing layer between the electronic elements and the wiring.... Agent: Morrison & Foerster LLP

20070105263 - Thin film semiconductor device, polycrystalline semiconductor thin film production process and production apparatus: A process for producing an image display device using a thin film semiconductor device is provided which includes forming a polycrystalline semiconductor thin film on a substrate. A substantially belt-shaped crystal is formed which is crystallized so as to grow crystal grains in a direction substantially parallel to a scanning... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070105264 - Manufacturing method of semiconductor device: To provide a thin semiconductor device having flexibility. A groove is formed in one surface of a substrate; an element layer including an element is formed, the element being disposed within the groove; the substrate is thinned from the other surface of the substrate until one surface of the element... Agent: Eric Robinson

20070105265 - Front side illuminated photodiode with backside bump: This invention relates to a novel optoelectronic chip with one or more optoelectronic devices, such as photodiodes, fabricated on a front side of a semiconductor wafer and contacts on a backside of the semiconductor wafer. The backside contacts can be contact bumps, which allow the optoelectronic chip to achieve the... Agent: Knobbe Martens Olson & Bear LLP

20070105266 - Anti-reflective substrate and the manufacturing method thereof: The present invention is to provide an anti-reflective substrate, and the manufacturing method of the substrate. The method comprises the steps of: (a) providing a substrate; (b) depositing an amorphous silicon layer on the substrate; and (c) etching the amorphous silicon layer and the substrate by chemical etching in solutions,... Agent: Bacon & Thomas, PLLC

20070105267 - Phase change memory with threshold switch select device: An ovonic threshold switch may be formed of a continuous chalcogenide layer. That layer spans multiple cells, forming a phase change memory. In other words, the ovonic threshold switch may be formed of a chalcogenide layer which extends, uninterrupted, over numerous cells of a phase change memory.... Agent: Trop Pruner & Hu, PC

20070105268 - Organic thin film transistor and process for manufacturing same: A process for manufacturing an organic thin film transistor includes the steps of arranging a shaping element having a first profile defining a slot, forming a mold suitable to define a cavity with the shaping element, depositing source and drain layers, an active material layer and a dielectric layer within... Agent: Hogan & Hartson LLP

20070105273 - Adjusting die placement on a semiconductor wafer to increase yield: A die placement of dice to be formed on a semiconductor wafer is adjusted by obtaining a die placement and one or more locations on the wafer contacted by one or more processing structures or a substance emitted by one or more processing structures. The die placement is adjusted based... Agent: Morrison & Foerster LLP

20070105271 - Method of designing package for semiconductor device, layout design tool for performing the same, and method of manufacturing semiconductor device using the same: A package design method for a semiconductor device of designing a package including a package substrate provided with a wiring pattern, a chip mounted on the package substrate, and a sealing resin which covers the package substrate and the chip, and the wiring pattern including an external connection terminal and... Agent: Mcdermott Will & Emery LLP

20070105272 - Microelectronic devices and microelectronic support devices, and associated assemblies and methods: Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a microelectronic device that includes a microfeature workpiece having a side and an aperture in the side. The device can further include a workpiece contact having a surface. At least... Agent: Perkins Coie LLP Patent-sea

20070105270 - Packaging methods: Packaging method. The method includes providing a conductive substrate comprising top and bottom surfaces, forming a first circuit layer of a package substrate and then packaging an active device overlying the top surface, and forming other circuit layers and a contact pad of the package substrate overlying the bottom surface.... Agent: Quintero Law Office, PC

20070105269 - Prealignment and gapping for rf substrates: A method is provided for manufacturing electronic module assemblies comprising a plurality of substrates and a housing. The method comprises providing an alignment plate having a plurality of protrusions disposed through an upper surface thereof, wherein the protrusions are positioned on the alignment plate according to a predetermined substrate layout... Agent: Stetina Brunda Garred & Brucker

20070105275 - Apparatus for positioning power semiconductor modules and method for surface treatment thereof: An apparatus and an associated method for receiving and positioning a plurality of spaced-apart power semiconductor modules using a molded positioning body. The molded positioning body has a planar first main face and a plurality of receptacles for receiving the power semiconductor modules therein. Each receptacle has a stop means,... Agent: Cohen, Pontani, Lieberman & Pavane

20070105276 - Mask, mask blank, and methods of producing these: A mask decreased in warping and having a high positioning precision, provided with at least a substrate aperture formed at a portion of a silicon substrate, a first silicon oxide film formed at one surface of the silicon substrate, a single crystal silicon layer formed on the first silicon layer... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20070105274 - Monolithically integrated semiconductor materials and devices: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a semiconductor structure includes a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a... Agent: Wolf Greenfield & Sacks, PC

20070105277 - Solder joint flip chip interconnection: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a... Agent: Haynes Beffel & Wolfeld LLP

20070105278 - Printed wiring board and method of manufacturing the same: In a printed wiring board 10, an upper electrode connecting portion 52 penetrates through a capacitor portion 40 in top to bottom direction so that an upper electrode connecting portion first part 52a is not in contact with the capacitor portion 40, passes through an upper electrode connecting portion third... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070105279 - Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering: A process for the preparation of low resistivity arsensic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.... Agent: Senniger Powers

20070105280 - Brace for wire loop: A method of connecting a lead frame (12) lead finger (16a) to a bond pad (18a) on an integrated circuit (IC) die (10) includes bonding a first bonding wire (20a) from the lead finger (16a) to an intermediate point (22). A second bonding wire (20b) is bonded from the lead... Agent: Freescale Semiconductor, Inc. Law Department

20070105281 - Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package: A leadless type resin-sealed semiconductor package includes a resin enveloper having a mounting face to be applied to a wiring board, and at least one side face associated with the mounting face to produce an angled side edge. A semiconductor chip is encapsulated and sealed in the resin enveloper. An... Agent: Sughrue Mion, PLLC

20070105282 - Micro lead frame packages and methods of manufacturing the same: A microelectronic package includes a microelectronic element having contacts, a dielectric element, at least a portion of the dielectric element extending beneath the microelectronic element, and a structure including portions of a lead frame. The structure includes a plurality of terminals and leads formed integrally with the terminals, at least... Agent: Tessera Lerner David Et Al.

20070105283 - Manufacturing method of semiconductor device and semiconductor device: In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body to perform a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C. Suite 370

20070105284 - Method for forming a memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide: A memory cell is formed of a semiconductor junction diode in series with an antifuse. The cell is programmed by rupture of the antifuse. The semiconductor junction diode comprises silicon, the silicon crystallized in contact with a silicide. The silicide apparently provides a template for crystallization, improving crystallinity and conductivity... Agent: Vierra Magen/sandisk Corporation

20070105285 - Semiconductor device and manufacturing method thereof: To provide a semiconductor device which is higher functional and reliable and a technique capable of manufacturing the semiconductor device with a high yield at low cost without complexing the apparatus or process. At least one of a first conductive layer and a second conductive layer is formed containing one... Agent: Eric Robinson

20070105286 - Thin film transistor array panel and manufacturing method thereof: The present invention relates to an OLED display and a manufacturing method thereof, including a substrate, a control electrode formed on the substrate, a polysilicon semiconductor formed on the control electrode, a data line including an input electrode at least partially overlapping the polysilicon semiconductor and an output electrode facing... Agent: Cantor Colburn, LLP

20070105287 - Low-temperature polysilicon display and method for fabricating same: A display panel comprising at least one display area and one peripheral circuit area having electronic components for driving the display components in the display area. The electronic components in the display area are fabricated substantially on a polysilicon layer converted from amorphous silicon by a solid phase crystallization process,... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070105288 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device with improved operating characteristics and reliability is provided. An amorphous semiconductor film is formed over a substrate, doped with a metal element promoting crystallization, and crystallized by first heat treatment to form a crystalline semiconductor film; a first oxide film formed over the... Agent: Eric Robinson

20070105289 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device according to one aspect of the present invention comprises: forming a gate insulation film on a semiconductor substrate in which element separation regions are formed; depositing a gate lower layer material on the semiconductor substrate via the gate insulation film; depositing a gate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070105290 - Tft array substrate and photo-masking method for fabricating same: An exemplary method for fabricating a thin film transistor array substrate (200) includes: providing an insulating substrate (201); coating a transparent conductive layer (202) and a gate metal layer (203) on the substrate; forming a gate electrode (213) and a pixel electrode (212) using a first photo-mask process; forming a... Agent: Wei Te Chung Foxconn International, Inc.

20070105292 - Method for fabricating high tensile stress film and strained-silicon transistors: A method for fabricating high tensile stress film and strained-silicon transistors. First, a semiconductor substrate is provided and a gate, at least a spacer, and a source/drain region are formed on the semiconductor substrate. Next, n deposition processes are performed to form n layers of high tensile stress film over... Agent: North America Intellectual Property Corporation

20070105295 - Method for forming lightly-doped-drain metal-oxide-semiconductor (ldd mos) device: An improved process for forming LDD MOS devices is disclosed herein. According the embodiments of the present invention, the LDD MOS structure can include a gate oxide and a gate electrode formed in a recessed region of a semiconductor substrate. The recessed region may be formed by selectively removing a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070105296 - Method for production of semiconductor device: A method for production of a semiconductor device including the steps of: forming a gate insulating film, a polysilicon film and a first insulating film on a silicon substrate; patterning the first insulating film; forming a metal film; formin a silicide layer by reacting the polysilicon film with the metal... Agent: Sughrue Mion, PLLC

20070105291 - Method of manufacturing a semiconductor device and semiconductor device obtained with such a method: The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type, which both are... Agent: Philips Intellectual Property & Standards

20070105298 - Methods of fabricating high voltage mosfet having doped buried layer: A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source... Agent: Myers Bigel Sibley & Sajovec

20070105293 - Methods of fabricating integrated circuit devices using anti-reflective coating as implant blocking layer: A patterned anti-reflective coating may be used as a selective implant-blocking layer during fabrication of an integrated circuit transistor. In particular, the anti-reflective coating may be used as a gate sidewall spacer to block at least some dopants from an integrated circuit substrate beneath the gate sidewall spacer. Moreover, a... Agent: Myers Bigel Sibley & Sajovec

20070105294 - Nitrogen based implants for defect reduction in strained silicon: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers... Agent: Texas Instruments Incorporated

20070105297 - Semiconductor devices and methods of manufacturing the same: Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular,... Agent: Myers Bigel Sibley & Sajovec

20070105299 - Dual stress memory technique method and related structure: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize... Agent: Hoffman, Warnick & D'alessandro LLC

20070105300 - Semiconductor substrate and method for manufacturing semiconductor device: A semiconductor substrate and a method for manufacturing a semiconductor device are provided. A method for manufacturing a BiCMOS semiconductor device is capable of preventing the generation of a block defect causing particle source in the process of forming a DUF nitride layer for protecting a rear surface of a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070105301 - High-gain vertex lateral bipolar junction transistor: A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well... Agent: Slater & Matsil, L.L.P.

20070105302 - Integrated circuit formed on a semiconductor substrate: An integrated circuit is provided, which is formed on a semiconductor substrate. The integrated circuit comprises electronic elements and isolation elements, wherein the electronic elements and the isolation elements are arranged at a top surface of the semiconductor substrate. The isolation elements each are arranged between electronic elements and electrically... Agent: Morrison & Foerster LLP

20070105303 - Methods of forming a plurality of circuit components and methods of forming a plurality of structures suspended elevationally above a substrate: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining... Agent: Wells St. John P.s.

20070105304 - Semiconductor device, fabrication method therefor, and film fabrication method: The present invention provides a semiconductor device, a fabrication method therefor, and a film fabrication method, the semiconductor device including a first substrate (e.g., a semiconductor chip), an anisotropic conductive film that is provided on the first substrate and has a wiring pattern having at least a portion providing conduction... Agent: Wagner, Murabito & Hao LLP

20070105305 - Method to form large grain size polysilicon films by nuclei-induced solid phase crystallization: A method to enhance grain size in polysilicon films while avoiding formation of hemispherical grains (HSG) is disclosed. The method begins by depositing a first amorphous silicon film, then depositing silicon nuclei, which will act as nucleation sites, on the amorphous film. After deposition of silicon nuclei, crystallization, and specifically... Agent: Vierra Magen/sandisk Corporation

20070105309 - Contactless nonvolatile memory device and method of forming the same: A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch... Agent: F. Chau & Associates, LLC

20070105311 - Flash memory and method for manufacturing the same: Provided are a flash memory and a method for manufacturing the same. The flash memory includes a semiconductor substrate having a device isolation region and an active region; a stacked gate on the semiconductor substrate; an insulation layer covering the semiconductor substrate and the stacked gate; a drain contact penetrating... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070105313 - In service programmable logic arrays with low tunnel barrier interpoly insulators: Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070105312 - Memory cell with nanocrystal as discrete storage element: A memory cell including: a substrate; a channel region located in the substrate; a tunnel dielectric located over the channel region; and nanocrystals located over the tunnel dielectric.... Agent: George Chen Blakely, Sokoloff, Taylor & Zafman LLP

20070105310 - Memory structure: A memory structure including a semiconductor substrate, an insulator layer formed on the semiconductor substrate and a gate layer formed on the insulator layer is disclosed. The insulator layer includes a first nanocrystal implanted region proximate to the gate layer and a second nanocrystal implanted region proximate to the semiconductor... Agent: Davidson Berquist Jackson & Gowdey LLP

20070105306 - Nanocrystal bitcell process integration for high density application: A method for making a multibit non-volatile memory cell structure is provided herein. In accordance with the method, a semiconductor substrate (101) is provided, and first and second sets of memory stacks (103, 105, 107, and 109) are formed on the substrate, each memory stack comprising a control gate (111)... Agent: Fortkort & Houston P.C.

20070105307 - Self-aligned double layered silicon-metal nanocrystal memory element, method for fabricating the same, and memory having the memory element: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a... Agent: Ishimaru & Zahrt LLP

20070105308 - Semiconductor device and fabrication method therefor: The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches (11) formed in a semiconductor substrate (10), first ONO films (18) provided on both side surfaces of the trenches, and first word lines (22) provided on side surfaces of the first ONO films (18)... Agent: Wagner, Murabito & Hao LLP

20070105315 - Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating c-mos structures: A method according to the invention enables first and second active zones to be produced on a front face of a support, which said zones are respectively formed by first and second monocrystalline semi-conducting materials that are distinct from one another and preferably have identical crystalline structures. The front faces... Agent: Oliff & Berridge, PLC

20070105314 - Process for manufacturing a non-volatile memory device: A non volatile memory device is integrated on a semiconductor substrate and includes a matrix of memory cells with an associated circuitry. The process for forming the memory device includes forming in the semiconductor substrate first dielectric insulation regions of the matrix to define and insulate first active areas of... Agent: Jenkens & Gilchrist, PC

20070105316 - Nanocrystal memory element, method for fabricating the same and memory having the memory element: A nanocrystal memory element and a method for fabricating the same involves repeatedly and alternately depositing, by atomic layer deposition, conductive layers and dielectric layers on a substrate with a tunnel oxide layer formed thereon, forming multiple layers of nanocrystal groups as a result of crystallization of conductive layers in... Agent: Birch Stewart Kolasch & Birch

20070105318 - Display device: A display device includes a display panel, first and second gate drivers and a data driver. The display panel includes pixel regions respectively having first, second and third pixels. The first pixel is coupled to first, second gate lines and a data line. The second gate line is adjacent to... Agent: Cantor Colburn, LLP

20070105317 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises a step of forming a gate insulating layer on a semiconductor substrate, a step of forming a first metal layer on the gate insulating layer, a step of forming a second metal layer including... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070105319 - Pattern density control using edge printing processes: A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of... Agent: Schmeiser, Olsen & Watts

20070105320 - Method and structure of multi-surface transistor device: A double gated MOS transistor structure and method of manufacture. Fabricating transistor devices on both top and bottom surfaces of the silicon layer creates vertical double gate transistor devices. The presented double gate transistor devices do not require alignment of the top and bottom gates. In addition to double gate... Agent: Townsend And Townsend And Crew, LLP

20070105321 - Method of manufacturing a nanowire device: The present invention provides a method for manufacturing a semiconductor nanowire device in mass production at a low cost without an additional complex nanowire alignment process or SOI substrate by forming a single crystal silicon nanowire with a simple process without forming an ultra fine pattern using an electron beam... Agent: Greenblum & Bernstein, P.L.C

20070105322 - Method of simultaneously controlling adi-aei cd differences of openings having different sizes and etching process utilizing the same method: A method of simultaneously controlling the ADI-AEI CD differences of openings having different sizes is disclosed. The openings are formed by: forming an ARC and a photoresist layer with a first and a second opening patterns of different sizes therein on a material layer, and etching the ARC and the... Agent: Jianq Chyun Intellectual Property Office

20070105323 - Method of forming a field effect transistor: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than... Agent: Wells St. John P.s.

20070105324 - Removing silicon nano-crystals: A technique for reducing the number of silicon (Si) nano-crystals available to attach or otherwise deposit upon semiconductor device surfaces. More particularly, embodiments of the invention make a wafer substantially free of Si nano-crystals resulting from a wet etch of oxide layer portions, while not impairing semiconductor device dimensions or... Agent: Intel/blakely

20070105325 - Method of manufacturing cmos devices by the implantation of n- and p-type cluster ions: A method of manufacturing a semiconductor device is described, wherein clusters of N- and P-type dopants are implanted to form the transistor structures in CMOS devices. For example, As4Hx+clusters and either B10Hx− or B10Hx+ clusters are used as sources of As and B doping, respectively, during the implants. An ion... Agent: Patent Administrator Katten Muchin Rosenman LLP

20070105326 - Rotated field effect transistors and method of manufacture: An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substantially orthogonal to an edge of the first... Agent: Greenblum & Bernstein, P.L.C

20070105327 - Methods of forming field effect transistors using disposable aluminum oxide spacers: Methods of forming a field effect transistor by forming a gate electrode on a semiconductor substrate and forming aluminum oxide spacers on sidewalls of the gate electrode. Source and drain region dopants of first conductivity type are implanted into the semiconductor substrate using the aluminum oxide spacers as an implant... Agent: Myers Bigel Sibley & Sajovec

20070105328 - Production method of cell electrodes: The invention relates to fuel cells and methods of making bipolar fuel cell electrodes. The invention provides a method of producing bipolar fuel cell electrodes, including providing a collector having a first side and a second side opposite the first side, coating the first side with a first active material,... Agent: Shumaker & Sieffert, P. A.

20070105329 - Semiconductor device and method of manufacturing the same: Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070105330 - Bandgap and recombination engineered emitter layers for sige hbt performance optimization: A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; and forming an emitter region over the compound base region including forming a first emitter layer within the emitter region... Agent: Sawyer Law Group LLP

20070105331 - Cmos transistor junction regions formed by a cvd etching and deposition sequence: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching... Agent: Intel/blakely

20070105332 - Integrated circuit capacitor having antireflective dielectric: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that... Agent: Texas Instruments Incorporated

20070105333 - Vertical interconnect structure, memory device and associated production method: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is... Agent: Brinks Hofer Gilson & Lione Infineon

20070105334 - Methods of fabricating semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby: In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are... Agent: Mills & Onello LLP

20070105335 - Monolithically integrated silicon and iii-v electronics: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant... Agent: Wolf Greenfield & Sacks, PC

20070105337 - Selective nitride liner formation for shallow trench isolation: A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070105336 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a semiconductor substrate formed with an active region and an isolation region and having a trench formed in the isolation region; an isolation insulating film embedded in the trench of the semiconductor substrate; and semiconductor nanocrystals buried in the isolation insulating film. The coefficient of linear... Agent: Mcdermott Will & Emery LLP

20070105338 - Trench insulation in substrate disks comprising logic semiconductors and power semiconductors: Disclosed is a layer arrangement (4b, 5b, 9b, 10, 9a, 5a, 4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insulating high-voltage power components (7) relative to low-voltage logic elements (6) that are integrated on the same chip (1, 2, 3). Also disclosed... Agent: Hunton & Williams LLP Intellectual Property Department

20070105341 - Bonding metals and non-metals using inductive heating: A bonding technique suitable for bonding a non-metal body, such as a silicon MEMS sensor, to a metal surface, such a steel mechanical component is rapid enough to be compatible with typical manufacturing processes, and avoids any detrimental change in material properties of the metal surface arising from the bonding... Agent: Beyer Weaver LLP

20070105340 - Interlayer bond to a substrate which, at least in regions on a surface, is provided with a coating of a metal, a method for production thereof and use: The invention relates to substrates which, at least in regions on a surface, are provided with a coating of a metal, a method for producing such substrates and the use thereof. It is thereby the object of the invention to improve the adhesion of a coating of a metal on... Agent: Jacobson Holman PLLC

20070105342 - Method of fabricating microelectromechanical system structures: A method of simultaneously bonding components, comprising the following steps. At least first, second and third components are provided and comprise: at least one glass component; and at least one conductive or semiconductive material component. The order of stacking of the components is determined to establish interfaces between the adjacent... Agent: Saile Ackerman LLC

20070105339 - Method of fabricating multi layer mems and microfluidic devices: A method for fabricating multi layer microelectromechanical and microfluidic devices is disclosed. Multi layer microelectromechanical and microfluidic devices are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstucted layers of devices at or on the weak bond regions. The layers are then peeled and... Agent: Reveo, Inc.

20070105344 - Method for pre-treating epitaxial layer, method for evaluating epitaxial layer, and apparatus for evaluating epitaxial layer: A method for pre-treating an epitaxial layer performed before evaluation of the epitaxial layer by making the epitaxial layer contact with a metal electrode by a capacitance-voltage measurement, the method comprising; applying carbon-bearing compound to a surface of the epitaxial layer; subsequently irradiating ultraviolet light to the surface of the... Agent: Kolisch Hartwell, P.C.

20070105343 - Method of grinding back surface of semiconductor wafer and semiconductor wafer grinding apparatus: A semiconductor wafer back-surface grinding method, for grinding a back surface of a semiconductor wafer, an opposed front surface of the semiconductor wafer being adhered to a support base material and being provided with a circuit pattern, including: measuring an initial thickness of the semiconductor wafer before grinding, in a... Agent: Christie, Parker & Hale, LLP

20070105345 - Semiconductor wafer dividing method: An element is formed on the major surface of a semiconductor wafer, and a groove is formed in the back surface of the semiconductor wafer along a dicing line or chip dividing line by a mechanical or chemical method. A modified layer is formed by irradiating the groove with a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070105346 - Small chips with fan-out leads: A method of expanding the contact pitch for un-diced chips in an array by pre-slicing the array in a first direction, attaching a lead frame to the chips' contacts, and then slicing the array and attached lead frame in the second direction. The lead frame has leads mechanically connected one... Agent: Tessera Lerner David Et Al.

20070105347 - Method for separating parts from a substrate: An improved method for producing a plurality of parts (30) from a plate-type substrate (20) is disclosed, comprising the steps of: (a) laterally separating the parts (30) from a plate-type substrate (20) fixed on a first vacuum plate (3); (b) sucking the parts (30) on a first vacuum plate (3);... Agent: Demont & Breyer, LLC

20070105348 - Wafer processing method: A wafer processing method for dividing a wafer having devices which are formed in areas sectioned by a plurality of streets formed in a lattice pattern on the front surface, along the streets, comprising a protective tape affixing step for putting a protective tape whose adhesive force is reduced by... Agent: Smith, Gambrell & Russell

20070105350 - Defect reduction by oxidation of silicon: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a... Agent: Scully, Scott, Murphy & Presser, P.C.

20070105349 - Epitaxial semiconductor structures having reduced stacking fault nucleation sites: Epitaxial silicon carbide layers are fabricated by forming features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. The epitaxial silicon carbide layer is... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070105351 - Gan single crystal substrate and method of making the same: The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer... Agent: Smith, Gambrell & Russell

20070105352 - Uniform seeding to control grain and defect density of crystallized silicon for use in sub-micron thin film transistors: A method to create a polysilicon layer with large grains and uniform grain density is described. A first amorphous silicon layer is formed. A crystallizing agent is selectively introduced in a substantially symmetric pattern, preferably symmetric in two dimensions, across an area of the first amorphous layer. The crystallizing agent... Agent: Vierra Magen/sandisk Corporation

20070105353 - Metallic quantum dots fabricated by a superlattice structure: A method for forming quantum dots includes forming a superlattice structure that includes at least one nanostrip protruding from the superlattice structure, providing a quantum dot substrate, transferring the at least one nanostrip to the quantum dot substrate, and removing at least a portion of the at least one nanostrip... Agent: Hewlett Packard Company

20070105354 - Buried subcollector for high frequency passive devices: A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector... Agent: Scully, Scott, Murphy & Pressner

20070105355 - Method of implanting a substrate and an ion implanter for performing the method: An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the subsequent fast scan speed... Agent: Robert W. Mulcahy Applied Materials, Inc.

20070105356 - Method of controlling nanowire growth and device with controlled-growth nanowire: Nanowire growth in situ on a planar surface, which is one of a crystalline surface having any crystal orientation, a polycrystalline surface and a non-crystalline surface, is controlled by guiding catalyzed growth of the nanowire from the planar surface in a nano-throughhole of a patterned layer formed on the planar... Agent: Hewlett Packard Company

20070105357 - Silicided recessed silicon: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less... Agent: Knobbe Martens Olson & Bear LLP

20070105358 - Method for forming silicide contacts: Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a... Agent: Marger Johnson & Mccollom, P.C.

20070105359 - Electrical interconnection structure formation: An electrical interconnection structure and method for forming. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the... Agent: Schmeiser, Olsen & Watts

20070105360 - Method of forming bump, method of forming image sensor using the method, semiconductor chip and the sensor so formed: A method of forming a bump, a method of forming an image sensor using the method, a semiconductor chip and the sensor so formed. According to a method of forming the bump, a conductive pad is used as a seed layer to form the bump by a plating process. Since... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070105361 - Method for forming a joint: A method for forming a joint. A module is introduced including a paper or plastic substrate, an integrated circuit on a chip mounted on the substrate and in electrical contact with contact areas of the module being located on the surface of the substrate. A web is introduced including one... Agent: Venable LLP

20070105363 - Antireflective hardmask and uses thereof: Antireflective hardmask compositions and techniques for the use of antireflective hardmask compositions for processing of semiconductor devices are provided. In one aspect of the invention, an antireflective hardmask layer for lithography is provided. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at... Agent: Ryan, Mason & Lewis, LLP

20070105364 - Method of forming interconnect having stacked alignment mark: A first film layer is formed over a substrate. A portion of the first film layer is removed to form a first alignment mark pattern and a first conductive layer is formed to fill the first alignment mark pattern to form a first alignment mark. A second film layer is... Agent: Jianq Chyun Intellectual Property Office

20070105362 - Methods of forming contact structures in low-k materials using dual damascene processes: A method of forming a via using a dual damascene process can include removing a material from a recess in a low-k material using an ashing process while maintaining a protective spacer on an entire side wall of the recess to cover the low-k material in the recess.... Agent: Myers Bigel Sibley & Sajovec

20070105365 - Metal printing blanket: The metal printing blanket includes a supporting layer formed of a metallic material having a relatively high thermal conductivity, and a rubber layer applied to the metallic supporting layer and serving to transfer a print. As an alternative, the metal printing blanket includes a supporting layer formed of a metallic... Agent: Cohen, Pontani, Lieberman & Pavane

20070105366 - Long-term heat-treated integrated circuit arrangements and methods for producing the same: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat... Agent: Brinks Hofer Gilson & Lione Infineon

20070105367 - Method for forming barrier layer: A method for forming barrier layers comprises steps of providing a conductive layer, forming a first dielectric layer on the conductive layer, the first dielectric layer having a via therein, forming a first metal layer covering the first dielectric layer and the conductive layer, forming a layer of metallized materials... Agent: Arent Fox PLLC

20070105368 - Method of fabricating a microelectronic device using electron beam treatment to induce stress: The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner... Agent: Texas Instruments Incorporated

20070105369 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film... Agent: Miles & Stockbridge PC

20070105370 - Methods for anchoring a seal ring to a substrate using vias and assemblies including an anchored seal ring: Disclosed are embodiments of a method for forming a seal ring on a substrate that is anchored to the substrate by a number of vias. Also disclosed are embodiments of an assembly including such an anchored seal ring. In some embodiments, a seal ring may extend around the periphery of... Agent: Intel Corporation C/o Intellevate, LLC

20070105371 - Forming method of silicide film: A manufacturing method of a semiconductor device includes forming a cobalt film on a silicon substrate on which a diffusion layer is formed, forming a titanium film on the cobalt film using a titanium target that has a surface from which a nitride film has previously been removed, forming a... Agent: Volentine Francos, & Whitt PLLC

20070105372 - Conductive material patterning methods: A pattering method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first... Agent: Mueting, Raasch & Gebhardt, P.A.

20070105373 - Method of direct deposition of polycrystalline silicon: A method for forming a polysilicon film in a plasma-assisted chemical vapor deposition (CVD) system including a chamber in which a first electrode and a second electrode spaced apart from the first electrode are provided comprises providing a substrate on the second electrode, the substrate including a surface exposed to... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070105374 - Method for making a metal oxide semiconductor device: A method for making a MOS device includes: forming an insulator layer on a semiconductor substrate, the insulator layer including a titanium dioxide film that has a surface with hydroxyl groups formed thereon; and forming an aluminum cap film on the surface of the titanium dioxide film, and conducting annealing... Agent: Christie, Parker & Hale, LLP

20070105375 - Catalytic nucleation monolayer for metal seed layers: A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating... Agent: Blakely Sokoloff Taylor & Zafman

20070105376 - Copper-based metal polishing solution and method for manufacturing semiconductor device: Disclosed is a copper-based metal polishing solution which hardly dissolves a Cu film or a Cu alloy film when the film is dipped into the solution, and has a dissolution velocity during polishing several times higher than that during dipping. This copper-based metal polishing solution contains at least one acid... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070105377 - Fabrication of semiconductor interconnect structure: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the... Agent: Beyer Weaver LLP

20070105382 - Fluid ejection device and method of fabricating the same: A fluid ejection device includes a first substrate having a first crystal orientation, a second substrate having a second crystal orientation, bound to the first substrate, a manifold through the first and second substrates, a chamber formed in the second substrate, connected with the manifold, and a plurality of nozzles... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070105378 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes subjecting a semiconductor substrate having an aluminum film formed thereabove to a processing to at least partially expose a surface of the aluminum film, and carrying out a surface processing to remove an after-processing residue that remains on the exposed surface of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070105383 - Photoactive adhesion promoter in a slam: A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems associated with the removal of a photoresist layer. More particularly, embodiments of the invention use a photoacid generator (PAG) material in conjunction with a sacrificial... Agent: Intel/blakely

20070105381 - Process for etching a metal layer suitable for use in photomask fabrication: Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a substrate including positioning a substrate having a metal layer disposed on an optically transparent material in a processing chamber, introducing a... Agent: Patterson & Sheridan, LLP

20070105379 - Substrate processing apparatus: The substrate processing apparatus has an enclosure structure enclosing a substrate support member to define a processing space. The enclosure structure has an opening closed by a shutter. A processing fluid supply unit, which supplies processing fluid, such as chemical liquid, is accommodated in a housing. The processing fluid supply... Agent: Smith, Gambrell & Russell

20070105380 - Substrate processing apparatus: The substrate processing apparatus has an enclosure structure enclosing a substrate support member to define a processing space. The enclosure structure has an opening closed by a shutter. A processing fluid supply unit, which supplies processing fluid, such as chemical liquid, is accommodated in a housing. The processing fluid supply... Agent: Smith, Gambrell & Russell

20070105384 - Automated process and apparatus for planarization of topographical surfaces: An improved apparatus (20) and method are provided for effective, high speed contact planarization of coated curable substrates such as microelectronic devices to achieve very high degrees of planarization. The apparatus (20) includes a planarizing unit (28) preferably having an optical flat flexible sheet (88) and a backup optical flat... Agent: Hovey Williams LLP

20070105385 - Method of fabricating suspended structure: A substrate having a sacrificial layer and a structural layer disposed on the front surface of the substrate is provided. Thereon an opening is formed on the back surface of the substrate and the sacrificial layer is exposed partially. A wet etching process is performed to etch the sacrificial layer... Agent: North America Intellectual Property Corporation

20070105387 - Gate critical dimension variation by use of ghost features: According to various embodiments, the present teachings include various methods for forming a semiconductor device, computer readable medium for forming a semiconductor device, mask sets for forming a semiconductor device, and a semiconductor device made according to various methods. For example, a method can comprise forming a first feature and... Agent: Texas Instruments Incorporated

20070105389 - Method and apparatus for manufacturing a semiconductor device, control program thereof and computer-readable storage medium storing the control program: A semiconductor device manufacturing method includes a plasma etching process for selectively plasma etching a silicon nitride film against a silicon oxide film formed under the silicon nitride film in a substrate to be processed. The plasma etching process uses an etching gas including a CmFn gas (m, n represent... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070105388 - Method for fabricating semiconductor device with recess gate: A method for fabricating a semiconductor device includes forming a mask pattern over a substrate; etching a certain portion of the substrate using the mask pattern as an etch mask to form a first recess having sidewalls; forming a polymer-based layer over the sidewalls of the first recess and a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070105386 - Method of etching a dielectric layer to form a contact hole and a via hole and damascene method: A method of etching a dielectric layer by a conductive mask includes providing the dielectric layer on a substrate, forming a pattern conductive mask on the dielectric layer, the pattern conductive mask contacting with the substrate, processing a dry etching on the dielectric layer by the pattern conductive mask. Because... Agent: North America Intellectual Property Corporation

20070105390 - Oxygen depleted etching process: A method for oxygen depleted plasma etching and mixed mode plasma etching are disclosed. The method includes using an oxygen free etch plasma or a substantially oxygen free etch plasma at a high temperature to etch a stack including a plurality of layers of thin film materials. The oxygen depleted... Agent: Unity Semiconductor Corporation

20070105391 - Semiconductor device fabrication method and semiconductor device: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070105392 - Batch photoresist dry strip and ash system and process: Photoresist stripping is provided that employs batch processing to maximize throughput and an upstream plasma activation source using vapor or gas processing to efficiently create reactive species and minimize chemical consumption. An upstream plasma activation source efficiently creates reactive species remote from the photoresist on the substrate surfaces. Either a... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070105393 - Method for forming patterns and thin film transistors: A method for forming a pattern is provided. First, a substrate is provided. Then, a discontinuous film is formed on the substrate so as to reduce the stress of the film. After that, the discontinuous film is patterned to form a pattern. Besides, a method for manufacturing a thin film... Agent: Jianq Chyun Intellectual Property Office

20070105396 - High resolution structures defined by brush painting fluid onto surface energy patterned substrates: Disclosed is a method for fabricating an electronic device, the method comprising creating a surface energy pattern on a substrate and brush painting a first fluid onto the substrate to form a pattern of fluid corresponding to the surface energy pattern on the substrate. Also disclosed is a thin film... Agent: Oliff & Berridge, PLC

20070105395 - Laser functionalization and patterning of thick-film inks: An apparatus and method for producing electronic components using thick-film inks, and the electronic components manufactured therefrom. The thick-film inks, which include silver and copper inks are applied to a substrate and sintered with a laser. This process allows the fabrication of components on low temperature substrates.... Agent: Bose Mckinney & Evans LLP James Coles

20070105394 - Method for coating a structure comprising semiconductor chips: A method for coating a structure that includes at least one semiconductor chip involves electrostatically depositing coating particles on the areas of the structure to be coated. The coating particles are first applied to a carrier and the latter is electrostatically charged with the coating particles. The structure including at... Agent: Edell, Shapiro & Finnan, LLC

20070105397 - Method for removing hydrogen gas from a chamber: Embodiments of the invention provide a method for removing hydrogen gas from a chamber and a method for performing a semiconductor device fabrication sub-process and removing hydrogen gas from a chamber. The method for removing hydrogen gas from a chamber comprises removing a substrate from a chamber, wherein residual hydrogen... Agent: Volentine Francos, & Whitt PLLC

20070105398 - Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device: A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a... Agent: Robert J. Depke Lewis T. Steadman

20070105399 - Method for making a metal oxide semiconductor device: A method for making a MOS device includes: forming a titanium dioxide film on a semiconductor substrate; and subjecting the titanium dioxide film to a fluorine-containing ambient, and conducting passivation of grain boundary defects of the titanium dioxide film through reaction of fluorine and titanium dangling bonds in the titanium... Agent: Christie, Parker & Hale, LLP

20070105400 - Method and apparatus for control of layer thicknesses: It is shown a method and apparatus for distributing a viscous liquid over a surface of a substrate with high homogeneity in a defined area, e. g. on a semiconductor wafer or a data storage media, by conditioning the liquid on the substrate thermally in a first step and exposing... Agent: Pearne & Gordon LLP

20070105402 - Film-forming method, method of manufacturing semiconductor device, semiconductor device, method of manufacturing display device, and display device: Disclosed is a film-forming method, comprising supplying into a plasma processing chamber at least three kinds of gases including a silicon compound gas, an oxidizing gas, and a rare gas, the percentage of the partial pressure of the rare gas (Pr) based on the total pressure being not smaller than... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070105401 - Multi-step system and method for curing a dielectric film: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070099309 - High-density data storage medium, method of manufacturing the data storage medium, data storage apparatus, and methods of writing data on, and reading and erasing data from the data storage medium by using the data storage apparatus: A high-density data storage medium, a method of manufacturing the data storage medium, a high-density data storage apparatus, and methods of writing data on, and reading and erasing data from the data storage medium by using the data storage apparatus are provided. The data storage medium includes a lower electrode,... Agent: Buchanan, Ingersoll & Rooney PC

20070099308 - Methods of implementing magnetic tunnel junction current sensors: Techniques are provided for sensing a first current produced by an active circuit component. According to these techniques, a current sensor is disposed over the active circuit component. The current sensor includes a Magnetic Tunnel Junction (“MTJ”) core disposed between a first conductive layer and a second conductive layer. The... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070099310 - Reclaiming substrates having defects and contaminants: Test substrates used to test semiconductor fabrication tools are reclaimed by reading from a database the process steps performed on each test substrate and selecting a reclamation process from a plurality of reclamation processes. The reclamation process can include crystal lattice defect or metallic contaminant reduction treatments for reclaiming each... Agent: Janah & Associates, P.C.

20070099311 - Nanoscale wicking methods and devices: A fluid transport method and fluid transport device are disclosed. Nanoscale fibers disposed in a patterned configuration allow transport of a fluid in absence of an external power source. The device may include two or more fluid transport components having different fluid transport efficiencies. The components may be separated by... Agent: Alessandro Steinfl, Esq. C/o Ladas & Parry

20070099312 - Structure and method for parallel testing of dies on a semiconductor wafer: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a... Agent: Townsend And Townsend And Crew, LLP

20070099313 - Method of design based process control optimization: The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout database including a design rule set. At least one algorithm is employed to query the circuit layout database to calculate at least... Agent: Lsi Logic Corporation

20070099314 - Modeling device variations in integrated circuit design: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation... Agent: Courtney Staniford & Gregory LLP

20070099315 - Germanium photo detector having planar surface through germanium epitaxial overgrowth: A method of fabricating a germanium photo detector includes preparing a silicon substrate wafer and depositing and planarizing a silicon oxide layer on the silicon substrate. Contact holes are formed in the silicon oxide layer. An N+ epitaxial germanium layer is grown on the silicon oxide layer and in the... Agent: Robert D. Varitz

20070099316 - Led manufacturing process: An LED manufacturing process involves having a light emitting chip set in a preset loading pit on a carrier with an encapsulating material; conductive circuits with different electrodes being disposed of a substrate on the perimeter of the carrier; golden plated wire connecting the chip and the circuits; ;the carrier... Agent: Troxell Law Office PLLC

20070099319 - Light emitting diodes (leds) with improved light extraction by roughening: Systems and methods are disclosed for fabricating a semiconductor light emitting diode (LED) device by forming an n-gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.... Agent: Patterson & Sheridan, L.L.P.

20070099320 - Method for manufacturing gallium nitride compound semiconductor: An Al0.15Ga0.85N layer 2 is formed on a silicon substrate 1 in a striped or grid pattern. A GaN layer 3 is formed in regions A where the substrate 1 is exposed and in regions B which are defined above the layer 2. At this time, the GaN layer grows... Agent: Mcginn Intellectual Property Law Group, PLLC

20070099317 - Method for manufacturing vertical structure light emitting diode: A method for manufacturing a vertical light emitting diode of the invention allows an easier process of individually separating chips. A light emitting structure is formed on a growth substrate having a plurality of device areas and at least one device isolation area. The light emitting structure has an n-type... Agent: Mcdermott Will & Emery LLP

20070099318 - Mold for display device and method for manufacturing display device using the same: A method for manufacturing a display device, comprises; providing an insulating substrate; forming a passivation layer on the insulating substrate; arranging a mold including a supporting layer, a pattern forming layer provided on a first surface of the supporting layer and having concaves-convexes formed thereon and a buffer layer formed... Agent: Macpherson Kwok Chen & Heid LLP

20070099321 - Method for fabricating semiconductor laser device: A first intermediate body is fabricated on a semiconductor substrate. The first intermediate body includes a first lasing portion of a multi-layer stack and a metal adherent layer. A second intermediate body is fabricated on a support substrate. The second intermediate body includes a second lasing portion formed of a... Agent: Arent Fox PLLC

20070099322 - Control element of an organic electro-luminescent display and manufacturing process thereof: A control element of an organic electro-luminescent display includes a first transistor, a second transistor and a capacitor. The first gate electrode of the first transistor is electrically connected to a scan line, and the first source/drain electrode of the first transistor is electrically connected to a data line. The... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070099323 - Manufacturing method of display device and mold therefor: A method of manufacturing a display device in which a film deposited on a substrate through openings in a covering layer is easily removed from the covering layer. A master layer having a predetermined pattern of openings is formed on a base substrate exposing portions of the base substrate. A... Agent: Macpherson Kwok Chen & Heid LLP

20070099324 - Method of manufacturing an optical semiconductor element: A method of manufacturing an optical semiconductor element comprises: forming a striped protruding body by selectively dry etching an along its thickness, the InGaAIP layer being formed on a substrate; forming a protection film on an upper face and on both side faces of the protruding body; and forming a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070099325 - Light emitting diode device, manufacturing method of the light emitting diode device and mounting structure of the light emitting diode device: The embodiment of the present invention provides an LED device, a manufacturing method of the LED device and a mounting structure of the LED device. In order to manufacture the LED device with low manufacturing cost through simple process capable of overcoming thermal fatigue due to heat generation, breaking of... Agent: Birch Stewart Kolasch & Birch

20070099326 - Efuse and methods of manufacturing the same: In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numerous other aspects are provided.... Agent: James R. Nock IBM Corporation

20070099327 - Method for integrated mems packaging: An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070099329 - Method of fabricating a germanium photo detector on a high quality germanium epitaxial overgrowth layer: A method of fabricating a germanium photo detector includes preparing a silicon substrate; depositing and planarizing a silicon oxide layer; forming contact holes in the silicon oxide layer which communicate with the underlying silicon substrate; growing an epitaxial germanium layer of a first type on the silicon oxide layer and... Agent: Robert D. Varitz

20070099328 - Semiconductor device and interconnect structure and their respective fabricating methods: A semiconductor device is described, including a substrate, a transistor, a hard mask layer and an anti-reflection layer. The substrate includes a first area and a second area, wherein the second area includes a photosensing area. The transistor is disposed on the substrate in the first area and the hard... Agent: Jianq Chyun Intellectual Property Office

20070099330 - Low viscosity precursor compositions and methods for the deposition of conductive electronic features: A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low... Agent: Jaimes Sher, Esq. Cabot Corporation

20070099332 - Chalcogenide pvd components and methods of formation: A PVD component forming method includes identifying two or more solids having different compositions, homogeneously mixing particles of the solids using proportions which yield a bulk formula, consolidating the homogeneous particle mixture to obtain a rigid mass while applying pressure and using a temperature below the minimum temperature of melting... Agent: Wells St. John P.s.

20070099331 - Hydrazine-free solution deposition of chalcogenide films: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce... Agent: Connolly Bove Lodge & Hutz LLP

20070099333 - Thin-film transistor, method of producing thin-film transistor, electronic circuit, display, and electronic device: Aspects of the invention can provide a thin-film transistor having good transistor characteristics and operable with a low driving voltage, a method of producing such a thin-film transistor, a high-reliability electronic circuit, a display, and an electronic device. In an exemplary thin-film transistor according to the invention, a gate electrode... Agent: Oliff & Berridge, PLC

20070099338 - Capacitor with a dielectric including a self-organized monolayer of an organic compound: A capacitor is formed that includes a self-organized monolayer of an organic compound between two electrodes.... Agent: Edell, Shapiro & Finnan, LLC

20070099334 - Electron beam microprocessing method: Onto a surface of an AlxGayIn1-x-yAszP1-z (0≦x, y, z≦1) layer including GaAs alone or an InP substrate, an electron beam controlled to an arbitrary electron beam diameter and current density is irradiated so as to selectively substitute or generate Ga2O3 for a natural oxide layer formed on the AlxGayIn1-x-yAszP1-z, layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070099335 - On-chip igniter and method of manufacture: A chip for igniting nanoenergetic materials, includes a substrate, an igniter positioned on the substrate and the nanoenergetic material arranged in a linear pattern positioned on said substrate. A method of making a chip for igniting nanoenergetic materials includes providing a substrate, forming an igniter on the substrate and coating... Agent: Greer, Burns & Crain, Ltd.

20070099336 - Plasma etch process for defining catalyst pads on nanoemissive displays: A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing... Agent: Ingrassia Fisher & Lorenz, P.C.

20070099337 - Positive tone bi-layer imprint lithography method: The present invention provides a method to pattern a substrate which features creating a multi-layered structure by forming, on the substrate, a patterned layer having protrusions and recessions. Formed upon the patterned layer is a conformal layer, with the multi-layered structure having a crown surface facing away from the substrate.... Agent: Molecular Imprints

20070099339 - Fabrication method for a chip packaging structure: A fabrication method for a chip packaging structure disclosed herein is utilizing the method of plating metal to connect different layers so as to replace the traditional method that drill hole firstly and then plate metal in the hole. In the present invention, the metal in the conductive through hole... Agent: Rosenberg, Klein & Lee

20070099342 - Method and structure for an organic package with improved bga life: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.... Agent: Connolly Bove Lodge & Hutz LLP

20070099341 - Method of making stacked die package: A method of making a stacked die package (39) includes placing a first flip chip die (16) on a base carrier (12) and electrically connecting the first flip chip die (16) to the base carrier (12). A second flip chip die (18) is attached back-to-back to the first flip chip... Agent: Freescale Semiconductor, Inc. Law Department

20070099340 - Method of manufacturing flash memory cards: A method is disclosed for forming semiconductor packages by a process of punching and cutting the packages from a panel of integrated circuits. During an encapsulation process for encapsulating the packages in a molding compound, portions of the panel may be left free of molding compound. Portions of the panel... Agent: Vierra Magen/sandisk Corporation

20070099343 - Semiconductor package with redistributed pads: A method for fabricating a semiconductor package which includes coupling an electrode of a semiconductor device to a portion of a lead frame, overmolding at least a portion of the die, and then removing a portion of the die to obtain a desired thickness.... Agent: Ostrolenk Faber Gerb & Soffen

20070099344 - Ultrathin leadframe bga circuit package: A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while supporting leadframe fingers are positioned below the reference plane. Jumper wires are wirebonded between terminals on the die and the bond pads to... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070099345 - Method for producing through-contacts and a semiconductor component with through-contacts: A method is described for producing through-contacts through a panel-shaped composite body including semiconductor chips and a plastic mass filled with conductive particles. The panel-shaped composite body is introduced between two high-voltage point electrodes. The point electrodes are oriented at positions at which through-contacts are to be introduced through the... Agent: Edell, Shapiro & Finnan, LLC

20070099346 - Surface treatments for underfill control: Methods to reduce or eliminate the bleed out of underfill material. Surface treatments to selective areas on a chip carrier substrate surface create a non-wettable surface or a reduced wettability surface in the areas where the underfill should not flow. The substrate surface is subjected to surface treatments such as... Agent: International Business Machines Corporation Dept. 18g

20070099347 - Array of cells including a selection bipolar transistor and fabrication method thereof: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a... Agent: Seed Intellectual Property Law Group PLLC

20070099349 - Manufacturing method for magnetic sensor and lead frame therefor: A magnetic sensor is constituted using magnetic sensor chips mounted on stages supported by interconnecting members and a frame having leads in a lead frame. Herein, the stages are inclined upon plastic deformation of the interconnecting members. When the frame is held in a metal mold and the stages are... Agent: Dickstein Shapiro, LLP

20070099348 - Methods and apparatus for flip-chip-on-lead semiconductor package: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material... Agent: Daly, Crowley, Mofford & Durkee, LLP

20070099351 - Sensing system: A ChemFET Sensing system is Described.... Agent: Hewlett Packard Company

20070099350 - Structure and method of fabricating finfet with buried channel: A method of manufacturing a fin structure comprises forming a first structure of a first material type on a wafer and forming a buried channel of a second material adjacent sidewalls of the first structure. The second material type is different than the first material type. The structure includes a... Agent: Greenblum & Bernstein, P.L.C

20070099357 - Devices containing annealed stabilized silver nanoparticles: An electronic device including in any suitable sequence: a substrate; an optional insulating layer or an optional semiconductor layer, or both the optional insulating layer and the optional semiconductor layer; and an electrically conductive element of the electronic device, wherein the electrically conductive element comprises annealed silver-containing nanoparticles, wherein the... Agent: Patent Documentation Center

20070099354 - Fabricating method of a pixel structure: A method of fabricating a pixel structure is disclosed. A substrate having a color filter layer thereon and a leveling layer further covers the color filter layer is provided. A first metal layer is formed over the leveling layer. The first metal layer is patterned to define a source/drain. A... Agent: Jianq Chyun Intellectual Property Office

20070099356 - Flat panel display device and method of manufacturing the same: A flat panel display device of which a display unit is efficiently sealed and which has good flexibility, and a method of manufacturing the flat panel display. The flat panel display device includes a substrate, a display unit formed on the substrate, and a sealing part formed so as to... Agent: Stein, Mcewen & Bui, LLP

20070099352 - Method for annealing silicon thin films and polycrystalline silicon thin films prepared therefrom: Disclosed is a method for annealing a silicon thin film in a substrate in which an insulation layer and the silicon thin film are subsequently formed. The method includes heating or preheating the silicon thin film within a temperature range at which the substrate is not transformed during the process... Agent: Cantor Colburn, LLP

20070099353 - Method for forming a semiconductor structure and structure thereof: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity... Agent: Freescale Semiconductor, Inc. Law Department

20070099355 - Satellite and method of manufacturing a semiconductor film using the satellite: A method of manufacturing a semiconductor film including a setting a substrate on a satellite; and a forming an alloy semiconductor thin film containing at least two different group V elements or group IV elements on the substrate by metal organic chemical vapor deposition while supplying thermal energy to the... Agent: Leydig Voit & Mayer, Ltd

20070099358 - Method of measuring pattern shift in semiconductor device: Disclosed is a method of measuring a pattern shift in a semiconductor device. The method measures a mobility or shift distance of a stepped portion occurring between a buried layer surface and a substrate surface during an epitaxial process on the buried layer. The method includes the steps of: recognizing... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070099359 - Carrier multiplication in quantum-confined semiconductor materials: The present invention is directed to processes and devices for carrier multiplication using nanosized quantum confined semiconductor materials such as semiconductor nanocrystals.... Agent: Los Alamos National Security, LLC

20070099360 - Integrated circuits having strained channel field effect transistors and methods of making: An integrated circuit is provided that includes a substrate, a p-type field effect transistor, a compressive nitride layer, n-type field effect transistor, a tensile nitride layer, and a mask. The compressive nitride layer induces a first compressive stress in a channel region of the p-type field effect transistor. The tensile... Agent: International Business Machines Corporation Dept. 18g

20070099366 - Lanthanum aluminum oxide dielectric layer: Lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum aluminum oxide dielectric layer is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. Attn: David R. Cochran

20070099362 - Low resistance contact semiconductor device structure: A method for making a semiconductor device structure includes producing a substrate having formed thereon a gate with spacers, respective source and drain regions adjacent to the gate and an; disposing a first metallic layer on the gate with spacers, and the source and drain regions, disposing a second metallic... Agent: Joseph P. Abate IBM Corporation, Dept. 18g

20070099361 - Method for forming a semiconductor structure and structure thereof: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity... Agent: Freescale Semiconductor, Inc. Law Department

20070099364 - Method for manufacturing a semiconductor device having a polymetal gate electrode: A method for forming a semiconductor device having a polymetal gate electrode includes the steps of forming a gate oxide film on a silicon substrate, forming a polysilicon film and a tungsten film on the gate oxide film, patterning the polysilicon film and tungsten film, and thermally oxidizing the polysilicon... Agent: Young & Thompson

20070099363 - Method of manufacturing semiconductor device: There are provided steps of: forming a gate insulating film on a semiconductor substrate; sequentially forming a first gate electrode material film, a first insulating film, a second gate electrode material film, which is thinner than the first gate electrode material film, on the gate insulating film, and patterning these... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070099365 - Semiconductor device and method of fabricating the same: An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a... Agent: Volentine Francos, & Whitt PLLC

20070099367 - Enhancement of electron and hole mobilities in 110 si under biaxial compressive strain: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress... Agent: Scully, Scott, Murphy & Presser, P.C.

20070099371 - Cmos image sensor and manufacturing method thereof: A CMOS image sensor and a method for manufacturing the same are provided. The method can include: forming a device isolation layer on a device isolation region of a semiconductor substrate; forming photodiodes on photodiode regions of the semiconductor substrate; forming a salicide metal layer and a barrier metal layer... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070099372 - Device having active regions of different depths: An SOI device having SOI layers at two or more different depths below the surface of active regions of the device. Transistors for high-speed digital applications may be formed in the shallower active regions and RF power or high-voltage transistors may be formed in the deeper active regions. In one... Agent: Mendelsohn & Associates, P.C.

20070099368 - Field effect transistor and method for manufacturing the same: A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate... Agent: Ladas & Parry LLP

20070099369 - Integration scheme method and structure for transistors using strained silicon: A method for forming CMOS integrated circuits. The method forms a blanket layer of silicon dioxide overlying an entirety of the surface region of a first well region and a second well region provided on a semiconductor substrate. The blanket layer of silicon dioxide is overlying the hard mask on... Agent: Townsend And Townsend And Crew, LLP

20070099370 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, and forming a gate electrode comprising a metal semiconductor compound layer and having a predetermined gate length on the gate insulating film, the forming the gate electrode including forming a polycrystalline semiconductor film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070099373 - Method for manufacturing an integrated semiconductor transistor device with parasitic bipolar transistor: To attain a comparatively high breakdown voltage at a high avalanche strength and with the physical size simultaneously being as small as possible, the invention proposes constructing a transistor device in a semiconductor material region in which a first source/drain region is used as a source region and in which... Agent: Lerner Greenberg Stemer LLP

20070099374 - Bicmos device and method of manufacturing a bicmos device: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.... Agent: Sherr & Nourse, PLLC

20070099375 - Method for fabricating capacitor: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070099376 - Memory cell, pixel structure and fabrication process of memory cell: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region... Agent: Jianq Chyun Intellectual Property Office

20070099379 - Method of manufacturing a dielectric film in a capacitor: A method of manufacturing a dielectric layer for a capacitor including sequentially supplying and purging a first and a second precursor material for a first and a second predetermined amount of time, respectively, in an initial cycle, sequentially supplying and purging the first and the second precursor materials for a... Agent: Lee & Morse, P.C.

20070099380 - Methods of fabricating flash memory devices including substantially uniform tunnel oxide layers: A method of forming a flash memory device in a memory cell region of a substrate includes forming a first insulating layer on the substrate, forming a first conductive layer on the first insulating layer, forming trench isolation regions in the substrate extending through the first conductive layer and the... Agent: Myers Bigel Sibley & Sajovec

20070099378 - Semiconductor device having align key and method of fabricating the same: Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor... Agent: Marger Johnson & Mccollom, P.C.

20070099377 - Thermal isolation of phase change memory cells: A memory includes an array of memory cells, each memory cell including resistive material, a first insulation material laterally surrounding the resistive material of each memory cell, and a heat spreader between the memory cells to thermally isolate each memory cell.... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070099381 - Dual-gate device and method: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor... Agent: Macpherson Kwok Chen & Heid LLP

20070099382 - Method of forming source contact of nand flash memory: A method of forming a source contact of a NAND flash memory, including the steps of forming a tunnel oxide film on a semiconductor substrate, and then removing the tunnel oxide film in a region in which the source contact will be formed; sequentially forming a first polysilicon layer and... Agent: Marshall, Gerstein & Borun LLP

20070099383 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes etching a predetermined portion of a substrate to form a first recess having a bottom middle portion roundly projected and bottom edge portions tapered to have a micro-trench profile; and etching the substrate beneath the first recess to form a second recess,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070099384 - Method for fabricating semiconductor device having recess gate: A method for fabricating a semiconductor device having a recess gate includes forming a hard mask pattern on a substrate, etching the substrate using the hard mask pattern as an etch barrier to form a recess pattern, forming a passivation layer protecting surfaces of the recess pattern, etching a bottom... Agent: Blakely Sokoloff Taylor & Zafman

20070099385 - Method of manufacturing semiconductor device: The present invention provides a method of manufacturing a semiconductor device, comprising forming an electrode pattern made of silicon on a gate insulating film in an n-MOS region and a p-MOS region of a semiconductor substrate, masking the n-MOS region including the first electrode pattern with a first insulating film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070099386 - Integration scheme for high gain fet in standard cmos process: A method for fabricating high gain FETs that substantially reduces or eliminates unwanted variation in device characteristics caused by using a prior art shadow masking process is provided. The inventive method employs a blocking mask that at least partially extends over the gate region wherein after extension and halo implants... Agent: Scully, Scott, Murphy & Pressner

20070099387 - Method for fabricating semiconductor device: A method for forming a uniform doped region in a substrate having a non-uniform material layer thereon is provided. The non-uniform material layer is removed form the substrate. Thereafter, a treatment process is performed to form an offset material layer on a predetermined doped region of the substrate. Next, an... Agent: J C Patents, Inc.

20070099388 - Source/drain extensions having highly activated and extremely abrupt junctions: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed.... Agent: Texas Instruments Incorporated

20070099389 - Capacitor layout technique for reduction of fixed pattern noise in a cmos sensor: A new capacitor architecture includes a front plate of the capacitor formed from a first polysilicon layer. The front plate is surrounded by a first dielectric layer and a second dielectric layer. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which... Agent: Dickstein Shapiro LLP

20070099390 - Vertical mim capacitors and method of fabricating the same: A method of fabricating a vertical MIM capacitor. An insulation layer is formed on the substrate. The insulation layer is patterned to form an opening in a predetermined area of a core electrode. Then, the opening is filled to form a sacrificial plug. Subsequently, the insulation layer is patterned to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070099392 - Fusion bonding process and structure for fabricating silicon-on-insulator (soi) semiconductor devices: A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 200 angstrom thick oxide layer thereover; etching the first semiconductor wafer to raise a pattern therein; doping the raised pattern of the first semiconductor wafer through the about 200 angstrom thick oxide layer; providing... Agent: Plevy & Howard & Darcy P.C.

20070099391 - Methods for forming semiconductor structures with buried isolation collars and semiconductor structures formed by these methods: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region... Agent: James R. Nock IBM Corporation, Dept. 917

20070099393 - Method of manufacturing isolation layer pattern in a semiconductor device and isolation layer pattern using the same: Disclosed is a method of manufacturing an isolation layer pattern in a semiconductor device and an isolation layer pattern in a semiconductor device. A device at a low voltage device formation region may be substantially immune to electric fields from a high voltage device formation region. A field insulation film... Agent: Sherr & Nourse, PLLC

20070099394 - Semiconductor device and manufacturing method thereof: A semiconductor device, has a semiconductor substrate; a first insulating film which is disposed above the semiconductor substrate; a second insulating film which is disposed above the first insulating film; a wiring which is disposed in the first insulating film and has a plug connecting part; a plug which is... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070099396 - Method of forming pattern, film structure, electrooptical device and electronic equipment: A method of forming a pattern includes forming mark partition walls that correspond to an alignment mark on a substrate before forming the pattern by providing a pattern forming material between partition walls, and providing a liquid material containing an alignment mark forming material between the mark partition walls.... Agent: Harness, Dickey & Pierce, P.L.C

20070099397 - Microfeature dies with porous regions, and associated methods and systems: Microfeature dies with porous regions, and associated methods and systems are disclosed. A method in accordance with one embodiment of the invention includes forming a porous region between a die and a remainder portion of a microfeature workpiece, and separating the die from the remainder portion by removing at least... Agent: Perkins Coie LLP Patent-sea

20070099395 - Wafer level packaging process: Wafer level packaging process for packaging MEMS or other devices. In some embodiments, a MEMS wafer with normal thickness is firstly bonded to a cap wafer of normal thickness, followed by a thinning on the backside of the MEMS wafer. After this, the bonded wafer stack and the capping of... Agent: Blakely Sokoloff Taylor & Zafman

20070099398 - Method and system for forming a nitrided germanium-containing layer using plasma processing: A method and system for forming a nitrided germanium-containing layer by plasma processing. The method includes providing a germanium-containing substrate in a process chamber, generating a plasma from a process gas containing N2 and a noble gas, where the plasma conditions are selected effective to form plasma excited N2 species... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070099399 - Relaxation of layers: The invention relates to a method of forming a layer of elastically unstrained crystalline material intended for electronics, optics, or optronics applications, wherein the method is carried out using a structure that includes a first crystalline layer which is elastically strained under tension (or respectively in compression) and a second... Agent: Winston & Strawn LLP Patent Department

20070099400 - Semiconductor circuit and method of fabricating the same: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high... Agent: Eric Robinson

20070099401 - Laser irradiating device, laser irradiating method and manufacturing method of semiconductor device: An object of the present invention is to provide a method and a device for constantly setting the energy distribution of a laser beam on an irradiating face, and uniformly irradiating the laser beam to the entire irradiating face. Further, another object of the present invention is to provide a... Agent: Eric Robinson

20070099402 - Method for fabricating reliable semiconductor structure: A reliable semiconductor structure and its fabrication method. Active regions and/or scribe lines on a semiconductor substrate are configured along a crack resistant crystalline direction. Thermal cracking due to the abrupt temperature ramp of rapid thermal processing can be avoided.... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070099403 - Plasma composition for selective high-k etch: A method for the selective removal of a high-k layer such as HfO2 over silicon or silicon dioxide is provided. More specifically, a method for etching high-k selectively over silicon and silicon dioxide and a plasma composition for performing the selective etch process is provided. Using a BCl3 plasma with... Agent: Knobbe Martens Olson & Bear LLP

20070099404 - Implant and anneal amorphization process: A method for improving a microelectronic device interface with an ultra-fast anneal process at an intermediate temperature that may be lower than those used in a dopant activation process. In one embodiment, a partial recrystalization of an amorphous silicon layer in the source drain region that is the precursor to... Agent: Blakely Sokoloff Taylor & Zafman

20070099405 - Methods for fabricating multi-terminal phase change devices: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created... Agent: Thelen Reid Brown Raysman & Steiner LLP

20070099406 - Semiconductor device manufacturing method: In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently, when the metal film is processed, part of the metal film is removed by a wet etching process using a given chemical liquid.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070099408 - Forming of silicide areas in a semiconductor device: An embodiment of a method for forming silicide areas of different thicknesses in a device comprising first and second silicon areas, comprising the steps of: implanting antimony or aluminum in the upper portion of the first silicon areas; covering the silicon areas with a metallic material; and heating the device... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20070099407 - Method for fabricating a transistor using a low temperature spike anneal: A method for making a transistor 20 that includes performing a low temperature spike anneal 314. The method also includes performing a silicide anneal 318 to fully silicide the gate electrode 90 of the transistor 20. A blocking layer 120 protects the source and drain regions 60 of the transistor... Agent: Texas Instruments Incorporated

20070099409 - Semiconductor device and method of manufacturing the same: A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070099410 - Hard intermetallic bonding of wafers for mems applications: A method of bonding two substrates in MEMS applications includes depositing a first metal in a bonding area on a first substrate, depositing a second metal, which is different from the first metal, in a bonding area on a second substrate, place the first substrate and the second substrate together... Agent: Mcdermott Will & Emery LLP

20070099411 - Reflow apparatus, a reflow method, and a manufacturing method of semiconductor device: A reflow apparatus, where formic acid is used for cleaning a surface of a solder electrode on a processing target, is disclosed. The reflow apparatus includes a processing chamber, a formic acid introduction mechanism for supplying an atmosphere gas containing formic acid to the processing chamber, and a shielding member... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070099412 - Soldering method for mounting semiconductor device on wiring board to ensure invariable gap therebetween, and soldering apparatus therefor: In a soldering method for mounting a semiconductor device on a wiring board, a plurality of solid-phase solders s are provided between the semiconductor device and the wiring board, and are thermally melted to thereby produce a plurality of liquid-phase solders therebetween. A constant force is exerted on the liquid-phase... Agent: Mcginn Intellectual Property Law Group, PLLC

20070099413 - Method for forming multi-layer bumps on a substrate: A method for forming multi-layer bumps on a substrate includes depositing a first metal powder on the substrate, and selectively melting or reflowing a portion of the first metal powder to form first bumps. A second metal powder is then deposited on the first bumps, and melted to form second... Agent: Freescale Semiconductor, Inc. Law Department

20070099414 - Semiconductor device comprising a contact structure based on copper and tungsten: By providing contact plugs having a lower plug portion, formed on the basis of well-established tungsten-based technologies, and an upper plug portion, which may comprise a highly conductive material such as copper or a copper alloy, a significant increase in conductivity of the contact structure may be achieved. For this... Agent: Williams, Morgan & Amerson

20070099415 - Integration process of tungsten atomic layer deposition for metallization application: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes positioning a substrate having an underlying tungsten layer within a process chamber and depositing a tungsten-containing barrier layer on the underlying tungsten layer during a cyclical layer deposition process. The tungsten-containing barrier layer... Agent: Patent Counsel Applied Materials, Inc.

20070099416 - Shrinking contact apertures through lpd oxide: Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The... Agent: International Business Machines Corporation Dept. 18g

20070099417 - Adhesion and minimizing oxidation on electroless co alloy films for integration with low k inter-metal dielectric and etch stop: A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon... Agent: Patterson & Sheridan, LLP

20070099418 - Resin plating method with added heat-treating process: A resin plating method for a resin molding is disclosed which involves a simple process as an additional process in resin plating to suppress the occurrence of such an undesirable phenomenon as a metal plating film peeling together with a thin resin film due to floating of a thin surface... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070099419 - Methods for forming semiconductor devices including thermal processing: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer... Agent: Myers Bigel Sibley & Sajovec

20070099420 - Direct tailoring of the composition and density of ald films: A method comprising introducing an organometallic precursor according to a first set of conditions in the presence of a substrate; introducing the organometallic precursor according to a different second set of conditions in the presence of the substrate; and forming a layer comprising a moiety of the organometallic precursor on... Agent: Blakely Sokoloff Taylor & Zafman

20070099421 - Methods for forming cobalt layers including introducing vaporized cobalt precursors and methods for manufacturing semiconductor devices using the same: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C≡C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate... Agent: Myers Bigel Sibley & Sajovec

20070099422 - Process for electroless copper deposition: Embodiments of the invention provide a method for depositing a copper material on a substrate by an electroless deposition process and also provide a composition of an electroless deposition solution. In one embodiment, the copper material is deposited from an electroless copper solution that contains an additive, such as an... Agent: Patterson & Sheridan, LLP

20070099425 - Method for etching non-conductive substrate surfaces: An etching composition for non-conductive substrates such as polyester, polyether, polyimide, polyurethane, epoxy resin, polysulfone, polyethersulfone, polyetherimide, and polyamide, comprising a halogenide and/or nitrate of a metal selected from the group consisting of Na, Mg, Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ca, Zn, and combinations... Agent: Senniger Powers

20070099423 - Method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process and etching method: A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing... Agent: North America Intellectual Property Corporation

20070099424 - Reduction of mechanical stress on pattern specific geometries during etch using double pattern layout and process approach: According to various embodiments, methods to eliminate high stress areas in a mask during a gate trim etch are provided. High stress areas can include, for example, gate regions that are anchored at only one end. The exemplary methods can include the use of a double pattern layout, for example,... Agent: Texas Instruments Incorporated

20070099426 - Polishing method, polishing apparatus, and electrolytic polishing apparatus: A polishing method polishes a substrate so as to remove an interconnect metal film and a barrier film formed on portions other than interconnect recesses. The method includes performing a first polishing process of polishing a surface of the substrate After performing the first polishing process, the surface of the... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070099427 - Method for preparing of cerium oxide powder for chemical mechanical polishing and method for preparing of chemical mechanical polishing slurry using the same: The present invention relates to a method of preparing a cerium oxide powder for a CMP slurry and a method of preparing a CMP slurry using the same, and more particularly, to a method of preparing a cerium oxide powder for a CMP slurry and a method of preparing a... Agent: Mckenna Long & Aldridge LLP

20070099428 - Plasma for patterning advanced gate stacks: A plasma composition and its use in a method for the dry etching of a stack of at least one material chemically too reactive towards the use of a Cl-based plasma are provided. Small amounts of nitrogen (5% up to 10%) can be added to a BCl3 comprising plasma and... Agent: Knobbe Martens Olson & Bear LLP

20070099429 - Post exposure resist bake: A preferred embodiment of the invention provides a method for forming an integrated circuit. The method comprises forming a resist layer on a substrate. Preferably, the photoresist layer comprises a photo acid generator (PAG). Embodiments include irradiating the resist through a mask to generate a photoacid in the resist, heating... Agent: Slater & Matsil LLP

20070099430 - Method for manufacturing a semiconductor component: A method for manufacturing a semiconductor component using a sacrificial masking structure. A semiconductor device is formed from a semiconductor substrate and a layer of dielectric material is formed over the semiconductor substrate and the semiconductor device. The layer of dielectric material may be formed directly on the semiconductor substrate... Agent: Farjami & Farjami LLP

20070099431 - Process for increasing feature density during the manufacture of a semiconductor device: A method used during the manufacture of a semiconductor device comprises the formation of a first patterned layer having individual features of a first density. Through the formation and etching of various layers, for example conformal layers and a spun-on layer, a second patterned layer results which comprises individual features... Agent: Kevin D. Martin Micron Technology, Inc.

20070099432 - Method for photolithography in semiconductor manufacturing: The present disclosure relates generally to the manufacturing of semiconductor devices. In one example, a method for forming a portion of a semiconductor device includes forming a photo sensitive layer over a substrate, developing the photo sensitive layer to expose a portion of the substrate and to create a seed... Agent: Haynes And Boone, LLP

20070099433 - Gas dielectric structure formation using radiation: Methods and resulting structure of forming a gas dielectric structure in an interconnect structure are disclosed. In one embodiment, the method includes providing the interconnect structure including at least one interconnect layer having a dielectric, at least one conductor and a first cap layer; and causing the dielectric to contract... Agent: Hoffman, Warnick & D'alessandro LLC

20070099434 - Method of forming oxide film of semiconductor device: An oxide film is formed by a radical oxidization process and nitrogen is introduced into the oxide film by an annealing process using NO gas. The nitrogen gathered at the interface of the oxide film and a semiconductor substrate is re-distributed by an annealing process using a mixed gas including... Agent: Townsend And Townsend And Crew, LLP

20070099435 - Method and system for forming a nitrided germanium-containing layer using plasma processing: A method and system for forming a nitrided germanium-containing layer by plasma processing. The method includes providing a germanium-containing substrate in a process chamber, generating a plasma from a process gas containing N2 and a noble gas, where the plasma conditions are selected effective to form plasma excited N2 species... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070099436 - Method of producing silicon oxide, negative electrode active material for lithium ion secondary battery and lithium ion secondary battery using the same: A method for producing a silicon oxide including the steps of supplying silicon atoms onto a substrate through an oxygen atmosphere to form a silicon oxide layer on the substrate, and separating the silicon oxide layer from the substrate and pulverizing the separated silicon oxide layer to obtain silicon oxide... Agent: Mcdermott Will & Emery LLP

20070099437 - Power module having at least two substrates: The invention relates to a power module 3 and a method for producing it. The power module 3 has a first substrate 1 having power semiconductor chips 4, and a second substrate 2 populated with signal semiconductor chips 5. The substrates 1 and 2 are oriented parallel one above the... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070099438 - Thin film deposition: A system, method and apparatus is capable of producing layers of various materials stacked on one another on a substrate without exposing the substrate to the pressure and contaminants of ambient air until the stack is complete. In one aspect, the stack of layers can include both an insulative layer... Agent: Applied Materials, Inc.

20070099439 - Arrangement and method for forming one or more separated scores in a surface of a substrate: The present invention is directed to an arrangement for forming one or more separated scores in a surface of a substrate. The arrangement comprises a laser for providing a laser beam, optical guiding means for guiding said laser beam to said surface of said substrate, means for moving said substrate... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070099440 - Method for manufacturing semiconductor device, semiconductor device, and laser irradiation apparatus: [Object]It is an object of the present invention to provide a laser irradiation apparatus being able to crystallize the semiconductor film homogeneously while suppressing the variation of the crystallinity in the semiconductor film and the unevenness of the state of the surface thereof. It is another object of the present... Agent: Nixon Peabody, LLP

20070099441 - Carbon nanotube with zno asperities: A ZnO asperity-covered carbon nanotube (CNT) device has been provided, along with a corresponding fabrication method. The method comprises: forming a substrate; growing CNTs from the substrate; conformally coating the CNTs with ZnO; annealing the ZnO-coated CNTs; and, forming ZnO asperities on the surface of the CNTs in response to... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski