Semiconductor device manufacturing: process inventions 04/07

20070092979 - Production method for polarization inversion unit: It is provided a novel method of producing polarization inversion parts by electric field polling process wherein the polarization inversion part extends to a deeper point from the surface of a substrate. The polarization inversion part is produced by electric field polling process using a comb electrode having a plurality... Agent: Burr & Brown

20070092980 - Method of fabricating gan: A method of fabricating a thick GaN layer includes forming a porous GaN layer having a thickness of 10-1000 nm by etching a GaN substrate in a reaction chamber in an HCl and NH3 gas atmosphere and forming an in-situ GaN growth layer in the reaction chamber. The method of... Agent: Stein, Mcewen & Bui, LLP

20070092981 - Display apparatus and fabricating method thereof: A display apparatus and method of forming the same comprise an insulating substrate; a thin film transistor formed on the insulating substrate; a first electrode electrically connected to the thin film transistor and having a first maximum roughness; a buffer layer formed on the first electrode and having a second... Agent: Cantor Colburn, LLP

20070092982 - Method of fabricating flexible micro-capacitive ultrasonic transducer by the use of imprinting and transfer printing techniques: A method of fabricating flexible micro-capacitive ultrasonic transducer by the use of imprinting and transfer printing techniques is disclosed, which mainly comprises the steps of: forming oscillation cavities by imprinting; forming fixed electrodes by transfer printing; forming oscillation films by transfer printing; forming driving electrodes by transfer printing; and so... Agent: Bruce H. Troxell

20070092983 - Process of forming a microphone using support member: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate... Agent: Bromberg & Sunstein LLP

20070092984 - Cmos image sensor and method for fabricating the same: An image sensor includes a semiconductor substrate; a pixel array disposed on the semiconductor substrate; and an insulating interlayer, formed on the semiconductor substrate, having a trench coinciding with the disposition of the pixel array, the trench having uniformly inclined inner sidewalls.... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070092985 - Solid-state imaging device and method of manufacturing the same: A solid-state imaging device includes a pixel formation region 4 and a peripheral circuit formation region 20 formed in the same semiconductor substrate; in the peripheral circuit formation region 20 a first element isolation portion is formed of an element isolation layer 21 in which an insulation layer is buried... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20070092986 - Method for fabricating cmos image sensor: This invention provides a CMOS image sensor having a pinned photodiode. A P substrate is provided having thereon a P well. The P well is adjacent to a light-sensing region of the CMOS image sensor. A gate electrode of a transfer transistor of the CMOS image sensor is formed on... Agent: North America Intellectual Property Corporation

20070092987 - Conductive electrode powder, a method for preparing the same, a method for preparing an electrode of a plasma display panel by using the same, and a plasma display panel comprising the same: The present invention provides a conductive electrode powder which includes electroconductive metal particles, and an inorganic oxide coating layer covering the surface of the electroconductive metal particles. By using a conductive electrode powder, the corrosion, the ionization, the migration such as ionization, and yellowing of the electrode such as colloidalization... Agent: Robert E. Bushnell

20070092989 - Conductive nanoparticles: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070092988 - Method for producing organic solar cells or photo detectors: The invention relates to a method for the production of organic solar cells or photo detectors, especially based on organic polymers. Said method comprises the following steps: a first organic n or p conducting semi-conductor layer is applied to an electrode, a second organic semi-conductor layer having other corresponding conductive... Agent: Fish & Richardson PC

20070092990 - Field effect transistors (fets) with inverted source/drain metallic contacts, and method of fabricating same: The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a... Agent: Scully Scott Murphy & Presser, PC

20070092991 - Method for manufacturing a semiconductor device: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame... Agent: Texas Instruments Incorporated

20070092994 - Method of manufacturing semiconductor device and a semiconductor device: The present invention provides a method of manufacturing a semiconductor device which comprises an upper and a lower film each having a wire, and a plurality of pellets each mounted on each of the upper and lower films, where the upper and lower films are electrically connected to each other.... Agent: Young & Thompson

20070092992 - Semiconductor component and method for production of a semiconductor component: A semiconductor substrate, a semiconductor chip and a semiconductor component with areas composed of a stressed monocrystalline material, and a method for production of a semiconductor component is disclosed. In one embodiment, the semiconductor chip includes relatively thick stressed layers achieving reduced switching times. For this purpose, the semiconductor substrate... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070092993 - Semiconductor device packaging for avoiding metal contamination: A semiconductor device manufacture method includes: bonding a main device surface of a semiconductor chip onto a package tape with adhesive material; and subjecting the semiconductor chip and the package tape to baking to cure the adhesive material. The baking of the semiconductor chip and the package tape is accompanied... Agent: Mcginn Intellectual Property Law Group, PLLC

20070092996 - Method of making semiconductor package with reduced moisture sensitivity: A method of making a semiconductor package (10) includes placing an integrated circuit (IC) die (12) on a first side (14) of a substrate (16) and electrically connecting the IC die (12) to the first side (14) of the substrate (16). First solder balls (22) are attached to a second... Agent: Freescale Semiconductor, Inc. Law Department

20070092995 - Microelectronics grade metal substrate, related metal-embedded devices and methods for fabricating same: Fabricating a microelectronics grade metal substrate comprises forming the metal substrate on a sacrificial substrate. An adhesion layer can be deposited on or over the surface of the sacrificial substrate. A seed layer of the metal can be deposited on or over the adhesion layer. The metal material can be... Agent: Lathrop & Clark LLP

20070092997 - Fabrication method of non-volatile memory: A method of fabrication a non-volatile memory is provided. A stacked structure is formed on a substrate, the stacked structure including a gate dielectric layer and a control gate. Then, a first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed on the top and... Agent: Jianq Chyun Intellectual Property Office

20070092998 - Semiconductor heat-transfer method: A semiconductor heat-transfer method includes the steps of (a) treating a high conductivity metal substrate through an electrolytic oxidation process to have an oxidized insulation layer be covered on the surface of the high conductivity metal substrate, (b) covering a metal conducting layer on the oxidized insulation layer at selected... Agent: Rosenberg, Klein & Lee

20070092999 - Method for evaluating and modifying solder attach design for integrated circuit packaging assembly: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is... Agent: Texas Instruments Incorporated

20070093000 - Pre-molded leadframe and method therefor: A method of manufacturing a pre-molded leadframe for use in a semiconductor package includes providing a leadframe having a die pad and a plurality of terminal leads. A first molding material is formed in the leadframe to expose the upper surface of the die pad and the upper surfaces of... Agent: Ishimaru & Zahrt LLP

20070093001 - Encapsulating electrical connections: An electrical connection is encapsulated by dispensing an encapsulant on a first side of the electrical connection only, and directing the encapsulant to a second side of the electrical connection from the first side, where the second side generally faces opposite the first side.... Agent: Hewlett Packard Company

20070093002 - Electric appliance, semiconductor device, and method for manufacturing the same: In the present circumstances, a film formation method of using spin coating in a manufacturing process is heavily used. As increasing the substrate size in future, the film formation method of using spin coating becomes at a disadvantage in mass production since a mechanism for rotating a large substrate becomes... Agent: Nixon Peabody, LLP

20070093003 - Method for fabricating thin film transistors: A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor... Agent: Jianq Chyun Intellectual Property Office

20070093004 - Method of manufacturing thin film transistor including zno thin layer: Provided is a method of manufacturing a thin film transistor (TFT) including a transparent ZnO thin layer that is formed at a low temperature by causing a surface chemical reaction between precursors containing elements constituting the ZnO thin layer. The method includes the steps of: depositing a gate metal layer... Agent: Mayer, Brown, Rowe & Maw LLP

20070093005 - Thin film transistor panel and method of manufacture: A thin film transistor array panel includes a pixel electrode formed on a substrate, a gate line formed on the pixel electrode, a gate insulating film formed on the gate line, a semiconductor formed on the gate insulating film, a data line and a drain electrode formed on the gate... Agent: Macpherson Kwok Chen & Heid LLP

20070093006 - Technique for preparing precursor films and compound layers for thin film solar cell fabrication and apparatus corresponding thereto: The present invention advantageously provides for, in different embodiments, improved contact layers or nucleation layers over which precursors and Group IBIIIAVIA compound thin films adhere well and form high quality layers with excellent micro-scale compositional uniformity. It also provides methods to form precursor stack layers, by wet deposition techniques such... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070093007 - Active matrix pixel device with photo sensor: An active matrix pixel device is provided, for example an electroluminescent display device, the device comprising circuitry supported by a substrate and including a polysilicon TFT (10) and an amorphous silicon thin film PIN diode (12). Polysilicon islands are formed before an amorphous silicon layer is deposited for the PIN... Agent: Philips Intellectual Property & Standards

20070093008 - Mos varactor property detection method and mos varactor manufacturing method using the same: Disclosed is a method for detecting properties of a Metal Oxide Silicon (MOS) varactor, which includes: establishing a MOS varactor model equation in conjunction with an area of a gate; calculating values of the coefficients of the MOS varactor model equation through measurements for test materials; and extracting the properties... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070093009 - Semiconductor device with vertical electron injection and its manufacturing method: A method for making a semiconductor device with vertical electron injection, including: transferring a monocrystalline thin film onto a first face of a support substrate; producing at least one electronic component from the monocrystalline thin film; forming at least one recess in a second face of the substrate to enable... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070093010 - Method of making an inverted-t channel transistor: A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of... Agent: Freescale Semiconductor, Inc. Law Department

20070093012 - Method for fabricating a gate dielectric of a field effect transistor: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070093013 - Method for fabricating a gate dielectric of a field effect transistor: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric... Agent: Patterson & Sheridan, LLP

20070093011 - Method of fabricating gate dielectric layer and method of fabricating semiconductor device: A method of fabricating a gate dielectric layer is described. First, a well is produced in a substrate. Later, the substrate is cleaned. Then the substrate is processed by a pre-annealed process. Afterwards, a gate dielectric layer is formed on the substrate. As a result, the on-current of the semiconductor... Agent: Jianq Chyun Intellectual Property Office

20070093016 - Formation of standard voltage threshold and low voltage threshold mosfet devices: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second... Agent: Dinsmore & Shohl LLP

20070093017 - Formation of standard voltage threshold and low voltage threshold mosfet devices: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second... Agent: Dinsmore & Shohl LLP

20070093014 - Method for preventing doped boron in a dielectric layer from diffusing into a substrate: The present invention provides a method for preventing doped boron in a dielectric layer from diffusing into a substrate. First, at least one gate is formed on a periphery circuit area and a memory array area of a substrate, respectively, wherein the pattern density in the memory array area is... Agent: Birch Stewart Kolasch & Birch

20070093015 - Semiconductor device and method for fabricating the same: A semiconductor device includes a first field-effect transistor including a first gate electrode and a second field-effect transistor including a second gate electrode. The first gate electrode and the second gate electrode are integrated using a connecting portion and are fully silicided with a metal in such a manner that... Agent: Mcdermott Will & Emery LLP

20070093018 - Dielectric material forming methods and enhanced dielectric materials: A dielectric material forming method includes forming a first monolayer and forming a second monolayer on the first monolayer, one of the first and second monolayers comprising tantalum and oxygen and the other of the first and second monolayers comprising oxygen and another element different from tantalum. A dielectric layer... Agent: Wells St. John P.s.

20070093019 - Method for producing a connection electrode for two semiconductor zones arranged one above another: Method for producing a connection electrode for two semiconductor zones arranged one above another The invention relates to a method for producing a connection electrode for a first semiconductor zone and a second semiconductor zone, which are arranged one above another and are doped complementarily with respect to one another,... Agent: Maginot, Moore & Beck Chase Tower

20070093020 - Methods of forming non-volatile memory devices and devices formed thereby: Methods of forming non-volatile memory devices include steps to define features that enhance shielding of electronic interference between adjacent floating gate electrodes and improve leakage current and threshold voltage characteristics. These features also support improved leakage current and threshold voltage characteristics in string selection transistors that are coupled to non-volatile... Agent: Myers Bigel Sibley & Sajovec

20070093021 - Mos transistor with recessed gate and method of fabricating the same: A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at... Agent: Marger Johnson & Mccollom, P.C.

20070093022 - Integrated circuitry: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is... Agent: Wells St. John P.s.

20070093025 - Etch stop layer in poly-metal structures: In accordance with one embodiment of the present invention, a method of interfacing a poly-metal structure and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the structure. The present invention also addresses the relative location of the etch stop layer in... Agent: Dinsmore & Shohl LLP

20070093023 - Non-volatile memory and fabricating method thereof: A non-volatile memory. The non-volatile memory comprises a substrate, a conductive layer, a charge storage layer, several first doped regions and several second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is located over the substrate, wherein the conductive layer fills in the trenches.... Agent: J.c. Patents, Inc. Suite 250

20070093024 - Split gate flash memory cell and fabrication method thereof: A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the... Agent: Birch Stewart Kolasch & Birch

20070093026 - Method of making thin silicon sheets for solar cells: A thin layer of single-crystal silicon is produced by forming first trenches in a silicon substrate having (111) orientation; forming narrower second trenches at the base of the trenches; anisotropically etching lateral channels (4) from the second trenches, until adjacent etch fonts (16) substantially meet; and detaching said layer from... Agent: Woodcock Washburn LLP

20070093027 - Semiconductor integrated circuit and fabrication process thereof: A semiconductor integrated circuit that includes thereon a flash memory and a plurality of MOS transistors using different power supply voltages is formed by a process in which a thermal oxidation process is applied to one of the device regions while covering the other device regions by an oxidation-resistant film.... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070093028 - Graded junction high voltage semiconductor device: A graded junction space decreasing an implant concentration gradient between n-well and p-well regions of a semiconductor device is provided for enhancing breakdown voltage in high voltage applications. Split or unified FOX regions may be provided overlapping with the graded junction space. By using a p-well blocking layer to separate... Agent: Merchant & Gould PC

20070093029 - Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods: A method of generating a layout of one or more planar double gate transistors can include generating a single gate transistor layout at least in part from one or more double gate transistor circuits, logic diagrams, or any combination thereof, and generating the planar double gate transistor layout at least... Agent: Larson Newman Abel Polansky & White, LLP

20070093030 - Reduction of boron diffusivity in pfets: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify... Agent: Whitham, Curtis & Christofferson, P.C.

20070093032 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070093031 - Methods of removing photoresist and fabricating semiconductor devices: A method for increasing the removal rate of a photoresist layer used as an ion implant mask. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the... Agent: Jianq Chyun Intellectual Property Office

20070093033 - Ultra shallow junction formation by solid phase diffusion: An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode,... Agent: Tung & Associates Suite 120

20070093034 - Methods of forming semiconductor constructions: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein... Agent: Wells St. John P.s.

20070093035 - Circuit board materials with improved bond to conductive metals and methods of the manufacture thereof: Use of a roughened dielectric layer between a dielectric substrate and a conductive layer, which allows increased adhesion between layers without the conductor loss associated with roughened conductor layers, as well as improved accuracy in etching. The method is widely applicable to a variety of dielectric substrate and conductive layer... Agent: Cantor Colburn, LLP

20070093036 - Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon... Agent: James R. Nock IBM Corporation, Dept. 917

20070093037 - Vertical structure semiconductor devices and method of fabricating the same: The present invention provides a vertical structure semiconductor device and method of fabricating the same. The method comprises providing a sapphire substrate bonded to a bottom surface of a semiconductor wafer, and a metal coated to the top surface of the semiconductor wafer. The method also comprises securely bonding a... Agent: Patent Docket Administrator Lowenstein Sandler PC

20070093038 - Method for making microchips and microchip made according to this method: Microchips have a first surface and a second surface, which second surface is opposite the first surface. Microelectronic structures are fabricated at the first surface. At least two layers of lacquer are deposited on the second surface of the microchip; however, any two contiguous layers have different mechanical properties.... Agent: Slater & Matsil LLP

20070093040 - Production method for device: A production method for devices includes: a bonding process for placing circuit surfaces of other divided plural semiconductor chips onto circuit surfaces of semiconductor chips of a wafer and bonding the other semiconductor chips to the semiconductor chips of the wafer; and a semiconductor chip grinding process for grinding rear... Agent: Brinks Hofer Gilson & Lione

20070093039 - Tools and methods for disuniting semiconductor wafers: A tool and method for disuniting two wafers, wherein at least one of the wafers is used in fabricating substrates for microelectronics, optoelectronics, or optics. The method includes the steps of temporarily affixing two gripper members to respective opposite faces of the wafers; and sufficiently displacing one of the gripper... Agent: Winston & Strawn LLP Patent Department

20070093041 - Compound semiconductor device and method of manufacturing the same: A method of manufacturing a compound semiconductor device comprises forming a scribed groove extending from an edge of a major surface of a laminated body to an internal region on the first major surface. The laminated body has the first major surface and a second major surface and is formed... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070093042 - Bit line implant: A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures... Agent: Harrity Snyder, L.L.P.

20070093043 - Semiconductor structure with reduced gate doping and methods for forming thereof: A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a... Agent: Freescale Semiconductor, Inc. Law Department

20070093044 - Method of depositing a metal layer onto a substrate and a method for measuring in three dimensions the topographical features of a substrate: A method of coating a substrate is disclosed in which a gas is activated using an electron beam. The coated substrate is then sliced using a particle beam to reveal, in cross-section, features of the resist. Those features of the resist are measured using a scanning electron microscope and a... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070093046 - Cmosfet with hybrid-strained channels: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from... Agent: Haynes And Boone, LLP

20070093045 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to manufacture a micromachine having a plurality of structural bodies with different functions and to shorten the time required for sacrifice layer etching in a process of manufacturing the micromachine. Another object of the present invention is to prevent a structural layer... Agent: Fish & Richardson P.C.

20070093047 - Semiconductor device and method for fabricating the same: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions.... Agent: Mcdermott Will & Emery LLP

20070093048 - Method for forming metal line of semiconductor device: A method for forming a metal line of a semiconductor device uses a low dielectric constant material as an interlayer dielectric layer and treats a surface of the interlayer dielectric layer with plasma to prevent moisture and ammonia from being adsorbed in the low dielectric constant material. The method for... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070093049 - Electronic interconnects and methods of making same: A method for making an interconnect is provided. The method includes depositing a conductive layer on a substrate, depositing a protective layer on the conductive layer, patterning the protective layer to form openings to the conductive layer, depositing contact pads on the conductive layer through the openings in the protective... Agent: Patrick S. Yoder Fletcher Yoder

20070093050 - Interconnection structures for semiconductor devices and methods of forming the same: An interconnection structure includes an inter-level insulation layer disposed on a semiconductor substrate. First contact structures are formed in the inter-level insulation layer. Second contact structures are formed in the inter-level insulation layer and are spaced apart from the first contact structures. First spacers are disposed between the first contact... Agent: Myers Bigel Sibley & Sajovec

20070093051 - Laminated structure, piezoelectric actuator and method of manufacturing the same: A laminated structure having an electrode hard to peel off and a method of manufacturing the laminated structure. The laminated structure has: a backing substrate; a lower electrode including an adhesive layer containing a metal oxide and a conductive layer formed on the backing substrate with the adhesive layer therebetween;... Agent: Sughrue Mion, PLLC

20070093052 - Semiconductor device have multiple wiring layers and method of producing the same: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070093053 - Method of fabricating interconnect structure: A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first porous low-k layer to electrically connect... Agent: Jianq Chyun Intellectual Property Office

20070093054 - Multiple device types including an inverted-t channel transistor and method therefor: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method... Agent: Freescale Semiconductor, Inc. Law Department

20070093055 - High-aspect ratio contact hole and method of making the same: A substrate has thereon a conductive region to be partially exposed by the contact hole, a contact etch stop layer overlying the substrate and covering the conductive region, and an inter-layer dielectric (ILD) layer on the contact etch stop layer. A photoresist pattern is formed on the ILD layer. The... Agent: North America Intellectual Property Corporation

20070093056 - Method for forming metal line and semiconductor device including the same: Disclosed is a technique of manufacturing a semiconductor device and a corresponding device. A metal line may be formed in a semiconductor device using a photoresist pattern with an oxide layer formed on the surface of a metal film, in accordance with embodiments. A heat-treatment process on a metal film... Agent: Sherr & Nourse, PLLC

20070093057 - Method of reducing charging damage to integrated circuits during semiconductor manufacturing: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the... Agent: North America Intellectual Property Corporation

20070093059 - Method and apparatus for thin film solar cell manufacturing: The present invention provides a method of making a Cu-In-Ga sputtering target by melting Cu, In and Ga, Cu and In or Cu and Ga to form a uniform melt with a pre-determined stoichiometry, which melt is sprayed to cause sprayed uniform melt particles to solidify into Cu-In-Ga particles with... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070093058 - Method for producing electric contact and electrical connector: A method for producing an electric contact extending from a copper foil, comprises steps of fixing a cover lay having a hole of a diameter smaller than that of the copper foil of a predetermined size to the copper foil, and plating the hole of the cover lay so as... Agent: Baker & Botts L.L.P.

20070093060 - Semiconductor device having a cu interconnection: A Cu interconnection in a semiconductor device has an ununiform profile of additive metal atoms wherein the additive metal atoms are rich in the vicinities of bottom and side surfaces of the Cu interconnection. The Cu interconnection also has an ununiform silicon profile wherein additive silicon atoms are rich in... Agent: Sughrue Mion, PLLC

20070093062 - Semiconductor device fabrication method: A method for fabricating a semiconductor device with a borderless via/wiring structure includes the steps of performing borderless via etching using a resist mask to form a contact hole in an interlevel dielectric layer over a semiconductor substrate so as to expose two different metal materials of lower layer patterns... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070093061 - Solvent removal of photoresist mask and gold impregnated residue and process: Solvent removal of photoresist mask and gold containing post-etch residues in the production of semiconductor wafer plasma etching is effectively conducted prior to further processing of the wafer. Using metallic iodine dissolved in a polar solvent system, the chemistry penetrates and quickly dissolves the photoresist mask while iodine complexes and... Agent: Arthur J. Plantamura General Chemical Performance Products LLC.

20070093063 - Method of chemical mechanical polishing and method of fabricating semiconductor device using the same: There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer... Agent: Myers Bigel Sibley & Sajovec

20070093065 - Method for manufacturing a semiconductor wafer: A method is used for manufacturing a semiconductor wafer. The back surface of a semiconductor wafer is ground. The back surface is cleaned with ozone water. The back surface of the semiconductor wafer is etched with a mixed acid that contains hydrofluoric acid and nitric acid. The cleaning and etching... Agent: Rabin & Berdo, PC

20070093064 - Polishing method of cu film and method for manufacturing semiconductor device: A method for polishing a Cu film comprises contacting a Cu film formed above a semiconductor substrate with a polishing pad attached to a turntable, and supplying a first chemical liquid which promotes the polishing of the Cu film and a second chemical liquid which contains a surfactant, to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070093066 - Stacked wafer or die packaging with enhanced thermal and device performance: Some embodiments of the present invention include apparatuses and methods relating to stacked wafer or die packaging with enhanced thermal and device performance.... Agent: Blakely Sokoloff Taylor & Zafman

20070093068 - Manufacturing method of semiconductor device: A semiconductor device manufacturing method involves heating up a solution containing sulfuric acid and hydrogen peroxide solution, replenishing the solution with a predetermined quantity of sulfuric acid and a predetermined quantity of hydrogen peroxide solution at a predetermined interval, maintaining a concentration of the sulfuric acid in the solution at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070093067 - Wafer edge cleaning process: A method of processing a semiconductor wafer can be used prior to an immersion lithography process. The method includes providing a layer of organic photoresist onto a surface of the semiconductor wafer and removing a portion of the photoresist from an outer edge of the wafer using an edge-bead removal... Agent: Haynes And Boone, LLP

20070093069 - Purge process after dry etching: A purge process for a chip performed after a dry etching process is provided. The dry etching process is carried out inside a reaction chamber. The purge process is used to remove any byproducts produced by said dry etching process. The purge process includes injecting an inert gas into the... Agent: Jianq Chyun Intellectual Property Office

20070093070 - Triple layer anti-reflective hard mask: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective... Agent: Harrity Snyder, L.L.P.

20070093071 - Method and apparatus for processing a wafer: A method of a single wafer wet/dry cleaning apparatus comprising: a transfer chamber having a wafer handler contained therein; a first single wafer wet cleaning chamber directly coupled to the transfer chamber; and a first single wafer ashing chamber directly coupled to the transfer chamber.... Agent: Applied Materials/blakely

20070093072 - Epitaxial wafer and method for producing same: After cleaning the front and back sides of a silicon wafer with a liquid SC-1 and liquid SC-2, the front and back sides of the silicon wafer are cleaned with an HF solution to be water-repellent surfaces. Following that, an epitaxial layer of silicon is formed on the front side.... Agent: Greenblum & Bernstein, P.L.C

20070093073 - Technique for the growth and fabrication of semipolar (ga,a1,in,b)n thin films, heterostructures, and devices: A method for growth and fabrication of semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation,... Agent: Gates & Cooper LLP Howard Hughes Center

20070093074 - Ge-based semiconductor structure fabricated using a non-oxygen chalcogen passivation step: A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material... Agent: Scully Scott Murphy & Presser, PC

20070093075 - Method for using film formation apparatus: In a method for using a film formation apparatus for a semiconductor process, process conditions of a film formation process are determined. The process conditions include a preset film thickness of a thin film to be formed on a target substrate. Further, a timing of performing a cleaning process is... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070093076 - Electromagnetic treatment in atmospheric-plasma coating process: A plasma is produced in a treatment space (58) by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes (54,56) separated by a dielectric material (64), and a precursor material is introduced into the treatment space to coat a substrate... Agent: Antonio R. Durando

20070093077 - Method of forming a trench semiconductor device and structure therefor: In one embodiment, a trench semiconductor device is formed to have an oxide of a first thickness along the sidewalls of the trench, and to have a greater thickness along at least a portion of a bottom of the trench.... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070093078 - Porous insulating film, method for producing the same, and semiconductor device using the same: The present invention provides a process of producing a porous insulating film effective as an insulating film constituting a semiconductor device and a process of producing a porous insulating film having high adhesion to a semiconductor material, which is in contact with the upper and lower interfaces of the insulating... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070093079 - Imprinting method and imprinting apparatus: An imprinting method of the present invention is to press a mold member (40) having thereon a mold pattern onto a film carried on a principal plane of a substrate (50) as an object to be processed, so as to transfer the mold pattern to the film. A plurality of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070087454 - Method of fabricating a magnetic shift register: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/ or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of trench. A seed... Agent: Samuel A. Kassatly Law Office

20070087455 - Independent control of ion density, ion energy distribution and ion dissociation in a plasma reactor: A method of processing a workpiece in a plasma reactor includes coupling RF power from at least three RF power source of three respective frequencies to plasma in the reactor, setting ion energy distribution shape by selecting a ratio between the power levels of a first pair of the at... Agent: Robert M. Wallace Suite 102

20070087456 - Substrate processing method and substrate processing apparatus: According to the substrate processing method of the invention, a jet of droplets generated from a gas and a heated processing liquid is supplied to the surface of a substrate. A resist stripping liquid to strip off the resist from the surface of the substrate is then supplied to the... Agent: Ostrolenk Faber Gerb & Soffen

20070087457 - Method for inspecting and mending defect of photo-resist and manufacturing process of printed circuit board: A method for inspecting and mending defects of photo-resist is provided. It includes the following steps. First, a substrate having at least one film is provided. Then, a patterned photo-resist layer is formed on the film. Next, an optical inspection procedure is performed to inspect whether the patterned photo-resist layer... Agent: Jianq Chyun Intellectual Property Office

20070087460 - Method of fabricating nitride-based semiconductor laser diode: A method of manufacturing a nitride-based semiconductor laser diode that can minimize optical absorption on a cavity mirror plane and improve the surface roughness of the cavity mirror plane is provided. The method includes the steps of: forming on a (0001) GaN (gallium nitride) substrate having at least two masks... Agent: Buchanan, Ingersoll & Rooney PC

20070087459 - Patchwork patterned devices and related methods: Devices, such as light-emitting devices (e.g., LEDs), and methods associated with such devices are provided. A light-emitting device may include an interface including a first region and a second region. The first region having a dielectric function that varies spatially according to a first pattern, and the second region having... Agent: Wolf Greenfield & Sacks, PC

20070087458 - Semiconductor device and manufacturing method of the same: An RTA method has a limitation on miniaturization. The RTA method needs a heating time of several seconds, and has a risk that impurities are diffused into a deep portion, since a semiconductor substrate is heated at a high temperature. Thus, the RTA method has a difficulty in responding miniaturization... Agent: Eric Robinson

20070087461 - Light emitting diode and method for manufacturing the same: A light emitting diode is disclosed. The light emitting diode comprises: a transparent substrate; a reflective layer located on a surface of the transparent substrate; a solder layer located on the other surface of the transparent substrate; a semiconductor epitaxial structure located on the solder layer, wherein the semiconductor epitaxial... Agent: Baker & Hostetler LLP Suite 1100

20070087462 - Method of forming a device package having edge interconnect pad: A method of forming a device package having an edge interconnect pad includes forming an array of MEMS devices overlaying at least one conductive via that electrically connects to an underlying layer. The method continues with depositing, by way of a damascene process, a conductive material on a substrate that... Agent: Hewlett Packard Company

20070087463 - Pixel sensor having doped isolation structure sidewall: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure... Agent: Scully, Scott, Murphy & Pressner

20070087464 - Method for producing etched holes and/or etched trenches as well as a diaphragm sensor unit: A method for producing etched holes and/or etched trenches of components based on silicon and/or a layered silicon/insulator structure. A germanium-containing layer and/or a germanium layer is provided at the point in the etching direction at which or in whose surroundings an etching procedure is to be completed. Germanium and/or... Agent: Kenyon & Kenyon LLP

20070087465 - Micromechanical component having an anodically bonded cap and a manufacturing method: A micromechanical component includes a cap wafer made up of at least a first silicon substrate and a thin glass substrate, and having a functional wafer made up of at least a second silicon substrate, at least one electrical contact surface being disposed on the functional wafer. The cap wafer... Agent: Kenyon & Kenyon LLP

20070087466 - Integrated microphone: A method of forming a microphone having a variable capacitance first deposits high temperature deposition material on a die. The high temperature material ultimately forms structure that contributes to the variable capacitance. The method then forms circuitry on the die after depositing the deposition material. The circuitry is configured to... Agent: Bromberg & Sunstein LLP

20070087467 - Cmos image sensor: A method for forming an image sensor device. An alignment mark is formed on or in a substrate with distance from the alignment mark to the substrate edge less than about 3 mm. An array of active photosensing pixels is formed on the substrate. At least one dielectric layer is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070087468 - Method for producing electronic components: The invention relates to a method for producing electronic components comprising adjacent electrodes interspaced at distances ranging between 10 nanometers and several micrometers on a substrate of any type. According to the invention, the electrodes are structured by means of overlapping edges on the deposited layer or by undercutting the... Agent: Mayer & Williams PC

20070087469 - Particulate for organic and inorganic light active devices and methods for fabricating the same: A method of making polymer blend light active particles, comprising the steps of providing a solution comprised of a first organic light active diode material and a second organic light active diode material in a solvent and providing a non-solvent liquid. The method of making polymer blend light active particles... Agent: Michaud-duffy Group LLP

20070087470 - Vapor phase synthesis of metal and metal oxide nanowires: Vapor phase methods for synthesizing metal nanowires directly without the help of templates. A vapor phase method in which nucleation and growth of metal oxides at temperatures higher than the oxide decomposition temperatures lead to the respective metal nanowires. The chemical vapor transport of tungsten in the presence of oxygen... Agent: David W. Carrithers Carrithers Law Office, PLLC

20070087476 - Apparatus for improved power distribution in wirebond semiconductor packages: A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting... Agent: Texas Instruments Incorporated

20070087474 - Assembly process for out-of-plane mems and three-axis sensors: A method of assembling a three dimensional micromachined structure comprising the steps of defining a cavity in a holder wafer having a thick upper layer, providing a plurality of fingers in the thick upper layer extending from the holder wafer into the cavity, and disposing an out-of-plane wafer into the... Agent: Daniel L. Dawes Myers Dawes Andras & Sherman LLP

20070087475 - Method and apparatus for peeling surface protective film: A method and an apparatus for peeling a surface protective film attached on the surface of a semiconductor wafer are provided. A heating block is set in proximity to the whole surface of the semiconductor wafer, and the whole surface protective film is heated by the heating block. Thus, the... Agent: Christie, Parker & Hale, LLP

20070087473 - Method for manufacturing semiconductor package substrate: A method for manufacturing a semiconductor package is proposed. A circuit board with a circuit layer on at least one surface thereof is provided. The circuit board has at least one free area, and the circuit layer has a plurality of electrically connecting pads distributed on the periphery of the... Agent: Mr. Joseph A. Sawyer, Jr. Sawyer Law Group LLP

20070087472 - Methods for magnetically directed self assembly: A fluidic assembly method includes dispersing a number of functional blocks in a fluid to form a slurry. Each of the functional blocks includes at least one element and a patterned magnetic film comprising at least one region. The fluidic assembly method further includes immersing at least a portion of... Agent: General Electric Company Global Research

20070087478 - Semiconductor chip package and method for manufacturing the same: A semiconductor chip package mainly comprises an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The present invention is characterized in that the peripheral substrate... Agent: Lowe Hauptman Berner, LLP

20070087477 - Semiconductor device having a low-resistance bus interconnect, method of manufacturing same, and display apparatus employing same: s

20070087471 - Semiconductor package and method of manufacturing the same: A semiconductor package comprises a silicon substrate having an insulative surface; a patterned metal layer, formed on the insulative surface of the silicon substrate; an insulation layer formed on the patterned metal layer, and the patterned metal layer being partially exposed for functioning as at least a set of the... Agent: Bacon & Thomas, PLLC

20070087479 - Method of manufacturing low cte substrates for use with low-k flip-chip package devices: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one... Agent: Baker & Mckenzie On Behalf Of Tsmc

20070087480 - Chip package method: The present invention relates to a method for manufacturing a semiconductor chip package structure including the following steps. A substrate is provided. A plurality of chips are assembled onto the substrate and are electrically connected with the substrate. A stiffener is assembled onto the substrate and the stiffener has a... Agent: Jianq Chyun Intellectual Property Office

20070087481 - Underfill aiding process for a tape: A tape having a predetermined area is provided for a chip. A hole is drilled within the predetermined area. The chip is adhered to the predetermined area by underfilling an underfill material between the chip and the tape from one side of the chip. By the hole, the invention provides... Agent: Lowe Hauptman Berner, LLP

20070087482 - Method and apparatus for operating nonvolatile memory cells with modified band structure: A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the nonvolatile memory cell, the band... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070087483 - Heat sink and method for its production: A method for producing a heat sink for cooling a semiconductor device including forming plural base members, the base member being each in plate or block-shape, the base member each having paths shaped on one or both sides of surfaces thereof, and the base member each having connecting regions on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087484 - Heating element of a printhead having resistive layer over conductive layer: A heating element of a printhead has a conductive layer deposited over a substrate, and a resistive layer deposited over and in electrical contact with the conductive layer.... Agent: Hewlett Packard Company

20070087485 - Methods for fabricating polysilicon film and thin film transistors: A method for fabricating polysilicon film is disclosed. First, a first substrate is provided, wherein a plurality of sunken patterns has been formed on the front surface of the first substrate. Then, a second substrate is provided and an amorphous polysilicon film is formed on the second substrate. Next, the... Agent: Jianq Chyun Intellectual Property Office

20070087489 - Organic thin film transistor, method of manufacturing the same, and flat panel display comprising the same: The organic TFT includes: a gate electrode; source and drain electrodes insulated from the gate electrode; an organic semiconductor layer insulated from the gate electrode and electrically connected to the source and drain electrodes; an insulating layer insulating the gate electrode from the source and drain electrodes and the organic... Agent: Stein, Mcewen & Bui, LLP

20070087487 - Semiconductor device and manufacturing method thereof: An object is to obtain a semiconductor device with improved characteristics by reducing contact resistance of a semiconductor film with electrodes or wirings, and improving coverage of the semiconductor film and the electrodes or wirings. The present invention relates to a semiconductor device including a gate electrode over a substrate,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070087488 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to control the plane orientation of crystal grains obtained by using a laser beam, into a direction that can be substantially regarded as one direction in an irradiation region of the laser beam. After forming a cap film over a semiconductor film,... Agent: Nixon Peabody, LLP

20070087486 - Thin-film transistor, tft-array substrate, liquid-crystal display device and method of fabricating the same: A thin-film transistor includes a gate layer, a gate insulting layer, a semiconductor layer, a drain layer, a passivation layer (each of which being formed on or over an insulating substrate), and a conductive layer formed on the passivation layer. The conductive layer is connected to the gate layer or... Agent: Mcginn Intellectual Property Law Group, PLLC

20070087490 - Thin film transistor and method of fabricating the same: A bottom gate thin film transistor and method of fabricating the same are disclosed, in which a channel region is crystallized by a super grain silicon (SGS) crystallization method, including: forming a gate electrode and a gate insulating layer on an insulating substrate; forming an amorphous silicon layer on the... Agent: H.c. Park & Associates, PLC

20070087491 - Transistor and method of fabricating the same: Disclosed is a method for fabricating a gate of a field effect transistor. The method comprises a) forming a field oxide layer on a silicon substrate and then applying a photoresist layer in order to define a gate, b) etching the silicon substrate using the photoresist layer as a mask,... Agent: Marger Johnson & Mccollom, P.C.

20070087492 - Method for forming semiconductor film, method for manufacturing semiconductor device and electrooptic device, apparatus for performing the same, and semiconductor device and electrooptic device: An object of the present invention is to provide a method for easily forming a polycrystalline semiconductor thin-film, such as polycrystalline silicon having high crystallinity and high quality, or a single crystalline semiconductor thin-film at inexpensive cost, the crystalline semiconductor thin-film having a large area, and to provide an apparatus... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20070087493 - Trench schottky device with single barrier: A process for forming a trench Schottky barrier device includes the forming of an oxide layer within the trenches in the surface of a silicon wafer, and then depositing a full continuous metal barrier layer over the full upper surface of the wafer including the trench interiors and the mesas... Agent: Ostrolenk Faber Gerb & Soffen

20070087494 - Method of manufacturing a semiconductor apparatus: A method of manufacturing a semiconductor apparatus of the present invention comprises forming body diffusion layer, a gate electrode, and an interlayer dielectric over an surface of a semiconductor substrate, forming a photoresist having an opening in a region overlapping with a part of the body diffusion layer, removing the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070087495 - Photomask and method for manufacturing thin film transistor: An exemplary photomask (150) has a slit. The slit has at least one turning region (D1) and at least one other regions, and the slit at the at least one turning region has a narrower width than the slit at the at least one other regions. An exemplary method for... Agent: Wei Te Chung Foxconn International, Inc.

20070087496 - Non-volatile memory devices including fuse covered field regions: A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse An isolation layer is configured to isolate the... Agent: Myers Bigel Sibley & Sajovec

20070087497 - Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer... Agent: J C Patents, Inc.

20070087498 - Methods of forming buried bit line dram circuitry: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within... Agent: Wells St. John P.s.

20070087501 - Semiconductor device and manufacturing method thereof: A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so as to protrude from a surface opposite to a semiconductor substrate 1... Agent: Miles & Stockbridge PC

20070087500 - Semiconductor device and method of manufacturing the same: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer... Agent: Marger Johnson & Mccollom, P.C.

20070087499 - Semiconductor memory device with vertical channel transistor and method of fabricating the same: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars... Agent: Mills & Onello LLP

20070087503 - Improving nrom device characteristics using adjusted gate work function: A method including adjusting a threshold voltage of an NROM (nitride, read only memory) device by adjusting a work function associated with a gate terminal of the NROM device.... Agent: Eitan Law Group C/o Landonip Inc.

20070087504 - Integration process flow for flash devices with low gap fill aspect ratio: A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with... Agent: Parsons Hsue & De Runtz LLP

20070087505 - Method of forming a semiconductor device: In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxidation. In a preferred embodiment, these steps are clustered and transportation... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070087506 - Method of forming a semiconductor device: In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxidation. In a preferred embodiment, these steps are clustered and transportation... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070087502 - Method of forming flash cell array having reduced word line pitch: A method of forming a NAND Flash memory device comprises forming a control gate polysilicon layer over a substrate, forming a mask layer over the control gate polysilicon layer, the mask layer including a mask pattern defining a plurality of spaced word lines of the FLASH memory device, the word... Agent: Duane Morris, LLPIPDepartment

20070087507 - Crystalline-type device and approach therefor: Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material is crystallized to form the single-crystal region using an... Agent: Crawford Maunu PLLC

20070087508 - Method for making a p-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse: A method is described for forming a nonvolatile one-time-programmable memory cell having reduced programming voltage. A contiguous p-i-n diode is paired with a dielectric rupture antifuse formed of a high-dielectric-constant material, having a dielectric constant greater than about 8. In preferred embodiments, the high-dielectric-constant material is formed by atomic layer... Agent: Vierra Magen/sandisk Corporation

20070087509 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087510 - Semiconductor devices and manufacturing methods of the same: A semiconductor device may include first and second silicon layers formed over a semiconductor substrate. An insulating layer may be formed between first and second silicon layers. A gate insulating layer, a gate electrode, and a spacer may be formed over a second silicon layer. A source/drain impurity area may... Agent: Sherr & Nourse, PLLC

20070087511 - Method for forming an avalanche photodiode: Methods for fabricating an avalanche photodiode (APD), wherein the APD provides both high optical coupling efficiency and low dark count rate. The APD is formed such that it provides an active region of sufficient width to enable high optical coupling efficiency and a low dark count rate. Some APDs fabricated... Agent: Demont & Breyer, LLC

20070087512 - Substrate embedded with passive device: A method for manufacturing a substrate embedded with a passive device, comprising the steps of (a) molding the passive device and (b) mounting the molded passive device in a cavity formed on the substrate, is disclosed. The substrate embedded with a passive device and the manufacturing method thereof in accordance... Agent: Staas & Halsey LLP

20070087513 - Method for forming a variable capacitor: A method for forming a variable capacitor including a conductive strip covering the inside of a cavity, and a flexible conductive membrane placed above the cavity, the cavity being formed according to the steps of: forming a recess in the substrate; placing a malleable material in the recess; having a... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070087514 - Soi substrate with selective oxide layer thickness control: A method for forming a SOI substrate device having multiple buried oxide regions comprising the steps of; forming a thin buried oxide layer in a silicon-containing substrate, forming a mask with openings therein on the substrate, implanting oxygen into the substrate through the openings in the mask, forming a buried... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087522 - Dielectric gap fill with oxide selectively deposited over silicon liner: A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the... Agent: Townsend And Townsend And Crew LLP / Amat

20070087521 - Fabrication method of semiconductor device: Fabrication method of semiconductor device to reduce leak current at junction interface of p-type well and n-type well. The method comprises forming a first trench portion 109 by selective dry etching of a silicon substrate 101 using a first etching gas and forming a second trench portion 113 including an... Agent: Young & Thompson

20070087515 - Low stress sti films and methods: The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive stress STI films will generally exhibit a compressive stress of less... Agent: Townsend And Townsend And Crew LLP / Amat

20070087519 - Method and structure for double lining for shallow trench isolation: A method of forming an integrated circuit device structure having a design rule of less than 0.13 micron. The method includes providing a substrate and forming a pad oxide layer overlying the substrate. The method includes forming a nitride layer overlying the pad oxide layer and patterning the nitride layer... Agent: Townsend And Townsend And Crew, LLP

20070087516 - Method for forming an isolating trench with a dielectric material: The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an isolating trench in a memory device.... Agent: Morrison & Foerster LLP

20070087520 - Method for manufacturing semiconductor device: A semiconductor device includes an element isolation film, which exhibits less variations in the height dimension from the surface of the substrate and has a desired height dimension from the surface of the substrate. A process for manufacturing a semiconductor device includes: providing a predetermined pattern of a silicon nitride... Agent: Young & Thompson

20070087517 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device including forming a pad oxide layer on a semiconductor substrate, forming a spacer oxide layer pattern on sidewalls of the pad oxide layer, and forming a nitride layer on the pad oxide layer. The method further includes forming a groove in the nitride... Agent: Jong-woon Choi

20070087518 - Semiconductor device and method for producing the same: A method for forming STIs in a semiconductor substrate includes forming a protective oxide film on the semiconductor substrate and forming a silicon nitride film on the protective oxide film, performing a photolithography and a dry etching so as to penetrate the silicon nitride film and the protective oxide film... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070087523 - Recessed shallow trench isolation: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070087524 - Wafer singulation process: A method of singulating a semiconductor die from a wafer is provided. The method includes etching or cutting several trenches into the wafer from a front surface of the wafer, such that each trench extends along an entire side of the die; depositing a passivation layer into the trenches to... Agent: Ostrolenk Faber Gerb & Soffen

20070087525 - Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a... Agent: Ibm Corporation, T.j. Watson Research Center

20070087527 - Method and device for bonding wafers: The invention relates to a method and a device (1) for bonding wafers (6, 9). Here at least one wafer surface is first wetted with a molecular dipolar compound, whereupon the wafers are brought into contact with each other. The bonding of the wafers then takes place by means of... Agent: Kusner & Jaffe Highland Place Suite 310

20070087528 - Method and structure for vertically-stacked device contact: Method and structure for vertically stacking microelectronic devices are disclosed. Subsequent to appropriate deposition, patterning, trenching, and passivation subprocesses, a conductive layer is formed wherein one end comprises an external contact portion for C4 interfacing, and another end establishes electrical contact with an internal contact at the bonding interface between... Agent: David C. Lundmark Intel Corporation, Sc4-202

20070087526 - Method of recycling an epitaxied donor wafer: A method for forming a semiconductor structure comprising a thin layer of semiconductor material on a receiver wafer is disclosed. The method comprises removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the... Agent: Winston & Strawn LLP Patent Department

20070087529 - Simulation method of wafer warpage: Disclosed is a simulation method for determining wafer warpage. This method includes dividing layers and evaluating a composition ratio of materials composing the layers. The method mathematically transforms a semiconductor device, which is constructed as a complicated structure with various materials, into a simplified, mathematically equivalent stacked structure comprising a... Agent: Mills & Onello LLP

20070087530 - Detection of seed layers on a semiconductor device: A device and/or method which detects a seed layer and a device and/or method of forming layers on a semiconductor device. The device which forms layers on the semiconductor device may include a metal layer forming unit (which forms a metal layer on a wafer), a copper seed layer forming... Agent: Sherr & Nourse, PLLC

20070087531 - Method and apparatus for flag-less water bonding tool: Embodiments in accordance with the present invention relate to methods and apparatuses for bonding together substrates in a manner that suppresses the formation of voids between them. In a specific embodiment, a backside of each substrate is adhered to a front area of flexible, porous chuck having a rear area... Agent: Townsend And Townsend And Crew, LLP

20070087532 - Method for applying a structure of joining material to the back surfaces of semiconductor chips: A structure of joining material is applied to the back surfaces of semiconductor chips in manufacturing semiconductor devices. The joining material is applied, in finely metered and structured form via a joining material jet appliance, to the back surfaces of the semiconductor chips of a divided semiconductor wafer.... Agent: Edell, Shapiro & Finnan, LLC

20070087534 - Electro-optical device, method of manufacturing the same, electronic apparatus, and semiconductor device: An electro-optical device includes: a substrate; a plurality of pixel units provided in a display region on the substrate; and a driving circuit that is provided in a peripheral region surrounding the display region and includes semiconductor elements that drive the plurality of pixel units, each of the semiconductor elements... Agent: Oliff & Berridge, PLC

20070087533 - Gas ring and method of processing substrates: A process gas to a reactor volume of a semiconductor processing reactor is provided through gas injector ports of a gas ring. The process gas flows horizontally from the gas injector ports across a principal surface of a rotating susceptor to exhaust ports of the gas ring. The spent process... Agent: Gunnison Mckay & Hodgson, LLP Garden West Office Plaza, Suite 220

20070087535 - Semiconductor device: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087537 - Manufacturing method of semiconductor device: A technology capable of improving the yield