Semiconductor device manufacturing: process inventions 04/07

20070092979 - Production method for polarization inversion unit: It is provided a novel method of producing polarization inversion parts by electric field polling process wherein the polarization inversion part extends to a deeper point from the surface of a substrate. The polarization inversion part is produced by electric field polling process using a comb electrode having a plurality... Agent: Burr & Brown

20070092980 - Method of fabricating gan: A method of fabricating a thick GaN layer includes forming a porous GaN layer having a thickness of 10-1000 nm by etching a GaN substrate in a reaction chamber in an HCl and NH3 gas atmosphere and forming an in-situ GaN growth layer in the reaction chamber. The method of... Agent: Stein, Mcewen & Bui, LLP

20070092981 - Display apparatus and fabricating method thereof: A display apparatus and method of forming the same comprise an insulating substrate; a thin film transistor formed on the insulating substrate; a first electrode electrically connected to the thin film transistor and having a first maximum roughness; a buffer layer formed on the first electrode and having a second... Agent: Cantor Colburn, LLP

20070092982 - Method of fabricating flexible micro-capacitive ultrasonic transducer by the use of imprinting and transfer printing techniques: A method of fabricating flexible micro-capacitive ultrasonic transducer by the use of imprinting and transfer printing techniques is disclosed, which mainly comprises the steps of: forming oscillation cavities by imprinting; forming fixed electrodes by transfer printing; forming oscillation films by transfer printing; forming driving electrodes by transfer printing; and so... Agent: Bruce H. Troxell

20070092983 - Process of forming a microphone using support member: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate... Agent: Bromberg & Sunstein LLP

20070092984 - Cmos image sensor and method for fabricating the same: An image sensor includes a semiconductor substrate; a pixel array disposed on the semiconductor substrate; and an insulating interlayer, formed on the semiconductor substrate, having a trench coinciding with the disposition of the pixel array, the trench having uniformly inclined inner sidewalls.... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070092985 - Solid-state imaging device and method of manufacturing the same: A solid-state imaging device includes a pixel formation region 4 and a peripheral circuit formation region 20 formed in the same semiconductor substrate; in the peripheral circuit formation region 20 a first element isolation portion is formed of an element isolation layer 21 in which an insulation layer is buried... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20070092986 - Method for fabricating cmos image sensor: This invention provides a CMOS image sensor having a pinned photodiode. A P substrate is provided having thereon a P well. The P well is adjacent to a light-sensing region of the CMOS image sensor. A gate electrode of a transfer transistor of the CMOS image sensor is formed on... Agent: North America Intellectual Property Corporation

20070092987 - Conductive electrode powder, a method for preparing the same, a method for preparing an electrode of a plasma display panel by using the same, and a plasma display panel comprising the same: The present invention provides a conductive electrode powder which includes electroconductive metal particles, and an inorganic oxide coating layer covering the surface of the electroconductive metal particles. By using a conductive electrode powder, the corrosion, the ionization, the migration such as ionization, and yellowing of the electrode such as colloidalization... Agent: Robert E. Bushnell

20070092989 - Conductive nanoparticles: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070092988 - Method for producing organic solar cells or photo detectors: The invention relates to a method for the production of organic solar cells or photo detectors, especially based on organic polymers. Said method comprises the following steps: a first organic n or p conducting semi-conductor layer is applied to an electrode, a second organic semi-conductor layer having other corresponding conductive... Agent: Fish & Richardson PC

20070092990 - Field effect transistors (fets) with inverted source/drain metallic contacts, and method of fabricating same: The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a... Agent: Scully Scott Murphy & Presser, PC

20070092991 - Method for manufacturing a semiconductor device: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame... Agent: Texas Instruments Incorporated

20070092994 - Method of manufacturing semiconductor device and a semiconductor device: The present invention provides a method of manufacturing a semiconductor device which comprises an upper and a lower film each having a wire, and a plurality of pellets each mounted on each of the upper and lower films, where the upper and lower films are electrically connected to each other.... Agent: Young & Thompson

20070092992 - Semiconductor component and method for production of a semiconductor component: A semiconductor substrate, a semiconductor chip and a semiconductor component with areas composed of a stressed monocrystalline material, and a method for production of a semiconductor component is disclosed. In one embodiment, the semiconductor chip includes relatively thick stressed layers achieving reduced switching times. For this purpose, the semiconductor substrate... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070092993 - Semiconductor device packaging for avoiding metal contamination: A semiconductor device manufacture method includes: bonding a main device surface of a semiconductor chip onto a package tape with adhesive material; and subjecting the semiconductor chip and the package tape to baking to cure the adhesive material. The baking of the semiconductor chip and the package tape is accompanied... Agent: Mcginn Intellectual Property Law Group, PLLC

20070092996 - Method of making semiconductor package with reduced moisture sensitivity: A method of making a semiconductor package (10) includes placing an integrated circuit (IC) die (12) on a first side (14) of a substrate (16) and electrically connecting the IC die (12) to the first side (14) of the substrate (16). First solder balls (22) are attached to a second... Agent: Freescale Semiconductor, Inc. Law Department

20070092995 - Microelectronics grade metal substrate, related metal-embedded devices and methods for fabricating same: Fabricating a microelectronics grade metal substrate comprises forming the metal substrate on a sacrificial substrate. An adhesion layer can be deposited on or over the surface of the sacrificial substrate. A seed layer of the metal can be deposited on or over the adhesion layer. The metal material can be... Agent: Lathrop & Clark LLP

20070092997 - Fabrication method of non-volatile memory: A method of fabrication a non-volatile memory is provided. A stacked structure is formed on a substrate, the stacked structure including a gate dielectric layer and a control gate. Then, a first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed on the top and... Agent: Jianq Chyun Intellectual Property Office

20070092998 - Semiconductor heat-transfer method: A semiconductor heat-transfer method includes the steps of (a) treating a high conductivity metal substrate through an electrolytic oxidation process to have an oxidized insulation layer be covered on the surface of the high conductivity metal substrate, (b) covering a metal conducting layer on the oxidized insulation layer at selected... Agent: Rosenberg, Klein & Lee

20070092999 - Method for evaluating and modifying solder attach design for integrated circuit packaging assembly: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is... Agent: Texas Instruments Incorporated

20070093000 - Pre-molded leadframe and method therefor: A method of manufacturing a pre-molded leadframe for use in a semiconductor package includes providing a leadframe having a die pad and a plurality of terminal leads. A first molding material is formed in the leadframe to expose the upper surface of the die pad and the upper surfaces of... Agent: Ishimaru & Zahrt LLP

20070093001 - Encapsulating electrical connections: An electrical connection is encapsulated by dispensing an encapsulant on a first side of the electrical connection only, and directing the encapsulant to a second side of the electrical connection from the first side, where the second side generally faces opposite the first side.... Agent: Hewlett Packard Company

20070093002 - Electric appliance, semiconductor device, and method for manufacturing the same: In the present circumstances, a film formation method of using spin coating in a manufacturing process is heavily used. As increasing the substrate size in future, the film formation method of using spin coating becomes at a disadvantage in mass production since a mechanism for rotating a large substrate becomes... Agent: Nixon Peabody, LLP

20070093003 - Method for fabricating thin film transistors: A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor... Agent: Jianq Chyun Intellectual Property Office

20070093004 - Method of manufacturing thin film transistor including zno thin layer: Provided is a method of manufacturing a thin film transistor (TFT) including a transparent ZnO thin layer that is formed at a low temperature by causing a surface chemical reaction between precursors containing elements constituting the ZnO thin layer. The method includes the steps of: depositing a gate metal layer... Agent: Mayer, Brown, Rowe & Maw LLP

20070093005 - Thin film transistor panel and method of manufacture: A thin film transistor array panel includes a pixel electrode formed on a substrate, a gate line formed on the pixel electrode, a gate insulating film formed on the gate line, a semiconductor formed on the gate insulating film, a data line and a drain electrode formed on the gate... Agent: Macpherson Kwok Chen & Heid LLP

20070093006 - Technique for preparing precursor films and compound layers for thin film solar cell fabrication and apparatus corresponding thereto: The present invention advantageously provides for, in different embodiments, improved contact layers or nucleation layers over which precursors and Group IBIIIAVIA compound thin films adhere well and form high quality layers with excellent micro-scale compositional uniformity. It also provides methods to form precursor stack layers, by wet deposition techniques such... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070093007 - Active matrix pixel device with photo sensor: An active matrix pixel device is provided, for example an electroluminescent display device, the device comprising circuitry supported by a substrate and including a polysilicon TFT (10) and an amorphous silicon thin film PIN diode (12). Polysilicon islands are formed before an amorphous silicon layer is deposited for the PIN... Agent: Philips Intellectual Property & Standards

20070093008 - Mos varactor property detection method and mos varactor manufacturing method using the same: Disclosed is a method for detecting properties of a Metal Oxide Silicon (MOS) varactor, which includes: establishing a MOS varactor model equation in conjunction with an area of a gate; calculating values of the coefficients of the MOS varactor model equation through measurements for test materials; and extracting the properties... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070093009 - Semiconductor device with vertical electron injection and its manufacturing method: A method for making a semiconductor device with vertical electron injection, including: transferring a monocrystalline thin film onto a first face of a support substrate; producing at least one electronic component from the monocrystalline thin film; forming at least one recess in a second face of the substrate to enable... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070093010 - Method of making an inverted-t channel transistor: A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of... Agent: Freescale Semiconductor, Inc. Law Department

20070093012 - Method for fabricating a gate dielectric of a field effect transistor: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070093013 - Method for fabricating a gate dielectric of a field effect transistor: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric... Agent: Patterson & Sheridan, LLP

20070093011 - Method of fabricating gate dielectric layer and method of fabricating semiconductor device: A method of fabricating a gate dielectric layer is described. First, a well is produced in a substrate. Later, the substrate is cleaned. Then the substrate is processed by a pre-annealed process. Afterwards, a gate dielectric layer is formed on the substrate. As a result, the on-current of the semiconductor... Agent: Jianq Chyun Intellectual Property Office

20070093016 - Formation of standard voltage threshold and low voltage threshold mosfet devices: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second... Agent: Dinsmore & Shohl LLP

20070093017 - Formation of standard voltage threshold and low voltage threshold mosfet devices: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second... Agent: Dinsmore & Shohl LLP

20070093014 - Method for preventing doped boron in a dielectric layer from diffusing into a substrate: The present invention provides a method for preventing doped boron in a dielectric layer from diffusing into a substrate. First, at least one gate is formed on a periphery circuit area and a memory array area of a substrate, respectively, wherein the pattern density in the memory array area is... Agent: Birch Stewart Kolasch & Birch

20070093015 - Semiconductor device and method for fabricating the same: A semiconductor device includes a first field-effect transistor including a first gate electrode and a second field-effect transistor including a second gate electrode. The first gate electrode and the second gate electrode are integrated using a connecting portion and are fully silicided with a metal in such a manner that... Agent: Mcdermott Will & Emery LLP

20070093018 - Dielectric material forming methods and enhanced dielectric materials: A dielectric material forming method includes forming a first monolayer and forming a second monolayer on the first monolayer, one of the first and second monolayers comprising tantalum and oxygen and the other of the first and second monolayers comprising oxygen and another element different from tantalum. A dielectric layer... Agent: Wells St. John P.s.

20070093019 - Method for producing a connection electrode for two semiconductor zones arranged one above another: Method for producing a connection electrode for two semiconductor zones arranged one above another The invention relates to a method for producing a connection electrode for a first semiconductor zone and a second semiconductor zone, which are arranged one above another and are doped complementarily with respect to one another,... Agent: Maginot, Moore & Beck Chase Tower

20070093020 - Methods of forming non-volatile memory devices and devices formed thereby: Methods of forming non-volatile memory devices include steps to define features that enhance shielding of electronic interference between adjacent floating gate electrodes and improve leakage current and threshold voltage characteristics. These features also support improved leakage current and threshold voltage characteristics in string selection transistors that are coupled to non-volatile... Agent: Myers Bigel Sibley & Sajovec

20070093021 - Mos transistor with recessed gate and method of fabricating the same: A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at... Agent: Marger Johnson & Mccollom, P.C.

20070093022 - Integrated circuitry: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is... Agent: Wells St. John P.s.

20070093025 - Etch stop layer in poly-metal structures: In accordance with one embodiment of the present invention, a method of interfacing a poly-metal structure and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the structure. The present invention also addresses the relative location of the etch stop layer in... Agent: Dinsmore & Shohl LLP

20070093023 - Non-volatile memory and fabricating method thereof: A non-volatile memory. The non-volatile memory comprises a substrate, a conductive layer, a charge storage layer, several first doped regions and several second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is located over the substrate, wherein the conductive layer fills in the trenches.... Agent: J.c. Patents, Inc. Suite 250

20070093024 - Split gate flash memory cell and fabrication method thereof: A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the... Agent: Birch Stewart Kolasch & Birch

20070093026 - Method of making thin silicon sheets for solar cells: A thin layer of single-crystal silicon is produced by forming first trenches in a silicon substrate having (111) orientation; forming narrower second trenches at the base of the trenches; anisotropically etching lateral channels (4) from the second trenches, until adjacent etch fonts (16) substantially meet; and detaching said layer from... Agent: Woodcock Washburn LLP

20070093027 - Semiconductor integrated circuit and fabrication process thereof: A semiconductor integrated circuit that includes thereon a flash memory and a plurality of MOS transistors using different power supply voltages is formed by a process in which a thermal oxidation process is applied to one of the device regions while covering the other device regions by an oxidation-resistant film.... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070093028 - Graded junction high voltage semiconductor device: A graded junction space decreasing an implant concentration gradient between n-well and p-well regions of a semiconductor device is provided for enhancing breakdown voltage in high voltage applications. Split or unified FOX regions may be provided overlapping with the graded junction space. By using a p-well blocking layer to separate... Agent: Merchant & Gould PC

20070093029 - Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods: A method of generating a layout of one or more planar double gate transistors can include generating a single gate transistor layout at least in part from one or more double gate transistor circuits, logic diagrams, or any combination thereof, and generating the planar double gate transistor layout at least... Agent: Larson Newman Abel Polansky & White, LLP

20070093030 - Reduction of boron diffusivity in pfets: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify... Agent: Whitham, Curtis & Christofferson, P.C.

20070093032 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070093031 - Methods of removing photoresist and fabricating semiconductor devices: A method for increasing the removal rate of a photoresist layer used as an ion implant mask. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the... Agent: Jianq Chyun Intellectual Property Office

20070093033 - Ultra shallow junction formation by solid phase diffusion: An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode,... Agent: Tung & Associates Suite 120

20070093034 - Methods of forming semiconductor constructions: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein... Agent: Wells St. John P.s.

20070093035 - Circuit board materials with improved bond to conductive metals and methods of the manufacture thereof: Use of a roughened dielectric layer between a dielectric substrate and a conductive layer, which allows increased adhesion between layers without the conductor loss associated with roughened conductor layers, as well as improved accuracy in etching. The method is widely applicable to a variety of dielectric substrate and conductive layer... Agent: Cantor Colburn, LLP

20070093036 - Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon... Agent: James R. Nock IBM Corporation, Dept. 917

20070093037 - Vertical structure semiconductor devices and method of fabricating the same: The present invention provides a vertical structure semiconductor device and method of fabricating the same. The method comprises providing a sapphire substrate bonded to a bottom surface of a semiconductor wafer, and a metal coated to the top surface of the semiconductor wafer. The method also comprises securely bonding a... Agent: Patent Docket Administrator Lowenstein Sandler PC

20070093038 - Method for making microchips and microchip made according to this method: Microchips have a first surface and a second surface, which second surface is opposite the first surface. Microelectronic structures are fabricated at the first surface. At least two layers of lacquer are deposited on the second surface of the microchip; however, any two contiguous layers have different mechanical properties.... Agent: Slater & Matsil LLP

20070093040 - Production method for device: A production method for devices includes: a bonding process for placing circuit surfaces of other divided plural semiconductor chips onto circuit surfaces of semiconductor chips of a wafer and bonding the other semiconductor chips to the semiconductor chips of the wafer; and a semiconductor chip grinding process for grinding rear... Agent: Brinks Hofer Gilson & Lione

20070093039 - Tools and methods for disuniting semiconductor wafers: A tool and method for disuniting two wafers, wherein at least one of the wafers is used in fabricating substrates for microelectronics, optoelectronics, or optics. The method includes the steps of temporarily affixing two gripper members to respective opposite faces of the wafers; and sufficiently displacing one of the gripper... Agent: Winston & Strawn LLP Patent Department

20070093041 - Compound semiconductor device and method of manufacturing the same: A method of manufacturing a compound semiconductor device comprises forming a scribed groove extending from an edge of a major surface of a laminated body to an internal region on the first major surface. The laminated body has the first major surface and a second major surface and is formed... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070093042 - Bit line implant: A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures... Agent: Harrity Snyder, L.L.P.

20070093043 - Semiconductor structure with reduced gate doping and methods for forming thereof: A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a... Agent: Freescale Semiconductor, Inc. Law Department

20070093044 - Method of depositing a metal layer onto a substrate and a method for measuring in three dimensions the topographical features of a substrate: A method of coating a substrate is disclosed in which a gas is activated using an electron beam. The coated substrate is then sliced using a particle beam to reveal, in cross-section, features of the resist. Those features of the resist are measured using a scanning electron microscope and a... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070093046 - Cmosfet with hybrid-strained channels: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from... Agent: Haynes And Boone, LLP

20070093045 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to manufacture a micromachine having a plurality of structural bodies with different functions and to shorten the time required for sacrifice layer etching in a process of manufacturing the micromachine. Another object of the present invention is to prevent a structural layer... Agent: Fish & Richardson P.C.

20070093047 - Semiconductor device and method for fabricating the same: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions.... Agent: Mcdermott Will & Emery LLP

20070093048 - Method for forming metal line of semiconductor device: A method for forming a metal line of a semiconductor device uses a low dielectric constant material as an interlayer dielectric layer and treats a surface of the interlayer dielectric layer with plasma to prevent moisture and ammonia from being adsorbed in the low dielectric constant material. The method for... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070093049 - Electronic interconnects and methods of making same: A method for making an interconnect is provided. The method includes depositing a conductive layer on a substrate, depositing a protective layer on the conductive layer, patterning the protective layer to form openings to the conductive layer, depositing contact pads on the conductive layer through the openings in the protective... Agent: Patrick S. Yoder Fletcher Yoder

20070093050 - Interconnection structures for semiconductor devices and methods of forming the same: An interconnection structure includes an inter-level insulation layer disposed on a semiconductor substrate. First contact structures are formed in the inter-level insulation layer. Second contact structures are formed in the inter-level insulation layer and are spaced apart from the first contact structures. First spacers are disposed between the first contact... Agent: Myers Bigel Sibley & Sajovec

20070093051 - Laminated structure, piezoelectric actuator and method of manufacturing the same: A laminated structure having an electrode hard to peel off and a method of manufacturing the laminated structure. The laminated structure has: a backing substrate; a lower electrode including an adhesive layer containing a metal oxide and a conductive layer formed on the backing substrate with the adhesive layer therebetween;... Agent: Sughrue Mion, PLLC

20070093052 - Semiconductor device have multiple wiring layers and method of producing the same: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070093053 - Method of fabricating interconnect structure: A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first porous low-k layer to electrically connect... Agent: Jianq Chyun Intellectual Property Office

20070093054 - Multiple device types including an inverted-t channel transistor and method therefor: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method... Agent: Freescale Semiconductor, Inc. Law Department

20070093055 - High-aspect ratio contact hole and method of making the same: A substrate has thereon a conductive region to be partially exposed by the contact hole, a contact etch stop layer overlying the substrate and covering the conductive region, and an inter-layer dielectric (ILD) layer on the contact etch stop layer. A photoresist pattern is formed on the ILD layer. The... Agent: North America Intellectual Property Corporation

20070093056 - Method for forming metal line and semiconductor device including the same: Disclosed is a technique of manufacturing a semiconductor device and a corresponding device. A metal line may be formed in a semiconductor device using a photoresist pattern with an oxide layer formed on the surface of a metal film, in accordance with embodiments. A heat-treatment process on a metal film... Agent: Sherr & Nourse, PLLC

20070093057 - Method of reducing charging damage to integrated circuits during semiconductor manufacturing: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the... Agent: North America Intellectual Property Corporation

20070093059 - Method and apparatus for thin film solar cell manufacturing: The present invention provides a method of making a Cu-In-Ga sputtering target by melting Cu, In and Ga, Cu and In or Cu and Ga to form a uniform melt with a pre-determined stoichiometry, which melt is sprayed to cause sprayed uniform melt particles to solidify into Cu-In-Ga particles with... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070093058 - Method for producing electric contact and electrical connector: A method for producing an electric contact extending from a copper foil, comprises steps of fixing a cover lay having a hole of a diameter smaller than that of the copper foil of a predetermined size to the copper foil, and plating the hole of the cover lay so as... Agent: Baker & Botts L.L.P.

20070093060 - Semiconductor device having a cu interconnection: A Cu interconnection in a semiconductor device has an ununiform profile of additive metal atoms wherein the additive metal atoms are rich in the vicinities of bottom and side surfaces of the Cu interconnection. The Cu interconnection also has an ununiform silicon profile wherein additive silicon atoms are rich in... Agent: Sughrue Mion, PLLC

20070093062 - Semiconductor device fabrication method: A method for fabricating a semiconductor device with a borderless via/wiring structure includes the steps of performing borderless via etching using a resist mask to form a contact hole in an interlevel dielectric layer over a semiconductor substrate so as to expose two different metal materials of lower layer patterns... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070093061 - Solvent removal of photoresist mask and gold impregnated residue and process: Solvent removal of photoresist mask and gold containing post-etch residues in the production of semiconductor wafer plasma etching is effectively conducted prior to further processing of the wafer. Using metallic iodine dissolved in a polar solvent system, the chemistry penetrates and quickly dissolves the photoresist mask while iodine complexes and... Agent: Arthur J. Plantamura General Chemical Performance Products LLC.

20070093063 - Method of chemical mechanical polishing and method of fabricating semiconductor device using the same: There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer... Agent: Myers Bigel Sibley & Sajovec

20070093065 - Method for manufacturing a semiconductor wafer: A method is used for manufacturing a semiconductor wafer. The back surface of a semiconductor wafer is ground. The back surface is cleaned with ozone water. The back surface of the semiconductor wafer is etched with a mixed acid that contains hydrofluoric acid and nitric acid. The cleaning and etching... Agent: Rabin & Berdo, PC

20070093064 - Polishing method of cu film and method for manufacturing semiconductor device: A method for polishing a Cu film comprises contacting a Cu film formed above a semiconductor substrate with a polishing pad attached to a turntable, and supplying a first chemical liquid which promotes the polishing of the Cu film and a second chemical liquid which contains a surfactant, to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070093066 - Stacked wafer or die packaging with enhanced thermal and device performance: Some embodiments of the present invention include apparatuses and methods relating to stacked wafer or die packaging with enhanced thermal and device performance.... Agent: Blakely Sokoloff Taylor & Zafman

20070093068 - Manufacturing method of semiconductor device: A semiconductor device manufacturing method involves heating up a solution containing sulfuric acid and hydrogen peroxide solution, replenishing the solution with a predetermined quantity of sulfuric acid and a predetermined quantity of hydrogen peroxide solution at a predetermined interval, maintaining a concentration of the sulfuric acid in the solution at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070093067 - Wafer edge cleaning process: A method of processing a semiconductor wafer can be used prior to an immersion lithography process. The method includes providing a layer of organic photoresist onto a surface of the semiconductor wafer and removing a portion of the photoresist from an outer edge of the wafer using an edge-bead removal... Agent: Haynes And Boone, LLP

20070093069 - Purge process after dry etching: A purge process for a chip performed after a dry etching process is provided. The dry etching process is carried out inside a reaction chamber. The purge process is used to remove any byproducts produced by said dry etching process. The purge process includes injecting an inert gas into the... Agent: Jianq Chyun Intellectual Property Office

20070093070 - Triple layer anti-reflective hard mask: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective... Agent: Harrity Snyder, L.L.P.

20070093071 - Method and apparatus for processing a wafer: A method of a single wafer wet/dry cleaning apparatus comprising: a transfer chamber having a wafer handler contained therein; a first single wafer wet cleaning chamber directly coupled to the transfer chamber; and a first single wafer ashing chamber directly coupled to the transfer chamber.... Agent: Applied Materials/blakely

20070093072 - Epitaxial wafer and method for producing same: After cleaning the front and back sides of a silicon wafer with a liquid SC-1 and liquid SC-2, the front and back sides of the silicon wafer are cleaned with an HF solution to be water-repellent surfaces. Following that, an epitaxial layer of silicon is formed on the front side.... Agent: Greenblum & Bernstein, P.L.C

20070093073 - Technique for the growth and fabrication of semipolar (ga,a1,in,b)n thin films, heterostructures, and devices: A method for growth and fabrication of semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation,... Agent: Gates & Cooper LLP Howard Hughes Center

20070093074 - Ge-based semiconductor structure fabricated using a non-oxygen chalcogen passivation step: A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material... Agent: Scully Scott Murphy & Presser, PC

20070093075 - Method for using film formation apparatus: In a method for using a film formation apparatus for a semiconductor process, process conditions of a film formation process are determined. The process conditions include a preset film thickness of a thin film to be formed on a target substrate. Further, a timing of performing a cleaning process is... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070093076 - Electromagnetic treatment in atmospheric-plasma coating process: A plasma is produced in a treatment space (58) by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes (54,56) separated by a dielectric material (64), and a precursor material is introduced into the treatment space to coat a substrate... Agent: Antonio R. Durando

20070093077 - Method of forming a trench semiconductor device and structure therefor: In one embodiment, a trench semiconductor device is formed to have an oxide of a first thickness along the sidewalls of the trench, and to have a greater thickness along at least a portion of a bottom of the trench.... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070093078 - Porous insulating film, method for producing the same, and semiconductor device using the same: The present invention provides a process of producing a porous insulating film effective as an insulating film constituting a semiconductor device and a process of producing a porous insulating film having high adhesion to a semiconductor material, which is in contact with the upper and lower interfaces of the insulating... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070093079 - Imprinting method and imprinting apparatus: An imprinting method of the present invention is to press a mold member (40) having thereon a mold pattern onto a film carried on a principal plane of a substrate (50) as an object to be processed, so as to transfer the mold pattern to the film. A plurality of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070087454 - Method of fabricating a magnetic shift register: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/ or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of trench. A seed... Agent: Samuel A. Kassatly Law Office

20070087455 - Independent control of ion density, ion energy distribution and ion dissociation in a plasma reactor: A method of processing a workpiece in a plasma reactor includes coupling RF power from at least three RF power source of three respective frequencies to plasma in the reactor, setting ion energy distribution shape by selecting a ratio between the power levels of a first pair of the at... Agent: Robert M. Wallace Suite 102

20070087456 - Substrate processing method and substrate processing apparatus: According to the substrate processing method of the invention, a jet of droplets generated from a gas and a heated processing liquid is supplied to the surface of a substrate. A resist stripping liquid to strip off the resist from the surface of the substrate is then supplied to the... Agent: Ostrolenk Faber Gerb & Soffen

20070087457 - Method for inspecting and mending defect of photo-resist and manufacturing process of printed circuit board: A method for inspecting and mending defects of photo-resist is provided. It includes the following steps. First, a substrate having at least one film is provided. Then, a patterned photo-resist layer is formed on the film. Next, an optical inspection procedure is performed to inspect whether the patterned photo-resist layer... Agent: Jianq Chyun Intellectual Property Office

20070087460 - Method of fabricating nitride-based semiconductor laser diode: A method of manufacturing a nitride-based semiconductor laser diode that can minimize optical absorption on a cavity mirror plane and improve the surface roughness of the cavity mirror plane is provided. The method includes the steps of: forming on a (0001) GaN (gallium nitride) substrate having at least two masks... Agent: Buchanan, Ingersoll & Rooney PC

20070087459 - Patchwork patterned devices and related methods: Devices, such as light-emitting devices (e.g., LEDs), and methods associated with such devices are provided. A light-emitting device may include an interface including a first region and a second region. The first region having a dielectric function that varies spatially according to a first pattern, and the second region having... Agent: Wolf Greenfield & Sacks, PC

20070087458 - Semiconductor device and manufacturing method of the same: An RTA method has a limitation on miniaturization. The RTA method needs a heating time of several seconds, and has a risk that impurities are diffused into a deep portion, since a semiconductor substrate is heated at a high temperature. Thus, the RTA method has a difficulty in responding miniaturization... Agent: Eric Robinson

20070087461 - Light emitting diode and method for manufacturing the same: A light emitting diode is disclosed. The light emitting diode comprises: a transparent substrate; a reflective layer located on a surface of the transparent substrate; a solder layer located on the other surface of the transparent substrate; a semiconductor epitaxial structure located on the solder layer, wherein the semiconductor epitaxial... Agent: Baker & Hostetler LLP Suite 1100

20070087462 - Method of forming a device package having edge interconnect pad: A method of forming a device package having an edge interconnect pad includes forming an array of MEMS devices overlaying at least one conductive via that electrically connects to an underlying layer. The method continues with depositing, by way of a damascene process, a conductive material on a substrate that... Agent: Hewlett Packard Company

20070087463 - Pixel sensor having doped isolation structure sidewall: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure... Agent: Scully, Scott, Murphy & Pressner

20070087464 - Method for producing etched holes and/or etched trenches as well as a diaphragm sensor unit: A method for producing etched holes and/or etched trenches of components based on silicon and/or a layered silicon/insulator structure. A germanium-containing layer and/or a germanium layer is provided at the point in the etching direction at which or in whose surroundings an etching procedure is to be completed. Germanium and/or... Agent: Kenyon & Kenyon LLP

20070087465 - Micromechanical component having an anodically bonded cap and a manufacturing method: A micromechanical component includes a cap wafer made up of at least a first silicon substrate and a thin glass substrate, and having a functional wafer made up of at least a second silicon substrate, at least one electrical contact surface being disposed on the functional wafer. The cap wafer... Agent: Kenyon & Kenyon LLP

20070087466 - Integrated microphone: A method of forming a microphone having a variable capacitance first deposits high temperature deposition material on a die. The high temperature material ultimately forms structure that contributes to the variable capacitance. The method then forms circuitry on the die after depositing the deposition material. The circuitry is configured to... Agent: Bromberg & Sunstein LLP

20070087467 - Cmos image sensor: A method for forming an image sensor device. An alignment mark is formed on or in a substrate with distance from the alignment mark to the substrate edge less than about 3 mm. An array of active photosensing pixels is formed on the substrate. At least one dielectric layer is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070087468 - Method for producing electronic components: The invention relates to a method for producing electronic components comprising adjacent electrodes interspaced at distances ranging between 10 nanometers and several micrometers on a substrate of any type. According to the invention, the electrodes are structured by means of overlapping edges on the deposited layer or by undercutting the... Agent: Mayer & Williams PC

20070087469 - Particulate for organic and inorganic light active devices and methods for fabricating the same: A method of making polymer blend light active particles, comprising the steps of providing a solution comprised of a first organic light active diode material and a second organic light active diode material in a solvent and providing a non-solvent liquid. The method of making polymer blend light active particles... Agent: Michaud-duffy Group LLP

20070087470 - Vapor phase synthesis of metal and metal oxide nanowires: Vapor phase methods for synthesizing metal nanowires directly without the help of templates. A vapor phase method in which nucleation and growth of metal oxides at temperatures higher than the oxide decomposition temperatures lead to the respective metal nanowires. The chemical vapor transport of tungsten in the presence of oxygen... Agent: David W. Carrithers Carrithers Law Office, PLLC

20070087476 - Apparatus for improved power distribution in wirebond semiconductor packages: A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting... Agent: Texas Instruments Incorporated

20070087474 - Assembly process for out-of-plane mems and three-axis sensors: A method of assembling a three dimensional micromachined structure comprising the steps of defining a cavity in a holder wafer having a thick upper layer, providing a plurality of fingers in the thick upper layer extending from the holder wafer into the cavity, and disposing an out-of-plane wafer into the... Agent: Daniel L. Dawes Myers Dawes Andras & Sherman LLP

20070087475 - Method and apparatus for peeling surface protective film: A method and an apparatus for peeling a surface protective film attached on the surface of a semiconductor wafer are provided. A heating block is set in proximity to the whole surface of the semiconductor wafer, and the whole surface protective film is heated by the heating block. Thus, the... Agent: Christie, Parker & Hale, LLP

20070087473 - Method for manufacturing semiconductor package substrate: A method for manufacturing a semiconductor package is proposed. A circuit board with a circuit layer on at least one surface thereof is provided. The circuit board has at least one free area, and the circuit layer has a plurality of electrically connecting pads distributed on the periphery of the... Agent: Mr. Joseph A. Sawyer, Jr. Sawyer Law Group LLP

20070087472 - Methods for magnetically directed self assembly: A fluidic assembly method includes dispersing a number of functional blocks in a fluid to form a slurry. Each of the functional blocks includes at least one element and a patterned magnetic film comprising at least one region. The fluidic assembly method further includes immersing at least a portion of... Agent: General Electric Company Global Research

20070087478 - Semiconductor chip package and method for manufacturing the same: A semiconductor chip package mainly comprises an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The present invention is characterized in that the peripheral substrate... Agent: Lowe Hauptman Berner, LLP

20070087477 - Semiconductor device having a low-resistance bus interconnect, method of manufacturing same, and display apparatus employing same: s

20070087471 - Semiconductor package and method of manufacturing the same: A semiconductor package comprises a silicon substrate having an insulative surface; a patterned metal layer, formed on the insulative surface of the silicon substrate; an insulation layer formed on the patterned metal layer, and the patterned metal layer being partially exposed for functioning as at least a set of the... Agent: Bacon & Thomas, PLLC

20070087479 - Method of manufacturing low cte substrates for use with low-k flip-chip package devices: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one... Agent: Baker & Mckenzie On Behalf Of Tsmc

20070087480 - Chip package method: The present invention relates to a method for manufacturing a semiconductor chip package structure including the following steps. A substrate is provided. A plurality of chips are assembled onto the substrate and are electrically connected with the substrate. A stiffener is assembled onto the substrate and the stiffener has a... Agent: Jianq Chyun Intellectual Property Office

20070087481 - Underfill aiding process for a tape: A tape having a predetermined area is provided for a chip. A hole is drilled within the predetermined area. The chip is adhered to the predetermined area by underfilling an underfill material between the chip and the tape from one side of the chip. By the hole, the invention provides... Agent: Lowe Hauptman Berner, LLP

20070087482 - Method and apparatus for operating nonvolatile memory cells with modified band structure: A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the nonvolatile memory cell, the band... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070087483 - Heat sink and method for its production: A method for producing a heat sink for cooling a semiconductor device including forming plural base members, the base member being each in plate or block-shape, the base member each having paths shaped on one or both sides of surfaces thereof, and the base member each having connecting regions on... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087484 - Heating element of a printhead having resistive layer over conductive layer: A heating element of a printhead has a conductive layer deposited over a substrate, and a resistive layer deposited over and in electrical contact with the conductive layer.... Agent: Hewlett Packard Company

20070087485 - Methods for fabricating polysilicon film and thin film transistors: A method for fabricating polysilicon film is disclosed. First, a first substrate is provided, wherein a plurality of sunken patterns has been formed on the front surface of the first substrate. Then, a second substrate is provided and an amorphous polysilicon film is formed on the second substrate. Next, the... Agent: Jianq Chyun Intellectual Property Office

20070087489 - Organic thin film transistor, method of manufacturing the same, and flat panel display comprising the same: The organic TFT includes: a gate electrode; source and drain electrodes insulated from the gate electrode; an organic semiconductor layer insulated from the gate electrode and electrically connected to the source and drain electrodes; an insulating layer insulating the gate electrode from the source and drain electrodes and the organic... Agent: Stein, Mcewen & Bui, LLP

20070087487 - Semiconductor device and manufacturing method thereof: An object is to obtain a semiconductor device with improved characteristics by reducing contact resistance of a semiconductor film with electrodes or wirings, and improving coverage of the semiconductor film and the electrodes or wirings. The present invention relates to a semiconductor device including a gate electrode over a substrate,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070087488 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to control the plane orientation of crystal grains obtained by using a laser beam, into a direction that can be substantially regarded as one direction in an irradiation region of the laser beam. After forming a cap film over a semiconductor film,... Agent: Nixon Peabody, LLP

20070087486 - Thin-film transistor, tft-array substrate, liquid-crystal display device and method of fabricating the same: A thin-film transistor includes a gate layer, a gate insulting layer, a semiconductor layer, a drain layer, a passivation layer (each of which being formed on or over an insulating substrate), and a conductive layer formed on the passivation layer. The conductive layer is connected to the gate layer or... Agent: Mcginn Intellectual Property Law Group, PLLC

20070087490 - Thin film transistor and method of fabricating the same: A bottom gate thin film transistor and method of fabricating the same are disclosed, in which a channel region is crystallized by a super grain silicon (SGS) crystallization method, including: forming a gate electrode and a gate insulating layer on an insulating substrate; forming an amorphous silicon layer on the... Agent: H.c. Park & Associates, PLC

20070087491 - Transistor and method of fabricating the same: Disclosed is a method for fabricating a gate of a field effect transistor. The method comprises a) forming a field oxide layer on a silicon substrate and then applying a photoresist layer in order to define a gate, b) etching the silicon substrate using the photoresist layer as a mask,... Agent: Marger Johnson & Mccollom, P.C.

20070087492 - Method for forming semiconductor film, method for manufacturing semiconductor device and electrooptic device, apparatus for performing the same, and semiconductor device and electrooptic device: An object of the present invention is to provide a method for easily forming a polycrystalline semiconductor thin-film, such as polycrystalline silicon having high crystallinity and high quality, or a single crystalline semiconductor thin-film at inexpensive cost, the crystalline semiconductor thin-film having a large area, and to provide an apparatus... Agent: David R. Metzger Sonnenschein Nath & Rosenthal

20070087493 - Trench schottky device with single barrier: A process for forming a trench Schottky barrier device includes the forming of an oxide layer within the trenches in the surface of a silicon wafer, and then depositing a full continuous metal barrier layer over the full upper surface of the wafer including the trench interiors and the mesas... Agent: Ostrolenk Faber Gerb & Soffen

20070087494 - Method of manufacturing a semiconductor apparatus: A method of manufacturing a semiconductor apparatus of the present invention comprises forming body diffusion layer, a gate electrode, and an interlayer dielectric over an surface of a semiconductor substrate, forming a photoresist having an opening in a region overlapping with a part of the body diffusion layer, removing the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070087495 - Photomask and method for manufacturing thin film transistor: An exemplary photomask (150) has a slit. The slit has at least one turning region (D1) and at least one other regions, and the slit at the at least one turning region has a narrower width than the slit at the at least one other regions. An exemplary method for... Agent: Wei Te Chung Foxconn International, Inc.

20070087496 - Non-volatile memory devices including fuse covered field regions: A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse An isolation layer is configured to isolate the... Agent: Myers Bigel Sibley & Sajovec

20070087497 - Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer... Agent: J C Patents, Inc.

20070087498 - Methods of forming buried bit line dram circuitry: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within... Agent: Wells St. John P.s.

20070087501 - Semiconductor device and manufacturing method thereof: A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so as to protrude from a surface opposite to a semiconductor substrate 1... Agent: Miles & Stockbridge PC

20070087500 - Semiconductor device and method of manufacturing the same: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer... Agent: Marger Johnson & Mccollom, P.C.

20070087499 - Semiconductor memory device with vertical channel transistor and method of fabricating the same: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars... Agent: Mills & Onello LLP

20070087503 - Improving nrom device characteristics using adjusted gate work function: A method including adjusting a threshold voltage of an NROM (nitride, read only memory) device by adjusting a work function associated with a gate terminal of the NROM device.... Agent: Eitan Law Group C/o Landonip Inc.

20070087504 - Integration process flow for flash devices with low gap fill aspect ratio: A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with... Agent: Parsons Hsue & De Runtz LLP

20070087505 - Method of forming a semiconductor device: In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxidation. In a preferred embodiment, these steps are clustered and transportation... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070087506 - Method of forming a semiconductor device: In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxidation. In a preferred embodiment, these steps are clustered and transportation... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070087502 - Method of forming flash cell array having reduced word line pitch: A method of forming a NAND Flash memory device comprises forming a control gate polysilicon layer over a substrate, forming a mask layer over the control gate polysilicon layer, the mask layer including a mask pattern defining a plurality of spaced word lines of the FLASH memory device, the word... Agent: Duane Morris, LLPIPDepartment

20070087507 - Crystalline-type device and approach therefor: Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material is crystallized to form the single-crystal region using an... Agent: Crawford Maunu PLLC

20070087508 - Method for making a p-i-n diode crystallized adjacent to a silicide in series with a dielectric antifuse: A method is described for forming a nonvolatile one-time-programmable memory cell having reduced programming voltage. A contiguous p-i-n diode is paired with a dielectric rupture antifuse formed of a high-dielectric-constant material, having a dielectric constant greater than about 8. In preferred embodiments, the high-dielectric-constant material is formed by atomic layer... Agent: Vierra Magen/sandisk Corporation

20070087509 - Semiconductor device and method of manufacturing the same: There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087510 - Semiconductor devices and manufacturing methods of the same: A semiconductor device may include first and second silicon layers formed over a semiconductor substrate. An insulating layer may be formed between first and second silicon layers. A gate insulating layer, a gate electrode, and a spacer may be formed over a second silicon layer. A source/drain impurity area may... Agent: Sherr & Nourse, PLLC

20070087511 - Method for forming an avalanche photodiode: Methods for fabricating an avalanche photodiode (APD), wherein the APD provides both high optical coupling efficiency and low dark count rate. The APD is formed such that it provides an active region of sufficient width to enable high optical coupling efficiency and a low dark count rate. Some APDs fabricated... Agent: Demont & Breyer, LLC

20070087512 - Substrate embedded with passive device: A method for manufacturing a substrate embedded with a passive device, comprising the steps of (a) molding the passive device and (b) mounting the molded passive device in a cavity formed on the substrate, is disclosed. The substrate embedded with a passive device and the manufacturing method thereof in accordance... Agent: Staas & Halsey LLP

20070087513 - Method for forming a variable capacitor: A method for forming a variable capacitor including a conductive strip covering the inside of a cavity, and a flexible conductive membrane placed above the cavity, the cavity being formed according to the steps of: forming a recess in the substrate; placing a malleable material in the recess; having a... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070087514 - Soi substrate with selective oxide layer thickness control: A method for forming a SOI substrate device having multiple buried oxide regions comprising the steps of; forming a thin buried oxide layer in a silicon-containing substrate, forming a mask with openings therein on the substrate, implanting oxygen into the substrate through the openings in the mask, forming a buried... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087522 - Dielectric gap fill with oxide selectively deposited over silicon liner: A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the... Agent: Townsend And Townsend And Crew LLP / Amat

20070087521 - Fabrication method of semiconductor device: Fabrication method of semiconductor device to reduce leak current at junction interface of p-type well and n-type well. The method comprises forming a first trench portion 109 by selective dry etching of a silicon substrate 101 using a first etching gas and forming a second trench portion 113 including an... Agent: Young & Thompson

20070087515 - Low stress sti films and methods: The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive stress STI films will generally exhibit a compressive stress of less... Agent: Townsend And Townsend And Crew LLP / Amat

20070087519 - Method and structure for double lining for shallow trench isolation: A method of forming an integrated circuit device structure having a design rule of less than 0.13 micron. The method includes providing a substrate and forming a pad oxide layer overlying the substrate. The method includes forming a nitride layer overlying the pad oxide layer and patterning the nitride layer... Agent: Townsend And Townsend And Crew, LLP

20070087516 - Method for forming an isolating trench with a dielectric material: The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an isolating trench in a memory device.... Agent: Morrison & Foerster LLP

20070087520 - Method for manufacturing semiconductor device: A semiconductor device includes an element isolation film, which exhibits less variations in the height dimension from the surface of the substrate and has a desired height dimension from the surface of the substrate. A process for manufacturing a semiconductor device includes: providing a predetermined pattern of a silicon nitride... Agent: Young & Thompson

20070087517 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device including forming a pad oxide layer on a semiconductor substrate, forming a spacer oxide layer pattern on sidewalls of the pad oxide layer, and forming a nitride layer on the pad oxide layer. The method further includes forming a groove in the nitride... Agent: Jong-woon Choi

20070087518 - Semiconductor device and method for producing the same: A method for forming STIs in a semiconductor substrate includes forming a protective oxide film on the semiconductor substrate and forming a silicon nitride film on the protective oxide film, performing a photolithography and a dry etching so as to penetrate the silicon nitride film and the protective oxide film... Agent: Hamre, Schumann, Mueller & Larson P.C.

20070087523 - Recessed shallow trench isolation: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees. In some embodiments, a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070087524 - Wafer singulation process: A method of singulating a semiconductor die from a wafer is provided. The method includes etching or cutting several trenches into the wafer from a front surface of the wafer, such that each trench extends along an entire side of the die; depositing a passivation layer into the trenches to... Agent: Ostrolenk Faber Gerb & Soffen

20070087525 - Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a... Agent: Ibm Corporation, T.j. Watson Research Center

20070087527 - Method and device for bonding wafers: The invention relates to a method and a device (1) for bonding wafers (6, 9). Here at least one wafer surface is first wetted with a molecular dipolar compound, whereupon the wafers are brought into contact with each other. The bonding of the wafers then takes place by means of... Agent: Kusner & Jaffe Highland Place Suite 310

20070087528 - Method and structure for vertically-stacked device contact: Method and structure for vertically stacking microelectronic devices are disclosed. Subsequent to appropriate deposition, patterning, trenching, and passivation subprocesses, a conductive layer is formed wherein one end comprises an external contact portion for C4 interfacing, and another end establishes electrical contact with an internal contact at the bonding interface between... Agent: David C. Lundmark Intel Corporation, Sc4-202

20070087526 - Method of recycling an epitaxied donor wafer: A method for forming a semiconductor structure comprising a thin layer of semiconductor material on a receiver wafer is disclosed. The method comprises removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the... Agent: Winston & Strawn LLP Patent Department

20070087529 - Simulation method of wafer warpage: Disclosed is a simulation method for determining wafer warpage. This method includes dividing layers and evaluating a composition ratio of materials composing the layers. The method mathematically transforms a semiconductor device, which is constructed as a complicated structure with various materials, into a simplified, mathematically equivalent stacked structure comprising a... Agent: Mills & Onello LLP

20070087530 - Detection of seed layers on a semiconductor device: A device and/or method which detects a seed layer and a device and/or method of forming layers on a semiconductor device. The device which forms layers on the semiconductor device may include a metal layer forming unit (which forms a metal layer on a wafer), a copper seed layer forming... Agent: Sherr & Nourse, PLLC

20070087531 - Method and apparatus for flag-less water bonding tool: Embodiments in accordance with the present invention relate to methods and apparatuses for bonding together substrates in a manner that suppresses the formation of voids between them. In a specific embodiment, a backside of each substrate is adhered to a front area of flexible, porous chuck having a rear area... Agent: Townsend And Townsend And Crew, LLP

20070087532 - Method for applying a structure of joining material to the back surfaces of semiconductor chips: A structure of joining material is applied to the back surfaces of semiconductor chips in manufacturing semiconductor devices. The joining material is applied, in finely metered and structured form via a joining material jet appliance, to the back surfaces of the semiconductor chips of a divided semiconductor wafer.... Agent: Edell, Shapiro & Finnan, LLC

20070087534 - Electro-optical device, method of manufacturing the same, electronic apparatus, and semiconductor device: An electro-optical device includes: a substrate; a plurality of pixel units provided in a display region on the substrate; and a driving circuit that is provided in a peripheral region surrounding the display region and includes semiconductor elements that drive the plurality of pixel units, each of the semiconductor elements... Agent: Oliff & Berridge, PLC

20070087533 - Gas ring and method of processing substrates: A process gas to a reactor volume of a semiconductor processing reactor is provided through gas injector ports of a gas ring. The process gas flows horizontally from the gas injector ports across a principal surface of a rotating susceptor to exhaust ports of the gas ring. The spent process... Agent: Gunnison Mckay & Hodgson, LLP Garden West Office Plaza, Suite 220

20070087535 - Semiconductor device: A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor T including a source region, a drain region, a channel region having a predetermined channel length, a first GOLD region having an impurity concentration... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087537 - Manufacturing method of semiconductor device: A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film.... Agent: Reed Smith LLP

20070087536 - Mosfet structure with multiple self-aligned silicide contacts: A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface... Agent: Scully, Scott, Murphy & Presser, P.C.

20070087538 - Method of manufacturing nand flash memory device: A method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; stripping the buffer oxide film at one side... Agent: Marshall, Gerstein & Borun LLP

20070087539 - Method for manufacturing compound semiconductor epitaxial substrate: A method for manufacturing a compound semiconductor epitaxial substrate with few concave defects is provided. The method for manufacturing a compound semiconductor epitaxial substrate comprises a step of epitaxially growing an InGaAs layer on an InP single crystal substrate or on an epitaxial layer lattice-matched to the InP single crystal... Agent: Fitch, Even, Tabin & Flannery

20070087540 - Transistor having high mobility channel and methods: Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is... Agent: Hoffman, Warnick & D'alessandro LLC

20070087541 - Method and apparatus for deposition & formation of metal silicides: Disclosed is a method and structure for forming a silicide on a silicon material. The invention places the silicon material in a vacuum environment, forms metal on the silicon material, and then heats the silicon surface and the metal without breaking the vacuum environment. The processes of forming the metal... Agent: Frederick W. Gibb, Iii Mcginn & Gibb, PLLC

20070087542 - Method of forming a silicide: At least one gate electrode is formed on a substrate. A first dielectric layer and a second dielectric layer are formed on the gate electrode, respectively. A portion of the second dielectric layer is removed to form a spacer on either side of the gate electrode. A portion of the... Agent: North America Intellectual Property Corporation

20070087543 - Fuse structure having reduced heat dissipation towards the substrate: A fuse structure (100) suitable for incorporation in an integrated circuit presents a reduced thermal conduction foot-print to the substrate (103). A patterned material stack (102) is formed on a substrate (103) and at least a portion of a material disposed between the substrate (103) and an upper portion of... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070087544 - Method for forming improved bump structure: Methods for forming an improved bump structure on a semiconductor device are provided. In one embodiment, a substrate is provided having at least one contact pad formed thereon. A first passivation layer is formed over the substrate, the first passivation layer having at least one opening therein exposing a portion... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070087545 - Method of manufacturing image display device: The present application relates to a method of manufacturing an image display device. The manufacturing method includes a step of arranging a side wall made of metal extending along an inner peripheral edge of a front substrate or a back substrate on the inner peripheral edge in a state that... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087546 - Etchant and method for forming bumps: A method for forming bumps is disclosed. First, a substrate having an adhesive, a barrier, and a wetting layer thereon is provided. Next, a patterned photoresist is formed on the wetting layer, in which the patterned photoresist includes at least one opening for exposing a portion of the wetting layer.... Agent: North America Intellectual Property Corporation

20070087548 - Method for forming bumps: A method for forming bumps is disclosed. First, a substrate having a surface and an under bump metallurgy layer formed thereon is provided, and a portion of the under bump metallurgy layer is removed thereafter. Next, a mask having a metal layer thereon is disposed over the surface of substrate,... Agent: North America Intellectual Property Corporation

20070087549 - Method of manufacturing a wire grid polarizer: A dielectric layer 2 is formed on a region including grid-shaped convex portions 1a of a resin substrate 1 having the grid-shaped convex portions 1a with pitches of 80 nm to 120 nm on its surface, and metal wires 3 are formed on the dielectric layer 2. It is thereby... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070087547 - Wafer structure with electroless plating metal connecting layer and method for fabricating the same: A wafer structure with an electroless plating metal connecting layer and a method for fabricating the same are proposed. A wafer has an active surface and an inactive surface opposite to the active surface. The active surface has a plurality of electrical connecting pads formed thereon. An insulating protective layer... Agent: Mr. Joseph A. Sawyer, Jr. Sawyer Law Group LLP

20070087550 - Low-voltage single-layer polysilicon eeprom memory cell: The present invention is an electronic memory cell and a method for the cell's fabrication comprising a The first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell.... Agent: Schneck & Schneck

20070087552 - Method for simulating the movement of particles: A method for determining the movement of particles, particularly impurities, in a medium, under the influence of a changing interface between two neighboring phases. In a first step, the temporal and/or local evolution of said interface is determined. In a second step, the movement of said particles in dependence of... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20070087551 - Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner: The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least... Agent: Scully, Scott, Murphy & Pressner

20070087553 - Semiconductor component and method for contracting said semiconductor component: The semiconductor component has several regularly arranged active cells (1), each comprising at least one main defining line (8). A bonding wire (18, 20) is fixed to at least one bonding surface (14, 16) by bonding with a bonding tool, oscillating in a main oscillation direction (22, 24), for external... Agent: Baker Botts L.L.P. Patent Department

20070087554 - Interconnection structure with low dielectric constant: A method for producing an interconnection structure including at least one insulating layer having a low dielectric constant and at least one metal connection element coated with a support layer and capable of connecting to at least one conductive area of a microelectronic device. The interconnection structure has an improved... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087555 - Interconnection structure with low dielectric constant: An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the... Agent: Hoffman, Warnick & D'alessandro LLC

20070087556 - Method and mesh reference structures for implementing z-axis cross-talk reduction through copper sputtering onto mesh reference planes: A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070087558 - Semiconductor device having isolation pattern in interlayer insulating layer between capacitor contact plugs and methods of fabricating the same: A semiconductor device having an isolation pattern inside an interlayer insulating layer between capacitor contact plugs and methods of fabrication the same: The semiconductor device includes an interlayer insulating layer covering a semiconductor substrate. At least two contact plugs passing the interlayer insulating layer and connected to the semiconductor substrate.... Agent: Marger Johnson & Mccollom, P.C.

20070087559 - Semiconductor device manufacturing method: A semiconductor device manufacturing method is provided which is capable of suppressing variation of the resistance value of resistive interconnection and preventing variation of transistor performance. A gate electrode and a resistive interconnection are formed on a substrate and impurity ions are implanted into the surface of the substrate to... Agent: Mcdermott Will & Emery LLP

20070087557 - Semiconductor device with a toroidal-like junction: Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited... Agent: Schneck & Schneck

20070087561 - Method for making an opening for electrical contact by etch back profile control: A method and apparatus for etchback profile control. The method includes performing a first etch through a first dielectric layer to form a first via and a second dielectric layer, filling the first via with a BARC material to form a first BARC layer, and performing a second etch on... Agent: Townsend And Townsend And Crew, LLP

20070087560 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate support in a process chamber, pre-heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 60 seconds or more, forming a... Agent: F. Chau & Associates, LLC

20070087562 - Method of fabricating semiconductor device by exposing upper sidewalls of contact plug to form charge storage electrode: According to some embodiments, a method includes forming at least two contact plugs that penetrate an insulating layer to connect with a semiconductor substrate. The contact plugs have an upper surface and upper sidewalls that are higher than a top surface of the insulating layer. An etch stop covers the... Agent: Marger Johnson & Mccollom, P.C.

20070087563 - Zirconium-doped tantalum oxide films: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070087564 - Method of forming an electronic device: A method of forming an electronic circuit component using the technique of drop on demand printing to deposit droplets of deposition material, said method comprising depositing a plurality of droplets on a surface to form a patterned electronic device comprising multiple discrete portions.... Agent: Wolf Greenfield & Sacks, PC

20070087565 - Methods of forming isolation regions and structures thereof: Methods of forming isolation regions for semiconductor devices and structures thereof are disclosed. A workpiece having a top surface is provided, a chemical mechanical polish (CMP) stop layer is formed over the workpiece, and a sacrificial material is formed over the CMP stop layer. The sacrificial material, the CMP stop... Agent: Slater & Matsil LLP

20070087566 - Controlled electroless plating: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine... Agent: Freescale Semiconductor, Inc. Law Department

20070087567 - Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization, and resultant structures: Copper-based metallization is formed in a trench on an integrated circuit substrate by forming a liner of refractory metal in the trench using physical vapor deposition, forming a copper plating seed layer on the liner using physical vapor deposition and then plating copper on the copper plating seed layer. Prior... Agent: Myers Bigel Sibley & Sajovec

20070087568 - Apparatus for etching wafer by single-wafer process and single wafer type method for etching wafer: An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating... Agent: Kolisch Hartwell, P.C.

20070087569 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a plurality of gate patterns over a substrate, each gate pattern comprising a hard mask and a gate electrode, forming a photoresist layer over the gate patterns, performing a planarizing process until the hard masks of the gate patterns are exposed... Agent: Blakely Sokoloff Taylor & Zafman

20070087570 - Planarization of a heteroepitaxial layer: A method of planarization of a surface of a heteroepitaxial layer by chemical-mechanical polishing the disturbed surface of the heteroepitaxial layer with a polishing pad having a compressibility greater than 2% and less than 15% and a slurry comprising at least 20% of silica particles having an average diameter between... Agent: Winston & Strawn LLP Patent Department

20070087571 - Etching bias reduction: A patterning device for implementing a pattern on a substrate includes a main pattern feature and a sacrificial pattern feature. Both the main pattern feature and the sacrificial pattern feature are transferable to an overlying layer on the substrate. The sacrificial pattern feature is positioned a distance from the main... Agent: Haynes And Boone, LLP

20070087572 - Method and apparatus for the improvement of material/voltage contrast: A method for observing voltage contrast from buried structures in SOI. The method includes depositing a thin transparent metal layer over the BOx to dissipate charging of the oxide, and using a low FIB beam current to avoid damage due to ion implantation and direct ion beam damage.... Agent: Deborah Wenocur C/o Shelly Garrett

20070087573 - Pre-treatment method for physical vapor deposition of metal layer and method of forming metal silicide layer: A pre-treatment method for physical vapor deposition of a metal layer is provided. A substrate is first provided and then a dry cleaning process is performed to the substrate using a chemical etching process, in which the chemical etching process causes a reaction to the oxide. Thereafter, an annealing process... Agent: J.c. Patents, Inc.

20070087577 - Barrier metal film production apparatus, barrier metal film production method, metal film production method, and metal film production apparatus: A Cl2 gas plasma is generated at a site within a chamber between a substrate and a metal member. The metal member is etched with the Cl2 gas plasma to form a precursor. A nitrogen gas is excited in a manner isolated from the chamber accommodating the substrate. A metal... Agent: Birch Stewart Kolasch & Birch

20070087574 - Conformal doping apparatus and method: A method of doping includes depositing a layer of dopant material on nonplanar and planar features of a substrate. Inert ions are generated from an inert feed gas. The inert ions are extracted towards the substrate where they physically knock the dopant material into both the planar and nonplanar features... Agent: Rauschenbach Patent Law Group, LLC

20070087575 - Method for fabricating silicon nitride spacer structures: Embodiments of methods for fabricating a spacer structure on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a spacer structure on a semiconductor substrate includes providing a substrate containing a base structure over which the spacer structure is to be formed. The spacer structure may... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070087576 - Substrate susceptor for receiving semiconductor substrates to be deposited upon: In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includes a body having a front substrate receiving side, a back side, and a... Agent: Wells St. John P.s.

20070087578 - Ion beam sputtering apparatus and film deposition method for a multilayer for a reflective-type mask blank for euv lithography: A film deposition method for a multilayer for a EUV mask blank by which a defect caused by the mixing of a particle in the layer during film formation can be prevented and an ion beam sputtering apparatus suitable for the method are presented. A film deposition method for forming... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070087580 - Composition for removing an insulation material, method of removing an insulation layer and method of recycling a substrate using the same: In one aspect, a composition is provided which is capable of removing an insulation material which includes at least one of a low-k material and a passivation material. The composition of this aspect includes about 5 to about 40 percent by weight of a fluorine compound, about 0.01 to about... Agent: Volentine Francos, & Whitt PLLC

20070087579 - Semiconductor device manufacturing method: A semiconductor device manufacturing method by which a process chamber can be self-cleaned, while keeping a temperature in the process chamber low or a semiconductor device manufacturing method by which a high-k film adhering in the process chamber can be effectively removed. The method is provided with a pre-coat process,... Agent: Oliff & Berridge, PLC

20070087581 - Technique for atomic layer deposition: A technique for atomic layer deposition is disclosed. In one particular exemplary embodiment, the technique may be realized by a method for forming a strained thin film. The method may comprise supplying a substrate surface with one or more precursor substances having atoms of at least one first species and... Agent: Hunton & Williams LLP/varian Semiconductor, Equipment Associates, Inc.

20070087582 - Gas jet reduction of iso-dense field thickness bias for gapfill process: A system and method affecting mass transport to reduce or eliminate iso-dense bias in spin-on-dielectric (SOD) or spin-on-glass (SOG) processes use a nozzle to dispense the liquid dielectric and a separate nozzle for jetting N2 or other gas onto a semiconductor wafer. The gas is jetted onto the wafer shortly... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070087583 - Method of forming a silicon oxynitride layer: A SiOxNy gate dielectric and a method for forming a SiOxNy gate dielectric by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 and then exposing the structure to a plasma comprising a nitrogen source are provided. In one aspect, the structure... Agent: Patterson & Sheridan, LLP

20070087584 - Plasma doping method and plasma doping apparatus for performing the same: In a method of doping ions into an object, such as a substrate, using plasma, a doping gas may be provided between first and second electrodes in a chamber. An electric field may be formed between the first and the second electrodes to excite the doping gas to a plasma... Agent: Lee & Morse, P.C.

20070082415 - Method of manufacturing a semiconductor device having a dual gate structure: A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic... Agent: Mills & Onello LLP

20070082414 - Perpendicular magnetic recording medium, method for production of the same, and magnetic recording apparatus: A perpendicular magnetic recording medium having compatibility between low noises and high thermal stability is provided. In the present medium having at least an underlayer, a magnetic recording layer, a protective layer and a lubricant layer sequentially stacked on a nonmagnetic substrate, the underlayer is composed from at least one... Agent: Venable LLP

20070082416 - Semiconductor device: A trench-structure semiconductor device is highly reliable and has an increased resistance to hydrofluoric acid cleaning or other cleaning of an insulation film between a gate electrode, which is embedded in a trench, and source electrode. In a trench-structure semiconductor device, a silicon nitride film is over the gate electrode... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070082413 - Semiconductor memory device with a capacitor formed therein and a method for forming the same: To integrate a capacitor device (40) into the region of a semiconductor memory device with a particularly small number of process steps, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) are provided to be formed directly underneath or directly above the material... Agent: Slater & Matsil LLP

20070082417 - Method and structure for reducing prior level edge interference with critical dimension measurement: A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via... Agent: Cantor Colburn LLP - IBM Fishkill

20070082418 - Method for manufacturing a light emitting device and light emitting device made therefrom: A method for manufacturing a light emitting device includes forming an epitaxial layer on a substrate, forming first and second electrodes that are electrically coupled to said epitaxial layer, forming a transparent layer on the epitaxial layer, forming particles of a mask material that are randomly scattered on a surface... Agent: Foley And Lardner LLP Suite 500

20070082419 - Optical pickup unit and method of manufacturing the same: An optical pickup unit comprising: a circuit connected to a light emitting device emitting light; and a counterpart circuit connected to the circuit, the circuit being soldered to the counterpart circuit.... Agent: Fish & Richardson P.C.

20070082420 - Surface preparation for selective silicon fusion bonding: An apparatus and method for a silicon-based Micro-Electro Mechanical System (MEMS) device, including a pair of silicon cover structures each having a substantially smooth and planar contact surface formed thereon; a silicon mechanism structure having a part thereof that is movably suspended relative to a relatively stationary frame portion thereof,... Agent: Honeywell International Inc.

20070082421 - Miniature silicon condenser microphone: A silicon condenser microphone package includes a transducer unit, a substrate, and a cover. The substrate includes an upper surface transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed... Agent: Marshall, Gerstein & Borun LLP

20070082422 - Method of fabricating suspended beam in a mems process: A method of fabricating a suspended beam in a MEMS process, said method comprising the steps of: (a) etching a pit in a substrate, said pit having a base and sidewalls; (b) depositing sacrificial material on a surface of said substrate so as to fill said pit; (c) removing said... Agent: Silverbrook Research Pty Ltd

20070082423 - Method of fabricating cmos image sensor: A method of fabricating a CMOS image sensor is disclosed, by which image sensor characteristics are enhanced. In one aspect, the method includes forming a plurality of photodiodes in the photodiode region of a semiconductor substrate; stacking a first insulating layer over the semiconductor substrate including the photodiodes; forming a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070082424 - Fabricating method of a thin film transistor array: A fabricating method of the thin film array is provided. The thin film transistor array includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, an etch barrier layer and a plurality of pixel electrodes. The scan lines and the data... Agent: Jianq Chyun Intellectual Property Office

20070082425 - Using a center pole illumination scheme to improve symmetry for contact hole lithography: In accordance with an embodiment the invention, there is a device manufacturing method. The method can comprise providing a substrate comprising a radiation-sensitive material disposed thereon and directing a beam of radiation through an aperture such that the radiation produces at least two illumination poles. The method can also comprise... Agent: Texas Instruments Incorporated

20070082426 - Carbon nanotube structure and method of vertically aligning carbon nanotubes: A Carbon NanoTube (CNT) structure includes a substrate, a CNT support layer, and a plurality of CNTs. The CNT support layer is stacked on the substrate and has pores therein. One end of each of the CNTs is attached to portions of the substrate exposed through the pores and each... Agent: Robert E. Bushnell

20070082427 - Method for manufacturing a compound semiconductor device having an improved via hole: In a method for manufacturing a compound semiconductor device, a principal surface of a SiC wafer, on which a compound semiconductor device is located, is bonded to a support substrate with an adhesive having a softening point higher than 200° C. A via hole is formed dry etching, including supplying... Agent: Leydig Voit & Mayer, Ltd

20070082428 - Semiconductor device protective structure and method for fabricating the same: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The... Agent: Kusner & Jaffe Highland Place Suite 310

20070082429 - Semiconductor substrate for build-up packages: The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070082430 - Semiconductor device and manufacturing method thereof: A high performance electric device which uses an adhesive layer over a substrate. A color filter is over a substrate, and an adhesive layer is also located over the substrate and color film. An insulating layer is over the adhesive layer, and thin film transistors cover the insulating film and... Agent: Fish & Richardson P.C.

20070082431 - Programmable fuse with silicon germanium: A programmable fuse and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer and a substrate. In one example, the... Agent: Freescale Semiconductor, Inc. Law Department

20070082435 - Flat panel display and fabrication method thereof: A flat panel display and fabrication method thereof. The present invention uses four etching processes to define a second conducting layer, a doped semiconductor layer and a semiconductor layer. The first etching process is a wet etching using a first resist layer to etch the second conducting layer. The second... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070082434 - Manufacturing of thin film transistor array panel: The present invention relates to a manufacturing method of a thin film transistor array panel. the method includes forming a gate line including a gate electrode on a substrate, forming a first insulating layer on the gate line, forming a semiconductor layer on the first insulating layer, forming an ohmic... Agent: Macpherson Kwok Chen & Heid LLP

20070082433 - Thin film transistor: A thin film transistor includes a semiconductor layer formed on a polycrystalline silicon layer crystallized by a super grain silicon (SGS) crystallization method. The thin film transistor is patterned such that the semiconductor layer does not include a seed or a grain boundary created when forming the semiconductor layer on... Agent: Stein, Mcewen & Bui, LLP

20070082432 - Variable exposure photolithography: A method of forming a thin film transistor on a substrate including an insulating layer and layers of etchable material over the insulating layer by depositing a layer of photoresist made of polymers that are altered by actinic energy. In the method, an amine cross-linking agent is used with portions... Agent: Morgan Lewis & Bockius LLP

20070082436 - Method of fabricating reflection type liquid crystal display: A liquid crystal display device includes (a) a first substrate, (b) a second substrate spaced away from and facing the first substrate, (c) a liquid crystal layer sandwiched between the first and second substrates, (d) a transistor formed on the first substrate, (e) a wiring layer formed on the first... Agent: Young & Thompson

20070082437 - Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby: Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070082438 - Thin film transistor and method for fabrication of an electronic device: A method for fabricating an electronic device is disclosed, the method comprising depositing a first layer of insulator over a substrate, depositing a first layer portion over the insulator using a printing technique, and removing a portion of the insulator using a photo-exposure technique or an etching technique, using the... Agent: Oliff & Berridge, PLC

20070082439 - Semiconductor device having a dual stress liner, method of manufacturing the semiconductor device and light exposure apparatus for forming the dual stress liner: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has... Agent: Myers Bigel Sibley & Sajovec

20070082442 - Recess gate transistor structure for use in semiconductor device and method thereof: An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a... Agent: Marger Johnson & Mccollom, P.C.

20070082440 - Semiconductor device and manufacturing method thereof: Gate trenches 108 are formed in a memory cell region M using a silicon nitride film 103 as a mask in a state in which the semiconductor substrate 100 in a P-type peripheral circuit region P and an N-type peripheral circuit region N is covered by a gate insulating film... Agent: Mcdermott Will & Emery LLP

20070082441 - Trench fet with improved body to gate alignment: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through... Agent: Townsend And Townsend And Crew, LLP

20070082443 - Method for manufacturing liquid crystal display device: A conventionally followed technique of manufacturing a liquid crystal display device is a method for forming various types of coatings over an entire surface of a substrate and for removing the coatings with a small region left by etching, which requires wasting a material cost and treating a large quantity... Agent: Nixon Peabody, LLP

20070082444 - Dynamic random access memory and menufacturing method thereof: A dynamic random access memory (DRAM) includes a substrate, an active device and a deep trench capacitor. A trench and a deep trench are formed in the substrate. The active device is disposed on the substrate. The active device includes a gate structure and a doped region. The gate structure... Agent: Jianq Chyun Intellectual Property Office

20070082445 - Metal-gate cmos device and fabrication method of making same: A metal-gate complementary metal-oxide-semiconductor (CMOS) device is disclosed. The CMOS device includes a PMOS transistor formed on a first area of a substrate and a NMOS transistor formed on a second area of the substrate and being coupled to the PMOS transistor. The PMOS transistor includes a first gate stack... Agent: North America Intellectual Property Corporation

20070082447 - Apparatus and method for a non-volatile memory structure comprising a multi-layer silicon-rich, silicon nitride trapping layer: A non-volatile memory structure comprises a trapping layer that includes a plurality of silicon-rich, silicon nitride layers. Each of the plurality of silicon-rich, silicon nitride layers can trap charge and thereby increase the density of memory structures formed using the methods described herein. In one aspect, the plurality of silicon-rich,... Agent: Baker & Mckenzie LLP Patent Department

20070082446 - Methods for fabricating non-volatile memory cell array: A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive... Agent: Slater & Matsil LLP

20070082448 - Semiconductor devices having transistors with vertical channels and method of fabricating the same: In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4 F2. The semiconductor device comprises: a cell array region having a plurality of unit cells, each unit cell having a cell occupation area, repeatedly aligned along a first... Agent: Mills & Onello LLP

20070082449 - Method and apparatus for maintaining topographical uniformity of a semiconductor memory array: A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack... Agent: Freescale Semiconductor, Inc. Law Department

20070082451 - Methods to fabricate mosfet devices using a selective deposition process: In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing... Agent: Patterson & Sheridan, LLP

20070082450 - Semiconductor device and method of manufacturing such a semiconductor device: The invention relates to a semiconductor device (10) with a substrate and a semiconductor body (1) comprising a first FET (3) with a source (2) and a drain (3) that are provided with connection regions (2B, 3B) of a metal silicide, and that are connected to source and drain extensions... Agent: Philips Intellectual Property & Standards

20070082452 - Semiconductor device manufacturing method: A memory transistor and a high breakdown voltage MOS transistor are easily formed on the same semiconductor substrate without changing the operational characteristics of the memory transistor. The process of forming the tunnel insulation film of the memory transistor and the process of forming the gate insulation film of the... Agent: Morrison & Foerster LLP

20070082453 - Method for making a semiconductor structure using silicon germanium: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the... Agent: Freescale Semiconductor, Inc. Law Department

20070082455 - Manufacturing method of semiconductor substrate: Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming... Agent: Reed Smith, LLP Attn: Patent Records Department

20070082454 - Microelectronic device and method of manufacturing a microelectronic device: A microelectronic device comprises a substrate and a transistor. The transistor comprises a channel region in the substrate, a recess in the channel region, a first dielectric layer and a second dielectric layer. The first dielectric layer comprises a first dielectric material and is deposited at the bottom of the... Agent: Morrison & Foerster LLP

20070082457 - Method for filling of nanoscale holes and trenches and for planarizing of a wafer surface: A processing method for use in the fabrication of fabrication of nanoscale electronic, optical, magnetic, biological, and fluidic devices and structures, for filling nanoscale holes and trenches, for planarizing a wafer surface, or for achieving both filling and planarizing of a wafer surface simultaneously. The method has the initial step... Agent: Polster, Lieder, Woodruff & Lucchesi

20070082456 - Polishing composition and polishing method: To provide a polishing composition which allows high-speed polishing while etching and erosion are prevented and the flatness of metal film is maintained, there is provided a a polishing composition, comprising (A) a compound having three or more azole moieties, (B) an oxidizing agent, and (C) one or more species... Agent: Sughrue Mion, PLLC

20070082458 - Semiconductor device and method of fabricating the same: A semiconductor device includes a semiconductor substrate and first and second trenches. The first trench with a high aspect ratio is formed in a surface of the semiconductor substrate and has a bottom, two sidewalls and an open end. The first trench is formed so that at the bottom side,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070082461 - Method of forming a recessed structure employing a reverse tone process: The present invention provides a method of forming recesses on a substrate, the method including forming on the substrate a patterning layer having first features; trim etching the first features to define trimmed features having a shape; and transferring an inverse of the shape into the substrate.... Agent: Molecular Imprints

20070082459 - Probes, methods of making probes and applications of probes: Provided herein are methods and apparatuses for analog molecules, particularly polymers, and molecular complexes with extended confirmations. In particular, the methods and apparatuses are used to identify sequence information in molecules or molecular ensembles which is subsequently used to determine structural information about the molecules. Further, provided herein are various... Agent: Reveo, Inc.

20070082460 - Wafer processing method and wafer processing apparatus: A method of processing a wafer includes a masking process for providing a mask on a surface of a film-formed wafer except for a wafer peripheral portion, and polishing process for spraying a processing liquid containing an inorganic material onto the wafer peripheral portion. According to the method of processing... Agent: Sughrue Mion, PLLC

20070082464 - Apparatus for block assembly process: Apparatuses and methods for improved fluidic self assembly (FSA). An apparatus performing an improved FSA method can include one or more of a block deposition and clearing section, a drying section, a lamination section and an inspection section. In a specific embodiment, each of these sections are connected in series... Agent: Blakely Sokoloff Taylor & Zafman

20070082463 - Semiconductor device with semiconductor chip and adhesive film and method for producing the same: A semiconductor device includes a semiconductor chip and an adhesive film between the back side of the semiconductor chip and a chip pad of a leadframe. The adhesive film includes a film core and adhesive layers that cover both sides of the film core. The film core includes a brittle,... Agent: Edell, Shapiro & Finnan, LLC

20070082462 - Wafer having indicator for first die and method of attaching die of the wafer: Provided are a wafer having an indicator for a first die and a method of attaching a die of the wafer. The wafer includes an indicator formed on a back surface at a position corresponding to a position of a first die on a front surface, for indicating the position... Agent: Mills & Onello LLP

20070082466 - High density plasma chemical vapor deposition apparatus, operating method thereof, and method of manufacturing semiconductor device: Disclosed are a chemical vapor deposition apparatus capable of improving gap-fill characteristics, an operating method thereof, and a method of manufacturing a semiconductor device. The chemical vapor deposition apparatus includes a first induction coil installed on an upper portion of a chamber to feed a first power having a first... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070082465 - Method of fabricating gan substrate: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN... Agent: Stein, Mcewen & Bui, LLP

20070082467 - Method for manufacturing compound semiconductor substrate: m

20070082468 - Atomic layer deposition methods: An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing... Agent: Wells St. John P.s.

20070082469 - Forming heaters for phase change memories: Rather than depositing a heater material into a pore, a heater material may be first blanket deposited. The heater material may then be covered by a mask, such that the mask and the heater material may be etched to form a stack. Then, the region between adjacent stacks that form... Agent: Trop Pruner & Hu, PC

20070082470 - Gate technology for strained surface channel and strained buried channel mosfet devices: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1−xGex layer on a substrate, a strained channel layer on the relaxed Si1−xGex layer, and a Si1−yGey layer; removing the Si1−yGey layer; and providing a dielectric layer. The dielectric layer includes a gate... Agent: Goodwin Procter LLP Patent Administrator

20070082471 - Method of fabricating semiconductor memory device having plurality of storage node electrodes: In one aspect, a method of fabricating a semiconductor memory device is provided which includes forming a mold insulating film over first and second portions of a semiconductor substrate, where the mold insulating film includes a plurality of storage node electrode holes spaced apart over the first portion of the... Agent: Volentine Francos, & Whitt PLLC

20070082472 - Method of manufacturing contact hole: A method of manufacturing contact hole is provided. First, a mask layer is formed on a substrate and a plurality of trenches is formed in the mask layer along two directions that cross over each other. The depth of the trenches is not greater than the thickness of the mask... Agent: Jianq Chyun Intellectual Property Office

20070082473 - Process for low resistance metal cap: An exemplary method includes: providing a substrate with exposed metal and dielectric surfaces, performing a reducing process on the metal and dielectric surfaces, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for selective metal layer deposition.... Agent: Duane Morris LLPIPDepartment (tsmc)

20070082474 - Process for making a metal seed layer: An exemplary method includes: providing a substrate with an exposed metal surface, performing a reducing process on the metal surface, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for metal layer deposition.... Agent: Duane Morris LLPIPDepartment (tsmc)

20070082475 - Method for forming bonding pad and semiconductor device having the bonding pad formed thereby: A first insulating film is formed on a substrate or a lower metal wiring, and a first metal layer is formed on the first insulating film. A second insulating film and a third insulating film are formed on the first insulating film and the first metal layer, and the third... Agent: Mayer, Brown, Rowe & Maw LLP

20070082476 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is provided. The method includes: (A) forming an insulating film with a porous structure on a substrate; (B) forming a trench in the insulating film, the trench being used for forming an interconnection; (C) depositing a metal layer over the insulating film such... Agent: Mcginn Intellectual Property Law Group, PLLC

20070082477 - Integrated circuit fabricating techniques employing sacrificial liners: The present invention provides techniques for fabricating integrated circuit structures in semiconductor wafer fabrication. A via hole is prepared in a dielectric stack having a bottom via etch stop layer. The via hole is not extended through the via etch stop layer at this stage of the process. The via... Agent: Patent Counsel Applied Materials, Inc.

20070082478 - Silicone polymer and organic polymer containing alloy and/or hybrid emulsion compositions: Emulsion compositions containing a silicone polymer and organic polymer as an alloy and/or hybrid emulsion can be made by (i) first forming an emulsion containing a silicone polymer by emulsion polymerization in which (a) the ring of a cyclic siloxane oligomer is opened, in which (b)an hydroxy endblocked siloxane oligomer... Agent: Dow Corning Corporation Co1232

20070082479 - Chemical mechanical polishing techniques for integrated circuit fabrication: The present invention provides methods for fabricating horizontal interconnect lines for use in semiconductor wafer fabrication. A dielectric layer is deposited on a dielectric stack having a planarized top surface. The dielectric layer is not planarized at this stage of the process. A pre-planarizing thickness profile of the non-planarized dielectric... Agent: Patent Counsel Applied Materials, Inc.

20070082481 - Method of forming dual damascene pattern: Disclosed is a method of forming a dual damascene pattern. The method can include forming a first etch stop layer, a first dielectric layer, a second etch stop layer, a second dielectric layer and a cap insulating layer on a substrate, forming a preliminary via hole exposing a part of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070082480 - Ultra thin fet: Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier... Agent: Ostrolenk Faber Gerb & Soffen

20070082482 - Method for forming contact hole of semiconductor device: A method for forming a contact hole of a semiconductor is provided. Conductive patterns are formed over a substrate. An insulation layer is formed over the substrate to bury the conductive patterns. A hard mask including an amorphous carbon layer and an oxide based layer are formed in sequential order... Agent: Blakely Sokoloff Taylor & Zafman

20070082483 - Method of etching carbon-containing layer and method of fabricating semiconductor device: A method of etching a carbon-containing layer on a semiconductor substrate using a Si-containing gas and a related method of fabricating a semiconductor device in which a plurality of contact holes having excellent sidewall profiles are formed by etching an interlayer insulating layer using a carbon-containing layer pattern formed in... Agent: Mills & Onello LLP

20070082484 - Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layer: Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070082485 - Methods for discretized formation of masking and capping layers on a substrate: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is... Agent: Courtney Staniford & Gregory LLP

20070082486 - Method for manufacturing nitride based single crystal substrate and method for manufacturing nitride based semiconductor device: A method for manufacturing a nitride based single crystal substrate and a method for manufacturing a nitride based semiconductor device. The method for manufacturing the nitride based single crystal substrate includes forming a nitride based single crystal layer on a preliminary substrate; forming a polymer support layer by applying a... Agent: Mcdermott Will & Emery LLP

20070082487 - Methods for discretized processing of regions of a substrate: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is... Agent: Courtney Staniford & Gregory LLP

20070082488 - Semiconductor device and manufacturing method thereof: A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first interconnect (wiring) 112, formed in a first interlayer insulating film 106 on a semiconductor substrate, not shown, a via 128 provided on... Agent: Young & Thompson

20070082489 - Method of fabricating openings and contact holes: A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the... Agent: North America Intellectual Property Corporation

20070082490 - Apparatus of chemical mechanical polishing and chemical mechanical polishing process: An apparatus of chemical mechanical polishing has a polishing machine, a first thickness metrology and a second thickness metrology. The first thickness metrology is connected with the polishing machine, and the second thickness metrology is connected with the polishing machine. Since the thickness of the first material layer and the... Agent: Jianq Chyun Intellectual Property Office

20070082491 - Semiconductor device manufacturing method and chemical fluid used for manufacturing semiconductor device: This disclosure is concerned a method of manufacturing a semiconductor device which includes providing an dielectric film on a substrate; providing a mask material on the dielectric film; etching the dielectric film using the mask material; performing a first treatment of removing a metal residue generated by etching the dielectric... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070082494 - Method for forming silicide layer: A method for forming a metal silicide over a substrate is provided. The method comprises steps of performing a fluorine-containing plasma treatment on the substrate to remove a plurality of residual over the substrate, wherein the fluorine-containing plasma treatment is performed in a first tool system. Then, a vacuum system... Agent: Jianq Chyun Intellectual Property Office

20070082493 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, includes forming a sacrifice film on an etching target film, forming an etching mask on the sacrifice film, etching the etching target film using the etching mask as a mask, removing the sacrifice film to allow the etching mask to adhere to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070082492 - Semiconductor memory device and method of fabricating the same: A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of... Agent: Myers Bigel Sibley & Sajovec

20070082495 - Semiconductor device having nano-pillars and method therefor: A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is... Agent: Freescale Semiconductor, Inc. Law Department

20070082496 - Resist film removing method: A resist film removing method for removing a resist film disposed on a substrate and having a cured layer at a surface includes covering the surface of the resist film with a protection film; causing popping in the resist film covered with the protection film; denaturing the resist film and... Agent: Smith, Gambrell & Russell

20070082497 - Composition for removing an insulation material and related methods: A composition for removing an insulation material and related methods of use are disclosed. The composition comprises about 1 to 50 percent by weight of an oxidizing agent, about 0.1 to 35 percent by weight of a fluorine-containing compound, and water. The insulation material comprises at least one of a... Agent: Volentine Francos, & Whitt PLLC

20070082498 - Method of cleaning a wafer: A wafer having a metal layer inclding salicide regions and unreacted metal regions disposed thereon is provided. Subsequently, an acidic solution is provided to remove the unreacted metal regions. Following that, a cold APM solution is used to remove particles subsequent to using the acidic solution to remove the unreacted... Agent: North America Intellectual Property Corporation

20070082499 - Photoresist coating apparatus, medium, and method efficiently spraying photoresist: A photoresist coating apparatus, medium, and method for efficiently spraying a liquid photoresist to maintain an atmosphere of ionized solvent vapor between a substrate and a spray nozzle of an upper portion by using a vapor inducing pipe supplying ionized solvent vapor, with the atmosphere being maintained by differently biasing... Agent: Staas & Halsey LLP

20070082500 - Ti, ta, hf, zr and related metal silicon amides for ald/cvd of metal-silicon nitrides, oxides or oxynitrides: wherein M is a metal selected from Group 4 of the Periodic Table of the Elements and R1-4 can be same or different selected from the group consisting of dialkylamide, difluoralkylamide, hydrogen, alkyl, alkoxy, fluoroalkyl and alkoxy, cycloaliphatic, and aryl with the additional provision that when R1 and R2 are... Agent: Air Products And Chemicals, Inc. Patent Department

20070082501 - Novel integrated circuit support structures and their fabrication: A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by... Agent: Dennison, Schultz & Macdonald

20070082502 - Method for producing a dielectric layer on a carrier material and an integrated circuit comprising a capacitor incorporating a dielectric layer: A dielectric material layer is formed on a carrier material. A gas mixture containing at least one precursor comprising a metallic element is alternately circulated with an oxidant gas in contact with the carrier material under first oxidizing conditions so as to form a first sub-layer having dielectric qualities. A... Agent: Jenkens & Gilchrist, PC

20070082503 - Method of fabricating a dielectric layer: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process... Agent: Jianq Chyun Intellectual Property Office

20070082505 - Method of forming an electrically insulating layer on a compound semiconductor: A method of forming an electrically insulating layer (130) on a compound semiconductor (110) comprises: providing a compound semiconductor structure; preparing an upper surface (111) of the compound semiconductor structure to be chemically clean; forming a template (120) on the compound semiconductor structure using a first precursor in a metalorganic... Agent: Kenneth A. Nelson Bryan Cave LLP

20070082506 - Multi-step annealing process: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process... Agent: Jianq Chyun Intellectual Property Office

20070082504 - Pre-metal dielectric semiconductor structure and a method for depositing a pre-metal dielectric on a semiconductor structure: The invention refers to a pre-metal dielectric semiconductor structure comprising a substrate, having features on a surface of the substrate, wherein the features are spaced from at least one gap between the features. The gap is filled with an advantageous layer combination. The layer combination comprises at least one spin-on... Agent: Morrison & Foerster LLP

20070082507 - Method and apparatus for the low temperature deposition of doped silicon nitride films: A method and apparatus for low temperature deposition of doped silicon nitride films is disclosed. The improvements include a mechanical design for a CVD chamber that provides uniform heat distribution for low temperature processing and uniform distribution of process chemicals, and methods for depositing at least one layer comprising silicon... Agent: Patterson & Sheridan, LLP

20070082508 - Methods for discretized processing and process sequence integration of regions of a substrate: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is... Agent: Courtney Staniford & Gregory LLP

20070077664 - Magnetic tunnel junction temperature sensors and methods: Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction (“MTJ”) temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070077666 - Efficient provision of alignment marks on semiconductor wafer: A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each... Agent: Cooper & Dunham, LLP

20070077667 - Semiconductor wafer test system: A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates... Agent: Mcdermott Will & Emery LLP

20070077665 - Tool for creating customized user interface definitions for a generic utility supporting on-demand creation of field device editor graphical user interfaces: A customization tool is described in association with a universal device type manager (DTM) utility. The customization tool includes a set of user interfaces and associated functionality that facilitates creating a set of customized templates for a particular device type. The customized templates define access to device data via graphical... Agent: Leydig Voit & Mayer, Ltd

20070077668 - Light-emitting device and manufacturing method thereof: Provides is a semiconductor light-emitting device. The semiconductor light-emitting device includes a first conduction-type cladding layer, an active layer, and a second conduction-type cladding layer, on a substrate. Portions of the substrate and the first conduction-type cladding layer are removed. According to the light-emitting device having the above-construction, damage to... Agent: Birch Stewart Kolasch & Birch

20070077669 - Nitride-based semiconductor device and method of fabricating the same: A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer... Agent: Mcdermott Will & Emery LLP

20070077670 - Super bright light emitting diode of nanorod array structure having ingan quantum well and method for manufacturing the same: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a... Agent: Intellectual Property Group Fredrikson & Byron, P.A.

20070077671 - In-situ substrate imaging: Methods and products, including computer program products, for endpoint determination. An image of a portion of a substrate is captured in-situ, where the image includes optical information that depends on a thickness of a substrate layer. The image is examined to find a location on the substrate, and a process... Agent: Fish & Richardson P.C.

20070077672 - Array substrate for liquid crystal display device and method of fabricating the same: An array substrate for an LCD device includes a first TFT including a first semiconductor layer, a first gate electrode, wherein the first gate electrode is directly over the first semiconductor layer; a first protrusion extending from the first gate electrode along an edge of the first semiconductor layer; a... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20070077673 - Method for manufacturing vertically structured light emitting diode: There is provided a method for manufacturing a vertically structured LED capable of performing a chip separation process with ease. In the method, a light-emitting structure is formed on a growth substrate having a plurality of device regions and at least one device isolation region, wherein the light-emitting structure has... Agent: Mcdermott Will & Emery LLP

20070077674 - Process for producing semiconductor light-emitting device: A process for producing a semiconductor light-emitting device is provided. The process includes providing a substrate including a substrate surface oriented along a substrate surface plane, forming a crystal seed layer on the substrate surface, forming a masking layer on the crystal seed layer, wherein the masking layer includes an... Agent: Bell, Boyd & Lloyd, LLP

20070077675 - Electronic component packaging: p

20070077676 - Method of fabricating pressure sensor: A method of fabricating a pressure sensor. An SOI wafer having a single crystalline silicon layer, an insulating layer and a silicon substrate is provided. The single crystalline silicon layer has a pressure sensing device. The silicon substrate and the insulating layer corresponding to the pressure sensing device are removed... Agent: North America Intellectual Property Corporation

20070077677 - Microelectronic packages and methods therefor: A microelectronic assembly includes a microelectronic package having a microelectronic element with faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic... Agent: Tessera Lerner David Et Al.

20070077678 - Method of fabricating image sensors: A method of fabricating image sensors includes forming an isolation pattern in a semiconductor substrate of a first conductivity type to define a light receiving region and an active region and forming a sidewall impurity region of a second conductivity type in the edge of the light receiving region to... Agent: F. Chau & Associates, LLC

20070077681 - Liquid phase fabrication of active devices including organic semiconductors: Techniques including steps of: providing a support body; forming an organic semiconductor composition body including an organic semiconductor composition on the support body, no more than 10% by weight of the organic semiconductor composition being pentacene; providing a first organic dielectric composition mobilized in a first liquid medium, the organic... Agent: The Eclipse Group

20070077682 - Method and apparatus for a metallic dry-filling process: An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the size of the grain features in the deposited material opening at... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070077683 - Method and apparatus for a metallic dry-filling process: An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the size of the grain features in the deposited material opening at... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070077679 - Method for production of a film: The invention concerns a film having at least one electrical component and a process for the production of such a film. An adhesive layer comprising a radiation-cross-linkable adhesive is applied to a base film. The adhesive layer is applied to the base film in a form of being structured in... Agent: Hoffmann & Baron

20070077680 - Preparation of self-assembled silicon nanotubes by hydrothermal method: The present invention relates to a method for preparing self-assembled silicon nanotubes (SiNTs) by a hydrothermal method. A method for preparing self-assembled SiNTs comprises forming a mixture of silicon oxide and water in a sealed container, wherein the mixture has a silicon oxide to water ratio of no more than... Agent: Knobbe Martens Olson & Bear LLP

20070077684 - Resistance welded solder crimp for joining stranded wire to a copper lead-frame: A method of connecting stranded wire to a lead-frame body 10 includes the provision of a stranded wire 12. It is ensured that insulation is stripped from an end 14 of the stranded wire. An electrically conductive lead-frame connection structure 16 is associated with the lead-frame body. The end 14... Agent: Siemens Corporation Intellectual Property Department

20070077685 - Production method of semiconductor chip: Provided is a method for producing a semiconductor chip, comprising applying a photothermal conversion layer on a light-transmitting support, provided that upon irradiation of radiation energy, the photothermal conversion layer converts the radiation energy into heat and decomposes due to the heat; laminating the semiconductor wafer and the light-transmitting support... Agent: 3m Innovative Properties Company

20070077687 - Method of producing circuit carriers with integrated passive components: The present invention relates to a method for producing an electrical subassembly comprising a circuit carrier and at least one passive component which is integrated into the circuit carrier and comprises an electrically functional material. For providing an improved method for manufacturing an electrical subassembly comprising a circuit carrier and... Agent: Michael Best & Friedrich, LLP

20070077686 - Packaging method for preventing chips from being interfered and package structure thereof: A package structure for preventing chips from being interfered is disclosed. The package structure includes a substrate and a chip. The substrate has a metal layer with a conducting trace area and a shielding area, and a dielectric layer having a plurality of via holes formed therein. The dielectric layer... Agent: North America Intellectual Property Corporation

20070077688 - Method for manufacturing flexible printed circuit boards: A method for manufacturing of flexible printed circuit boards is provided. The method includes the steps of: providing a tape substrate having an electrically insulating layer and an electrically conducting layer; forming a wiring pattern at the electrically conducting layer; attaching a back film on a surface of the tape... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070077689 - Complimentary lateral iii-nitride transistors: A semiconductor device which includes a laterally extending stack of laterally adjacent conductive semiconductor regions formed over a support surface of a substrate, and a method for fabricating the device.... Agent: Ostrolenk Faber Gerb & Soffen

20070077692 - Liquid crystal display device and fabricating method thereof: A method for fabricating an LCD device includes forming sequentially a first conductive layer, a first insulation layer, a semiconductor layer, and an ohmic contact layer on a first substrate; forming a gate line by patterning the first conductive layer, the first insulation layer, the semiconductor layer, and the ohmic... Agent: Morgan Lewis & Bockius LLP

20070077691 - Manufacturing method of semiconductor device: It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the... Agent: Eric Robinson

20070077693 - Method of fabricating fin field effect transistor using isotropic etching technique: Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its... Agent: Marger Johnson & Mccollom, P.C.

20070077690 - Semiconductor device with transistors and fabricating method therefor: A semiconductor device with transistors and a fabricating method therefore are provided. The electrodes of the transistors are formed on the same layer, and they are coupled to one another by a conductor layer. Therefore, the requirement for the vias in whole circuit is reduced, and the cost is decreased.... Agent: Rabin & Berdo, PC

20070077694 - Three-dimensional integrated circuit structure: A semiconductor structure includes an interconnect region and a semiconductor stack bonded to the interconnect region through a bonding region. The stack includes at least two semiconductor layers having different electrical properties. The stack also includes single crystalline semiconductor material. The stack can be processed to form a mesa structure... Agent: Greg L. Martinez

20070077695 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device including forming a trench on a first surface of a silicon substrate, forming a thermal oxide layer and a deposited oxide layer on the trench and the silicon substrate, planarizing a second surface of the silicon substrate by a chemical mechanical polishing (CMP)... Agent: Jin-hyo Jung

20070077696 - Laser irradiation method and laser irradiation apparatus: An object of the present invention is to provide a laser irradiation method and a laser irradiation apparatus for irradiating an irradiation surface with a linear beam having more homogeneous intensity by blocking a low-intensity part of the linear beam without forming the fringes due to the diffraction on the... Agent: Eric Robinson

20070077698 - Method for fabricating dual-metal gate device: A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the... Agent: Freescale Semiconductor, Inc. Law Department

20070077697 - Semiconductor device with semi-insulating substrate portions and method for forming the same: A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation... Agent: Duane Morris LLPIPDepartment (tsmc)

20070077699 - Multilevel programming of phase change memory cells: A method for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase... Agent: Trop Pruner & Hu, PC

20070077700 - Capacitance process using passivation film scheme: In accordance with the objectives of the invention a new method and structure is provided for the creation of a capacitor. A contact pad and a lower capacitor plate have been provided over a substrate. Under the first embodiment of the invention, a layer of etch stop material, serving as... Agent: Duane Morris, LLPIPDepartment

20070077701 - Method of forming a gate stack containing a gate dielectric layer having reduced metal content: A method is provided for reducing the metal content and controlling the metal depth profile of a gate dielectric layer in a gate stack. The method includes providing a substrate in a process chamber, depositing a gate dielectric layer on the substrate, where the gate dielectric layer includes a metal... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070077702 - Trench memory cell and method for making the same: A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the trench, and a dielectric... Agent: International Business Machines Corporation Dept. 18g

20070077703 - Semiconductor devices having improved gate insulating layers and related methods of fabricating such devices: Semiconductor devices are provided on a substrate having a cell array region and a peripheral circuit region. A first device isolation layer defines a cell active region in the cell array region and a second device isolation layer having first and second sidewalls defines a peripheral active region in the... Agent: Myers Bigel Sibley & Sajovec

20070077704 - Method of fabricating a bottle-shaped trench: A method of fabricating a bottle-shaped trench is described. A substrate having a deep trench is provided. A conformal silicon material layer is formed on the substrate. A photoresist layer is formed in the deep trench to cover a portion of the silicon material layer. An ion implantation process is... Agent: Jianq Chyun Intellectual Property Office

20070077710 - Method for manufacturing flash memory device: A method for manufacturing a flash memory device including the steps of forming a gate oxide film for high voltage on the whole surface of a semiconductor substrate on which a cell region, a low voltage region and a high voltage region have been formed, etching the gate oxide film... Agent: Marshall, Gerstein & Borun LLP

20070077706 - Method of making a multi-bit nov-volatile memory (nym) cell and structure: A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer... Agent: Freescale Semiconductor, Inc. Law Department

20070077707 - Non volatile memory device and method of manufacturing the same: The present invention provides a non-volatile memory device and a method of manufacturing the same. The non-volatile memory device includes: a semiconductor substrate including an active region defined by an isolation layer, having a first conductivity type; a gate formed on the substrate; a first threshold voltage adjusting layer formed... Agent: Jun-hyo Jung

20070077709 - Semiconductor device having self-aligned contact hole and method of fabricating the same: According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered... Agent: Marger Johnson & Mccollom, P.C.

20070077705 - Split gate memory cell and method therefor: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has... Agent: Freescale Semiconductor, Inc. Law Department

20070077708 - Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stress: By partially removing an etch stop layer prior to the formation of a first contact etch stop layer, a superior stress transfer mechanism may be provided in an integration scheme for generating strain by means of contact etch stop layers. Thus, a semiconductor device having different types of transistors may... Agent: Williams, Morgan & Amerson

20070077711 - Fabricating method of an non-volatile memory: A method of fabricating a non-volatile memory is provided. A substrate having a trench therein for forming a trench device is provided. Then, a doped metal silicide layer is formed on the substrate in the trench. A heating process is performed to form a source/drain area in the substrate under... Agent: Jianq Chyun Intellectual Property Office

20070077712 - Methods of fabricating non-volatile memory devices including nanocrystals: Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic... Agent: Myers Bigel Sibley & Sajovec

20070077713 - Semiconductor device having recessed gate electrode and method of fabricating the same: In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is... Agent: Mills & Onello LLP

20070077714 - Method for fabricating a semiconductor device: A method of fabricating a HI-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.... Agent: Ostrolenk Faber Gerb & Soffen

20070077715 - Semiconductor device and method of fabricating the same: Example embodiments relate to a semiconductor device and a method of fabricating the same. A dummy pattern may be formed on a semiconductor substrate. Source and drain regions may be formed on the semiconductor substrate at sides of the dummy pattern. A first metal silicide layer may be formed on... Agent: Harness, Dickey & Pierce, P.L.C

20070077716 - Method and structure for second spacer formation for strained silicon mos transistors: A method for forming a CMOS semiconductor wafer. The method includes providing a semiconductor substrate (e.g., silicon wafer) and forming a dielectric layer (e.g., silicon dioxide, silicon oxynitride) overlying the semiconductor substrate. The method includes forming a gate layer overlying the dielectric layer and patterning the gate layer to form... Agent: Townsend And Townsend And Crew, LLP

20070077717 - Method for forming transistor of semiconductor device: A method for forming a transistor of a semiconductor device includes forming a spacer oxide film having a uniform thickness i at a high speed. The method includes forming a plurality of gate stacks on a semiconductor substrate; and forming a spacer oxide film on a plurality of the gate... Agent: Townsend And Townsend And Crew, LLP

20070077718 - Process for manufacturing silicon-on-insulator substrate: A process for manufacturing a silicon-on-insulator substrate comprising a single-crystal silicon substrate in which an oxide layer has been locally buried includes forming a step on the silicon substrate so that a region corresponding to the oxide layer has a greater surface height than other regions; then implanting oxygen ions... Agent: Kolisch Hartwell, P.C.

20070077719 - Semiconductor device manufacturing method: In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070077720 - Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing an integrated circuit substrate having a main surface; providing a dielectric layer on said main surface; providing a via in said dielectric layer, said... Agent: Morrison & Foerster LLP

20070077721 - Semiconductor device and manufacturing method therefor: A semiconductor device comprising a capacitive element which is provided above the semiconductor substrate and which has a capacitive insulation film held between an upper electrode and a lower electrode, a conductor for upper electrode which is connected to the upper electrode, a side-wall adsorbent member which covers a side... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070077722 - Flat-type capacitor for integrated circuit and method of manufacturing the same: Embodiments of the invention provide flat-type capacitors that prevent degradation of the dielectric layer, thereby improving the electrical properties of the capacitor. The capacitor includes a lower interconnection formed in a predetermined portion of a semiconductor substrate, a lower electrode formed on the lower interconnection that is electrically coupled to... Agent: Marger Johnson & Mccollom, P.C.

20070077724 - Etching methods and apparatus and substrate assemblies produced therewith: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma... Agent: Williams, Morgan & Amerson

20070077723 - Method of forming shallow trench isolation in a semiconductor device: An exemplary method of forming a shallow trench isolation layer in a semiconductor device according to an embodiment of the present invention includes depositing a silicon nitride layer as a hard mask layer on a silicon substrate, forming a first moat pattern in the silicon nitride layer by a photolithography... Agent: Heui-gyun Ahn

20070077725 - Positive-intrinsic-negative (pin) / negative-intrinsic-positive (nip) diode: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070077726 - Semiconductor device and fabrication method therefor: The present invention provides a method of fabricating a semiconductor device including forming an insulation film on or above a semiconductor substrate, forming contact holes in the insulation film, forming a metal layer in the contact hole, polishing an upper portion of the insulation film below a top surface of... Agent: Wagner, Murabito & Hao LLP

20070077727 - Method of forming a cavity by two-step etching and method of reducing dimension of a mems device: A method for reducing dimension of an MEMS device. A single crystalline substrate having a diaphragm is provided. A first-step anisotropic dry etching process is performed to form an opening corresponding to the diaphragm in the back surface, the anisotropic dry etching stopping on a specific lattice plane extending from... Agent: North America Intellectual Property Corporation

20070077728 - Adhesive system for supporting thin silicon wafer: In some embodiments, an adhesive system for supporting thin silicon wafer is presented. In this regard, a method is introduced to bond a silicon wafer to a translucent carrier through the use of an adhesive. Other embodiments are also disclosed and claimed.... Agent: Blakely Sokoloff Taylor & Zafman

20070077730 - Method and device for extracting an electronic chip from a silicon wafer and transporting the chip to its installation location on an electronic device:

20070077729 - Method of fabricating a release substrate: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer... Agent: Winston & Strawn LLP Patent Department

20070077731 - Processing method of wafer: A separation groove having a depth corresponding to a finished thickness of a semiconductor chip is formed in a boundary between a device region and an outer peripheral surplus region of a wafer, a protection tape whose adhesion is deteriorated by irradiation of ultraviolet rays is adhered on a surface,... Agent: Brinks Hofer Gilson & Lione

20070077732 - Semiconductor device and a manufacturing method of the same: The present invention enhances the processing efficiency of assembling of a semiconductor device. After performing resin molding by a through-gate method, the package dicing is performed such that leads and inclined portions of sealing bodies are cut while adhering a dicing tape to front surfaces of a plurality of sealing... Agent: Miles & Stockbridge PC

20070077733 - Germanium compound delivery device: Germanium compounds suitable for use as vapor phase deposition precursors for germanium films are provided. Methods of depositing films containing germanium using such compounds are also provided. Such germanium films are particularly useful in the manufacture of electronic devices.... Agent: S. Matthew Cairns Rohm And Haas Electronic Materials LLC

20070077734 - Thin buffer layers for sige growth on mismatched substrates: Growth of SiGe on a significantly lattice mismatched substrate (e.g., Si) is provided by depositing a SiGe buffer layer at a growth temperature, then annealing the resulting structure at a temperature higher than the growth temperature. Additional buffer layers can be included following the same steps. The SiGe buffer is... Agent: Lumen Intellectual Property Services, Inc.

20070077735 - Element of low temperature poly-silicon thin film and method of making poly-silicon thin film by direct deposition at low temperature and inductively-coupled plasma chemical vapor deposition equipment therefor: A low temperature poly-silicon thin film element, method of making poly-silicon thin film by direct deposition at low temperature, and the inductively-coupled plasma chemical vapor deposition equipment utilized, wherein the poly-silicon material is induced to crystallize into a poly-silicon thin film at low temperature by means of high density plasma... Agent: Birch Stewart Kolasch & Birch

20070077736 - Method of manufacturing semiconductor device carrying out ion implantation before silicide process: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070077737 - Plasma processing method and plasma processing apparatus: A microwave is radiated into a processing chamber (1) from a planar antenna member of an antenna (7) through a dielectric plate (6). With this, a C5F8 gas supplied into the processing chamber (1) from a gas supply member (3) is changed (activated) into a plasma so as to form... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070077738 - Fabrication of small scale matched bi-polar tvs devices having reduced parasitic losses: A method of fabricating plural bipolar transient voltage suppressors includes preparing a doped base material having a planar surface and then depositing onto the planar surface an doped epitaxial layer of opposite type thereby forming a semiconductor interface. The epitaxial layer is preferentially etched leaving mesas having side walls to... Agent: Gene Scott Patent Law & Venture Group

20070077739 - Carbon controlled fixed charge process: Carbon may be implanted into a p-type silicon channel to form a carbon region in an n-type metal oxide semiconductor (NMOS) transistor. After an annealing process, the implanted carbon may diffuse from the channel into an interface of a gate dielectric layer and the channel. The diffusion may cause an... Agent: Blakely Sokoloff Taylor & Zafman

20070077740 - Methods of fabricating fully silicide gate and semiconductor memory device having the same: A method of fabricating a semiconductor device having a fully silicide gate comprises: forming a gate insulation film on a substrate; forming a patterned poly-silicon gate and an insulation layer on the gate insulation film; forming side wall spacers on both sides of the patterned poly-silicon gate; forming source/drain regions... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20070077741 - Technique for creating different mechanical strain by a contact etch stop layer stack with an intermediate etch stop layer: The present invention provides a technique for forming differently stressed contact etch stop layers, wherein sidewall spacers are removed prior to the formation of the contact etch stop layers. During the partial removal of respective contact etch stop layers, a corresponding etch stop layer regime is used to substantially avoid... Agent: Williams, Morgan & Amerson

20070077742 - Composition for forming silicon-cobalt film, silicon-cobalt film and method forming same: There are provided a composition and method for forming a silicon-cobalt film at low production cost without expensive vacuum equipment and high-frequency generator. The composition is a silicon-cobalt film forming composition comprising a silicon compound and a cobalt compound. A silicon-cobalt film is formed by applying this composition on a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070077743 - Multiple fin formation: A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of these patterned features. A second set of sidewall... Agent: Freescale Semiconductor, Inc. Law Department

20070077744 - Epitaxial substrate, method of making same and method of making a semiconductor chip: Proposed is an epitaxial substrate, particularly for making thin-film semiconductor chips based on III-V semiconductors, comprising a sacrificial layer that is applied to a wafer substrate and whose band gap is smaller than the band gap of the surrounding substrate, and a method of making the epitaxial substrate. Further described... Agent: Fish & Richardson PC

20070077745 - Iii-nitride semiconductor fabrication: A process for fabricating a III-nitride power semiconductor device which includes forming a gate structure while providing a protective body over areas that are to receive power electrodes.... Agent: Ostrolenk Faber Gerb & Soffen

20070077746 - Method of manufacturing a semiconductor device including a bump forming process: A method of manufacturing a semiconductor device includes an improved bump forming process. The bump forming process includes a bump forming step for forming a bump on the pad by feeding a gold wire from a capillary while moving the capillary; a sliding step of slightly moving the capillary in... Agent: Mcdermott Will & Emery LLP

20070077750 - Atomic layer deposition processes for ruthenium materials: Embodiments of the invention provide a method for depositing ruthenium materials on a substrate by various vapor deposition processes, such as atomic layer deposition (ALD) and plasma-enhanced ALD (PE-ALD). In one aspect, the process has little or no initiation delay and maintains a fast deposition rate while forming a ruthenium... Agent: Patterson & Sheridan, LLP

20070077748 - Method for forming a semiconductor product and semiconductor product: A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged... Agent: Slater & Matsil LLP

20070077749 - Method for forming a tungsten interconnect structure with enhanced sidewall coverage of the barrier layer: By performing a re-sputter process during the formation of a barrier layer for a contact opening in a tungsten-based process, the reliability of the tungsten deposition, as well as the performance of the resulting contact plug, may be enhanced. During the re-sputtering process, a thickness of the titanium-based barrier layer... Agent: Williams, Morgan & Amerson

20070077747 - Microelectronic package having multiple conductive paths through an opening in a support substrate: Microelectronic packages are disclosed. A microelectronic package may include a substrate having first and second sides. Passive components may be located on the first side of the substrate. Interconnects may also be located on the first side of the substrate, and may be electrically coupled with the passive components. Microelectronic... Agent: Blakely Sokoloff Taylor & Zafman

20070077751 - Method of restoring low-k material or porous low-k layer: A method of restoring a low-k material is described, applied to a substrate with a low-k material thereon, wherein the substrate has been subject to a previous process that raised the k-value of the low-k material. The method includes performing a plasma treatment to the low-k material to decrease the... Agent: Jianq Chyun Intellectual Property Office

20070077752 - Rework process for removing residual uv adhesive from c4 wafer surfaces: A method for the removal of residual UV radiation-sensitive adhesive from the surfaces of semiconductor wafers, remaining thereon from protective UV radiation-sensitive tapes which were stripped from the semiconductor wafers. Moreover, provided is an arrangement for implementing the removal of residual sensitive adhesive, which remain from tapes employed as protective... Agent: Steven Fischman, Esq. Scully, Scott, Murphy & Presser

20070077753 - Fabrication of via contacts having dual silicide layers: A method is provided for fabricating a via contact structure contacting a single-crystal semiconductor diffusion region at a top surface of a substrate. In such method, a first layer is formed in contact with the diffusion region at the top surface, the first layer consisting essentially of a silicide of... Agent: International Business Machines Corporation Dept. 18g

20070077754 - Contact spacer formation using atomic layer deposition: A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal deposited in the via.... Agent: Harrity Snyder, L.L.P.

20070077755 - Method of forming metal wiring in a semiconductor device: A method for forming metal wiring in a semiconductor device includes forming a first metal wiring, an etch stopping layer, and an interlayer insulation film on a semiconductor substrate. A via-hole and a trench are respectively formed by selectively removing a portion of the interlayer insulation film. The etch stopping... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070077756 - Methods of fabricating a fully silicided gate and semiconductor memory device having the same: A method of fabricating a semiconductor device having a fully silicided gate, the method includes: forming a gate insulation layer on a substrate; forming a polysilicon layer on the gate insulation film; transforming the polysilicon layer into a silicide layer; patterning the silicide layer to provide a gate electrode; forming... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070077757 - Method of forming metal wiring in semiconductor device: A method of forming a metal wiring in a semiconductor device includes forming a lower wiring layer, forming an etch stopping film and an interlayer insulation film, forming a photo-resist pattern, forming a via-hole using the photo-resist pattern as a mask, ashing the photo-resist pattern, cleaning the via-hole, etching a... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070077759 - Method for forming dielectric film and method for manufacturing semiconductor device by using the same: In a method of manufacturing a semiconductor device, a lower electrode of a capacitor is formed above a semiconductor substrate. Thermal treatment is carried out to a base layer, which includes the lower electrode, in an atomic layer deposition apparatus. A dielectric film is formed on the base layer after... Agent: Mcginn Intellectual Property Law Group, PLLC

20070077758 - Process for producing wiring circuit board: The present invention provides a process for producing a wiring circuit board which can be inhibited from developing whiskers and can be reduced in the unevenness of connectivity with electronic parts while retaining the connectivity. According to the present invention, a wiring pattern 12 comprising a thin metal film 31... Agent: Sughrue-265550

20070077760 - Method and apparatus for forming nickel silicide with low defect density in fet devices: A method and apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of... Agent: International Business Machines Corporation Dept. 18g

20070077762 - Method of accelerating test of semiconductor device: Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070077761 - Technique for forming a copper-based metallization layer including a conductive capping layer: By providing a conductive capping layer for metal-based interconnect lines, an enhanced performance with respect to electromigration may be achieved. Moreover, a corresponding manufacturing technique is provided in which via openings may be reliably etched into the capping layer without exposing the underlying metal, such as copper-based material, thereby also... Agent: Williams, Morgan & Amerson

20070077763 - Deposition technique to planarize a multi-layer structure: The present invention is directed to a method of coating a substrate having a solidified layer formed thereon, that features depositing a flowable material upon the solidified layer and forming an additional layer having a smooth flowable surface upon the substrate by imparting rotational movement upon the substrate followed by... Agent: Molecular Imprints

20070077764 - Polishing method, polishing composition and polishing composition kit: A polishing method for polishing a polysilicon film provided on a silicon substrate having an isolation region is provided. The method includes preliminarily polishing the polysilicon film using a preliminary polishing composition containing abrasive grains, an alkali, a water-soluble polymer, and water till a part of the top surface of... Agent: Vidas, Arrett & Steinkraus, P.A.

20070077765 - Etch stop and hard mask film property matching to enable improved replacement metal gate process: A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard... Agent: Blakely Sokoloff Taylor & Zafman

20070077766 - Method for fabricating image sensor: The present invention relates to a method of fabricating an image sensor wherein it can enhance adhesive strength between an USG layer and a SiN layer. The method of fabricating the image sensor according to the present invention includes patterning a metal pad on a circuit region of a substrate;... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070077767 - Method of plasma etching of high-k dielectric materials: A method of etching high dielectric constant materials using a halogen gas, a reducing gas and an etch rate control gas chemistry.... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070077768 - Substrate processing method: A substrate processing method includes: performing an etching process to form a predetermined pattern on an etching-target film disposed on a substrate; denaturing a substance remaining after the etching process to be soluble in a predetermined liquid; then, performing a silylation process on a surface of the etching-target film having... Agent: Smith, Gambrell & Russell

20070077769 - Method of removing organic contaminants from a semiconductor surface: A method for removing organic contaminants from a semiconductor surface whereby the semiconductor is held in a tank and the tank is filled with a fluid such as a liquid or a gas. Organic contaminants, such as photoresist, photoresidue, and dry etched residue, occur in process steps of semiconductor fabrication... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070077770 - Etching technique to planarize a multi-layer structure: The present invention is directed to a method of etching a multi-layer structure formed from a layer of a first material and a layer of a second material differing from the first material to obtain a desired degree of planarization. To that end, the method includes creating a first set... Agent: Molecular Imprints

20070077772 - Apparatus and method for manufacturing semiconductor device using plasma: An apparatus and related manufacturing method for semiconductor devices are disclosed. A plasma generator is used to convert a plasma source into plasma. Plasma particles are then captured in plasma capsules formed from a protective layer, and introduced into a process chamber adapted to form a material layer on a... Agent: Volentine Francos, & Whitt PLLC

20070077775 - Deposition of tin films in a batch reactor: Titanium nitride (TiN) films are formed in a batch reactor using titanium chloride (TiCl4) and ammonia (NH3) as precursors. The TiCl4 is flowed into the reactor in temporally separated pulses. The NH3 can also be flowed into the reactor in temporally spaced pulses which alternate with the TiCl4 pulses, or... Agent: Knobbe Martens Olson & Bear LLP

20070077774 - Method for manufacturing a semiconductor device having a stepped contact hole: A process for forming a stepped contact hole includes: dry-etching a portion of a silicon oxide film using a mixed gas including carbon-rich fluorocarbon gas to form a first contact hole, forming a specific film on the sidewall of the first contact hole; dry-etching the remaining portion of the silicon... Agent: Young & Thompson

20070077771 - Method for producing buried micro-channels and micro-device comprising such micro-channels: The invention relates to a method for producing at least one buried micro-channel on a substrate consisting in applying and moving an optic radiation on a stacking in a predetermined direction. The stacking successively comprises a deformable absorbent thin layer and a thin-layer formed by a material able to locally... Agent: Oliff & Berridge, PLC

20070077773 - Technique for creating different mechanical strain in different cpu regions by forming an etch stop layer having differently modified intrinsic stress: The present invention provides a technique for reducing stress or stress gradients in highly sensitive device regions, such as cache areas, while still providing high transistor performance in logic areas by correspondingly providing contact etch stop layers with compressive and tensile stress for P-channel transistors and N-channel transistors in these... Agent: Williams, Morgan & Amerson

20070077776 - Method for forming an insulating film in a semiconductor device: This invention provides a method for forming a semiconductor device, capable of preventing as many impurities as possible, which cause deterioration in film quality, from existing in an gate insulating film. In this invention, a step of forming an insulating film so as to have a thickness in the range... Agent: Cantor Colburn, LLP

20070077777 - Method of forming a silicon oxynitride film with tensile stress: A method for forming a densified silicon oxynitride film with tensile stress and a semiconductor device including the densified silicon oxynitride film. The densified silicon oxynitride film can be formed by depositing a porous SiNC:H film on a substrate in a LPCVD process, and exposing the porous SiNC:H film to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070077778 - Method of forming low dielectric constant layer: Dielectric layers having a low dielectric constant are fabricated by using an asymmetric organocyclosiloxane as a precursor gas. The carbon content of the deposited layer is reduced to less than about 50 percent by use an oxidizing agent, a silicon containing compound, or a combination thereof.... Agent: The Boc Group, Inc.

20070077779 - Poly(organosiloxane) materials and methods for hybrid organic-inorganic dielectrics for integrated circuit applications: fully fluorinated; and M1 is an element from group I of the periodic table; so as to form a compound of the general formula R1MOR33; hydrolyzing and condensing R1MOR33 so as to form a hybrid organic-inorganic material with a molecular weight of at least 500; depositing the hybrid organic-inorganic material... Agent: Kubovcik & Kubovcik

20070077780 - Process to open carbon based hardmask: A method of opening a carbon-based hardmask layer composed of amorphous carbon containing preferably at least 60% carbon and between 10 and 40% hydrogen. The hardmask is opened by plasma etching using an etching gas composed of H2, N2, and CO. The etching is preferably performed in a plasma etch... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20070077781 - Plural treatment step process for treating dielectric films: A method and computer readable medium for treating a dielectric film on one or more substrates includes disposing the one or more substrates in a process chamber configured to perform plural treatment processes on a dielectric film. The dielectric film is formed on at least one of said one or... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070077782 - Treatment of low dielectric constant films using a batch processing system: A method and system for treating a dielectric film in a batch processing system includes exposing at least one surface of the dielectric film to a treating compound including a CxHy containing compound, where x and y represent integers greater than or equal to unity. The plurality of wafers are... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.