Semiconductor device manufacturing: process inventions 03/07

20070072312 - Interconnect connecting a diffusion metal layer and a power plane metal and fabricating method thereof: A giant magnetoresistance (GMR) pad on the same level of GMR memory bit layer is used as an intermediate connection for plugs between the GMR pad and an underlying diffusion metal layer. A single large power metal plug is used to connect the GMR pad and the overlying power plane... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070072311 - Interconnect for a gmr stack layer and an underlying conducting layer: Metal plugs located in a planar dielectric layer, under a GMR stack layer, are used to connect the nonmagnetic conducting layer of the GMR stack layer and a conducting layer under the planar dielectric layer.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070072310 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising a semiconductor substrate and memory cells. Each memory cell comprises a switching transistor and a ferroelectric capacitor, both formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film held between the lower and upper electrodes. A first wire... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072313 - Anisotropic conductive connector and circuit device inspection method: It is an object to provide an anisotropically conductive connector having an excellent repetitive use durability and a method of inspecting a circuit device having a high inspection efficiency which are used in the inspection of the circuit device such as a semiconductor integrated circuit having a solder projected electrode.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072315 - Method and system for reliability similarity of semiconductor devices: A method and system for reliability similarity of semiconductor devices. The method includes providing a first plurality of semiconductor devices, providing a second plurality of semiconductor devices, and determining a first reliability associated with the first plurality of semiconductor devices. The first reliability is represented by at least a first... Agent: Townsend And Townsend And Crew, LLP

20070072317 - Method for predicting contributions of silicon interstitials to n-type dopant transient enhanced diffusion during a pn junction formation: A method for predicting the contribution of silicon interstitials to n-type dopant transient enhanced diffusion during a pn junction formation is disclosed. Initially, fundamental data for a set of microscopic processes that can occur during one or more material processing operations are obtained. The fundamental data are then utilized to... Agent: Dillon & Yudell LLP

20070072318 - Method for predicting the formation of silicon nanocrystals in embedded oxide matrices: A method for predicting the formation of silicon nanocrystals in an oxide matrix is disclosed. Initially, fundamental data for a set of microscopic processes that can occur during one or more material processing operations are obtained. Kinetic models are then built by utilizing the fundamental data for a set of... Agent: Dillon & Yudell LLP

20070072314 - Method of preparing an integrated circuit die for imaging: Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be removed, especially if they are formed from the same metal as the metal lines, as in copper damascene... Agent: Ogilvy Renault LLP

20070072316 - Wiring pattern determination method and computer program product thereof: A wiring pattern determination method and a computer program thereof comprise a step of moving positions of tentatively designed plated leads on an edge of a semiconductor package to the positions that can be accommodated in positionable windows nearest to the respective tentatively designed plated lead positions, in a template... Agent: Chadbourne & Parke, L.L.P.

20070072319 - Integrated circuit capacitor structure: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first... Agent: Marger Johnson & Mccollom, P.C.

20070072320 - Process for producing an epitalixal layer of galium nitride: A method of manufacturing a low defect density GaN material comprising at least two step of growing epitaxial layers of GaN with differences in growing conditions, (a.) a first step of growing an epitaxial layer GaN on an epitaxially compentent layer under first growing conditions selected to induce island features... Agent: Blakely Sokoloff Taylor & Zafman

20070072321 - Device package and methods for the fabrication and testing thereof: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second... Agent: Rohm And Haas Electronic Materials LLC

20070072322 - Methods for patterning films, fabricating organic electroluminescence display and fabricating thin film transistor array substrate: A method for fabricating a thin film transistor array substrate is provided. Wherein, a plurality of contact holes and recesses are formed in a protection layer disposed upon thin film transistors. Each recess comprises an under-cut profile while each contact hole exposes a drain-metal layer of a corresponding thin film... Agent: Jianq Chyun Intellectual Property Office

20070072323 - Method of manufacturing display panel for flexible display device: A liquid crystal display panel manufacturing method includes forming at least one thin film on a flexible plastic substrate by sputtering at a temperature of about 80° C. to about 150° C. Sputtering can be in a chamber evacuated to about 1×10−6 Torr to about 9×10−6 Torr. Sputtering targets and... Agent: Macpherson Kwok Chen & Heid LLP

20070072324 - Substrate for growing a iii-v light emitting device: A substrate including a host and a seed layer bonded to the host is provided, then a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. In some embodiments, a bonding layer bonds the host to the... Agent: Patent Law Group LLP

20070072326 - Photodiode for multiple wavelength operation: A method of a fabricating a multiple wavelength adapted photodiode and resulting photodiode includes the steps of providing a substrate having a first semiconductor type surface region on at least a portion thereof, implanting and forming a second semiconductor type shallow surface layer into the surface region, and forming a... Agent: Akerman Senterfitt

20070072325 - Self-aligned photodiode for cmos image sensor and method of making: A method for forming a photodiode that is self-aligned to a transfer gate while being compatible with a metal silicide process is disclosed. The method comprises forming a gate stack of gate oxide, polysilicon, and a sacrificial/disposable cap insulator over the polysilicon. The insulator may be a combination of silicon... Agent: Perkins Coie LLP

20070072329 - Method and apparatus for manufacturing a display apparatus: A light-shielding layer is formed and patterned on a front substrate that is opposed to a back substrate and on which a number of electron-emitting elements are arranged. A phosphor layer is formed and patterned on the part on which the light-shielding layer is not provided. A metal back layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072328 - Method and system for hermetically sealing packages for optics: A system for hermetically sealing devices. The system includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of... Agent: Townsend And Townsend And Crew, LLP

20070072327 - Method of forming an integrated mems resonator: A method of producing an integrated MEMS resonator includes providing a substrate including single crystal silicon and partially forming a resonator in a first portion of the substrate, the resonator having a resonating element formed by the substrate and an electrode, the resonating element and the electrode forming a variable... Agent: Bromberg & Sunstein LLP

20070072331 - Method for manufacturing a micro-electro-mechanical device: A technique for manufacturing a micro-electro-mechanical (MEM) device includes a number of steps. Initially, a first wafer is provided. Next, a bonding layer is formed on a first surface of the first wafer. Then, a portion of the bonding layer is removed to provide a cavity including a plurality of... Agent: Delphi Technologies, Inc.

20070072330 - Wafer bonding compatible with bulk micro-machining: A method for forming a microstructure is disclosed in which, after a polymer substance has been applied to a first substrate, the first substrate is micromachined to remove at least one portion of the first substrate. A second substrate is then adhered to the first substrate via the polymer substance.... Agent: Wolf Greenfield & Sacks, PC

20070072332 - Semiconductor radiation detectors and method for fabrication thereof: The invention relates to a method for fabricating semiconductor radiation detectors comprising a bulk of a first conductivity type for detecting radiation with further semiconductor layers of a second and a first conductivity type patterned thereon, at least one of the further semiconductor layers being deposited by epitaxy. The invention... Agent: Jeffrey S. Habib, Esq. Hooker & Habib, P.C.

20070072333 - Reduced barrier photodiode / gate device structure for high efficiency charge transfer and reduced lag and method of formation: A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is... Agent: Dickstein Shapiro LLP

20070072334 - Semiconductor fabrication process employing spacer defined vias: A semiconductor fabrication process includes forming a first etch mask (131) that defines a first opening (132) and a second etch mask (140) that defines a second opening (142) overlying an interlevel dielectric (ILD) (108). The ILD (108) is etched to form a first via (154) defined by the first... Agent: Freescale Semiconductor, Inc. Law Department

20070072336 - Method of manufacturing nano size-gap electrode device: Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed... Agent: Ladas & Parry LLP

20070072337 - Method of manufacturing the organic electroluminescent display and organic electroluminescent display manufactured by the method: The present invention provides an organic EL display panel manufacturing method which is capable of forming a desired organic film or the like with high accuracy without imparting damages to a substrate and an organic film and an organic EL display panel which is manufactured by the method. An opening... Agent: Stanley P. Fisher Reed Smith LLP

20070072335 - Semiconductor devices having nano-line channels and methods of fabricating the same: A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line... Agent: Myers Bigel Sibley & Sajovec

20070072340 - Electronic device with inductor and integrated componentry: Semiconductor devices and methods for their assembly are described in which inductor elements and additional passive or active circuit components may be combined in novel configurations. An electronic device and associated methods provide an inductor element encapsulated within a dielectric package, the inductor package having a plurality of electrical contacts... Agent: Sam Tung Texas Instruments Incorporated

20070072338 - Method for separating package of wlp: The present invention provides a semiconductor device package singulation method. The method comprises printing a photo epoxy layer on the back surface of a substrate of a wafer for marking the scribe lines to be diced. Then etching is performed through the substrate along the marks in the photo epoxy... Agent: Kusner & Jaffe Highland Place Suite 310

20070072339 - Process for fabricating chip package structure: A process for fabricating a chip package structure is disclosed. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier... Agent: Jianq Chyun Intellectual Property Office

20070072341 - Die package and method for making the same: The present invention relates to a die package and method for making the same. The method of the invention comprises the steps of: (a) providing a plate, having a first surface and a second surface; (b) forming a plurality of first dice on the plate, the first dice having a... Agent: Volentine Francos, & Whitt PLLC

20070072342 - Depopulation of a ball grid array to allow via placement: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path... Agent: Blakely Sokoloff Taylor & Zafman

20070072343 - Semiconductor constructions comprising multi-level patterns of radiation-imageable material: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with... Agent: Wells St. John P.s.

20070072344 - Gel package structural enhancement of compression system board connections: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by... Agent: Lynn L. Augspurger IBM Corporation

20070072345 - Semiconductor device and method for manufacturing the same: A method of manufacturing a semiconductor device is disclosed, which includes at least the steps of preparing a laminated structure including a single chip or a plurality of chips, and dividing the laminated structure into a plurality of sub-laminated structures. A laminated structure comprised of a silicon substrate and a... Agent: GlobalIPCounselors, LLP

20070072347 - Method of assembly for multi-flip chip on lead frame on overmolded ic package: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller... Agent: Hiscock & Barclay, LLP

20070072346 - Method of resin-seal-molding electronic component and apparatus therefor: A mold for resin-seal-molding an electronic component is constituted by a first mold and a second mold. At a mold face (PL face) of the molds, a substrate supply-set surface having a flat shape without a step is provided. A pot block is joined with and separated from a side... Agent: Birch Stewart Kolasch & Birch

20070072349 - Manufacturing method of a display device: The present invention provides a manufacturing method of a display device which can decrease the lowering of a yield rate of the display device attributed to the aggregations generated by pseudo single crystallization of a silicon film. A manufacturing method of a display device includes a semiconductor film reforming step... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070072348 - Method of manufacturing an amoled: The present invention relating to a method of manufacturing an AMOLED panel. The method comprises providing a substrate, forming a TFT on the substrate, forming an inter-layer insulator layer, forming a plurality of via holes, forming a metal layer which electrically contacts a source and a drain, forming a transparent... Agent: North America Intellectual Property Corporation

20070072350 - Method of manufacturing semiconductor device: In a step of doping a silicon-based semiconductor film as a TFT active layer such as channel doping or the like, a protective film is formed by a CVD method as a pretreatment so as to prevent the silicon-based semiconductor film from being contaminated and etched. However, in the case... Agent: Eric Robinson

20070072351 - Method of fabricating semiconductor device: An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072352 - Insulated gate field effect transistor and manufacturing method thereof: A separation hole is provided in the center of the gate electrode. Accordingly, it is possible to suppress a drastic increase in feedback capacitance Crss in the case where drain-source voltage VDS is decreased and the width of the depletion layer is narrowed. Thus, high-frequency switching characteristics are improved. Moreover,... Agent: Morrison & Foerster LLP

20070072353 - Method of fabricating strained-silicon transistors and strained-silicon cmos transistors: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process... Agent: North America Intellectual Property Corporation

20070072354 - Structures with planar strained layers: A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar,... Agent: Goodwin Procter LLP Patent Administrator

20070072355 - Method of manufacturing semiconductor device: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070072356 - Method for reducing positive charges accumulated on chips during ion implantation: In the plasma etching process of the integrated circuit, a portion of the charges from the plasma accumulates on the semiconductor device through the conductive portion of the integrated circuit so as to damage the device. The phenomenon mentioned above is so called antenna effect. In order to decreased the... Agent: Jianq Chyun Intellectual Property Office

20070072357 - Method of manufacturing devices having vertical junction edge: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and... Agent: Michael G. Fletcher Fletcher Yoder

20070072358 - Method of manufacturing metal-oxide-semiconductor transistor devices: A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed. In the method, a silicon nitride spacer is formed and will be removed after an ion implantation process to form a source/drain region and a salicide process to form a metal silicide layer on the surface of the source/drain region... Agent: North America Intellectual Property Corporation

20070072359 - Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the... Agent: Rossi, Kimms & Mcdowell LLP.

20070072360 - Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance: A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias,... Agent: Patent Dept., Sandisk 3d LLC(matrix)

20070072361 - Method of reducing current leakage in a metal insulator metal semiconductor capacitor and semiconductor capacitor thereof: A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top... Agent: North America Intellectual Property Corporation

20070072362 - Solid electrolytic capacitor, fabrication method thereof, and coupling agent utilizing in the same: A solid electrolytic capacitor, fabrication method, and coupling agent utilized in the same. The capacitor includes a valve metal layer, an oxide dielectric layer on at least a part of the surface of the valve metal layer, a coupling layer having a molecular chain with a first end bonding to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070072363 - Method for fabricating transistor gate structures and gate dielectrics thereof: Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may... Agent: Texas Instruments Incorporated

20070072364 - Method for fabricating transistor gate structures and gate dielectrics thereof: Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may... Agent: Texas Instruments Incorporated

20070072368 - Method of cleaning semiconductor surfaces: Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include cleaning using a supercritical fluid. Advantages include a combination of both chemical and mechanical removal abilities from the supercritical fluid. Mechanical energy for cleaning is... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070072367 - Method of manufacturing semiconductor silicon substrate: The present invention provides a method of manufacturing a semiconductor silicon substrate provided with a capacitor structure having a capacitor hole, the capacitor hole having a depth of equal to or greater than 3 μm and an aspect ratio equal to or greater than 30, the method including at least:... Agent: Mcdermott Will & Emery LLP

20070072365 - Methods of forming a recessed gate: A method of forming a recessed gate may include forming a gate recess including an upper recess and a lower recess at an upper portion of a semiconductor substrate, the lower recess may have a width substantially wider than that of the upper recess, forming a gate insulation layer on... Agent: Lee & Morse, P.C.

20070072366 - Transistor structure for semiconductor device and method of fabricating the same: A transistor for a semiconductor device may include a lower semiconductor layer, an active pattern, including a groove region, on the lower semiconductor layer, a gate pattern at least partially overlapping the active pattern including the groove region, and a gate insulating layer interposed between the active pattern and the... Agent: Lee & Morse, P.C.

20070072373 - Fabrication method of an non-volatile memory: A non-volatile memory cell is provided. The non-volatile memory includes a substrate, a gate stacked layer, an isolation layer and a conductive layer. The gate stacked layer includes a tunneling layer, a charge trapping layer, a barrier layer and a control gate layer sequentially stacked over the substrate, and the... Agent: Jianq Chyun Intellectual Property Office

20070072372 - Method for forming metal line in flash memory device: A method for forming a metal line in a flash memory device includes sequentially forming a first inter-layer insulation layer, an etch stop layer, a second inter-layer insulation layer, and a hard mask layer over a substrate where a contact plug is formed, etching the hard mask layer to form... Agent: Blakely Sokoloff Taylor & Zafman

20070072369 - Non-volatile memory and fabricating method thereof: A non-volatile memory includes a substrate, a plurality of isolation layers, a plurality of active layers, a plurality of floating gates, a plurality of control gates and a plurality of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the... Agent: Jianq Chyun Intellectual Property Office

20070072370 - Non-volatile memory and fabricating method thereof: A method for fabricating a non-volatile memory is described. A substrate having isolation structures is provided. These isolation structures protrude from the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mask layer is formed on the substrate. The second and the... Agent: Jianq Chyun Intellectual Property Office

20070072371 - Semiconductor device and method for fabricating the same: A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to... Agent: Mcdermott Will & Emery LLP

20070072374 - Semiconductor device: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072375 - Method for manufacturing semiconductor device: a method for manufacturing a semiconductor device comprises the steps of forming a gate trench in a semiconductor substrate, forming a gate insulation film in an inner wall of the gate trench, filling a gate electrode material into at least an inside of the gate trench, forming a gate electrode... Agent: Mcdermott Will & Emery LLP

20070072376 - Strained-induced mobility enhancement nano-device structure and integrated process architecture for cmos technologies: A CMOS semiconductor integrated circuit device. The CMOS device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within... Agent: Townsend And Townsend And Crew, LLP

20070072377 - Process of making a iii-v compound semiconductor heterostructure mosfet: A method of forming a compound semiconductor device comprises forming a gate insulator layer overlying a compound semiconductor substrate, defining an active device region within the compound semiconductor substrate, forming ohmic contacts to the compound semiconductor substrate proximate opposite sides of the active device region, and forming a gate metal... Agent: Freescale Semiconductor, Inc. Law Department

20070072378 - Method of manufacturing metal-oxide-semiconductor transistor devices: A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed. In the method, a silicon nitride spacer is formed and will be removed after an ion implantation process used to form a source/drain region and a salicide process used to form a metal silicide layer on the surface of the... Agent: North America Intellectual Property Corporation

20070072379 - Mos transistor and manufacturing method thereof: Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, and a silicon carbide layer is deposited... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070072381 - Method for fabricating a semiconductor device including the use of a compound containing silicon and nitrogen to form an insulation film of sin, sicn or siocn: The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070072380 - Methods for fabrication of a stressed mos device: Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed overlying the monocrystalline semiconductor substrate. The substrate is... Agent: Ingrassia Fisher & Lorenz, P.C.

20070072382 - Method of manufacturing semiconductor device: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070072383 - Phosphorus activated nmos using sic process: A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure... Agent: Texas Instruments Incorporated

20070072384 - Plastically deformable irreversible storage medium and method of producing one such medium: The storage medium comprises an array of memory cells (3) which can be addressed by first (1) and second (2) conductors. Each memory cell (3) comprises one zone (10) of an active layer (8) which is initially electrically insulating and which can be made electrically conductive by means of localised... Agent: Oliff & Berridge, PLC

20070072385 - Electrical open/short contact alignment structure for active region vs. gate region: An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070072386 - Method of forming an alignment key having a capping layer and method of fabricating a semiconductor device using the same: A method of forming an alignment key with a capping layer in a semiconductor device without an additional mask formation process, and a method of fabricating a semiconductor device using the same, may be provided. The method of forming an alignment key may include forming an isolation layer confining an... Agent: Harness, Dickey & Pierce, P.L.C

20070072388 - Bottle-shaped trench and method of fabricating the same: Fabrication of a bottle-shaped trench is disclosed. A semiconductor substrate with a trench therein is provided. An ion-doped barrier layer is formed in the trench, exposing the upper portion surfaces of the sidewall of the trench. An ion implantation is performed on the upper portion surfaces of the sidewall of... Agent: Birch Stewart Kolasch & Birch

20070072387 - Method of fabricating shallow trench isolation structure: A method of fabricating a shallow trench isolation structure is provided. A substrate having a patterned pad layer is provided. A part of the substrate is removed by using the patterned pad layer as a mask and a trench is thus formed in the substrate. A first insulation layer is... Agent: Jianq Chyun Intellectual Property Office

20070072389 - Method for fabricating semiconductor device having taper type trench: A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070072390 - Techniques for removal of photolithographic films: Techniques for removal of photolithographic films used in the manufacture of semiconductor devices are provided. A substrate support member of a first processing chamber includes at least three retractable pins capable of elevating a wafer from a surface of the substrate support member. In addition, the first processing chamber is... Agent: Townsend And Townsend And Crew, LLP

20070072392 - Method of cleaning cover glass having spacer: The present invention provides a method of cleaning a cover glass having a spacer which is to be incorporated in a solid image pickup device, comprising: a dry cleaning step performed after dry etching; a wipe-off cleaning step performed after the dry cleaning step; a primary wet cleaning step performed... Agent: Sughrue Mion, PLLC

20070072391 - Method of sealing two plates with the formation of an ohmic contact therebetween: e

20070072393 - Method for preparing and assembling substrates: A method for assembling a first and a second wafer of material, including routing at least the first wafer and assembling the first and second wafer.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072394 - Semiconductor device manufacturing apparatus, semiconductor device manufacturing method and semiconductor device: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072395 - Substrate and method of separating components from a substrate: A substrate (1) having a first groove (4) is provided with a plurality of protrusions (3) on the first groove (4). These protrusions (4) can have a top with an apex angle of 30 to 150 degrees and results in a controlled breaking of the substrate (1) and a minimum... Agent: Philips Intellectual Property & Standards

20070072398 - Method for manufacturing semiconductor device and epitaxial growth equipment: A method for manufacturing a semiconductor device includes steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the main surface and in the trench; and forming a second epitaxial film on the first epitaxial film. The step of forming the... Agent: Posz Law Group, PLC

20070072396 - Method of producing self supporting substrates comprising iii-nitrides by means of heteroepitaxy on a sacrificial layer: The invention relates to a method for the production of self-supporting substrates comprising element III nitrides. More specifically, the invention relates to a method of producing a self-supporting substrate comprising a III-nitride, in particular, gallium nitride (GaN), which is obtained by means of epitaxy using a starting substrate. The invention... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20070072397 - Semiconductor device, method for manufacturing the same and method for evaluating the same: A method for manufacturing a semiconductor device includes steps of: forming a first epitaxial film on a silicon substrate; forming a trench in the first epitaxial film; and forming a second epitaxial film on the first epitaxial film and in the trench. The step of forming the second epitaxial film... Agent: Posz Law Group, PLC

20070072399 - Semiconductor devices having epitaxial layers with suppressed lateral growth and related methods of manufacturing such devices: Semiconductor devices are provided having a selective epitaxial growth layer that exhibits suppressed lateral growth. These semiconductor devices may include a semiconductor substrate having a silicon region, and an epitaxial growth layer formed on the silicon region. The epitaxial growth layer may comprise alternatively stacked silicon and silicon germanium epitaxial... Agent: Myers Bigel Sibley & Sajovec

20070072400 - Apparatus and methods for thermally processing undoped and lightly doped substrates without pre-heating: Apparatus for and methods of thermally processing undoped or lightly doped semiconductor wafers (30) that typically are not very absorptive of an annealing radiation beam (14) are disclosed. The apparatus (10) uses a relatively low power activating radiation beam (240) with a photon energy greater than the bandgap energy of... Agent: Allston L. Jones Peters, Verny, Jones, Schmitt & Aston L.L.P.

20070072401 - Method for purifying a metal carbonyl precursor: A method of purifying a metal carbonyl precursor in a metal precursor vaporization system where the metal carbonyl precursor comprises a metal particulate impurity. The method includes flowing a CO-containing gas through the metal precursor vaporization system to a precursor collection system in fluid communication with the metal precursor vaporization... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070072402 - Method of fabricating semiconductor devices and method of removing a spacer: A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on... Agent: North America Intellectual Property Corporation

20070072403 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device includes the steps of forming a high-k layer insulating layer on a SOI substrate; forming a gate electrode layer on the high-k insulating layer; forming a resist layer on the gate electrode layer; removing selectively the gate electrode layer using the resist layer... Agent: Rabin & Berdo, PC

20070072404 - Phase-change optical disk: A phase-change optical disk includes a layer structure including a ZnS—SiO2 first dielectric layer, an oxynitride second dielectric layer including SiHfON, a ZnS—SiO2 third dielectric layer, a GeN interface layer, a Ge2Sb2Te5 recording layer, a GeN interface layer, a ZnS—SiO2 dielectric layer, and a reflective layer, which are consecutively deposited... Agent: Foley And Lardner LLP Suite 500

20070072405 - Semiconductor device and method for manufacturing the same: There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. An insulating resin layer which insulates metal wires from one... Agent: Stevens, Davis, Miller & Mosher, LLP

20070072408 - Fabrication method of semiconductor integrated circuit device: The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves,... Agent: Miles & Stockbridge PC

20070072407 - Method of fabricating self-aligned contact pad using chemical mechanical polishing process: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping... Agent: F. Chau & Associates, LLC

20070072406 - Methods of forming integrated circuit devices having metal interconnect structures therein: Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first... Agent: Myers Bigel Sibley & Sajovec

20070072410 - Method of forming copper interconnection using dual damascene process: Disclosed is a method of forming a copper interconnection using a dual damascene process. The method generally prevents formation of an undeveloped photoresist caused by the topology between a via hole and a trench and reduces or prevents defects in the copper interconnection, such as disconnection, via holes or voids.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070072409 - Reflector with non-uniform metal oxide layer surface: A reflector includes a non-uniform metal oxide layer surface.... Agent: Hewlett Packard Company

20070072411 - Method for forming metal line in semiconductor device: A method for forming a metal line in a semiconductor device includes forming a plug buried in an inter-layer insulation layer formed over a substrate, forming a metal line layer over the plug and the substrate, forming a contact mask over the metal line layer, etching first portions of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070072412 - Preventing damage to interlevel dielectric: Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of the opening. The re-sputtered... Agent: Hoffman, Warnick & D'alessandro LLC

20070072413 - Methods of forming copper interconnect structures on semiconductor substrates: Methods of forming copper interconnect structures according to embodiments of the present invention include forming an electrically insulating layer having a recess therein on a semiconductor substrate and then forming a layer of copper having a thickness greater than about 3000 Å on an upper surface of the electrically insulating... Agent: Myers Bigel Sibley & Sajovec

20070072414 - Method for controlling the step coverage of a ruthenium layer on a patterned substrate: A method for forming a Ru layer for an integrated circuit by providing a patterned substrate in a process chamber, and exposing the substrate to a process gas comprising a ruthenium carbonyl precursor and a CO gas to form a Ru layer over a feature of the patterned substrate. In... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070072415 - Method for integrating a ruthenium layer with bulk copper in copper metallization: A method for integrating a Ru layer with bulk Cu in semiconductor manufacturing. The method includes depositing a Ru layer onto a substrate in a chemical vapor deposition process, modifying the deposited Ru layer by oxidation, or nitridation, or a combination thereof, depositing an ultra thin Cu layer onto the... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070072416 - Method of forming a low resistance semiconductor contact and structure therefor: In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070072417 - Method for forming wiring structure, wiring structure, method for forming semiconductor device, and display device: A method for forming a wiring structure includes forming a metal layer on a substrate, and annealing the metal layer by irradiating the metal layer with light emitted from at least one flash tube, thereby growing crystalline grains of the metal layer.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072418 - Method of forming tungsten silicide layer and method of fabricating semiconductor element using same: A method of forming a tungsten silicide layer and a related method of fabricating a semiconductor element. The method of forming the tungsten silicide layer includes forming a pre-coating layer within a CVD process chamber by injecting a tungsten source gas (A) and a silicon source gas (B) at a... Agent: Volentine Francos, & Whitt PLLC

20070072419 - Chip, ship stack, and method of manufacturing the same: Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in... Agent: Blakely Sokoloff Taylor & Zafman

20070072420 - Method of forming copper interconnection using dual damascene process and semiconductor device having copper interconnection according to the same: Disclosed is a method of forming a copper interconnection using a dual damascene process, in which an etch profile anomaly and the trench depth variation caused by the trench etching process are reduced or prevented, so that the copper interconnection is obtained substantially without voids or interconnection defects. The method... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070072422 - Hydrogen treatment to improve photoresist adhesion and rework consistency: A process for selectively removing photoresist, organic overlayers, and/or polymers/residues from a substrate without altering the surface chemistry and adhesion properties of the underlying substrate layers is provided. Generally, the process includes pretreating the substrate with hydrogen (e.g., by way of a hydrogen-based plasma) prior to deposition of a photoresist... Agent: Townsend And Townsend And Crew LLP / Amat

20070072421 - Method to passivate defects in integrated circuits: Defects in an integrated circuit are electrically passivated. A hydrogen diffusion blocking film is placed on the integrated circuit. Atomic hydrogen is implanted through the hydrogen diffusion blocking film. The integrated circuit is annealed so that the implanted atomic hydrogen diffuses towards locations where the defects are concentrated.... Agent: Avago Technologies, Ltd.

20070072423 - Unpolished semiconductor wafer and method for producing an unpolished semiconductor wafer: Unpolished semiconductor wafers are produced by: (a) pulling a single crystal of a semiconductor material, (b) grinding the single crystal round, (c) separating a semiconductor wafer from this crystal, (d) rounding the edge of the semiconductor wafer, (e) surface-grinding at least one side of the semiconductor wafer, (f) treating the... Agent: Brooks Kushman P.C.

20070072424 - Method of manufacturing silicon rich oxide (sro) and semiconductor device employing sro: Provided are methods for manufacturing silicon rich oxide (SRO) layers useful in the fabrication of semiconductor devices, for example, non-volatile memory devices, and methods for fabricating semiconductor devices incorporating such SRO layers. The methods include absorbing a first silicon source gas onto the substrate, oxidizing the first absorbed layer to... Agent: Harness, Dickey & Pierce, P.L.C

20070072426 - Chemical mechanical polishing process and apparatus therefor: A CMP process and a CMP apparatus therefor are provided. First, a substrate including a semiconductor structure, a liner layer over the semiconductor structure and a metal layer over the liner layer is provided. Next, a metal polishing step is performed to polish the metal layer until a portion of... Agent: Jianq Chyun Intellectual Property Office

20070072427 - Method for fabricating semiconductor device and polishing method: A method for fabricating a semiconductor device includes forming a copper film above a surface of a substrate, forming on a polishing pad a material which contains copper, wherein said copper does not derive from said copper film, and after having formed the copper-containing material on said polishing pad, polishing... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070072425 - Substrate and method for producing same: A substrate according to the present invention includes a metal plate, and an insulating film, which is provided on the surface of the metal plate and which includes needle alumina particles and granular particles. The substrate of the present invention has excellent insulating property and can be manufactured on an... Agent: Nixon Peabody, LLP

20070072428 - Method for manufacturing a micro-electro-mechanical structure: A technique for manufacturing a micro-electro-mechanical (MEM) structure includes a number of steps. Initially, a substrate is provided. Next, a plurality of trenches are etched into the substrate with a first etch. Then, a charging layer is formed at a bottom of each of the trenches to form undercut trenches.... Agent: Delphi Technologies, Inc.

20070072429 - Pattern enhancement by crystallographic etching: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to... Agent: Scully Scott Murphy & Presser, PC

20070072431 - Method for cleaning substrate having exposed silicon and silicon germanium layers and related method for fabricating semiconductor device: A method for cleaning a substrate on which a silicon layer and a silicon germanium layer are formed and exposed, and method for fabricating a semiconductor device using the cleaning method are disclosed. The cleaning method comprises preparing a semiconductor substrate on which a silicon layer and a silicon germanium... Agent: Volentine Francos, & Whitt PLLC

20070072430 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includes the steps... Agent: Cooper & Dunham, LLP

20070072433 - Apparatus for the removal of a fluorinated polymer from a substrate and methods therefor: An apparatus generating a plasma for removing fluorinated polymer from a substrate is disclosed. The embodiment includes a powered electrode assembly, including a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The embodiment also includes a grounded... Agent: Ipsg, P.C.

20070072432 - Apparatus for the removal of a metal oxide from a substrate and methods therefor: An apparatus generating a plasma for removing metal oxide from a substrate is disclosed. The embodiment includes a powered electrode assembly, including a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The embodiment also includes a grounded... Agent: Ipsg, P.C.

20070072434 - Method and system for operating a physical vapor deposition process: A method for fabricating semiconductor wafers using physical vapor deposition. The method includes maintaining a substrate on a susceptor in a chamber. The substrate has a face positioned within a vicinity of a target material, which is within the chamber. The target member comprises a first side and a second... Agent: Townsend And Townsend And Crew, LLP

20070072435 - Method for plasma etching a chromium layer through a carbon hard mask suitable for photomask fabrication: Methods for etching chromium and forming a photomask using a carbon hard mask are provided. In one embodiment, a method of a chromium layer includes providing a substrate in a processing chamber, the substrate having a chromium layer partially exposed through a patterned carbon hard mask layer, providing a process... Agent: Patterson & Sheridan, LLP

20070072436 - Substrate processing apparatus and substrate processing method: In a substrate processing apparatus of the present invention, when substrates are loaded into a chamber, a frame part formed integral with a substrate holding part is interposed between the chamber and a cover, thereby sealing the interior of the chamber. When the substrates are unloaded to above the chamber,... Agent: Ostrolenk Faber Gerb & Soffen

20070072437 - Method for forming narrow structures in a semiconductor device: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered... Agent: Harrity Snyder, L.L.P.

20070072438 - Method of forming an oxide layer: A method for forming an oxide layer on a substrate. The method includes exposing a process gas containing H2, an oxygen-containing gas, and a halogen-containing oxidation accelerant gas to the substrate, where the process chamber is maintained at a subatmospheric pressure, and forming an oxide layer through thermal oxidization of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072439 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070065955 - Perpendicular magnetic recording medium, manufacturing method therefor, and magnetic read/write apparatus using the same: A perpendicular magnetic recording medium includes: a substrate; at least one underlayer formed above the substrate; and a perpendicular magnetic recording layer formed above the at least one underlayer, an easy magnetization axis of the perpendicular magnetic recording layer being oriented perpendicular to the substrate, the perpendicular magnetic recording layer... Agent: Sughrue Mion, PLLC

20070065956 - Contact probe, measuring pad used for the contact probe, and method of manufacturing the contact probe: There is provided a contact probe that is smaller than 50 μm in a pitch between a signal electrode and a ground electrode and can correctly conduct a high-speed high-frequency measurement, a measuring pad used for the contact probe, and a method of manufacturing the contact probe. The contact probe... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070065957 - Method for manufacturing semiconductor device: In the case of forming fine wires and the like by a droplet discharging apparatus to manufacture electric circuits, discharging controls including controls of a discharging position, a discharging timing, and the like are required to have very high accuracy. After forming design diagram data of an electric circuit by... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070065958 - Method for attaching an optical filter to an encapsulated package: A method for attaching an optical device to an encapsulated electronic package. The method may include aligning and attaching an optical device to a non-singulated encapsulated electronic package using an adhesive, and curing the entire package. The method may further include singulating the non-singulated encapsulated electronic package with the optical... Agent: Avago Technologies, Ltd.

20070065959 - Method for manufacturing light-emitting diode: A method for manufacturing a light-emitting diode is described, comprising the following steps. A substrate is provided. An illuminant epitaxial structure is formed on the substrate, wherein the illuminant epitaxial structure comprises a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer stacked on... Agent: Daniel B. Schein, Ph.d., Esq., Inc.

20070065960 - Method for producing a light emitting device: A production method for producing a light-emitting device 1 in which a light-emitting layer at least comprised of a n-type substrate bearing layer 3 and a p-type substrate bearing layer 4 is layered on a transparent crystal substrate 2 is provided with a step of forming a transfer layer 5... Agent: Greenblum & Bernstein, P.L.C

20070065961 - Method of manufacturing amorphous nio thin films and nonvolatile memory devices using the same: Example embodiments relate to a method of manufacturing amorphous NiO thin films and nonvolatile memory devices including amorphous thin films that use a resistance material. Other example embodiments relate to a method of manufacturing amorphous NiO thin films having improved switching and resistance characteristics by reducing a leakage current and... Agent: Harness, Dickey & Pierce, P.L.C

20070065962 - Manufacturing of optoelectronic devices: A method for manufacturing optoelectronic devices is disclosed. A layered structure may be formed with a plurality of layers including a bottom electrode layer, a top electrode layer, and one or more active layers between the top and bottom electrode layers. The layered structure is divided into one or more... Agent: Nanosolar, Inc.

20070065964 - Integrated passive devices: The specification describes a new composite IPD substrate material with properties that are compatible with highly integrated thin film structures. The new composite substrate is a laminate of a wafer of single crystal silicon and a wafer of an insulator. The composite is produced at the wafer level by bonding... Agent: Law Firm Of Peter V.d. Wilde

20070065965 - Manufacturing method and manufacturing apparatus for image display device: After sealing layers are formed on peripheral edge parts of a front substrate and a rear substrate, the front substrate and the rear substrate are disposed to be opposed to each other. Current paths are formed in the sealing layers, and power supply is begun. An electric current, which reaches... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070065963 - Method of manufacturing a micro-mechanical element: A method of manufacturing a micromechanical element wherein the method comprises the steps of providing a layer of base material, applying at least one at least partly sacrificial layer of an etchable material, patterning the at least partly sacrificial layer, to define at least a portion of the shape of... Agent: Cantor Colburn, LLP

20070065967 - Micromachined structures using collimated drie: A method of making an etch structure in a substrate involves the steps of providing a mask on a substrate with a pattern that leaves at least one opening leaving the substrate in direct contact with the ambient, performing an isotropic or quasi-isotropic etch through a mask to create a... Agent: Marks & Clerk

20070065966 - Process for single and multiple level metal-insulator-metal integration with a single mask: Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive... Agent: Greenblum & Bernstein, P.L.C

20070065968 - Fabrication of silicon microphone: A silicon microphone is formed using the steps of providing a first wafer including a layer of heavily doped silicon, a layer of silicon and an intermediate layer of oxide between the two silicon layers. The first wafer has a first major surface on one surface of the layer of... Agent: Jay S Cinamon Abelman Frayne & Schwab

20070065969 - Cmos image sensor and methods of manufacturing the same: An image sensor and methods of manufacturing the same are provided. An isolation layer of a CMOS image sensor including an active pixel region and a logic circuit region and methods of manufacturing the same are also provided. A method of manufacturing an image sensor having a unit pixel, which... Agent: Harness, Dickey & Pierce, P.L.C

20070065970 - Method of fabricating a storage gate pixel design: A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first charge storage region and between the first storage region and a floating diffusion region. A global shutter gate is formed to control the charge... Agent: Dickstein Shapiro LLP

20070065971 - Thin film transistor array substrate and fabricating method thereof: A thin film transistor array substrate structure includes a plurality of data lines; a plurality of gate lines intersecting the data lines to define pixel areas, the gate line being adjacent to at least two pixel areas; a plurality of common lines disposed between the at least two pixel areas;... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20070065972 - Image sensor and method of making same: An image sensor is formed by providing a semiconductor substrate having first, second and third pixel regions and first and second color filters disposed on their respective pixel regions. A photoresist layer is coated over the first and second color filters and the third color pixel region. The photoresist is... Agent: Mills & Onello LLP

20070065973 - Pre-patterned thin film capacitor and method for embedding same in a package substrate: An embedded passive structure, its method of formation, and its integration onto a substrate during fabrication are disclosed. In one embodiment, the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower... Agent: Intel/blakely

20070065977 - Low temperature methods for forming patterned electrically conductive thin films and patterned articles therefrom: A method of forming patterned thin films includes the steps of providing a porous membrane and a solution including a plurality of solid constituents and at least one surface stabilizing agent for preventing the solid constituents from flocculating out of suspension. The solution is dispensed onto a surface of the... Agent: Akerman Senterfitt

20070065976 - Method and apparatus for fabricating organic light emitting display device: A method and an apparatus for fabricating an organic light emitting display, in which a large-sized transmissible film is fabricated to be easily used in an affixing process for a large-sized substrate. The apparatus includes: a first chamber including a plurality of first through holes and having a first transmissible... Agent: Robert E. Bushnell

20070065974 - Method for producing a field effect semiconductor device: There is provided a method for producing a field effect semiconductor device, e.g., a field effect transistor 6 using carbon nanotubes in a channel layer 5, wherein the method includes the step of subjecting the carbon nanotubes to plasma treatment to change a physical or chemical state of the carbon... Agent: Sonnenschein Nath & Rosenthal LLP

20070065975 - Purification of carbon nanotubes based on the chemistry of fenton's reagent: The present invention is directed to methods of purifying carbon nanotubes (CNTs). In general, such methods comprise the following steps: (a) preparing an aqueous slurry of impure CNT material; (b) establishing a source of Fe2+ ions in the slurry to provide a catalytic slurry; (c) adding hydrogen peroxide to the... Agent: Ross Spencer Garsson Winstead Sechrest & Minick P.C.

20070065978 - Method for manufacturing micro-machined switch using pull-up type contact pad: The present invention relates to the manufacture of a semiconductor switch for use in a variety of communication systems, and particularly to the manufacture of a RF micro-machined switch of pull-up type, wherein an electrostatic electrode is used so as to cause the contact pad involved in the operation of... Agent: Darby & Darby P.C.

20070065980 - Method of manufacturing semiconductor chip: A insulation film removing tape 38 is pasted on a metal film 34 so as to cover an opening portion 32, then an insulation film 17 is formed so as to cover the side wall of a through hole 21 from the second major surface 11B side of the semiconductor... Agent: Drinker Biddle & Reath (dc)

20070065979 - Methods and systems for pack-size-oriented rounding: Methods and systems are provided for packing a required quantity of products, wherein a plurality of different packages for packing the products and a plurality of packaging specifications comprising rounding rules are provided. In one implementation, a method is provided comprising determining a packaging specification out of a plurality of... Agent: Sap / Finnegan, Henderson LLP

20070065981 - Semiconductor system-in-package: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070065982 - Controlling overspray coating in semiconductor devices: A manufacturing method, in which two device bars are bonded prior to facet coating to form a stacked bar pair. In one embodiment, each of the device bars has a p-side and an n-side, each side having a plurality of bonding pads, with at least some bonding pads located at... Agent: Mendelsohn & Associates, P.C.

20070065983 - Decoupling capacitor closely coupled with integrated circuit: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070065984 - Thermal enhanced package for block mold assembly: A heat spreader (20) is added to a package to enhance thermal and advantageously electrical performance. In manufacture, a heat spreader precursor (24) is advantageously placed over a group of dies and secured after bonding (e.g., wire or tape bonding or flip-chip bonding) and before matrix/block mold. For example, a... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070065985 - Bonding apparatus and method of bonding for a semiconductor chip: A method of bonding and a bonding apparatus for a semiconductor chip that apply ultrasonic vibration to the semiconductor chip to bond the semiconductor chip to a substrate carry out leveling effectively at low cost and in a short time and can improve the bonding between the semiconductor chip and... Agent: Staas & Halsey LLP

20070065986 - Method for manufacturing substrate with cavity: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second... Agent: Staas & Halsey LLP

20070065987 - Stacked mass storage flash memory package: A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent... Agent: Trask Britt, P.C./ Micron Technology

20070065988 - Method for manufacturing substrate with cavity: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit patter on both sides of a seed layer by use of a first dry film, the seed layer being for forming a circuit pattern on both sides; (b) laminating a second... Agent: Staas & Halsey LLP

20070065989 - Method for manufacturing an adhesive substrate with a die-cavity sidewall: A method for manufacturing an adhesive substrate with a die-cavity sidewall is disclosed. A region for forming die-cavity sidewall is defined on one surface of the substrate. The substrate is laminated with a sacrificial film, a partially cured resin is formed between the substrate and the sacrificial film. And then,... Agent: Troxell Law Office PLLC

20070065990 - Recursive spacer defined patterning: A method for the patterning of a plurality of fins in a MugFET device is provided. The method involves depositing at least one temporary pattern using photolithography. Further processing steps include a combination of depositing a conformal layer and spacer defined patterning of the conformal layer such that a very... Agent: Knobbe Martens Olson & Bear LLP

20070065993 - Fabricating method for flexible thin film transistor array substrate: A method of fabricating a flexible thin film transistor array substrate is provided. First, a rigid substrate is provided, and a polymer material layer is coated on the rigid substrate. Then, an insulating layer is coated over the polymer material layer by a spin coating process. The insulating layer covers... Agent: Jianq Chyun Intellectual Property Office

20070065992 - Higher selectivity, method for passivating short circuit current paths in semiconductor devices: Certain modifications and additions to the prior art short passivation technique have lead to improvements in the low light voltage of solar cells which are made using the improved passivation technique. Examples of the modifications include: 1) reducing the voltage bias on the cell while increasing the time of application... Agent: Energy Conversion Devices, Inc.

20070065996 - Method for manufacturing a semiconductor device: It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device with preferable yield. In the invention, two-step etching is performed when selectively removing an interlayer insulating film with at least two layers constituting a semiconductor device, and forming an opening. One... Agent: Eric Robinson

20070065994 - Passivation structure for ferroelectric thin-film devices: Ferroelectric thin film devices including a passivation structure to reduce or control a leakage path between two electrodes and along an interface between a ferroelectric thin film layer and a passivation layer are described. Methods for fabricating such devices are also disclosed. The passivation structure includes a first passivation layer... Agent: Fenwick & West LLP

20070065995 - Semiconductor device and method of manufacturing the same: There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a... Agent: Eric Robinson

20070065991 - Thin film transistor array panel and method of manufacturing the same: The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention... Agent: Macpherson Kwok Chen & Heid LLP

20070065997 - Fabricating method of an active-matrix organic electroluminescent display panel: A method for fabricating an active-matrix organic electroluminescent (OEL) display panel is described. A transparent conductive layer is formed on a substrate as a common anode for all organic light emitting diodes (OLED), and a passivation layer is formed on the transparent conductive layer. Thin film transistors are formed on... Agent: Jianq Chyun Intellectual Property Office

20070065998 - Polysilicon thin film fabrication method: A polysilicon thin film fabrication method is provided, in which a heat-absorbing layer is used to provide sufficient heat for grain growth of an amorphous silicon thin film, and an insulating layer is used to isolate the heat-absorbing layer and the amorphous silicon thin film. A regular heat-conducting layer is... Agent: Rosenberg, Klein & Lee

20070065999 - Method for manufacturing semiconductor memory device using asymmetric junction ion implantation: A method for manufacturing a semiconductor memory device using asymmetric junction ion implantation, including performing ion implantation for adjusting a threshold voltage to a semiconductor substrate, forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region, implanting a first... Agent: Marshall, Gerstein & Borun LLP

20070066000 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device including an elevated source/drain structure that can suppress emergence of a junction leak current. The method includes forming a trench on a predetermined position on a surface of a semiconductor substrate, forming an isolation layer so as to fill the trench, and so... Agent: Young & Thompson

20070066001 - Semiconductor device and manufacturing method thereof: The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first semiconductor element device including a pair of first diffusion layers formed in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070066002 - Source capacitor enhancement for improved dynamic ir drop prevention: An implant is added at the interface between the source region of an MOS transistor and the well material to improve dynamic IR drop performance. The additional implant raises the underlying capacitance of the source region. This, in turn, provides for an increase in charge storage which, in turn, provides... Agent: Stallman & Pollock LLP

20070066003 - Methods of forming non-volatile memory devices having trenches: A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the... Agent: Myers Bigel Sibley & Sajovec

20070066004 - Semiconductor device and its manufacture method: A non-volatile semiconductor memory device which simultaneously possesses a non-volatile memory cell region which possesses an isolating insulation film which has been formed selectively within a semiconductor substrate, which also possesses a first electroconductive film (floating gate electrode) via a first gate insulating film which has been formed on the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070066005 - Semiconductor device and method of fabricating the same: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070066006 - Method and structure for electrostatic discharge protection of photomasks: A mask for manufacturing integrated circuits and use of the mask. The mask has a mask substrate. The mask also has an active mask region within a first po