Semiconductor device manufacturing: process inventions 03/07

20070072312 - Interconnect connecting a diffusion metal layer and a power plane metal and fabricating method thereof: A giant magnetoresistance (GMR) pad on the same level of GMR memory bit layer is used as an intermediate connection for plugs between the GMR pad and an underlying diffusion metal layer. A single large power metal plug is used to connect the GMR pad and the overlying power plane... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070072311 - Interconnect for a gmr stack layer and an underlying conducting layer: Metal plugs located in a planar dielectric layer, under a GMR stack layer, are used to connect the nonmagnetic conducting layer of the GMR stack layer and a conducting layer under the planar dielectric layer.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070072310 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising a semiconductor substrate and memory cells. Each memory cell comprises a switching transistor and a ferroelectric capacitor, both formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film held between the lower and upper electrodes. A first wire... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072313 - Anisotropic conductive connector and circuit device inspection method: It is an object to provide an anisotropically conductive connector having an excellent repetitive use durability and a method of inspecting a circuit device having a high inspection efficiency which are used in the inspection of the circuit device such as a semiconductor integrated circuit having a solder projected electrode.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072315 - Method and system for reliability similarity of semiconductor devices: A method and system for reliability similarity of semiconductor devices. The method includes providing a first plurality of semiconductor devices, providing a second plurality of semiconductor devices, and determining a first reliability associated with the first plurality of semiconductor devices. The first reliability is represented by at least a first... Agent: Townsend And Townsend And Crew, LLP

20070072317 - Method for predicting contributions of silicon interstitials to n-type dopant transient enhanced diffusion during a pn junction formation: A method for predicting the contribution of silicon interstitials to n-type dopant transient enhanced diffusion during a pn junction formation is disclosed. Initially, fundamental data for a set of microscopic processes that can occur during one or more material processing operations are obtained. The fundamental data are then utilized to... Agent: Dillon & Yudell LLP

20070072318 - Method for predicting the formation of silicon nanocrystals in embedded oxide matrices: A method for predicting the formation of silicon nanocrystals in an oxide matrix is disclosed. Initially, fundamental data for a set of microscopic processes that can occur during one or more material processing operations are obtained. Kinetic models are then built by utilizing the fundamental data for a set of... Agent: Dillon & Yudell LLP

20070072314 - Method of preparing an integrated circuit die for imaging: Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be removed, especially if they are formed from the same metal as the metal lines, as in copper damascene... Agent: Ogilvy Renault LLP

20070072316 - Wiring pattern determination method and computer program product thereof: A wiring pattern determination method and a computer program thereof comprise a step of moving positions of tentatively designed plated leads on an edge of a semiconductor package to the positions that can be accommodated in positionable windows nearest to the respective tentatively designed plated lead positions, in a template... Agent: Chadbourne & Parke, L.L.P.

20070072319 - Integrated circuit capacitor structure: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first... Agent: Marger Johnson & Mccollom, P.C.

20070072320 - Process for producing an epitalixal layer of galium nitride: A method of manufacturing a low defect density GaN material comprising at least two step of growing epitaxial layers of GaN with differences in growing conditions, (a.) a first step of growing an epitaxial layer GaN on an epitaxially compentent layer under first growing conditions selected to induce island features... Agent: Blakely Sokoloff Taylor & Zafman

20070072321 - Device package and methods for the fabrication and testing thereof: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second... Agent: Rohm And Haas Electronic Materials LLC

20070072322 - Methods for patterning films, fabricating organic electroluminescence display and fabricating thin film transistor array substrate: A method for fabricating a thin film transistor array substrate is provided. Wherein, a plurality of contact holes and recesses are formed in a protection layer disposed upon thin film transistors. Each recess comprises an under-cut profile while each contact hole exposes a drain-metal layer of a corresponding thin film... Agent: Jianq Chyun Intellectual Property Office

20070072323 - Method of manufacturing display panel for flexible display device: A liquid crystal display panel manufacturing method includes forming at least one thin film on a flexible plastic substrate by sputtering at a temperature of about 80° C. to about 150° C. Sputtering can be in a chamber evacuated to about 1×10−6 Torr to about 9×10−6 Torr. Sputtering targets and... Agent: Macpherson Kwok Chen & Heid LLP

20070072324 - Substrate for growing a iii-v light emitting device: A substrate including a host and a seed layer bonded to the host is provided, then a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. In some embodiments, a bonding layer bonds the host to the... Agent: Patent Law Group LLP

20070072326 - Photodiode for multiple wavelength operation: A method of a fabricating a multiple wavelength adapted photodiode and resulting photodiode includes the steps of providing a substrate having a first semiconductor type surface region on at least a portion thereof, implanting and forming a second semiconductor type shallow surface layer into the surface region, and forming a... Agent: Akerman Senterfitt

20070072325 - Self-aligned photodiode for cmos image sensor and method of making: A method for forming a photodiode that is self-aligned to a transfer gate while being compatible with a metal silicide process is disclosed. The method comprises forming a gate stack of gate oxide, polysilicon, and a sacrificial/disposable cap insulator over the polysilicon. The insulator may be a combination of silicon... Agent: Perkins Coie LLP

20070072329 - Method and apparatus for manufacturing a display apparatus: A light-shielding layer is formed and patterned on a front substrate that is opposed to a back substrate and on which a number of electron-emitting elements are arranged. A phosphor layer is formed and patterned on the part on which the light-shielding layer is not provided. A metal back layer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072328 - Method and system for hermetically sealing packages for optics: A system for hermetically sealing devices. The system includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of... Agent: Townsend And Townsend And Crew, LLP

20070072327 - Method of forming an integrated mems resonator: A method of producing an integrated MEMS resonator includes providing a substrate including single crystal silicon and partially forming a resonator in a first portion of the substrate, the resonator having a resonating element formed by the substrate and an electrode, the resonating element and the electrode forming a variable... Agent: Bromberg & Sunstein LLP

20070072331 - Method for manufacturing a micro-electro-mechanical device: A technique for manufacturing a micro-electro-mechanical (MEM) device includes a number of steps. Initially, a first wafer is provided. Next, a bonding layer is formed on a first surface of the first wafer. Then, a portion of the bonding layer is removed to provide a cavity including a plurality of... Agent: Delphi Technologies, Inc.

20070072330 - Wafer bonding compatible with bulk micro-machining: A method for forming a microstructure is disclosed in which, after a polymer substance has been applied to a first substrate, the first substrate is micromachined to remove at least one portion of the first substrate. A second substrate is then adhered to the first substrate via the polymer substance.... Agent: Wolf Greenfield & Sacks, PC

20070072332 - Semiconductor radiation detectors and method for fabrication thereof: The invention relates to a method for fabricating semiconductor radiation detectors comprising a bulk of a first conductivity type for detecting radiation with further semiconductor layers of a second and a first conductivity type patterned thereon, at least one of the further semiconductor layers being deposited by epitaxy. The invention... Agent: Jeffrey S. Habib, Esq. Hooker & Habib, P.C.

20070072333 - Reduced barrier photodiode / gate device structure for high efficiency charge transfer and reduced lag and method of formation: A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is... Agent: Dickstein Shapiro LLP

20070072334 - Semiconductor fabrication process employing spacer defined vias: A semiconductor fabrication process includes forming a first etch mask (131) that defines a first opening (132) and a second etch mask (140) that defines a second opening (142) overlying an interlevel dielectric (ILD) (108). The ILD (108) is etched to form a first via (154) defined by the first... Agent: Freescale Semiconductor, Inc. Law Department

20070072336 - Method of manufacturing nano size-gap electrode device: Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed... Agent: Ladas & Parry LLP

20070072337 - Method of manufacturing the organic electroluminescent display and organic electroluminescent display manufactured by the method: The present invention provides an organic EL display panel manufacturing method which is capable of forming a desired organic film or the like with high accuracy without imparting damages to a substrate and an organic film and an organic EL display panel which is manufactured by the method. An opening... Agent: Stanley P. Fisher Reed Smith LLP

20070072335 - Semiconductor devices having nano-line channels and methods of fabricating the same: A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line... Agent: Myers Bigel Sibley & Sajovec

20070072340 - Electronic device with inductor and integrated componentry: Semiconductor devices and methods for their assembly are described in which inductor elements and additional passive or active circuit components may be combined in novel configurations. An electronic device and associated methods provide an inductor element encapsulated within a dielectric package, the inductor package having a plurality of electrical contacts... Agent: Sam Tung Texas Instruments Incorporated

20070072338 - Method for separating package of wlp: The present invention provides a semiconductor device package singulation method. The method comprises printing a photo epoxy layer on the back surface of a substrate of a wafer for marking the scribe lines to be diced. Then etching is performed through the substrate along the marks in the photo epoxy... Agent: Kusner & Jaffe Highland Place Suite 310

20070072339 - Process for fabricating chip package structure: A process for fabricating a chip package structure is disclosed. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier... Agent: Jianq Chyun Intellectual Property Office

20070072341 - Die package and method for making the same: The present invention relates to a die package and method for making the same. The method of the invention comprises the steps of: (a) providing a plate, having a first surface and a second surface; (b) forming a plurality of first dice on the plate, the first dice having a... Agent: Volentine Francos, & Whitt PLLC

20070072342 - Depopulation of a ball grid array to allow via placement: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path... Agent: Blakely Sokoloff Taylor & Zafman

20070072343 - Semiconductor constructions comprising multi-level patterns of radiation-imageable material: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with... Agent: Wells St. John P.s.

20070072344 - Gel package structural enhancement of compression system board connections: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by... Agent: Lynn L. Augspurger IBM Corporation

20070072345 - Semiconductor device and method for manufacturing the same: A method of manufacturing a semiconductor device is disclosed, which includes at least the steps of preparing a laminated structure including a single chip or a plurality of chips, and dividing the laminated structure into a plurality of sub-laminated structures. A laminated structure comprised of a silicon substrate and a... Agent: GlobalIPCounselors, LLP

20070072347 - Method of assembly for multi-flip chip on lead frame on overmolded ic package: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller... Agent: Hiscock & Barclay, LLP

20070072346 - Method of resin-seal-molding electronic component and apparatus therefor: A mold for resin-seal-molding an electronic component is constituted by a first mold and a second mold. At a mold face (PL face) of the molds, a substrate supply-set surface having a flat shape without a step is provided. A pot block is joined with and separated from a side... Agent: Birch Stewart Kolasch & Birch

20070072349 - Manufacturing method of a display device: The present invention provides a manufacturing method of a display device which can decrease the lowering of a yield rate of the display device attributed to the aggregations generated by pseudo single crystallization of a silicon film. A manufacturing method of a display device includes a semiconductor film reforming step... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070072348 - Method of manufacturing an amoled: The present invention relating to a method of manufacturing an AMOLED panel. The method comprises providing a substrate, forming a TFT on the substrate, forming an inter-layer insulator layer, forming a plurality of via holes, forming a metal layer which electrically contacts a source and a drain, forming a transparent... Agent: North America Intellectual Property Corporation

20070072350 - Method of manufacturing semiconductor device: In a step of doping a silicon-based semiconductor film as a TFT active layer such as channel doping or the like, a protective film is formed by a CVD method as a pretreatment so as to prevent the silicon-based semiconductor film from being contaminated and etched. However, in the case... Agent: Eric Robinson

20070072351 - Method of fabricating semiconductor device: An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072352 - Insulated gate field effect transistor and manufacturing method thereof: A separation hole is provided in the center of the gate electrode. Accordingly, it is possible to suppress a drastic increase in feedback capacitance Crss in the case where drain-source voltage VDS is decreased and the width of the depletion layer is narrowed. Thus, high-frequency switching characteristics are improved. Moreover,... Agent: Morrison & Foerster LLP

20070072353 - Method of fabricating strained-silicon transistors and strained-silicon cmos transistors: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process... Agent: North America Intellectual Property Corporation

20070072354 - Structures with planar strained layers: A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar,... Agent: Goodwin Procter LLP Patent Administrator

20070072355 - Method of manufacturing semiconductor device: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070072356 - Method for reducing positive charges accumulated on chips during ion implantation: In the plasma etching process of the integrated circuit, a portion of the charges from the plasma accumulates on the semiconductor device through the conductive portion of the integrated circuit so as to damage the device. The phenomenon mentioned above is so called antenna effect. In order to decreased the... Agent: Jianq Chyun Intellectual Property Office

20070072357 - Method of manufacturing devices having vertical junction edge: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and... Agent: Michael G. Fletcher Fletcher Yoder

20070072358 - Method of manufacturing metal-oxide-semiconductor transistor devices: A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed. In the method, a silicon nitride spacer is formed and will be removed after an ion implantation process to form a source/drain region and a salicide process to form a metal silicide layer on the surface of the source/drain region... Agent: North America Intellectual Property Corporation

20070072359 - Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the... Agent: Rossi, Kimms & Mcdowell LLP.

20070072360 - Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance: A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias,... Agent: Patent Dept., Sandisk 3d LLC(matrix)

20070072361 - Method of reducing current leakage in a metal insulator metal semiconductor capacitor and semiconductor capacitor thereof: A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top... Agent: North America Intellectual Property Corporation

20070072362 - Solid electrolytic capacitor, fabrication method thereof, and coupling agent utilizing in the same: A solid electrolytic capacitor, fabrication method, and coupling agent utilized in the same. The capacitor includes a valve metal layer, an oxide dielectric layer on at least a part of the surface of the valve metal layer, a coupling layer having a molecular chain with a first end bonding to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070072363 - Method for fabricating transistor gate structures and gate dielectrics thereof: Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may... Agent: Texas Instruments Incorporated

20070072364 - Method for fabricating transistor gate structures and gate dielectrics thereof: Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may... Agent: Texas Instruments Incorporated

20070072368 - Method of cleaning semiconductor surfaces: Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include cleaning using a supercritical fluid. Advantages include a combination of both chemical and mechanical removal abilities from the supercritical fluid. Mechanical energy for cleaning is... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070072367 - Method of manufacturing semiconductor silicon substrate: The present invention provides a method of manufacturing a semiconductor silicon substrate provided with a capacitor structure having a capacitor hole, the capacitor hole having a depth of equal to or greater than 3 μm and an aspect ratio equal to or greater than 30, the method including at least:... Agent: Mcdermott Will & Emery LLP

20070072365 - Methods of forming a recessed gate: A method of forming a recessed gate may include forming a gate recess including an upper recess and a lower recess at an upper portion of a semiconductor substrate, the lower recess may have a width substantially wider than that of the upper recess, forming a gate insulation layer on... Agent: Lee & Morse, P.C.

20070072366 - Transistor structure for semiconductor device and method of fabricating the same: A transistor for a semiconductor device may include a lower semiconductor layer, an active pattern, including a groove region, on the lower semiconductor layer, a gate pattern at least partially overlapping the active pattern including the groove region, and a gate insulating layer interposed between the active pattern and the... Agent: Lee & Morse, P.C.

20070072373 - Fabrication method of an non-volatile memory: A non-volatile memory cell is provided. The non-volatile memory includes a substrate, a gate stacked layer, an isolation layer and a conductive layer. The gate stacked layer includes a tunneling layer, a charge trapping layer, a barrier layer and a control gate layer sequentially stacked over the substrate, and the... Agent: Jianq Chyun Intellectual Property Office

20070072372 - Method for forming metal line in flash memory device: A method for forming a metal line in a flash memory device includes sequentially forming a first inter-layer insulation layer, an etch stop layer, a second inter-layer insulation layer, and a hard mask layer over a substrate where a contact plug is formed, etching the hard mask layer to form... Agent: Blakely Sokoloff Taylor & Zafman

20070072369 - Non-volatile memory and fabricating method thereof: A non-volatile memory includes a substrate, a plurality of isolation layers, a plurality of active layers, a plurality of floating gates, a plurality of control gates and a plurality of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the... Agent: Jianq Chyun Intellectual Property Office

20070072370 - Non-volatile memory and fabricating method thereof: A method for fabricating a non-volatile memory is described. A substrate having isolation structures is provided. These isolation structures protrude from the substrate, and a first mask layer is formed on the substrate between the isolation structures. A second mask layer is formed on the substrate. The second and the... Agent: Jianq Chyun Intellectual Property Office

20070072371 - Semiconductor device and method for fabricating the same: A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to... Agent: Mcdermott Will & Emery LLP

20070072374 - Semiconductor device: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072375 - Method for manufacturing semiconductor device: a method for manufacturing a semiconductor device comprises the steps of forming a gate trench in a semiconductor substrate, forming a gate insulation film in an inner wall of the gate trench, filling a gate electrode material into at least an inside of the gate trench, forming a gate electrode... Agent: Mcdermott Will & Emery LLP

20070072376 - Strained-induced mobility enhancement nano-device structure and integrated process architecture for cmos technologies: A CMOS semiconductor integrated circuit device. The CMOS device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within... Agent: Townsend And Townsend And Crew, LLP

20070072377 - Process of making a iii-v compound semiconductor heterostructure mosfet: A method of forming a compound semiconductor device comprises forming a gate insulator layer overlying a compound semiconductor substrate, defining an active device region within the compound semiconductor substrate, forming ohmic contacts to the compound semiconductor substrate proximate opposite sides of the active device region, and forming a gate metal... Agent: Freescale Semiconductor, Inc. Law Department

20070072378 - Method of manufacturing metal-oxide-semiconductor transistor devices: A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed. In the method, a silicon nitride spacer is formed and will be removed after an ion implantation process used to form a source/drain region and a salicide process used to form a metal silicide layer on the surface of the... Agent: North America Intellectual Property Corporation

20070072379 - Mos transistor and manufacturing method thereof: Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, and a silicon carbide layer is deposited... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070072381 - Method for fabricating a semiconductor device including the use of a compound containing silicon and nitrogen to form an insulation film of sin, sicn or siocn: The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070072380 - Methods for fabrication of a stressed mos device: Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed overlying the monocrystalline semiconductor substrate. The substrate is... Agent: Ingrassia Fisher & Lorenz, P.C.

20070072382 - Method of manufacturing semiconductor device: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070072383 - Phosphorus activated nmos using sic process: A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure... Agent: Texas Instruments Incorporated

20070072384 - Plastically deformable irreversible storage medium and method of producing one such medium: The storage medium comprises an array of memory cells (3) which can be addressed by first (1) and second (2) conductors. Each memory cell (3) comprises one zone (10) of an active layer (8) which is initially electrically insulating and which can be made electrically conductive by means of localised... Agent: Oliff & Berridge, PLC

20070072385 - Electrical open/short contact alignment structure for active region vs. gate region: An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070072386 - Method of forming an alignment key having a capping layer and method of fabricating a semiconductor device using the same: A method of forming an alignment key with a capping layer in a semiconductor device without an additional mask formation process, and a method of fabricating a semiconductor device using the same, may be provided. The method of forming an alignment key may include forming an isolation layer confining an... Agent: Harness, Dickey & Pierce, P.L.C

20070072388 - Bottle-shaped trench and method of fabricating the same: Fabrication of a bottle-shaped trench is disclosed. A semiconductor substrate with a trench therein is provided. An ion-doped barrier layer is formed in the trench, exposing the upper portion surfaces of the sidewall of the trench. An ion implantation is performed on the upper portion surfaces of the sidewall of... Agent: Birch Stewart Kolasch & Birch

20070072387 - Method of fabricating shallow trench isolation structure: A method of fabricating a shallow trench isolation structure is provided. A substrate having a patterned pad layer is provided. A part of the substrate is removed by using the patterned pad layer as a mask and a trench is thus formed in the substrate. A first insulation layer is... Agent: Jianq Chyun Intellectual Property Office

20070072389 - Method for fabricating semiconductor device having taper type trench: A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070072390 - Techniques for removal of photolithographic films: Techniques for removal of photolithographic films used in the manufacture of semiconductor devices are provided. A substrate support member of a first processing chamber includes at least three retractable pins capable of elevating a wafer from a surface of the substrate support member. In addition, the first processing chamber is... Agent: Townsend And Townsend And Crew, LLP

20070072392 - Method of cleaning cover glass having spacer: The present invention provides a method of cleaning a cover glass having a spacer which is to be incorporated in a solid image pickup device, comprising: a dry cleaning step performed after dry etching; a wipe-off cleaning step performed after the dry cleaning step; a primary wet cleaning step performed... Agent: Sughrue Mion, PLLC

20070072391 - Method of sealing two plates with the formation of an ohmic contact therebetween: e

20070072393 - Method for preparing and assembling substrates: A method for assembling a first and a second wafer of material, including routing at least the first wafer and assembling the first and second wafer.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072394 - Semiconductor device manufacturing apparatus, semiconductor device manufacturing method and semiconductor device: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072395 - Substrate and method of separating components from a substrate: A substrate (1) having a first groove (4) is provided with a plurality of protrusions (3) on the first groove (4). These protrusions (4) can have a top with an apex angle of 30 to 150 degrees and results in a controlled breaking of the substrate (1) and a minimum... Agent: Philips Intellectual Property & Standards

20070072398 - Method for manufacturing semiconductor device and epitaxial growth equipment: A method for manufacturing a semiconductor device includes steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the main surface and in the trench; and forming a second epitaxial film on the first epitaxial film. The step of forming the... Agent: Posz Law Group, PLC

20070072396 - Method of producing self supporting substrates comprising iii-nitrides by means of heteroepitaxy on a sacrificial layer: The invention relates to a method for the production of self-supporting substrates comprising element III nitrides. More specifically, the invention relates to a method of producing a self-supporting substrate comprising a III-nitride, in particular, gallium nitride (GaN), which is obtained by means of epitaxy using a starting substrate. The invention... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20070072397 - Semiconductor device, method for manufacturing the same and method for evaluating the same: A method for manufacturing a semiconductor device includes steps of: forming a first epitaxial film on a silicon substrate; forming a trench in the first epitaxial film; and forming a second epitaxial film on the first epitaxial film and in the trench. The step of forming the second epitaxial film... Agent: Posz Law Group, PLC

20070072399 - Semiconductor devices having epitaxial layers with suppressed lateral growth and related methods of manufacturing such devices: Semiconductor devices are provided having a selective epitaxial growth layer that exhibits suppressed lateral growth. These semiconductor devices may include a semiconductor substrate having a silicon region, and an epitaxial growth layer formed on the silicon region. The epitaxial growth layer may comprise alternatively stacked silicon and silicon germanium epitaxial... Agent: Myers Bigel Sibley & Sajovec

20070072400 - Apparatus and methods for thermally processing undoped and lightly doped substrates without pre-heating: Apparatus for and methods of thermally processing undoped or lightly doped semiconductor wafers (30) that typically are not very absorptive of an annealing radiation beam (14) are disclosed. The apparatus (10) uses a relatively low power activating radiation beam (240) with a photon energy greater than the bandgap energy of... Agent: Allston L. Jones Peters, Verny, Jones, Schmitt & Aston L.L.P.

20070072401 - Method for purifying a metal carbonyl precursor: A method of purifying a metal carbonyl precursor in a metal precursor vaporization system where the metal carbonyl precursor comprises a metal particulate impurity. The method includes flowing a CO-containing gas through the metal precursor vaporization system to a precursor collection system in fluid communication with the metal precursor vaporization... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070072402 - Method of fabricating semiconductor devices and method of removing a spacer: A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on... Agent: North America Intellectual Property Corporation

20070072403 - Semiconductor device and method for fabricating the same: A method for fabricating a semiconductor device includes the steps of forming a high-k layer insulating layer on a SOI substrate; forming a gate electrode layer on the high-k insulating layer; forming a resist layer on the gate electrode layer; removing selectively the gate electrode layer using the resist layer... Agent: Rabin & Berdo, PC

20070072404 - Phase-change optical disk: A phase-change optical disk includes a layer structure including a ZnS—SiO2 first dielectric layer, an oxynitride second dielectric layer including SiHfON, a ZnS—SiO2 third dielectric layer, a GeN interface layer, a Ge2Sb2Te5 recording layer, a GeN interface layer, a ZnS—SiO2 dielectric layer, and a reflective layer, which are consecutively deposited... Agent: Foley And Lardner LLP Suite 500

20070072405 - Semiconductor device and method for manufacturing the same: There is provided a semiconductor device in which the junction strength of land portions and external terminals is increased, the disconnection of the external terminal is surely prevented, and the connection reliability is ensured over an extended period of time. An insulating resin layer which insulates metal wires from one... Agent: Stevens, Davis, Miller & Mosher, LLP

20070072408 - Fabrication method of semiconductor integrated circuit device: The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves,... Agent: Miles & Stockbridge PC

20070072407 - Method of fabricating self-aligned contact pad using chemical mechanical polishing process: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping... Agent: F. Chau & Associates, LLC

20070072406 - Methods of forming integrated circuit devices having metal interconnect structures therein: Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first... Agent: Myers Bigel Sibley & Sajovec

20070072410 - Method of forming copper interconnection using dual damascene process: Disclosed is a method of forming a copper interconnection using a dual damascene process. The method generally prevents formation of an undeveloped photoresist caused by the topology between a via hole and a trench and reduces or prevents defects in the copper interconnection, such as disconnection, via holes or voids.... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070072409 - Reflector with non-uniform metal oxide layer surface: A reflector includes a non-uniform metal oxide layer surface.... Agent: Hewlett Packard Company

20070072411 - Method for forming metal line in semiconductor device: A method for forming a metal line in a semiconductor device includes forming a plug buried in an inter-layer insulation layer formed over a substrate, forming a metal line layer over the plug and the substrate, forming a contact mask over the metal line layer, etching first portions of the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070072412 - Preventing damage to interlevel dielectric: Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of the opening. The re-sputtered... Agent: Hoffman, Warnick & D'alessandro LLC

20070072413 - Methods of forming copper interconnect structures on semiconductor substrates: Methods of forming copper interconnect structures according to embodiments of the present invention include forming an electrically insulating layer having a recess therein on a semiconductor substrate and then forming a layer of copper having a thickness greater than about 3000 Å on an upper surface of the electrically insulating... Agent: Myers Bigel Sibley & Sajovec

20070072414 - Method for controlling the step coverage of a ruthenium layer on a patterned substrate: A method for forming a Ru layer for an integrated circuit by providing a patterned substrate in a process chamber, and exposing the substrate to a process gas comprising a ruthenium carbonyl precursor and a CO gas to form a Ru layer over a feature of the patterned substrate. In... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070072415 - Method for integrating a ruthenium layer with bulk copper in copper metallization: A method for integrating a Ru layer with bulk Cu in semiconductor manufacturing. The method includes depositing a Ru layer onto a substrate in a chemical vapor deposition process, modifying the deposited Ru layer by oxidation, or nitridation, or a combination thereof, depositing an ultra thin Cu layer onto the... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070072416 - Method of forming a low resistance semiconductor contact and structure therefor: In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070072417 - Method for forming wiring structure, wiring structure, method for forming semiconductor device, and display device: A method for forming a wiring structure includes forming a metal layer on a substrate, and annealing the metal layer by irradiating the metal layer with light emitted from at least one flash tube, thereby growing crystalline grains of the metal layer.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072418 - Method of forming tungsten silicide layer and method of fabricating semiconductor element using same: A method of forming a tungsten silicide layer and a related method of fabricating a semiconductor element. The method of forming the tungsten silicide layer includes forming a pre-coating layer within a CVD process chamber by injecting a tungsten source gas (A) and a silicon source gas (B) at a... Agent: Volentine Francos, & Whitt PLLC

20070072419 - Chip, ship stack, and method of manufacturing the same: Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in... Agent: Blakely Sokoloff Taylor & Zafman

20070072420 - Method of forming copper interconnection using dual damascene process and semiconductor device having copper interconnection according to the same: Disclosed is a method of forming a copper interconnection using a dual damascene process, in which an etch profile anomaly and the trench depth variation caused by the trench etching process are reduced or prevented, so that the copper interconnection is obtained substantially without voids or interconnection defects. The method... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070072422 - Hydrogen treatment to improve photoresist adhesion and rework consistency: A process for selectively removing photoresist, organic overlayers, and/or polymers/residues from a substrate without altering the surface chemistry and adhesion properties of the underlying substrate layers is provided. Generally, the process includes pretreating the substrate with hydrogen (e.g., by way of a hydrogen-based plasma) prior to deposition of a photoresist... Agent: Townsend And Townsend And Crew LLP / Amat

20070072421 - Method to passivate defects in integrated circuits: Defects in an integrated circuit are electrically passivated. A hydrogen diffusion blocking film is placed on the integrated circuit. Atomic hydrogen is implanted through the hydrogen diffusion blocking film. The integrated circuit is annealed so that the implanted atomic hydrogen diffuses towards locations where the defects are concentrated.... Agent: Avago Technologies, Ltd.

20070072423 - Unpolished semiconductor wafer and method for producing an unpolished semiconductor wafer: Unpolished semiconductor wafers are produced by: (a) pulling a single crystal of a semiconductor material, (b) grinding the single crystal round, (c) separating a semiconductor wafer from this crystal, (d) rounding the edge of the semiconductor wafer, (e) surface-grinding at least one side of the semiconductor wafer, (f) treating the... Agent: Brooks Kushman P.C.

20070072424 - Method of manufacturing silicon rich oxide (sro) and semiconductor device employing sro: Provided are methods for manufacturing silicon rich oxide (SRO) layers useful in the fabrication of semiconductor devices, for example, non-volatile memory devices, and methods for fabricating semiconductor devices incorporating such SRO layers. The methods include absorbing a first silicon source gas onto the substrate, oxidizing the first absorbed layer to... Agent: Harness, Dickey & Pierce, P.L.C

20070072426 - Chemical mechanical polishing process and apparatus therefor: A CMP process and a CMP apparatus therefor are provided. First, a substrate including a semiconductor structure, a liner layer over the semiconductor structure and a metal layer over the liner layer is provided. Next, a metal polishing step is performed to polish the metal layer until a portion of... Agent: Jianq Chyun Intellectual Property Office

20070072427 - Method for fabricating semiconductor device and polishing method: A method for fabricating a semiconductor device includes forming a copper film above a surface of a substrate, forming on a polishing pad a material which contains copper, wherein said copper does not derive from said copper film, and after having formed the copper-containing material on said polishing pad, polishing... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070072425 - Substrate and method for producing same: A substrate according to the present invention includes a metal plate, and an insulating film, which is provided on the surface of the metal plate and which includes needle alumina particles and granular particles. The substrate of the present invention has excellent insulating property and can be manufactured on an... Agent: Nixon Peabody, LLP

20070072428 - Method for manufacturing a micro-electro-mechanical structure: A technique for manufacturing a micro-electro-mechanical (MEM) structure includes a number of steps. Initially, a substrate is provided. Next, a plurality of trenches are etched into the substrate with a first etch. Then, a charging layer is formed at a bottom of each of the trenches to form undercut trenches.... Agent: Delphi Technologies, Inc.

20070072429 - Pattern enhancement by crystallographic etching: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to... Agent: Scully Scott Murphy & Presser, PC

20070072431 - Method for cleaning substrate having exposed silicon and silicon germanium layers and related method for fabricating semiconductor device: A method for cleaning a substrate on which a silicon layer and a silicon germanium layer are formed and exposed, and method for fabricating a semiconductor device using the cleaning method are disclosed. The cleaning method comprises preparing a semiconductor substrate on which a silicon layer and a silicon germanium... Agent: Volentine Francos, & Whitt PLLC

20070072430 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includes the steps... Agent: Cooper & Dunham, LLP

20070072433 - Apparatus for the removal of a fluorinated polymer from a substrate and methods therefor: An apparatus generating a plasma for removing fluorinated polymer from a substrate is disclosed. The embodiment includes a powered electrode assembly, including a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The embodiment also includes a grounded... Agent: Ipsg, P.C.

20070072432 - Apparatus for the removal of a metal oxide from a substrate and methods therefor: An apparatus generating a plasma for removing metal oxide from a substrate is disclosed. The embodiment includes a powered electrode assembly, including a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The embodiment also includes a grounded... Agent: Ipsg, P.C.

20070072434 - Method and system for operating a physical vapor deposition process: A method for fabricating semiconductor wafers using physical vapor deposition. The method includes maintaining a substrate on a susceptor in a chamber. The substrate has a face positioned within a vicinity of a target material, which is within the chamber. The target member comprises a first side and a second... Agent: Townsend And Townsend And Crew, LLP

20070072435 - Method for plasma etching a chromium layer through a carbon hard mask suitable for photomask fabrication: Methods for etching chromium and forming a photomask using a carbon hard mask are provided. In one embodiment, a method of a chromium layer includes providing a substrate in a processing chamber, the substrate having a chromium layer partially exposed through a patterned carbon hard mask layer, providing a process... Agent: Patterson & Sheridan, LLP

20070072436 - Substrate processing apparatus and substrate processing method: In a substrate processing apparatus of the present invention, when substrates are loaded into a chamber, a frame part formed integral with a substrate holding part is interposed between the chamber and a cover, thereby sealing the interior of the chamber. When the substrates are unloaded to above the chamber,... Agent: Ostrolenk Faber Gerb & Soffen

20070072437 - Method for forming narrow structures in a semiconductor device: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered... Agent: Harrity Snyder, L.L.P.

20070072438 - Method of forming an oxide layer: A method for forming an oxide layer on a substrate. The method includes exposing a process gas containing H2, an oxygen-containing gas, and a halogen-containing oxidation accelerant gas to the substrate, where the process chamber is maintained at a subatmospheric pressure, and forming an oxide layer through thermal oxidization of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070072439 - Semiconductor device and manufacturing method thereof: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070065955 - Perpendicular magnetic recording medium, manufacturing method therefor, and magnetic read/write apparatus using the same: A perpendicular magnetic recording medium includes: a substrate; at least one underlayer formed above the substrate; and a perpendicular magnetic recording layer formed above the at least one underlayer, an easy magnetization axis of the perpendicular magnetic recording layer being oriented perpendicular to the substrate, the perpendicular magnetic recording layer... Agent: Sughrue Mion, PLLC

20070065956 - Contact probe, measuring pad used for the contact probe, and method of manufacturing the contact probe: There is provided a contact probe that is smaller than 50 μm in a pitch between a signal electrode and a ground electrode and can correctly conduct a high-speed high-frequency measurement, a measuring pad used for the contact probe, and a method of manufacturing the contact probe. The contact probe... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070065957 - Method for manufacturing semiconductor device: In the case of forming fine wires and the like by a droplet discharging apparatus to manufacture electric circuits, discharging controls including controls of a discharging position, a discharging timing, and the like are required to have very high accuracy. After forming design diagram data of an electric circuit by... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070065958 - Method for attaching an optical filter to an encapsulated package: A method for attaching an optical device to an encapsulated electronic package. The method may include aligning and attaching an optical device to a non-singulated encapsulated electronic package using an adhesive, and curing the entire package. The method may further include singulating the non-singulated encapsulated electronic package with the optical... Agent: Avago Technologies, Ltd.

20070065959 - Method for manufacturing light-emitting diode: A method for manufacturing a light-emitting diode is described, comprising the following steps. A substrate is provided. An illuminant epitaxial structure is formed on the substrate, wherein the illuminant epitaxial structure comprises a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer stacked on... Agent: Daniel B. Schein, Ph.d., Esq., Inc.

20070065960 - Method for producing a light emitting device: A production method for producing a light-emitting device 1 in which a light-emitting layer at least comprised of a n-type substrate bearing layer 3 and a p-type substrate bearing layer 4 is layered on a transparent crystal substrate 2 is provided with a step of forming a transfer layer 5... Agent: Greenblum & Bernstein, P.L.C

20070065961 - Method of manufacturing amorphous nio thin films and nonvolatile memory devices using the same: Example embodiments relate to a method of manufacturing amorphous NiO thin films and nonvolatile memory devices including amorphous thin films that use a resistance material. Other example embodiments relate to a method of manufacturing amorphous NiO thin films having improved switching and resistance characteristics by reducing a leakage current and... Agent: Harness, Dickey & Pierce, P.L.C

20070065962 - Manufacturing of optoelectronic devices: A method for manufacturing optoelectronic devices is disclosed. A layered structure may be formed with a plurality of layers including a bottom electrode layer, a top electrode layer, and one or more active layers between the top and bottom electrode layers. The layered structure is divided into one or more... Agent: Nanosolar, Inc.

20070065964 - Integrated passive devices: The specification describes a new composite IPD substrate material with properties that are compatible with highly integrated thin film structures. The new composite substrate is a laminate of a wafer of single crystal silicon and a wafer of an insulator. The composite is produced at the wafer level by bonding... Agent: Law Firm Of Peter V.d. Wilde

20070065965 - Manufacturing method and manufacturing apparatus for image display device: After sealing layers are formed on peripheral edge parts of a front substrate and a rear substrate, the front substrate and the rear substrate are disposed to be opposed to each other. Current paths are formed in the sealing layers, and power supply is begun. An electric current, which reaches... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070065963 - Method of manufacturing a micro-mechanical element: A method of manufacturing a micromechanical element wherein the method comprises the steps of providing a layer of base material, applying at least one at least partly sacrificial layer of an etchable material, patterning the at least partly sacrificial layer, to define at least a portion of the shape of... Agent: Cantor Colburn, LLP

20070065967 - Micromachined structures using collimated drie: A method of making an etch structure in a substrate involves the steps of providing a mask on a substrate with a pattern that leaves at least one opening leaving the substrate in direct contact with the ambient, performing an isotropic or quasi-isotropic etch through a mask to create a... Agent: Marks & Clerk

20070065966 - Process for single and multiple level metal-insulator-metal integration with a single mask: Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive... Agent: Greenblum & Bernstein, P.L.C

20070065968 - Fabrication of silicon microphone: A silicon microphone is formed using the steps of providing a first wafer including a layer of heavily doped silicon, a layer of silicon and an intermediate layer of oxide between the two silicon layers. The first wafer has a first major surface on one surface of the layer of... Agent: Jay S Cinamon Abelman Frayne & Schwab

20070065969 - Cmos image sensor and methods of manufacturing the same: An image sensor and methods of manufacturing the same are provided. An isolation layer of a CMOS image sensor including an active pixel region and a logic circuit region and methods of manufacturing the same are also provided. A method of manufacturing an image sensor having a unit pixel, which... Agent: Harness, Dickey & Pierce, P.L.C

20070065970 - Method of fabricating a storage gate pixel design: A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first charge storage region and between the first storage region and a floating diffusion region. A global shutter gate is formed to control the charge... Agent: Dickstein Shapiro LLP

20070065971 - Thin film transistor array substrate and fabricating method thereof: A thin film transistor array substrate structure includes a plurality of data lines; a plurality of gate lines intersecting the data lines to define pixel areas, the gate line being adjacent to at least two pixel areas; a plurality of common lines disposed between the at least two pixel areas;... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20070065972 - Image sensor and method of making same: An image sensor is formed by providing a semiconductor substrate having first, second and third pixel regions and first and second color filters disposed on their respective pixel regions. A photoresist layer is coated over the first and second color filters and the third color pixel region. The photoresist is... Agent: Mills & Onello LLP

20070065973 - Pre-patterned thin film capacitor and method for embedding same in a package substrate: An embedded passive structure, its method of formation, and its integration onto a substrate during fabrication are disclosed. In one embodiment, the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower... Agent: Intel/blakely

20070065977 - Low temperature methods for forming patterned electrically conductive thin films and patterned articles therefrom: A method of forming patterned thin films includes the steps of providing a porous membrane and a solution including a plurality of solid constituents and at least one surface stabilizing agent for preventing the solid constituents from flocculating out of suspension. The solution is dispensed onto a surface of the... Agent: Akerman Senterfitt

20070065976 - Method and apparatus for fabricating organic light emitting display device: A method and an apparatus for fabricating an organic light emitting display, in which a large-sized transmissible film is fabricated to be easily used in an affixing process for a large-sized substrate. The apparatus includes: a first chamber including a plurality of first through holes and having a first transmissible... Agent: Robert E. Bushnell

20070065974 - Method for producing a field effect semiconductor device: There is provided a method for producing a field effect semiconductor device, e.g., a field effect transistor 6 using carbon nanotubes in a channel layer 5, wherein the method includes the step of subjecting the carbon nanotubes to plasma treatment to change a physical or chemical state of the carbon... Agent: Sonnenschein Nath & Rosenthal LLP

20070065975 - Purification of carbon nanotubes based on the chemistry of fenton's reagent: The present invention is directed to methods of purifying carbon nanotubes (CNTs). In general, such methods comprise the following steps: (a) preparing an aqueous slurry of impure CNT material; (b) establishing a source of Fe2+ ions in the slurry to provide a catalytic slurry; (c) adding hydrogen peroxide to the... Agent: Ross Spencer Garsson Winstead Sechrest & Minick P.C.

20070065978 - Method for manufacturing micro-machined switch using pull-up type contact pad: The present invention relates to the manufacture of a semiconductor switch for use in a variety of communication systems, and particularly to the manufacture of a RF micro-machined switch of pull-up type, wherein an electrostatic electrode is used so as to cause the contact pad involved in the operation of... Agent: Darby & Darby P.C.

20070065980 - Method of manufacturing semiconductor chip: A insulation film removing tape 38 is pasted on a metal film 34 so as to cover an opening portion 32, then an insulation film 17 is formed so as to cover the side wall of a through hole 21 from the second major surface 11B side of the semiconductor... Agent: Drinker Biddle & Reath (dc)

20070065979 - Methods and systems for pack-size-oriented rounding: Methods and systems are provided for packing a required quantity of products, wherein a plurality of different packages for packing the products and a plurality of packaging specifications comprising rounding rules are provided. In one implementation, a method is provided comprising determining a packaging specification out of a plurality of... Agent: Sap / Finnegan, Henderson LLP

20070065981 - Semiconductor system-in-package: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070065982 - Controlling overspray coating in semiconductor devices: A manufacturing method, in which two device bars are bonded prior to facet coating to form a stacked bar pair. In one embodiment, each of the device bars has a p-side and an n-side, each side having a plurality of bonding pads, with at least some bonding pads located at... Agent: Mendelsohn & Associates, P.C.

20070065983 - Decoupling capacitor closely coupled with integrated circuit: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070065984 - Thermal enhanced package for block mold assembly: A heat spreader (20) is added to a package to enhance thermal and advantageously electrical performance. In manufacture, a heat spreader precursor (24) is advantageously placed over a group of dies and secured after bonding (e.g., wire or tape bonding or flip-chip bonding) and before matrix/block mold. For example, a... Agent: Wiggin And Dana LLP Attention: Patent Docketing

20070065985 - Bonding apparatus and method of bonding for a semiconductor chip: A method of bonding and a bonding apparatus for a semiconductor chip that apply ultrasonic vibration to the semiconductor chip to bond the semiconductor chip to a substrate carry out leveling effectively at low cost and in a short time and can improve the bonding between the semiconductor chip and... Agent: Staas & Halsey LLP

20070065986 - Method for manufacturing substrate with cavity: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second... Agent: Staas & Halsey LLP

20070065987 - Stacked mass storage flash memory package: A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent... Agent: Trask Britt, P.C./ Micron Technology

20070065988 - Method for manufacturing substrate with cavity: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit patter on both sides of a seed layer by use of a first dry film, the seed layer being for forming a circuit pattern on both sides; (b) laminating a second... Agent: Staas & Halsey LLP

20070065989 - Method for manufacturing an adhesive substrate with a die-cavity sidewall: A method for manufacturing an adhesive substrate with a die-cavity sidewall is disclosed. A region for forming die-cavity sidewall is defined on one surface of the substrate. The substrate is laminated with a sacrificial film, a partially cured resin is formed between the substrate and the sacrificial film. And then,... Agent: Troxell Law Office PLLC

20070065990 - Recursive spacer defined patterning: A method for the patterning of a plurality of fins in a MugFET device is provided. The method involves depositing at least one temporary pattern using photolithography. Further processing steps include a combination of depositing a conformal layer and spacer defined patterning of the conformal layer such that a very... Agent: Knobbe Martens Olson & Bear LLP

20070065993 - Fabricating method for flexible thin film transistor array substrate: A method of fabricating a flexible thin film transistor array substrate is provided. First, a rigid substrate is provided, and a polymer material layer is coated on the rigid substrate. Then, an insulating layer is coated over the polymer material layer by a spin coating process. The insulating layer covers... Agent: Jianq Chyun Intellectual Property Office

20070065992 - Higher selectivity, method for passivating short circuit current paths in semiconductor devices: Certain modifications and additions to the prior art short passivation technique have lead to improvements in the low light voltage of solar cells which are made using the improved passivation technique. Examples of the modifications include: 1) reducing the voltage bias on the cell while increasing the time of application... Agent: Energy Conversion Devices, Inc.

20070065996 - Method for manufacturing a semiconductor device: It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device with preferable yield. In the invention, two-step etching is performed when selectively removing an interlayer insulating film with at least two layers constituting a semiconductor device, and forming an opening. One... Agent: Eric Robinson

20070065994 - Passivation structure for ferroelectric thin-film devices: Ferroelectric thin film devices including a passivation structure to reduce or control a leakage path between two electrodes and along an interface between a ferroelectric thin film layer and a passivation layer are described. Methods for fabricating such devices are also disclosed. The passivation structure includes a first passivation layer... Agent: Fenwick & West LLP

20070065995 - Semiconductor device and method of manufacturing the same: There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a... Agent: Eric Robinson

20070065991 - Thin film transistor array panel and method of manufacturing the same: The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention... Agent: Macpherson Kwok Chen & Heid LLP

20070065997 - Fabricating method of an active-matrix organic electroluminescent display panel: A method for fabricating an active-matrix organic electroluminescent (OEL) display panel is described. A transparent conductive layer is formed on a substrate as a common anode for all organic light emitting diodes (OLED), and a passivation layer is formed on the transparent conductive layer. Thin film transistors are formed on... Agent: Jianq Chyun Intellectual Property Office

20070065998 - Polysilicon thin film fabrication method: A polysilicon thin film fabrication method is provided, in which a heat-absorbing layer is used to provide sufficient heat for grain growth of an amorphous silicon thin film, and an insulating layer is used to isolate the heat-absorbing layer and the amorphous silicon thin film. A regular heat-conducting layer is... Agent: Rosenberg, Klein & Lee

20070065999 - Method for manufacturing semiconductor memory device using asymmetric junction ion implantation: A method for manufacturing a semiconductor memory device using asymmetric junction ion implantation, including performing ion implantation for adjusting a threshold voltage to a semiconductor substrate, forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region, implanting a first... Agent: Marshall, Gerstein & Borun LLP

20070066000 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device including an elevated source/drain structure that can suppress emergence of a junction leak current. The method includes forming a trench on a predetermined position on a surface of a semiconductor substrate, forming an isolation layer so as to fill the trench, and so... Agent: Young & Thompson

20070066001 - Semiconductor device and manufacturing method thereof: The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first semiconductor element device including a pair of first diffusion layers formed in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070066002 - Source capacitor enhancement for improved dynamic ir drop prevention: An implant is added at the interface between the source region of an MOS transistor and the well material to improve dynamic IR drop performance. The additional implant raises the underlying capacitance of the source region. This, in turn, provides for an increase in charge storage which, in turn, provides... Agent: Stallman & Pollock LLP

20070066003 - Methods of forming non-volatile memory devices having trenches: A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the... Agent: Myers Bigel Sibley & Sajovec

20070066004 - Semiconductor device and its manufacture method: A non-volatile semiconductor memory device which simultaneously possesses a non-volatile memory cell region which possesses an isolating insulation film which has been formed selectively within a semiconductor substrate, which also possesses a first electroconductive film (floating gate electrode) via a first gate insulating film which has been formed on the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070066005 - Semiconductor device and method of fabricating the same: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070066006 - Method and structure for electrostatic discharge protection of photomasks: A mask for manufacturing integrated circuits and use of the mask. The mask has a mask substrate. The mask also has an active mask region within a first portion of the mask substrate. The active region is adapted to accumulate a pre-determined level of static electricity. The mask also has... Agent: Townsend And Townsend And Crew, LLP

20070066008 - Method of fabricating non-volatile memory: A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the... Agent: Jianq Chyun Intellectual Property Office

20070066007 - Method to obtain fully silicided gate electrodes: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material... Agent: Texas Instruments Incorporated

20070066009 - Sidewall image transfer (sit) technologies: A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces... Agent: Schmeiser, Olsen & Watts

20070066011 - Integrated circuitry production processes, methods, and systems: The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a substrate. The organic material is contacted with a chemical mechanical polishing pad and a polishing fluid to remove the organic material from the substrate. The polishing fluid... Agent: Wells St. John P.s.

20070066010 - Method of manufacturing semiconductor device: The invention aims at enabling leakage current characteristics and a step coverage property to be improved by depositing a hafnium silicate film by utilizing an atomic layer evaporation method using a hafnium raw material, a silicon raw material and an oxidizing agent. Disclosed herein is a method of manufacturing a... Agent: Robert J. Depke Lewis T. Steadman

20070066012 - Semiconductor device and method for fabricating the same: A semiconductor device comprises a capacitor formed by sequentially stacking a lower electrode, a capacitor insulating film, and an upper electrode over a substrate. The capacitor insulating film is made of Hf oxide or Zr oxide, and between the lower electrode and the capacitor insulating film, a first barrier film... Agent: Mcdermott Will & Emery LLP

20070066015 - Capacitor, method of forming the same, semiconductor device having the capacitor and method of manufacturing the same: Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method... Agent: Harness, Dickey & Pierce, P.L.C

20070066016 - Dynamic random access memory of semiconductor device and method for manufacturing the same: The present invention discloses an improved DRAM of semiconductor device and method for manufacturing the same wherein an ONO (oxide-nitride-oxide) structure for trapping electrons or holes used in a non-volatile memory is employed in a gate insulating film of the DRAM to reduce impurity concentrations of a channel region and... Agent: Heller Ehrman LLP

20070066013 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a first gate conductive layer over the gate insulation layer, forming a barrier metal over the first gate conductive layer, sequentially forming a second gate conductive layer and a gate hard mask over... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070066014 - Nonvolatile memory device and method of fabricating the same: A nonvolatile memory device includes a device isolation layer defining an active region protruding from a semiconductor substrate and an active region separation layer isolating the active region into first and second active regions spaced apart from each other. The active region separation layer is narrower than the device isolation... Agent: F. Chau & Associates, LLC

20070066017 - Horizontal memory devices with vertical gates: Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity of the device fabrication process. The novel memory cell includes a source region and a drain region separated by a channel... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070066018 - Methods of fabricating vertical channel field effect transistors having insulating layers thereon: A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain... Agent: Myers Bigel Sibley & Sajovec

20070066019 - Surround gate access transistors with grown ultra-thin bodies: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short... Agent: Knobbe Martens Olson & Bear LLP

20070066020 - Iii-nitride current control device and method of manufacture: A III-nitride device includes a recessed electrode to produce a nominally off, or an enhancement mode, device. By providing a recessed electrode, a conduction channel formed at the interface of two III-nitride materials is interrupted when the electrode contact is inactive to prevent current flow in the device. The electrode... Agent: Ostrolenk Faber Gerb & Soffen

20070066021 - Formation of gate dielectrics with uniform nitrogen distribution: The present invention provides a method for manufacturing a gate dielectric (710) that includes providing a nitrided dielectric layer (220) over a substrate (120). The nitrided dielectric layer (220) has a nonuniform concentration of nitrogen in a bulk thereof. The nitrided dielectric layer (220) is exposed to oxygen radicals (410),... Agent: Texas Instruments Incorporated

20070066022 - Method of fabricating silicon nitride layer and method of fabricating semiconductor device: A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The silicon nitride layer is UV-cured in an atmosphere lower than the standard atmospheric pressure. Through the UV curing treatment, the tensile stress of the... Agent: J.c. Patents, Inc. Suite 250

20070066023 - Method to form a device on a soi substrate: A method and apparatus for depositing a planar silicon containing layer, depositing an oxide layer, patterning the oxide layer to expose regions of the silicon containing layer above remaining regions of the oxide layer, selectively depositing a silicon and germanium containing layer on the regions of the silicon containing layer,... Agent: Patterson & Sheridan, LLP

20070066024 - Phosphorus activated nmos using sic process: A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure... Agent: Texas Instruments Incorporated

20070066025 - Pattern forming method, computer program thereof, and semiconductor device manufacturing method using the computer program: A pattern forming method for forming a pattern of a desired size on a substrate of a semiconductor device, includes preparing a first database by allocating property data to each position in a chip when the pattern is exposed, preparing a second database by pairing a cell name of a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070066028 - Method for creating narrow trenches in dielectric materials: A method for producing narrow trenches in semiconductor devices. The narrow trenches are formed by chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in the first dielectric layer is converted locally and becomes etchable by a first etching substance.... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070066029 - Method for fabrication of semiconductor device: On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of the depressed portion or less.... Agent: Morrison & Foerster LLP

20070066027 - Method of fabricating microphone device and thermal oxide layer and low-stress structural layer thereof: A substrate is provided and a plurality of trenches are formed in the front surface of the substrate. Then, a thermal oxide layer is formed on inner walls of the trenches and the front surface of the substrate. Subsequently, a first structural layer is formed on the thermal oxide layer,... Agent: North America Intellectual Property Corporation

20070066026 - Method of preventing a peeling issue of a high stressed thin film: A wafer including a high stressed thin film thereon is lifted, and a pre-heating process is performed while the wafer is lifted. Subsequently, a dielectric layer is deposited on the high stressed thin film.... Agent: North America Intellectual Property Corporation

20070066030 - Method of manufacturing an isolation layer of a flash memory: A method including forming a first mask material layer on a semiconductor substrate in order to mask a cell region and to not mask a peripheral circuit region. The method further includes forming a second mask material layer on an entire surface of the substrate in the cell region and... Agent: Mayer, Brown, Rowe & Maw LLP

20070066031 - Method of manufacturing semiconductor stucture: A method of manufacturing a semiconductor structure for a substrate having electronic elements formed thereon is described. The method includes steps of forming a dielectric layer over the substrate and forming a trench in the dielectric layer. It should be noticed that a border shape of the trench is a... Agent: Jianq Chyun Intellectual Property Office

20070066032 - Nanopowder coating for scribing and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a conformal layer of a water soluble nanopowder on a wafer, and then scribing the wafer.... Agent: Blakely Sokoloff Taylor & Zafman

20070066035 - Cleaved silicon substrate active device: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070066033 - Process for producing high-resistance silicon wafers and process for producing epitaxial wafers and soi wafers (as amended): By using oxygen-containing silicon wafers obtained by the CZ method and by combining the first heat treatment comprising controlled heat-up operation (ramping) with the second heat treatment comprising high-temperature heat treatment and medium temperature heat treatment in accordance with the process for producing high-resistance silicon wafers according to the present... Agent: Clark & Brody

20070066034 - Semiconductor substrate with islands of diamond and resulting devices: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the... Agent: Intel Corporation C/o Intellevate, LLC

20070066036 - Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers: A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow... Agent: Brooks Kushman P.C.

20070066038 - Fast gas switching plasma processing apparatus: A plasma chamber with a plasma confinement zone with an electrode is provided. A gas distribution system for providing a first gas and a second gas is connected to the plasma chamber, wherein the gas distribution system can substantially replace one gas in the plasma zone with the other gas... Agent: Beyer Weaver LLP

20070066037 - Method of manufacturing nitride semicondctor device: A method of manufacturing a nitride semiconductor device includes the steps of, forming a stripping layer including In on a substrate; forming a nitride semiconductor layer on the stripping layer; causing a decomposition of the stripping layer by increasing a temperature of the stripping layer; irradiating the stripping layer with... Agent: Ndq&m Watchstone LLP

20070066039 - Methods of processing semiconductor wafers having silicon carbide power devices thereon: Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070066040 - Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces: Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a substrate and a terminal carried by the substrate, and removing a section of the... Agent: Perkins Coie LLP Patent-sea

20070066041 - Fabricating method for a metal oxide semiconductor transistor: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate... Agent: Jianq Chyun Intellectual Property Office

20070066042 - Method of forming an electrical contact: In a test system, a silicon interconnect is provided that can accommodate a packaged part, such as a Land Grid Array (LGA) package. The interconnect can be made by etching a silicon substrate to form projections therefrom; forming an insulation or passivation layer through deposition or growth; depositing a seed... Agent: Trask Britt, P.C./ Micron Technology

20070066043 - Semiconductor device and fabrication process thereof: A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field effect transistor having a second polysilicon gate electrode... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070066044 - Semiconductor manufacturing method: In a stealth dicing process for a semiconductor device with a low dielectric constant layer, the occurrence of poor appearance such as a defective shape or discoloration in the layer is reduced or prevented as follows. A low dielectric constant layer is formed in an interlayer insulating layer formed on... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070066045 - Method for manufacturing substrate with cavity: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a barrier around a predetermined area where the cavity is to be formed on a copper foil laminated master, an internal circuit formed in the copper foil laminated master; (b) coating a thermosetting material... Agent: Staas & Halsey LLP

20070066046 - Method of electrically connecting a microelectronic component: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first... Agent: Tessera Lerner David Et Al.

20070066048 - Method for creating electrically conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies: A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric layer may be formed thereover. At least one depression may be laser ablated in the dielectric layer and an electrically conductive material... Agent: Trask Britt, P.C./ Micron Technology

20070066047 - Method of forming opening and contact: A method for forming an opening on a material layer is provided. First, a dielectric layer is formed on the material layer. Then, a metallic hard mask layer and a cap layer are sequentially formed on the dielectric layer. Thereafter, a patterned photoresist layer is formed on the cap layer.... Agent: Jianq Chyun Intellectual Property Office

20070066049 - Method for patterning and etching a passivation layer: A method for patterning passivation layers including providing a semiconductor wafer comprising metal interconnects; forming a dielectric passivation layer on the metal interconnects; forming a photosensitive polymeric passivation layer on the dielectric passivation layer; patterning the photosensitive polymeric passivation layer in a first patterning process to form a first opening... Agent: Tung & Associates

20070066050 - Semiconductor device and a method of manufacturing the same: An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070066051 - Method for forming gate pattern for electronic device: A method for forming a gate pattern for an electronic device, comprising steps of: providing a substrate, whereon a first photo-resist layer is formed; performing a first photo-lithography process so as to form a first pattern with a first width on the substrate; forming a second photo-resist layer, covering the... Agent: Bruce H. Troxell

20070066052 - Semiconductor device having three-dimensional construction and method for manufacturing the same: A semiconductor device includes: a silicon substrate; and a silicon oxide film disposed on the silicon substrate. The silicon oxide film includes a part, which separates from a surface of the silicon substrate, so that the silicon oxide film provides a three-dimensional construction. By using the three-dimensional construction, an additional... Agent: Posz Law Group, PLC

20070066053 - Method for producing substrate having carbon-doped titanium oxide layer: A method for producing a substrate having a carbon-doped titanium oxide layer, which is excellent in durability (high hardness, scratch resistance, wear resistance, chemical resistance, heat resistance) and functions as a visible light responding photocatalyst, is provided. The surface of a substrate, which has at least a surface layer comprising... Agent: Sughrue Mion, PLLC

20070066054 - Method of forming contact layers on substrates: A method is provided for manufacturing removable contact structures on the surface of a substrate to conduct electricity from a contact member to the surface during electroprocessing. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact... Agent: Knobbe Martens Olson & Bear LLP

20070066055 - Method of fabricating conductive layer: A method of fabricating a patterned conductive layer is provided. First, a conductive layer whose material includes at least aluminum-copper (Al—Cu) alloy is formed on a substrate. Then, a heat treatment process is performed to heat the conductive layer to a temperature higher than the phase change temperature of the... Agent: Jianq Chyun Intellectual Property Office

20070066056 - Method of removing a photoresist and method of manufacturing a semiconductor device using the same: Example embodiments of the present invention provide a method of removing a photoresist and a method of manufacturing a semiconductor device using the same. In a method of removing a photoresist and a method of manufacturing a semiconductor device, a plasma including active ions and radicals may be generated. The... Agent: Harness, Dickey & Pierce, P.L.C

20070066057 - Defectivity and process control of electroless deposition in microelectronics applications: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.... Agent: Senniger Powers

20070066058 - Defectivity and process control of electroless deposition in microelectronics applications: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.... Agent: Senniger Powers

20070066059 - Defectivity and process control of electroless deposition in microelectronics applications: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.... Agent: Senniger Powers

20070066060 - Semiconductor devices and fabrication methods thereof: Semiconductor devices and fabrication methods thereof. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an tungsten-containing barrier is conformably formed in the opening, with a thickness less than 50 Å. A tungsten layer is formed over the atomic layer deposited (ALD)... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070066061 - Organic aluminum precursor and method of forming a metal wire using the same: An organic aluminum precursor includes aluminum as a central metal, and borohydride and trimethylamine as ligands. In a method of forming an aluminum layer or wire, the organic aluminum presursor is introduced onto a substrate, and then thermally decomposed. The aluminum decomposed from the organic aluminum precursor is deposited on... Agent: Volentine Francos, & Whitt PLLC

20070066062 - Landing uniformity ring for etch chamber: A novel landing uniformity ring for an etch chamber is disclosed. The landing uniformity ring includes an annular ring body defining a ring opening and an increased-diameter inner flange extending inwardly from the ring body, into the ring opening. When mounted in a landing uniformity ring assembly, the inner flange... Agent: Tung & Associates

20070066063 - Method for chemical mechanical planarization of a metal layer located over a photoresist layer and a method for manufacturing a micro pixel array using the same: The present invention provides a method for planarizing a metal layer, and a method for manufacturing a micro pixel array. The method for planarizing the metal layer, without limitation, may include the steps of forming a metal layer over a photoresist layer, and then planarizing the metal layer using a... Agent: Texas Instruments Incorporated

20070066064 - Methods to avoid unstable plasma states during a process transition: In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by... Agent: Aagaard & Balzan, LLP

20070066065 - Metal-polishing liquid and chemical-mechanical polishing method: The present invention provides a metal-polishing liquid comprising an oxidizing agent and a heterocyclic aromatic ring compound, wherein the time until the oxidation reaction rate is (E1+E2)/2 is shorter than 1.0 second, E1 being an oxidation reaction rate immediately after initiation of oxidation of a metal surface to be polished... Agent: Sughrue Mion, PLLC

20070066066 - Polishing method for glass substrate, and glass substrate: A surface of a glass substrate containing SiO2 as the main component, is polished with a polishing slurry comprising colloidal silica having an average primary particle size of at most 50 nm, an acid and water, and having the pH adjusted to be within a range of from 0.5 to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070066067 - Method for reducing foreign material concentrations in etch chambers: A method of reducing foreign material concentrations in an etch chamber having inner chamber walls is described. The method includes the step of etching a work piece in the etch chamber such that reaction products from the work piece having one or more elements form a first layer of reaction... Agent: Anthony J. CanaleIPLaw Department, 972e

20070066068 - Method of depositing a layer comprising silicon, carbon, and flourine onto a semiconductor substrate: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing... Agent: Wells St. John P.s.

20070066069 - Radiation-resistant zone plates and methods of manufacturing thereof: Disclosed are radiation-resistant zone plates for use in laser-produced plasma (LPP) devices, and methods of manufacturing such zone plates. In one aspect, a method of manufacturing a zone plate provides for forming a masking layer over a supporting membrane, and creating openings through the masking layer in a diffractive... Agent: Baker & Mckenzie LLP Patent Department

20070066070 - Apparatus for imprinting lithography and fabrication thereof: An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vertical sidewalls of a wet chemical etched trench. The sidewalls are aligned with and... Agent: Hewlett Packard Company

20070066072 - Method of fabricating semiconductor device: Disclosed is a method of manufacturing a semiconductor device using a dual damascene process. A first etching barrier film, an insulation film and a second etching barrier film are formed in sequence on a semiconductor substrate having a first metallic wiring therein and are then selectively etched to form a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070066071 - Novel organic remover for advanced reticle contamination cleaning: A method includes introducing an acid solution having ethanol and an acid to a substrate and cleaning the substrate using the acid solution; applying an ultrasonic wave to the acid solution substantially during the cleaning of the substrate; and performing a fine cleaning of the substrate after the cleaning of... Agent: Haynes And Boone, LLP

20070066073 - Like integrated circuit devices with different depth: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth... Agent: International Business Machines Corporation Dept. 18g

20070066075 - Semiconductor manufacturing method: According to an aspect of the embodiment, there is provided a semiconductor manufacturing method comprises: purging a growth chamber including a reaction product, a treatment chamber, and a glove box hermetically surrounding the growth chamber, with an inert gas atmosphere; transferring the reaction product from the growth chamber to the... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701

20070066074 - Shallow trench isolation structures and a method for forming shallow trench isolation structures: A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is... Agent: Hitt Gaines, PC Agere Systems Inc.

20070066077 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes doping a surface of a silicon-containing dielectric film with nitrogen to change an etching rate of the silicon-containing dielectric film relative to a predetermined solution such that the etching rate is lower at a surface portion doped with nitrogen than at a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070066076 - Substrate processing method and apparatus using a combustion flame: A substrate processing method and apparatus using a combustion flame of a gaseous mixture of hydrogen and a non-oxygen oxidizer is described. The method uses the hydrogen and non-oxygen oxidizer combustion flame to impinge upon a substrate surface for chemically reacting with a thin film on the surface and thus... Agent: Harness, Dickey & Pierce, P.L.C

20070066078 - Method of producing a substrate having areas of different hydrophilicity and/or oleophilicity on the same surface: The present invention relates to flexible substrates having on their surface a wetting contrast. The wetting contrast comprises adjacent areas of different hydrophilicity and/or oleophilicity. The present invention further relates to methods of production of such substrates and to methods of producing microelectronic components wherein electronically functional material is deposited... Agent: Oliff & Berridge, PLC

20070066080 - Method of producing a substrate having areas of different hydrophilicity and/or oleophilicity on the same surface: The present invention relates to substrates having wetting contrasts which include a top layer of polymer matrix and particles of an inorganic material. Such substrates can be processed in various ways which allow the production of good wetting contrasts by various processing means. According to a first aspect of the... Agent: Oliff & Berridge, PLC

20070066079 - Sealing porous dielectrics with silane coupling reagents: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at... Agent: Blakely Sokoloff Taylor & Zafman

20070066081 - Catalytic activation technique for electroless metallization of interconnects: A method of forming a metal interconnect for an integrated circuit comprises providing a substrate that includes a trench formed in a dielectric layer, employing a first dry thermal process to deposit a barrier layer onto the dielectric layer and within the trench, employing a second dry thermal process to... Agent: Blakely Sokoloff Taylor & Zafman

20070066082 - Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafer: Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by placing a wafer on a susceptor, pretreating under a hydrogen atmosphere, in and then with addition of an etching medium, and coating epitaxially on a polished front side, wherein an etching treatment of the susceptor is effected after... Agent: Brooks Kushman P.C.

20070066083 - Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same: In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a... Agent: Volentine Francos, & Whitt PLLC

20070066084 - Method and system for forming a layer with controllable spstial variation: A method and processing system for treating a surface of a substrate. The surface is exposed to at least two radicals from at least two radical sources. The radicals generated from the respective radical sources interact with different areas of the substrate surface. The invention suitably improves uniformity of oxidation,... Agent: Dla Piper US LLP

20070066085 - Method of fabricating dielectric layer: A method of fabricating a dielectric layer is described. A twelve-inch wafer having at least three metallic layers thereon is provided. A dielectric layer is formed over the twelve-inch wafer by performing a high-density plasma process. The high-density plasma process includes applying a total bias radio frequency (RF) power and... Agent: Jianq Chyun Intellectual Property Office

20070066086 - Method of forming silicon-containing insulation film having low dielectric constant and low film stress: A method for forming a silicon-containing insulation film on a substrate by plasma polymerization includes: introducing a reaction gas comprising (i) a source gas consisting of a silicon-containing hydrocarbon linear compound containing at least one vinyl group (Si-vinyl compound), and (ii) an additive gas, into a reaction chamber where a... Agent: Knobbe Martens Olson & Bear LLP

20070066087 - Method of manufacturing a semiconductor device: According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device having active regions including a SONOS device region, a high voltage device region, and a logic device region, includes defining the active regions by forming a device isolation region on a semiconductor substrate; performing... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070059846 - Manufacturing method for semiconductor memory: A semiconductor memory is fabricated in the following manner. A tungsten plug is formed by burying metal material such as W into a contact hole formed in an inter-layer insulation film. Then, the inter-layer insulation film is etched back by a predetermined thickness so that the upper end portion of... Agent: Volentine Francos, & Whitt PLLC

20070059847 - Method and system for optimizing a barc stack: In the present invention, a BARC stack comprising at least a first BARC layer and at least a second BARC layer is optimized for reducing substrate reflectivity in lithographic processing applications. The first BARC layer is positioned adjacent the resist layer, while the second BARC layer is positioned adjacent the... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070059849 - Method and system for barc optimization for high numerical aperture applications: A method is described for setting up lithographic processing of a substrate. The lithographic processing uses a bottom anti-reflective coating for minimizing the substrate reflectivity. Such bottom anti-reflective coating typically is characterized by a set of selectable BARC parameters, such as the thickness, real refractive index, and/or absorption coefficient. The... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070059850 - Method and system for derivation of breakdown voltage for mos integrated circuit devices: A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and... Agent: Townsend And Townsend And Crew, LLP

20070059848 - Method of controlling impurity doping and impurity doping apparatus: Disclosed here is a method of controlling a dose amount of dopant to be doped into object (1) to be processed in plasma doping. According to the method, the doping control is formed of the following processes: determining the temperature of object (1), the amount of ions having dopant in... Agent: Wenderoth, Lind & Ponack L.L.P.

20070059851 - Multiple point gate oxide integrity test method and system for the manufacture of semiconductor integrated circuits: A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a... Agent: Townsend And Townsend And Crew, LLP

20070059853 - Method for manufacturing semiconductor device: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a... Agent: Miles & Stockbridge PC

20070059852 - Semiconductor light-emitting device and fabrication method thereof: An underlying layer ALY of GaN is formed on a sapphire substrate SSB; a transfer layer TLY of GaN with a bump and dip shaped surface is formed on the underlying layer ALY; a light absorption layer BLY is formed on the bump and dip shaped surface of the transfer... Agent: Arent Fox PLLC

20070059854 - Flexible pixel array substrate and method for fabricating the same: The present invention provides a method for fabricating a flexible pixel array substrate as follows. First, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and the release layer being higher than that... Agent: Jianq Chyun Intellectual Property Office

20070059855 - Method for manufacturing ffs mode lcd: In the present invention, a method for manufacturing a liquid crystal display is provided. The method includes steps of providing a substrate, forming a first metal layer on the substrate, etching the first metal layer to form a plurality of gate lines on the substrate, forming a common electrode on... Agent: Volpe And Koenig, P.C.

20070059856 - Method for manufacturing optical device: A method for manufacturing an optical device having an optical block, through which a light is transmitted, is provided. The method includes steps of: forming a plurality of silicon oxide members, which is disposed on a silicon substrate, wherein the silicon oxide members are arranged in parallel each other by... Agent: Posz Law Group, PLC

20070059858 - Microfabricated capacitive ultrasonic transducer for high frequency applications: The invention relates to an electro-acoustic transducer, particularly an ultrasonic transducer, comprising a plurality of electrostatic micro-cells of the cMUT type. The electrostatic micro-cells are arranged in homogeneous groups of micro-cells having the same geometrical characteristics. The micro-cells of each group have geometries different from the geometry of the micro-cells... Agent: Woodard, Emhardt, Moriarty, Mcnett & Henry LLP

20070059857 - Three-axis accelerometer: The invention comprises a method of fabricating a three-axis accelerometer. A first wafer having a first and a second major surface provided with etching at least two cavities in the first major surface of the first wafer and patterning metal onto the first major surface of the first wafer to... Agent: Abelman Frayne & Schwab

20070059859 - Hydrogen reservoir based on silicon nano-structures: The invention relates to a hydrogen reservoir comprising a substance suitable for storing hydrogen wherein said substance is made up of nano-structured silicon. It also relates to a process for manufacturing and a method for use of this hydrogen reservoir.... Agent: Hutchison Law Group PLLC

20070059860 - Method for manufacturing semiconductor package: A die for encapsulating an IC structural body having bonding wires with a molt resin is provided with at least one first half having an ejector-pin-through-hole and at least one second half coupled together to form a cavity therebetween. An ejector pin having a mirror-finished surface at a tip end... Agent: Volentine Francos, & Whitt PLLC

20070059861 - Systems and methods for transferring small lot size substrate carriers between processing tools: In a first aspect, a method of managing work in progress within a small lot size semiconductor device manufacturing facility is provided. The first method includes providing a small lot size semiconductor device manufacturing facility having (1) a plurality of processing tools; and (2) a high speed transport system adapted... Agent: Dugan & Dugan, PC

20070059862 - Multiple chip semiconductor package: A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality... Agent: Trask Britt, P.C./ Micron Technology

20070059863 - Method of manufacturing quad flat non-leaded semiconductor package: A method of manufacturing a quad flat non-leaded semiconductor package is provided. A metal plate is prepared and is defined with predetermined positions of a plurality of electrically conductive pads. A resist layer is formed on the metal plate, and a plurality of openings are formed in the resist layer... Agent: Edwards & Angell, LLP

20070059864 - Method for manufacturing thermal interface material with carbon nanotubes: A method for manufacturing a thermal interface material includes the steps of: (a) forming an array of carbon nanotubes on a substrate; (b) submerging the carbon nanotubes in a liquid macromolecular material; (c) solidifying the liquid macromolecular material; and (d) cutting the solidified liquid macromolecular material, to obtain the thermal... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070059865 - Semiconductor package with a support structure and fabrication method thereof: A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip... Agent: Ishimaru & Zahrt LLP

20070059866 - Fan out type wafer level package structure and method of the same: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover,... Agent: Gary M. Nath Nath & Associates PLLC

20070059867 - Method of manufacturing an optical module: Manufacturing an optical module includes providing a frame, attaching a light-emitting diode chip and a sensor chip to the frame, and forming overcoats on the light-emitting diode chip and the sensor chip. Each of the overcoats includes a lens. The overcoats can prevent internal chips from being damaged and suffering... Agent: North America Intellectual Property Corporation

20070059868 - Thin film transistor manufacturing method and substrate structure: A method of TFT (Thin Film Transistor) manufacturing and a substrate structure are provided. The structure includes a substrate and a self-alignment mask. A self-alignment mask on a substrate is first manufactured and then the self-alignment mask may synchronously extend with the substrate during the thermal process. When an exposure... Agent: Rabin & Berdo, PC

20070059869 - Electrode for electric chemical capacitor, manufacturing method and apparatus thereof: A manufacturing method for an electrode for an electrochemical capacitor according to the present invention comprises a first process (steps S1-S3) for forming a polarizable electrode layer on a current collector, a second process (step S4) for subjecting the front surface of the polarizable electrode layer formed on the current... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070059870 - Method of forming carbon-containing silicon nitride layer: A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia and at least one carbon-source precursor as reactant gases is provided.... Agent: Jianq Chyun Intellectual Property Office

20070059872 - Mos transistor gates with doped silicide and methods for making the same: Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates,... Agent: Texas Instruments Incorporated

20070059871 - Semiconductor device and manufacturing method thereof: In a method of manufacturing a semiconductor device, a recess is formed in a semiconductor substrate. A gate insulating film is formed on a surface of the semiconductor substrate and a surface of the recess; and a gate electrode film is deposited on the gate insulating film to fill the... Agent: Sughrue Mion, PLLC

20070059874 - Dual metal gate and method of manufacture: Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned... Agent: Fulbright & Jaworski L.L.P.

20070059873 - Fabrication of single or multiple gate field plates: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a... Agent: Gates & Cooper LLP Howard Hughes Center

20070059875 - Semiconductor device and method of manufacturing the same, and semiconductor substrate and method of manufacturing the same: A method of manufacturing a semiconductor device including a substrate; an insulating film formed thereon; a first semiconductor layer where strain is induced in the directions parallel to the surface of the substrate, the first semiconductor layer being on the insulating film; a source region and a drain region formed... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070059876 - Method of fabricating a flash memory device: A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate using the mask patterns as an etch mask to form a plurality of trenches, and filling the trenches with... Agent: Volentine Francos, & Whitt PLLC

20070059877 - Spin transistor using spin-orbit coupling induced magnetic field: A spin transistor having wide ON/OFF operation margin and producing less noise is provided. The spin transistor includes a substrate having a channel, a source, a drain and a gate formed on the substrate. The source and the drain are formed to have magnetization directions perpendicular to the length direction... Agent: Perkins Coie LLP

20070059878 - Salicide process: A salicide process includes providing a substrate, in which the surface of the substrate contains at least a silicon layer; performing a degas process on the substrate; performing a cooling process on the substrate; depositing a metal layer over the surface of the substrate, in which the surface of the... Agent: North America Intellectual Property Corporation

20070059879 - Pixel structure and fabricating method thereof: A pixel structure is provided, which includes a substrate, a thin film transistor (TFT), a capacitor, a protection layer and a pixel electrode. The substrate has an active device region and a capacitor region and a plurality of openings are formed within the capacitor region. Besides, the TFT is disposed... Agent: J.c. Patents, Inc.

20070059881 - Atomic layer deposited zirconium aluminum oxide: A dielectric layer having atomic layer deposited zirconium aluminum oxide and a method of fabricating such a dielectric layer may produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The zirconium aluminum oxide may be formed in an atomic layer deposition process that includes... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070059880 - Hsg process and process of fabricating large-area electrode: A hemispherical silicon grain (HSG) process is described. A doped poly-Si layer is formed on a substrate, and then an oxidative gas is used to oxidize the surface of the doped poly-Si layer to form an oxide layer. An a-Si layer is then formed on the oxide layer, and the... Agent: Jianq Chyun Intellectual Property Office

20070059882 - Memory elements having patterned electrodes and method of forming the same: A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes over a substrate and forming a blanket material stack over the first electrodes. The stack includes a plurality of layers, at least one layer of... Agent: Dickstein Shapiro LLP

20070059883 - Method of fabricating trap nonvolatile memory device: A method of fabricating a floating trap type nonvolatile memory device is provided. The method includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequentially stacked; thermally... Agent: Marger Johnson & Mccollom, P.C.

20070059884 - Method of manufacturing flash memory device: The invention provides a method of manufacturing a flash memory device. Nitride film spacers are formed on sidewalls of protruded isolation films. A recess is formed in a semiconductor substrate by a self-aligned etch process using the nitride film spacers as masks. It is therefore possible to form a uniform... Agent: Marshall, Gerstein & Borun LLP

20070059885 - Semiconductor device and method of manufacturing same: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070059886 - System and method for automatically calculating parameters of an mosfet: A system for automatically calculating parameters of an MOSFET is disclosed. The parameter calculating system runs in a computer. The parameter calculating system is used for receiving values inputted, and for calculating parameters of the MOSFET according to the input values. The parameter calculating system includes an operation selecting module... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070059887 - Method for producing a trench transistor and trench transistor: A method is disclosed for producing a trench transistor which has at least two trenches with in each case a field electrode arranged therein and a gate electrode arranged therein. In the method, it is provided to implement the trenches with different trench widths and then to produce the field... Agent: Maginot, Moore & Beck Chase Tower

20070059888 - Semiconductor integrated circuit device and manufacturing method thereof: A semiconductor integrated circuit device having a pair of adjacent MOS transistors and a contact plug 33, buried into a contact hole formed by a self-aligned contact process using a silicon nitride film as an etching stopper and electrically connected to diffusion layers 2 and 3 constituting the MOS transistor... Agent: Mcginn Intellectual Property Law Group, PLLC

20070059889 - Recessed gate electrode and method of forming the same and semiconductor device having the recessed gate electrode and method of manufacturing the same: A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner... Agent: Marger Johnson & Mccollom, P.C.

20070059890 - Methods of manufacturing semiconductor thin film, electronic device and liquid crystal display device: A semiconductor thin film manufacturing method includes: forming a semiconductor thin film on a substrate; forming a transcriptional body containing a metal element on a part thereof; bringing a part of the transcriptional body into contact with the semiconductor thin film, and transferring the metal element onto the semiconductor thin... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070059891 - Mandrel/trim alignment in sit processing: Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus,... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070059892 - Method for fabricating a semiconductor structure: A semiconductor structure is fabricated to have a transistor cell region and a connection region. The transistors both of a transistor cell region and of a connection region are coated with a first oxide layer, the layer thickness of the first oxide layer being dimensioned in such a way that... Agent: Slater & Matsil LLP

20070059893 - Stacked capacitor and method for producing stacked capacitors for dynamic memory cells: A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26).... Agent: Slater & Matsil LLP

20070059894 - Selective deposition of germanium spacers on nitride: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070059895 - Dielectric layer, method of manufacturing the dielectric layer and method of manufacturing capacitor using the same: A dielectric layer, an MIM capacitor, a method of manufacturing the dielectric layer and a method of manufacturing the MIM capacitor. The method of manufacturing the dielectric layer includes chemically reacting a metal source with different amounts of an oxidizing agent based on the cycle of the chemical reactions in... Agent: Stanzione & Kim, LLP

20070059896 - Nitrous oxide anneal of teos/ozone cvd for improved gapfill: A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes varying over time a ratio of... Agent: Townsend And Townsend And Crew LLP / Amat

20070059897 - Isolation for semiconductor devices: Methods of forming and structures for isolation structures for semiconductor devices are disclosed. The isolation structures are wider at the bottom than at the top, providing the ability to further scale the size of semiconductor devices. A first etch process is used to form a first trench portion, and a... Agent: Slater & Matsil LLP

20070059898 - Semiconductor devices including trench isolation structures and methods of forming the same: Trench isolation methods include forming a first trench and a second trench, having a larger width than the first trench, in a semiconductor substrate. A lower isolation layer is formed having a first thickness on an upper sidewall of the first trench and a second thickness on an upper sidewall... Agent: Robert W. Glatz Myers Bigel Sibley & Sajovec, P.A.

20070059899 - Sub-micron space liner and filler process: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a... Agent: Knobbe Martens Olson & Bear LLP

20070059900 - Multi-step depositing process: The present invention provides a multi-steps depositing process. The process provides a substrate having at least a shallow trench, and then performs a first high density plasma chemical vapor deposition (HDP CVD) to form a first dielectric layer on the substrate and a surface of the shallow trench. A partial... Agent: North America Intellectual Property Corporation

20070059901 - Metal and electronically conductive polymer transfer: The invention relates to a donor laminate comprising in order, a substrate, an electronically conductive polymer layer in contact with said substrate, and a metal layer.... Agent: Paul A. Leipold Patent Legal Staff

20070059902 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is disclosed, in which a laser marking is formed on a rear surface of a wafer to prevent a Cu layer from being peeled by a protrusion of the laser marking. The method includes forming a laser marking on a rear surface of... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070059903 - Pressure-sensitive adhesive sheet and method of processing articles: To provide a pressure-sensitive adhesive that is used in processing an article such as a semiconductor wafer, the pressure-sensitive adhesive sheet is one that has a base, an intermediate layer and a pressure-sensitive adhesive layer in order, wherein the intermediate layer has an elastic modulus at elongation at 23° C.... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070059904 - Method of manufacturing silicon wafer: The present invention provides a method of manufacturing a silicon wafer where a defect does not exist at a wafer surface layer part on which a device is formed, without affecting productivity and production costs of the wafer. An ingot of a silicon single crystal is grown by way of... Agent: Foley And Lardner LLP Suite 500

20070059905 - Metal product producing method,metal product,metal component connecting method,and connection structure: A deposition is gradually formed by molding a product main body, removing a defect periphery including a defect generated on a surface to be treated of the product main body by molding so that a recess portion is formed on the surface to be treated of the product main body,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070059906 - Semiconductor device having a spacer layer doped with slower diffusing atoms than substrate: A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed... Agent: Hiscock & Barclay, LLP

20070059907 - Implantation process in semiconductor fabrication: A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity... Agent: Slater & Matsil LLP

20070059909 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semiconductor substrate; processing at least the... Agent: Young & Thompson

20070059908 - Transistor design self-aligned to contact: The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one aspect, the method of manufacturing a transistor device includes providing a gate structure (140) over a substrate (110). An insulating layer (310) is formed over the... Agent: Texas Instruments Incorporated

20070059910 - Semiconductor structure and method for manufacturing the same: A semiconductor structure and method for manufacturing the same is disclosed. The present invention relates to a semiconductor having a dielectric layer applied on a gate of a transistor, and a high dielectric-coefficient, and a manufacturing method of the semiconductor. Ti is formed on HfO2 to absorb oxygen from the... Agent: Rabin & Berdo, P.C. Suite 500

20070059912 - Method of forming metal silicide layer and related method of fabricating semiconductor devices: A method of forming a composite metal silicide layer is disclosed in which a PVD-metal layer is deposited on a silicon layer using a Physical Vapor Deposition (PVD) process, and is substantially simultaneously silicidated to form a PVD-metal silicide layer. Un-reacted portions of the PVD-metal layer are then removed and... Agent: Volentine Francos, & Whitt PLLC

20070059911 - Semiconductor fabrication process including silicide stringer removal processing: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the... Agent: Freescale Semiconductor, Inc. Law Department

20070059913 - Capping layer to reduce amine poisoning of photoresist layers: An apparatus for reducing amine poisoning of photoresist layers comprises a substrate, an etch stop layer containing amines formed over the substrate, and a dense capping layer formed directly on the etch stop layer, wherein the dense capping layer substantially prevents the amines from diffusing out of the etch stop... Agent: Blakely Sokoloff Taylor & Zafman

20070059915 - Method of forming an electrical contact: In a test system, a silicon interconnect is provided that can accommodate a packaged part, such as a Land Grid Array (LGA) package. The interconnect can be made by etching a silicon substrate to form projections therefrom; forming an insulation or passivation layer through deposition or growth; depositing a seed... Agent: Trask Britt, P.C./ Micron Technology

20070059914 - Method of forming micro patterns in semiconductor devices: A method of forming a micro pattern in a semiconductor device is disclosed. An oxide film mask is divided into a cell oxide film mask and a peri oxide film mask. Therefore, a connection between the cell and the peri region can be facilitated. A portion of a top surface... Agent: Marshall, Gerstein & Borun LLP

20070059916 - Manufacturing method of semiconductor device: A lead for external connection is formed of the alloy (42Alloy) of Fe and Ni, and a plating film which includes alloy of Sn and Cu is formed on the surface. Next, using a heat-treat furnace, the heat treatment at the temperature beyond melting-point T0 of the plating film is... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070059917 - Printed circuit board having fine pattern and manufacturing method thereof: A manufacturing method for a printed circuit board having a fine pattern is disclosed, comprising: providing a carrier plate; coating the carrier plate with a photosensitive material; forming a first circuit pattern on the photosensitive material; forming a first circuit layer by drying a conductive paste printed into a space... Agent: Staas & Halsey LLP

20070059919 - Method of manufacturing semiconductor device: Disclosed herein is a method of manufacturing a semiconductor device, including the steps of: forming an interlayer insulating film on a semiconductor substrate; forming a metal mask on the interlayer insulating film; forming a pattern trench in the metal mask and the interlayer insulating film by etching away parts of... Agent: Sonnenschein Nath & Rosenthal LLP

20070059918 - Rigid-flexible printed circuit board for package on package and manufacturing method: The present invention relates to a rigid-flexible multi-layer printed circuit board comprising: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a... Agent: Staas & Halsey LLP

20070059920 - Method of fabricating copper damascene and dual damascene interconnect wiring: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual... Agent: Schmeiser, Olsen & Watts

20070059921 - Semiconductor device interconnection contact and fabrication method: A semiconductor device interconnection contact and fabrication method comprises fabricating one or more active devices on a semiconductor substrate. A diffusion barrier layer is deposited over the devices, followed by an Al-based metallization layer. The diffusion barrier and metallization layers are masked and etched to define interconnection traces. Mask and... Agent: Koppel, Patrick & Heybl

20070059923 - Methods of fabricating damascene interconnection line in semiconductor devices and semiconductor devices fabricated using such methods: Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening... Agent: Lee & Morse, P.C.

20070059922 - Post-etch removal of fluorocarbon-based residues from a hybrid dielectric structure: The present invention relates to methods for post-etch, particularly post-RIE, removal of fluorocarbon-based residues from a hybrid dielectric structure. The hybrid dielectric structure contains a first dielectric material, and a line-level dielectric layer containing a second, different dielectric material, and wherein said second, different dielectric material comprises a polymeric thermoset... Agent: Scully Scott Murphy & Presser, PC

20070059924 - Method of manufacturing semiconductor device: According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including forming on a semiconductor substrate an insulating film having a recessed portion in a surface thereof, forming on the insulating film a first metal film so as to fill... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070059925 - Method of forming metal wiring layer of semiconductor device: A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second... Agent: Volentine Francos, & Whitt PLLC

20070059926 - Method for fabricating semiconductor device including resist flow process and film coating process: A method for fabricating a semiconductor device wherein a photoresist pattern is formed over an underlying layer, followed by a resist flow process and a coating treatment process, thereby obtaining a photoresist pattern reduced to the same size regardless of pattern density of photoresist. As a result, the disclosed method... Agent: Marshall, Gerstein & Borun LLP

20070059927 - Method of fabricating semiconductor device including resist flow process and film coating process: A method for fabricating a semiconductor device wherein a photoresist pattern is formed over an underlying layer, followed by a resist flow process and a coating treatment process, thereby obtaining a photoresist pattern reduced to the same size regardless of pattern density of photoresist. As a result, the disclosed method... Agent: Marshall, Gerstein & Borun LLP

20070059928 - Methods for synthesis of metal nanowires: Methods for synthesizing metal nanowires are provided. A metalorganic layer is deposited on a substrate as a thin film. The thermal decomposition of the metalorganic thin film in the presence of air synthesizes metal nanowires. The metal can be varied to produce nanowires with different properties.... Agent: Honda/fenwick

20070059929 - Method of forming a tantalum carbon nitride layer and method of manufacturing a semiconductor device using the same: In some embodiments of the present invention, methods of forming a tantalum carbon nitride layer include introducing a source gas including a tantalum metal complex onto a substrate, wherein one or more of the ligands of the tantalum metal complex include nitrogen and one or more of the ligands of... Agent: Myers Bigel Sibley & Sajovec

20070059931 - Contact structure having silicide layers, semiconductor device employing the same, and methods of fabricating the contact structure and semiconductor device: A contact structure having silicide layers, a semiconductor device employing the same, and methods of fabricating the contact structure and semiconductor device are provided. The contact structure includes a first conductive region and a second conductive region on a substrate. An insulating layer covers the first and second conductive regions.... Agent: Mills & Onello LLP

20070059930 - Method of forming conductive metal silicides by reaction of metal with silicon: The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a nitride, boride, carbide, or oxide comprising layer is atomic layer deposited onto... Agent: Wells St. John P.s.

20070059932 - Methods of forming films in semiconductor devices with solid state reactants: A method of self-aligned silicidation involves interruption of the silicidation process prior to complete reaction of the blanket material (e.g., metal) in regions directly overlying patterned and exposed other material (e.g., silicon). Diffusion of excess blanket material from over other regions (e.g., overlying insulators) is thus prevented. Control and uniformity... Agent: Knobbe Martens Olson & Bear LLP

20070059934 - Methods of forming fine patterns, and methods of forming trench isolation layers using the same: Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the... Agent: Myers Bigel Sibley & Sajovec

20070059933 - Plasma ashing method: A plasma ashing method is used for removing a patterned resist film in a processing chamber after etching a portion of a low-k film from an object to be processed in the processing chamber by using the patterned resist film as a mask. The method includes a first step of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070059935 - Polishing method for semiconductor wafer: A polishing method includes a slurry adjusting step for adjusting a polishing slurry containing silica particles so that the number of silica particles having a composition ratio of Si/O of 50-60 wt %/40-50 wt %, a modulus of elasticity of 1.4×1010 Pa or higher and a particle size of 1... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070059936 - Electronic sensing circuit: A sensor (10) has an output coupled to a first comparator input. A control circuit (18) is arranged to switch from an upward tracking mode to a downward relative level detection mode, to a downward tracking mode, to an upward relative level detection mode and back to the upward tracking... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070059937 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device deposits a plurality of bottom antireflective coating films to prevent a standing wave caused by a light source of a short wavelength in forming a fine pattern. The method includes forming a pattern formation layer on an entire surface of a wafer, forming... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070059938 - Method and system for etching silicon oxide and silicon nitride with high selectivity relative to silicon: A method and system for etching features in a substrate, whereby silicon oxide or silicon nitride or both are etched with high selectivity relative to silicon. In one embodiment, the process chemistry utilized to achieve high selectivity includes trifluoromethane (CHF3), difluoromethane (CH2F2), an oxygen containing gas, such as O2, and... Agent: Dla Piper US LLP

20070059939 - Method of producing a conductive layer on a substrate: A method of producing a conductive layer (5) on a substrate (1) comprises depositing an insulator such as a photodefinable insulator (2) on the substrate (1), defining a groove (3) for the conductive layer (5) in the insulator material, filling the groove (3) with a precursor material and curing the... Agent: Philips Intellectual Property & Standards

20070059940 - Photosensitizer, semiconductor electrode, and photoelectric conversion device: and a photosensitizer expressed in General Formula (X) as D(m+m′)−(A+)m(A′+)m′ or in General Formula (Y) as D(m+m′+n)−(A+)m(A′+)m′(B+)n (where D has a molecular structure capable of absorbing visible light or infrared ray, A and A′ represent the guanidine derivative, and B represents an ion other than the guanidine derivative), and a... Agent: Nixon & Vanderhye, PC

20070059941 - Methods of forming patterns and capacitors for semiconductor devices using the same: A semiconductor structure may be formed by a wet etching process using an etchant containing water. The semiconductor structure may include a plurality of patterns having an increased or higher aspect ratio and may be arranged closer to one another. A dry cleaning process may be performed using hydrogen fluoride... Agent: Harness, Dickey & Pierce, P.L.C

20070059942 - Plasma cvd process for manufacturing multilayer anti-reflection coatings: A plasma chemical vapor deposition (CVD) process for the production of a multilayer anti-reflection coating on substrates (especially on substrates with curved or uneven surface) is disclosed. The CVD process utilizes free radical plasma to form the multilayer anti-reflection coating in order to achieve necessary coating thickness uniformity.... Agent: Pai Patent & Trademark Law Firm

20070059943 - Ion-assisted oxidation methods and the resulting structures: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions,... Agent: Trask Britt, P.C./ Micron Technology

20070059944 - Plasma processing method and computer storage medium: According to the present invention, when a nitridation process by plasma generated by a microwave is applied to a substrate with an oxide film having been formed thereon to form an oxynitride film, the microwave is intermittently supplied. By the intermittent supply of the microwave, ion bombardment is reduced in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070059945 - Atomic layer deposition with nitridation and oxidation: A dielectric layer is created for use with non-volatile memory and/or other devices. The dielectric layer is created using atomic layer deposition to deposit multiple components whose mole fractions change as a function of depth in the dielectric layer in order to create a rounded bottom of a conduction band... Agent: Vierra Magen/sandisk Corporation

20070059946 - Method for compensating film height modulations in spin coating of a resist film layer: A method compensates film height modulations in spin coating of a resist film layer. From a desired layout pattern, a substrate topography as a result of lithographically structuring in image fields is determined. A spin coating model is provided to determine a modeled resist film height based on the substrate... Agent: Slater & Matsil LLP

20070059947 - Method of manufacturing carbon nanotube semiconductor device: Provided is a method of controlling an alignment direction of CNTs in manufacturing a carbon nanotube semiconductor device using the CNTs for a channel region formed between a source electrode and a drain electrode. In manufacturing a carbon nanotube semiconductor device including a gate electrode, a gate insulating film, a... Agent: Nixon Peabody, LLP

20070059948 - Ald metal oxide deposition process using direct oxidation: Embodiments of the invention provide methods for forming hafnium materials, such as oxides and nitrides, by sequentially exposing a substrate to hafnium precursors and active oxygen or nitrogen species (e.g., ozone, oxygen radicals, or nitrogen radicals). The deposited hafnium materials have significantly improved uniformity when deposited by these atomic layer... Agent: Patterson & Sheridan, LLP

20070059949 - Laser irradiating apparatus and method of manufacturing semiconductor apparatus: First laser light is irradiated (energy density of 400 to 500 mj/cm2) to a semiconductor film 102 in an atmosphere containing oxygen in order to obtain a semiconductor film 102b having large depressions and projections on the surface. Then, an oxidized film 105a formed by the irradiation of the first... Agent: Eric Robinson

20070054419 - Wafer level chip size package for cmos image sensor module and manufacturing method thereof: Disclosed is a wafer level chip size package for an image sensor module and a manufacturing method thereof, more particularly to a small size image sensor module characterized by a structure where a glass formed with an I/R cut-off filter (layer) is assembled onto an image sensor chip by a... Agent: Baker & Hostetler LLP

20070054421 - Production process of structured material: Disclosed herein is a process for producing a structured material, comprising the steps of forming a film on a substrate, forming a plurality of holes in a first region of the film, forming a plurality of holes composed of a hole wall member different from a hole wall member of... Agent: Fitzpatrick Cella Harper & Scinto

20070054420 - Substrate structure and method for wideband power decoupling: A substrate structure and method of wideband power decoupling comprising one or more embedded capacitors each comprising a ferroelectric material.... Agent: Hugh R. Kress Browning Bushman P.c.

20070054423 - Method for controlling thickness distribution of a film: A method for forming an oxide film includes a first in-situ steam generation (ISSG) process using a 1%-H2 concentration in the ambient gas and a subsequent second ISSG process using a 5%-H2 concentration in the ambient gas, wherein the second ISSG process compensates an in-plane thickness distribution of the film... Agent: Young & Thompson

20070054422 - Test structure for electrically verifying the depths of trench-etching in an soi wafer, and associated working methods: The aim of the invention is to discover a simple to implement and reliable recognition of the moment at which insulation trenches reach the buried insulating layer during an etch process. The technological reliability during the etching of these trenches should be increased, the production of refuse should be prevented,... Agent: Greenblum & Bernstein, P.L.C

20070054424 - Semiconductor heating heater holder and semiconductor manufacturing apparatus: A semiconductor heater holder for setting a heater for heating a semiconductor, having an opening, wherein the heat capacity of the semiconductor heater holder is not more than 1.5 times the heat capacity of the heater, and a semiconductor manufacturing apparatus comprising this semiconductor heater holder.... Agent: Mcdermott Will & Emery LLP

20070054425 - Apparatus for measuring semiconductor physical characteristics: A reflectometry method and apparatus for gathering reflectance data indicative of one or more characteristics of a semiconductor substance being grown on a substrate within a reaction chamber. The method includes directing light of known characteristics from a light source into the reaction chamber towards the surface of the semiconductor... Agent: James D. Stevens Reising, Ethington, Barnes, Kisselle, P.c.

20070054426 - A method for preparing an optical active layer with 1~10 nm distributed silicon quantum dots: The present invention relates to a method for preparing an optical active layer with 1˜10 nm distributed silicon quantum dots, it adopts high temperature processing and atmospheric-pressure chemical vapor deposition (APCVD), and directly deposit to form a silicon nitride substrate containing 1˜10 nm distributed quantum dots, said distribution profile of... Agent: Michael Lin

20070054428 - Light-emitting device and manufacturing method thereof: A light emitting element having a superior light emitting characteristic is provided by forming a region partly including a phosphor (light emitting region) in manufacturing of a light emitting element having an organic compound layer using a high molecular weight material. A solution in which a high polymer having a... Agent: Eric Robinson

20070054427 - Terahertz radiating device based on semiconductor coupled quantum wells: A method is presented for fabricating a semiconductor device operable to generate a THz spectral range radiation in response to an external field. According to this method, a heterostructure is formed from selected layers. The layers include at least first and second semiconductor layers made of materials having a certain... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20070054429 - Back panel manufacturing process: A method for manufacturing a back panel on a substrate is provided. The substrate has at least a switching device formed therein and a dielectric layer structure formed thereon. An interconnect structure is also formed in the dielectric layer structure. The method of forming the back panel comprises the step... Agent: Jianq Chyun Intellectual Property Office

20070054430 - Method of fabricating organic electroluminescent devices: m

20070054431 - Nitride semiconductor laser element and method for manufacturing the same: A substrate with a nitride semiconductor layer is cleaved to form resonator end faces, on which a coating film is formed so as to make a nitride semiconductor laser bar. This is divided into nitride semiconductor laser elements. Prior to forming the coating film on the resonator end face, the... Agent: Harness, Dickey & Pierce, P.L.C

20070054432 - Method for producing a structure with a low aspect ratio: A method for producing a structure with a low aspect ratio is disclosed. In one embodiment, an initial structure is formed conformally within an opening in a semiconductor substrate, the opening being filled with a sacrificial structure, and the initial structure being removed outside the opening. By removing a part... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070054433 - High temperature microelectromechanical (mem) devices and fabrication method: A microelectromechanical (MEM) device per the present invention comprises a semiconductor wafer—typically an SOI wafer, a substrate, and a high temperature bond which bonds the wafer to the substrate to form a composite structure. Portions of the composite structure are patterned and etched to define stationary and movable MEM elements,... Agent: Koppel, Patrick & Heybl

20070054434 - Methods of fabricating an image sensor: Provided are methods of fabricating an image sensor. Embodiments of such methods can include forming a first gate insulation layer in a first region of a semiconductor substrate and a first gate electrode layer, to cover the first gate insulation layer and forming a second gate insulation layer within a... Agent: Myers Bigel Sibley & Sajovec

20070054435 - Process for preparation of absorption layer of solar cell: Provided is a process for preparing an absorption layer of a solar cell composed of a 1B-3A-Se compound, comprising applying a metal selenide nanoparticle as a precursor material to a base material and subjecting the applied nanoparticle to thermal processing, whereby the crystal size of the 1B-3A-Se compound can be... Agent: Cantor Colburn, LLP

20070054436 - Method of manufacturing optical film: To provide a method of manufacturing an optical film formed on a plastic substrate. There is provided a method of manufacturing an optical film including the steps of laminating a separation layer and an optical filter on a first substrate, separating the optical filter from the first substrate, attaching the... Agent: Fish & Richardson P.c.

20070054437 - Optical element and its manufacturing method: An optical element includes a substrate, a surface-emitting type semiconductor laser that emits laser light in a direction vertical to a surface of the substrate, and a light-receiving element formed above or below the surface-emitting type semiconductor laser provided above the substrate. The optical element includes a first insulation layer... Agent: Harness, Dickey & Pierce, P.L.C

20070054438 - Carrier-free semiconductor package with stand-off member and fabrication method thereof: A carrier-free semiconductor package with a stand-off member and a fabrication method thereof are proposed. A carrier with a recessed portion and a plurality of electrical contacts on a surface of the carrier is provided. At least one chip is mounted to the recessed portion of the carrier and is... Agent: Edwards & Angell, LLP

20070054439 - Multi-chip stack structure: A multi-chip stack structure includes at least one first chip having an active surface and an opposed non-active surface, wherein the active surface is formed with a plurality of connecting pads thereon; a plurality of electrical contacts formed around the first chip; an insulating layer formed on the first chip... Agent: Edwards & Angell, LLP

20070054440 - Method for fabricating a device with flexible substrate and method for stripping flexible-substrate: A method for fabricating a device with flexible substrate includes providing a rigid substrate. Then, a flexible substrate layer is directly formed on the rigid substrate, wherein the flexible substrate layer fully contacts the rigid substrate and a contact interface is formed. A device structure is formed on the flexible... Agent: J.c. Patents, Inc.

20070054443 - Method for manufacturing semiconductor device: A semiconductor device having high electrical characteristics is manufactured at low cost and with high throughput. A semiconductor film is crystallized or activated by being irradiated with a laser beam emitted from one fiber laser. Alternatively, laser beams are emitted from a plurality of fiber lasers and coupled by a... Agent: Nixon Peabody, LLP

20070054442 - Method for manufacturing thin film transistor, thin film transistor and pixel structure: A method for manufacturing a thin film transistor is provided. First, a poly-silicon island is formed on a substrate. Then, a patterned gate dielectric layer and a gate are formed on the poly-silicon island. Next, a source/drain is formed in the poly-silicon island beside the gate, wherein the region between... Agent: J C Patents, Inc.

20070054441 - Thin film transistor and manufacturing process thereof: A thin film transistor including a gate, a gate insulator layer, a channel layer, a source, a drain, and an ohmic contact layer is provided. The gate insulator layer covers the gate; the channel layer is disposed on the gate insulator layer above the gate; the source and the drain... Agent: J C Patents, Inc.

20070054444 - Manufacturing method of a semiconductor device: An amorphous layer 101 is formed in a region from a surface of a silicon substrate 100 to a first depth A. At this time, defects 103 are generated near an amorphous-crystal interface 102. By heat treatment, the crystal structure of the amorphous layer 101 is restored in a region... Agent: Mcdermott Will & Emery LLP

20070054445 - Method of manufacturing nano scale semiconductor device using nano particles: Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating... Agent: Buchanan, Ingersoll & Rooney Pc

20070054447 - Multistep etching method: A multi-step etching method is provided. First, a substrate including a gate over the substrate and a spacer over the gate is provided. Then, an anisotropic etching step is performed for etching a first region and a second region in the substrate at two sides of the gate. Thereafter, an... Agent: J C Patents, Inc.

20070054446 - Work function control of metals: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the... Agent: Texas Instruments Incorporated

20070054448 - Nonvolatile memory device having multi-bit storage and method of manufacturing the same: Provided are a nonvolatile memory device having multi bit storage and a method of manufacturing the same. The method includes forming a tunneling dielectric layer, a charge storage layer and a charge blocking layer on a fin-active region, forming sacrificial patterns having a groove to open a crossing region of... Agent: Mills & Onello LLP

20070054449 - Methods of forming charge-trapping dielectric layers for semiconductor memory devices: Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer;... Agent: Akin Gump Strauss Hauer & Feld L.l.p.

20070054451 - Semiconductor device and method for manufacturing the same: The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070054452 - Source side injection storage device with spacer gates and method therefor: A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates... Agent: Freescale Semiconductor, Inc. Law Department

20070054450 - Structure and fabrication of an mram cell: MTJ stacks formed using prior art processes often fail because of shorts between the pinned layer and the top electrode. This problem has been overcome by depositing a protective layer on the MTJ sidewalls followed by an inter-layer dielectric. Then planarizing until the protective layer is just exposed. Finally, an... Agent: George O. Saile

20070054453 - Methods of forming integrated circuit memory devices having a charge storing layer formed by plasma doping: Methods of forming an integrated circuit memory device include forming a dielectric layer on a substrate and forming a charge storing layer on an upper surface of the dielectric layer using a plasma doping process with a remaining portion of the dielectric layer under the charge storing layer defining a... Agent: Myers Bigel Sibley & Sajovec

20070054454 - Semiconductor device and programming method therefor: A semiconductor device includes bit line's (14) provided in a semiconductor substrate (10), word lines (16) provided above the bit lines and running in a width direction of the bit lines (14), metal lines (22) provided above the word lines (16) and running in a length direction of the bit... Agent: Ingrassia Fisher & Lorenz, P.c.

20070054455 - Method to obtain uniform nitrogen profile in gate dielectrics: The present invention provides, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the... Agent: Texas Instruments Incorporated

20070054456 - Semiconductor device and method for fabricating the same: A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage... Agent: Mcdermott Will & Emery LLP

20070054457 - Method of fabricating mos transistor having epitaxial region: Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an... Agent: Harness, Dickey & Pierce, P.L.C

20070054458 - Method of fabricating spacers and cleaning method of post-etching and semiconductor device: A method of fabricating spacers is provided. The method includes providing a substrate with a device structure formed thereon. The device structure comprises a gate structure and a pair of source/drain regions. Then, a spacer material layer is formed over the substrate to cover the substrate and the device structure.... Agent: J C Patents, Inc.

20070054459 - Soi wafer and method for producing the same: The present invention provides a SOI wafer produced by an ion implantation delamination method wherein a width of a SOI island region in a terrace portion generated in an edge portion of the SOI wafer where a surface of a base wafer is exposed is narrower than 1 mm and... Agent: Oliff & Berridge, Plc

20070054460 - System and method for providing a nanoscale, highly selective, and thermally resilient silicon, germanium, or silicon-germanium etch-stop: A method and resulting etch-stop layer comprising a silicon-germanium layer and a dopant layer within the silicon-germanium layer. The silicon-germanium layer is comprised of less than about 70% germanium and contains one or more dopant elements selected from the group consisting of boron and carbon. The dopant layer has one... Agent: Schneck & Schneck

20070054461 - Trench capacitor and method for manufacturing the same: A structure of a trench capacitor and method for manufacturing the same. The method includes providing a substrate having a defined memory area and logic area, and performing an STI process to form at least one STI region on the memory area of the substrate and at least one STI... Agent: North America Intellectual Property Corporation

20070054462 - Semiconductor device including direct contact between capacitor electrode and contact plug and method of manufacturing the same: A semiconductor device comprises an insulation film that is provided on a semiconductor substrate, a first contact plug that is provided in the insulation film and includes a metal, a first adhesive film that is provided on the insulation film, has a higher oxygen affinity than the metal, and includes... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.c.

20070054463 - Method for forming spacers between bitlines in virtual ground memory array and related structure: According to one exemplary embodiment, a method of fabricating a virtual ground memory array, which includes bitlines situated in a substrate, includes forming at least one recess in the substrate between two adjacent bitlines, where the at least one recess is situated in a bitline contact region of the virtual... Agent: Farjami & Farjami LLP

20070054464 - Different sti depth for ron improvement for ldmos integration with submicron devices: An integrated circuit device having deeper STI trenches for device isolation and shallower STI trenches at the gate edge for low on-resistance and a method for forming the same are described. The integrated circuit device of the invention comprises a gate electrode on a gate dielectric layer overlying a substrate,... Agent: Ishimaru & Zahrt LLP

20070054465 - Lattice-mismatched semiconductor structures on insulators: Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.... Agent: Goodwin Procter LLP Patent Administrator

20070054466 - Semiconductor-on-insulator type heterostructure and method of fabrication: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer.... Agent: Winston & Strawn LLP Patent Department

20070054467 - Methods for integrating lattice-mismatched semiconductor structure on insulators: Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.... Agent: Goodwin Procter LLP Patent Administrator

20070054468 - Method for producing silicon epitaxial wafer: For a silicon single crystal substrate PW to which boron, arsenic or phosphorus is added as a dopant in a concentration of 1×1019/cm3 or more and in which a CVD oxide film 1 is formed on a rear surface, wet etching of an oxide film on a main surface of... Agent: Oliff & Berridge, Plc

20070054470 - Method for thinning substrate and method for manufacturing circuit device: The supporting plate 1 and the substrate W are joined by using an adhesive layer 2, and a sheet 6 is attached to the supporting plate 1. The surface of the supporting plate 1 to which the sheet 6 has been attached is mounted and fixed by attraction onto an... Agent: Carrier Blackman And Associates

20070054469 - Pressure-sensitive adhesive sheet and method of processing articles: To provide a pressure-sensitive adhesive sheet, which is used in processing an article such as a semiconductor wafer, the pressure-sensitive adhesive sheet has a base, an intermediate layer and a pressure-sensitive adhesive layer in this order, wherein the intermediate layer has an elastic modulus in tension at 23° C. of... Agent: Frishauf, Holtz, Goodman & Chick, Pc

20070054471 - Alignment mark and method of forming the same: An alignment mark is fabricated containing a mark portion and a trench structure. The trench structure surrounds the mark portion and is at a distance from the mark portion. The mark portion has a plurality of notches. Due to the erosion effect caused by the trench structure, it can prevent... Agent: Jianq Chyun Intellectual Property Office

20070054472 - Apparatus for preparing oxide thin film and method for preparing the same: An oxide thin film having good characteristic properties is prepared by reducing an occurrence of an oxygen defect of the resulting oxide thin film and promoting the epitaxial growth of the film. The oxide thin film is prepared by admixing a raw gas, a carrier gas and an oxidation gas... Agent: Arent Fox Pllc

20070054473 - Method of semiconductor thin film crystallization and semiconductor device fabrication: A method for fabricating a semiconductor device includes providing a substrate, forming an amorphous silicon layer over the substrate, forming a heat retaining layer on the amorphous silicon layer, patterning the heat retaining layer, and irradiating the patterned heat retaining layer.... Agent: Akin Gump Strauss Hauer & Feld L.l.p.

20070054474 - Crack-free iii-v epitaxy on germanium on insulator (goi) substrates: A method of forming III-V epitaxy on a germanium-on-insulator (GOI) substrate having a bonded layer and a handle substrate begins with measuring a lattice parameter of the bonded layer at a first temperature. The lattice parameter of the bonded layer, which is a function of a coefficient of thermal expansion... Agent: Freescale Semiconductor, Inc. Law Department

20070054475 - Method of forming a phase changeable material layer, a method of manufacturing a phase changeable memory unit, and a method of manufacturing a phase changeable semiconductor memory device: A phase changeable material layer usable in a semiconductor memory device and a method of forming the same are disclosed. The method includes forming a plasma in a chamber having a substrate disposed therein, providing a first source gas including a germanium based material to form a first layer including... Agent: Stanzione & Kim, LLP

20070054476 - Method of producing a nitride semiconductor device and nitride semiconductor device: AlxInyGa1-x-yN (0≦x≦1; 0≦x≦1; 0≦x+y≦1) layered device chips are produced by the steps of preparing a defect position controlled substrate of AlxInyGa1-x-yN (0≦x≦1; 0≦y≦1; 0≦x+y≦1) having a closed loop network defect accumulating region H of slow speed growth and low defect density regions ZY of high speed growth enclosed by the... Agent: Mcdermott Will & Emery LLP

20070054479 - Laser irradiation device: In annealing a non-single crystal silicon film through the use of a linear laser beam emitted by a YAG laser of a light source, it is the object of the present invention to prevent heterogeneity in energy caused by an optical interference produced in the linear laser beam from having... Agent: Eric Robinson

20070054477 - Method of forming polycrystalline silicon thin film and method of manufacturing thin film transistor using the method: Provided are a method of forming a polycrystalline silicon thin film with improved electrical characteristics and a method of manufacturing a thin film transistor using the method of forming the polycrystalline silicon thin film. The method includes forming an amorphous silicon thin film on a substrate, partially melting a portion... Agent: Macpherson Kwok Chen & Heid LLP

20070054478 - Method of forming polysilicon film using a laser annealing apparatus: An excimer laser annealing apparatus and the application of the same for stabilizing the atmosphere surrounding an area irradiated by an excimer laser. The apparatus includes a chamber, a gas diversion nozzle, an excimer laser and a gas supply device. The gas diversion nozzle is positioned inside the chamber. The... Agent: Jianq Chyun Intellectual Property Office

20070054480 - Anti-halo compensation: An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length. The method includes doping a short channel device and a long channel device with a first dopant, and doping the short channel device and the long channel... Agent: Greenblum & Bernstein, P.L.C

20070054481 - Semiconductor device having nickel silicide and method of fabricating nickel silicide: A semiconductor device having nickel suicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the... Agent: North America Intellectual Property Corporation

20070054482 - Semiconductor device fabrication method: According to one aspect of the invention, there is provided a semiconductor device fabrication method having: forming a film on a semiconductor substrate; forming a mask comprising a predetermined pattern on the film; etching one of the film and the semiconductor substrate by using the mask; and performing at least... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070054483 - Integrated die bumping process: An integrated die bumping process includes providing a load board, defining a plurality of die regions on a surface of the load board for placing dice of a plurality of die specifications, affixing a plurality of dice respectively on the die regions according to the plurality of die specifications, and... Agent: North America Intellectual Property Corporation

20070054484 - Method for fabricating semiconductor packages: A method for positioning a semiconductor component is disclosed. The method includes providing the semiconductor component and a carrier, the carrier having a plurality of openings, a protruded portion being provided at each corner position of each of the openings and extended toward a center of the opening, a distance... Agent: Ishimaru & Zahrt LLP

20070054485 - Integration control and reliability enhancement of interconnect air cavities: An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material is introduced on the edges of interconnect lines and vias within an interconnect stack. This incorporates and controls air cavities formation, thus enhancing the signal propagation performance... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20070054486 - Method for forming opening: A method for forming an opening. The method comprises steps of providing a substrate having at least one element structure formed thereon and then forming a dielectric layer over the substrate to cover the element structure. A patterned metal silicide layer is formed on the dielectric layer and then the... Agent: Jianq Chyun Intellectual Property Office

20070054487 - Atomic layer deposition processes for ruthenium materials: Embodiments of the invention provide a method for depositing ruthenium materials on a substrate by various vapor deposition processes, such as atomic layer deposition (ALD) and plasma-enhanced ALD (PE-ALD). In one aspect, the process has little or no initiation delay and maintains a fast deposition rate while forming a ruthenium... Agent: Patterson & Sheridan, LLP

20070054489 - Interconnect structures with encasing cap and methods of making thereof: A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.... Agent: Connolly Bove Lodge & Hutz LLP Suite 800

20070054488 - Low resistance and reliable copper interconnects by variable doping: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a... Agent: Duane Morris, LLP Ip Department

20070054493 - Methods of forming patterns using phase change material and methods for removing the same: In a method of forming patterns using a phase change material layer a phase change material layer may be formed, and selectively phase-changed along a pattern using an exposure beam or other heat source. A phase change material layer pattern may be formed by selectively removing phase-changed portions using a... Agent: Harness, Dickey & Pierce, P.L.C

20070054492 - Photoreactive removal of ion implanted resist: A method for removing ion implanted photoresist from a surface of a substrate is provided. The method may include introducing a gas to a reaction chamber containing the substrate; illuminating the ion implanted photoresist with radiation from a laser in the presence of the gas; and scanning the radiation across... Agent: Harrity Snyder, LLP

20070054490 - Semiconductor process for preventing layer peeling in wafer edge area and method for manufacturing interconnects: A semiconductor process for preventing the layer on a wafer edge from peeling is provided. First, a dielectric layer is formed on the front side of a substrate. Then, a photoresist layer is formed to cover the front side and part of the backside of the substrate. Thereafter, an edge... Agent: J C Patents, Inc.

20070054491 - Wafer cleaning process: The invention is directed to a wafer cleaning process for being applied on a wafer after an etching process is performed on the wafer, wherein the wafer has a wafer center, a wafer radius and a wafer circumference. The wafer cleaning process comprises a step of dispensing a cleaning solution... Agent: J C Patents, Inc.

20070054494 - Method for planarizing semiconductor structures: A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first... Agent: Howard Chen Preston Gates & Ellis LLP

20070054495 - Cmp composition of boron surface-modified abrasive and nitro-substituted sulfonic acid and method of use: A composition and associated method for chemical mechanical planarization (or other polishing) are described. The composition contains a boron surface-modified abrasive, a nitro-substituted sulfonic acid compound, a per-compound oxidizing agent, and water. The composition affords high removal rates for barrier layer materials in metal CMP processes. The composition is particularly... Agent: Air Products And Chemicals, Inc. Patent Department

20070054496 - Gas mixture for removing photoresist and post etch residue from low-k dielectric material and method of use thereof: Atomic oxygen generated in oxygen stripping plasmas reacts with and damages low-k dielectric materials during stripping of dielectric post etch residues. While damage of low-k dielectric materials during stripping of dielectric post etch residues is lower with hydrogen stripping plasmas, hydrogen stripping plasmas exhibit lower strip rates. Inclusion of oxygen... Agent: Buchanan, Ingersoll & Rooney Pc

20070054498 - Method for applying resin film to face of semiconductor wafer: A method for applying a resin film to the face of a semiconductor wafer, comprising: an assembly holding step of holding an assembly on the surface of chuck means, with the back of the assembly being opposed to the surface of the chuck means, the assembly including a frame having... Agent: Smith, Gambrell & Russell

20070054497 - Method for preventing contamination and lithographic device: The invention relates to a method for preventing contamination of the surfaces of reflective optical elements for the soft X-ray and EUV wavelength range during their irradiation at operating wavelength in an evacuated closed system having a residual gas atmosphere, said elements comprising a cover layer consisting of at least... Agent: Hudak Shunk & Farine Co

20070054499 - Apparatus and method for forming polycrystalline silicon thin film: Apparatus and method for forming a polycrystalline silicon thin film by converting an amorphous silicon thin film into the polycrystalline silicon thin film using a metal are provided. The method includes: a metal nucleus adsorbing step of introducing a vapor phase metal compound into a process space where the glass... Agent: Ditthavong Mori & Steiner, P.c.

20070054500 - Removable amorphous carbon cmp stop: A method is provided for processing a substrate including removing amorphous carbon material disposed on a low k dielectric material with minimal or reduced defect formation and minimal dielectric constant change of the low k dielectric material. In one aspect, the invention provides a method for processing a substrate including... Agent: Patterson & Sheridan, LLP

20070054501 - Process for modifying dielectric materials: The invention relates to a process for modifying materials including, e.g., dielectric materials associated with electronic substrates, semiconductor chips, wafers, and the like, damaged by fabrication processes such as plasma etch processing. The described method improves structural integrity as measured, e.g., by Young's Modulus, as well as hydrophobicity, as measured,... Agent: Battelle Memorial Institute Attn: Ip Services, K1-53

20070054502 - Nanodot memory and fabrication method thereof: A nanodot memory formed by applying a nanodot colloid solution on a semiconductor substrate to more uniformly arranging nanodot particles with a size of several nanometers on the semiconductor substrate and a fabrication method thereof are provided. In the nanodot memory fabrication method, a first insulating film may be formed... Agent: Harness, Dickey & Pierce, P.L.C

20070054503 - Film forming method and fabrication process of semiconductor device: A method of forming a film on a substrate includes a first step of carrying out first film formation on an insulation layer formed on the substrate by an ALD process, and a second step of carrying out second film formation in continuation to the first step by a CVD... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.c.

20070054504 - Post deposition plasma treatment to increase tensile stress of hdp-cvd sio2: A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and... Agent: Patent Counsel, M/s 2061 Applied Materials, Inc.

20070054506 - Grooved substrates for uniform underfilling solder ball assembled electronic devices: A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A metallic bump (304) made of reflowable metal is attached to each of these contact pads. An electrically insulating substrate (305) has a surface with a... Agent: Texas Instruments Incorporated

20070054505 - Pecvd processes for silicon dioxide films: Embodiments of the present invention provide PECVD (plasma enhanced chemical vapor deposition) processes that produce uniform, dense SiO2 (silicon dioxide) films having a high purity that are suitable for use in IC device fabrication. Advantageously, these processes do not require the use of a DC bias or dual frequency RF... Agent: Blakely Sokoloff Taylor & Zafman

20070054507 - Method of fabricating oxide semiconductor device: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.... Agent: Fitzpatrick Cella Harper & Scinto

20070048879 - Integrated circuit chip utilizing oriented carbon nanotube conductive layers: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070048880 - Capacitor, method of manufacturing the same, method of manufacturing ferroelectric memory device, method of manufacturing actuator, and method of manufacturing liquid jet head: A method of manufacturing a capacitor, including: forming a lower electrode on a substrate; forming a dielectric film of a ferroelectric or a piezoelectric on the lower electrode; forming an upper electrode on the dielectric film; and forming a silicon oxide film so that at least the dielectric film is... Agent: Harness, Dickey & Pierce, P.L.C

20070048881 - Memory device transistors: Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070048882 - Method to reduce plasma-induced charging damage: In some implementations, a method is provided for inhibiting charge damage in a plasma processing chamber during a process transition from one process step to another process step, including performing a pre-transition compensation of at least one process parameter so as to inhibit charge damage from occurring during the process... Agent: Aagaard & Balzan, LLP

20070048883 - Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device: By measuring an electric characteristic of a test pad that is connected to a plurality of test vias formed in accordance with a specified process flow for forming contacts and vias of a semiconductor device, one or more process specific parameters may quantitatively be estimated. Thus, a fast and precise... Agent: Williams, Morgan & Amerson

20070048884 - Method and apparatus for localizing production errors in a semiconductor component part: The invention relates to a method and to an arrangement for localizing production errors in a semiconductor component part by generating excess charge carriers in the semiconductor component part and by determining the electric potential in said part. In order to be able to localize production errors with simple measures... Agent: Dennison, Schultz & Macdonald

20070048885 - Thin film led: A method of fabricating a light emitting diode (LED) includes providing an LED chip that emits light having a first wavelength where the LED chip includes a first electrical contact and a second electrical contact. The method further includes forming a tinted thin film layer over the LED chip where... Agent: Mckenna Long & Aldridge LLP

20070048886 - Electrical connection in oled devices: A method of making an OLED device, including providing a substrate having a first electrode and a conductive bus line provided over the substrate and organic EL media provided over the first electrode and over the conductive bus line; forming a radiation absorbing structure associated with the conductive bus line;... Agent: Pamela R. Crocker Patent Legal Staff

20070048888 - Electrical contact for a mems device and method of making: A method for making a subsurface electrical contact on a micro-electrical-mechanical-systems (MEMS) device. The contact is formed by depositing a layer of polycrystalline silicon onto a surface within a cavity buried under a device silicon layer. The polycrystalline silicon layer is deposited in the cavity through holes etched through the... Agent: Delphi Technologies, Inc.

20070048887 - Wafer level hermetic bond using metal alloy: Systems and methods for forming an encapsulated MEMS device include a hermetic seal which seals an insulating gas between two substrates, one of which supports the MEMS device. The hermetic seal may be formed by heating at least two metal layers, in order to melt at least one of the... Agent: Jaquelin K. Spong

20070048889 - Method of forming a piezoresistive device capable of selecting standards and method of forming a circuit layout capable of selecting sub-circuit layouts: A wafer is provided, and a circuit layout including a first piezoresistive device layout and a second piezoresistive device layout is formed on the front surface of the wafer. The first piezoresistive device layout includes a plurality of first nodes and the second piezoresistive device layout includes a plurality of... Agent: North America Intellectual Property Corporation

20070048890 - Semiconductor device fabrication method and semiconductor device: A semiconductor device fabrication method in which when a semiconductor device with a built-in light receiving element is fabricated, a section for dividing the light receiving element is protected from damage caused by, for example, etching. An antireflection coating is formed not only on a light receiving area in a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070048891 - Device transferring method, and device arraying method: A method of selectively transferring devices arrayed on a first substrate to a second substrate on which an adhesive resin layer is previously formed is provided. The method includes steps of selectively heating the adhesive resin layer on the second substrate by laser irradiation from the back surface side of... Agent: Bell, Boyd & Lloyd, LLC

20070048892 - Encapsulating electrode: An organic photosensitive optoelectronic device is formed in which the organic photoconductive materials are encapsulated by an electrode of the device. A first transparent film is provided that comprises a first electrically conductive material, arranged on a transparent substrate. A first photoconductive organic material is deposited over the first electrically... Agent: Stuart J Sinder Kenyon & Kenyon

20070048893 - Laser induced thermal imaging apparatus and fabricating method of organic light emitting diode using the same: A laser induced thermal imaging apparatus and a fabricating method of organic light emitting diodes using the same, which laminate an acceptor substrate and a donor film using a magnetic force in vacuum, and are used to form a pixel array on the acceptor substrate. A substrate stage includes a... Agent: Christie, Parker & Hale, LLP

20070048895 - Method of manufacturing an organic electronic device: An organic electronic device using an extremely thin substrate is manufactured by a simple and easy method. That is, according to the method of manufacturing the organic electronic device of the present invention, a first surface of a substrate is subjected to polishing, a protective layer is provided on the... Agent: Bruce L. Adams, Esq.

20070048894 - System and method for reduced material pileup: An embodiment of the invention pertains to a two stage process that facilitates the formation of a substantially uniform layer. A material is isotropically deposited on a re-entry shaped surface topography and a substrate resulting in a non-wetting film on the re-entry shaped surface topography and the substrate. Regions of... Agent: Fish & Richardson P.C.

20070048896 - Conductive through via structure and process for electronic device carriers: Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon... Agent: John A. Jordan, Esq.

20070048897 - Method and apparatus for depositing conductive paste in circuitized substrate openings: A method and apparatus for depositing conductive paste in openings of a circuitized substrate such as a multilayered printed circuit board to produce effective conductive thru-holes capable of being electrically coupled to selected conductive layers of the substrate. The invention comprises using vacuum to draw from the underside of the... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20070048900 - Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of underfilling microelectronic devices: Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of disposing underfill including electrically charged filler elements on microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a microelectronic component, a plurality of electrical couplers carried by... Agent: Perkins Coie LLP Patent-sea

20070048898 - Wafer level hermetic bond using metal alloy with raised feature: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the... Agent: Jaquelin K. Spong

20070048899 - Wafer level package and method for making the same: The present invention relates to a wafer level package and method for making the same. The method of the invention comprises: (a) providing a metal layer, the metal layer having a first surface and a second surface; (b) forming a plurality of first caves and a plurality of second caves... Agent: Volentine Francos, & Whitt PLLC

20070048902 - Microfeature workpieces, carriers, and associated methods: Microfeature workpieces, carriers, and associated methods are disclosed. In a particular embodiment, one method for processing a microfeature workpiece can include temporarily attaching the microfeature workpiece to a carrier with a releasable connector, wherein the connector is at least partially metallic. The method can further include performing a manufacturing process... Agent: Perkins Coie LLP Patent-sea

20070048903 - Multi-chip package type semiconductor device: A multi-chip package type semiconductor device includes an insulating substrate having first and second conductive patterns thereon, a first semiconductor chip on the insulating substrate and having a first terminal pad and a relay pad isolated from the first terminal pad. The device further includes a second semiconductor chip on... Agent: Junichi Mimura Oki America Inc.

20070048904 - Radiant energy heating for die attach: Methods and systems for attaching a chip to a next level package by directing radiant energy at the chip back side while substantially preventing irradiation of the next level package are described.... Agent: Cyndi M. Wheeler Blakely, Sokoloff, Taylor & Zafman LLP

20070048901 - Wafer-level package and ic module assembly method for the wafer-level package: A wafer-level package and an IC module assembly method for a wafer-level package are provided in the present invention. The method comprises forming a metal bump on a wafer, applying a high polymer resin coating to the wafer, grinding a surface of the resin coating, printing an endpoint on the... Agent: Hershkovitz & Associates

20070048905 - Method for encapsulating a component, especially an electric or electronic component, by means of an improved solder seam: A method for encapsulating a component by using a chamber in which there is a vacuum or controlled atmosphere, positioning a continuous sealing seam made of a metal or a metal alloy on a wettable surface previously placed on a substrate including at least one component and extending around the... Agent: Burr & Brown

20070048908 - Method and apparatus for fabricating a carbon nanotube transistor: A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least... Agent: Moser, Patterson & Sheridan, LLP

20070048906 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is disclosed in which a doping depth of an ion implanted dopant is prevented from being increased during annealing, so as to form a junction having a depth of 20 nm or below without any problem in the technology of 65 nm or... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070048907 - Methods of forming nmos/pmos transistors with source/drains including strained materials and devices so formed: A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a <100> crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.... Agent: Myers Bigel Sibley & Sajovec

20070048909 - Superjunction device with improved ruggedness: An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension... Agent: Ostrolenk Faber Gerb & Soffen

20070048910 - Method for manufacturing thin film transistor array panel for display device: A gate wire including gate lines, gate electrodes, and gate pads and extending in a transverse direction is formed on a substrate. A gate insulating layer is formed thereafter, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. A conductive material is deposited and patterned to... Agent: Macpherson Kwok Chen & Heid LLP

20070048911 - Etching tape and method of fabricating array substrate for liquid crystal display using the same: A method of fabricating a liquid crystal display array substrate includes forming a gate wiring line having a gate pad electrode, forming a data wiring line having a data pad electrode, forming a protection layer over the gate pad electrode and the data pad electrode, and positioning etching tapes on... Agent: Jenkens & Gilchrist, P.C.

20070048912 - Method of forming single crystalline silicon layer, structure including the same, and method of fabricating thin film transistor using the same: Provided are a method of forming a single crystalline silicon layer, a structure including the same, and method of fabricating a thin film transistor (“TFT”) using the same. The method of forming the single crystalline silicon layer includes forming a silicon nitride layer on a substrate, forming an insulating layer... Agent: Cantor Colburn, LLP

20070048913 - Method of manufacturing a stacked semiconductor device: In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern having a first opening may be formed on the seed layer. A first SEG process may be carried out to form a first plug partially filling the... Agent: Harness, Dickey & Pierce, P.L.C

20070048914 - Method of fabricating dual gate electrode of cmos semiconductor device: In an embodiment, a method of fabricating a dual gate electrode includes forming an initial semiconductor layer doped with impurities of a first conductivity type on a semiconductor substrate having a first region and a second region. The initial semiconductor layer of the second region is partially etched to form... Agent: Marger Johnson & Mccollom, P.C.

20070048915 - Method for forming a thin film transistor: A method for forming a thin film transistor. A buffer layer is formed on a substrate. A single crystal layer is formed on the buffer layer. An amorphous layer is formed on the single crystal layer. The amorphous layer is transferred to a crystallized layer by laser annealing. A gate... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070048918 - Method for fabricating electronic device: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the... Agent: Mcdermott Will & Emery LLP

20070048916 - Method for fabricating semiconductor device: The method for fabricating a semiconductor device comprises the steps of: forming on a silicon substrate 10 a hard mask 20 of a silicon oxide film 12, and a silicon nitride film 14 having a width smaller than a width of the silicon oxide film 12; etching the silicon substrate... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070048917 - Process for producing semiconductor integrated circuit device: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W... Agent: Miles & Stockbridge PC

20070048921 - Method for manufacturing semiconductor device: A method of manufacturing a semiconductor device includes performing a first etching process on a gate electrode layer to form a gate electrode of a first transistor group including a transistor pair, and performing a second etching process different from the first etching on the gate electrode layer to form... Agent: Foley And Lardner LLP Suite 500

20070048920 - Methods for dual metal gate cmos integration: Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask layer may be deposited on the first metal layer and subsequently etch. The first metal layer is then etched. Without... Agent: Fulbright & Jaworski L.L.P.

20070048919 - Modified hybrid orientation technology: A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122)... Agent: Hamilton & Terrile, LLP

20070048923 - Flash memory with low tunnel barrier interpoly insulators: Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070048922 - Nand flash memory devices and methods of fabricating the same: A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on... Agent: Harness, Dickey & Pierce, P.L.C

20070048924 - Method of fabricating nonvolatile memory device: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to... Agent: Lee & Morse, P.C.

20070048925 - Body-contacted silicon on insulation (soi) field effect transistors: An apparatus and method for reducing resistance under a body contact region. The method comprises providing a substrate including a gate structure comprising an active region and a contact body region. The method also includes forming a first impurity region under the contact body region at a higher dose than... Agent: Greenblum & Bernstein, P.L.C

20070048926 - Lanthanum aluminum oxynitride dielectric films: Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of electronic systems. The lanthanum aluminum oxynitride film may be structured as one or more monolayers. The lanthanum aluminum oxynitride film may be formed by atomic layer... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070048927 - Shallow trench isolation by atomic-level silicon reconstruction: Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidewall surface, prior to performing oxidation, by reconstructing silicon atoms... Agent: Dickstein Shapiro LLP

20070048928 - Method in the fabrication of a monolithically integrated vertical device on an soi substrate: A method in the fabrication of a monolithically integrated vertical device on an SOI substrate comprises the steps of providing an SOI substrate including, from bottom to top, a silicon bulk material, an insulating layer, and an monocrystalline silicon layer; forming an opening in the substrate, which extends into the... Agent: Maginot, Moore & Beck Bank One Tower

20070048929 - Semiconductor device with dielectric structure and method for fabricating the same: A semiconductor device with a dielectric structure and a method for fabricating the same are provided. A capacitor in the semiconductor device includes: a bottom electrode formed on a substrate; a first dielectric layer made of titanium dioxide (TiO2) in rutile phase and formed on the bottom electrode; and an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070048930 - Peripheral gate stacks and recessed array gates: Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within... Agent: Knobbe Martens Olson & Bear LLP

20070048931 - Semiconductor device and its manufacture method: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070048932 - Semiconductor constructions comprising conductive structures, and methods of forming conductive structures: The invention includes methods of forming pluralities of electrically conductive structures. The methods can include formation of a gradient-containing material across a substrate and in direct physical contact with conductive surfaces of nodes. The gradient-containing material can consist essentially of tantalum nitride at a lowermost portion in contact with the... Agent: Wells St. John P.s.

20070048933 - Semiconductor device manufacturing method: Provided is a semiconductor device manufacturing method including the steps of: forming an n-type impurity diffusion region by ion-implanting arsenic into a capacitor formation region of a silicon substrate under a condition that a beam current is not less than 1 μA but less than 3 mA; forming a capacitor... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070048934 - Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions: Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a... Agent: Harness, Dickey & Pierce, P.L.C

20070048940 - Dense non-volatile memory array and method of fabrication: A non-volatile memory array has word lines spaced a sub-F (sub-minimum feature size F) width apart and bit lines generally perpendicular to the word lines. The present invention also includes a method for word-line patterning of a non-volatile memory array which includes generating sub-F word lines from mask generated elements... Agent: Tiajoloff & Kelly

20070048935 - Flash memory with recessed floating gate: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected... Agent: Knobbe Martens Olson & Bear LLP

20070048936 - Method for forming memory cell and periphery circuits: A method for forming a memory cell and periphery circuit includes providing a substrate with a peripheral circuit region and a memory cell region. A mask layer is formed on the substrate to define multiple active regions in the peripheral circuit region and to define multiple channel regions in the... Agent: J C Patents, Inc.

20070048937 - Method of fabricating non-volatile memory: A method of fabricating a non-volatile memory is provided. A substrate having a memory cell area and a peripheral circuit area is provided. A plurality of device isolation structures is formed in the substrate. A tunneling dielectric layer is formed on the substrate in the memory cell area and a... Agent: Jianq Chyun Intellectual Property Office

20070048938 - Method of manufacturing mos transistor with multiple channel structure: A method of manufacturing a MOS transistor with a multiple channel structure prevents damage to and loss of material of a channel region. The method includes: forming a stacked structure including a plurality of first material layers and a plurality of second material layers that have different etching selectivities and... Agent: Mills & Onello LLP

20070048939 - Single-poly eprom device and method of manufacturing: The invention relates to a single-poly EPROM comprising a source, a drain, a control gate, a floating gate and an additional gate. The control gate is positioned laterally of a channel between the source and the drain. The floating gate is positioned above the channel above the control gate. The... Agent: Texas Instruments Incorporated

20070048941 - Transistor gate forming methods and transistor structures: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within... Agent: Wells St. John P.s.

20070048942 - Methods of forming field effect transistors on substrates: The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and... Agent: Wells St. John P.s.

20070048943 - Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.... Agent: Dickstein Shapiro LLP

20070048944 - Low voltage trigger and save area electrostatic discharge device: Techniques for ESD protection are provided. An ESD protection device includes a first well region and a second well region disposed in a semiconductor substrate, with an isolation region therebetween. N+ implant regions are disposed in the second well region and are coupled in common at a first node. NLDD... Agent: Townsend And Townsend And Crew, LLP

20070048945 - Memory device and method of making same: A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a substantially planar first area of electrical communication with the phase-change material. The radial memory device also includes a second electrode in electrical communication with the phase-change material,... Agent: Rader, Fishman & Grauer PLLC

20070048947 - Multi-structured si-fin and method of manufacture: Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction... Agent: Harness, Dickey & Pierce, P.L.C

20070048946 - Transistor gate forming methods and integrated circuits: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited... Agent: Wells St. John P.s.

20070048948 - Apparatus and method for non-contact assessment of a constituent in semiconductor substrates: Methods and apparatus for assessing a constituent in a semiconductor substrate. Several embodiments of the invention are directed toward non-contact methods and systems for identifying an atom specie of a dopant implanted into the semiconductor substrate using techniques that do not mechanically contact the substrate with electrical leads or other... Agent: Perkins Coie LLP Patent-sea

20070048949 - Process of manufacturing semiconductor device: The present invention aims to suppress etching damage without increasing a chip area of a semiconductor device. An integrated circuit including a MOS transistor is formed in a device area, and a discharge diffusion region is formed in a grid area. The discharge diffusion region is connected to a metal... Agent: Volentine Francos, & Whitt PLLC

20070048950 - Magnetic devices and techniques for formation thereof: Techniques for forming a magnetic device are provided. In one aspect, a method of forming a via hole self-aligned with a magnetic device comprises the following steps. A dielectric layer is formed over at least a portion of the magnetic device. The dielectric layer is configured to have an underlayer... Agent: Ryan, Mason & Lewis, LLP

20070048951 - Method for production of semiconductor memory devices: Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks.... Agent: Slater & Matsil LLP

20070048952 - Method to manufacture ldmos transistors with improved threshold voltage control: A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant... Agent: Texas Instruments Incorporated

20070048953 - Graded dielectric layers: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment,... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070048954 - Method for etching and apparatus for etching: A method of etching for forming a groove in a SOI substrate includes a forming step, in which a mixed gas plasma is formed by using a mixed gas of a fluorinate gas and an oxygenic gas, and an applying step, in which a high-frequency bias is intermittently applied to... Agent: Posz Law Group, PLC

20070048955 - Method for enhancing electrode surface area in dram cell capacitors: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode,... Agent: Whyte Hirschboeck Dudek S.c.

20070048956 - Interrupted deposition process for selective deposition of si-containing films: A method is provided for selectively forming a Si-containing film on a substrate in an interrupted deposition process. The method includes providing a substrate containing a growth surface and a non-growth surface, and selectively forming the Si-containing film on the growth surface by exposing the substrate to HX gas while... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070048957 - Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device: In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device includes forming the charge-trapping dielectric, and a first oxide layer including silicon oxide. A silicon nitride layer including silicon-rich nitride is formed by a cyclic chemical vapor deposition (CVD) process using a silicon... Agent: Marger Johnson & Mccollom, P.C.

20070048958 - Three-dimensional multi-gate device and fabricating method thereof: A three-dimensional multi-gate device has a silicon fin, a gate structure, and a stress-adjusting layer. The gate structure contacts with three surface of the silicon fin to form a three-dimensional gate structure. The stress-adjusting layer is disposed on the gate structure to provide stress along the direction parallel to the... Agent: North America Intellectual Property Corporation

20070048959 - Registration mark within an overlap of dopant regions: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO... Agent: Schneck & Schneck

20070048960 - Resistor integration structure and technique for noise elimination: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW... Agent: Texas Instruments Incorporated

20070048961 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof are provided. In the fabricating method, two trenches are formed in the substrate and, then the first dielectric layers is formed on the sidewalls of the trenches and a source/drain layer is formed in each trench. A second dielectric layer is formed on... Agent: Jianq Chyun Intellectual Property Office

20070048963 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device including the steps of: forming a first insulating film on a silicon substrate; forming a capacitor in which a lower electrode, a capacitor dielectric film configured of ferroelectric material, and an upper electrode are laminated in this order on the first... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070048962 - Tan integrated circuit (ic) capacitor formation: Formation of a capacitor as part of an integrated circuit (IC) fabrication process is disclosed. The capacitor generally comprises a top conductive plate, a capacitor dielectric and a bottom conductive plate that respectively comprise a patterned layer of tantalum nitride TaN, a layer of a nitride based material and a... Agent: Texas Instruments Incorporated

20070048964 - Three dimensional scaffold and method of fabricating the same: A three dimensional scaffold having a three dimensional structure is easily fabricated by employing a lithography process used in a semiconductor manufacturing process. A method of fabricating the same is also disclosed have a conformational structure. In the method of fabricating a three dimensional scaffold having the conformational structure according... Agent: Cantor Colburn, LLP

20070048965 - Reduced refractive index and extinction coefficient layer for enhanced photosensitivity: An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop... Agent: Haynes And Boone, LLP

20070048966 - Narrow semiconductor trench structure: Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material... Agent: Wagner, Murabito & Hao LLP

20070048967 - Low-leakage transistor and manufacturing method thereof: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a... Agent: Banner & Witcoff

20070048970 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to manufacture, with high yield, a semiconductor device in which an element that has a layer containing an organic compound is provided over a flexible substrate. A method for manufacturing a semiconductor device includes: forming a separation layer over a substrate; forming... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070048968 - Semiconductor on glass insulator with deposited barrier layer: Methods and apparatus provide for: a silicon on insulator structure, comprising: a glass substrate; a layer of semiconductor material; and a deposited barrier layer of between about 60 nm to about 600 nm disposed between the glass substrate and the semiconductor material, where the glass substrate and semiconductor material are... Agent: Corning Incorporated

20070048969 - Stacked chip package using photosensitive polymer and manufacturing method thereof: In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with such voids. The present invention is applicable... Agent: Mills & Onello LLP

20070048971 - Laminated substrate manufacturing method and laminated substrate manufactured by the method: Adhesion of particles due to static buildup during a laminated substrate manufacturing process is constrained, so as to reduce generation of a void or a blister in a lamination step and improve yield. A laminate 13 is formed by superimposing a first semiconductor substrate 11, which is to be an... Agent: Reed Smith, LLP Attn: Patent Records Department

20070048972 - Method and apparatus for breaking semiconductor wafers: An apparatus and method for breaking a semiconductor wafer along scribe lines to separate individual die. A scribe line of the wafer is aligned with a straight, elongated pyramid-shaped edge of a precision bending bar, and a compressive force is applied to the surface of the wafer by a compressive... Agent: Law Offices Of Barry N. Young

20070048973 - Semiconductor device and method of manufacturing the same: In a method of manufacturing a semiconductor device having a through electrode 56 that connects an electrode pad 20 of a semiconductor element 14, which has a device forming layer 18 and the electrode pad 20 on one surface side, and a rewiring pattern 52 on other surface side of... Agent: Drinker Biddle & Reath (dc)

20070048974 - Epi wafer and method of making the same: A method including forming alignment marks in an upper surface of a semiconductor wafer; selectively depositing a mask over the alignment marks leaving portions of the upper surface exposed; depositing an epitaxial layer over the exposed portions of the upper surface; and thereafter removing the mask.... Agent: Tung & Associates

20070048975 - Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types, the semiconductor layers comprising first, second, and third semiconductor layers. The method further includes forming a nitride... Agent: Ibm Corporation, T.j. Watson Research Center

20070048976 - Methods of forming semiconductor constructions and capacitors: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed... Agent: Wells St. John P.s.

20070048977 - Method of depositing ge-sb-te thin film: There is provided a method of depositing a Ge—Sb—Te thin film, including: a Ge—Sb—Te thin-film forming step of feeding and purging a first precursor including any one of Ge, Sb and Te, a second precursor including another one of Ge, Sb and Te and a third precursor including the other... Agent: Ladas & Parry LLP

20070048978 - Mask for sequential lateral solidification (sls) process and a method thereof: A mask for sequential lateral solidification (SLS) process with at least one transparency region is provided. The transparent region is defined by two lengthwise edges, a front edge, and a rear edge. The two lengthwise edges also define a quadrilateral. The front edge is located outside the quadrilateral, and the... Agent: Birch Stewart Kolasch & Birch

20070048979 - Heating apparatus, and coating and developing apparatus: A heating apparatus 2 comprises a housing 20; a flat heating chamber 4 which is provided in the housing 2 and adapted to heat a wafer W used as a substrate, with one side of the heating chamber 4 opening for carrying in and carrying out the wafer; and a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070048980 - Method for post-rie passivation of semiconductor surfaces for epitaxial growth: A method for preparing a substrate for epitaxial crystal growth thereon includes performing a reactive ion etch (RIE) on a selected area of the substrate to be prepared for epitaxial crystal growth, discontinuing the introduction of an etchant species associated with the RIE, and introducing a monolayer forming species into... Agent: Cantor Colburn LLP - IBM Fishkill

20070048981 - Method for protecting a semiconductor device from carbon depletion based damage: A method for protecting a semiconductor device from carbon depletion type damage includes enriching an exposed surface of a porous interlevel dielectric material (ILD) with a carbon based material, and implementing a plasma based operation on the porous ILD material. The enriching of the porous ILD material reduces effects of... Agent: Cantor Colburn LLP - IBM Fishkill

20070048982 - Method of manufacturing semiconductor device and semiconductor device formed by the method: The method of manufacturing a semiconductor device includes forming a p-type anode layer and an anode electrode on one major surface of an n-type semiconductor substrate, irradiating an electron beam to the semiconductor substrate to introduce crystal defects into the semiconductor substrate, grinding the other major surface of semiconductor substrate... Agent: Rossi, Kimms & Mcdowell LLP.

20070048983 - Method of fabricating silicon thin film layer: A method of fabricating a high-quality silicon thin layer includes making Xe ions generated by RF power collide with a silicon target material layer to generate silicon particles from the silicon target material layer; and depositing the silicon particles on a predetermined substrate. The method is performed under a pressure... Agent: Cantor Colburn, LLP

20070048984 - Metal work function adjustment by ion implantation: A system, method and program product for adjusting metal work function by ion implantation is disclosed. The invention determines the work function of the metal and determines a desired work function threshold for the metal. The desired work function threshold may be a range and is usually based on the... Agent: Hoffman, Warnick & D'alessandro LLC

20070048985 - Dual silicide semiconductor fabrication process: A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After... Agent: Freescale Semiconductor, Inc. Law Department

20070048986 - Salicide process: A salicide process is provided. A metal layer selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second step of the second thermal... Agent: Jianq Chyun Intellectual Property Office

20070048987 - Manufacturing method of semiconductor device: Disclosed is a manufacturing method of a semiconductor device which comprising: preparing a substrate having a gate electrode film formed thereon and a gate insulation film formed between the substrate and the gate electrode film; and etching the gate electrode film formed on the gate insulation film of the substrate... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070048988 - Method for manufacturing semiconductor device using polymer: A method for manufacturing a semiconductor device using a polymer is provided, wherein a first insulating layer is formed on a substrate, and a first photoresist pattern is formed over the first insulating layer. A polymer is formed around the first photoresist pattern, the polymer having an opening exposing a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070048989 - Atomic layer deposition of gdsco3 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd2O3) and scandium oxide (Sc2O3) acting as a single dielectric layer with a formula of GdScO3, and a method of fabricating such a dielectric layer, is described that produces a reliable structure with a high... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070048990 - Method of buffer layer formation for rram thin film deposition: A method of buffer layer formation for RRAM thin film deposition includes preparing a substrate; depositing a bottom electrode on the substrate; depositing a thin layer of a transition metal having a multiple valence on the bottom electrode; depositing a layer of metal oxide on the transition metal; depositing a... Agent: Robert D. Varitz

20070048991 - Copper interconnect structures and fabrication method thereof: Copper interconnect structures for interconnection. The interconnect structure has a copper recess in a damascene structure with copper filled in a via/trench of a dielectric layer. Furthermore, the interconnect structure can also have a metal cap filled the copper recess.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070048992 - Integrated pvd system using designated pvd chambers: A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one load lock chamber, at least one first... Agent: Patterson & Sheridan, LLP

20070048995 - Method for production of semiconductor devices: A method for production of semiconductor devices which includes the steps of forming, on an interlayer insulating film formed on a substrate, a copper-containing conductive layer in such a way that its surface is exposed, performing heat treatment with a reducing gas composed mainly of hydrogen on the surface of... Agent: Sonnenschein Nath & Rosenthal LLP

20070048994 - Methods for forming through-wafer interconnects and structures resulting therefrom: The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the... Agent: Trask Britt, P.C./ Micron Technology

20070048993 - Semiconductor product and method for forming a semiconductor product: A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling... Agent: Slater & Matsil LLP

20070048997 - Chip package structure and method for manufacturing bumps: A method for manufacturing bumps is provided. First, a first metal layer is formed on a substrate. Then, a patterned second metal layer is formed on the first metal layer. Then, flat bumps are formed on the second metal layer. Finally, the first metal layer is patterned to form bond... Agent: J.c. Patents, Inc. Suite 250

20070048996 - Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that... Agent: Texas Instruments Incorporated

20070048999 - Method for fabricating semiconductor component having conductors and bonding pads with wire bondable surfaces and selected thickness: A method for fabricating a semiconductor component includes the step of providing a semiconductor die having a die contact and at least one integrated circuit in electrical communication with the die contact. The method also includes the steps of forming a first polymer layer on the die, forming a conductor... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20070048998 - Method for fabricating semiconductor components encapsulated, bonded, interconnect contacts on redistribution contacts: A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the die, forming a plurality of interconnect contacts on the redistribution contacts, and forming an insulating layer on the interconnect contacts while leaving the tip portions exposed. The... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20070049001 - Bumping process and structure thereof: A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM... Agent: Birch Stewart Kolasch & Birch

20070049000 - Method for re-forming bga of a semiconductor package: A method for re-forming BGA of a semiconductor package includes the steps of, providing a semiconductor package element formed with balls grid array, at least one of diameter of the ball is larger than the others ; providing a jig formed with penetrated holes corresponding to the each of balls... Agent: Pro-techtor International Services

20070049002 - Semiconductor device and method of packaging the same: Embodiments of the invention provide a semiconductor-chip mounting body, a semiconductor device including the mounting body, and a method of packaging the semiconductor device. According to some embodiments, when a semiconductor chip is mounted on the mounting body as a flip-chip type, an encapsulation process using an encapsulation resin is... Agent: Marger Johnson & Mccollom, P.C.

20070049003 - Semiconductor constructions and methods of forming layers: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to... Agent: Wells St. John P.s.

20070049004 - Semiconductor constructions, and methods of forming layers: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to... Agent: Wells St. John P.s.

20070049005 - Method for forming dual damascene pattern in semiconductor manufacturing process: A method for forming a dual damascene structure in a semiconductor manufacturing process is provided. The method includes forming a first dielectric layer and a first conductive layer on a semiconductor substrate; forming a second dielectric layer on the first conductive layer; applying a photoresist on the second dielectric layer;... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070049006 - Method for integration of a low-k pre-metal dielectric: A semiconductor manufacturing process for integrating a low-k dielectric layer in a fabrication process includes depositing a low-k dielectric layer (12) over a semiconductor structure (10) and planarizing the dielectric layer (12) with a CMP process to form a planarized low-k dielectric layer (20). By depositing a protective cap layer... Agent: Hamilton & Terrile, LLP

20070049007 - Interconnect structure and method for forming the same: An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage from occurring. That is, the bottom surface of the trenches... Agent: Hoffman, Warnick & D'alessandro LLC

20070049008 - Method for forming a capping layer on a semiconductor device: A method for making a semiconductor device includes forming a patterned dielectric overlying active circuitry, the patterned dielectric having a plurality of cavities. A diffusion barrier is formed over the patterned dielectric. A conductive layer is formed over the diffusion barrier in the plurality of cavities. The conductive layer is... Agent: Freescale Semiconductor, Inc. Law Department

20070049009 - Method of manufacturing conductive layer: A method of manufacturing a conductive layer is described. A substrate having a dielectric layer thereon is provided. The dielectric layer has a patterned structure and the patterned structure exposes a portion of the conductive layer. The surface of the substrate is cleaned in a first cleaning step and a... Agent: Jianq Chyun Intellectual Property Office

20070049010 - Disposable pillars for contact formation: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line... Agent: Knobbe Martens Olson & Bear LLP

20070049011 - Method of forming isolated features using pitch multiplication: Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed... Agent: Knobbe Martens Olson & Bear LLP

20070049012 - Dual damascene structure and fabrication thereof: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal... Agent: Jianq Chyun Intellectual Property Office

20070049013 - Method and apparatus for manufacturing semiconductor device, control program and computer storage medium: In a method for manufacturing a semiconductor device having a dual damascene structure, a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film is loaded into a processing chamber, and a via hole is formed by etching the insulating film through... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070049014 - Method of performing salicide processes on mos transistors: A method of performing salicide processes on a MOS transistor, wherein the MOS transistor comprises a gate structure and a source/drain region, the method comprising: performing a selective growth process to form a silicon layer on the top of the gate and the source/drain region; performing an ion implantation process... Agent: North America Intellectual Property Corporation

20070049015 - Silicided recessed silicon: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less... Agent: Knobbe Martens Olson & Bear LLP

20070049016 - Microfeature workpieces and methods for forming interconnects in microfeature workpieces: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an... Agent: Perkins Coie LLP Patent-sea

20070049019 - Method of selectively depositing materials on a substrate using a supercritical fluid: A method for depositing one or more materials on a substrate, such as for example, a semiconductor substrate that includes providing the substrate; applying a polymer film to at least a portion of a surface of the substrate; and exposing the semiconductor substrate to a supercritical fluid containing at least... Agent: Dinsmore & Shohl LLP

20070049018 - Method to reduce charge buildup during high aspect ratio contact etch: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas.... Agent: Dinsmore & Shohl LLP One Dayton Centre

20070049017 - Plug fabricating method for dielectric layer: A method of fabricating a plug for a hole in a dielectric layer is disclosed. The method includes a first deposition process to partially filling the hole with a conductive material. Later, an etching process is performed at the partially filled hole. In addition, a second deposition process is performed... Agent: Jianq Chyun Intellectual Property Office

20070049021 - Atomic layer deposition method: The invention includes atomic layer deposition (ALD) methods for forming crystalline materials. The crystalline materials can have a first atomic arrangement within one layer, and a second atomic arrangement within another layer; with the first and second atomic arrangements having different crystallographic orientations relative to one another. Alternatively, or additionally,... Agent: Wells St. John P.s.

20070049020 - Method and apparatus for reducing tensile stress in a deposited layer: A method and apparatus for compensating for tensile stress on a layer deposited on a substrate. The method includes disposing the substrate between a bladder and a contact ring, and applying pressure against a back side of the substrate toward the contact ring to bend a center region of the... Agent: Patterson & Sheridan, LLP

20070049022 - Nickel alloy silicide including indium and a method of manufacture therefor: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The... Agent: Texas Instruments Incorporated

20070049023 - Zirconium-doped gadolinium oxide films: Electronic apparatus and methods of forming the electronic apparatus include a zirconium-doped gadolinium oxide film for use in a variety of electronic systems. The zirconium-doped gadolinium oxide film may be structured as one or more monolayers. The zirconium-doped gadolinium oxide film may be formed by atomic layer deposition.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070049027 - Chemical mechanical polishing and method for manufacturing semiconductor device using the same: Provided is a CMP method. According to the CMP method, an interlayer insulating layer having two or more layers is etched to form a trench and/or via hole, and a combined thickness of the two or more layers are measured. A barrier metal layer and a metal layer are sequentially... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070049025 - Chemical-mechanical planarization composition having ketooxime compounds and associated method for use: A composition and associated method for chemical mechanical planarization (or other polishing) are described. The composition contains a ketooxime compound and water. The composition may also contain an abrasive and/or a per compound oxidizing agent. The composition affords tunability of removal rates for metal, barrier material, and dielectric layer materials... Agent: Air Products And Chemicals, Inc. Patent Department

20070049026 - Dielectric film and process for its fabrication: A dielectric film production process comprising a baking step in which a dielectric film is formed by heating a precursor layer formed on a metal layer, wherein the metal layer contains at least one type of metal selected from the group consisting of Cu, Ni, Al, stainless steel and inconel,... Agent: Oliff & Berridge, PLC

20070049024 - Manufacture method for semiconductor device having concave portions filled with conductor containing cu as its main composition: An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the insulating film are covered with an auxiliary film made of Cu alloy containing a first metal element other than Cu. A conductive member containing... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070049031 - Etching method, method of fabricating metal film structure, and etching structure: There is provided an etching method in which a protective film existing in an etching-destined region of a substrate structure is removed by means of ICP-RIE to form an exposure region of the principal surface of the substrate. The substrate structure comprises a substrate, a protective film formed on the... Agent: Rabin & Berdo, PC

20070049029 - Method of etching a te/pcmo stack using an etch stop layer: A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the... Agent: Robert D. Varitz

20070049028 - Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same: A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a template base. At least one conformal pattern layer and one conformal spacing layer, and generally a plurality of alternating pattern layers and spacing layers, are formed... Agent: Micron Technology, Inc.

20070049030 - Pitch multiplication spacers and methods of forming the same: Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the... Agent: Knobbe Martens Olson & Bear LLP

20070049032 - Protective coating for planarization: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer... Agent: Knobbe Martens Olson & Bear LLP

20070049033 - Film tray for fabricating flexible display: A film tray for fabricating a flexible display, the film tray preventing a flexible substrate or film from sagging. The film tray includes a support plate and at least one pair of clamps, each clamp of the at least one pair of clamps located along an opposite edge of the... Agent: Christie, Parker & Hale, LLP

20070049034 - High aspect ratio gap fill application using high density plasma chemical vapor deposition: A high density plasma chemical vapor deposition process including exciting gas mixture to create a plasma including ions, and directing the plasma into a dense region above the upper surface of the semiconductor wafer, heating the wafer using an additional heat source, and allowing a material from the plasma to... Agent: Tung & Associates

20070049035 - Method of forming pitch multipled contacts: Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction.... Agent: Knobbe Martens Olson & Bear LLP

20070049036 - Etching process for decreasing mask defect: The present invention provides an etching process for decreasing mask defect. The process comprises providing a substrate, and sequentually forming a thin film layer, a mask, and a photoresist on the surface of the substrate. Then the photoresist is trimmed by a bromide compound, and a first etching process is... Agent: North America Intellectual Property Corporation

20070049037 - Methods of forming openings into dielectric material: This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a lowest point and opposing sidewalls of the dielectric material. At least respective portions of the opposing sidewalls within the opening are lined with an... Agent: Wells St. John P.s.

20070049038 - Dry etching process to form a conductive layer within an opening without use of a mask during the formation of a semiconductor device: A method for use in fabrication of a semiconductor device comprises forming a conformal conductive layer over a planarized surface of a dielectric layer, and within an opening formed in the dielectric layer. The opening will typically have an aspect ratio of about 4:1 or greater. An etch is performed... Agent: Micron Technology, Inc.

20070049039 - Method for fabricating a semiconductor device: Method for fabricating a semiconductor device in which a by-product of etching is deposited on a photoresist film for using as a mask. The method for fabricating a semiconductor device includes the steps of depositing a polysilicon, and a bottom anti-refection coating on an entire surface of a substrate in... Agent: Mckenna Long & Aldridge LLP

20070049040 - Multiple deposition for integration of spacers in pitch multiplication process: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where... Agent: Knobbe Martens Olson & Bear LLP

20070049041 - Methods for etching doped oxides in the manufacture of microfeature devices: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method... Agent: Perkins Coie LLP Patent-sea

20070049045 - Atomic layer deposition method for depositing a layer: The invention is related to an ALD method for depositing a layer comprising the steps of a) providing a semiconductor substrate in a reactor; b) providing a pulse of a first precursor gas into the reactor; c) providing a pulse of a second precursor gas into the reactor; d) providing... Agent: Knobbe Martens Olson & Bear LLP

20070049042 - Method of cleaning a wafer: A wafer is provided and loaded in a reaction chamber. Subsequently, the wafer is lifted up, and a dry clean process is performed on the wafer to clean the front side, the back side, and the bevel of the wafer. Following that, a deposition process is performed on the wafer.... Agent: North America Intellectual Property Corporation

20070049043 - Nitrogen profile engineering in hi-k nitridation for device performance enhancement and reliability improvement: A method and apparatus for forming a nitrided gate dielectric. The method comprises incorporating nitrogen into a dielectric film using a plasma nitridation process to form a nitrided gate dielectric. The first step involves providing a substrate comprising a gate dielectric film. The second step involves inducing a voltage on... Agent: Patterson & Sheridan, LLP

20070049046 - Oxide film filled structure, oxide film filling method, semiconductor device and manufacturing method thereof: The present invention aims at offering the filled structure of an oxide film etc. which can form an insulating film (oxide film) without void in a predetermined depressed portion by an economical and practical method and without increasing RF bias. According to the first invention, the oxide film filled structure... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070049044 - Porous organosilicate layers, and vapor deposition systems and methods for preparing same: The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous organosilicate layers are useful, for example, as masks.... Agent: Mueting, Raasch & Gebhardt, P.A.

20070049047 - Porous thin-film-deposition substrate, electron emitting element, methods of producing them, and switching element and display element: A method of producing a porous thin-film-deposition substrate, which has the steps of: placing onto a substrate that has an electrostatic charge on its surface, fine particles with a surface electrostatic charge opposite to the electrostatic charge of the substrate surface, depositing a thin film on the fine-particle-placed substrate, and... Agent: Buchanan, Ingersoll & Rooney PC

20070049048 - Method and apparatus for improving nitrogen profile during plasma nitridation: A semiconductor manufacturing apparatus and process for forming a nitrided dielectric film includes generating a plasma source (44) over a wafer structure (46), where the plasma source (44) includes neutral species (such as nitrogen atoms) and charged species (such as nitrogen ions) that are formed in an inductively coupled plasma... Agent: Hamilton & Terrile, LLP

20070049050 - Bit line structure and method of fabrication: The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made... Agent: Brinks Hofer Gilson & Lione

20070049049 - Test-key for checking interconnect and corresponding checking method: A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor.... Agent: Jianq Chyun Intellectual Property Office

20070049051 - Atomic layer deposition of zrx hfy sn1-x-y o2 films as high k gate dielectrics: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of ZrXHfYSn1-X-YO2, and a method of fabricating such a dielectric layer is described that produces a reliable structure... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070049052 - Method for processing a layered stack in the production of a semiconductor device: A resist layer is deposited a resist layer on a first layer of a layered stack. The stack also includes a second layer below the first layer. The resist layer is processed with a lithographic method to achieve a first structured resist layer. At least a part of the first... Agent: Slater & Matsil LLP

20070049055 - Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing... Agent: Mueting, Raasch & Gebhardt, P.A.

20070049054 - Cobalt titanium oxide dielectric films: Electronic apparatus and methods of forming the electronic apparatus include a cobalt titanium oxide film on a substrate for use in a variety of electronic systems. The cobalt titanium oxide film may be structured as one or more monolayers. The cobalt titanium oxide film may be formed by atomic layer... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070049053 - Pretreatment processes within a batch ald reactor: Embodiments of the invention provide methods for forming a material on a substrate which includes exposing a plurality of substrates within a batch process chamber to a first oxidizing gas during a pretreatment process, exposing the substrates sequentially to a precursor and a second oxidizing gas during an ALD cycle... Agent: Patterson & Sheridan, LLP

20070049056 - Silicon surface preparation: Methods are provided for producing a pristine hydrogen-terminated silicon wafer surface with high stability against oxidation. The silicon wafer is treated with high purity, heated dilute hydrofluoric acid with anionic surfactant, rinsed in-situ with ultrapure water at room temperature, and dried. Alternatively, the silicon wafer is treated with dilute hydrofluoric... Agent: Knobbe Martens Olson & Bear LLP

20070049057 - Heat treatment apparatus and heat treatment method using the same: A heat treatment apparatus and a heat treatment method using the same are disclosed. In the method, a support plate on which a device substrate is mounted is loaded into the heat treatment apparatus using a transfer unit in an in-line manner, and the device substrate mounted on the support... Agent: Knobbe Martens Olson & Bear LLP