Semiconductor device manufacturing: process inventions 02/07

20070042508 - Pulsed mass flow delivery system and method: A system for delivering a desired mass of gas, including a chamber, a first valve controlling flow into the chamber, a second valve controlling flow out of the chamber, a pressure transducer connected to the chamber, an input device for providing a desired mass to be delivered, and a controller... Agent: Mcdermott Will & Emery LLP Attn: Intellectual Property Deptartment

20070042509 - Detecting endpoint using luminescence in the fabrication of a microelectronics device: The present invention provides a method of detecting an endpoint of the removal of a material from a microelectronics substrate. This embodiment includes removing at least a portion of an overlying material 210 located over a luminescent layer 215 that is located over a microelectronics substrate 220 and using luminescence... Agent: Texas Instruments Incorporated

20070042512 - Apparatus and method of predicting performance of semiconductor manufacturing process and semiconductor device, and manufacturing method of semiconductor device: Apparatus and method of predicting performance of a semiconductor manufacturing process and device, which reduces simulation resources to predict the performance distribution in the wafer and manufacturing method of a semiconductor device are disclosed. According to one aspect, it is provided a performance prediction apparatus comprising a uniform mesh data... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070042510 - In situ process monitoring and control: Systems and methods for monitoring a semiconductor manufacturing process are provided. The method includes: performing a semiconductor manufacturing process step on a wafer; directing light having a known wavelength at the wafer; monitoring a predetermined spectral range of light transmitted through a selected region of the wafer to detect an... Agent: Macpherson Kwok Chen & Heid LLP

20070042511 - Substrate processing apparatus and substrate processing method: A substrate processing apparatus performs a chemical solution process in a chemical solution process room that is partially formed within a chamber. During the chemical solution process, the substrate processing apparatus seals the chemical solution process room, and measures the pressure within the chemical solution process room, and controls the... Agent: Ostrolenk Faber Gerb & Soffen

20070042513 - Electron beam exposure method, hot spot detecting apparatus, semiconductor device manufacturing method, and computer program product: An EB exposure method includes dividing drawing layer pattern to be transferred onto drawing layer by EB exposure and underlying pattern to be transferred onto an underlying layer of the drawing layer by the EB exposure respectively into unit regions, setting representative figure in each of the unit regions of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070042514 - Method and apparatus for cooling a blade server: A method and apparatus adapted to cool a circuit board in a rack-mountable housing includes transferring heat from a heat source on the board to a primary heat storage medium positioned at an edge of the board or within a rack-mountable housing using at least one heat pipe, transferring heat... Agent: Hoffmann & Baron, LLP

20070042516 - Methods for fabrication of localized membranes on single crystal substrate surfaces: A method is provided for fabricating thin membrane structures in localized surface regions of a single crystal substrate. In the method, ion implantation masks are patterned on the surface of the single crystal substrate with openings that define the localized surface regions. Foreign ions are implanted through the openings into... Agent: Baker & Botts L.L.P.

20070042515 - Printed fuse devices and methods for making the same: Embodiments of the invention relate to efficient formation of improved fuses and fuse arrays, such as can be used in memory devices for example, by use of a printer that transfers material to a flexible substrate. In one embodiment, a fuse is printed using an inkjet printer on a flexible... Agent: Lexmark International, Inc. Intellectual Property Law Department

20070042517 - Light-emitting element, production method thereof, and light-emitting apparatus: The present invention provides an light-emitting element in which an organic compound layer containing a carbonate, for example Cs2CO3 and Li2CO3, as a dopant is in substantially electrical contact with a cathode by providing an organic compound layer having a dopant easy in handling so as to bring the organic... Agent: Fitzpatrick Cella Harper & Scinto

20070042518 - Method of manufacturing an amoled: The present invention relates to a method of manufacturing an AMOLED panel. The method comprises providing a substrate, forming a data line and a drain metal on the substrate, forming a buffer insulator layer, forming an active layer, forming a gate insulator layer, forming a gate metal, performing an ion... Agent: North America Intellectual Property Corporation

20070042519 - Manufacturing method of solid-state imaging device and solid-state imaging device: A manufacturing method of a solid-state imaging device, the device comprising: a semiconductor substrate; photodiodes each comprising a surface-side first conductivity type region formed adjacent to a surface of the semiconductor substrate and a second conductivity type region provided directly under the surface-side first conductivity type region; a second conductivity... Agent: Birch Stewart Kolasch & Birch

20070042520 - Method of manufacturing vertical gan-based light emitting diode: The present invention relates to a method of manufacturing a vertical GaN-based LED. The method includes forming an insulating pattern on a substrate to define LED regions having a predetermined size; sequentially stacking an n-type GaN-based semiconductor layer, an active layer, and a p-type GaN-based semiconductor layer on the substrate... Agent: Mcdermott Will & Emery LLP

20070042522 - Method of fabricating resistive probe having self-aligned metal shield: A method of fabricating a resistive probe having a self-aligned metal shield. The method includes sequentially forming a first insulating layer, a metal shield, and a second insulating layer on a resistive tip of a substrate; etching the second insulating layer to expose the metal shield on a resistive region;... Agent: Sughrue Mion, PLLC

20070042521 - Microelectromechanical devices and fabrication methods: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. An embodiment further includes a buried polysilicon layer and a... Agent: Courtney Staniford & Gregory LLP

20070042523 - Photoelectric current multiplier using molecular crystal and production method therefor: A NTCDA single crystal is used as a photoelectric current multiplier layer, and Au thin films are formed as electrodes on the opposite surfaces of the multiplier layer by a vapor deposition method to form a sandwich type cell. When a voltage is applied to the NTCDA single crystal by... Agent: Rader Fishman & Grauer PLLC

20070042524 - Mems devices having support structures with substantially vertical sidewalls and methods for fabricating the same: Embodiments of MEMS devices include support structures having substantially vertical sidewalls. Certain support structures are formed through deposition of self-planarizing materials or via a plating process. Other support structures are formed via a spacer etch. Other MEMS devices include support structures at least partially underlying a movable layer, where the... Agent: Knobbe, Martens, Olson & Bear, LLP

20070042525 - Laser ablation method for fabricating high performance organic devices: A laser ablation method is utilized to define the channel length of an organic transistor. A substrate is coated with a deposition of a metal or conductive polymer deposition, applied in a thin layer in order to enhance the resolution that can be attained by laser ablation. The laser ablation... Agent: Hogan & Hartson LLP

20070042526 - Metal oxide solid solution, preparation and use thereof: Disclosed is a method for preparing a metal oxide solid solution in nano size. The metal oxide solid solution is prepared by reacting a reactant mixture containing water and at least two water-soluble metal compounds at 200 to 700° C. under a pressure of 180 to 550 bar in a... Agent: Abelman Frayne & Schwab

20070042528 - Defining electrode regions of electroluminescent panel: An electroluminescent panel includes a partial electroluminescent panel base, a layer of electrically isolated conductive areas next to the partial electroluminescent panel base, and an activatable conductive layer next to the layer of electrically isolated conductive areas. The activatable conductive layer is selectively activated to electrically connect selected electrically isolated... Agent: Hewlett Packard Company

20070042527 - Microelectronic package optionally having differing cover and device thermal expansivities: A microelectronic package is provided that includes a microelectronic device and a cover. The device and the cover are typically substantially immobilized relative to each other. The cover typically has a higher coefficient of thermal expansion while the device has a higher effective stiffness. The package may be formed in... Agent: Tessera Lerner David Et Al.

20070042530 - Electronic package for image sensor, and the packaging method thereof: A semiconductor device package and method for its fabrication are provided. The semiconductor device package generally includes at least one semiconductor die and a substrate coupled to the semiconductor die. The semiconductor die is provided with a front side defining a sealing area, and a first solder sealing ring pad... Agent: Rosenberg, Klein & Lee

20070042529 - Methods and apparatus for high-density chip connectivity: Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a... Agent: Fish & Richardson P.C.

20070042531 - Method for producing semiconductor device and semiconductor device: The method of producing a semiconductor device in which chips are resin-molded, including steps of: preparing frames having front and back surfaces and die pads; preparing an insulation resin sheet having a first and a second surfaces; preparing a resin-sealing metal mold having cap pins; mounting the resin sheet inside... Agent: Buchanan, Ingersoll & Rooney PC

20070042532 - System and methods for packing in turnkey services: A system of packing for turnkey services. An input port receives first and second wafer lots from a semiconductor manufacturer. The first wafer lot comprises a first number of dies, and the second wafer lot comprises a second number of dies. A packing device loads dies of the first wafer... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070042533 - Heat conductive silicone grease composition and cured product thereof: Provided is a heat conductive silicone grease composition including (A) 100 parts by mass of an organopolysiloxane containing 2 or more alkenyl groups bonded to silicon atoms within each molecule, (B) an organohydrogenpolysiloxane containing 2 or more hydrogen atoms bonded to silicon atoms within each molecule, in sufficient quantity to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042534 - Chip package and package process thereof: A chip package and a package process thereof are provided. The chip package comprises a package substrate, a chip, a plurality of spacers, an adhesive layer, and a plurality of wires. The package substrate has a carrying surface. The chip is disposed on the carrying surface. The spacers are formed... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070042535 - Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors: A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate... Agent: Texas Instruments Incorporated

20070042536 - Thin film transistor and method for manufacturing the same: A method for manufacturing a thin film transistor of the invention comprises steps of: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming a polysilicon layer on the gate insulating layer; forming an etching-stop layer on the polysilicon layer and corresponding to... Agent: Rabin & Berdo, PC

20070042537 - Method of manufacturing a thin film transistor matrix substrate: A method of manufacturing a thin film transistor matrix substrate is provided. The first photo-mask process is used to define a gate electrode and a signal electrode. The second photo-mask process is used to obtain different thickness of a PR layer in different regions for forming a channel, gate electrode... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070042538 - Methods for preserving strained semiconductor substrate layers during cmos processing: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad... Agent: Goodwin Procter LLP Patent Administrator

20070042539 - Method of manufacturing a non-volatile memory device: In a method of manufacturing a non-volatile memory device, a first gate insulation layer and a conductive layer are formed on a substrate and then the conductive layer is partially oxidized to form an oxide layer pattern. The conductive layer is partially etched using the oxide layer pattern as an... Agent: Mills & Onello LLP

20070042540 - Method of forming a capacitor in a semiconductor device without wet etchant damage to the capacitor parts: To form a capacitor in a semiconductor device, an etching barrier layer and a mold insulating layer are sequentially formed on an interlayer insulating film having a contact plug. A hole exposing the contact plug is formed by etching the mold insulating layer and the etching barrier layer. A first... Agent: Ladas & Parry LLP

20070042541 - Semiconductor device and its manufacture method: A method for manufacturing a semiconductor device by which deterioration in the characteristics of an oxide dielectric capacitor is suppressed and the gap between capacitors and the gap between electrodes can be filled while suppressing generation of voids. The method for manufacturing a semiconductor device comprises the steps of (a)... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070042542 - Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement: A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is... Agent: Brinks Hofer Gilson & Lione Infineon

20070042543 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, the method comprising the steps of: (a) forming a titanium layer above a substrate; (b) forming a barrier layer above the titanium layer; (c) changing the titanium layer to a titanium nitride layer by conducting a heat treatment in a nitrogen containing atmosphere;... Agent: Harness, Dickey & Pierce, P.L.C

20070042545 - Bottom electrode for memory device and method of forming the same: Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap... Agent: Dickstein Shapiro LLP

20070042544 - Low-k spacer structure for flash memory: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070042546 - Method for forming floating gates within nvm process: A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), depositing a layer of polysilicon (62), planarizing the polysilicon layer with a CMP process... Agent: Hamilton & Terrile, LLP

20070042548 - Methods of forming floating gates in non-volatile memory devices including alternating layers of amorphous silicon and ald dopant layers and floating gates so formed: A method of forming a silicon layer on a substrate includes providing a silicon source gas to form an amorphous silicon layer on a substrate and providing a dopant source gas to adsorb dopants onto the amorphous silicon layer to form a dopant layer on a surface of the amorphous... Agent: Myers Bigel Sibley & Sajovec

20070042547 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070042549 - Semiconductor device having reduced effective substrate resistivity and associated methods: A semiconductor device includes at least one device active region formed in a first surface of a semiconductor substrate, an electrical contact layer on a second surface of the semiconductor substrate, and at least one resistivity-lowering body positioned in a corresponding recess in the substrate and connected to the electrical... Agent: Hiscock & Barclay, LLP

20070042552 - Method for fabricating a semiconductor device: A process for fabricating a power semiconductor device is disclosed.... Agent: Ostrolenk Faber Gerb & Soffen

20070042550 - Method for fabricating a semiconductor structure having selective dopant regions: A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070042551 - Method of manufacturing a trench transistor having a heavy body region: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the... Agent: Townsend And Townsend And Crew, LLP

20070042553 - Fabrication method for semiconductor memory components: A storage layer sequence (20) and gate electrodes (34) are arranged on a substrate (10). The gate electrodes (34) may be fabricated in a gate electrode layer (22) made of electrically conductively doped polysilicon. Apart from an optional barrier layer (45), the word lines are solely formed from a material... Agent: Slater & Matsil LLP

20070042554 - Methods of forming sram cells having landing pad in contact with upper and lower cell gate patterns: SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting... Agent: Myers Bigel Sibley & Sajovec

20070042555 - Formation of uniform silicate gate dielectrics: The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising... Agent: Texas Instruments Incorporated

20070042556 - Method of fabricating metal oxide semiconductor transistor: A method of fabricating a metal oxide semiconductor transistor is described. A substrate having device isolation structures thereon is provided. A stack gate structure is formed over the substrate. An etching stop layer is formed over the substrate to cover the stack gate structure, the substrate and the device isolation... Agent: Jianq Chyun Intellectual Property Office

20070042557 - Data download to imager chip using image sensor as a receptor: An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to control the imaging operations. The data-input can be based upon variations in light color, value, intensity, and patterning, or any combinations of the... Agent: Dickstein Shapiro LLP

20070042558 - Process for manufacturing a high-quality soi wafer: In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body of semiconductor material having a front face, a buried cavity, which extends at a distance from the front face and delimits, with the front face, a surface region of the monolithic body,... Agent: Graybeal Jackson Haley LLP

20070042559 - Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment: The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided dielectric layer (520) over a substrate (310), the nitrided dielectric... Agent: Texas Instruments Incorporated

20070042560 - Method for growing thin nitride film onto substrate and thin nitride film device: The present invention provides a method for growing a thin nitride film over a substrate and a thin nitride film device, in which the polarity of the thin nitride film can be controlled by a low temperature process. In the method for growing the thin nitride film over a substrate,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042561 - Semiconductor device and productioin method thereof: A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP-type semiconductor device, which is configured so that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with... Agent: Rader Fishman & Grauer PLLC

20070042562 - Integrated circuit device: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation,... Agent: Tessera Lerner David Et Al.

20070042564 - Semiconductor including sti and method for manufacturing the same: Provided is a semiconductor device and method of making, incorporating a trench having rounded edges. According to an embodiment, a pad oxide layer, nitride layer, and TEOS layer are sequentially formed on a substrate. The TEOS layer, nitride layer, and pad oxide layer are dry-etched using a photosensitive layer pattern... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070042563 - Single crystal based through the wafer connections technical field: A through-the-wafer (TTW) electrically conductive connection can be produced in a heavily doped substrate. An annular trench is created from one side of the wafer such that the trench almost reaches the second side of the wafer. The annular trench can be filled with an electrically insulating material. Alternatively, an... Agent: Kris T. Fredrick Honeywell International Inc.

20070042565 - Fluidic mems device: A method of manufacturing a fluidic MEMS package includes attaching a cover plate with a plurality of openings to a substrate with a plurality of bond rings with breaches such that the cover plate, the substrate and the bond rings define a plurality of respective inner cavities. The cover plate,... Agent: Hewlet-packard Company Intellectual Property Administration

20070042566 - Strained silicon on insulator (ssoi) structure with improved crystallinity in the strained silicon layer: This invention generally relates to strained silicon on insulator (SSOI) structure, and to a process for making the same. The process includes a high temperature thermal anneal of a SSOI structure to improve the crystallinity of the strained silicon layer, while maintaining the strain present therein.... Agent: Senniger Powers

20070042567 - Process for producing silicon wafer: A process for producing a silicon wafer comprising a single-wafer etching step of performing an etching by supplying an etching solution through a supplying-nozzle to a surface of a single and a thin-discal wafer obtained by slicing a silicon single crystal ingot and rotating the wafer to spread the etching... Agent: Kolisch Hartwell, P.C.

20070042568 - Semiconductor device with a thinned semiconductor chip and method for producing the thinned semiconductor chip: A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070042572 - Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates: Methods are provided for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects. Amorphous SiGe layers are deposited by CVD from trisilane and GeH4. The amorphous SiGe layers are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also... Agent: Knobbe Martens Olson & Bear LLP

20070042569 - Low temperature formation of patterned epitaxial si containing films: A method for selectively forming an epitaxial Si containing film on a semiconductor structure at low temperature. The method includes providing the structure in a process chamber, the structure containing a Si substrate having an epitaxial Si surface area and a patterned film area thereon. A Si film is non-selectively... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042571 - Method of forming group-iii nitride crystal, layered structure and epitaxial substrate: Heat treatment is conducted at a predetermined temperature of not less than 1250° C. on an underlying substrate obtained by epitaxially forming a first group-III nitride crystal on a predetermined base as an underlying layer. Three-dimensional fine irregularities resulting from crystalline islands are created on the surface of the underlying... Agent: Burr & Brown

20070042570 - Sequential deposition process for forming si-containing films: A method is provided for forming a Si film in sequential deposition process. The method includes providing a substrate in a process chamber, forming a chlorinated Si film by exposing the substrate to a chlorinated silane gas, and dry etching the chlorinated Si film to reduce the chlorine content of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042573 - Methods of forming conductive polysilicon thin films via atomic layer deposition and methods of manufacturing semiconductor devices including such polysilicon thin films: A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a... Agent: Myers Bigel Sibley & Sajovec

20070042574 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device that can prevent short-circuiting between gate electrodes and increases in the leakage current of a capacitive insulating film caused by the bottom electrode of the capacitor is provided. The method for manufacturing a semiconductor device according to the present invention comprises a first... Agent: Mcdermott Will & Emery LLP

20070042575 - Crystallization apparatus and method of amophous silicon: A plurality laser beams generated by a plurality of beam generators are synthesized by a beam synthesizer. The synthesized beam is splitted into a plurality of beamlets and provided for a plurality of optical units controlling the beamlets. Each beamlet controlled by each optical unit is illuminated onto an amorphous... Agent: F. Chau & Associates, LLC

20070042576 - Stable, water-soluble quantum dot, method of preparation and conjugates thereof: A method for manufacturing powdered quantum dots comprising the steps of: a) reacting quantum dots comprising a core, a cap and a first ligand associated with the outer surfaces thereof with a second ligand, the second ligand displacing the first ligand and attaching to the outer surfaces of the quantum... Agent: Birch Stewart Kolasch & Birch

20070042577 - Method of preparing a film layer-by-layer using plasma enhanced atomic layer deposition: A method for forming a thin film on a substrate layer by layer using plasma enhanced atomic layer deposition is described. The method comprises using a low power reduction step for at least one cycle in order to substantially avoid partial layer film growth, followed by using a high power... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042578 - Method for making junction and processed material formed using the same: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to... Agent: Mcdermott Will & Emery LLP

20070042579 - System and method for ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits: A system and method for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070042580 - Ion implanted insulator material with reduced dielectric constant: An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material... Agent: Law Office Of Robert M. Wallace

20070042581 - Manufacturing method of semiconductor device and substrate processing apparatus: The method comprises a step of forming a film containing the metal atom and the silicon atom on a substrate 30 in a reaction chamber 4, and performing a nitriding process for the film, wherein the film is formed by changing a silicon concentration at least in two stages in... Agent: Oliff & Berridge, PLC

20070042582 - Method of forming a nanowire and method of manufacturing a semiconductor device using the same: In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire... Agent: Mills & Onello LLP

20070042583 - Semiconductor device and method of manufacturing the same: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed... Agent: Marger Johnson & Mccollom, P.C.

20070042584 - Method of forming a silicide: At least one gate electrode is formed on a substrate. A first dielectric layer and a second dielectric layer are formed on the gate electrode, respectively. A portion of the second dielectric layer is removed to form a spacer on either side of the gate electrode. A portion of the... Agent: North America Intellectual Property Corporation

20070042585 - Method of forming metal plate pattern and circuit board: A method of forming a high aspect ratio metal plate pattern or circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one or two surfaces of a copper plate (10) and patterned into a resist pattern. A tin plating layer (14) is... Agent: Chadbourne & Parke L.l.p

20070042586 - Stabilization of ni monosilicide thin films in cmos devices using implantation of ions before silicidation: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation... Agent: Scully, Scott, Murphy & Presser, P.C.

20070042589 - Composite inter-level dielectric structure for an integrated circuit: A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on... Agent: Mayer & Williams PC

20070042590 - Method for maufacturing semiconductor device: A diffusion barrier film which covers the surface of a first insulating film provided on an upper surface of a semiconductor substrate, a second insulating film which covers over the diffusion barrier film, and a cap film which covers the second insulating film, are sequentially laminated. A wiring trench portion,... Agent: Volentine Francos, & Whitt PLLC

20070042587 - Method of forming a catalyst layer on the barrier layer of a conductive interconnect of a semiconductor device: A method is provided for depositing a conductive material in a sub-micron recessed feature formed on a substrate. The method begins by depositing a barrier layer over a dielectric layer disposed on the substrate while under a vacuum of the type found in a vacuum chamber. A catalytic layer is... Agent: Mayer & Williams PC

20070042588 - Single damascene with disposable stencil and method therefore: In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited... Agent: Slater & Matsil LLP

20070042592 - Novel approach to high temperature wafer processing: At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows... Agent: Kris T. Fredrick Honeywell International Inc.

20070042591 - Signal routing on redistribution layer: A semiconductor wafer has a dielectric layer, a metal last layer, a passivation layer, and a redistribution layer. The metal last layer is formed over the dielectric layer, and the metal last layer has first and second locations that are spaced apart from each other. The passivation layer is formed... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070042593 - Bonding pad structure and method of forming the same: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070042594 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes providing a base plate; mounting a plurality of semiconductor chips each having a plurality of connection pads formed on an upper surface thereof to the base plate, the plural semiconductor chips being mounted apart from each other; forming an insulating film on... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070042595 - Packaging of electronic chips with air-bridge structures: A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070042597 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which prevention of disconnection due to a step caused by a surface shape before film formation, control of increase in the cost in forming an insulating film over a large-sized substrate, improvement... Agent: Nixon Peabody, LLP

20070042596 - Method of forming an interconnect structure for a semiconductor device: A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrate as well as from the... Agent: Dickstein Shapiro LLP

20070042598 - Dielectric with sidewall passivating layer: A polymer dielectric material includes a sidewall passivating layer on the opposing sidewall surfaces of an opening in the dielectric layer for a via or trench. The sidewall passivating layer may be deposited on the sidewall surfaces, as well as the bottom surface of an opening having a first depth... Agent: Trop Pruner & Hu, PC

20070042600 - Method for fabricating semiconductor device: In a Cu interconnect process, an organic-based low-dielectric-constant interlayer film is formed, and then a protective film is deposited on the side and back surfaces of a wafer bevel and the back surface of a wafer edge. Thereafter, a lithography process and an etching process are carried out, a copper... Agent: Mcdermott Will & Emery LLP

20070042599 - Methods to facilitate etch uniformity and selectivity: A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered.... Agent: Texas Instruments Incorporated

20070042604 - Copolymers, polymer resin composition for buffer layer method of forming a pattern using the same and method of manufacturing a capacitor using the same: wherein the variables L, M and N represent the relative molar fractions of the monomers and satisfy the expressions 0<L≦0.8; 0<M≦0.25; 0<N≦0.35; and L+M+N=1; and, wherein R1, R2 and R3 are independently selected from C1-C6 alkyls and derivatives thereof. The invention is also directed to polymer compositions that, when used... Agent: Harness, Dickey & Pierce, P.L.C

20070042602 - Etch method using supercritical fluids: Methods are described for removing a material from a substrate by dissolving an etchant into a solvent to form a solution; and exposing the substrate to the solution so that the etchant in the solution removes material from the substrate; wherein during the exposure the solution is maintained in a... Agent: Fish & Richardson PC

20070042603 - Method for etching having a controlled distribution of process results: Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to... Agent: Patterson & Sheridan, LLP Applied Materials Inc

20070042601 - Method for etching high dielectric constant materials: In one implementation, a method is provided for etching a high k dielectric material in a plasma etch reactor, the method comprising plasma etching the high k dielectric material with a first plasma gas reactant mixture having BCl3. The high k dielectric material may include Al2O3 in a stack having... Agent: Aagaard & Balzan, LLP

20070042605 - Method of etching a substrate and method of forming a feature on a substrate: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing... Agent: Wells St. John P.s.

20070042606 - Creating novel structures using deep trenching of oriented silicon substrates: A potassium hydroxide (KOH) etch process can produce deep high aspect ratio trenches in (110) oriented silicon substrates. The trenches, however, are perpendicular to the (111) direction of the silicon substrate's crystal lattice. The trenches are used to produce thermally isolating areas and through the wafer electrical connections. These structures... Agent: Attorney, Intellectual Property Honeywell International, Inc.

20070042607 - Etch features with reduced line edge roughness: A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the... Agent: Beyer Weaver & Thomas, LLP

20070042608 - Method of substantially uniformly etching non-homogeneous substrates: A method of substantially uniformly etching oxides from non-homogeneous substrates is provided. The method utilizes a substantially non-aqueous etchant including an organic solvent and a fluorine-containing compound. The fluorine containing compound may include HF, HF:NH4F, (NH4)HF2, or TMAF:HF and mixtures thereof. The etchant may be applied to chemically non-homogeneous layers... Agent: Dinsmore & Shohl LLP One Dayton Centre

20070042610 - Method of depositing low k barrier layers: A method is provided for processing a substrate including providing a processing gas comprising an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in damascene or dual damascene applications... Agent: Patterson & Sheridan, LLP

20070042609 - Molecular caulk: a pore sealant for ultra-low k dielectrics: Methods of use of parylene based polymers with porous ultra-low κ dielectric materials and use of parylene barriers in integrated circuit fabrication are presented.... Agent: Heslin Rothenberg Farley & Mesiti PC

20070042611 - Method of producing a trench in a photo-resist on a iii-v wafer and a compound wafer having a photo-resist including such a trench: A method of producing a trench in a photo-resist on a III-V wafer comprising providing a III-V wafer; providing a photo-resist on the wafer; exposing the photo-resist to UV radiation through a mask; removing one of the exposed or non-exposed portions of the photo-resist to produce a recess; applying a... Agent: Howard & Howard Attorneys, P.C.

20070042612 - Method for manufacturing semiconductor device: It is made possible to form a silicon nitride film, an aluminum oxide film and a transition metal high-k insulation film of high quality. A manufacturing method includes: forming an insulation film having at least one kind of bonds selected out of silicon-nitrogen bonds, aluminum-oxygen bonds, transition metal-oxygen-silicon bonds, transition... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070037299 - Low power magnetoresistive random access memory elements: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070037298 - Semiconductor device with ferroelectric capacitor and fabrication method thereof: A semiconductor device fabrication method includes the steps of forming a conductive plug in an insulating film so as to be connected to an element on a semiconductor substrate; forming a titanium aluminum nitride (TiAlN) oxygen barrier film over the conductive plug; forming a titanium (Ti) seed film over the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070037301 - Method and apparatus for monitoring precision of wafer placement alignment: A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the... Agent: Brinks Hofer Gilson & Lione Infineon

20070037300 - Systems and methods for plasma processing of microfeature workpieces: Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured... Agent: Perkins Coie LLP Patent-sea

20070037303 - Apparatus and method of illuminating the surface of a wafer in a wafer inspection system: An apparatus for illuminating the surface of a wafer in a wafer inspection system, comprising a first flash source for emitting a first light beam and a second flash source for emitting a second light beam, a redirecting optics and a control means, wherein the flash sources are arranged for... Agent: Simpson & Simpson, PLLC

20070037302 - Method of preparing electrode: Methods of preparing electrodes, as well as related devices, components, systems, and methods, are disclosed.... Agent: Attn: Tony Zhang Konarka Technologies, Inc.

20070037304 - Method for manufacturing semiconductor device and semiconductor device: In a method for manufacturing a semiconductor device, insulation resistance of the porous film is stabilized, and leakage current between adjacent interconnects provides an improved reliability in signal propagation therethrough. The method includes: sequentially forming over a semiconductor substrate a porous film and a patterned resist film; forming a concave... Agent: Young & Thompson

20070037306 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes: forming a protrusion-patterned layer on a substrate, the protrusion-patterned layer including a plurality of separated protrusions, each of which includes a base portion formed on the substrate and a top end portion opposite to the base portion; laterally growing a base layer... Agent: Foley And Lardner LLP Suite 500

20070037305 - Method of manufacturing semiconductor light- emitting device and semiconductor light-emitting device: A semiconductor light-emitting device and method for manufacturing the semiconductor light-emitting device includes a mask layer etching process on first and second mask layers provided on a Group-III nitride-based compound semiconductor substrate, the mask layer with a higher etching rate being closer to the p-type semiconductor layer; a semiconductor layer... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070037307 - Method of forming three-dimensional features on light emitting diodes for improved light extraction: A method is disclosed for obtaining a high-resolution lenticular pattern on the surface of a light emitting diode. The method comprises imprinting a patterned sacrificial layer of etchable material that is positioned on a semiconductor surface that is in turn adjacent a light emitting active region, and thereafter etching the... Agent: Summa, Allan & Additon, P.A.

20070037308 - Method for manufacturing gan semiconductor light-emitting element: A method for manufacturing a GaN semiconductor light-emitting element is provided. The method for manufacturing a GaN semiconductor light-emitting element includes forming, by crystal growth, a first GaN compound semiconductor layer of a first conductivity type, the top face of which corresponds to the A plane, an active layer composed... Agent: Bell, Boyd & Lloyd, LLC

20070037309 - Semiconductor device and method for manufacturing the same: The TFT electric characteristic is ready to be influenced by the channel region in the neighborhood of an interface between a semiconductor and a gate insulating film. The present invention provides TFTs reduced in electric characteristic deviations and a method for manufacturing the same. The invention forms a region or... Agent: Nixon Peabody, LLP

20070037310 - Semiconductor sensor production method and semiconductor sensor: A semiconductor sensor production method includes the steps of (A) forming a first etching mask layer on a support part segment of a backside semiconductor layer, except on a portion of the support part segment which portion is along edges of the support part segment; (B) forming a second etching... Agent: Cooper & Dunham, LLP

20070037311 - Manufacturing method of microelectromechanical system: To provide a method of easily forming a three-dimensional structure typified by a cantilever by using a thin film formed over an insulating surface, and provide a microelectromechanical system formed by such a method. A three-dimensional structure typified by a cantilever is formed by using a mask having a nonuniform... Agent: Fish & Richardson P.C.

20070037313 - Cmos image sensor and manufacturing method thereof: Disclosed are a CMOS image sensor and a manufacturing method thereof. The method includes forming an isolation layer in a semiconductor substrate, defining an active region including a photo diode region and a transistor region; forming a gate insulating layer and a gate electrode on the transistor region; forming a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070037312 - Image sensor and fabrication method thereof: Example embodiments relate to an image sensor and a fabrication method thereof, capable of reducing dark current and a fabrication method thereof. The image sensor may include a semiconductor substrate including an active region defined by an isolation layer, a photoelectric-conversion region and a charge-movement-prevention region formed at an interface... Agent: Harness, Dickey & Pierce, P.L.C

20070037314 - Method for fabricating image sensor without lto-based passivation layer: A method for fabricating an image sensor including a first region, which is a light receiving region, and a second region, which is a pad region, includes forming a metal line in the second region over a substrate structure comprising a photodiode, forming a passivation layer over the substrate structure,... Agent: Morgan Lewis & Bockius LLP

20070037315 - Silicone metalization: A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide... Agent: Eddie E. Scott Attorney

20070037316 - Memory cell contact using spacers: A method of forming contacts used in a memory device. The method involves forming a via in an insulating layer, forming spacers on sidewalls of the via, and filling the via with a conductive material. The resulting contact has rounded upper corners to improve the reliability of the memory device.... Agent: Dickstein Shapiro LLP

20070037318 - Method and apparatus for flip-chip bonding: Provided are a laser flip-chip bonding method having high productivity and excellent bonding reliability and a flip-chip bonder employing the same. The flip-chip bonder includes: a bonding stage on which a substrate rests; a bonding head picking up a semiconductor chip and attaching the semiconductor chip to the substrate; and... Agent: Gardner Carton & Douglas LLP Attn: Patent Docket Dept.

20070037317 - Method and device for attaching a chip in a housing: A method and the associated device for attaching at least one micromechanical chip in a housing which is optically transparent to radiation of at least one predefined transmission wavelength, in which an adhesive layer is applied between the chip and the housing and the adhesive layer is irradiated through the... Agent: Kenyon & Kenyon LLP

20070037320 - Multichip packages with exposed dice: Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip... Agent: Beyer Weaver & Thomas, LLP

20070037319 - Semiconductor package with contact support layer and method to produce the package: A semiconductor package comprises a substrate which includes a plurality of conducting traces and upper contact areas on its upper surface and a second plurality of lower conductive traces and external contact areas on its bottom surface and external conducting members attached to the external contact areas. The semiconductor package... Agent: Edell, Shapiro & Finnan, LLC

20070037321 - semiconductor device and a manufacturing method of the same: The semiconductor device having the structure which laminated the chip in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070037322 - End electrode structure of a surface-mounted resettable over-current protection device: The present invention relates to an end electrode structure of a surface-mounted resettable over-current protection device. A polymer-based sheet is punched with a mold for manufacturing a plurality of H-shaped through-holes separated at an equal interval, such that several strip-shaped sheets are formed. Then, a first pair of electrodes and... Agent: Ladas & Parry LLP

20070037325 - After deposition method of thinning film to reduce pinhole defects: A method of forming a thin film is provided in which a film having a first thickness is deposited over a substrate, wherein the first thickness is greater than a thickness at which the initially deposited film begins to dewet from the substrate. The initially deposited film is then stabilized... Agent: International Business Machines Corporation Dept. 18g

20070037323 - Manufacturing strained silicon substrates using a backing material: A method for forming a strained silicon layer of semiconductor material. The method includes providing a deformable surface region having a first predetermined radius of curvature, which is defined by R(l) and is defined normal to the surface region. A backing plate is coupled to the deformable surface region to... Agent: Townsend And Townsend And Crew, LLP

20070037324 - Process for producing an mos transistor and corresponding integrated circuit: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the... Agent: Jenkens & Gilchrist, PC

20070037328 - Method of manufacturing a non-volatile memory device: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070037326 - Shallow source/drain regions for cmos transistors: A transistor having shallow, high-dopant concentration source/drain regions is provided. A gate electrode is formed on a substrate, and the source/drain regions of the substrate are transformed into an amorphous state by, for example, implanting Si, Ge, Xe, In, Ar, Kr, Rn, a combination thereof, or the like ions. A... Agent: Slater & Matsil, L.L.P.

20070037327 - Structure and method for forming inter-poly dielectric in a shielded gate field effect transistor: A shielded gate trench FET is formed as follows. A trench is formed in a silicon region of a first conductivity type, the trench including a shield electrode insulated from the silicon region by a shield dielectric. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer... Agent: Townsend And Townsend And Crew, LLP

20070037329 - Growing [110] silicon on [001] oriented substrate with rare-earth oxide buffer film: An assembly and method of making the same wherein the assembly incorporates a rare-earth oxide film to form a [110] crystal lattice orientation semiconductor film. The assembly comprises a substrate, a rare-earth oxide film formed on the substrate, and a [110]-oriented semiconductor film formed on the rare-earth oxide film. The... Agent: Blakely Sokoloff Taylor & Zafman

20070037330 - Evaluation method of semiconductor device, manufacturing method of the semiconductor device, design management system of device comprising the semiconductor device, dose amount control program for the semiconductor device, computer-readable recording medi: There is provided a new method of obtaining the dopant activation rate of a device accurately and simply in a different way from a method of obtaining a carrier density with use of a Hall measurement or CV measurement, and also provided a production method of a device performed with... Agent: Nixon Peabody, LLP

20070037332 - Laser irradiation apparatus, laser irradiation method, and method for manufacturing semiconductor device: In order to solve the problem, a pulsed laser beam 1 having a wavelength absorbed sufficiently in the semiconductor film is used in combination with a laser beam 2 having a high output and having a wavelength absorbed sufficiently in the melted semiconductor film. After irradiating the laser beam 1... Agent: Eric Robinson

20070037331 - Laser irradiation method, laser irradiation apparatus, and semiconductor device: An object of the present invention is obtaining a semiconductor film with uniform characteristics by improving irradiation variations of the semiconductor film. The irradiation variations are generated due to scanning while irradiating with a linear laser beam of the pulse emission. At a laser crystallization step of irradiating a semiconductor... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070037335 - Dual work function cmos devices utilizing carbide based electrodes: Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work... Agent: Texas Instruments Incorporated

20070037337 - Manufacturing method of semiconductor device: A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070037334 - Memory device and method of manufacturing a memory device: The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070037336 - Semiconductor device with improved gate resistance and method of its manufacture: A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch... Agent: Marger Johnson & Mccollom, P.C.

20070037333 - Work function separation for fully silicided gates: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal is added to a first region of polysilicon overlying a dielectric that is on a substrate, and a second metal is added to a second region of the polysilicon. A third metal is... Agent: Texas Instruments Incorporated

20070037338 - Cmos image sensor and manufacturing method thereof: Provided is a CMOS (complementary metal oxide semiconductor) image sensor and a manufacturing method therof, In the method, a photodiode, an interlayer insulating layer, a color filter layer, and a planarizing layer are sequentially formed on a substrate. A photoresist is applied on the planarizing layer. The photoresist is selectively... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070037339 - Semiconductor circuit arrangement with trench isolation and fabrication method: An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insulating function between adjacent components, the patterning of the charge-storing layer and also the... Agent: Brinks Hofer Gilson & Lione

20070037340 - Fabrication method for fabricating a semiconductor structure and semiconductor structure: In a method for fabricating a semiconductor structure a semiconductor substrate comprising an active region with an uncovered top side is provided, at least one STI trench adjoining the active region is formed, and an STI divot is formed in the insulating filling. The at least one STI trench comprises... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070037341 - Method and structure for shallow trench isolation during integrated circuit device manufacture: A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises etching through silicon nitride and pad oxide layers and into a semiconductor wafer to form a trench into the wafer. A shallow trench isolation (STI)... Agent: Micron Technology, Inc.

20070037342 - Method to obtain fully silicided poly gate: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them.... Agent: Texas Instruments Incorporated

20070037343 - Process for manufacturing dual work function metal gates in a microelectronics device: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a... Agent: Texas Instruments Incorporated

20070037344 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a semiconductor substrate 10, a conducting film 20 formed on the semiconductor substrate 10 and including two conductor patterns adjacent to each other; an etching stopper film covering the upper surface of the conducting film 20; an insulation film 28 which includes a contact hole which... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070037345 - Memory cell array and memory cell: A method of forming a memory cell array including a plurality of memory cells includes patterning isolation trenches on a semiconductor substrate and filling with an insulating material to define active area lines. In particular, the isolation trenches are patterned as straight lines, resulting in the active area lines being... Agent: Edell, Shapiro & Finnan, LLC

20070037347 - Capacitor of semiconductor device and method of fabricating the same: A capacitor of a semiconductor device includes an oxide layer pattern including a trench formed on a semiconductor substrate, the trench having an inner wall and a bottom, quantum dots discontinuously formed on the inner wall of the trench, a bottom electrode formed on the inner wall and the bottom... Agent: F. Chau & Associates, LLC

20070037346 - Rapid thermal annealing of targeted thin film layers: A method for rapid thermal annealing of thin film layers is provided. The method directs a series of pulses or flashes of heat energy toward a targeted layer on a substrate. Each pulse may be at a first temperature range sufficient to anneal the targeted layer, but has a duration... Agent: Greenberg Traurig, LLP

20070037348 - Method of fabricating trench isolation of semiconductor device: In a method of fabricating a trench isolation structure of a semiconductor device, excellent gap filling properties are attained, without the generation of defects. In one aspect, the method comprises: loading a substrate with a trench formed therein into a high-density plasma (HDP) chemical vapor deposition apparatus; primarily heating the... Agent: Mills & Onello LLP

20070037349 - Method of forming electrodes: To form a semiconductor device, a plurality of upwardly extending conductors can be formed. The conductors extend outward from a surface of a semiconductor body, adjacent ones of the conductors being separated from each other by a separating material. At least one support structure is formed between adjacent ones of... Agent: Slater & Matsil LLP

20070037350 - Flash memory cell having reduced floating gate to floating gate coupling: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric... Agent: Blakely Sokoloff Taylor & Zafman

20070037351 - Method of fabricating a resistance based memory device and the memory device: Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device... Agent: Harness, Dickey & Pierce, P.L.C

20070037352 - Display device and manufacturing method of display device: According to one feature of the present invention, a display device is manufactured according to the steps of forming a semiconductor layer; forming a gate insulating layer over the semiconductor layer; forming a gate electrode layer over the gate insulating layer; forming source and drain electrode layers in contact with... Agent: Eric Robinson

20070037353 - Efficient transistor structure: An integrated circuit comprises a first drain region having a symmetric shape across at least one of horizontal and vertical centerlines. A first gate region has a first shape that surrounds the first drain region. A second drain region has the symmetric shape. A second gate region has the first... Agent: Harness, Dickey & Pierce P.L.C

20070037354 - Semiconductor device having a structure to improve contact processing margin, and method of fabricating the same: A method for fabricating a semiconductor device includes forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate; forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern; forming a second insulating pattern... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070037355 - Esd protection device for high voltage: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically... Agent: Slater & Matsil, L.L.P.

20070037356 - Method of manufacture of raised source drain mosfet with top notched gate structure filled with dielectric plug: A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack... Agent: Graham S. Jones, Ii

20070037357 - Method for removing photoresist using a thermal bake in the presence of hydrogen and a semiconductor device manufactured using the same: The present invention provides a method for removing photoresist, and a method for manufacturing a semiconductor device. The method for removing photoresist, without limitation, may include subjecting a photoresist layer (210) located over a substrate (110) to a thermal bake (410) in the presence of hydrogen, and then removing the... Agent: Texas Instruments Incorporated

20070037358 - Apparatus for etching a glass substrate: An apparatus for etching a glass substrate includes a container for receiving an etching solution and at least two rollers disposed in the container. The at least two rollers may face with each other. The glass substrate is inserted between the at least two rollers, and the glass substrate is... Agent: Harness, Dickey & Pierce, P.L.C

20070037359 - Method of forming align key in well structure formation process and method of forming element isolation structure using the align key: A method of forming an align key in a well structure formation process is provided. The method includes: providing a semiconductor substrate having an align key region and a first well region and forming a first ion implantation mask on the substrate. The first ion implantation mask has a groove... Agent: F. Chau & Associates, LLC

20070037361 - Method for forming void-free trench isolation layer: Disclosed method for forming void-free isolation comprises the steps of: forming a trench in an isolation region in a semiconductor substrate; and forming a filling oxide on the semiconductor substrate to fill the trench. The filling oxide is formed by HDP-CVD process and by using reactant gas mixture that includes... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070037360 - Semiconductor device using epi-layer and method of forming the same: A method of fabricating a semiconductor device includes forming a pad oxide film and a nitride film on a semiconductor substrate; exposing the semiconductor substrate by selectively etching the pad oxide film and the nitride film; forming a trench in the exposed semiconductor substrate; forming a gap-fill dielectric film in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070037362 - Method and apparatus for integrating iii-v semiconductor devices into silicon processes: Method and apparatus for fabricating semiconductor devices, for example, III-V semiconductor devices, having a desired substrate, for example, a silicon substrate. A method for fabricating semiconductor devices includes providing a semiconductor wafer that includes a plurality of semiconductor structures attached to a native substrate formed of a first substrate material,... Agent: Avago Technologies, Ltd.

20070037363 - Method for forming a brittle zone in a substrate by co-implantation: The invention concerns a method for making a thin film, which consists in creating a brittle zone embedded by implantation of a chemical species in a substrate, so as to be able subsequently to provoke a fracture of the substrate along said brittle zone to separate therefrom said thin film.... Agent: Brinks Hofer Gilson & Lione

20070037364 - Method for manufacturing semiconductor chip: It is the object of the invention to provide a method for manufacturing a semiconductor chip capable of obtaining a semiconductor chip at a high manufacturing efficiency without damages. The invention is a method for manufacturing a semiconductor chip, which comprises a tape adhesion step of sticking a pressure sensitive... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070037365 - Semiconductor nanostructures and fabricating the same: During the growth of semiconductor nanowires on a substrate, different respective vapor-liquid-solid reactions that respectively form target segments and sacrificial segments of the semiconductor nanowires at growth locations defined by catalyst particles are supported. The sacrificial segments of the semiconductor nanowires are selectively removed to form semiconductor nanostructures corresponding to... Agent: Agilent Technologies Inc.

20070037366 - Method of crystallizing amorphous semiconductor film: A method of crystallizing a non-monocrystalline semiconductor film, including forming a non-monocrystalline semiconductor film on a substrate, subjecting the non-monocrystalline semiconductor film to a dehydrogenation treatment by way of at least one kind of heat treatment which is selected from the group consisting of irradiating flash lamp beam to a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070037367 - Apparatus for plasma doping: A doping device is provided having a vacuum container defining a chamber therein. The container has a portion made of dielectric material and bears an impurity to be doped in a substrate provided in the chamber. Also provided is a plasma source for generating a plasma in the chamber by... Agent: Wenderoth, Lind & Ponack L.L.P.

20070037368 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device includes a processing step of high-energy ion implantation. After performing the high-energy ion implantation process and before beginning a thermal process, a buffer layer is partially removed together with particles or contaminants that may be generated from the ion implantation process. Surface defects... Agent: Mills & Onello LLP

20070037369 - Method of manufacturing silicon carbide semiconductor device: A manufacturing method for forming a region into which impurity ions are implanted, and an electrode is coupled to the region, in a self-aligned manner. An oxide film is formed on an n-type semiconductor layer composed of a silicon carbide semiconductor, and then the oxide film on regions in which... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070037370 - Method and apparatus for high-efficiency synthesis of carbon nanostructure, and carbon nanostructure: A high-efficiency synthesis method of carbon nanostructure according to the present invention is a high-efficiency synthesis method of carbon nanostructure, the method comprising: bringing raw material gas and a catalyst into contact with each other under reactive conditions so as to produce a carbon nanostructure, wherein: the initiation of contact... Agent: Harness, Dickey & Pierce, P.L.C

20070037371 - Method of forming gate electrode structures: In one example, the method includes forming a patterned hard mask feature above a layer of gate electrode material, the hard mask feature having a photoresist feature formed thereabove and the hard mask feature having a critical dimension. The method further includes performing an etching process on the patterned hard... Agent: Williams, Morgan & Amerson

20070037372 - Planarizing a semiconductor structure to form replacement metal gates: A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a