Semiconductor device manufacturing: process inventions 02/07

20070042508 - Pulsed mass flow delivery system and method: A system for delivering a desired mass of gas, including a chamber, a first valve controlling flow into the chamber, a second valve controlling flow out of the chamber, a pressure transducer connected to the chamber, an input device for providing a desired mass to be delivered, and a controller... Agent: Mcdermott Will & Emery LLP Attn: Intellectual Property Deptartment

20070042509 - Detecting endpoint using luminescence in the fabrication of a microelectronics device: The present invention provides a method of detecting an endpoint of the removal of a material from a microelectronics substrate. This embodiment includes removing at least a portion of an overlying material 210 located over a luminescent layer 215 that is located over a microelectronics substrate 220 and using luminescence... Agent: Texas Instruments Incorporated

20070042512 - Apparatus and method of predicting performance of semiconductor manufacturing process and semiconductor device, and manufacturing method of semiconductor device: Apparatus and method of predicting performance of a semiconductor manufacturing process and device, which reduces simulation resources to predict the performance distribution in the wafer and manufacturing method of a semiconductor device are disclosed. According to one aspect, it is provided a performance prediction apparatus comprising a uniform mesh data... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070042510 - In situ process monitoring and control: Systems and methods for monitoring a semiconductor manufacturing process are provided. The method includes: performing a semiconductor manufacturing process step on a wafer; directing light having a known wavelength at the wafer; monitoring a predetermined spectral range of light transmitted through a selected region of the wafer to detect an... Agent: Macpherson Kwok Chen & Heid LLP

20070042511 - Substrate processing apparatus and substrate processing method: A substrate processing apparatus performs a chemical solution process in a chemical solution process room that is partially formed within a chamber. During the chemical solution process, the substrate processing apparatus seals the chemical solution process room, and measures the pressure within the chemical solution process room, and controls the... Agent: Ostrolenk Faber Gerb & Soffen

20070042513 - Electron beam exposure method, hot spot detecting apparatus, semiconductor device manufacturing method, and computer program product: An EB exposure method includes dividing drawing layer pattern to be transferred onto drawing layer by EB exposure and underlying pattern to be transferred onto an underlying layer of the drawing layer by the EB exposure respectively into unit regions, setting representative figure in each of the unit regions of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070042514 - Method and apparatus for cooling a blade server: A method and apparatus adapted to cool a circuit board in a rack-mountable housing includes transferring heat from a heat source on the board to a primary heat storage medium positioned at an edge of the board or within a rack-mountable housing using at least one heat pipe, transferring heat... Agent: Hoffmann & Baron, LLP

20070042516 - Methods for fabrication of localized membranes on single crystal substrate surfaces: A method is provided for fabricating thin membrane structures in localized surface regions of a single crystal substrate. In the method, ion implantation masks are patterned on the surface of the single crystal substrate with openings that define the localized surface regions. Foreign ions are implanted through the openings into... Agent: Baker & Botts L.L.P.

20070042515 - Printed fuse devices and methods for making the same: Embodiments of the invention relate to efficient formation of improved fuses and fuse arrays, such as can be used in memory devices for example, by use of a printer that transfers material to a flexible substrate. In one embodiment, a fuse is printed using an inkjet printer on a flexible... Agent: Lexmark International, Inc. Intellectual Property Law Department

20070042517 - Light-emitting element, production method thereof, and light-emitting apparatus: The present invention provides an light-emitting element in which an organic compound layer containing a carbonate, for example Cs2CO3 and Li2CO3, as a dopant is in substantially electrical contact with a cathode by providing an organic compound layer having a dopant easy in handling so as to bring the organic... Agent: Fitzpatrick Cella Harper & Scinto

20070042518 - Method of manufacturing an amoled: The present invention relates to a method of manufacturing an AMOLED panel. The method comprises providing a substrate, forming a data line and a drain metal on the substrate, forming a buffer insulator layer, forming an active layer, forming a gate insulator layer, forming a gate metal, performing an ion... Agent: North America Intellectual Property Corporation

20070042519 - Manufacturing method of solid-state imaging device and solid-state imaging device: A manufacturing method of a solid-state imaging device, the device comprising: a semiconductor substrate; photodiodes each comprising a surface-side first conductivity type region formed adjacent to a surface of the semiconductor substrate and a second conductivity type region provided directly under the surface-side first conductivity type region; a second conductivity... Agent: Birch Stewart Kolasch & Birch

20070042520 - Method of manufacturing vertical gan-based light emitting diode: The present invention relates to a method of manufacturing a vertical GaN-based LED. The method includes forming an insulating pattern on a substrate to define LED regions having a predetermined size; sequentially stacking an n-type GaN-based semiconductor layer, an active layer, and a p-type GaN-based semiconductor layer on the substrate... Agent: Mcdermott Will & Emery LLP

20070042522 - Method of fabricating resistive probe having self-aligned metal shield: A method of fabricating a resistive probe having a self-aligned metal shield. The method includes sequentially forming a first insulating layer, a metal shield, and a second insulating layer on a resistive tip of a substrate; etching the second insulating layer to expose the metal shield on a resistive region;... Agent: Sughrue Mion, PLLC

20070042521 - Microelectromechanical devices and fabrication methods: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. An embodiment further includes a buried polysilicon layer and a... Agent: Courtney Staniford & Gregory LLP

20070042523 - Photoelectric current multiplier using molecular crystal and production method therefor: A NTCDA single crystal is used as a photoelectric current multiplier layer, and Au thin films are formed as electrodes on the opposite surfaces of the multiplier layer by a vapor deposition method to form a sandwich type cell. When a voltage is applied to the NTCDA single crystal by... Agent: Rader Fishman & Grauer PLLC

20070042524 - Mems devices having support structures with substantially vertical sidewalls and methods for fabricating the same: Embodiments of MEMS devices include support structures having substantially vertical sidewalls. Certain support structures are formed through deposition of self-planarizing materials or via a plating process. Other support structures are formed via a spacer etch. Other MEMS devices include support structures at least partially underlying a movable layer, where the... Agent: Knobbe, Martens, Olson & Bear, LLP

20070042525 - Laser ablation method for fabricating high performance organic devices: A laser ablation method is utilized to define the channel length of an organic transistor. A substrate is coated with a deposition of a metal or conductive polymer deposition, applied in a thin layer in order to enhance the resolution that can be attained by laser ablation. The laser ablation... Agent: Hogan & Hartson LLP

20070042526 - Metal oxide solid solution, preparation and use thereof: Disclosed is a method for preparing a metal oxide solid solution in nano size. The metal oxide solid solution is prepared by reacting a reactant mixture containing water and at least two water-soluble metal compounds at 200 to 700° C. under a pressure of 180 to 550 bar in a... Agent: Abelman Frayne & Schwab

20070042528 - Defining electrode regions of electroluminescent panel: An electroluminescent panel includes a partial electroluminescent panel base, a layer of electrically isolated conductive areas next to the partial electroluminescent panel base, and an activatable conductive layer next to the layer of electrically isolated conductive areas. The activatable conductive layer is selectively activated to electrically connect selected electrically isolated... Agent: Hewlett Packard Company

20070042527 - Microelectronic package optionally having differing cover and device thermal expansivities: A microelectronic package is provided that includes a microelectronic device and a cover. The device and the cover are typically substantially immobilized relative to each other. The cover typically has a higher coefficient of thermal expansion while the device has a higher effective stiffness. The package may be formed in... Agent: Tessera Lerner David Et Al.

20070042530 - Electronic package for image sensor, and the packaging method thereof: A semiconductor device package and method for its fabrication are provided. The semiconductor device package generally includes at least one semiconductor die and a substrate coupled to the semiconductor die. The semiconductor die is provided with a front side defining a sealing area, and a first solder sealing ring pad... Agent: Rosenberg, Klein & Lee

20070042529 - Methods and apparatus for high-density chip connectivity: Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a... Agent: Fish & Richardson P.C.

20070042531 - Method for producing semiconductor device and semiconductor device: The method of producing a semiconductor device in which chips are resin-molded, including steps of: preparing frames having front and back surfaces and die pads; preparing an insulation resin sheet having a first and a second surfaces; preparing a resin-sealing metal mold having cap pins; mounting the resin sheet inside... Agent: Buchanan, Ingersoll & Rooney PC

20070042532 - System and methods for packing in turnkey services: A system of packing for turnkey services. An input port receives first and second wafer lots from a semiconductor manufacturer. The first wafer lot comprises a first number of dies, and the second wafer lot comprises a second number of dies. A packing device loads dies of the first wafer... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070042533 - Heat conductive silicone grease composition and cured product thereof: Provided is a heat conductive silicone grease composition including (A) 100 parts by mass of an organopolysiloxane containing 2 or more alkenyl groups bonded to silicon atoms within each molecule, (B) an organohydrogenpolysiloxane containing 2 or more hydrogen atoms bonded to silicon atoms within each molecule, in sufficient quantity to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042534 - Chip package and package process thereof: A chip package and a package process thereof are provided. The chip package comprises a package substrate, a chip, a plurality of spacers, an adhesive layer, and a plurality of wires. The package substrate has a carrying surface. The chip is disposed on the carrying surface. The spacers are formed... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070042535 - Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors: A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate... Agent: Texas Instruments Incorporated

20070042536 - Thin film transistor and method for manufacturing the same: A method for manufacturing a thin film transistor of the invention comprises steps of: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming a polysilicon layer on the gate insulating layer; forming an etching-stop layer on the polysilicon layer and corresponding to... Agent: Rabin & Berdo, PC

20070042537 - Method of manufacturing a thin film transistor matrix substrate: A method of manufacturing a thin film transistor matrix substrate is provided. The first photo-mask process is used to define a gate electrode and a signal electrode. The second photo-mask process is used to obtain different thickness of a PR layer in different regions for forming a channel, gate electrode... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070042538 - Methods for preserving strained semiconductor substrate layers during cmos processing: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad... Agent: Goodwin Procter LLP Patent Administrator

20070042539 - Method of manufacturing a non-volatile memory device: In a method of manufacturing a non-volatile memory device, a first gate insulation layer and a conductive layer are formed on a substrate and then the conductive layer is partially oxidized to form an oxide layer pattern. The conductive layer is partially etched using the oxide layer pattern as an... Agent: Mills & Onello LLP

20070042540 - Method of forming a capacitor in a semiconductor device without wet etchant damage to the capacitor parts: To form a capacitor in a semiconductor device, an etching barrier layer and a mold insulating layer are sequentially formed on an interlayer insulating film having a contact plug. A hole exposing the contact plug is formed by etching the mold insulating layer and the etching barrier layer. A first... Agent: Ladas & Parry LLP

20070042541 - Semiconductor device and its manufacture method: A method for manufacturing a semiconductor device by which deterioration in the characteristics of an oxide dielectric capacitor is suppressed and the gap between capacitors and the gap between electrodes can be filled while suppressing generation of voids. The method for manufacturing a semiconductor device comprises the steps of (a)... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070042542 - Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement: A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is... Agent: Brinks Hofer Gilson & Lione Infineon

20070042543 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, the method comprising the steps of: (a) forming a titanium layer above a substrate; (b) forming a barrier layer above the titanium layer; (c) changing the titanium layer to a titanium nitride layer by conducting a heat treatment in a nitrogen containing atmosphere;... Agent: Harness, Dickey & Pierce, P.L.C

20070042545 - Bottom electrode for memory device and method of forming the same: Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap... Agent: Dickstein Shapiro LLP

20070042544 - Low-k spacer structure for flash memory: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070042546 - Method for forming floating gates within nvm process: A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), depositing a layer of polysilicon (62), planarizing the polysilicon layer with a CMP process... Agent: Hamilton & Terrile, LLP

20070042548 - Methods of forming floating gates in non-volatile memory devices including alternating layers of amorphous silicon and ald dopant layers and floating gates so formed: A method of forming a silicon layer on a substrate includes providing a silicon source gas to form an amorphous silicon layer on a substrate and providing a dopant source gas to adsorb dopants onto the amorphous silicon layer to form a dopant layer on a surface of the amorphous... Agent: Myers Bigel Sibley & Sajovec

20070042547 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070042549 - Semiconductor device having reduced effective substrate resistivity and associated methods: A semiconductor device includes at least one device active region formed in a first surface of a semiconductor substrate, an electrical contact layer on a second surface of the semiconductor substrate, and at least one resistivity-lowering body positioned in a corresponding recess in the substrate and connected to the electrical... Agent: Hiscock & Barclay, LLP

20070042552 - Method for fabricating a semiconductor device: A process for fabricating a power semiconductor device is disclosed.... Agent: Ostrolenk Faber Gerb & Soffen

20070042550 - Method for fabricating a semiconductor structure having selective dopant regions: A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070042551 - Method of manufacturing a trench transistor having a heavy body region: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the... Agent: Townsend And Townsend And Crew, LLP

20070042553 - Fabrication method for semiconductor memory components: A storage layer sequence (20) and gate electrodes (34) are arranged on a substrate (10). The gate electrodes (34) may be fabricated in a gate electrode layer (22) made of electrically conductively doped polysilicon. Apart from an optional barrier layer (45), the word lines are solely formed from a material... Agent: Slater & Matsil LLP

20070042554 - Methods of forming sram cells having landing pad in contact with upper and lower cell gate patterns: SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting... Agent: Myers Bigel Sibley & Sajovec

20070042555 - Formation of uniform silicate gate dielectrics: The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising... Agent: Texas Instruments Incorporated

20070042556 - Method of fabricating metal oxide semiconductor transistor: A method of fabricating a metal oxide semiconductor transistor is described. A substrate having device isolation structures thereon is provided. A stack gate structure is formed over the substrate. An etching stop layer is formed over the substrate to cover the stack gate structure, the substrate and the device isolation... Agent: Jianq Chyun Intellectual Property Office

20070042557 - Data download to imager chip using image sensor as a receptor: An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to control the imaging operations. The data-input can be based upon variations in light color, value, intensity, and patterning, or any combinations of the... Agent: Dickstein Shapiro LLP

20070042558 - Process for manufacturing a high-quality soi wafer: In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body of semiconductor material having a front face, a buried cavity, which extends at a distance from the front face and delimits, with the front face, a surface region of the monolithic body,... Agent: Graybeal Jackson Haley LLP

20070042559 - Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment: The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided dielectric layer (520) over a substrate (310), the nitrided dielectric... Agent: Texas Instruments Incorporated

20070042560 - Method for growing thin nitride film onto substrate and thin nitride film device: The present invention provides a method for growing a thin nitride film over a substrate and a thin nitride film device, in which the polarity of the thin nitride film can be controlled by a low temperature process. In the method for growing the thin nitride film over a substrate,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042561 - Semiconductor device and productioin method thereof: A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP-type semiconductor device, which is configured so that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with... Agent: Rader Fishman & Grauer PLLC

20070042562 - Integrated circuit device: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation,... Agent: Tessera Lerner David Et Al.

20070042564 - Semiconductor including sti and method for manufacturing the same: Provided is a semiconductor device and method of making, incorporating a trench having rounded edges. According to an embodiment, a pad oxide layer, nitride layer, and TEOS layer are sequentially formed on a substrate. The TEOS layer, nitride layer, and pad oxide layer are dry-etched using a photosensitive layer pattern... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070042563 - Single crystal based through the wafer connections technical field: A through-the-wafer (TTW) electrically conductive connection can be produced in a heavily doped substrate. An annular trench is created from one side of the wafer such that the trench almost reaches the second side of the wafer. The annular trench can be filled with an electrically insulating material. Alternatively, an... Agent: Kris T. Fredrick Honeywell International Inc.

20070042565 - Fluidic mems device: A method of manufacturing a fluidic MEMS package includes attaching a cover plate with a plurality of openings to a substrate with a plurality of bond rings with breaches such that the cover plate, the substrate and the bond rings define a plurality of respective inner cavities. The cover plate,... Agent: Hewlet-packard Company Intellectual Property Administration

20070042566 - Strained silicon on insulator (ssoi) structure with improved crystallinity in the strained silicon layer: This invention generally relates to strained silicon on insulator (SSOI) structure, and to a process for making the same. The process includes a high temperature thermal anneal of a SSOI structure to improve the crystallinity of the strained silicon layer, while maintaining the strain present therein.... Agent: Senniger Powers

20070042567 - Process for producing silicon wafer: A process for producing a silicon wafer comprising a single-wafer etching step of performing an etching by supplying an etching solution through a supplying-nozzle to a surface of a single and a thin-discal wafer obtained by slicing a silicon single crystal ingot and rotating the wafer to spread the etching... Agent: Kolisch Hartwell, P.C.

20070042568 - Semiconductor device with a thinned semiconductor chip and method for producing the thinned semiconductor chip: A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070042572 - Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates: Methods are provided for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects. Amorphous SiGe layers are deposited by CVD from trisilane and GeH4. The amorphous SiGe layers are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also... Agent: Knobbe Martens Olson & Bear LLP

20070042569 - Low temperature formation of patterned epitaxial si containing films: A method for selectively forming an epitaxial Si containing film on a semiconductor structure at low temperature. The method includes providing the structure in a process chamber, the structure containing a Si substrate having an epitaxial Si surface area and a patterned film area thereon. A Si film is non-selectively... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042571 - Method of forming group-iii nitride crystal, layered structure and epitaxial substrate: Heat treatment is conducted at a predetermined temperature of not less than 1250° C. on an underlying substrate obtained by epitaxially forming a first group-III nitride crystal on a predetermined base as an underlying layer. Three-dimensional fine irregularities resulting from crystalline islands are created on the surface of the underlying... Agent: Burr & Brown

20070042570 - Sequential deposition process for forming si-containing films: A method is provided for forming a Si film in sequential deposition process. The method includes providing a substrate in a process chamber, forming a chlorinated Si film by exposing the substrate to a chlorinated silane gas, and dry etching the chlorinated Si film to reduce the chlorine content of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042573 - Methods of forming conductive polysilicon thin films via atomic layer deposition and methods of manufacturing semiconductor devices including such polysilicon thin films: A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a... Agent: Myers Bigel Sibley & Sajovec

20070042574 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device that can prevent short-circuiting between gate electrodes and increases in the leakage current of a capacitive insulating film caused by the bottom electrode of the capacitor is provided. The method for manufacturing a semiconductor device according to the present invention comprises a first... Agent: Mcdermott Will & Emery LLP

20070042575 - Crystallization apparatus and method of amophous silicon: A plurality laser beams generated by a plurality of beam generators are synthesized by a beam synthesizer. The synthesized beam is splitted into a plurality of beamlets and provided for a plurality of optical units controlling the beamlets. Each beamlet controlled by each optical unit is illuminated onto an amorphous... Agent: F. Chau & Associates, LLC

20070042576 - Stable, water-soluble quantum dot, method of preparation and conjugates thereof: A method for manufacturing powdered quantum dots comprising the steps of: a) reacting quantum dots comprising a core, a cap and a first ligand associated with the outer surfaces thereof with a second ligand, the second ligand displacing the first ligand and attaching to the outer surfaces of the quantum... Agent: Birch Stewart Kolasch & Birch

20070042577 - Method of preparing a film layer-by-layer using plasma enhanced atomic layer deposition: A method for forming a thin film on a substrate layer by layer using plasma enhanced atomic layer deposition is described. The method comprises using a low power reduction step for at least one cycle in order to substantially avoid partial layer film growth, followed by using a high power... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070042578 - Method for making junction and processed material formed using the same: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to... Agent: Mcdermott Will & Emery LLP

20070042579 - System and method for ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits: A system and method for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070042580 - Ion implanted insulator material with reduced dielectric constant: An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material... Agent: Law Office Of Robert M. Wallace

20070042581 - Manufacturing method of semiconductor device and substrate processing apparatus: The method comprises a step of forming a film containing the metal atom and the silicon atom on a substrate 30 in a reaction chamber 4, and performing a nitriding process for the film, wherein the film is formed by changing a silicon concentration at least in two stages in... Agent: Oliff & Berridge, PLC

20070042582 - Method of forming a nanowire and method of manufacturing a semiconductor device using the same: In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire... Agent: Mills & Onello LLP

20070042583 - Semiconductor device and method of manufacturing the same: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed... Agent: Marger Johnson & Mccollom, P.C.

20070042584 - Method of forming a silicide: At least one gate electrode is formed on a substrate. A first dielectric layer and a second dielectric layer are formed on the gate electrode, respectively. A portion of the second dielectric layer is removed to form a spacer on either side of the gate electrode. A portion of the... Agent: North America Intellectual Property Corporation

20070042585 - Method of forming metal plate pattern and circuit board: A method of forming a high aspect ratio metal plate pattern or circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one or two surfaces of a copper plate (10) and patterned into a resist pattern. A tin plating layer (14) is... Agent: Chadbourne & Parke L.l.p

20070042586 - Stabilization of ni monosilicide thin films in cmos devices using implantation of ions before silicidation: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation... Agent: Scully, Scott, Murphy & Presser, P.C.

20070042589 - Composite inter-level dielectric structure for an integrated circuit: A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on... Agent: Mayer & Williams PC

20070042590 - Method for maufacturing semiconductor device: A diffusion barrier film which covers the surface of a first insulating film provided on an upper surface of a semiconductor substrate, a second insulating film which covers over the diffusion barrier film, and a cap film which covers the second insulating film, are sequentially laminated. A wiring trench portion,... Agent: Volentine Francos, & Whitt PLLC

20070042587 - Method of forming a catalyst layer on the barrier layer of a conductive interconnect of a semiconductor device: A method is provided for depositing a conductive material in a sub-micron recessed feature formed on a substrate. The method begins by depositing a barrier layer over a dielectric layer disposed on the substrate while under a vacuum of the type found in a vacuum chamber. A catalytic layer is... Agent: Mayer & Williams PC

20070042588 - Single damascene with disposable stencil and method therefore: In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited... Agent: Slater & Matsil LLP

20070042592 - Novel approach to high temperature wafer processing: At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows... Agent: Kris T. Fredrick Honeywell International Inc.

20070042591 - Signal routing on redistribution layer: A semiconductor wafer has a dielectric layer, a metal last layer, a passivation layer, and a redistribution layer. The metal last layer is formed over the dielectric layer, and the metal last layer has first and second locations that are spaced apart from each other. The passivation layer is formed... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070042593 - Bonding pad structure and method of forming the same: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer... Agent: Thomas, Kayden, Hostemeyer & Risley LLP

20070042594 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes providing a base plate; mounting a plurality of semiconductor chips each having a plurality of connection pads formed on an upper surface thereof to the base plate, the plural semiconductor chips being mounted apart from each other; forming an insulating film on... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070042595 - Packaging of electronic chips with air-bridge structures: A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070042597 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which prevention of disconnection due to a step caused by a surface shape before film formation, control of increase in the cost in forming an insulating film over a large-sized substrate, improvement... Agent: Nixon Peabody, LLP

20070042596 - Method of forming an interconnect structure for a semiconductor device: A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrate as well as from the... Agent: Dickstein Shapiro LLP

20070042598 - Dielectric with sidewall passivating layer: A polymer dielectric material includes a sidewall passivating layer on the opposing sidewall surfaces of an opening in the dielectric layer for a via or trench. The sidewall passivating layer may be deposited on the sidewall surfaces, as well as the bottom surface of an opening having a first depth... Agent: Trop Pruner & Hu, PC

20070042600 - Method for fabricating semiconductor device: In a Cu interconnect process, an organic-based low-dielectric-constant interlayer film is formed, and then a protective film is deposited on the side and back surfaces of a wafer bevel and the back surface of a wafer edge. Thereafter, a lithography process and an etching process are carried out, a copper... Agent: Mcdermott Will & Emery LLP

20070042599 - Methods to facilitate etch uniformity and selectivity: A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered.... Agent: Texas Instruments Incorporated

20070042604 - Copolymers, polymer resin composition for buffer layer method of forming a pattern using the same and method of manufacturing a capacitor using the same: wherein the variables L, M and N represent the relative molar fractions of the monomers and satisfy the expressions 0<L≦0.8; 0<M≦0.25; 0<N≦0.35; and L+M+N=1; and, wherein R1, R2 and R3 are independently selected from C1-C6 alkyls and derivatives thereof. The invention is also directed to polymer compositions that, when used... Agent: Harness, Dickey & Pierce, P.L.C

20070042602 - Etch method using supercritical fluids: Methods are described for removing a material from a substrate by dissolving an etchant into a solvent to form a solution; and exposing the substrate to the solution so that the etchant in the solution removes material from the substrate; wherein during the exposure the solution is maintained in a... Agent: Fish & Richardson PC

20070042603 - Method for etching having a controlled distribution of process results: Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to... Agent: Patterson & Sheridan, LLP Applied Materials Inc

20070042601 - Method for etching high dielectric constant materials: In one implementation, a method is provided for etching a high k dielectric material in a plasma etch reactor, the method comprising plasma etching the high k dielectric material with a first plasma gas reactant mixture having BCl3. The high k dielectric material may include Al2O3 in a stack having... Agent: Aagaard & Balzan, LLP

20070042605 - Method of etching a substrate and method of forming a feature on a substrate: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing... Agent: Wells St. John P.s.

20070042606 - Creating novel structures using deep trenching of oriented silicon substrates: A potassium hydroxide (KOH) etch process can produce deep high aspect ratio trenches in (110) oriented silicon substrates. The trenches, however, are perpendicular to the (111) direction of the silicon substrate's crystal lattice. The trenches are used to produce thermally isolating areas and through the wafer electrical connections. These structures... Agent: Attorney, Intellectual Property Honeywell International, Inc.

20070042607 - Etch features with reduced line edge roughness: A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the... Agent: Beyer Weaver & Thomas, LLP

20070042608 - Method of substantially uniformly etching non-homogeneous substrates: A method of substantially uniformly etching oxides from non-homogeneous substrates is provided. The method utilizes a substantially non-aqueous etchant including an organic solvent and a fluorine-containing compound. The fluorine containing compound may include HF, HF:NH4F, (NH4)HF2, or TMAF:HF and mixtures thereof. The etchant may be applied to chemically non-homogeneous layers... Agent: Dinsmore & Shohl LLP One Dayton Centre

20070042610 - Method of depositing low k barrier layers: A method is provided for processing a substrate including providing a processing gas comprising an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in damascene or dual damascene applications... Agent: Patterson & Sheridan, LLP

20070042609 - Molecular caulk: a pore sealant for ultra-low k dielectrics: Methods of use of parylene based polymers with porous ultra-low κ dielectric materials and use of parylene barriers in integrated circuit fabrication are presented.... Agent: Heslin Rothenberg Farley & Mesiti PC

20070042611 - Method of producing a trench in a photo-resist on a iii-v wafer and a compound wafer having a photo-resist including such a trench: A method of producing a trench in a photo-resist on a III-V wafer comprising providing a III-V wafer; providing a photo-resist on the wafer; exposing the photo-resist to UV radiation through a mask; removing one of the exposed or non-exposed portions of the photo-resist to produce a recess; applying a... Agent: Howard & Howard Attorneys, P.C.

20070042612 - Method for manufacturing semiconductor device: It is made possible to form a silicon nitride film, an aluminum oxide film and a transition metal high-k insulation film of high quality. A manufacturing method includes: forming an insulation film having at least one kind of bonds selected out of silicon-nitrogen bonds, aluminum-oxygen bonds, transition metal-oxygen-silicon bonds, transition... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070037299 - Low power magnetoresistive random access memory elements: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070037298 - Semiconductor device with ferroelectric capacitor and fabrication method thereof: A semiconductor device fabrication method includes the steps of forming a conductive plug in an insulating film so as to be connected to an element on a semiconductor substrate; forming a titanium aluminum nitride (TiAlN) oxygen barrier film over the conductive plug; forming a titanium (Ti) seed film over the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070037301 - Method and apparatus for monitoring precision of wafer placement alignment: A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the... Agent: Brinks Hofer Gilson & Lione Infineon

20070037300 - Systems and methods for plasma processing of microfeature workpieces: Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured... Agent: Perkins Coie LLP Patent-sea

20070037303 - Apparatus and method of illuminating the surface of a wafer in a wafer inspection system: An apparatus for illuminating the surface of a wafer in a wafer inspection system, comprising a first flash source for emitting a first light beam and a second flash source for emitting a second light beam, a redirecting optics and a control means, wherein the flash sources are arranged for... Agent: Simpson & Simpson, PLLC

20070037302 - Method of preparing electrode: Methods of preparing electrodes, as well as related devices, components, systems, and methods, are disclosed.... Agent: Attn: Tony Zhang Konarka Technologies, Inc.

20070037304 - Method for manufacturing semiconductor device and semiconductor device: In a method for manufacturing a semiconductor device, insulation resistance of the porous film is stabilized, and leakage current between adjacent interconnects provides an improved reliability in signal propagation therethrough. The method includes: sequentially forming over a semiconductor substrate a porous film and a patterned resist film; forming a concave... Agent: Young & Thompson

20070037306 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes: forming a protrusion-patterned layer on a substrate, the protrusion-patterned layer including a plurality of separated protrusions, each of which includes a base portion formed on the substrate and a top end portion opposite to the base portion; laterally growing a base layer... Agent: Foley And Lardner LLP Suite 500

20070037305 - Method of manufacturing semiconductor light- emitting device and semiconductor light-emitting device: A semiconductor light-emitting device and method for manufacturing the semiconductor light-emitting device includes a mask layer etching process on first and second mask layers provided on a Group-III nitride-based compound semiconductor substrate, the mask layer with a higher etching rate being closer to the p-type semiconductor layer; a semiconductor layer... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070037307 - Method of forming three-dimensional features on light emitting diodes for improved light extraction: A method is disclosed for obtaining a high-resolution lenticular pattern on the surface of a light emitting diode. The method comprises imprinting a patterned sacrificial layer of etchable material that is positioned on a semiconductor surface that is in turn adjacent a light emitting active region, and thereafter etching the... Agent: Summa, Allan & Additon, P.A.

20070037308 - Method for manufacturing gan semiconductor light-emitting element: A method for manufacturing a GaN semiconductor light-emitting element is provided. The method for manufacturing a GaN semiconductor light-emitting element includes forming, by crystal growth, a first GaN compound semiconductor layer of a first conductivity type, the top face of which corresponds to the A plane, an active layer composed... Agent: Bell, Boyd & Lloyd, LLC

20070037309 - Semiconductor device and method for manufacturing the same: The TFT electric characteristic is ready to be influenced by the channel region in the neighborhood of an interface between a semiconductor and a gate insulating film. The present invention provides TFTs reduced in electric characteristic deviations and a method for manufacturing the same. The invention forms a region or... Agent: Nixon Peabody, LLP

20070037310 - Semiconductor sensor production method and semiconductor sensor: A semiconductor sensor production method includes the steps of (A) forming a first etching mask layer on a support part segment of a backside semiconductor layer, except on a portion of the support part segment which portion is along edges of the support part segment; (B) forming a second etching... Agent: Cooper & Dunham, LLP

20070037311 - Manufacturing method of microelectromechanical system: To provide a method of easily forming a three-dimensional structure typified by a cantilever by using a thin film formed over an insulating surface, and provide a microelectromechanical system formed by such a method. A three-dimensional structure typified by a cantilever is formed by using a mask having a nonuniform... Agent: Fish & Richardson P.C.

20070037313 - Cmos image sensor and manufacturing method thereof: Disclosed are a CMOS image sensor and a manufacturing method thereof. The method includes forming an isolation layer in a semiconductor substrate, defining an active region including a photo diode region and a transistor region; forming a gate insulating layer and a gate electrode on the transistor region; forming a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070037312 - Image sensor and fabrication method thereof: Example embodiments relate to an image sensor and a fabrication method thereof, capable of reducing dark current and a fabrication method thereof. The image sensor may include a semiconductor substrate including an active region defined by an isolation layer, a photoelectric-conversion region and a charge-movement-prevention region formed at an interface... Agent: Harness, Dickey & Pierce, P.L.C

20070037314 - Method for fabricating image sensor without lto-based passivation layer: A method for fabricating an image sensor including a first region, which is a light receiving region, and a second region, which is a pad region, includes forming a metal line in the second region over a substrate structure comprising a photodiode, forming a passivation layer over the substrate structure,... Agent: Morgan Lewis & Bockius LLP

20070037315 - Silicone metalization: A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide... Agent: Eddie E. Scott Attorney

20070037316 - Memory cell contact using spacers: A method of forming contacts used in a memory device. The method involves forming a via in an insulating layer, forming spacers on sidewalls of the via, and filling the via with a conductive material. The resulting contact has rounded upper corners to improve the reliability of the memory device.... Agent: Dickstein Shapiro LLP

20070037318 - Method and apparatus for flip-chip bonding: Provided are a laser flip-chip bonding method having high productivity and excellent bonding reliability and a flip-chip bonder employing the same. The flip-chip bonder includes: a bonding stage on which a substrate rests; a bonding head picking up a semiconductor chip and attaching the semiconductor chip to the substrate; and... Agent: Gardner Carton & Douglas LLP Attn: Patent Docket Dept.

20070037317 - Method and device for attaching a chip in a housing: A method and the associated device for attaching at least one micromechanical chip in a housing which is optically transparent to radiation of at least one predefined transmission wavelength, in which an adhesive layer is applied between the chip and the housing and the adhesive layer is irradiated through the... Agent: Kenyon & Kenyon LLP

20070037320 - Multichip packages with exposed dice: Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip... Agent: Beyer Weaver & Thomas, LLP

20070037319 - Semiconductor package with contact support layer and method to produce the package: A semiconductor package comprises a substrate which includes a plurality of conducting traces and upper contact areas on its upper surface and a second plurality of lower conductive traces and external contact areas on its bottom surface and external conducting members attached to the external contact areas. The semiconductor package... Agent: Edell, Shapiro & Finnan, LLC

20070037321 - semiconductor device and a manufacturing method of the same: The semiconductor device having the structure which laminated the chip in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070037322 - End electrode structure of a surface-mounted resettable over-current protection device: The present invention relates to an end electrode structure of a surface-mounted resettable over-current protection device. A polymer-based sheet is punched with a mold for manufacturing a plurality of H-shaped through-holes separated at an equal interval, such that several strip-shaped sheets are formed. Then, a first pair of electrodes and... Agent: Ladas & Parry LLP

20070037325 - After deposition method of thinning film to reduce pinhole defects: A method of forming a thin film is provided in which a film having a first thickness is deposited over a substrate, wherein the first thickness is greater than a thickness at which the initially deposited film begins to dewet from the substrate. The initially deposited film is then stabilized... Agent: International Business Machines Corporation Dept. 18g

20070037323 - Manufacturing strained silicon substrates using a backing material: A method for forming a strained silicon layer of semiconductor material. The method includes providing a deformable surface region having a first predetermined radius of curvature, which is defined by R(l) and is defined normal to the surface region. A backing plate is coupled to the deformable surface region to... Agent: Townsend And Townsend And Crew, LLP

20070037324 - Process for producing an mos transistor and corresponding integrated circuit: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the... Agent: Jenkens & Gilchrist, PC

20070037328 - Method of manufacturing a non-volatile memory device: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070037326 - Shallow source/drain regions for cmos transistors: A transistor having shallow, high-dopant concentration source/drain regions is provided. A gate electrode is formed on a substrate, and the source/drain regions of the substrate are transformed into an amorphous state by, for example, implanting Si, Ge, Xe, In, Ar, Kr, Rn, a combination thereof, or the like ions. A... Agent: Slater & Matsil, L.L.P.

20070037327 - Structure and method for forming inter-poly dielectric in a shielded gate field effect transistor: A shielded gate trench FET is formed as follows. A trench is formed in a silicon region of a first conductivity type, the trench including a shield electrode insulated from the silicon region by a shield dielectric. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer... Agent: Townsend And Townsend And Crew, LLP

20070037329 - Growing [110] silicon on [001] oriented substrate with rare-earth oxide buffer film: An assembly and method of making the same wherein the assembly incorporates a rare-earth oxide film to form a [110] crystal lattice orientation semiconductor film. The assembly comprises a substrate, a rare-earth oxide film formed on the substrate, and a [110]-oriented semiconductor film formed on the rare-earth oxide film. The... Agent: Blakely Sokoloff Taylor & Zafman

20070037330 - Evaluation method of semiconductor device, manufacturing method of the semiconductor device, design management system of device comprising the semiconductor device, dose amount control program for the semiconductor device, computer-readable recording medi: There is provided a new method of obtaining the dopant activation rate of a device accurately and simply in a different way from a method of obtaining a carrier density with use of a Hall measurement or CV measurement, and also provided a production method of a device performed with... Agent: Nixon Peabody, LLP

20070037332 - Laser irradiation apparatus, laser irradiation method, and method for manufacturing semiconductor device: In order to solve the problem, a pulsed laser beam 1 having a wavelength absorbed sufficiently in the semiconductor film is used in combination with a laser beam 2 having a high output and having a wavelength absorbed sufficiently in the melted semiconductor film. After irradiating the laser beam 1... Agent: Eric Robinson

20070037331 - Laser irradiation method, laser irradiation apparatus, and semiconductor device: An object of the present invention is obtaining a semiconductor film with uniform characteristics by improving irradiation variations of the semiconductor film. The irradiation variations are generated due to scanning while irradiating with a linear laser beam of the pulse emission. At a laser crystallization step of irradiating a semiconductor... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070037335 - Dual work function cmos devices utilizing carbide based electrodes: Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work... Agent: Texas Instruments Incorporated

20070037337 - Manufacturing method of semiconductor device: A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070037334 - Memory device and method of manufacturing a memory device: The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070037336 - Semiconductor device with improved gate resistance and method of its manufacture: A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch... Agent: Marger Johnson & Mccollom, P.C.

20070037333 - Work function separation for fully silicided gates: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal is added to a first region of polysilicon overlying a dielectric that is on a substrate, and a second metal is added to a second region of the polysilicon. A third metal is... Agent: Texas Instruments Incorporated

20070037338 - Cmos image sensor and manufacturing method thereof: Provided is a CMOS (complementary metal oxide semiconductor) image sensor and a manufacturing method therof, In the method, a photodiode, an interlayer insulating layer, a color filter layer, and a planarizing layer are sequentially formed on a substrate. A photoresist is applied on the planarizing layer. The photoresist is selectively... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20070037339 - Semiconductor circuit arrangement with trench isolation and fabrication method: An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insulating function between adjacent components, the patterning of the charge-storing layer and also the... Agent: Brinks Hofer Gilson & Lione

20070037340 - Fabrication method for fabricating a semiconductor structure and semiconductor structure: In a method for fabricating a semiconductor structure a semiconductor substrate comprising an active region with an uncovered top side is provided, at least one STI trench adjoining the active region is formed, and an STI divot is formed in the insulating filling. The at least one STI trench comprises... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070037341 - Method and structure for shallow trench isolation during integrated circuit device manufacture: A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises etching through silicon nitride and pad oxide layers and into a semiconductor wafer to form a trench into the wafer. A shallow trench isolation (STI)... Agent: Micron Technology, Inc.

20070037342 - Method to obtain fully silicided poly gate: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them.... Agent: Texas Instruments Incorporated

20070037343 - Process for manufacturing dual work function metal gates in a microelectronics device: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a... Agent: Texas Instruments Incorporated

20070037344 - Semiconductor device and method for fabricating the same: The semiconductor device comprises a semiconductor substrate 10, a conducting film 20 formed on the semiconductor substrate 10 and including two conductor patterns adjacent to each other; an etching stopper film covering the upper surface of the conducting film 20; an insulation film 28 which includes a contact hole which... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070037345 - Memory cell array and memory cell: A method of forming a memory cell array including a plurality of memory cells includes patterning isolation trenches on a semiconductor substrate and filling with an insulating material to define active area lines. In particular, the isolation trenches are patterned as straight lines, resulting in the active area lines being... Agent: Edell, Shapiro & Finnan, LLC

20070037347 - Capacitor of semiconductor device and method of fabricating the same: A capacitor of a semiconductor device includes an oxide layer pattern including a trench formed on a semiconductor substrate, the trench having an inner wall and a bottom, quantum dots discontinuously formed on the inner wall of the trench, a bottom electrode formed on the inner wall and the bottom... Agent: F. Chau & Associates, LLC

20070037346 - Rapid thermal annealing of targeted thin film layers: A method for rapid thermal annealing of thin film layers is provided. The method directs a series of pulses or flashes of heat energy toward a targeted layer on a substrate. Each pulse may be at a first temperature range sufficient to anneal the targeted layer, but has a duration... Agent: Greenberg Traurig, LLP

20070037348 - Method of fabricating trench isolation of semiconductor device: In a method of fabricating a trench isolation structure of a semiconductor device, excellent gap filling properties are attained, without the generation of defects. In one aspect, the method comprises: loading a substrate with a trench formed therein into a high-density plasma (HDP) chemical vapor deposition apparatus; primarily heating the... Agent: Mills & Onello LLP

20070037349 - Method of forming electrodes: To form a semiconductor device, a plurality of upwardly extending conductors can be formed. The conductors extend outward from a surface of a semiconductor body, adjacent ones of the conductors being separated from each other by a separating material. At least one support structure is formed between adjacent ones of... Agent: Slater & Matsil LLP

20070037350 - Flash memory cell having reduced floating gate to floating gate coupling: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric... Agent: Blakely Sokoloff Taylor & Zafman

20070037351 - Method of fabricating a resistance based memory device and the memory device: Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device... Agent: Harness, Dickey & Pierce, P.L.C

20070037352 - Display device and manufacturing method of display device: According to one feature of the present invention, a display device is manufactured according to the steps of forming a semiconductor layer; forming a gate insulating layer over the semiconductor layer; forming a gate electrode layer over the gate insulating layer; forming source and drain electrode layers in contact with... Agent: Eric Robinson

20070037353 - Efficient transistor structure: An integrated circuit comprises a first drain region having a symmetric shape across at least one of horizontal and vertical centerlines. A first gate region has a first shape that surrounds the first drain region. A second drain region has the symmetric shape. A second gate region has the first... Agent: Harness, Dickey & Pierce P.L.C

20070037354 - Semiconductor device having a structure to improve contact processing margin, and method of fabricating the same: A method for fabricating a semiconductor device includes forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate; forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern; forming a second insulating pattern... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070037355 - Esd protection device for high voltage: An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically... Agent: Slater & Matsil, L.L.P.

20070037356 - Method of manufacture of raised source drain mosfet with top notched gate structure filled with dielectric plug: A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack... Agent: Graham S. Jones, Ii

20070037357 - Method for removing photoresist using a thermal bake in the presence of hydrogen and a semiconductor device manufactured using the same: The present invention provides a method for removing photoresist, and a method for manufacturing a semiconductor device. The method for removing photoresist, without limitation, may include subjecting a photoresist layer (210) located over a substrate (110) to a thermal bake (410) in the presence of hydrogen, and then removing the... Agent: Texas Instruments Incorporated

20070037358 - Apparatus for etching a glass substrate: An apparatus for etching a glass substrate includes a container for receiving an etching solution and at least two rollers disposed in the container. The at least two rollers may face with each other. The glass substrate is inserted between the at least two rollers, and the glass substrate is... Agent: Harness, Dickey & Pierce, P.L.C

20070037359 - Method of forming align key in well structure formation process and method of forming element isolation structure using the align key: A method of forming an align key in a well structure formation process is provided. The method includes: providing a semiconductor substrate having an align key region and a first well region and forming a first ion implantation mask on the substrate. The first ion implantation mask has a groove... Agent: F. Chau & Associates, LLC

20070037361 - Method for forming void-free trench isolation layer: Disclosed method for forming void-free isolation comprises the steps of: forming a trench in an isolation region in a semiconductor substrate; and forming a filling oxide on the semiconductor substrate to fill the trench. The filling oxide is formed by HDP-CVD process and by using reactant gas mixture that includes... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070037360 - Semiconductor device using epi-layer and method of forming the same: A method of fabricating a semiconductor device includes forming a pad oxide film and a nitride film on a semiconductor substrate; exposing the semiconductor substrate by selectively etching the pad oxide film and the nitride film; forming a trench in the exposed semiconductor substrate; forming a gap-fill dielectric film in... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070037362 - Method and apparatus for integrating iii-v semiconductor devices into silicon processes: Method and apparatus for fabricating semiconductor devices, for example, III-V semiconductor devices, having a desired substrate, for example, a silicon substrate. A method for fabricating semiconductor devices includes providing a semiconductor wafer that includes a plurality of semiconductor structures attached to a native substrate formed of a first substrate material,... Agent: Avago Technologies, Ltd.

20070037363 - Method for forming a brittle zone in a substrate by co-implantation: The invention concerns a method for making a thin film, which consists in creating a brittle zone embedded by implantation of a chemical species in a substrate, so as to be able subsequently to provoke a fracture of the substrate along said brittle zone to separate therefrom said thin film.... Agent: Brinks Hofer Gilson & Lione

20070037364 - Method for manufacturing semiconductor chip: It is the object of the invention to provide a method for manufacturing a semiconductor chip capable of obtaining a semiconductor chip at a high manufacturing efficiency without damages. The invention is a method for manufacturing a semiconductor chip, which comprises a tape adhesion step of sticking a pressure sensitive... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070037365 - Semiconductor nanostructures and fabricating the same: During the growth of semiconductor nanowires on a substrate, different respective vapor-liquid-solid reactions that respectively form target segments and sacrificial segments of the semiconductor nanowires at growth locations defined by catalyst particles are supported. The sacrificial segments of the semiconductor nanowires are selectively removed to form semiconductor nanostructures corresponding to... Agent: Agilent Technologies Inc.

20070037366 - Method of crystallizing amorphous semiconductor film: A method of crystallizing a non-monocrystalline semiconductor film, including forming a non-monocrystalline semiconductor film on a substrate, subjecting the non-monocrystalline semiconductor film to a dehydrogenation treatment by way of at least one kind of heat treatment which is selected from the group consisting of irradiating flash lamp beam to a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070037367 - Apparatus for plasma doping: A doping device is provided having a vacuum container defining a chamber therein. The container has a portion made of dielectric material and bears an impurity to be doped in a substrate provided in the chamber. Also provided is a plasma source for generating a plasma in the chamber by... Agent: Wenderoth, Lind & Ponack L.L.P.

20070037368 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device includes a processing step of high-energy ion implantation. After performing the high-energy ion implantation process and before beginning a thermal process, a buffer layer is partially removed together with particles or contaminants that may be generated from the ion implantation process. Surface defects... Agent: Mills & Onello LLP

20070037369 - Method of manufacturing silicon carbide semiconductor device: A manufacturing method for forming a region into which impurity ions are implanted, and an electrode is coupled to the region, in a self-aligned manner. An oxide film is formed on an n-type semiconductor layer composed of a silicon carbide semiconductor, and then the oxide film on regions in which... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070037370 - Method and apparatus for high-efficiency synthesis of carbon nanostructure, and carbon nanostructure: A high-efficiency synthesis method of carbon nanostructure according to the present invention is a high-efficiency synthesis method of carbon nanostructure, the method comprising: bringing raw material gas and a catalyst into contact with each other under reactive conditions so as to produce a carbon nanostructure, wherein: the initiation of contact... Agent: Harness, Dickey & Pierce, P.L.C

20070037371 - Method of forming gate electrode structures: In one example, the method includes forming a patterned hard mask feature above a layer of gate electrode material, the hard mask feature having a photoresist feature formed thereabove and the hard mask feature having a critical dimension. The method further includes performing an etching process on the patterned hard... Agent: Williams, Morgan & Amerson

20070037372 - Planarizing a semiconductor structure to form replacement metal gates: A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.... Agent: Trop Pruner & Hu, PC

20070037373 - Salicide process utilizing a cluster ion implantation process: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting... Agent: North America Intellectual Property Corporation

20070037374 - Semiconductor device and its manufacturing method: A semiconductor device comprising a wiring suitable for miniaturization and manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising an insulator formed above a semiconductor substrate, and a wiring formed in the insulator and having surface roughness capable of... Agent: Foley And Lardner LLP Suite 500

20070037375 - Semiconductor memory devices having contact pads with silicide caps thereon: An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad... Agent: Myers Bigel Sibley & Sajovec

20070037376 - Method and apparatus for fine pitch solder joint: According to one embodiment of the invention, a method of assembling a package has been provided that includes coupling a plurality of solder balls to a first surface of a substrate. At least one of the plurality of solder balls is in communication with a trace that extends from the... Agent: Texas Instruments Incorporated

20070037377 - Tin-silver solder bumping in electronics manufacture: A process for forming a solder bump on an under bump metal structure in the manufacture of a microelectronic device comprising exposing the under bump metal structure to an electrolytic bath comprising a source of Sn2+ ions, a source of Ag+ ions, a thiourea compound and/or a quaternary ammonium surfactant;... Agent: Senniger Powers

20070037378 - Method for forming metal pad in semiconductor device: A method for manufacturing a metal pad connected to a metal line in a semiconductor device is provided. The method includes forming an interlevel dielectric (ILD) layer on a substrate; forming at least one metal line on the ILD layer; forming a metal barrier on the ILD layer and the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070037379 - 3d ic method and device: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070037380 - Controlling lateral distribution of air gaps in interconnects: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20070037381 - Method for fabricating al metal line: Disclosed is a method for fabricating an Al metal line. The method includes forming an insulating layer on a semiconductor substrate; forming a Ti layer, a bottom TiN layer, an Al layer and a top TiN layer in successive order on the insulating layer; plasma-treating the top TiN layer; forming... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070037382 - Semiconductor device having a multilayer interconnection structure, fabrication method thereof, and designing method thereof: A semiconductor device includes an interconnection structure in which via-plug density is higher in an upper layer part than a lower layer part, wherein the peeling of the lower via-plugs at the time of formation of the upper-via-plugs is avoided by restricting the density of the upper s, defined for... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070037383 - Method for damascene process: Disclosed are methods for carrying out a damascene process in semiconductor fabrication including the steps of: forming an intermetal dielectric film on a semiconductor substrate; patterning the intermetal dielectric film and forming an intermetal dielectric pattern comprising at least two layers of different chemical compositions that includes at least an... Agent: Mills & Onello LLP

20070037384 - A method for processing ic designs for different metal beol processes: A method for processing IC designs for different metal BEOL processes is provided for enabling fabricating using a metal fabrication process an IC originally having a backend design for a different metal fabrication process. The method first determines layer constructions of an original design of an IC for a first... Agent: Zeming M. Gao 3law Techlaw Services

20070037385 - Metal interconnect structure and method: A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive... Agent: Slater & Matsil LLP

20070037386 - Sloped thin film substrate edges: A photoresist layer applied over a thin film substrate layer over a base substrate is patterned, resulting in an exposed portion of the thin film substrate layer. The photoresist layer and the exposed portion of the thin film substrate layer are physical plasma etched, resulting in the thin film substrate... Agent: Hewlett Packard Company

20070037387 - Method to form an interconnect: Embodiments of methods, apparatuses, devices, and/or systems for forming an interconnect are described.... Agent: Hewlett Packard Company

20070037388 - Method of forming an insulating capping layer for a copper metallization layer: A new technique is disclosed in which a barrier/capping layer for a copper-based metal line is formed by using a thermal-chemical treatment followed by an in situ plasma-based deposition of silicon nitride and/or silicon carbon nitride. The thermal-chemical treatment is performed on the basis of an ammonium/nitrogen mixture in the... Agent: Williams, Morgan & Amerson

20070037389 - Method for electroless plating metal cap barrier on copper: A process for electroless plating a metal cap barrier on a substrate is disclosed. Copper metallization is formed on the substrate such that the substrate has an exposed top surface of a copper line. The exposed top surface of the copper line is pre-cleaned. The pre-cleaned exposed top surface of... Agent: North America Intellectual Property Corporation

20070037391 - Atomic layer deposition of metal-containing films using surface-activating agents: Atomic layer deposition processes for the formation of metal-containing films on surfaces are provided.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070037390 - Plasma cvd apparatus for forming uniform film: A plasma CVD film formation apparatus includes: a reaction chamber; a shower plate installed inside the reaction chamber; and a susceptor for placing a wafer thereon installed substantially parallel to and facing the shower plate. The shower plate has a surface facing the susceptor, which is configured using a convex... Agent: Knobbe Martens Olson & Bear LLP

20070037392 - Atomic layer deposition of ruthenium-containing films using surface-activating agents and novel ruthenium complexes: This invention is directed to processes for the formation of ruthenium-containing films on surfaces in atomic layer deposition (ALD) processes using surface-activating agents, and to ruthenium complexes that can be used as ruthenium precursors in these processes.... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070037393 - Process of physical vapor depositing mirror layer with improved reflectivity: A process of physical vapor depositing mirror layer with improved reflectivity is disclosed. A wafer is loaded into a PVD tool comprising a degas chamber, a Ti/TiN sputter deposition chamber, a cooling chamber, and an aluminum sputter deposition chamber. A wafer degas process is first performed within the degas chamber.... Agent: North America Intellectual Property Corporation

20070037394 - A method for using a cu beol process to fabricate an integrated circuit (ic) originally having an al design: A semiconductor fabrication method or process is provided for fabricating an integrated circuit (IC) originally having an Al backend design using a Cu BEOL fabrication process. The method converts the Al backend design to a Cu backend design without redesigning the IC for Cu BEOL fabrication process, and uses the... Agent: Zeming M. Gao 3law Techlaw Services

20070037396 - Semiconductor processing using energized hydrogen gas and in combination with wet cleaning: A method of fabricating a semiconductor device. The method comprises subjecting a substrate having formed thereon photoresist layer to a plasma hydrogen, the substrate further having formed thereon a sacrificial layer; contacting the photoresist layer with a photoresist removal solution; subjecting the sacrificial layer to a plasma hydrogen; and contacting... Agent: Applied Materials/blakely

20070037395 - Stringer elimination in a bicmos process: A method of preventing formation of stringers adjacent a side of a CMOS gate stack during the deposition of mask and poly layers for the formation of a base and emitter of a bi-polar device on a CMOS integrated circuit wafer. The stringers are formed by incomplete removal of a... Agent: Hitt Gaines, PC Agere Systems Inc.

20070037397 - Two-piece dome with separate rf coils for inductively coupled plasma reactors: A substrate processing system has a housing that defines a process chamber, a gas-delivery system, a high-density plasma generating system, a substrate holder, and a controller. The housing includes a sidewall and a dome positioned above the sidewall. The dome has physically separated and noncontiguous pieces. The gas-delivery system introduces... Agent: Townsend And Townsend And Crew LLP / Amat

20070037398 - Two-piece dome with separate rf coils for inductively coupled plasma reactors: In manufacturing a semiconductor device, a metal film is formed on a semiconductor substrate, and a high-temperature amorphous carbon film pattern for defining a wiring forming area is formed on the metal film. The metal film is etched by using the high-temperature amorphous carbon film pattern as an etching barrier... Agent: Ladas & Parry LLP

20070037399 - High-pressure device for closing a container in a clean room: The invention relates to a very compact device and to a method for closing a container by means of a rotational symmetric lifting system, which contains a working piston and a guide cylinder and is operated essentially using the same fluid that is placed inside the container while serving a... Agent: Marshall & Melhorn

20070037400 - Composition and methods removing polysilicon: Embodiments of the invention provide a composition adapted to remove polysilicon. The composition comprises about 1.0 to 10 percent by weight of alkylammonium hydroxide, about 0.1 to 5.0 percent by weight of hydrogen peroxide, and water.... Agent: Volentine Francos, & Whitt PLLC

20070037401 - Method of forming trench isolation: A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least 10, under conditions and for... Agent: Wells St. John P.s.

20070037402 - Method for manufacturing semi-transparent semi-reflective electrode substrate, reflective element substrate, method for manufacturing same, etching composition used for the method for manufacturing the reflective electrode substrate: An etchant for selective etching is used to simplify the production process of a semi-transparent semi-reflective electrode substrate, and temporal loss is not produced by avoiding troublesome repeated works, thereby efficiently providing a semi-transparent semi-reflective electrode substrate. A method for manufacturing a semi-transparent semi-reflective electrode substrate where a metal oxide... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070037406 - Methods of fabricating a semiconductor device using a photosensitive polyimide layer and semiconductor devices fabricated thereby: A method of fabricating a semiconductor device includes forming a photo-sensitive polyimide layer on a semiconductor substrate, patterning the photo-sensitive polyimide layer using a mask having a layer for adjusting light transmittance, and forming an epoxy molding compound on the substrate having the photo-sensitive polyimide layer patterns.... Agent: Marger Johnson & Mccollom, P.C.

20070037405 - Methods of forming metal-insulator-metal (mim) capacitors with passivation layers on dielectric layers and devices so formed: Methods of forming a dielectric layer of a MIM capacitor can include forming a passivation layer on a dielectric layer of a MIM capacitor to separate the dielectric layer from direct contact with an overlying photo-resist pattern. Related capacitor structures are also disclosed.... Agent: Myers Bigel Sibley & Sajovec

20070037404 - Siox:si composite articles and methods of making same: Article are made from silicon oxide and electrically conductive doped silicon materials that are joined in a protective environment to yield a composite SiOx:Si material that exhibits the properties of SiOx and yet is electrically conductive due to the presence of the Si. Articles from such composite materials find many... Agent: Dickinson Wright PLLC

20070037403 - Via bottom contact and method of manufacturing same: A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via... Agent: Greenblum & Bernstein, P.L.C

20070037407 - Method of cleaning semiconductor device fabrication apparatus: A semiconductor device fabrication apparatus is cleaned after a conductive layer is formed on a metal oxide layer of a substrate. The substrate is disposed on a heater in a process chamber of the apparatus, and the conductive layer is formed by introducing source gases into the chamber. Then the... Agent: Volentine Francos, & Whitt PLLC

20070037409 - Composite dielectric forming methods and composite dielectrics: A composite dielectric forming method includes atomic layer depositing alternate layers of hafnium oxide and lanthanum oxide over a substrate. The hafnium oxide can be thermally stable, crystalline hafnium oxide and the lanthanum oxide can be thermally stable, crystalline lanthanum oxide. A transistor may comprise the composite dielectric as a... Agent: Wells St. John P.s.

20070037408 - Method and apparatus for plasma processing: A plasma processing method using an apparatus including an electrode unit configured by providing a dielectric layer on a surface of a metal substrate having a surface defining a plurality of through holes and by superimposing a plurality of the metal substrates so that the through holes coincide, the method... Agent: Lowe Hauptman Berner, LLP

20070037410 - Method for forming a lithography pattern: A method of lithography patterning includes forming a first material layer on a substrate, the first material layer being substantially free of silicon, and forming a patterned resist layer including at least one opening therein above the first material layer. A second material layer containing silicon is formed on the... Agent: Haynes And Boone, LLP

20070037411 - Method of manufacturing an electronic device: The electronic device with a layer of mesoporous silica can be obtained by applying a composition comprising alkoxysilane, a surfactant and a solvent onto a substrate, and by subsequently removing the surfactant and the solvent. The customary dehydroxylation treatment is not necessary if the composition contains a mixture of tetra-alkoxysilane,... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070037412 - In-situ atomic layer deposition: An in situ method for forming a HfO2 high-k dielectric layer in a batch wafer processing system. The method comprises first loading a plurality of wafers into a process chamber, and then pre-treating the plurality of wafers in the process chamber with a first oxidizer. After pre-treating the wafers, and... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070037413 - Surface treatment method, manufacturing method of semiconductor device, and manufacturing method of capacitive element: A method for processing an object containing moisture is provided to efficiently remove the moisture and to prevent re-adsorption of the moisture. In particular, the method has a step of removing the moisture contained in the object in an atmosphere containing excited hydrogen, deuterium, deuterated hydrogen, or tritium.... Agent: Fitzpatrick Cella Harper & Scinto

20070037415 - Lanthanum hafnium oxide dielectrics: Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070037414 - Switch element, memory element and magnetoresistive effect element: A switch element includes a substrate; a plurality of carbon nanotubes provided upright on the substrate; magnetic particles arranged at tip ends of the carbon nanotubes respectively; and a plurality of conductive layers formed between base ends of the carbon nanotubes and the substrate. A switching operation of the switching... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070031981 - Method for forming ferroelectric film and semiconductor device: In a method for forming a ferroelectric film of insulating metal oxide on a surface of an electrode with a concave or a convex or in convex shape which is formed above a substrate, multiple types of source gases constituting a material gas and each containing an organometallic compound are... Agent: Mcdermott Will & Emery LLP

20070031982 - Method of classifying defects and apparatus for performing the method: In a method of classifying defects, actual information with respect to actual defects by each of processes on an object on which the processes are sequentially carried out is obtained. The actual information is accumulated in sequence of the processes to obtain composite information by each of the processes with... Agent: Marger Johnson & Mccollom, P.C.

20070031983 - Thin plate manufacturing method and thin plate manufacturing apparatus: In order to obtain a thin plate manufacturing method capable of extremely increasing manufacturing efficiency by enlarging the production scale and remarkably reducing the manufacturing cost per unit area and an apparatus for manufacturing this thin plate, a method and an apparatus performing introduction of a substrate into a main... Agent: Nixon & Vanderhye, PC

20070031984 - Method of fabricating submicron suspended objects and application to the mechanical characterization of said objects: A method of fabricating submicron objects that includes the following steps: depositing a void layer on a support, depositing a transfer layer on the void layer, producing the objects in the transfer layer, producing a hard mask on a portion of the transfer layer to delimit a region comprising a... Agent: Sofer & Haroun LLP.

20070031985 - Semiconductor laser device and method for fabricating the same: A method for fabricating a buried semiconductor laser device including the steps of: forming a mesa structure including a bottom cladding layer, an active layer and a top cladding layer overlying an n-type semiconductor substrate; and forming a current confinement structure by growing a p-type current blocking layer and an... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070031987 - Method of operating image sensor: Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field... Agent: Dickstein Shapiro LLP

20070031986 - Solar cell manufacturing method: A method of manufacturing a solar cell includes forming a diffusion layer on a crystal-type silicon substrate. The diffusion layer has a conductivity opposite to that of the substrate. Furthermore, the method includes etching and removing a part of the diffusion layer by using sodium silicate, and forming a first... Agent: Buchanan, Ingersoll & Rooney PC

20070031988 - Backside silicon wafer design reducing image artifacts from infrared radiation: Imaging devices having reduced image artifacts are disclosed. The image artifacts in the imaging devices are reduced by redirecting, absorbing or scattering IR radiation that passes through the imaging device substrate away from dark pixels.... Agent: Dickstein Shapiro LLP

20070031989 - Separating semiconductor wafers having exposed micromechanical structures into individual chips: The inventive method enables chips (1) to be separated without damaging them, which have exposed sensitive micromechanical structures, from the group of wafers by means of standard parting-off grinding processes. During the parting-off grinding process, the micromechanical structures are covered with a thermofilm (4) thereby protecting them. The parting-off grinding,... Agent: Hunton & Williams LLP Intellectual Property Department

20070031990 - Manufacturing method of semiconductor device: In view of the problem that an organic semiconductor layer of an organic TFT is likely to deteriorate due to water, light, oxygen, or the like, it is an object of the present invention to simplify a manufacturing step and to provide a method for manufacturing a semiconductor device having... Agent: Nixon Peabody, LLP

20070031991 - Method for depositing compounds on a substrate by means of metalorganic chemical vapor deposition: The invention relates to a method for depositing compounds on a substrate by means of metalorganic chemical vapor deposition and a first mixture comprising at least one carrier gas and at least one organometallic compound as well as a second mixture comprising at least one carrier gas and at least... Agent: The Firm Of Karl F Ross

20070031992 - Apparatuses and methods facilitating functional block deposition: A guiding feature used to assist deposition of a functional block into a recessed region formed in a substrate. A template is used to create the guiding feature on a substrate. The template comprises a first feature configured to create a corresponding recessed region in a substrate and a second... Agent: Blakely Sokoloff Taylor & Zafman

20070031993 - Method and system for machine vision-based feature detection and mark verification in a workpiece or wafer marking system: A precision laser based method of marking semiconductor wafers, packages, substrates or similar workpieces is provided. The workpieces have articles which may include die, chip scale packages, circuit patterns and the like. The marking occurs in a workpiece marking system and within a designated region relative to an article position.... Agent: Brooks Kushman P.C.

20070031994 - Method for fabricating protective caps for protecting elements on a wafer surface: A method of fabricating protective caps for protecting devices on wafer surface includes: (a) providing a non-metal cap substrate and forming a metal layer on the non-metal cap substrate; (b) forming a plurality of cavities on a surface of the metal layer, wherein the location of each cavity corresponds to... Agent: North America Intellectual Property Corporation

20070031995 - Mounting structure, electro-optical device, and electronic apparatus: A mounting structure is provided. The mounting structure includes: a substrate; a line formed on the substrate; an electronic component in which a terminal having a protrusion protruded to the substrate and made of an elastic material and a conductive member disposed on the protruded surface of the protrusion and... Agent: Harness, Dickey & Pierce, P.L.C

20070031996 - Packaged integrated circuit having a heat spreader and method therefor: An integrated circuit is packaged, in one embodiment, by wire bonding to pads supported by tape. The tape also supports traces that run from the wire bonded location to a pad for solder balls. A heat spreader is thermally connected to the integrated circuit and is located not just in... Agent: Freescale Semiconductor, Inc. Law Department

20070031997 - Jig and vacuum equipment for surface adhesion and adhesion method using the vacuum operative adhesion: Provided is a jig which can be used in a process of adhering a adhering object to a to-be adhered object in a vacuum atmosphere, and vacuum equipment for use in the adhering process. The jig includes a first frame and a second frame which together define a chamber for... Agent: Macpherson Kwok Chen & Heid LLP

20070031998 - Method and apparatus for removing encapsulating material from a packaged microelectronic device: A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at least partially surrounds a microelectronic substrate by directing a source of laser radiation toward the encapsulating material. The method can further include exposing a surface of the microelectronic... Agent: Perkins Coie LLP Patent-sea

20070031999 - Non-volatile memory cells and methods of manufacturing the same: Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070032000 - Vertical pixel structures for emi-flective display and methods for making the same: A vertical pixel structure for emi-flective display and a method thereof are provided. The vertical pixel structure has a substrate, a emitting pixel unit arranged on the substrate and a reflective pixel unit arranged on the emitting pixel unit. By using the vertical pixel structure the aperture of the display... Agent: Jianq Chyun Intellectual Property Office

20070032001 - Semiconductor device having a trench isolation and method of fabricating the same: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070032002 - Ion implantation mask and method for manufacturing same, silicon carbide semiconductor device using ion implantation mask, and method for manufacturing same: A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal... Agent: Birch Stewart Kolasch & Birch

20070032004 - Copper barrier reflow process employing high speed optical annealing: A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect... Agent: Patent Counsel, M/s 2061 Applied Materials, Inc.

20070032006 - Fabrication method of flash memory: A fabrication method of a flash memory is provided. The substrate having a cell region and a peripheral circuitry region is provided. A patterned dielectric layer and a patterned conductive layer are formed on the substrate, and isolation structures are formed in the substrate. An inter gate dielectric layer and... Agent: Jianq Chyun Intellectual Property Office

20070032003 - Method for forming uniaxially strained devices: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate (201) with a gate structure (209) disposed thereon, wherein the gate structure comprises a gate electrode (227) and at least one spacer structure (215, 217), and... Agent: Fortkort Grether & Kelton LLP

20070032007 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating... Agent: Mcdermott Will & Emery LLP

20070032005 - Semiconductor device and method of fabricating the same: The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region through a first resist opening portion of a first resist pattern;... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070032008 - Mos semiconductor devices having polysilicon gate electrodes and high dielectric constant gate dielectric layers and methods of manufacturing such devices: A semiconductor device includes a substrate divided into an NMOS region and a PMOS region, a first gate pattern formed on the PMOS region, and a second gate pattern formed on the NMOS region. The first gate pattern includes a first gate oxide layer pattern, a metal oxide layer pattern,... Agent: D. Randal Ayers Myers Bigel Sibley & Sajovec, P.A.

20070032009 - Semiconductor devices having strained dual channel layers: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium... Agent: Goodwin Procter LLP Patent Administrator

20070032010 - Formation of fully silicided (fusi) gate using a dual silicide process: A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of... Agent: Scully Scott Murphy & Presser, PC

20070032012 - I-shaped and l-shaped contact structures and their fabrication methods: Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the... Agent: Stout, Uxa, Buyan & Mullins LLP

20070032011 - Methods of forming memory circuitry: The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines... Agent: Wells St. John P.s.

20070032013 - Methods of forming a metal oxide layer including zirconium oxide and methods of forming a capacitor for semiconductor devices including the same: The present invention provides methods of forming a metal oxide layer and methods of forming a capacitor including the same. The methods of forming the metal oxide include forming a thin layer including a metal oxide, such as zirconium oxide, on a substrate and performing a post-treatment on the thin... Agent: Myers Bigel Sibley & Sajovec

20070032014 - Methods of forming pluralities of capacitors: The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on a substrate. A patterned masking layer is formed over the metal. The patterned masking layer comprises openings therethrough to an outer surface of the metal. Individual of the... Agent: Wells St. John P.s.

20070032015 - Semiconductor device and manufacturing method of the same: To provide a semiconductor device capable of improving accuracy in finishing a hole in which a conductive plug right under a capacitor, and a manufacturing method of such a semiconductor device comprising the following steps: a step of forming first and second conductive plugs 32a, 32b in first and second... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070032016 - Protective layer in memory device and method therefor: A method protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, die protective layer being adapted to absorb electromagnetic wave energy... Agent: Tiajoloff & Kelly

20070032017 - Nonvolatile memory devices and methods of fabricating the same: Methods of fabricating a nonvolatile memory device include forming a trench mask pattern on a semiconductor substrate including a first region and a second region. Substrate trenches defining active regions are formed in the semiconductor substrate in the first region and the second region using the trench mask pattern as... Agent: Myers Bigel Sibley & Sajovec

20070032018 - Nand flash memory with densely packed memory gates and fabrication process: NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source... Agent: Edward S. Wright

20070032019 - Flash memory device and method for fabricating the same: A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070032020 - Structures and methods for forming shielded gate field effect transistors: A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in... Agent: Townsend And Townsend And Crew, LLP

20070032022 - Mask read only memory (rom) and method of fabricating the same: The Mask ROM includes a plurality of doped lines arranged on a substrate of a first conductivity. The doped lines have a second conductivity. In addition, the Mask ROM further includes an insulation film covering the substrate, a plurality of interconnections intersecting the doped lines in parallel and arranged on... Agent: F. Chau & Associates, LLC

20070032021 - Method for forming a gate dielectric of a semiconductor device: Disclosed is a method for forming a gate dielectric in a semiconductor device. The present method includes forming a first dielectric layer on a semiconductor substrate; removing a portion of the first dielectric layer to expose a portion of the substrate; forming a nitride layer on the exposed portion of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070032023 - Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest... Agent: Wolf Greenfield & Sacks, PC

20070032024 - Methods for fabricating a stressed mos device: A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench... Agent: Ingrassia Fisher & Lorenz, P.C.

20070032025 - Method for forming germanides and devices obtained thereof: The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070032026 - Formation of strained si channel and si1-xgex source/drain structures using laser annealing: A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal... Agent: The Law Offices Of Mikio Ishimaru

20070032027 - Method for manufacturing mos transistor of semiconductor device: Disclosed is a method for manufacturing a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor. The present method includes a low-voltage well implantation process on a semiconductor substrate to form a first well in a first region of the substrate and a second well in a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070032028 - Structure and method for reducing overlap capacitance in field effect transistors: A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations... Agent: Cantor Colburn LLP - IBM Fishkill

20070032029 - Lateral trench power mosfet with reduced gate-to-drain capacitance: In one aspect, a lateral MOS device is provided. The lateral MOS device includes a gate electrode disposed at least partially in a gate trench to apply a voltage to a channel region, and a drain electrode spaced from the gate electrode, and in electrical communication with a drift region... Agent: Wolf Greenfield & Sacks, PC

20070032031 - Method for conducting electric activation of electric double layer capacitors: An object of the present invention is to provide a method for conducting electric activation of an electric double layer capacitor, the method making it possible to increase the electrostatic capacitance and to decrease the internal resistance. The method is for conducting electric activation of an electric double layer capacitor... Agent: Harness, Dickey & Pierce, P.L.C

20070032030 - Method for high performance inductor fabrication using a triple damascene process with copper beol: A method of forming a high performance inductor comprises providing a substrate; forming a plurality of wiring levels over the substrate, wherein each of the wiring levels comprise a dielectric layer; forming a first trench having a first depth in a first dielectric layer on a first wiring level; forming... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070032032 - Connecting structure and method for manufacturing the same: A method for manufacturing a surface strap connection between a trench capacitor and a selection transistor includes providing a masking material on a surface of a semiconductor substrate in areas where no trench capacitors have been formed. An undoped semiconductor layer having vertical and horizontal areas is applied. An oblique... Agent: Edell, Shapiro & Finnan, LLC

20070032033 - Connecting structure and method for manufacturing the same: A connecting structure connects a storage electrode of a trench capacitor and a selection transistor that are at least partially formed in a semiconductor substrate. The connecting structure includes a portion of an intermediate layer disposed adjacent to a surface of the storage electrode, and an electrically conducting material disposed... Agent: Edell, Shapiro & Finnan, LLC

20070032034 - Method for manufacturing semiconductor storage device: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride... Agent: Mcdermott Will & Emery LLP

20070032035 - Container capacitor structure and method of formation thereof: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available... Agent: Leffert Jay & Polglaze, P.A.

20070032036 - Array substrate for lcd and method of fabrication thereof: A liquid crystal display array substrate. A trench is in a substrate. A gate, a gate dielectric layer, a semiconductor layer and a doped semiconductor layer are disposed in the trench, wherein the semiconductor layer comprises a channel. A source electrode and a drain electrode are respectively electrically connected to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070032037 - Method of forming soi-like structure in a bulk semiconductor substrate using self-organized atomic migration: Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the... Agent: Slater & Matsil, L.L.P.

20070032038 - Method for forming recesses: A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask... Agent: Quintero Law Office

20070032039 - Sti process for eliminating silicon nitride liner induced defects: The present invention discloses an improved shallow trench isolation process. A semiconductor substrate having a pad oxide disposed thereon and a pad nitride disposed directly on the pad oxide is provided. A trench is etched, through the pad oxide and the pad oxide, into the semiconductor substrate. A thermal oxide... Agent: North America Intellectual Property Corporation

20070032041 - Gallium nitride device substrate containing a lattice parameter altering element: A gallium nitride device substrate comprises a layer of gallium nitride containing an additional lattice parameter altering element located over a substitute substrate.... Agent: Avago Technologies, Ltd.

20070032040 - Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses: The present invention provides a method of manufacturing a multilayer semiconductor structure featuring reduced ohmic losses with respect to standard multilayer semiconductor structures. The semiconductor structure comprises a high resistivity silicon substrate with resistivity higher than 3 KΩ.cm, an active semiconductor layer and an insulating layer in between the silicon... Agent: Bacon & Thomas, PLLC

20070032042 - Peeling method: A peeling method is provided which does not cause damage to a layer to be peeled, and the method enables not only peeling of the layer to be peeled having a small area but also peeling of the entire layer to be peeled having a large area at a high... Agent: Eric Robinson

20070032044 - Method and structure for fabricating devices using one or more films provided by a layer transfer process and etch back: A method for fabricating one or more devices using semiconductor substrate with a cleave region. The method includes providing a substrate. In a preferred embodiment, the substrate has a thickness of semiconductor material and a surface region. In a specific embodiment, the substrate also has a cleave plane (including a... Agent: Townsend And Townsend And Crew, LLP

20070032043 - Soi wafer and its manufacturing method: Since a supporting wafer contains boron of 9×1018 atoms/cm3 or more, therefore a part of the metal impurities in an active layer wafer and the metal impurities in the wafer can be captured by the boron during the heat treatment for bonding. As a result, metal contamination in the active... Agent: Greenblum & Bernstein, P.L.C

20070032047 - Method and apparatus for forming silicon-containing insulating film: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a purge gas, a first process gas containing a silane family gas, and a second process gas containing a gas selected from the group consisting of nitriding, oxynitriding, and... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070032048 - Method for depositing thin film by controlling effective distance between showerhead and susceptor: A method for depositing a thin film on a substrate by plasma CVD includes: providing a vacuum chamber including a showerhead and a susceptor entirely facing the showerhead in parallel, placing a substrate on the susceptor entirely within the inner portion; and applying an RF power between the showerhead and... Agent: Knobbe Martens Olson & Bear LLP

20070032045 - Method for manufacturing semiconductor device and substrate processing apparatus: Provided are a step of loading at least one wafer 200 into a reaction chamber 201, a step of introducing reaction gas into the reaction chamber 201, and exhausting an inside of the reaction chamber 201, thereby processing the wafer 200, and a step of unloading the processed wafer 200... Agent: Oliff & Berridge, PLC

20070032046 - Method for simultaneously producing multiple wafers during a single epitaxial growth run and semiconductor structure grown thereby: HVPE method for simultaneously fabricating multiple Group III nitride semiconductor structures during a single reactor run. A HVPE reactor includes a reactor tube, a growth zone, a heating element and a plurality of gas blocks. A substrate holder is capable of holding multiple substrates and can be a single or... Agent: Bingham Mccutchen LLP

20070032049 - Process for manufacturing a semiconductor device: A first amorphous semiconductor film is formed on an insulating surface. A catalyst element for promoting crystallization is added thereto. Thereafter, by a first heat treatment in an inert gas, a first crystalline semiconductor film is formed. A barrier layer and a second semiconductor layer are formed on the first... Agent: Eric Robinson

20070032050 - Mask for sequential lateral solidification and method of manufacturing the same: A mask for sequential lateral solidification capable of preventing pattern deformation that may be caused by laser beam, and a method of manufacturing the same are provided. The mask includes a transparent substrate, and a heat-resistant oxide film pattern, disposed on the transparent substrate, blocking a laser beam.... Agent: Macpherson Kwok Chen & Heid LLP

20070032051 - Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest... Agent: Wolf Greenfield & Sacks, PC

20070032052 - Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest... Agent: Wolf Greenfield & Sacks, PC

20070032053 - Method of producing silicon carbide semiconductor substrate, silicon carbide semiconductor substrate obtained thereby and silicon carbide semiconductor using the same: The present invention provides a method of producing a silicon carbide semiconductor substrate in which a silicon carbide buffer layer doped with germanium and a semiconductor device layer are sequentially laminated on the buffer layer, a silicon carbide semiconductor substrate obtained by the method and a silicon carbide semiconductor in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070032054 - Semiconductor substrate process using a low temperature deposited carbon-containing hard mask: A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern, and depositing a carbon-containing hard mask layer... Agent: Patent Counsel, M/s 2061 Applied Materials, Inc.

20070032055 - Dry etchback of interconnect contacts: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The... Agent: International Business Machines Corporation Dept. 18g

20070032056 - Manufacturing method of semiconductor device: This invention relates to a technology to form a polysilicon resistor having a high resistance in a semiconductor device using a silicide process. A manufacturing method of the semiconductor device of this invention includes forming an insulation film on a semiconductor substrate, forming a polysilicon film on the insulation film,... Agent: Morrison & Foerster LLP

20070032057 - Semiconductor device and method of fabricating the same: A method for fabricating a semiconductor device, including forming a gate insulating layer and a gate electrode on a substrate; forming insulating layer sidewalls at sides of the gate electrode; forming source/drain regions in surface portions of the substrate that are located, respectively, at sides of the gate electrode; forming... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070032060 - Method for forming conductive wiring and interconnects: A method for forming conductive wiring is provided. First, a material layer having at least a trench is provided. A conductive material layer is formed on the material layer to fill the trench and cover the top surface of the material layer. A patterned mask layer is formed on the... Agent: J C Patents, Inc.

20070032058 - Method of fabricating interconnect: A method of fabricating interconnect is described. A first dielectric layer having an opening is formed over a substrate. A metal layer is filled into the opening. A material layer is formed over the first dielectric layer and the metal layer. A surface treatment process is performed to the material... Agent: Jianq Chyun Intellectual Property Office

20070032059 - Method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure: This invention provides a method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure. The method comprises the steps of: providing a semiconductor wafer (1) having a bulk region (1a) and an active region (1b); forming a plurality of contact trenches (5a-5f) in said semiconductor... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070032062 - Methods of forming dual-damascene metal wiring patterns for integrated circuit devices and wiring patterns formed thereby: Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop... Agent: Myers Bigel Sibley & Sajovec

20070032061 - Methods of forming through-wafer interconnects and structures resulting therefrom: Methods for forming conductive vias or through-wafer interconnects in semiconductor substrates and resulting through wafer interconnect structures are disclosed. In one embodiment of the present invention, a method of forming a through wafer interconnect structure includes the acts of forming an aperture in a first surface of a substrate, depositing... Agent: Trask Britt, P.C./ Micron Technology

20070032063 - Efficient transistor structure: An integrated circuit comprises a first source, a first drain, a second source, a first gate arranged between the first source and the first drain, and a second gate arranged between the first drain and the second source. The first and second gates define alternating first and second regions in... Agent: Harness, Dickey & Pierce P.L.C

20070032064 - Use of an internal on-chip inductor for electrostatic discharge protection of circuits which use bond wire inductance as their load: A method for forming and packaging an integrated circuit having a plurality of circuit components on a semi conductive substrate die. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an... Agent: Garlick Harrison & Markison

20070032065 - Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size: Systems and methods are disclosed herein for determining the placement of storage and non-storage cells or components, representing a semiconductor component in a design stage, on an integrated circuit die. In one embodiment, regions of a semiconductor die are analyzed with respect to the susceptibility of a region to be... Agent: Avago Technologies, Ltd.

20070032066 - Semiconductor device and method of fabricating the same: A semiconductor wafer is thinned to a predetermined thickness by grinding the backside thereof (which is opposite to the side where a plurality of devices are formed and metal posts are further formed), and then a metal layer made of metal having a linear thermal expansion coefficient close to that... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070032068 - Semiconductor device and method for fabricating the same: A semiconductor device has a porous low-dielectric-constant film formed on a substrate and having an opening and a fine particle film composed of a plurality of aggregately deposited fine particles each having a diameter of not less than 1 nm and not more than 2 nm and formed on a... Agent: Mcdermott Will & Emery LLP

20070032067 - Semiconductor device and method of manufacturing the same: There is disclosed a semiconductor device comprising at least one first insulating film provided above a substrate, being formed with at least one first recess having a first width, and being formed with at least one second recess having a second width which is 1/x (x: positive numbers larger than... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070032069 - Selective metal deposition over dielectric layers: Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is... Agent: Dinsmore & Shohl LLP One Dayton Centre

20070032070 - Semiconductor device and method for manufacturing same: A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device includes a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 140 provided on the interlayer insulating film 102. The semiconductor device also... Agent: Young & Thompson

20070032071 - Methods of forming cosi2, methods of forming field effect transistors, and methods of forming conductive contacts: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt.... Agent: Wells St. John P.s.

20070032072 - Nucleation layer deposition on semiconductor process equipment parts: A plasma chamber is provided having an upper insulating member as a lid of the plasma chamber. The lid of the plasma chamber, usually in the form of a bell jar, has an inside surface which will be exposed to the interior of the plasma chamber. A nucleation layer is... Agent: Stmicroelectronics, Inc.

20070032074 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device comprises sequentially forming a first conductive layer, a first insulating interlayer, a second conductive layer, and a second insulating interlayer on a semiconductor substrate. A mask layer is formed on the second insulating interlayer, and then the second insulating interlayer, the second conductive... Agent: Volentine Francos, & Whitt PLLC

20070032073 - Method of substrate processing and apparatus for substrate processing: In a substrate-processing method and a substrate-processing apparatus according to the invention, a natural oxide film that has been formed on each surface layer of a gate 21, a source 15 and a drain 17 of a MOSFET 11 is removed by an NF3 gas that has been activated. Then,... Agent: Smith, Gambrell & Russell

20070032075 - Deposition method for wiring thin film: An Al3Ti film having a large amount of dissolved Si is deposited on a semiconductor substrate to form a laminate with an Al wiring film, and heat treatment is performed at a temperature of at least 400° C., to thereby absorb excessive Si into the Al3Ti film and to so... Agent: Volentine Francos, & Whitt PLLC

20070032076 - Nanowire device and method of fabricating the same: A nanowire device having a structure allowing for formation of p-type and n-type doped portions in a nanowire, and a method of fabricating the same. The nanowire device includes a substrate, a first electrode layer formed on the substrate, a second electrode layer facing the first electrode layer, a plurality... Agent: Sughrue Mion, PLLC

20070032077 - Method of manufacturing metal plug and contact: A method for manufacturing a metal plug is described. A substrate with an opening is provided. Then, a barrier layer is formed on a surface of the opening. Thereafter, a metallic layer is formed over the substrate so that the opening is also filled. Next, a planarization process is performed... Agent: Jianq Chyun Intellectual Property Office

20070032078 - Suspension for filling via holes in silicon and method for making the same: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The... Agent: Delio & Peterson, LLC

20070032079 - Method for thin film deposition using multi-tray film precursor evaporation system: A method for depositing a Ru metal layer on a patterned substrate from a film precursor vapor delivered from a multi-tray film precursor evaporation system. The method comprises providing a patterned substrate in a process chamber of a deposition system, and forming a process gas containing Ru3(CO)12 precursor vapor and... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070032080 - System and method for manufacturing flexible copper clad laminate film: Disclosed is a system and a method for manufacturing flexible copper clad laminate film capable of efficiently electroplating both surfaces of a polyimide-based film to form copper plating layers thereon while making it easy to repair and maintain the apparatus or clean its plating or cleaning bath. The system includes... Agent: Conley Rose, P.C.

20070032081 - Edge ring assembly with dielectric spacer ring: An edge ring assembly surrounds a substrate support surface in a plasma etching chamber. The edge ring assembly comprises an edge ring and a dielectric spacer ring. The dielectric spacer ring, which surrounds the substrate support surface and which is surrounded by the edge ring in the radial direction, is... Agent: Buchanan, Ingersoll & Rooney PC

20070032082 - Semiconductor substrate process using an optically writable carbon-containing mask: A method of processing a thin film structure on a semiconductor substrate using an optically writable mask, the method includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be exposed to a light source in accordance with a predetermined pattern, depositing... Agent: Patent Counsel Applied Materials, Inc.

20070032083 - Planarization method for manufacturing semiconductor device: A method for planarizing a layer of a semiconductor device includes heating the layer to exhibit flowability, and applying pressure through an optically flat surface layer onto the layer to planarize the layer. And the planarizing method further comprises etch-back or chemical-mechanical polishing on the planarized layer.... Agent: Townsend And Townsend And Crew, LLP

20070032084 - Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process: A method for fabricating one or more devices, e.g., integrated circuits. The method includes providing a substrate (e.g., silicon), which has a thickness of semiconductor material and a surface region. The substrate also has a cleave plane provided within the substrate to define the thickness of semiconductor material. The method... Agent: Townsend And Townsend And Crew, LLP

20070032085 - Method for forming recesses: A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask... Agent: Quintero Law Office

20070032087 - Damage-free ashing process and system for post low-k etch: A process is provided for substrate ashing following the etching of features in a low dielectric constant (low-k) layer. The low-k layer can include ultra-low-k material, or a porous low-k material. The process may be configured to remove etch byproducts while preserving feature critical dimension. The ashing process comprises the... Agent: Dla Piper Rudnick Gray Cary US LLP

20070032086 - Mehtod of manufacturing an electronic device: A method of manufacturing an electronic device is provided wherein an interconnect is made using 193 nm lithography. No deformation of the desired linewidth takes place in that during a plasma gas is used which dissociates in low-weight ions. The electronic device is particularly an integrated circuit.... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070032088 - Device and method for detecting foreign material on the surface of plasma processing apparatus: A detection technique for detecting foreign material on the surface of a plasma processing apparatus, capable of accurately sucking/extracting and measuring foreign material contained in the measurement object surface is provided. The detection device comprises a gauge head or probe having a gas blow out opening for intermittently blowing a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070032089 - Printable semiconductor structures and related methods of making and assembling: The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized... Agent: Greenlee Winner And Sullivan P C

20070032092 - Method for manufacturing semiconductor device having trench: A method for manufacturing a semiconductor device includes steps of: forming a trench on a semiconductor substrate, which is made of silicon; and filling the trench with an epitaxial layer. The epitaxial layer is made of silicon, and the step of filling the trench includes a step of performing a... Agent: Posz Law Group, PLC

20070032091 - Methods and devices for forming nanostructure monolayers and devices including such monolayers: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also... Agent: Quine Intellectual Property Law Group, P.C.

20070032090 - Plasma rapid thermal process apparatus in which supply part of radical source is improved: Disclosed is a plasma rapid thermal process apparatus having an improved plasma supply port for supplying atomic radicals to a rapid thermal process chamber. The supply port includes an inner tube and an outer tube. The inner tube has one end which is opened and connected to the discharge tube... Agent: Ipla P.A.

20070032094 - Energy beam treatment to improve packaging reliability: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a... Agent: Texas Instruments Incorporated

20070032093 - Structure and method of forming a semiconductor material wafer: A structure and method of forming a semiconductor material wafer comprising forming an ingot of semiconductor material. A first dielectric layer is formed on the surface of the ingot, and the surface of the first dielectric layer is larger than the surface of the ingot. A 5 second dielectric layer... Agent: Rosenberg, Klein & Lee

20070032095 - Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer: A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio... Agent: Patent Counsel, M/s 2061 Applied Materials, Inc.

20070032097 - Method and apparatus for processing semiconductor work pieces: A processing apparatus for semiconductor work pieces and related methodology is disclosed and which includes a processing chamber having an internal cavity, and which has a plurality of rotatable processing stations positioned therein and wherein the rotatable processing stations each process a semiconductor work piece.... Agent: Wells St. John P.s.

20070032096 - System and process for providing multiple beam sequential lateral solidification: A process and system for processing a thin film on a sample are provided. In particular, a plurality of separated beams each including beam pulses are generated. At least one first beam of the separated beams is forwarded through a mask to irradiate and heat the thin film sample prior... Agent: Baker & Botts L.L.P.

20070026536 - Organic thin film transistor for liquid crystal display and method of manufacturing the same: An organic thin film transistor for a liquid crystal display and a method of manufacturing an organic thin film transistor. The method of manufacturing an organic thin film transistor for a liquid crystal display comprises forming a gate conductive film pattern on a substrate; forming a gate insulating film on... Agent: Sughrue Mion, PLLC

20070026538 - Deposition defined trackwidth for very narrow trackwidth cpp device: In one embodiment, a method of forming a CPP sensor comprises providing a sensor having a hard mask disposed on a left side thereof and a right side with a portion of the sensor material removed therefrom, the hard mask having a vertical surface; forming a right dielectric layer including... Agent: Townsend And Townsend And Crew LLP

20070026537 - Method for fabricating a magnetic head for perpendicular recording using a cmp lift-off and resistant layer: A method using a CMP resistant hardmask in a process of fabricating a pole piece for a magnetic head is described. A set of layers used as the mask for milling the pole piece preferably includes a CMP resistant hardmask of silicon dioxide, a resist hardmask, an upper hardmask and... Agent: Marlin Knight

20070026539 - Method of selecting and analyzing scrap silicon: Non-destructive testing is performed on individual pieces of silicon using an energy dispersive x-ray fluorescent analyzer to determine from the obtained spectral data whether a prescribed impurity element is contained therein. The electrical resistivity of each piece of scrap silicon can be measured, and the concentration of the impurity element... Agent: Michael Tobias

20070026540 - Method of forming non-conformal layers: In one aspect, non-conformal layers are formed by variations of plasma enhanced atomic layer deposition, where one or more of pulse duration, separation, RF power on-time, reactant concentration, pressure and electrode spacing are varied from true self-saturating reactions to operate in a depletion-effect mode. Deposition thus takes place close to... Agent: Knobbe Martens Olson & Bear LLP

20070026541 - Method and system for manufacturing semiconductor device having less variation in electrical characteristics: A method of manufacturing a semiconductor device, which has a gate electrode and a pair of diffusion layers formed in a semiconductor substrate on sides of the gate electrode, includes forming an insulating film and a gate electrode on a semiconductor substrate, obtaining a thickness of an affected layer formed... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070026542 - Formation of conductive templates employing indium tin oxide: The present invention is directed to a method forming conductive templates that includes providing a substrate; forming a mesa on the substrate; and forming a plurality of recessions and projections on the mesa with a nadir of the recessions comprising electrically conductive material and the projections comprising electrically insulative material.... Agent: Molecular Imprints

20070026543 - Method for forming misalignment inspection mark and method for manufacturing semiconductor device: A method for forming a misalignment inspection mark is disclosed. The formation method includes forming a reference layer device pattern and a first mark in a reference layer and forming an overlying layer device pattern and a second mark in a layer over the reference layer, the overlying layer device... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070026547 - Cluster tool and method for process integration in manufacture of a gate structure of a field effect transistor: A method and apparatus for process integration in manufacture of a gate structure of a field effect transistor are disclosed. The method includes assembling an integrated substrate processing system having a metrology module and a vacuumed processing platform to perform controlled and adaptive plasma processes without exposing the substrate to... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070026544 - Impurity diffusion simulation method, impurity diffusion simulation apparatus, and impurity diffusion simulation program: The as-implanted concentration profile of impurity atoms in the semiconductor substrate is calculated, and a number of interstitial atoms to be generated in the semiconductor substrate by one impurity atom implanted with the ion implantation is set based on a peak concentration of the calculated as-implanted concentration profile of impurity... Agent: Mcdermott Will & Emery LLP

20070026546 - Method of detecting misalignment of ion implantation area: A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting first and second conduction type impurity ions into the first and second areas, respectively, and measuring a resistance of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070026545 - Methods and systems for controlling semiconductor device manufacturing processes: A first process time period for a manufacturing process is determined, and a thickness of a material on a sample semiconductor substrate using the first process time period is measured. If the thickness is not within a desired thickness range, a second process time period for the manufacturing process for... Agent: Myers Bigel Sibley & Sajovec

20070026548 - Integrated circuit and method for manufacturing: A semiconductor structure, fluid ejection device, and methods for manufacturing the same are provided, such that a contact to a substrate is formed from a conductive layer.... Agent: Hewlett-packard Company Intellectual Property Administration

20070026549 - Array substrate, method of manufacturing the same and method of crystallizing silicon: An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in... Agent: Cantor Colburn, LLP

20070026552 - Compound semiconductor device and its manufacture: A compound semiconductor device has: a substrate; a GaN channel layer; an n-type AlqGal-qN (0<q (1) electron supply layer; an n-type GaN cap layer; a gate electrode disposed on the cap layer and forming a Schottky contact; recesses formed on both sides of the gate electrode on source and drain... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070026550 - Method of manufacturing semiconductor light emitting apparatus and semiconductor light emitting apparatus: A method of manufacturing a semiconductor light emitting apparatus according to the invention includes: the mask layer forming step of forming two mask layers in descending order of etching rates from a side near a p-type semiconductor layer; the mask layer etching step; the semiconductor layer etching step; the side... Agent: Hogan & Hartson L.L.P.

20070026551 - Production method of gallium nitride-based compound semiconductor multilayer structure: An object of the present invention is to provide a method for producing a gallium nitride-based compound semiconductor multilayer structure useful for the production of a gallium nitride-based compound semiconductor light-emitting device which can ensure that the operating voltage is reduced, the light emission output is good and the light... Agent: Sughrue Mion, PLLC

20070026553 - Method of forming a semiconductor device: A method of forming a semiconductor device from a semiconductor substrate (1) comprising circuitry (2) and terminal means (3) for establishing electrical connection to the circuitry; and a sheet (4) for forming a further layer of the device, the sheet comprising at least one groove (5). Adhesive is applied to... Agent: Howson And Howson

20070026554 - Semiconductor device and process for producing same: A semiconductor device and process for producing same are provided. The process for producing a semiconductor device includes a first embossing step of pressing a stamp having a relief pattern onto a surface of a substrate to form a depression pattern on the surface of the substrate; a second step... Agent: Bell, Boyd & Lloyd, LLC

20070026556 - Liquid crystal display device and method of fabricating the same: A liquid crystal display device includes a first substrate including a thin film transistor, a data line, a pixel electrode, and a common electrode, a second substrate, and liquid crystal sandwiched between the first and second substrates, wherein an image signal is applied to the thin film transistor through the... Agent: Sughrue Mion, PLLC

20070026555 - Method of fabricating array substrate for liquid crystal display device: A method of fabricating an array substrate for a liquid crystal display device is provided. The method includes steps of forming an amorphous silicon pattern on a substrate; forming a catalyst metal pattern on the amorphous silicon pattern; annealing the amorphous silicon pattern to be converted into a polycrystalline silicon... Agent: Morgan Lewis & Bockius LLP

20070026557 - Method and structure for aluminum chemical mechanical polishing: A method for chemical mechanical polishing of mirror structures. Such mirror structures may be used for displays (e.g., LCOS, DLP), optical devices, and the like. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method forms a first dielectric layer overlying the semiconductor substrate and forms an aluminum... Agent: Townsend And Townsend And Crew, LLP

20070026558 - Magnetic tunnel junction sensor method: Methods and apparatus are provided for sensing physical parameters. The apparatus comprises a magnetic tunnel junction (MTJ) and a magnetic field source whose magnetic field overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. The MTJ comprises first and second magnetic... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070026561 - Method of manufacturing piezoelectric element and method of manufacturing liquid-jet head: While a piezoelectric element is being formed by sequentially laminating a lower electrode whose uppermost layer is made of iridium, a titanium layer, a piezoelectric layer and an upper electrode to each other on a substrate, the piezoelectric layer is formed, by an MOD method, on the titanium layer with... Agent: Sughrue, Mion, PLLC

20070026560 - Method of producing semiconductor pressure sensor: A method of producing a semiconductor pressure sensor, the sensor having a diaphragm to be deformed by pressure, including: a step of preparing a semiconductor substrate having front and rear surfaces, both of the surfaces being mirror surfaces; a thermally oxidizing step of forming a thermally-oxidized film on the rear... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070026559 - System and method for direct-bonding of substrates: A method of forming a MEMS (Micro-Electro-Mechanical System), includes forming an ambient port through a MEMS cap which defines a cavity containing a plurality of MEMS actuators therein; and bonding a lid arrangement to the MEMS cap to hermetically seal the ambient port.... Agent: Hewlett Packard Company

20070026562 - Method of forming a seal between a housing and a diaphragm of a capacitance sensor: The axial distance between opposing conductors of a capacitance pressure transducer can depend, in part, upon the thickness of a seal that is disposed between a housing and a diaphragm of the capacitance pressure transducer. The present invention utilizes spacer elements and sealing beads to form a seal that is... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070026563 - Method of manufacturing semiconductor photodetector: A method of manufacturing a semiconductor photodetector having spectral sensitivity close to relative luminous characteristics at low cost includes steps of sealing a light receiving surface side of a semiconductor light receiving element having high spectral sensitivity in wavelengths from the visible light region to infrared region with a sealing... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070026564 - Method for forming microlenses of different curvatures and fabricating process of solid-state image sensor: A method for forming microlenses of different curvatures is described, wherein a transparent photosensitive layer is formed on a substrate having a planar upper surface. A photomask is used to pattern the photosensitive layer, wherein the photomask has at least two patterns of different transparencies thereon such that at least... Agent: Jianq Chyun Intellectual Property Office

20070026565 - Selective area growth carbon nanotubes by metal imprint method: Manufacturing methods of using a metal imprint technique for growing carbon nanotubes on selective areas and the structures formed thereof are provided. One of the manufacturing methods includes steps of forming a first substrate with tapered structures applied with a metal catalyst, imprinting a second substrate on the first substrate... Agent: Silicon Valley Patent Group LLP

20070026566 - Phase change memory with damascene memory element: A phase change material may be formed within a trench in a first layer to form a damascene memory element and in an overlying layer to form a threshold device. Below the first layer may be a wall heater. The wall heater that heats the overlying phase change material may... Agent: Trop Pruner & Hu, PC

20070026567 - Semiconductor module comprising components for microwave engineering in plastic casing and method for the production thereof: A semiconductor module (1) has components (6) for microwave engineering in a plastic casing (7). The semiconductor module (1) has a principal surface (8) with an upper side (9) of a plastic package molding compound (10) and at least one active upper side (11) of a semiconductor chip (12). Disposed... Agent: Baker Botts, L.L.P.

20070026568 - Methods for bonding and devices according to such methods: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder... Agent: Knobbe Martens Olson & Bear LLP

20070026570 - Roll-to-roll fabricated electronically active device: An electronically active sheet, comprising a first substrate having an electrically conductive surface; a second substrate having an electrically conductive pattern disposed thereon; at least one semiconductor element having a first conductor and a second conductor. The electronically active sheet includes an adhesive having at least one semiconductor element fixed... Agent: Michaud-duffy Group LLP

20070026571 - Roll-to-roll fabricated encapsulated semiconductor circuit devices: An encapsulated semiconductor device, comprising a first substrate having an electrically conductive surface; a second substrate having an electrically conductive pattern disposed thereon; and a pattern of semiconductor elements, each of the semiconductor elements having a first conductor and a second conductor. The encapsulated semiconductor device includes an adhesive having... Agent: Michaud-duffy Group LLP

20070026569 - Semiconducting device with folded interposer: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070026572 - Dicing/die bonding sheet: The present invention provides a dicing/die bonding sheet which can be used as a dicing tape during dicing, enables ready separation of the semiconductor element and the adhesive layer from the pressure-sensitive adhesive layer during pickup, and in which the adhesive layer has satisfactory adhesiveness as a die bonding material.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070026573 - Method of making a stacked die package: A method of making a stacked die package (50) includes attaching and electrically connecting a first integrated circuit (IC) die (52) to a base carrier (56). A plurality of successive layers (54A, 54B and 54C) of an adhesive material (54) is formed on the first die (52). A second die... Agent: Freescale Semiconductor, Inc. Law Department

20070026574 - Interconnect apparatus and methods: Disclosed are interconnect structures and methods which utilize a bonding surface comprising copper nitride. The interconnect structures include a bonding surface comprising copper nitride which is effective at preventing oxidation and/or other unwanted corrosion of the underlying conductive material while providing the basis for a high conductivity bond. The copper... Agent: Kulicke And Soffa Industries, Inc.

20070026575 - No flow underfill device and method: A more reliable and easier to manufacture underfill assembly is shown. Underfill layers are shown that are manufacturable separately from an assembly operation. In one example, underfill layers have the ability for pick and place operations during assembly. Another advantage of underfill layers provided includes self aligning holes that aid... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070026576 - Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure: A method for sealing electronic devices formed on a semiconductor substrate includes forming a plurality of first electronic devices adjacent a first portion of the semiconductor substrate, with each first electronic device including a first region comprising at least one first conductive layer projecting from the semiconductor substrate. A first... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070026577 - High voltage non punch through igbt for switch mode power supplies: A process for forming an NPT IGBT in a thin N type silicon wafer in which the bottom surface of a thin silicon wafer (100 microns thick or less) has a shallow reduced lifetime region in its bottom formed by a light species atom implant to a depth of less... Agent: Ostrolenk Faber Gerb & Soffen

20070026578 - Method for forming a silicided gate: A gate is silicided through its sides while limiting silicidation through the top of the gate. A blocking layer may be formed over the gate layer, and the sidewalls of the gate layer are exposed. A layer of metal is formed on the sidewalls of the gate and thermally treated... Agent: Marger Johnson & Mccollom, P.C.

20070026579 - Doped single crystal silicon silicided efuse: An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070026583 - Electrooptical device and a method of manufacturing the same: To provide a semiconductor device of high reliability by arranging TFTs that have appropriate structures in accordance with circuit functions. In a semiconductor device having a driver circuit portion and a pixel portion on the same insulator, gate insulating films of a driver TFT are designed to be thinner than... Agent: Nixon Peabody, LLP

20070026582 - Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device: A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a predetermined region of a semiconductor base, forming a second semiconductor layer whose etching selective ratio is smaller than that of the first semiconductor layer on the first semiconductor layer, forming a support member to support... Agent: Edwards & Angell, LLP

20070026580 - Method for manufacturing semiconductor device: A semiconductor device is manufactured by forming a gate electrode layer over a substrate having a light transmitting property; forming a gate insulating layer over the gate electrode layer; forming a photocatalyst material over the gate insulating layer; immersing the photocatalyst material in a solution containing a plating catalyst material... Agent: Nixon Peabody, LLP

20070026581 - Method of manufacturing thin-film electronic device: A method of manufacturing a thin-film electronic device comprising providing a dielectric layer on a base, providing a first electrically conductive layer having a first opening and covering at least part of the dielectric layer; and forming a first through-hole extending through the base and communicating with the first opening.... Agent: Oliff & Berridge, PLC

20070026584 - Dielectric isolated body biasing of silicon on insulator: The present invention provides, in one aspect, a microelectronics device 100 that includes a silicon on insulator (SOI) region 110 located over a microelectronics substrate 115. The SOI region 110 comprises a first dielectric layer 120 located over the microelectronics substrate 115, a biasing layer 125 located over the first... Agent: Texas Instruments Incorporated

20070026585 - Patterned-print thin-film transistors with top gate geometry: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to... Agent: JasIPConsulting Suite F

20070026586 - Mask for manufacturing a display substrate capable of improving image quality: A mask for forming a display substrate capable of improving color reproducibility by avoiding color spots and color shifts is presented. The mask includes a first sub-mask, a second sub-mask, a first overlapping portion and a second overlapping portion. The first sub-mask includes color reticles to form color pixels in... Agent: Macpherson Kwok Chen & Heid LLP

20070026587 - Normally off iii-nitride semiconductor device having a programmable gate: A III-nitride semiconductor device which includes a charged gate insulation body.... Agent: Ostrolenk Faber Gerb & Soffen

20070026589 - Method and apparatus for stacking sheets, and method and apparatus for manufacturing liquid crystal display panel: A broad crystal display panel having a color filter substrate is supported by supporting nails and the middle portion of a supporting span is pressed by a loading bar. From this state, the supporting nails are removed to release the supporting, and subsequently the supporting nails are also removed to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070026588 - Method of fabricating a thin film transistor: A method of fabricating a thin film transistor is provided. An amorphous silicon layer is formed on a substrate. Then, the amorphous silicon layer is transformed into a polysilicon layer. After that, a heat process is performed for repairing the lattice defects of the polysilicon layer. Then, an ion implantation... Agent: Jianq Chyun Intellectual Property Office

20070026590 - Dynamic schottky barrier mosfet device and method of manufacture: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically... Agent: Dorsey & Whitney LLP Intellectual Property Department

20070026591 - Insulated gate field effect transistor having passivated schottky barriers to the channel: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which... Agent: Sonnenschein Nath & Rosenthal LLP

20070026593 - Diffusion barrier for nickel silicides in a semiconductor fabrication process: A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier “curtains” on sidewalls of the source/drain recesses. A metal layer is... Agent: Freescale Semiconductor, Inc. Law Department

20070026596 - Gate electrode structure and method of forming the same, and semiconductor transistor having the gate electrode structure and method of manufacturing the same: In a gate structure and a method of forming the same, a first conductive pattern is formed on a substrate and comprises a metal-containing material. A second conductive pattern is formed on the first conductive pattern, and the second conductive pattern comprises metal and silicon. A third conductive pattern is... Agent: Mills & Onello LLP

20070026594 - Method and apparatus for evaluating semiconductor layers: A method for evaluating semiconductor layers includes irradiating semiconductor layers on a substrate with light; measuring an optical spectrum peculiar to excitons in the semiconductor layers; and analyzing a broadening factor of optical spectral features of the optical spectrum. The method provides a quick measurement of a surface state of... Agent: Leydig Voit & Mayer, Ltd

20070026595 - Method for fabricating semiconductor device and method for designing semiconductor device: A method for fabricating a semiconductor device includes the steps of: forming a first MISFET including first source/drain regions and a first gate electrode of a polycrystalline silicon, and a second MISFET including second source/drain regions and a second gate electrode of a polycrystalline silicon and having a gate length... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070026597 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device including a MOS transistor includes: forming a gate electrode on a semiconductor substrate via a gate insulating film; performing ion implantation on the semiconductor substrate using the gate electrode as a mask, and performing a heat treatment, thereby forming a diffusion layer in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070026592 - Semiconductor device and method for manufacturing the same: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, in which active and inactive regions are separated by a field oxidation film; source/drain junctions contacting the field oxidation film and formed in the active regions of the semiconductor substrates; a... Agent: Marshall, Gerstein & Borun LLP

20070026600 - Manufacturing method of semiconductor device and semiconductor device: The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070026598 - Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations: A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of the first conductivity type on a second... Agent: Cantor Colburn LLP-ibm Burlington

20070026599 - Methods for fabricating a stressed mos device: Methods are provided for fabricating a stressed MOS device. The method comprises the steps of forming a plurality of parallel MOS transistors in and on a semiconductor substrate. The parallel MOS transistors having a common source region, a common drain region, and a common gate electrode. A first trench is... Agent: Ingrassia Fisher & Lorenz, P.C.

20070026601 - Dram constructions and electronic systems: The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The... Agent: Wells St. John P.s.

20070026602 - Method of minimal wafer support on bevel edge of wafer: The present invention generally provides a method and apparatus for supporting and transferring a substrate in and out a wet cleaning chamber with minimal contact. One embodiment of the present invention provides an apparatus for support and transferring a substrate. The apparatus comprises a frame connected with an actuator configured... Agent: Patterson & Sheridan, LLP

20070026603 - Methods for fabricating dynamic random access memory cells having laterally offset storage nodes: DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided... Agent: Myers Bigel Sibley & Sajovec

20070026604 - Semiconductor device and fabrication method therefor: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy... Agent: Wagner, Murabito & Hao LLP

20070026605 - Fabricating approach for memory device: To address problems encountered during the fabrication of a nonvolatile memory cell, such as preventing top oxide loss, preventing contact between the nitride and the polysilicon, and reducing the problem of BD over-diffusion, various fabrication embodiments are used. In one approach, the top dielectric of an ONO structure is formed... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20070026608 - Flash memory devices having multilayered inter-gate dielectric layers including metal oxide layers and methods of manufacturing the same: Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active regions; forming an inter-gate dielectric layer on the semiconductor substrate... Agent: Myers Bigel Sibley & Sajovec

20070026606 - Method and structure for fabricating non volatile memory arrays: An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first... Agent: Townsend And Townsend And Crew, LLP

20070026607 - Method for forming floating gate in flash memory device: A method for fabricating a nonvolatile memory device including successively forming a first oxide layer, an electrically conductive layer, a second oxide layer, a nitride layer and a third oxide layer on a semiconductor substrate. The method also includes patterning the third oxide layer, forming spacers at sidewalls of the... Agent: Mr. Heong Jin Kim

20070026609 - Non-volatile memory and fabricating method thereof: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between... Agent: J C Patents, Inc.

20070026610 - Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure: An integrated circuit includes a semiconductor substrate including first and second portions, with first electronic devices adjacent the first portion. Each first electronic device includes a first region comprising at least one first conductive layer projecting from the semiconductor substrate. First protective spacers are adjacent sidewalls of the first regions... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070026611 - Method for manufacturing semiconductor devices: A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing Al2O3 and a polysilicon or SiO2 layer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl3,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070026612 - Method of fabricating flash memory device having self-aligned floating gate: A method of fabricating a flash memory device having a self-aligned floating gate (SAFG) wherein a floating gate is formed by a SAFG process. After a dielectric layer is formed, the dielectric layer of a test pattern region is stripped and a control gate is formed so that the control... Agent: Marshall, Gerstein & Borun LLP

20070026613 - Flash memory device having a split gate: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer... Agent: Lee & Morse, P.C.

20070026614 - Cmos-compatible high-performance microscanners, including structures, high-yield simplified fabrication methods and applications: The present invention relates to systems and methods for fabricating microscanners. The fabrication processes employed pursuant to some embodiments are compatible with well known CMOS fabrication techniques, allowing devices for control, monitoring and/or sensing to be integrated onto a single chip. Both one- and two-dimensional microscanners are described. Applications including... Agent: Michaelson & Associates

20070026615 - Method of forming a finfet structure: A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gate (18) and channel (23) connected via source/drain extensions (22, 24) which... Agent: Freescale Semiconductor, Inc. Law Department

20070026616 - Method for fabricating semiconductor device and semiconductor device fabricated using the same: Provided are a method for fabricating a semiconductor device and a semiconductor device fabricated using the same. The method for fabricating a semiconductor device comprises forming gate stacks on a semiconductor substrate, forming gate spacers made of a dielectric material having a dielectric constant of 2 to 4, on the... Agent: Marshall, Gerstein & Borun LLP

20070026617 - Method of fabricating semiconductor side wall fin: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.... Agent: Whitham, Curtis & Christofferson, P.C.

20070026618 - Method of manufacturing high-voltage device: A method of manufacturing a high-voltage device DDD (Double Doped Drain) ion implantation process is performed at a tilt angle in order to form a smooth junction profile. Accordingly, the intensity of an electric field can be reduced and breakdown voltage margin can be secured.... Agent: Marshall, Gerstein & Borun LLP

20070026620 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device having high output power and excellent long-term reliability by preventing thermal adverse influence exerted at the time of window structure formation is provided. The method comprises a 1st step of forming predetermined semiconductor layers 2 to 9 containing at least an active layer... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070026619 - Thin-film transistor, method for manufacturing thin-film transistor, and display using thin-film transistors: The present invention provides a thin-film transistor offering a higher electron (or hole) mobility, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. The present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070026621 - Non-volatile semiconductor devices and methods of manufacturing the same: Provided herein is a non-volatile semiconductor device that includes a tunnel insulation layer pattern formed on a semiconductor substrate, a charge trapping layer pattern formed on the tunnel insulation layer pattern, a blocking dielectric layer pattern formed on the charge trapping layer pattern and a tantalum carbon nitride layer pattern... Agent: Myers Bigel Sibley & Sajovec

20070026623 - Method for producing electrochemical capacitor electrode: A method is provided for optimizing the physical characteristics of a coating solution for a polarizable electrode layer formed on a collector. A first step is carried out to prepare a coating solution that includes porous particles, a fluorine-based binder, a good solvent that dissolves said fluorine-based binder, and a... Agent: Young Law Firm, P.C. Alan W. Young

20070026622 - Method for producing solid electrolytic capacitor: The invention provides a method for producing a solid electrolytic capacitor reliable with good LC value after mounting, wherein a solid electrolytic capacitor element comprises an anode body composed of a material containing at least one selected from a group consisting of an earth-acid metal, an alloy comprising an earth-acid... Agent: Sughrue Mion, PLLC

20070026626 - Integrated decoupling capacitor process: The present invention discloses a fabrication process for integrated high dielectric constant capacitors for circuit decoupling. The top electrode is protected against the re-deposition of material from the bottom electrode during the patterning process of the bottom electrode, thus provides better capacitor yield against the shortage of top and bottom... Agent: Tue Nguyen

20070026625 - Method of fabricating metal-insulator-metal capacitor: In one embodiment, a method of fabricating a MIM capacitor includes forming an interlayer insulating layer having a contact plug on a semiconductor substrate, forming an etch stop layer on the interlayer insulating layer, and forming a mold layer having an opening exposing the contact plug on the etch stop... Agent: Marger Johnson & Mccollom, P.C.

20070026624 - Process of producing activated carbon for electrode of electric double layer capacitor: A process for producing an activated carbon for an electrode of an electric double-layer capacitor, includes a step of subjecting a carbonized material to an alkali activating treatment, wherein the carbonized material has an average true specific gravity of 1.450 to 1.650 and a variation of the true specific gravities... Agent: Arent Fox PLLC

20070026627 - Well photoresist pattern of semiconductor device and method for forming the same: Disclosed is a well photoresist pattern of a semiconductor, and the fabrication method thereof. The method includes the steps of: (a) forming a sacrificial oxide layer on a semiconductor substrate; (b) applying a primer on the sacrificial oxide layer; (c) applying a photoresist on the primer; (d) soft-baking the photoresist;... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070026628 - Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses: A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or... Agent: Howard Chen Preston Gates & Ellis LLP

20070026631 - Metal pad or metal bump over pad exposed by passivation layer: A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed... Agent: North America Intellectual Property Corporation

20070026632 - Method of manufacturing a semiconductor device and the semiconductor device: The present invention provides a method of manufacturing a trench with a rounded corner portion and a broadened opening. Anisotropic oxidation is carried out using a halogen oxidation method using dichloroethylene (DCE) to form an anisotropic oxide film such that the film thickness in a shoulder portion of the trench... Agent: Mcdermott Will & Emery LLP

20070026629 - Novel structure for a multiple-gate fet device and a method for its fabrication: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form... Agent: Haynes And Boone, LLP

20070026630 - Reliable gap-filling process and apparatus for performing the process in the manufacturing of semiconductor devices: A reliable gap-filling process is performed in the manufacturing of a semiconductor device. An apparatus for performing the gap-filling process includes a chamber in which a wafer chuck is disposed, a plasma generator for generating plasma used to etch the wafer, an end-point detection unit for detecting the point at... Agent: Volentine Francos, & Whitt PLLC

20070026633 - Semiconductor device and related method: A semiconductor device comprising a trench device isolation layer and a method for fabricating the semiconductor device are disclosed. The method comprises forming a plurality of first trenches on a first region of a semiconductor substrate, filling the first trenches with a first insulation material to form first device isolation... Agent: Volentine Francos, & Whitt PLLC

20070026634 - Etch back with aluminum cmp for lcos devices: A method for manufacturing an LCOS device. The method includes providing a substrate (e.g., silicon wafer) having a surface region. The method includes forming an interlayer dielectric layer overlying the surface region of the substrate. The method patterns the interlayer dielectric layer to form a plurality of recessed regions. Each... Agent: Townsend And Townsend And Crew, LLP

20070026635 - Crystallization method of amorphous silicon for forming large grain, and layer structure employed for the crystallization method: A layer structure comprising substrate, a metal layer, a first amorphous silicon layer, an insulating layer, and a second amorphous silicon layer, and a method of crystallizing the second amorphous silicon layer by irradiating single pulse laser to the layer structure are provided. The method provides an effect of forming... Agent: Ladas & Parry LLP

20070026636 - Wide and narrow trench formation in high aspect ratio mems: Methods have been provided for forming both wide and narrow trenches on a high-aspect ratio microelectromechanical (MEM) device on a substrate including a substrate layer (126), an active layer (128), and a first sacrificial layer (130) disposed at least partially therebetween. The method includes the steps of forming a first... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070026639 - Manufacturing method of semiconductor device: A glass substrate is bonded through a resin to the top surface of a semiconductor wafer on which a first wiring is formed. A V-shaped groove is formed by notching from the back surface of the wafer. A second wiring connected with the first wiring and extending over the back... Agent: Morrison & Foerster LLP

20070026638 - Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process: A reusable transfer substrate member for forming a tiled substrate structure. The member including a transfer substrate, which has a surface region. The surface region comprises a plurality of donor substrate regions. Each of the donor substrate regions is characterized by a donor substrate thickness and a donor substrate surface... Agent: Townsend And Townsend And Crew, LLP

20070026637 - Soi wafer and its manufacturing method: Since a supporting wafer contains nitrogen of 1×1014 atmos/cm3 and interstitial oxygen atom concentration, Oi, (old ASTM) of 13×1017 atoms/cm3, therefore a part of the metal impurities in an active layer wafer and the metal impurities in a bonded wafer can be captured by the BMD and the OSF in... Agent: Greenblum & Bernstein, P.L.C

20070026640 - Method for adhering protecting tape of wafer and adhering apparatus: A method for adhering a protecting tape to a protection surface of a wafer is disclosed. The method comprises: cutting the protecting tape of which one surface is processed to be an adhering surface into predetermined size and shape; storing the protecting tape so as to release tensile force therein;... Agent: Brinks Hofer Gilson & Lione

20070026641 - Film separation method and film separation apparatus: A film separation apparatus (100) for separating a film (110) attached to a film application surface of a wafer (120) comprises a wafer adsorption unit (31) for adsorbing the wafer with the film application surface up, a release tape supply unit (42) for supplying the release tape (3) onto the... Agent: Christie, Parker & Hale, LLP

20070026645 - Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest... Agent: Wolf Greenfield & Sacks, PC

20070026643 - Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method: A growth plane of substrate 1 is processed to have a concavo-convex surface. The bottom of the concave part may be masked. When a crystal is grown by vapor phase growth using this substrate, an ingredient gas does not sufficiently reach the inside of a concave part 12, and therefore,... Agent: Leydig Voit & Mayer, Ltd

20070026644 - Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method: A growth plane of substrate 1 is processed to have a concavo-convex surface. The bottom of the concave part may be masked. When a crystal is grown by vapor phase growth using this substrate, an ingredient gas does not sufficiently reach the inside of a concave part 12, and therefore,... Agent: Leydig Voit & Mayer, Ltd

20070026642 - Surface modification method and surface modification apparatus for interlayer insulating film: The present invention relates to a method for modifying a surface of an interlayer insulating film that is formed by applying a coating solution on a substrate to form a coating film, and sintering the coating film at a predetermined temperature. The method comprises the steps of: heating an inside... Agent: Smith, Gambrell & Russell

20070026646 - Method for arraying nano material and method for fabricating liquid crystal display device using the same: A method for arraying nano material includes preparing a substrate coated with a dispersion solution where nano materials are dispersed and arraying the nano materials in the dispersion solution, in a uniform direction using a charged body.... Agent: Brinks Hofer Gilson & Lione

20070026647 - Method for forming polycrystalline silicon thin film: A method for forming a polycrystalline silicon thin film, comprising steps of: providing a substrate; forming an amorphous silicon thin film on the substrate; and inducing a plurality of eddy currents to heat up the substrate such that the amorphous silicon thin-film is annealed to form the polycrystalline silicon thin... Agent: Bruce H. Troxell

20070026648 - Sequential lateral solidification mask: A sequential lateral solidification (SLS) mask comprises a plurality of parallelizing repeat patterns. Each of the patterns further comprises a major symmetrical axis and a short axis, and each of the patterns is also composed of first units and second units, in which both the first unit and the second... Agent: Birch Stewart Kolasch & Birch

20070026649 - Plasma doping method and plasma doping apparatus: In order to realize a plasma doping method capable of carrying out a stable low-density doping, exhaustion is carried out with a pump while introducing a predetermined gas into a vacuum chamber from a gas supplying apparatus, the pressure of the vacuum chamber is held at a predetermined pressure and... Agent: Sheridan Ross PC

20070026650 - Method of limiting vacancy diffusion in a heterostructure: A method of fabricating a heterostructure comprising at least a first layer of semi-conductor material such as, for example, a silicon-germanium (SiGe) layer on a second layer or a substrate of another material. The material of the second layer may differ from that of the first layer. To prevent elements... Agent: Winston & Strawn LLP Patent Department

20070026651 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first... Agent: Harness, Dickey & Pierce, P.L.C

20070026652 - Soi device with reduced drain induced barrier lowering: A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating... Agent: Knobbe Martens Olson & Bear LLP

20070026653 - Cap layer on doped dielectric: A method for capping over a doped dielectric. The method comprises providing a substrate and depositing a doped dielectric layer on the substrate from a gas mixture. The gas mixture comprises a silicon source gas, a dopant gas and an oxygen source gas. A cap layer is in-situ deposited on... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070026654 - Systems and methods for avoiding base address collisions: Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal... Agent: Knobbe Martens Olson & Bear LLP

20070026655 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device for use in such applications as a flash memory device, a field insulating pattern defines an opening that exposes an active region of a semiconductor substrate. The field insulating pattern includes a first portion protruding from the substrate and a second portion... Agent: Mills & Onello LLP

20070026656 - Method and structure for landing polysilicon contact: A method for fabricating an integrated circuit device, e.g., DRAM. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of MOS transistor devices overlying the semiconductor substrate. Each of the MOS transistor devices has a nitride cap and nitride sidewall spacers. Each of... Agent: Townsend And Townsend And Crew, LLP

20070026657 - Methods of forming semiconductor devices with contact holes self-aligned in two directions and devices so formed: A method of forming a semiconductor device can include forming a plurality of gate structure patterns including gates and first mask patterns stacked on a semiconductor substrate, the gate structure patterns being spaced apart from each other and extending in a first direction, forming a first interlayer insulating layer covering... Agent: Myers Bigel Sibley & Sajovec

20070026658 - Process of forming an as-grown active p-type iii-v nitride compound: In a method of forming an as-grown active p-type III-V nitride compound layer, a substrate is introduced and heated in a reaction chamber. N2 carrier gas and reactive compounds including a source compound of a group III element, a nitrogen source compound, and a p-type impurity are fed in the... Agent: David I. Roche Baker & Mckenzie LLP

20070026660 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device, including: (a) forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; (b) fusing the resin layer without being cured and shrunk by a first energy supply processing; (c) forming a resin boss by curing... Agent: Oliff & Berridge, PLC

20070026659 - Post last wiring level inductor using patterned plate process: A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.... Agent: Schmeiser, Olsen & Watts

20070026661 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes: (a) preparing a semiconductor chip having a plurality of electrodes; (b) preparing a substrate having a plurality of electrical connection portions; (c) holding the semiconductor chip by a holding tool; (d) planarizing an upper surface of the electrode of the semiconductor chip... Agent: Harness, Dickey & Pierce, P.L.C

20070026662 - Semiconductor device and method of manufacturing the same: A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10,... Agent: Young & Thompson

20070026663 - A semiconductor device and method for manufacturing the semiconductor device: A semiconductor device, comprises: a wiring formed on a first insulating film, a second insulating film formed on the first insulating film and on the wiring, a contact hole formed in the second insulating film and located on the wiring, a coating that covers a sidewall of the contact hole... Agent: Harness, Dickey & Pierce, P.L.C

20070026664 - Semiconductor device and a method of manufacturing the same: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu... Agent: Miles & Stockbridge PC

20070026665 - Method of fabricating a dual damascene interconnect structure: A method of fabricating a dual damascene interconnect structure uses a very high frequency high-density plasma and selectively controlled substrate bias for in-situ etching a trench above a via hole of the interconnect structure and a barrier layer between the via hole and underlying conductive layer.... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070026666 - Method of forming metal line on semiconductor device: Provided is a method of forming a metal line of a semiconductor device. The method includes the following. A metal line is formed on a semiconductor substrate. An etch barrier layer is formed on the entire surface of the semiconductor substrate including the metal line. A low-k dielectric layer is... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070026667 - Composition for forming etching stopper layer: An object of the present invention is to provide a composition for formation of etching stopper layer, which can simultaneously realize dry etching selectivity and low permittivity, and a production process of a semiconductor device using the same. This object can be attained by a composition for formation of etching... Agent: Az Electronic Materials Usa Corp. Attention: Industrial Property Dept.

20070026668 - Low k dielectric surface damage control: A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying... Agent: Duane Morris LLPIPDepartment (tsmc)

20070026669 - Semiconductor device and method of fabricating the same: A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate; a wiring formed in predetermined pattern above the semiconductor substrate, a first insulating film lying right under the wiring, and a second insulating film lying in a peripheral portion other than a portion right under... Agent: Foley And Lardner LLP Suite 500

20070026670 - Method of reducing contamination by removing an interlayer dielectric from the substrate edge: By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of... Agent: Williams, Morgan & Amerson

20070026671 - Method of forming low resistance tungsten films: Provided is a method for forming low resistance metal films in which an underlying film, for example, a barrier layer or an adhesion layer, is formed on a semiconductor substrate. The underlying film is then subjected to a partial etch back in order to reduce the surface roughness and form... Agent: Harness, Dickey & Pierce, P.L.C

20070026672 - Pitch doubled circuit layout: In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing... Agent: Knobbe Martens Olson & Bear LLP

20070026673 - Semiconductor device having a multilayer interconnection structure and fabrication process thereof: A multilayer interconnection structure includes a first interconnection layer having a copper interconnection pattern and a second interconnection layer having an aluminum interconnection layer and formed on the first interconnection layer via an intervening interlayer insulation film, wherein a tungsten plug is formed in a via-hole formed in the interlayer... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070026677 - Method for plasma etching performance enhancement: A method for etching features in a dielectric layer is provided. A mask is formed over the dielectric layer. A protective silicon-containing coating is formed on exposed surfaces of the mask. The features are etched through the mask and protective silicon-containing coating. The features may be partially etched before the... Agent: Beyer Weaver & Thomas, LLP

20070026674 - Method of protecting wafer front pattern and method of performing double-sided process: A wafer comprising a front surface and a back surface is provided. The wafer further includes a front pattern on the front surface, the front pattern having a plurality of holes. A low-viscosity fluid is formed on the front surface and filled into the holes. Following that, a high-viscosity fluid... Agent: North America Intellectual Property Corporation

20070026675 - System and method for improving mesa width in a semiconductor device: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench... Agent: Harrity Snyder, L.L.P.

20070026676 - Via hole machining for microwave monolithic integrated circuits: A method for forming a via in a sapphire substrate with a laser machining system that includes an ultrafast pulsed laser source. The sapphire substrate is provided. Pulses of laser light are substantially focused to a beam spot on the first surface of the sapphire substrate such that each focused... Agent: Ratnerprestia

20070026678 - Wet etchable laminated body, insulation film, and electronic circuit part using the laminated body and the film: The present invention provides a laminate comprising an insulating layer having suppressed dusting properties, an insulating film comprising the insulating layer, and an electronic circuit component comprising a pattern of the insulating layer. The laminate has a layer construction of first inorganic material layer-insulating layer-second inorganic material layer or a... Agent: Oliff & Berridge, PLC

20070026679 - Method and structure for aluminum chemical mechanical polishing and protective layer: A method for chemical mechanical polishing of mirror structures. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a first dielectric layer overlying the semiconductor substrate and forming an aluminum layer overlying the first dielectric layer, the aluminum layer having an upper surface with a... Agent: Townsend And Townsend And Crew, LLP

20070026680 - Method for manufacturing semiconductor device: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a bit line contact region and a storage node contact region are simultaneously formed, and then a storage node contact hole is formed after a form of bit line to reduce a height of a... Agent: Heller Ehrman White & Mcauliffe LLP

20070026681 - Dry etching process and method for manufacturing magnetic memory device: Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry... Agent: Rader Fishman & Grauer PLLC

20070026682 - Method for advanced time-multiplexed etching: A method of anisotropic plasma etching of a substrate material through a window defined in an etching mask comprises the steps of: disposing a hard mask material by injection of a precursor gas or precursor liquid and plasma-activated deposition to form a hard mask layer to form a temporary etch... Agent: Daniel L. Dawes Myers Dawes Andras & Sherman LLP

20070026683 - Method for reducing amine based contaminants: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not... Agent: Greenblum & Bernstein, P.L.C

20070026684 - Method of producing pitch fractionizations in semiconductor technology: Spacers are formed on sidewalls of striplike parts of a pattern layer of periodic structure. The pattern layer is removed, and the spacers are covered with a further spacer layer, which is then structured to second sidewall spacers. Gaps between the spacers are filled with a complementary layer. The upper... Agent: Slater & Matsil LLP

20070026685 - Mask structure, method of forming the mask structure, method of forming a pattern using the mask structure and method of forming contacts in a semiconductor device using the mask structure: A mask structure may include a first mask pattern and a second mask pattern formed on an object. When the object includes a first material, the first and the second mask patterns may include a second material and a third material, respectively. The second mask pattern may have at least... Agent: Harness, Dickey & Pierce, P.L.C

20070026686 - Self-repair and enhancement of nanostructures by liquification under guiding conditions: In accordance with the invention, the structure of a patterned nanoscale or near nanoscale device (“nanostructure”) is repaired and/or enhanced by liquifying the patterned device in the presence of appropriate guiding conditions for a period of time and then permitting the device to solidify. Advantageous guiding conditions include adjacent spaced... Agent: Polster, Lieder, Woodruff & Lucchesi

20070026687 - Oxygen-rich gas supplying apparatus provided with a condensate removal unit: An apparatus for supplying an oxygen-rich gas includes an oxygen-rich gas generating device for generating an oxygen-rich gas; and a condensate removal unit for removing condensates occurring in a transfer line from the oxygen-rich gas. The condensate removal unit has an inlet, an outlet and a drain port and the... Agent: Bacon & Thomas, PLLC

20070026688 - Method of forming a zro2 thin film using plasma enhanced atomic layer deposition and method of fabricating a capacitor of a semiconductor memory device having the thin film: Example embodiments of the present invention relate to a method of forming a dielectric thin film and a method of fabricating a semiconductor memory device having the same. Other example embodiments of the present invention relate to a method of forming a ZrO2 thin film and a method of fabricating... Agent: Harness, Dickey & Pierce, P.L.C

20070026689 - Silica film forming material, silica film and method of manufacturing the same, multilayer wiring structure and method of manufacturing the same, and semiconductor device and method of manufacturing the same: The silica film forming material of the present invention comprises a silicone polymer which comprises, as part of its structure, CHx, an Si—O—Si bond, an Si—CH3 bond and an Si—CHx- bond, where x represents an integer of 0 to 2.... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070026690 - Selective frequency uv heating of films: A layer, such as a dielectric, formed on a substrate, such as a silicon substrate, is heated by selecting a specific wavelength or energy for the material of the layer, such that photons readily pass and are absorbed by the material and then reflected from the interface of the layer... Agent: Macpherson Kwok Chen & Heid LLP

20070026691 - Low-field non-contact charging apparatus for testing substrates: An apparatus and method for charging substrates without introducing high electric fields into the work environment. A non-contact charging plate is combined with a source of bipolar air (or gas) ions to effect the charging. This method is useful for studying the effects of static charge in charge sensitive processes.... Agent: Mks Instruments Inc.

20070026692 - Method for applying a high temperature heat treatment to a semiconductor wafer: The invention provides methods for applying high temperature treatments to semiconductor wafers that limit surface tearing-off defects and surface particle contamination. In preferred embodiments, the high temperature treatments begin at boat-in temperatures of less than about 550° C. and include a first temperature ramp-up to the HT treatment temperatures at... Agent: Winston & Strawn LLP Patent Department

20070026693 - Method of thermally oxidizing silicon using ozone: A method and apparatus for oxidizing materials used in semiconductor integrated circuits, for example, for oxidizing silicon to form a dielectric gate. An ozonator is capable of producing a stream of least 70% ozone. The ozone passes into an RTP chamber through a water-cooled injector projecting into the chamber. Other... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.