Semiconductor device manufacturing: process inventions 01/07

20070020772 - Gradient structures interfacing microfluidics and nanofluidics, methods for fabrication and uses thereof: The present invention relates to a device for interfacing nanofluidic and microfluidic components suitable for use in performing high throughput macromolecular analysis. Diffraction gradient lithography (DGL) is used to form a gradient interface between a microfluidic area and a nanofluidic area. The gradient interface area reduces the local entropic barrier... Agent: Woodcock Washburn LLP

20070020771 - Nanoparticles and method of making thereof: A method of making nanoparticles includes contacting a powder having particles of a first size and an etching material, and heating the powder and the etching material to reduce particles of the first size to nanoparticles having a second size smaller than the first size.... Agent: Foley And Lardner LLP Suite 500

20070020773 - Fabrication of nano-object array: This disclosure relates to a system and method for creating nano-object arrays. A nano-object array can be created by exposing troughs in a corrugated surface to nano-objects and depositing the nano-objects within or orienting the nano-objects with the troughs.... Agent: Hewlett Packard Company

20070020774 - Methods of utilizing magnetoresistive memory constructions: The invention includes a method of forming a magnetoresistive memory device having a memory bit stack. The stack includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization... Agent: Wells St. John P.s.

20070020775 - System and method for reducing shorting in memory cells: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and,... Agent: Knobbe Martens Olson & Bear LLP

20070020776 - Method and apparatus for wall film monitoring: A wall film monitoring system includes first and second microwave mirrors in a plasma processing chamber each having a concave surface. The concave surface of the second mirror is oriented opposite the concave surface of the first mirror. A power source is coupled to the first mirror and configured to... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070020777 - Controlling system for gate formation of semiconductor devices: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may... Agent: Slater & Matsil, L.L.P.

20070020778 - Method and monitor structure for detecting and locating ic defects: A 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process, the method including forming a first metallization layer; carrying out a first wafer acceptance testing (WAT) process to test the electrical continuity... Agent: Tung & Associates

20070020783 - Method of feed forward control of scanned rapid thermal processing: A thermal processing system and method including scanning a line beam of intense radiation in a direction transverse to the line direction for thermally processing a wafer with a localized effectively pulsed beam of radiant energy. The thickness of the wafer is two-dimensionally mapped and the map is used to... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20070020782 - Method of monitoring a semiconductor manufacturing trend: A method of monitoring trends in semiconductor processes is provided. Lot values are assigned to each of a set of wafer lots prior to performing semiconductor processes. After at least some of the semiconductor processes, at least some of the wafer lots are tested to generate a set of test... Agent: Barry Dove Patent Services, Inc.

20070020780 - Method of processing semiconductor substrate responsive to a state of chamber contamination: In one embodiment, a method of processing a semiconductor substrate includes measuring a state of a processing chamber contamination before processing each semiconductor substrate. A process condition is then changed responsive to the state of chamber contamination to compensate for an influence of the state of chamber contamination on the... Agent: Marger Johnson & Mccollom, P.C.

20070020779 - Quantum dot conjugates in a sub-micrometer fluidic channel: A nanofluidic channel fabricated in fused silica with an approximately 500 nm square cross section was used to isolate, detect and identify individual quantum dot conjugates. The channel enables the rapid detection of every fluorescent entity in solution. A laser of selected wavelength was used to excite multiple species of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020781 - Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display... Agent: Drinker Biddle & Reath (dc)

20070020784 - Method and system for determining optical properties of semiconductor wafers: A method and system are disclosed for determining at least one optical characteristic of a substrate, such as a semiconductor wafer. Once the optical characteristic is determined, at least one parameter in a processing chamber may be controlled for improving the process. For example, in one embodiment, the reflectivity of... Agent: Dority & Manning, P.A.

20070020785 - Systems and methods for alignment of laser beam(s) for semiconductor link processing: A method makes a discrete adjustment to static alignment of a laser beam in a machine for selectively irradiating conductive links on or within a semiconductor substrate using the laser beam. The laser beam propagates along a beam path having an axis extending from a laser to a laser beam... Agent: Stoel Rives LLP

20070020786 - Device comprising a field of tips used in biotechnology applications: A method for manufacturing a device including a field of micrometric tips, including forming a polycrystalline layer on a support; performing an anisotropic plasma etching of all or part of the polycrystalline layer by using a gas mixture including chlorine and helium, whereby tips are formed at the surface of... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070020787 - Electrifying method and manufacturing method of electron-source substrate: m

20070020788 - Fabrication method of high-brightness light emitting diode having reflective layer: A method for fabricating a high brightness LED structure is disclosed herein, which comprises at least the following steps. First, a first layered structure is provided by sequentially forming a light generating structure, a non-alloy ohmic contact layer, and a first metallic layer from bottom to top on a side... Agent: Lin & Associates Intellectual Property

20070020791 - Image sensor with optical guard ring and fabrication method thereof: An image sensor device and fabrication method thereof wherein a substrate having at least one shallow trench isolation structure therein is provided. At least one photosensor and at least one light emitting element, e.g., such as MOS or LED, are formed in the substrate. The photosensor and the light emitting... Agent: Birch Stewart Kolasch & Birch

20070020790 - Light emitting device methods: Light-emitting device methods are disclosed.... Agent: Wolf Greenfield & Sacks, PC

20070020789 - Light emitting devices and method for fabricating the same: Light emitting devices and a method for fabricating the same have an advantage in that an etching film formed between a plurality of light emitting structures is removed to separate respective lateral surfaces of the light emitting structures from one another, and a substrate is removed to separate lower portions... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070020792 - Optical sheet, backlight unit, electro-optic device, electronic device, method for manufacturing optical sheet, and method for cutting optical sheet: A method for manufacturing an optical sheet includes: a) discharging a liquid lens material onto a sheet having a light-transmitting property, the liquid lens material being to be a material of micro lenses; b) discharging a liquid material onto the sheet, the liquid material being to be a material of... Agent: Harness, Dickey & Pierce, P.L.C

20070020793 - Three-dimensional shaped solid dosimeter and method of use: The invention relates to a solid plastic three-dimensional dosimeter which is useful in treatment planning, optimization of the radiation field, dose verification, dose validation, commissioning, and quality assurance of complex radiotherapeutic procedures. Dosimeters of the invention can be formed in any clinically relevant shape, and contain a reporter leuco dye... Agent: Mathews, Shepherd, Mckay, & Bruneau, P.A.

20070020794 - Method of strengthening a microscale chamber formed over a sacrificial layer: A method for forming an improved chamber for a micro-electromechanical device includes depositing a sacrificial layer on a substrate; depositing a masking layer on a surface of the sacrificial layer; removing at least one predetermined portion of the masking layer down to the sacrificial layer to form an etch pattern;... Agent: Mark G. Bocchetti Patent Legal Staff

20070020796 - Image sensor having multi-gate insulating layers and fabrication method: An image sensor and related method of fabrication are disclosed. The image sensor includes a first gate insulating layer of first material layer type disposed in a sensor region of a semiconductor substrate, a second gate insulating layer of second material layer type disposed in an analog region of the... Agent: Volentine Francos, & Whitt PLLC

20070020795 - Solid-state imaging device and its manufacturing method: In a method for manufacturing a solid-state imaging device of the present invention, a pad insulting film 2 made of an oxide film and an anti-oxidizing film 3 made of a nitride film are deposited on a n-type semiconductor substrate 1. Then, an opening 4 is formed to expose an... Agent: Mcdermott Will & Emery LLP

20070020797 - Self-aligned process for manufacturing phase change memory cells: A process for manufacturing phase change memory cells includes the step of forming a heater element in a semiconductor wafer and a storage region of a phase change material on and in contact with the heater element. In order to form the heater element and the phase change storage region... Agent: Seed Intellectual Property Law Group PLLC

20070020798 - Methods to minimize contact resistance: A method is disclosed for making a metal electrode which minimizes the contact resistance between it and an organic semiconductor. Acid-stabilized metal nanoparticles are deposited upon a substrate and annealed. This creates a metal electrode and releases acid. Upon deposition of semiconductor and subsequent annealing, the acid diffuses from the... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070020799 - Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation... Agent: Marger Johnson & Mccollom, P.C.

20070020805 - Etch stop layer for silicon (si) via etch in three-dimensional (3-d) wafer-to-wafer vertical stack: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the... Agent: Intel/blakely

20070020800 - Ic chip mounting method: An IC chip mounting method which mounts two or more IC chips on a base, includes: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by dividing the wafer into... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070020801 - Ic chip mounting method: The present invention provides an IC chip mounting method for mounting two or more IC chips on a base, including: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070020806 - Method and structure for forming strained si for cmos devices: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only... Agent: Greenblum & Bernstein, P.L.C

20070020804 - Method of manufacturing electronic circuit device: The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an electrode pad 16 integrally formed with the interconnect 14; preparing an electronic circuit chip 20 including a solder electrode 22; and melting... Agent: Mcginn Intellectual Property Law Group, PLLC

20070020802 - Packaging method for segregating die paddles of a leadfram: The present invention relates to a packaging method for segregating die paddles of a leadframe. The method comprising: (a) providing a leadframe having a top surface, a bottom surface and a die paddle region, the die paddle region having a plurality of die paddles, wherein at least two of the... Agent: Volentine Francos, & Whitt PLLC

20070020807 - Protective structures and methods of fabricating protective structures over wafers: A method of fabricating a protective structure and a packaged structure are described.... Agent: Avago Technologies, Ltd.

20070020803 - Semiconductor device and manufacturing method of the same: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070020808 - Low profile, chip-scale package and method of fabrication: Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate with first and second surfaces, at least one opening, and a certain thickness. On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads; at least one of the contact pads... Agent: Texas Instruments Incorporated

20070020809 - Semiconductor device and method of producing high contrast identification mark: A semiconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts with the color of the semiconductor die. The coating layer is patterned to... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070020811 - Method and apparatus for attaching microelectronic substrates and support members: A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first surface, a second surface facing opposite the first surface, and a projection extending away from the first surface. A quantity of adhesive material can be... Agent: Perkins Coie LLP Patent-sea

20070020810 - Thermoplastic/thermoset composition material and method of attaching a wafer to a substrate: A process for mounting a wafer on a substrate includes applying a pre-applied die attach on a backside of the wafer with a composition having a thermoplastic portion and a thermoset portion. The composition has a predetermined cure temperature. The process further includes heating the wafer to a temperature sufficient... Agent: Lowrie, Lando & Anastasi

20070020812 - Circuit board structure integrated with semiconductor chip and method of fabricating the same: A circuit board structure integrated with semiconductor chip and a method of fabricating the same are proposed. A supporting plate formed with at least one cavity is provided and a semiconductor chip having a plurality of conductive contacts is embedded in the cavity. An anisotropic conductive film (ACF) layer and... Agent: Clark & Brody

20070020813 - Device and method for package warp compensation in an integrated heat spreader: A device and method for designing and manufacturing an integrated heat spreader so that the integrated heat spreader will have a flat surface on which to mount a heat sink after being assembled into a package and exposed to the heat of a die. This device and method for designing... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020814 - Methods of underfilling and encapsulating semiconductor assemblies with materials having selected properties using stereolithography: Methods of forming semiconductor packages include immersing a semiconductor device assembly in a liquid photopolymerizable resin including a plurality of discrete particles dispersed therethrough, and selectively at least partially curing portions of the resin adjacent at least one semiconductor die of the semiconductor device assembly. In some embodiments, the semiconductor... Agent: Trask Britt

20070020815 - Process for exposing solder bumps on an underfill coated semiconductor: A process for applying a solvent-free underfill onto a bumped semiconductor comprises: providing an underfill in a compressible state on a semiconductor, contacting the underfill with a compliant surface and applying sufficient pressure to expose the bumps, optionally hardening the underfill to a solid state, and removing the compliant surface.... Agent: Jane E. Gennaro National Starch An Chemical

20070020816 - Manufacturing process for chip package without core: A manufacturing process for chip package without core is disclosed. First of all, a conductive layer with a first surface and a second surface is provided. A first film is formed onto the first surface, and the conductive layer is patterned to form a patterned circuit layer. A solder resistance... Agent: J.c. Patents, Inc.

20070020817 - Wafer level incapsulation chip and encapsulation chip manufacturing method: A wafer level encapsulation chip and an encapsulation chip manufacturing method. The encapsulation chip includes a device substrate, a circuit module mounted on the device substrate, a bonding layer deposited on a predetermined area of the device substrate, a protection cap forming a cavity over the circuit module and bonded... Agent: Sughrue Mion, PLLC

20070020818 - Esd protection device in high voltage and manufacturing method for the same: Electrostatic discharge (ESD) protection device in high voltage and the relevant manufacturing method is disclosed. The mentioned ESD protection device is disposed to bridge a ground and an input connected with an inner circuit to be protected. In which, the ESD protection device for high voltage comprises at least one... Agent: Birch Stewart Kolasch & Birch

20070020819 - Vertical transistor structures having vertical-surrounding-gates with self-aligned features: The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in... Agent: David J. Paul Microntechnology, Inc.

20070020820 - Process for forming an electronic device including discontinuous storage elements: A process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate and forming a trench within the substrate. The process can also include forming a second set of discontinuous storage elements within the trench. The process can... Agent: Larson Newman Abel Polansky & White, LLP

20070020821 - Method for forming a thin-film transistor: A method for forming a thin-film transistor includes forming a source electrode and a drain electrode on an element-side substrate, forming a semiconductor layer in contact with the source electrode and the drain electrode, forming a gate insulating layer overlaid on the semiconductor layer, and forming a gate electrode overlaid... Agent: Harness, Dickey & Pierce, P.L.C

20070020822 - Method for manufacturing bottom substrate of liquid crystal display device: A method for manufacturing liquid crystal display substrates comprises the steps of: (a) providing a substrate having a transparent electrode layer and a metal layer; (b) forming a patterned photoresist layer through half-tone or diffraction; (c) defining signal line area and thin film diode area, or pixel area and conductive... Agent: Bacon & Thomas, PLLC

20070020823 - Method for manufacturing thin film device and semiconductor device: The present invention relates to a method for manufacturing a thin film device. The thin film device is manufactured by bonding a second substrate (106) to a thin film device layer (103) provided on a protective layer (102) formed on a first substrate (101) through a first adhesive layer (105),... Agent: Sonnenschein Nath & Rosenthal LLP

20070020826 - Method for manufacturing semiconductor device: It is an object of the invention to provide a technique forming a crystalline semiconductor film whose orientation is uniform by control of crystal orientation and obtaining a crystalline semiconductor film in which concentration of an impurity is reduced. A configuration of the invention is that a first semiconductor region... Agent: Nixon Peabody, LLP

20070020825 - Method of manufacturing thin film transistor substrate: A method of manufacturing a thin film transistor (TFT) substrate to minimize a rugged surface of an organic layer overlapping with a storage electrode is provided. The method includes forming a passivation layer on a substrate having a storage electrode and an organic layer covering the passivation layer, forming a... Agent: F. Chau & Associates, LLC

20070020824 - Multi-layered complementary conductive line structure and manufacturing method thereof and manufacturing method of a thin film transistor display array: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is... Agent: Jianq Chyun Intellectual Property Office

20070020827 - Methods of forming semiconductor device: A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type... Agent: Mills & Onello LLP

20070020828 - Method for manufacturing semiconductor apparatus and the semiconductor apparatus: A method for manufacturing a semiconductor apparatus, comprises: forming a first semiconductor layer on a semiconductor substrate of a transistor formation region; etching and removing a part of the first semiconductor layer sandwiched by a source formation region and a drain formation region to form a groove section in which... Agent: Edwards & Angell, LLP

20070020829 - Semiconductor device and a method of manufacturing the same: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching... Agent: Miles & Stockbridge PC

20070020835 - Atomic layer deposition of ceo2/al2o3 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020830 - Improved cmos (complementary metal oxide semiconductor) technology: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material... Agent: Schmeiser, Olsen & Watts

20070020834 - Method for forming film pattern, and method for manufacturing device, electro-optical device, electronic apparatus and active matrix substrate: A method for forming a film pattern, comprises: disposing a first bank forming material to a substrate so as to form a first bank layer; disposing a second bank forming material on the first bank layer so as to form a second bank layer; and pattering the first bank layer... Agent: Harness, Dickey & Pierce, P.L.C

20070020833 - Method for making a semiconductor device including a channel with a non-semiconductor layer monolayer: A method for making a semiconductor device may include forming at least one metal oxide semiconductor field-effect transistor (MOSFET) on a semiconductor substrate. The MOSFET may include spaced-apart source and drain regions, a channel between the source and drain regions, and a gate overlying the channel defining an interface therewith.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070020831 - Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming: A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes... Agent: Larson Newman Abel Polansky & White, LLP

20070020832 - Semiconductor devices and method of fabrication: A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070020836 - Method for manufacturing thin film transistor substrate: A method for manufacturing a TFT substrate includes forming a gate metal layer on an insulating substrate, forming a photo-sensitive layer pattern on the gate metal layer, forming a gate wiring by etching the gate metal layer using the photo-sensitive layer pattern, exposing the gate wiring by stripping the photo-sensitive... Agent: Cantor Colburn, LLP

20070020837 - High performance capacitors in planar back gates cmos: A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.... Agent: Greenblum & Bernstein, P.L.C

20070020838 - High performance capacitors in planar back gates cmos: Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer... Agent: Hoffman, Warnick & D'alessandro LLC

20070020839 - Methods to selectively protect nmos regions, pmos regions, and gate layers during epi process: A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner... Agent: Texas Instruments Incorporated

20070020840 - Programmable structure including nanocrystal storage elements in a trench: A storage cell includes a semiconductor substrate defining a trench, a bottom dielectric lining the trench, and a charge storage layer on the bottom dielectric. The charge storage layer includes a plurality of discontinuous storage elements (DSEs). A control gate and a top dielectric cover the DSEs. The storage cell... Agent: Larson Newman Abel Polansky & White, LLP

20070020841 - Method of manufacturing gate structure and method of manufacturing semiconductor device including the same: In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution.... Agent: Volentine Francos, & Whitt PLLC

20070020842 - Method of manufacturing mask rom: A method of manufacturing a ROM is disclosed. The method comprises steps of (a) providing a substrate and forming a plurality of gate structures on said substrate, (b) forming a first oxide layer on said substrate and said plurality of gate structures, (c) forming a mask layer on said first... Agent: Bacon & Thomas, PLLC

20070020843 - Method of producing a chip-type solid electrolytic capacitor: A chip-type solid electrolytic capacitor comprises capacitor elements. A cathode terminal comprising a plate-like conductor is interposed between cathode layers of the capacitor elements. The capacitor elements are bonded to each other by a bonding agent such as a solder or a conductive adhesive. The cathode terminal is provided with... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070020844 - Method for fabricating bit line of memory device: A damascene process. A substrate covered by a dielectric layer and an overlying polysilicon masking layer with an opening exposing the underlying dielectric layer is provided. The exposed dielectric layer is etched to form a damascene opening therein and a portion of polysilicon masking layer remains on the dielectric layer.... Agent: Quintero Law Office

20070020846 - Flash memory device and method for fabricating the same: A flash memory device including an isolation layer for defining active regions in a semiconductor substrate. The active region is a region in which flash memory cells are to be formed. The device also includes a gate stack is formed to come across the active region and the isolation layer,... Agent: Mayer, Brown, Rowe & Maw LLP

20070020847 - Method for fabricating flash memory device: A method of fabricating a flash memory device. A DDD ion is implanted into a high voltage PMOS transistor and into source and drain junctions of a cell transistor in order to facilitate a pinch-off phenomenon in the gate to drain overlap region and also increase the number of hot... Agent: Marshall, Gerstein & Borun LLP

20070020848 - Method for fabricating semiconductor device: In a method for fabricating a semiconductor device in which a semiconductor memory element having an ONO film and a CMOS part are formed on a single semiconductor substrate, a CMOS gate-oxidation step is performed several times. Thereafter, a bit line diffusion layer and a bit line oxide film are... Agent: Mcdermott Will & Emery LLP

20070020845 - Method of fabricating programmable structure including discontinuous storage elements and spacer control gates in a trench: A method of fabricating a semiconductor storage cell that includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals.... Agent: Larson Newman Abel Polansky & White, LLP

20070020849 - Source side injection storage device with spacer gates and method therefor: A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates... Agent: Freescale Semiconductor, Inc. Law Department

20070020851 - Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench and a method of using the same: A programmable storage device includes a first diffusion region underlying a portion of a first trench defined in a semiconductor substrate and a second diffusion region occupying an upper portion of the substrate adjacent to the first trench. The device includes a charge storage stack lining sidewalls and a portion... Agent: Larson Newman Abel Polansky & White, LLP

20070020850 - Method for manufacturing semiconductor device and semiconductor device: A method for manufacturing a semiconductor device including the steps of: forming a hole having a predetermined depth in a semiconductor layer of a first conductivity type in correspondence with a drain region, the semiconductor layer being formed on a semiconductor substrate; forming a diffusion source layer containing impurities of... Agent: Rabin & Berdo, P.C.

20070020852 - Semiconductor memory device with a stacked gate including a floating gate and a control gate: A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070020854 - Be-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is... Agent: Ronald L. Yin Patent Department

20070020853 - Bidirectional split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining... Agent: George W. Hughes

20070020855 - Semiconductor device having vertical channels and method of manufacturing the same: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The... Agent: Marger Johnson & Mccollom, P.C.

20070020856 - Process for forming an electronic device including discontinuous storage elements: forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also... Agent: Larson Newman Abel Polansky & White, LLP

20070020857 - Process for forming an electronic device including discontinuous storage elements: A process for forming an electronic device can include forming a first trench within a substrate, wherein the trench includes a wall and a bottom and extends from a primary surface of the substrate. The process can also include forming discontinuous storage elements and forming a first gate electrode within... Agent: Larson Newman Abel Polansky & White, LLP

20070020858 - Layout structure of mos transistors and methods of disposing mos transistors on an active region: In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench... Agent: Harness, Dickey & Pierce, P.L.C

20070020859 - Method of making non-volatile field effect devices and arrays of same: Methods of making non-volatile field effect devices and arrays of same. Under one embodiment, a method of making a non-volatile field effect device includes providing a substrate with a field effect device formed therein. The field effect device includes a source, drain and gate with a field-modulatable channel between the... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070020860 - Method for making semiconductor device including a strained superlattice and overlying stress layer and related methods: A method for making a semiconductor device may include forming a superlattice layer including a plurality of stacked groups of layers, and forming a stress layer above the strained superlattice layer to induce a strain therein. Each group of layers of the superlattice layer may include a plurality of stacked... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070020861 - Method to engineer etch profiles in si substrate for advanced semiconductor devices: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material... Agent: William Stoffel

20070020862 - Semiconductor device and method of fabricating the same: In an embodiment, a semiconductor device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate of the field region to define the active region, and has a protrusion higher than a... Agent: Marger Johnson & Mccollom, P.C.

20070020863 - Ldmos transistor: A semiconductor device comprises a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor comprising a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of... Agent: Baker Botts, L.L.P.

20070020864 - Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor: The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers... Agent: William Stoffel

20070020867 - Buried stress isolation for high-performance cmos technology: A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070020866 - Cmos transistor with high drive current and low sheet resistance: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim gate spacer along a side of the gate electrode, and a source/drain region substantially aligned with an edge of... Agent: Slater & Matsil, L.L.P.

20070020865 - Multi-work function gates for cmos circuit and method of manufacture: A method of manufacturing a device and the device. The device includes doping a low voltage threshold area and a high voltage threshold area. The method further includes forming gate structures over the low voltage threshold area and the high voltage threshold area and protecting the gate structure over the... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20070020868 - Semiconductor processing method and field effect transistor: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with... Agent: Wells St. John P.s.

20070020869 - Method for manufacturing capacitor for semiconductor device: Disclosed is a method for manufacturing a capacitor in a semiconductor device. A method consistent with the present invention includes forming a lower electrode on a semiconductor substrate; forming a first interlevel dielectric layer on an entire surface of the semiconductor substrate, covering the lower electrode; selectively removing the first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070020870 - Semiconductor capacitor structure and method to form same: A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semiconductor capacitor structure is fabricated by forming a base of metal silicide material along the sidewalls... Agent: David J. Paul Micron Technology, Inc.

20070020871 - Three dimensional ic device and alignment methods of ic device substrates: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070020873 - Method of manufacturing composite wafer structure: The invention provides a method of manufacturing a composite wafer structure. In particular, the method, according to the invention, is based on the fracture mechanics theory to actively control fracture induced during the manufacture of the composite wafer structure and to further protect from undesired edge damage. Thereby, the method,... Agent: Birch Stewart Kolasch & Birch

20070020872 - Process and apparatus for producing single crystal: Disclosed are a production apparatus and a production process in which a thick and high-quality single crystal film can be formed on both sides of a colored substrate. Both single crystal growth surfaces of a colored substrate which has been fixed through a substrate holder within a reactor are substantially... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070020874 - Method for controlling dislocation positions in silicon germanium buffer layers: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes depositing a strained silicon germanium layer on the substrate and irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent. The dislocation inducing agent may include ions, electrons,... Agent: VistaIPLaw Group LLP

20070020876 - Integrated circuitry, dynamic random access memory cells, electronic systems, and semiconductor processing methods: The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having... Agent: Wells St. John P.s.

20070020878 - Method for fabricating a metal-insulator-metal capacitor: A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and the silicon substrate to form a trench... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070020880 - Method of fabricating a semiconductor device and a method of generating a mask pattern: At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film... Agent: Mcdermott Will & Emery LLP

20070020879 - Method of forming an isolation layer and method of manufacturing a field effect transistor using the same: In a method of forming a device isolation layer, a trench is formed in a substrate and a preliminary fin is formed on the substrate using a hard mask pattern on a surface of the substrate as an etching mask. A first thin layer is formed on the bottom and... Agent: Harness, Dickey & Pierce, P.L.C

20070020881 - Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.... Agent: Wells St. John P.s.

20070020875 - Seamless trench fill method utilizing sub-atmospheric pressure chemical vapor deposition technique: A seamless trench fill method utilizing ozone-assisted sub-atmospheric pressure chemical vapor deposition (SACVD) technique is provided. After the deposition of a SACVD silicon oxide film, the substrate is subjected to a steam anneal that is performed under H2O2 environment at a relatively lower temperature ranging between 500° C. and 800°... Agent: North America Intellectual Property Corporation

20070020877 - Shallow trench isolation structure and method of fabricating the same: A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP) oxide layer substantially filling the trench.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070020882 - Method of manufacturing transistor having recessed channel: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that... Agent: Marger Johnson & Mccollom, P.C.

20070020883 - Patterned structures fabricated by printing mask over lift-off pattern: A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e.g., by printing a wax pattern that... Agent: Bever, Hoffman & Harms, LLP

20070020884 - Semiconductor structures formed on substrates and methods of manufacturing the same: Processes used to transfer semiconductor structures from an initial substrate to a base substrate include bonding the initial substrate with a silicon dioxide layer to a doped silicon structure weakened sufficiently by hydrogen implantation for cleaving. After cleaving, a doped silicon layer remains, burying the silicon dioxide layer between the... Agent: Townsend And Townsend And Crew, LLP

20070020885 - Tube formed of bonded silicon staves: Tubular silicon members advantageously formed by extrusion from a silicon melt or by fixing together silicon staves in a barrel shape. A silicon-based wafer support tower is particularly useful for batch-mode thermal chemical vapor deposition and other high-temperature processes, especially reflow of silicate glass at above 1200° C. The surfaces... Agent: Law Offices Of Charles Guenzer

20070020886 - Method for reducing the trap density in a semiconductor wafer: The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species... Agent: Winston & Strawn LLP Patent Department

20070020887 - Processing method and grinding apparatus of wafer: To facilitate handling of a wafer in processing or carrying after the wafer being reduced in thickness by grinding, the whole back of a wafer having a surface on which a device region having a plurality of devices formed therein and a peripheral surplus region enclosing the device region are... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070020888 - Semiconductor device and method of manufacturing the same: A semiconductor device having performance comparable with a MOSFET is provided. An active layer of the semiconductor device is formed by a crystalline silicon film crystallized by using a metal element for promoting crystallization, and further by carrying out a heat treatment in an atmosphere containing a halogen element to... Agent: Fish & Richardson P.C.

20070020889 - Method for manufacturing semiconductor device: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a device isolation film having a step difference occurring during a process of forming a device isolation film in a scribe lane region serves as a first alignment key, and a second alignment key formed... Agent: Heller Ehrman White & Mcauliffe LLP

20070020890 - Method and apparatus for semiconductor processing: A method and apparatus for manufacturing semiconductors, comprising at least two transfer chambers with exterior walls, at least one holding chamber attached to the transfer chamber, at least one load lock chamber attached to the walls of the transfer chambers, and at least five process chambers attached to the walls... Agent: Patterson & Sheridan, LLP

20070020891 - Gesn alloys and ordered phases with direct tunable bandgaps grown directly on silicon: A method for depositing an epitaxial Ge—Sn layer on a substrate in a CVD reaction chamber includes introducing into the chamber a gaseous precursor comprising SnD4 under conditions whereby the epitaxial Ge—Sn layer is formed on the substrate. the gaseous precursor comprises SnD4 and high purity H2 of about 15-20%... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070020893 - Low defect epitaxial semiconductor substrate having gettering function, image sensor using the same, and fabrication method thereof: Low defect epitaxial semiconductor substrates having a gettering function and methods of fabricating such substrates are described. A substrate in accordance with this invention includes a semiconductor substrate, a non-carrier characteristic dopant layer formed in the semiconductor substrate, a carrier characteristic dopant layer including the non-carrier characteristic dopant layer therein,... Agent: Mills & Onello LLP

20070020892 - Method of fabricating semiconductor device using selective epitaxial growth: A method of fabricating a semiconductor device using selective epitaxial growth (SEG) is disclosed. The method comprises; forming a seed window exposing a portion of a substrate through an interlayer insulating layer, growing a single crystal silicon SEG layer in the seed window using the exposed portion of the substrate... Agent: Volentine Francos, & Whitt PLLC

20070020894 - Method for preparing atomistically straight boundary junctions in high temperature superconducting oxides: A method for preparing film oxides deposited on a substrate with a resulting grain boundary junction that is atomistically straight. A bicrystal substrate having a straight grain boundary is prepared as a template. The Miller indices h1, k1, h2, k2 of the two grains of the substrate are chosen such... Agent: Baker & Botts L.L.P.

20070020895 - Method for production of a very thin layer with thinning by means of induced self-support: The invention relates to a process for obtaining a thin layer made of a first material on a substrate made of a second material called the final substrate, including the following steps: bonding a thick layer of a first material on one of its main faces on the final substrate... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070020896 - Semiconductor device and method for fabricating the same: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than... Agent: Mcdermott Will & Emery LLP

20070020897 - Manufacturing method of semiconductor device: When CW laser is irradiated on a semiconductor film while being relatively scanned in a fabrication process of a semiconductor device, many crystal grains extending in a scanning direction are formed. The semiconductor film irradiated in this way has characteristics substantially approximate to those of a single crystal in the... Agent: Eric Robinson

20070020898 - System and method for semiconductor processing: Systems and methods are disclosed to perform semiconductor processing with a process chamber; a flash lamp adapted to be repetitively triggered; and a controller coupled to the control input of the flash lamp to trigger the flash lamp. The system can deploy a solid state plasma source in parallel with... Agent: Fliesler Meyer, LLP

20070020899 - Forming method for film pattern, device, electro-optical apparatus, electronic apparatus, and manufacturing method for active matrix substrate: A forming method for a film pattern, includes: forming a first bank layer on a substrate; forming a second bank layer on the first bank layer; patterning the first bank layer and the second bank layer thereby forming a bank having a pattern formation region including a first pattern formation... Agent: Harness, Dickey & Pierce, P.L.C

20070020900 - Highly doped gate electrode made by rapidly melting and resolidifying the gate electrode: The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode... Agent: Texas Instruments Incorporated

20070020901 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0≦x<0.25), subjecting the first layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070020902 - Transistor for semiconductor device and method of forming the same: Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a novel transistor structure combining a plane channel transistor and a fin-type channel transistor formed on the semiconductor substrate is provided to secure a sufficient channel width as compared... Agent: Heller Ehrman White & Mcauliffe LLP

20070020903 - Hybrid pvd-cvd system: A method for making a film stack containing one or more silicon-containing layers and one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes one or more transfer chambers coupled to one or more load... Agent: Patterson & Sheridan, LLP

20070020905 - Low resistance contact in a semiconductor device: In a method for manufacturing a contact electrically contacting an electrically conductive silicon structure, a substrate with a surface is provided, the substrate having the silicon structure at the surface. Silicon oxide is grown selectively on at least part of the silicon structure. A layer is produced over the surface... Agent: Morrison & Foerster LLP

20070020906 - Method for forming high reliability bump structure: Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070020907 - Method of forming a connecting conductor and wirings of a semiconductor chip: A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the resist... Agent: Dickstein, Shapiro, Morin & Oshinsky, LLP

20070020904 - Selectively filling microelectronic features: Some embodiments of the present invention include filling features using selective fill techniques.... Agent: Blakely Sokoloff Taylor & Zafman

20070020909 - Forming of conductive bumps for an integrated circuit: A method for forming conductive bumps on conductive pads formed on an electronic circuit wafer, comprising the steps of: including forming a resist mask with holes above the pads; depositing balls in the holes; performing a thermal processing to melt the balls; and eliminating the mask.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070020908 - Multilayer structure having a warpage-compensating layer: A multilayer structure is provided that includes a semiconductor member having opposing first and second major surfaces, a warpage-compensating layer deposited on the first major surface, and a substrate bonded to the second major surface. The warpage-compensating layer has a stiffness and a coefficient of thermal expansion keyed to the... Agent: Tessera Lerner David Et Al.

20070020910 - Photoresist stripper composition and methods for forming wire structures and for fabricating thin film transistor substrate using composition: A photoresist stripper composition, a method for forming wire structures thereby, and a method of fabricating a thin film transistor substrate using the composition. The photoresist stripper composition includes about 50 WT % to about 70 WT % of butyldiglycol, about 20 to about 40 WT % of an alkylpyrrolidone,... Agent: Macpherson Kwok Chen & Heid LLP

20070020911 - Self alignment features for an electronic assembly: Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020912 - Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an... Agent: Sughrue Mion, PLLC

20070020913 - Method of forming solder bump with reduced surface defects: A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a... Agent: Harness, Dickey & Pierce, P.L.C

20070020914 - Circuit substrate and method of manufacturing the same: In a method of manufacturing a circuit substrate of the present invention, a first through hole is formed in a semiconductor substrate and a first insulating layer is formed on the entire surface of the semiconductor substrate, and then first wiring layers connected to each other via an outer through... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070020916 - Methods for forming flexible column die interconnects and resulting structures: A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in the form of a contact pad to which they... Agent: Trask Britt, P.C./ Micron Technology

20070020917 - Methods for forming macroporous monolithic methylsilsesquioxanes: The present invention relates to a two-step method of preparing methylsilsequixane (MSQ) materials suitable for chromatographic applications comprising treating a MSQ precursor with a suitable acid followed by treatment with a suitable base under conditions to form a MSQ monolith suitable for chromatographic applications.... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20070020915 - Mmic having back-side multi-layer signal routing: A method includes providing a single crystal wafer having MMIC chips. Each chip has an active device in a first surface portion of a semiconductor substrate provided by the wafer and an electrical interconnect having a first portion disposed on a second surface of the semiconductor substrate. The semiconductor substrate... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20070020918 - Substrate processing method and substrate processing apparatus: The present invention provides a substrate processing method that can perform improved flattening and processing upon the formation of interconnects. The a substrate processing method includes a step of eliminating a level difference in a surface of a interconnect material to flatten a surface, a step of removing the interconnect... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070020919 - Preamorphization to minimize void formation: Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the... Agent: Amin, Turocy & Calvin, LLP

20070020920 - Method for fabricating low leakage interconnect layers in integrated circuits: A method for fabricating a low leakage integrated circuit structure. An antireflective layer is disposed without intervening layers directly onto the top of an interconnect conductor, and a dielectric layer is disposed over the antireflective layer. The interconnect conductor is aluminum; the antireflective layer is titanium nitride, and the antireflective... Agent: Avago Technologies, Ltd. C/o Klaas, Law, O'meara & Malkin, P.C.

20070020922 - Method of depositing a metal seed layer on semiconductor substrates: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material... Agent: Kenyon & Kenyon LLP

20070020921 - Prevention of trench photoresist scum: Methods of preventing photoresist scum formation for etch processes for patterning material layers of semiconductor device material layers are disclosed. A treatment of N2 and O2 is used to prevent the formation of photoresist scum. The treatment may be performed in-situ, and may be performed during the etch process, after... Agent: Slater & Matsil, L.L.P.

20070020923 - Ald formed titanium nitride films: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-containing precursor chemical such as TDEAT,... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020924 - Tungsten nitride atomic layer deposition processes: In one embodiment, a method for forming a tungsten barrier material on a substrate is provided which includes depositing a tungsten layer on a substrate during a vapor deposition process and exposing the substrate sequentially to a tungsten precursor and a nitrogen precursor to form a tungsten nitride layer on... Agent: Patterson & Sheridan, LLP

20070020925 - Method of forming a nickel platinum silicide: A substrate having at least one silicon device is provided. A nickel platinum alloy layer is formed on the substrate. A rapid thermal process is performed to react the nickel platinum alloy layer with the silicon device to produce a nickel platinum silicide. A passivation layer is formed on the... Agent: North America Intellectual Property Corporation

20070020926 - Electrical connections in substrates: A method of making an electrical connection between a first (top) and a second (bottom) surface of a conducting or semi-conducting substrate includes creating a trench in the first surface, and establishing an insulating enclosure entirely separating a portion of the substrate, defined by the trench. Also described is a... Agent: Young & Thompson

20070020927 - Manufacturing method for electronic substrate, manufacturing method for electro-optical device, and manufacturing method for electronic device: A manufacturing method for an electronic substrate, includes: preparing a substrate and a mask having a predetermined region; forming a wiring pattern on the substrate; forming an aperture portion in the predetermined region of the mask; affixing the mask on the substrate; and removing at least a part of the... Agent: Harness, Dickey & Pierce, P.L.C

20070020928 - Multi-layer interconnect with isolation layer: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation... Agent: Knobbe Martens Olson & Bear LLP

20070020929 - Method for reducing dendrite formation in nickel silicon salicide processes: A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of... Agent: Cantor Colburn LLP - IBM Fishkill

20070020930 - Semiconductor device fabricated by a method of reducing the contact resistance of the connection regions: A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer... Agent: Knobbe Martens Olson & Bear LLP

20070020931 - Manufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy and semiconductor device of this kind: (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070020932 - Manufacturing method of wiring board and semiconductor device: A manufacturing method of a wiring board and a semiconductor device at low cost and by a simple process, without performing complicated steps many times is proposed. Furthermore, a manufacturing method of a wiring board at low cost and with fewer adverse effects on the environment, and a manufacturing method... Agent: Eric Robinson

20070020937 - Etch chamber with dual frequency biasing sources and a single frequency plasma generating source: A method and apparatus for selectively controlling a plasma in a processing chamber during wafer processing. The method includes providing process gasses into the chamber over a wafer to be processed, and providing high frequency RF power to a plasma generating element and igniting the process gases into the plasma.... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20070020934 - Hard mask structure for patterning of materials: Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a... Agent: Ryan, Mason & Lewis, LLP

20070020933 - Method of cleaning treatment and method for manufacturing semiconductor device: In a crystal growth reactor, a source material having an etching action and a crystal growth source material are simultaneously supplied to a semiconductor wafer surface, so that residual impurities can be eliminated in an efficient manner by balancing etching rate and crystal growth rate.... Agent: Young & Thompson

20070020936 - Methods of etching features into substrates: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the... Agent: Wells St. John P.s.

20070020935 - Process for enhancing solubility and reaction rates in supercritical fluids: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes,... Agent: Dinsmore & Shohl LLP One Dayton Centre

20070020938 - Semiconductor probe with resistive tip and method of fabricating the same, and information recording apparatus, information reproducing apparatus, and information measuring apparatus having the semiconductor probe: Provided are a semiconductor probe having a resistive tip, a method of fabricating the semiconductor probe, and a method of recording and reproducing information using the semiconductor probe. The semiconductor probe includes a tip and a cantilever. The tip is doped with first impurities. The cantilever has an end portion... Agent: Sughrue Mion, PLLC

20070020939 - Controlled geometry hardmask including subresolution elements: Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high... Agent: Trask Britt, P.C./ Micron Technology

20070020940 - Method of forming fluorinated carbon film: The present invention is made to solve a problem to improve adhesion between a fluorine-containing carbon film and a foundation film. In order to achieve this object, according to the present invention, a fluorine-containing carbon film forming method of forming a fluorine-containing carbon film on a to-be-processed substrate includes: a... Agent: Crowell & Moring LLP Intellectual Property Group

20070020941 - Plasma etching apparatus and particle removal method: The invention provides a particle removal method for a plasma processing apparatus, the method easily removing particles in the chamber up to its lower part. In a plasma etching apparatus including an upper antenna, a lower electrode, pressure gauges P1 and P2, gas introducing means, evacuating means, and phase controlling... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070020942 - Method and system for providing a continuous motion sequential lateral solidification for reducing or eliminating artifacts, and a mask for facilitating such artifact reduction/elimination: An arrangement, process and mask for implementing single-scan continuous motion sequential lateral solidification of a thin film provided on a sample such that artifacts formed at the edges of the beamlets irradiating the thin film are significantly reduced. According to this invention, the edge areas of the previously irradiated and... Agent: Baker & Botts L.L.P.

20070020943 - Apparatus and method for removing a photoresist structure from a substrate: In an apparatus and method for removing a photoresist structure from a substrate, a chamber for receiving the substrate includes a showerhead for uniformly distributing a mixture of water vapor and ozone gas onto the substrate. The showerhead includes a first space having walls and configured to receive the water... Agent: Harness, Dickey & Pierce, P.L.C

20070020944 - Selective etch process of a sacrificial light absorbing material (slam) over a dielectric material: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070020946 - Method for modifying surface of substrate and method for manufacturing semiconductor device: An insulating film is formed on a substrate selected from a group containing a BT resin substrate and an epoxy resin substrate. Copper wirings and copper posts including wirings are formed on the insulating film. Plasma processing is effected on exposed surfaces of the insulating film, copper wirings and copper... Agent: Rabin & Berdo, PC

20070020947 - Method of reducing roughness of a thick insulating layer: A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate; treating the first substrate to form a zone of weakness beneath the insulator layer;... Agent: Winston & Strawn LLP Patent Department

20070020945 - Semiconductor processing system and method: Systems and methods are disclosed to perform semiconductor processing with a process chamber; a flash lamp adapted to be repetitively triggered; and a controller coupled to the control input of the flash lamp to trigger the flash lamp. The system can deploy a solid state plasma source in parallel with... Agent: Fliesler Meyer, LLP

20070020948 - Self-packaged optical interference display device having anti-stiction bumps, integral micro-lens, and reflection-absorbing layers: An electronic device of an embodiment of the invention is disclosed that at least partially displays a pixel of a display image. The device includes a first reflector and a second reflector defining an optical cavity therebetween that is selective of a visible wavelength at an intensity. The device includes... Agent: Hewlett-packard Company Intellectual Property Administration

20070020949 - Method for manufacturing simox wafer and simox wafer: One embodiment of this method for manufacturing a SIMOX wafer includes: while heating a silicon wafer, implanting oxygen ions so as to form a high oxygen concentration layer; implanting oxygen ions into the silicon wafer obtained by the forming of the high oxygen concentration layer so as to form an... Agent: Kolisch Hartwell, P.C.

20070020950 -