Semiconductor device manufacturing: process inventions 01/07

20070020772 - Gradient structures interfacing microfluidics and nanofluidics, methods for fabrication and uses thereof: The present invention relates to a device for interfacing nanofluidic and microfluidic components suitable for use in performing high throughput macromolecular analysis. Diffraction gradient lithography (DGL) is used to form a gradient interface between a microfluidic area and a nanofluidic area. The gradient interface area reduces the local entropic barrier... Agent: Woodcock Washburn LLP

20070020771 - Nanoparticles and method of making thereof: A method of making nanoparticles includes contacting a powder having particles of a first size and an etching material, and heating the powder and the etching material to reduce particles of the first size to nanoparticles having a second size smaller than the first size.... Agent: Foley And Lardner LLP Suite 500

20070020773 - Fabrication of nano-object array: This disclosure relates to a system and method for creating nano-object arrays. A nano-object array can be created by exposing troughs in a corrugated surface to nano-objects and depositing the nano-objects within or orienting the nano-objects with the troughs.... Agent: Hewlett Packard Company

20070020774 - Methods of utilizing magnetoresistive memory constructions: The invention includes a method of forming a magnetoresistive memory device having a memory bit stack. The stack includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization... Agent: Wells St. John P.s.

20070020775 - System and method for reducing shorting in memory cells: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and,... Agent: Knobbe Martens Olson & Bear LLP

20070020776 - Method and apparatus for wall film monitoring: A wall film monitoring system includes first and second microwave mirrors in a plasma processing chamber each having a concave surface. The concave surface of the second mirror is oriented opposite the concave surface of the first mirror. A power source is coupled to the first mirror and configured to... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070020777 - Controlling system for gate formation of semiconductor devices: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may... Agent: Slater & Matsil, L.L.P.

20070020778 - Method and monitor structure for detecting and locating ic defects: A 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process, the method including forming a first metallization layer; carrying out a first wafer acceptance testing (WAT) process to test the electrical continuity... Agent: Tung & Associates

20070020783 - Method of feed forward control of scanned rapid thermal processing: A thermal processing system and method including scanning a line beam of intense radiation in a direction transverse to the line direction for thermally processing a wafer with a localized effectively pulsed beam of radiant energy. The thickness of the wafer is two-dimensionally mapped and the map is used to... Agent: Law Offices Of Charles Guenzer Attn: Applied Materials, Inc.

20070020782 - Method of monitoring a semiconductor manufacturing trend: A method of monitoring trends in semiconductor processes is provided. Lot values are assigned to each of a set of wafer lots prior to performing semiconductor processes. After at least some of the semiconductor processes, at least some of the wafer lots are tested to generate a set of test... Agent: Barry Dove Patent Services, Inc.

20070020780 - Method of processing semiconductor substrate responsive to a state of chamber contamination: In one embodiment, a method of processing a semiconductor substrate includes measuring a state of a processing chamber contamination before processing each semiconductor substrate. A process condition is then changed responsive to the state of chamber contamination to compensate for an influence of the state of chamber contamination on the... Agent: Marger Johnson & Mccollom, P.C.

20070020779 - Quantum dot conjugates in a sub-micrometer fluidic channel: A nanofluidic channel fabricated in fused silica with an approximately 500 nm square cross section was used to isolate, detect and identify individual quantum dot conjugates. The channel enables the rapid detection of every fluorescent entity in solution. A laser of selected wavelength was used to excite multiple species of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020781 - Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display... Agent: Drinker Biddle & Reath (dc)

20070020784 - Method and system for determining optical properties of semiconductor wafers: A method and system are disclosed for determining at least one optical characteristic of a substrate, such as a semiconductor wafer. Once the optical characteristic is determined, at least one parameter in a processing chamber may be controlled for improving the process. For example, in one embodiment, the reflectivity of... Agent: Dority & Manning, P.A.

20070020785 - Systems and methods for alignment of laser beam(s) for semiconductor link processing: A method makes a discrete adjustment to static alignment of a laser beam in a machine for selectively irradiating conductive links on or within a semiconductor substrate using the laser beam. The laser beam propagates along a beam path having an axis extending from a laser to a laser beam... Agent: Stoel Rives LLP

20070020786 - Device comprising a field of tips used in biotechnology applications: A method for manufacturing a device including a field of micrometric tips, including forming a polycrystalline layer on a support; performing an anisotropic plasma etching of all or part of the polycrystalline layer by using a gas mixture including chlorine and helium, whereby tips are formed at the surface of... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070020787 - Electrifying method and manufacturing method of electron-source substrate: m

20070020788 - Fabrication method of high-brightness light emitting diode having reflective layer: A method for fabricating a high brightness LED structure is disclosed herein, which comprises at least the following steps. First, a first layered structure is provided by sequentially forming a light generating structure, a non-alloy ohmic contact layer, and a first metallic layer from bottom to top on a side... Agent: Lin & Associates Intellectual Property

20070020791 - Image sensor with optical guard ring and fabrication method thereof: An image sensor device and fabrication method thereof wherein a substrate having at least one shallow trench isolation structure therein is provided. At least one photosensor and at least one light emitting element, e.g., such as MOS or LED, are formed in the substrate. The photosensor and the light emitting... Agent: Birch Stewart Kolasch & Birch

20070020790 - Light emitting device methods: Light-emitting device methods are disclosed.... Agent: Wolf Greenfield & Sacks, PC

20070020789 - Light emitting devices and method for fabricating the same: Light emitting devices and a method for fabricating the same have an advantage in that an etching film formed between a plurality of light emitting structures is removed to separate respective lateral surfaces of the light emitting structures from one another, and a substrate is removed to separate lower portions... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070020792 - Optical sheet, backlight unit, electro-optic device, electronic device, method for manufacturing optical sheet, and method for cutting optical sheet: A method for manufacturing an optical sheet includes: a) discharging a liquid lens material onto a sheet having a light-transmitting property, the liquid lens material being to be a material of micro lenses; b) discharging a liquid material onto the sheet, the liquid material being to be a material of... Agent: Harness, Dickey & Pierce, P.L.C

20070020793 - Three-dimensional shaped solid dosimeter and method of use: The invention relates to a solid plastic three-dimensional dosimeter which is useful in treatment planning, optimization of the radiation field, dose verification, dose validation, commissioning, and quality assurance of complex radiotherapeutic procedures. Dosimeters of the invention can be formed in any clinically relevant shape, and contain a reporter leuco dye... Agent: Mathews, Shepherd, Mckay, & Bruneau, P.A.

20070020794 - Method of strengthening a microscale chamber formed over a sacrificial layer: A method for forming an improved chamber for a micro-electromechanical device includes depositing a sacrificial layer on a substrate; depositing a masking layer on a surface of the sacrificial layer; removing at least one predetermined portion of the masking layer down to the sacrificial layer to form an etch pattern;... Agent: Mark G. Bocchetti Patent Legal Staff

20070020796 - Image sensor having multi-gate insulating layers and fabrication method: An image sensor and related method of fabrication are disclosed. The image sensor includes a first gate insulating layer of first material layer type disposed in a sensor region of a semiconductor substrate, a second gate insulating layer of second material layer type disposed in an analog region of the... Agent: Volentine Francos, & Whitt PLLC

20070020795 - Solid-state imaging device and its manufacturing method: In a method for manufacturing a solid-state imaging device of the present invention, a pad insulting film 2 made of an oxide film and an anti-oxidizing film 3 made of a nitride film are deposited on a n-type semiconductor substrate 1. Then, an opening 4 is formed to expose an... Agent: Mcdermott Will & Emery LLP

20070020797 - Self-aligned process for manufacturing phase change memory cells: A process for manufacturing phase change memory cells includes the step of forming a heater element in a semiconductor wafer and a storage region of a phase change material on and in contact with the heater element. In order to form the heater element and the phase change storage region... Agent: Seed Intellectual Property Law Group PLLC

20070020798 - Methods to minimize contact resistance: A method is disclosed for making a metal electrode which minimizes the contact resistance between it and an organic semiconductor. Acid-stabilized metal nanoparticles are deposited upon a substrate and annealed. This creates a metal electrode and releases acid. Upon deposition of semiconductor and subsequent annealing, the acid diffuses from the... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070020799 - Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation... Agent: Marger Johnson & Mccollom, P.C.

20070020805 - Etch stop layer for silicon (si) via etch in three-dimensional (3-d) wafer-to-wafer vertical stack: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the... Agent: Intel/blakely

20070020800 - Ic chip mounting method: An IC chip mounting method which mounts two or more IC chips on a base, includes: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by dividing the wafer into... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070020801 - Ic chip mounting method: The present invention provides an IC chip mounting method for mounting two or more IC chips on a base, including: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070020806 - Method and structure for forming strained si for cmos devices: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only... Agent: Greenblum & Bernstein, P.L.C

20070020804 - Method of manufacturing electronic circuit device: The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an electrode pad 16 integrally formed with the interconnect 14; preparing an electronic circuit chip 20 including a solder electrode 22; and melting... Agent: Mcginn Intellectual Property Law Group, PLLC

20070020802 - Packaging method for segregating die paddles of a leadfram: The present invention relates to a packaging method for segregating die paddles of a leadframe. The method comprising: (a) providing a leadframe having a top surface, a bottom surface and a die paddle region, the die paddle region having a plurality of die paddles, wherein at least two of the... Agent: Volentine Francos, & Whitt PLLC

20070020807 - Protective structures and methods of fabricating protective structures over wafers: A method of fabricating a protective structure and a packaged structure are described.... Agent: Avago Technologies, Ltd.

20070020803 - Semiconductor device and manufacturing method of the same: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070020808 - Low profile, chip-scale package and method of fabrication: Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate with first and second surfaces, at least one opening, and a certain thickness. On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads; at least one of the contact pads... Agent: Texas Instruments Incorporated

20070020809 - Semiconductor device and method of producing high contrast identification mark: A semiconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts with the color of the semiconductor die. The coating layer is patterned to... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070020811 - Method and apparatus for attaching microelectronic substrates and support members: A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first surface, a second surface facing opposite the first surface, and a projection extending away from the first surface. A quantity of adhesive material can be... Agent: Perkins Coie LLP Patent-sea

20070020810 - Thermoplastic/thermoset composition material and method of attaching a wafer to a substrate: A process for mounting a wafer on a substrate includes applying a pre-applied die attach on a backside of the wafer with a composition having a thermoplastic portion and a thermoset portion. The composition has a predetermined cure temperature. The process further includes heating the wafer to a temperature sufficient... Agent: Lowrie, Lando & Anastasi

20070020812 - Circuit board structure integrated with semiconductor chip and method of fabricating the same: A circuit board structure integrated with semiconductor chip and a method of fabricating the same are proposed. A supporting plate formed with at least one cavity is provided and a semiconductor chip having a plurality of conductive contacts is embedded in the cavity. An anisotropic conductive film (ACF) layer and... Agent: Clark & Brody

20070020813 - Device and method for package warp compensation in an integrated heat spreader: A device and method for designing and manufacturing an integrated heat spreader so that the integrated heat spreader will have a flat surface on which to mount a heat sink after being assembled into a package and exposed to the heat of a die. This device and method for designing... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020814 - Methods of underfilling and encapsulating semiconductor assemblies with materials having selected properties using stereolithography: Methods of forming semiconductor packages include immersing a semiconductor device assembly in a liquid photopolymerizable resin including a plurality of discrete particles dispersed therethrough, and selectively at least partially curing portions of the resin adjacent at least one semiconductor die of the semiconductor device assembly. In some embodiments, the semiconductor... Agent: Trask Britt

20070020815 - Process for exposing solder bumps on an underfill coated semiconductor: A process for applying a solvent-free underfill onto a bumped semiconductor comprises: providing an underfill in a compressible state on a semiconductor, contacting the underfill with a compliant surface and applying sufficient pressure to expose the bumps, optionally hardening the underfill to a solid state, and removing the compliant surface.... Agent: Jane E. Gennaro National Starch An Chemical

20070020816 - Manufacturing process for chip package without core: A manufacturing process for chip package without core is disclosed. First of all, a conductive layer with a first surface and a second surface is provided. A first film is formed onto the first surface, and the conductive layer is patterned to form a patterned circuit layer. A solder resistance... Agent: J.c. Patents, Inc.

20070020817 - Wafer level incapsulation chip and encapsulation chip manufacturing method: A wafer level encapsulation chip and an encapsulation chip manufacturing method. The encapsulation chip includes a device substrate, a circuit module mounted on the device substrate, a bonding layer deposited on a predetermined area of the device substrate, a protection cap forming a cavity over the circuit module and bonded... Agent: Sughrue Mion, PLLC

20070020818 - Esd protection device in high voltage and manufacturing method for the same: Electrostatic discharge (ESD) protection device in high voltage and the relevant manufacturing method is disclosed. The mentioned ESD protection device is disposed to bridge a ground and an input connected with an inner circuit to be protected. In which, the ESD protection device for high voltage comprises at least one... Agent: Birch Stewart Kolasch & Birch

20070020819 - Vertical transistor structures having vertical-surrounding-gates with self-aligned features: The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in... Agent: David J. Paul Microntechnology, Inc.

20070020820 - Process for forming an electronic device including discontinuous storage elements: A process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate and forming a trench within the substrate. The process can also include forming a second set of discontinuous storage elements within the trench. The process can... Agent: Larson Newman Abel Polansky & White, LLP

20070020821 - Method for forming a thin-film transistor: A method for forming a thin-film transistor includes forming a source electrode and a drain electrode on an element-side substrate, forming a semiconductor layer in contact with the source electrode and the drain electrode, forming a gate insulating layer overlaid on the semiconductor layer, and forming a gate electrode overlaid... Agent: Harness, Dickey & Pierce, P.L.C

20070020822 - Method for manufacturing bottom substrate of liquid crystal display device: A method for manufacturing liquid crystal display substrates comprises the steps of: (a) providing a substrate having a transparent electrode layer and a metal layer; (b) forming a patterned photoresist layer through half-tone or diffraction; (c) defining signal line area and thin film diode area, or pixel area and conductive... Agent: Bacon & Thomas, PLLC

20070020823 - Method for manufacturing thin film device and semiconductor device: The present invention relates to a method for manufacturing a thin film device. The thin film device is manufactured by bonding a second substrate (106) to a thin film device layer (103) provided on a protective layer (102) formed on a first substrate (101) through a first adhesive layer (105),... Agent: Sonnenschein Nath & Rosenthal LLP

20070020826 - Method for manufacturing semiconductor device: It is an object of the invention to provide a technique forming a crystalline semiconductor film whose orientation is uniform by control of crystal orientation and obtaining a crystalline semiconductor film in which concentration of an impurity is reduced. A configuration of the invention is that a first semiconductor region... Agent: Nixon Peabody, LLP

20070020825 - Method of manufacturing thin film transistor substrate: A method of manufacturing a thin film transistor (TFT) substrate to minimize a rugged surface of an organic layer overlapping with a storage electrode is provided. The method includes forming a passivation layer on a substrate having a storage electrode and an organic layer covering the passivation layer, forming a... Agent: F. Chau & Associates, LLC

20070020824 - Multi-layered complementary conductive line structure and manufacturing method thereof and manufacturing method of a thin film transistor display array: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is... Agent: Jianq Chyun Intellectual Property Office

20070020827 - Methods of forming semiconductor device: A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type... Agent: Mills & Onello LLP

20070020828 - Method for manufacturing semiconductor apparatus and the semiconductor apparatus: A method for manufacturing a semiconductor apparatus, comprises: forming a first semiconductor layer on a semiconductor substrate of a transistor formation region; etching and removing a part of the first semiconductor layer sandwiched by a source formation region and a drain formation region to form a groove section in which... Agent: Edwards & Angell, LLP

20070020829 - Semiconductor device and a method of manufacturing the same: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching... Agent: Miles & Stockbridge PC

20070020835 - Atomic layer deposition of ceo2/al2o3 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020830 - Improved cmos (complementary metal oxide semiconductor) technology: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material... Agent: Schmeiser, Olsen & Watts

20070020834 - Method for forming film pattern, and method for manufacturing device, electro-optical device, electronic apparatus and active matrix substrate: A method for forming a film pattern, comprises: disposing a first bank forming material to a substrate so as to form a first bank layer; disposing a second bank forming material on the first bank layer so as to form a second bank layer; and pattering the first bank layer... Agent: Harness, Dickey & Pierce, P.L.C

20070020833 - Method for making a semiconductor device including a channel with a non-semiconductor layer monolayer: A method for making a semiconductor device may include forming at least one metal oxide semiconductor field-effect transistor (MOSFET) on a semiconductor substrate. The MOSFET may include spaced-apart source and drain regions, a channel between the source and drain regions, and a gate overlying the channel defining an interface therewith.... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070020831 - Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming: A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes... Agent: Larson Newman Abel Polansky & White, LLP

20070020832 - Semiconductor devices and method of fabrication: A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer... Agent: Ingrassia, Fisher & Lorenz, P.C.

20070020836 - Method for manufacturing thin film transistor substrate: A method for manufacturing a TFT substrate includes forming a gate metal layer on an insulating substrate, forming a photo-sensitive layer pattern on the gate metal layer, forming a gate wiring by etching the gate metal layer using the photo-sensitive layer pattern, exposing the gate wiring by stripping the photo-sensitive... Agent: Cantor Colburn, LLP

20070020837 - High performance capacitors in planar back gates cmos: A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.... Agent: Greenblum & Bernstein, P.L.C

20070020838 - High performance capacitors in planar back gates cmos: Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer... Agent: Hoffman, Warnick & D'alessandro LLC

20070020839 - Methods to selectively protect nmos regions, pmos regions, and gate layers during epi process: A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner... Agent: Texas Instruments Incorporated

20070020840 - Programmable structure including nanocrystal storage elements in a trench: A storage cell includes a semiconductor substrate defining a trench, a bottom dielectric lining the trench, and a charge storage layer on the bottom dielectric. The charge storage layer includes a plurality of discontinuous storage elements (DSEs). A control gate and a top dielectric cover the DSEs. The storage cell... Agent: Larson Newman Abel Polansky & White, LLP

20070020841 - Method of manufacturing gate structure and method of manufacturing semiconductor device including the same: In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution.... Agent: Volentine Francos, & Whitt PLLC

20070020842 - Method of manufacturing mask rom: A method of manufacturing a ROM is disclosed. The method comprises steps of (a) providing a substrate and forming a plurality of gate structures on said substrate, (b) forming a first oxide layer on said substrate and said plurality of gate structures, (c) forming a mask layer on said first... Agent: Bacon & Thomas, PLLC

20070020843 - Method of producing a chip-type solid electrolytic capacitor: A chip-type solid electrolytic capacitor comprises capacitor elements. A cathode terminal comprising a plate-like conductor is interposed between cathode layers of the capacitor elements. The capacitor elements are bonded to each other by a bonding agent such as a solder or a conductive adhesive. The cathode terminal is provided with... Agent: Frishauf, Holtz, Goodman & Chick, PC

20070020844 - Method for fabricating bit line of memory device: A damascene process. A substrate covered by a dielectric layer and an overlying polysilicon masking layer with an opening exposing the underlying dielectric layer is provided. The exposed dielectric layer is etched to form a damascene opening therein and a portion of polysilicon masking layer remains on the dielectric layer.... Agent: Quintero Law Office

20070020846 - Flash memory device and method for fabricating the same: A flash memory device including an isolation layer for defining active regions in a semiconductor substrate. The active region is a region in which flash memory cells are to be formed. The device also includes a gate stack is formed to come across the active region and the isolation layer,... Agent: Mayer, Brown, Rowe & Maw LLP

20070020847 - Method for fabricating flash memory device: A method of fabricating a flash memory device. A DDD ion is implanted into a high voltage PMOS transistor and into source and drain junctions of a cell transistor in order to facilitate a pinch-off phenomenon in the gate to drain overlap region and also increase the number of hot... Agent: Marshall, Gerstein & Borun LLP

20070020848 - Method for fabricating semiconductor device: In a method for fabricating a semiconductor device in which a semiconductor memory element having an ONO film and a CMOS part are formed on a single semiconductor substrate, a CMOS gate-oxidation step is performed several times. Thereafter, a bit line diffusion layer and a bit line oxide film are... Agent: Mcdermott Will & Emery LLP

20070020845 - Method of fabricating programmable structure including discontinuous storage elements and spacer control gates in a trench: A method of fabricating a semiconductor storage cell that includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals.... Agent: Larson Newman Abel Polansky & White, LLP

20070020849 - Source side injection storage device with spacer gates and method therefor: A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates... Agent: Freescale Semiconductor, Inc. Law Department

20070020851 - Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench and a method of using the same: A programmable storage device includes a first diffusion region underlying a portion of a first trench defined in a semiconductor substrate and a second diffusion region occupying an upper portion of the substrate adjacent to the first trench. The device includes a charge storage stack lining sidewalls and a portion... Agent: Larson Newman Abel Polansky & White, LLP

20070020850 - Method for manufacturing semiconductor device and semiconductor device: A method for manufacturing a semiconductor device including the steps of: forming a hole having a predetermined depth in a semiconductor layer of a first conductivity type in correspondence with a drain region, the semiconductor layer being formed on a semiconductor substrate; forming a diffusion source layer containing impurities of... Agent: Rabin & Berdo, P.C.

20070020852 - Semiconductor memory device with a stacked gate including a floating gate and a control gate: A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070020854 - Be-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is... Agent: Ronald L. Yin Patent Department

20070020853 - Bidirectional split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining... Agent: George W. Hughes

20070020855 - Semiconductor device having vertical channels and method of manufacturing the same: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The... Agent: Marger Johnson & Mccollom, P.C.

20070020856 - Process for forming an electronic device including discontinuous storage elements: forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also... Agent: Larson Newman Abel Polansky & White, LLP

20070020857 - Process for forming an electronic device including discontinuous storage elements: A process for forming an electronic device can include forming a first trench within a substrate, wherein the trench includes a wall and a bottom and extends from a primary surface of the substrate. The process can also include forming discontinuous storage elements and forming a first gate electrode within... Agent: Larson Newman Abel Polansky & White, LLP

20070020858 - Layout structure of mos transistors and methods of disposing mos transistors on an active region: In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench... Agent: Harness, Dickey & Pierce, P.L.C

20070020859 - Method of making non-volatile field effect devices and arrays of same: Methods of making non-volatile field effect devices and arrays of same. Under one embodiment, a method of making a non-volatile field effect device includes providing a substrate with a field effect device formed therein. The field effect device includes a source, drain and gate with a field-modulatable channel between the... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070020860 - Method for making semiconductor device including a strained superlattice and overlying stress layer and related methods: A method for making a semiconductor device may include forming a superlattice layer including a plurality of stacked groups of layers, and forming a stress layer above the strained superlattice layer to induce a strain therein. Each group of layers of the superlattice layer may include a plurality of stacked... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070020861 - Method to engineer etch profiles in si substrate for advanced semiconductor devices: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material... Agent: William Stoffel

20070020862 - Semiconductor device and method of fabricating the same: In an embodiment, a semiconductor device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate of the field region to define the active region, and has a protrusion higher than a... Agent: Marger Johnson & Mccollom, P.C.

20070020863 - Ldmos transistor: A semiconductor device comprises a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor comprising a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of... Agent: Baker Botts, L.L.P.

20070020864 - Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor: The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers... Agent: William Stoffel

20070020867 - Buried stress isolation for high-performance cmos technology: A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070020866 - Cmos transistor with high drive current and low sheet resistance: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim gate spacer along a side of the gate electrode, and a source/drain region substantially aligned with an edge of... Agent: Slater & Matsil, L.L.P.

20070020865 - Multi-work function gates for cmos circuit and method of manufacture: A method of manufacturing a device and the device. The device includes doping a low voltage threshold area and a high voltage threshold area. The method further includes forming gate structures over the low voltage threshold area and the high voltage threshold area and protecting the gate structure over the... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20070020868 - Semiconductor processing method and field effect transistor: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with... Agent: Wells St. John P.s.

20070020869 - Method for manufacturing capacitor for semiconductor device: Disclosed is a method for manufacturing a capacitor in a semiconductor device. A method consistent with the present invention includes forming a lower electrode on a semiconductor substrate; forming a first interlevel dielectric layer on an entire surface of the semiconductor substrate, covering the lower electrode; selectively removing the first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070020870 - Semiconductor capacitor structure and method to form same: A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semiconductor capacitor structure is fabricated by forming a base of metal silicide material along the sidewalls... Agent: David J. Paul Micron Technology, Inc.

20070020871 - Three dimensional ic device and alignment methods of ic device substrates: Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070020873 - Method of manufacturing composite wafer structure: The invention provides a method of manufacturing a composite wafer structure. In particular, the method, according to the invention, is based on the fracture mechanics theory to actively control fracture induced during the manufacture of the composite wafer structure and to further protect from undesired edge damage. Thereby, the method,... Agent: Birch Stewart Kolasch & Birch

20070020872 - Process and apparatus for producing single crystal: Disclosed are a production apparatus and a production process in which a thick and high-quality single crystal film can be formed on both sides of a colored substrate. Both single crystal growth surfaces of a colored substrate which has been fixed through a substrate holder within a reactor are substantially... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070020874 - Method for controlling dislocation positions in silicon germanium buffer layers: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes depositing a strained silicon germanium layer on the substrate and irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent. The dislocation inducing agent may include ions, electrons,... Agent: VistaIPLaw Group LLP

20070020876 - Integrated circuitry, dynamic random access memory cells, electronic systems, and semiconductor processing methods: The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having... Agent: Wells St. John P.s.

20070020878 - Method for fabricating a metal-insulator-metal capacitor: A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and the silicon substrate to form a trench... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070020880 - Method of fabricating a semiconductor device and a method of generating a mask pattern: At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film... Agent: Mcdermott Will & Emery LLP

20070020879 - Method of forming an isolation layer and method of manufacturing a field effect transistor using the same: In a method of forming a device isolation layer, a trench is formed in a substrate and a preliminary fin is formed on the substrate using a hard mask pattern on a surface of the substrate as an etching mask. A first thin layer is formed on the bottom and... Agent: Harness, Dickey & Pierce, P.L.C

20070020881 - Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.... Agent: Wells St. John P.s.

20070020875 - Seamless trench fill method utilizing sub-atmospheric pressure chemical vapor deposition technique: A seamless trench fill method utilizing ozone-assisted sub-atmospheric pressure chemical vapor deposition (SACVD) technique is provided. After the deposition of a SACVD silicon oxide film, the substrate is subjected to a steam anneal that is performed under H2O2 environment at a relatively lower temperature ranging between 500° C. and 800°... Agent: North America Intellectual Property Corporation

20070020877 - Shallow trench isolation structure and method of fabricating the same: A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP) oxide layer substantially filling the trench.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070020882 - Method of manufacturing transistor having recessed channel: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that... Agent: Marger Johnson & Mccollom, P.C.

20070020883 - Patterned structures fabricated by printing mask over lift-off pattern: A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e.g., by printing a wax pattern that... Agent: Bever, Hoffman & Harms, LLP

20070020884 - Semiconductor structures formed on substrates and methods of manufacturing the same: Processes used to transfer semiconductor structures from an initial substrate to a base substrate include bonding the initial substrate with a silicon dioxide layer to a doped silicon structure weakened sufficiently by hydrogen implantation for cleaving. After cleaving, a doped silicon layer remains, burying the silicon dioxide layer between the... Agent: Townsend And Townsend And Crew, LLP

20070020885 - Tube formed of bonded silicon staves: Tubular silicon members advantageously formed by extrusion from a silicon melt or by fixing together silicon staves in a barrel shape. A silicon-based wafer support tower is particularly useful for batch-mode thermal chemical vapor deposition and other high-temperature processes, especially reflow of silicate glass at above 1200° C. The surfaces... Agent: Law Offices Of Charles Guenzer

20070020886 - Method for reducing the trap density in a semiconductor wafer: The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species... Agent: Winston & Strawn LLP Patent Department

20070020887 - Processing method and grinding apparatus of wafer: To facilitate handling of a wafer in processing or carrying after the wafer being reduced in thickness by grinding, the whole back of a wafer having a surface on which a device region having a plurality of devices formed therein and a peripheral surplus region enclosing the device region are... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070020888 - Semiconductor device and method of manufacturing the same: A semiconductor device having performance comparable with a MOSFET is provided. An active layer of the semiconductor device is formed by a crystalline silicon film crystallized by using a metal element for promoting crystallization, and further by carrying out a heat treatment in an atmosphere containing a halogen element to... Agent: Fish & Richardson P.C.

20070020889 - Method for manufacturing semiconductor device: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a device isolation film having a step difference occurring during a process of forming a device isolation film in a scribe lane region serves as a first alignment key, and a second alignment key formed... Agent: Heller Ehrman White & Mcauliffe LLP

20070020890 - Method and apparatus for semiconductor processing: A method and apparatus for manufacturing semiconductors, comprising at least two transfer chambers with exterior walls, at least one holding chamber attached to the transfer chamber, at least one load lock chamber attached to the walls of the transfer chambers, and at least five process chambers attached to the walls... Agent: Patterson & Sheridan, LLP

20070020891 - Gesn alloys and ordered phases with direct tunable bandgaps grown directly on silicon: A method for depositing an epitaxial Ge—Sn layer on a substrate in a CVD reaction chamber includes introducing into the chamber a gaseous precursor comprising SnD4 under conditions whereby the epitaxial Ge—Sn layer is formed on the substrate. the gaseous precursor comprises SnD4 and high purity H2 of about 15-20%... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070020893 - Low defect epitaxial semiconductor substrate having gettering function, image sensor using the same, and fabrication method thereof: Low defect epitaxial semiconductor substrates having a gettering function and methods of fabricating such substrates are described. A substrate in accordance with this invention includes a semiconductor substrate, a non-carrier characteristic dopant layer formed in the semiconductor substrate, a carrier characteristic dopant layer including the non-carrier characteristic dopant layer therein,... Agent: Mills & Onello LLP

20070020892 - Method of fabricating semiconductor device using selective epitaxial growth: A method of fabricating a semiconductor device using selective epitaxial growth (SEG) is disclosed. The method comprises; forming a seed window exposing a portion of a substrate through an interlayer insulating layer, growing a single crystal silicon SEG layer in the seed window using the exposed portion of the substrate... Agent: Volentine Francos, & Whitt PLLC

20070020894 - Method for preparing atomistically straight boundary junctions in high temperature superconducting oxides: A method for preparing film oxides deposited on a substrate with a resulting grain boundary junction that is atomistically straight. A bicrystal substrate having a straight grain boundary is prepared as a template. The Miller indices h1, k1, h2, k2 of the two grains of the substrate are chosen such... Agent: Baker & Botts L.L.P.

20070020895 - Method for production of a very thin layer with thinning by means of induced self-support: The invention relates to a process for obtaining a thin layer made of a first material on a substrate made of a second material called the final substrate, including the following steps: bonding a thick layer of a first material on one of its main faces on the final substrate... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070020896 - Semiconductor device and method for fabricating the same: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than... Agent: Mcdermott Will & Emery LLP

20070020897 - Manufacturing method of semiconductor device: When CW laser is irradiated on a semiconductor film while being relatively scanned in a fabrication process of a semiconductor device, many crystal grains extending in a scanning direction are formed. The semiconductor film irradiated in this way has characteristics substantially approximate to those of a single crystal in the... Agent: Eric Robinson

20070020898 - System and method for semiconductor processing: Systems and methods are disclosed to perform semiconductor processing with a process chamber; a flash lamp adapted to be repetitively triggered; and a controller coupled to the control input of the flash lamp to trigger the flash lamp. The system can deploy a solid state plasma source in parallel with... Agent: Fliesler Meyer, LLP

20070020899 - Forming method for film pattern, device, electro-optical apparatus, electronic apparatus, and manufacturing method for active matrix substrate: A forming method for a film pattern, includes: forming a first bank layer on a substrate; forming a second bank layer on the first bank layer; patterning the first bank layer and the second bank layer thereby forming a bank having a pattern formation region including a first pattern formation... Agent: Harness, Dickey & Pierce, P.L.C

20070020900 - Highly doped gate electrode made by rapidly melting and resolidifying the gate electrode: The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode... Agent: Texas Instruments Incorporated

20070020901 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0≦x<0.25), subjecting the first layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070020902 - Transistor for semiconductor device and method of forming the same: Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a novel transistor structure combining a plane channel transistor and a fin-type channel transistor formed on the semiconductor substrate is provided to secure a sufficient channel width as compared... Agent: Heller Ehrman White & Mcauliffe LLP

20070020903 - Hybrid pvd-cvd system: A method for making a film stack containing one or more silicon-containing layers and one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes one or more transfer chambers coupled to one or more load... Agent: Patterson & Sheridan, LLP

20070020905 - Low resistance contact in a semiconductor device: In a method for manufacturing a contact electrically contacting an electrically conductive silicon structure, a substrate with a surface is provided, the substrate having the silicon structure at the surface. Silicon oxide is grown selectively on at least part of the silicon structure. A layer is produced over the surface... Agent: Morrison & Foerster LLP

20070020906 - Method for forming high reliability bump structure: Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the... Agent: Birch, Stewart, Kolasch & Birch, LLP

20070020907 - Method of forming a connecting conductor and wirings of a semiconductor chip: A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the resist... Agent: Dickstein, Shapiro, Morin & Oshinsky, LLP

20070020904 - Selectively filling microelectronic features: Some embodiments of the present invention include filling features using selective fill techniques.... Agent: Blakely Sokoloff Taylor & Zafman

20070020909 - Forming of conductive bumps for an integrated circuit: A method for forming conductive bumps on conductive pads formed on an electronic circuit wafer, comprising the steps of: including forming a resist mask with holes above the pads; depositing balls in the holes; performing a thermal processing to melt the balls; and eliminating the mask.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070020908 - Multilayer structure having a warpage-compensating layer: A multilayer structure is provided that includes a semiconductor member having opposing first and second major surfaces, a warpage-compensating layer deposited on the first major surface, and a substrate bonded to the second major surface. The warpage-compensating layer has a stiffness and a coefficient of thermal expansion keyed to the... Agent: Tessera Lerner David Et Al.

20070020910 - Photoresist stripper composition and methods for forming wire structures and for fabricating thin film transistor substrate using composition: A photoresist stripper composition, a method for forming wire structures thereby, and a method of fabricating a thin film transistor substrate using the composition. The photoresist stripper composition includes about 50 WT % to about 70 WT % of butyldiglycol, about 20 to about 40 WT % of an alkylpyrrolidone,... Agent: Macpherson Kwok Chen & Heid LLP

20070020911 - Self alignment features for an electronic assembly: Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020912 - Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an... Agent: Sughrue Mion, PLLC

20070020913 - Method of forming solder bump with reduced surface defects: A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a... Agent: Harness, Dickey & Pierce, P.L.C

20070020914 - Circuit substrate and method of manufacturing the same: In a method of manufacturing a circuit substrate of the present invention, a first through hole is formed in a semiconductor substrate and a first insulating layer is formed on the entire surface of the semiconductor substrate, and then first wiring layers connected to each other via an outer through... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070020916 - Methods for forming flexible column die interconnects and resulting structures: A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in the form of a contact pad to which they... Agent: Trask Britt, P.C./ Micron Technology

20070020917 - Methods for forming macroporous monolithic methylsilsesquioxanes: The present invention relates to a two-step method of preparing methylsilsequixane (MSQ) materials suitable for chromatographic applications comprising treating a MSQ precursor with a suitable acid followed by treatment with a suitable base under conditions to form a MSQ monolith suitable for chromatographic applications.... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20070020915 - Mmic having back-side multi-layer signal routing: A method includes providing a single crystal wafer having MMIC chips. Each chip has an active device in a first surface portion of a semiconductor substrate provided by the wafer and an electrical interconnect having a first portion disposed on a second surface of the semiconductor substrate. The semiconductor substrate... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20070020918 - Substrate processing method and substrate processing apparatus: The present invention provides a substrate processing method that can perform improved flattening and processing upon the formation of interconnects. The a substrate processing method includes a step of eliminating a level difference in a surface of a interconnect material to flatten a surface, a step of removing the interconnect... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070020919 - Preamorphization to minimize void formation: Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the... Agent: Amin, Turocy & Calvin, LLP

20070020920 - Method for fabricating low leakage interconnect layers in integrated circuits: A method for fabricating a low leakage integrated circuit structure. An antireflective layer is disposed without intervening layers directly onto the top of an interconnect conductor, and a dielectric layer is disposed over the antireflective layer. The interconnect conductor is aluminum; the antireflective layer is titanium nitride, and the antireflective... Agent: Avago Technologies, Ltd. C/o Klaas, Law, O'meara & Malkin, P.C.

20070020922 - Method of depositing a metal seed layer on semiconductor substrates: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material... Agent: Kenyon & Kenyon LLP

20070020921 - Prevention of trench photoresist scum: Methods of preventing photoresist scum formation for etch processes for patterning material layers of semiconductor device material layers are disclosed. A treatment of N2 and O2 is used to prevent the formation of photoresist scum. The treatment may be performed in-situ, and may be performed during the etch process, after... Agent: Slater & Matsil, L.L.P.

20070020923 - Ald formed titanium nitride films: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-containing precursor chemical such as TDEAT,... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070020924 - Tungsten nitride atomic layer deposition processes: In one embodiment, a method for forming a tungsten barrier material on a substrate is provided which includes depositing a tungsten layer on a substrate during a vapor deposition process and exposing the substrate sequentially to a tungsten precursor and a nitrogen precursor to form a tungsten nitride layer on... Agent: Patterson & Sheridan, LLP

20070020925 - Method of forming a nickel platinum silicide: A substrate having at least one silicon device is provided. A nickel platinum alloy layer is formed on the substrate. A rapid thermal process is performed to react the nickel platinum alloy layer with the silicon device to produce a nickel platinum silicide. A passivation layer is formed on the... Agent: North America Intellectual Property Corporation

20070020926 - Electrical connections in substrates: A method of making an electrical connection between a first (top) and a second (bottom) surface of a conducting or semi-conducting substrate includes creating a trench in the first surface, and establishing an insulating enclosure entirely separating a portion of the substrate, defined by the trench. Also described is a... Agent: Young & Thompson

20070020927 - Manufacturing method for electronic substrate, manufacturing method for electro-optical device, and manufacturing method for electronic device: A manufacturing method for an electronic substrate, includes: preparing a substrate and a mask having a predetermined region; forming a wiring pattern on the substrate; forming an aperture portion in the predetermined region of the mask; affixing the mask on the substrate; and removing at least a part of the... Agent: Harness, Dickey & Pierce, P.L.C

20070020928 - Multi-layer interconnect with isolation layer: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation... Agent: Knobbe Martens Olson & Bear LLP

20070020929 - Method for reducing dendrite formation in nickel silicon salicide processes: A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of... Agent: Cantor Colburn LLP - IBM Fishkill

20070020930 - Semiconductor device fabricated by a method of reducing the contact resistance of the connection regions: A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer... Agent: Knobbe Martens Olson & Bear LLP

20070020931 - Manufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy and semiconductor device of this kind: (a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070020932 - Manufacturing method of wiring board and semiconductor device: A manufacturing method of a wiring board and a semiconductor device at low cost and by a simple process, without performing complicated steps many times is proposed. Furthermore, a manufacturing method of a wiring board at low cost and with fewer adverse effects on the environment, and a manufacturing method... Agent: Eric Robinson

20070020937 - Etch chamber with dual frequency biasing sources and a single frequency plasma generating source: A method and apparatus for selectively controlling a plasma in a processing chamber during wafer processing. The method includes providing process gasses into the chamber over a wafer to be processed, and providing high frequency RF power to a plasma generating element and igniting the process gases into the plasma.... Agent: Robert M. Wallace Law Office Of Robert M. Wallace

20070020934 - Hard mask structure for patterning of materials: Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a... Agent: Ryan, Mason & Lewis, LLP

20070020933 - Method of cleaning treatment and method for manufacturing semiconductor device: In a crystal growth reactor, a source material having an etching action and a crystal growth source material are simultaneously supplied to a semiconductor wafer surface, so that residual impurities can be eliminated in an efficient manner by balancing etching rate and crystal growth rate.... Agent: Young & Thompson

20070020936 - Methods of etching features into substrates: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the... Agent: Wells St. John P.s.

20070020935 - Process for enhancing solubility and reaction rates in supercritical fluids: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes,... Agent: Dinsmore & Shohl LLP One Dayton Centre

20070020938 - Semiconductor probe with resistive tip and method of fabricating the same, and information recording apparatus, information reproducing apparatus, and information measuring apparatus having the semiconductor probe: Provided are a semiconductor probe having a resistive tip, a method of fabricating the semiconductor probe, and a method of recording and reproducing information using the semiconductor probe. The semiconductor probe includes a tip and a cantilever. The tip is doped with first impurities. The cantilever has an end portion... Agent: Sughrue Mion, PLLC

20070020939 - Controlled geometry hardmask including subresolution elements: Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high... Agent: Trask Britt, P.C./ Micron Technology

20070020940 - Method of forming fluorinated carbon film: The present invention is made to solve a problem to improve adhesion between a fluorine-containing carbon film and a foundation film. In order to achieve this object, according to the present invention, a fluorine-containing carbon film forming method of forming a fluorine-containing carbon film on a to-be-processed substrate includes: a... Agent: Crowell & Moring LLP Intellectual Property Group

20070020941 - Plasma etching apparatus and particle removal method: The invention provides a particle removal method for a plasma processing apparatus, the method easily removing particles in the chamber up to its lower part. In a plasma etching apparatus including an upper antenna, a lower electrode, pressure gauges P1 and P2, gas introducing means, evacuating means, and phase controlling... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070020942 - Method and system for providing a continuous motion sequential lateral solidification for reducing or eliminating artifacts, and a mask for facilitating such artifact reduction/elimination: An arrangement, process and mask for implementing single-scan continuous motion sequential lateral solidification of a thin film provided on a sample such that artifacts formed at the edges of the beamlets irradiating the thin film are significantly reduced. According to this invention, the edge areas of the previously irradiated and... Agent: Baker & Botts L.L.P.

20070020943 - Apparatus and method for removing a photoresist structure from a substrate: In an apparatus and method for removing a photoresist structure from a substrate, a chamber for receiving the substrate includes a showerhead for uniformly distributing a mixture of water vapor and ozone gas onto the substrate. The showerhead includes a first space having walls and configured to receive the water... Agent: Harness, Dickey & Pierce, P.L.C

20070020944 - Selective etch process of a sacrificial light absorbing material (slam) over a dielectric material: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon... Agent: MoserIPLaw Group / Applied Materials, Inc.

20070020946 - Method for modifying surface of substrate and method for manufacturing semiconductor device: An insulating film is formed on a substrate selected from a group containing a BT resin substrate and an epoxy resin substrate. Copper wirings and copper posts including wirings are formed on the insulating film. Plasma processing is effected on exposed surfaces of the insulating film, copper wirings and copper... Agent: Rabin & Berdo, PC

20070020947 - Method of reducing roughness of a thick insulating layer: A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate; treating the first substrate to form a zone of weakness beneath the insulator layer;... Agent: Winston & Strawn LLP Patent Department

20070020945 - Semiconductor processing system and method: Systems and methods are disclosed to perform semiconductor processing with a process chamber; a flash lamp adapted to be repetitively triggered; and a controller coupled to the control input of the flash lamp to trigger the flash lamp. The system can deploy a solid state plasma source in parallel with... Agent: Fliesler Meyer, LLP

20070020948 - Self-packaged optical interference display device having anti-stiction bumps, integral micro-lens, and reflection-absorbing layers: An electronic device of an embodiment of the invention is disclosed that at least partially displays a pixel of a display image. The device includes a first reflector and a second reflector defining an optical cavity therebetween that is selective of a visible wavelength at an intensity. The device includes... Agent: Hewlett-packard Company Intellectual Property Administration

20070020949 - Method for manufacturing simox wafer and simox wafer: One embodiment of this method for manufacturing a SIMOX wafer includes: while heating a silicon wafer, implanting oxygen ions so as to form a high oxygen concentration layer; implanting oxygen ions into the silicon wafer obtained by the forming of the high oxygen concentration layer so as to form an... Agent: Kolisch Hartwell, P.C.

20070020950 - Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires: A method of manufacturing silicon nano wires including forming microgrooves on a surface of a silicon substrate, forming a first doping layer doped with a first dopant on the silicon substrate and forming a second doping layer doped with a second dopant between the first doping layer and a surface... Agent: Cantor Colburn, LLP

20070020955 - Fabrication method of composite metal oxide dielectric film, and composite metal oxide dielectric film fabricated thereby: The invention relates to a fabrication method of a composite metal oxide dielectric film containing at least two metallic elements on a substrate, and a composite metal oxide dielectric film fabricated thereby. The method includes: forming an amorphous film containing at least one of the metallic elements; preparing a hydrothermal... Agent: Mcdermott Will & Emery LLP

20070020951 - Fluorocarbon film and method for forming same: The major objective is to provide a fluorocarbon film wherein fine voids are formed by a step (SA1) for introducing a mixed gas containing a first carbon fluoride gas and a second carbon fluoride gas on a substrate placed inside a chamber, and depositing a fluorocarbon film on the substrate;... Agent: Hedman & Costigan P.C.

20070020953 - Method for forming a high density dielectric film by chemical vapor deposition: A method for forming a high density dielectric film by chemical vapor deposition. The method comprises: (a) a substrate is provided in a processing chamber; (b) a first gas is introduced into the processing chamber with a first pressure and adsorbed on the substrate, wherein the first gas comprises silicon-containing... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070020954 - Method for manufacturing semiconductor optical device using inductive coupled plasma-enhance cvd: The present invention provides a semiconductor laser diode prevents not only the adhesion of the upper electrode but the heat dissipation of the mesa from degrading. The laser diode includes a substrate, portion of which forms a mesa including an active layer, an insulating layer formed so as to bury... Agent: Venable LLP

20070020952 - Repairing method for low-k dielectric materials: A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k... Agent: Slater & Matsil, L.L.P.

20070020956 - Semiconductor device and method for manufacturing the same: It is made possible to reduce the influence upon adjacent elements. Voids are provided in a Ge substrate. An insulation film containing Ge is provided to cover top faces of the voids.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070020957 - Method of forming an insulating film, method of manufacturing a semiconductor device, and semiconductor device: A method of forming an insulating film includes forming a base film comprising a material whose surface is oxidized by being exposed to an oxidant. A source gas containing a metal material and a first oxidant having a first oxidation force are alternately supplied to form a first insulating film... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070020958 - Plasma processing method and apparatus: With evacuation of interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070015294 - Novel structure/method to fabricate a high-performance magnetic tunneling junction mram: An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta capping layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent... Agent: Saile Ackerman LLC

20070015293 - Tmr device with surfactant layer on top of cofexby/cofez inner pinned layer: A high performance TMR element is fabricated by inserting an oxygen surfactant layer (OSL) between a pinned layer and AlOx tunnel barrier layer in a bottom spin valve configuration. The pinned layer preferably has a SyAP configuration with an outer pinned layer, a Ru coupling layer, and an inner pinned... Agent: George O. Saile

20070015295 - Methods and systems for characterizing semiconductor materials: Methods for determining parameters of a semiconductor material, in particular non-classical substrates such as silicon-on-insulator (SOI) substrates, strained silicon-on-insulator (sSOI) substrates, silicon-germanium-on-insulator (GOI) substrates, and strained silicon-germanium-on-insulator (sGeOI) substrates. The method provides steps for transforming data corresponding to the semiconductor material from real space to reciprocal space. The critical points... Agent: Fulbright & Jaworski L.L.P.

20070015296 - Methods and systems for characterizing semiconductor materials: Methods for determining parameters of a semiconductor material, for example, non-classical substrates such as silicon-on-insulator (SOI) substrates, strained silicon-on-insulator (sSOI) substrates, silicon-germanium-on-insulator (GeOI) substrates, and strained silicon-germanium-on-insulator (sGeOI) substrates are described. The method provides steps for transforming data corresponding to the semiconductor material from real space to reciprocal space. The... Agent: Fulbright & Jaworski L.L.P.

20070015297 - Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing: A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate... Agent: Lsi Logic Corporation

20070015299 - Co-doping for fermi level control in semi-insulating group iii nitrides: Semi-insulating Group III nitride layers and methods of fabricating semi-insulating Group III nitride layers include doping a Group III nitride layer with a shallow level p-type dopant and doping the Group III nitride layer with a deep level dopant, such as a deep level transition metal dopant. Such layers and/or... Agent: Myers Bigel Sibley & Sajovec

20070015298 - Optical element, optical module and method for manufacturing the same: A method for manufacturing an optical element having a surface-emitting type semiconductor laser and a photodetector element that detects light emitted from the surface-emitting type semiconductor laser, the method including the steps of: (a) laminating, above a substrate, semiconductor layers for forming a first mirror, an active layer, a second... Agent: Harness, Dickey & Pierce, P.L.C

20070015300 - Method for fabricating a light-emitting device: The present invention discloses a method for fabricating a light-emitting device, wherein a thermosonic bonding process is utilized to join the contacts on a substrate with bond pads on the light-emitting element. Thereby, the deterioration of the substrate can be reduced, and the yield can also be promoted. Further, in... Agent: Rosenberg, Klein & Lee

20070015301 - Multi spectral sensor: A light sensor having a light conversion element between first and second electrodes is disclosed. The light conversion element includes a body of semiconductor material having first and second surfaces. The body of semiconductor material is of a first conductivity type and has doping elements in a concentration gradient that... Agent: The Law Offices Of Calvin B. Ward Suite 305

20070015302 - Semiconductor device and method of manufacturing thereof: The manufacturing method of a semiconductor device according to the present invention comprises steps of forming a metal film, an insulating film, and an amorphous semiconductor film in sequence over a first substrate; crystallizing the metal film and the amorphous semiconductor film; forming a first semiconductor element by using the... Agent: Eric Robinson

20070015303 - Nanotube device structure and methods of fabrication: Nanotube device structures and methods of fabrication. A method of making a nanotube switching element includes forming a first structure having at a first output electrode; forming second structure having a second output electrode; forming a conductive article having at least one nanotube, the article having first and second ends;... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070015304 - Low compressive tinx, materials and methods of making the same: Disclosed herein is a microelectromechanical device having a structural layer composed of a low stress TiNx layer and a method of making the same.... Agent: Texas Instruments Incorporated

20070015305 - Semiconductor device with micro-lens and method of making the same: A semiconductor device including a semiconductor substrate having a photosensor formed therein; a first layer overlying the substrate, the first layer includes a portion having a generally concave shaped surface being the negative shaped of a micro-lens to be formed there over; a second layer overlying the first layer, the... Agent: Tung & Associates Suite 120

20070015306 - Manufacturing method of p type group iii nitride semiconductor layer and light emitting device: A p type group III nitride semiconductor layer can be manufactured without causing its crystal deterioration, and without requiring any complicated post-treatment, by repeating a plurality of times the following steps: the step A of growing a group III nitride semiconductor layer containing p type impurities; the step B of... Agent: Hogan & Hartson L.L.P.

20070015307 - Method for manufacturing semiconductor device: The present invention relates to a method for manufacturing a semiconductor film, including the steps of forming a transparent conductive film, forming a first conductive film over the transparent conductive film, forming a second conductive film over the first conductive film, etching the second conductive film with a gas including... Agent: Nixon Peabody, LLP

20070015308 - Schottky diode structure to reduce capacitance and switching losses and method of making same: A SiC Schottky barrier diode (SBD) is provided having a substrate and two or more epitaxial layers, including at least a thin, lightly doped N-type top epitaxial layer, and an N-type epitaxial layer on which the topmost epitaxial layer is disposed. Multiple epitaxial layers support the blocking voltage of the... Agent: Hiscock & Barclay, LLP

20070015309 - Electronic part manufacturing method: Provided is a method of manufacturing an electronic part in which a circuit element (3) is formed on a surface of a ceramic substrate (1) and conductive balls (2) are used as terminals of the electronic part. After the ceramic substrate (1) and the conductive balls (2) are fixed, the... Agent: Patent Docket Clerk Cowan, Liebowitz & Latman, P.C.

20070015312 - Method for forming bump protective collars on a bumped wafer: A method of forming bump protective collars is disclosed. A wafer has an active surface with a plurality of bonding pads and a passivation layer. A plurality of reflowed bumps are formed over the bonding pads. A photoresist is coated on the active surface. Using the reflowed bumps as a... Agent: Troxell Law Office PLLC

20070015310 - Polyceramic-coated tool for applying a flowable composition: A tool is provided for applying a flowable composition onto a receiving surface. The tool includes a polyceramic coating on a surface thereof and may take the form of a stencil or mold. Also provided are an apparatus and a method that uses the tool. In use, the tool is... Agent: Tessera Lerner David Et Al.

20070015311 - Structure of mounting electronic component and method of mounting the same: The structure of mounting an electronic component on a circuit board is capable of securely flip-chip-bonding the electronic component having bumps, whose separations are very short, to the circuit board without displacement. The structure of mounting an electronic component on a circuit board is characterized in that bumps of the... Agent: Arent Fox PLLC

20070015313 - Submount of semiconductor laser diode, method of manufacturing the same, and semiconductor laser diode assembly using the submount: Provided is a submount flip-chip bonded to a semiconductor laser diode chip with stepped first and second electrodes. The submount includes a substrate having first and second surfaces which are separated by a step height corresponding to a height difference between the first and second electrodes; first and second metal... Agent: Buchanan, Ingersoll & Rooney PC

20070015314 - Adhesive/spacer island structure for multiple die package: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of... Agent: Haynes Beffel & Wolfeld LLP

20070015315 - Semiconductor device and manufacturing method thereof: A manufacturing method of a semiconductor device is disclosed. The manufacturing method includes a first step that mounts plural semiconductor elements on a first substrate, a second step that inspects each of the semiconductor elements mounted on the first substrate, a third step that divides the first substrate by dicing... Agent: Ladas & Parry LLP

20070015316 - Folded frame carrier for mosfet bga: A folded frame carrier has a die attach pad (DAP) 30 and one or more folded edges 32, 33, 34, 35. Each folded edge has one or more studs 36 and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper... Agent: Hiscock & Barclay, LLP

20070015317 - Method of forming metal line and contact plug of flash memory device: A method of forming a metal line and a contact plug of a flash memory device, wherein if first, second, and third etch processes are performed on an anti-reflection film and regions (a region in which a contact plug through which a gate is exposed is formed/a region in which... Agent: Marshall, Gerstein & Borun LLP

20070015321 - Manufacturing method for semiconductor device: With respect to the selective ratio in the etching process, it is an object to give design freedom in size of an LDD overlapped with a gate electrode, which is formed in a self-aligning manner, by performing an etching process under an etching condition that has a high selective ratio... Agent: Nixon Peabody, LLP

20070015319 - Method for forming contact hole and method for fabricating thin film transistor plate using the same: A method for forming a contact hole includes forming a conductive layer on a substrate, patterning the conductive layer to form a wiring, forming an insulating layer on the wiring and the substrate through a low temperature process, and dry etching the insulating layer using an anoxic gas to expose... Agent: F. Chau & Associates, LLC

20070015322 - Method of forming doped regions in the bulk substrate of an soi substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same: In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate in an area above the... Agent: Williams, Morgan & Amerson

20070015320 - Method of making a polycrystalline thin film, a mask pattern used in the same and a method of making a flat panel display device using the same: A method of forming a polycrystalline thin film for a thin film transistor, a mask used in the method, and a method of making a flat panel display device using the method of forming a polycrystalline thin film for a thin film transistor are disclosed. Certain embodiments are capable of... Agent: Knobbe Martens Olson & Bear LLP

20070015318 - Method of manufacturing a thin film transistor: A method of manufacturing a semiconductor device characterized by its high-speed operation and high reliability is provided in which a semiconductor layer crystallized by a CW laser is used for an active layer of a TFT. When a semiconductor layer is crystallized by a CW laser, one part is formed... Agent: Nixon Peabody, LLP

20070015323 - Semiconductor device and method of manufacturing the same: An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in TFT channel formation regions, and is capable of preventing... Agent: Eric Robinson

20070015324 - Fabrication method for single and dual gate spacers on a semiconductor device: A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate.... Agent: Birch Stewart Kolasch & Birch

20070015325 - Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing a semiconductor substrate (1) having an upper surface (O) and having first and second transistor regions (T1, T2); wherein said first transistor region (T1)... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070015326 - Integrated circuit and fabrication process: An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried capacitive elementary trench forming the elementary storage capacitor, and... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20070015327 - Method of fabricating a trench capacitor dram device: The present invention discloses a STI-first process for making trench DRAM devices. According to the preferred embodiment, the etching recipe for etching the STI region in the memory array is completely compatible with the logic STI process.... Agent: North America Intellectual Property Corporation

20070015330 - Metal/semiconductor/metal (msm) back-to-back schottky diode: A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070015329 - Metal/znox/metal current limiter: A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070015328 - Msm binary switch memory device: A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top... Agent: Sharp Laboratories Of America, Inc

20070015332 - Non-volatile memory with asymmetrical doping profile: Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped... Agent: Vierra Magen/sandisk Corporation

20070015331 - Nor flash memory cell with high storage density: Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070015333 - Method for manufacturing silicon carbide semiconductor devices: A method of manufacturing a semiconductor device is disclosed that includes the treating the surface of a SiC semiconductor substrate prior to forming a gate oxide film on the SiC semiconductor substrate in order to etch the SiC semiconductor substrate by several nm to 0.1 μm with hydrogen in a... Agent: Rossi, Kimms & Mcdowell LLP.

20070015334 - Method for forming a fully silicided gate and devices obtained thereof: A method for manufacturing a MOSFET device with a fully silicided (FUSI) gate is described. This method may be used to prevent formation of shorts between the FUSI gate and a contact to a source and/or a drain region. In particular, the method discloses the formation of an expansion volume... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070015335 - Production method for antenna and production device for antenna: m

20070015336 - Method of making a multi-electrode double layer capacitor having hermetic electrolyte seal: A long life double layer capacitor and method of making the same including a case and a first terminal with an electrically insulating hermitic seal interposed between the first terminal and the case. A first current collector foil is electrically coupled to an interior portion of the first terminal and... Agent: Hensley Kim & Edgington, LLC

20070015337 - Semiconductor device and method for fabricating the same: A semiconductor device includes a lower electrode having a bend in its cross-section,FIG a capacitor dielectric film of a ferroelectric deposited on the top face of the lower electrode and an upper electrode deposited on the top face of the capacitor dielectric film. The upper electrode is deposited by chemical... Agent: Mcdermott Will & Emery LLP

20070015338 - Substrate applicable to both wire bonding and flip chip bonding, smart card modules having the substrate and methods for fabricating the same: A substrate, a smart card module having the substrate and methods for fabricating the same are provided. A substrate having metal patterns formed on both sides and applicable to both wire bonding and flip chip bonding, a smart card module having the same and methods of fabricating the same are... Agent: Harness, Dickey & Pierce, P.L.C

20070015339 - Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.... Agent: Wells St. John P.s.

20070015340 - Method and structure for interfacing electronic devices: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.... Agent: Intel/blakely

20070015341 - Method of making mems wafers: A wafer level package for a MEMS device is made by bonding a MEMS wafer and a lid wafer together to form a hermetically sealed cavity. One or more vias filled with conductive or semiconductive material is etched one of the wafers to form one or more rods extending through... Agent: Marks & Clerk

20070015342 - Fabrication method of semiconductor circuit device: When a semiconductor wafer is formed to be thin, steps need to be taken to prevent warping of the wafer. For this purpose, a protective tape is affixed to a surface of the semiconductor wafer, and a back side of the semiconductor wafer is then ground to a predetermined thickness.... Agent: Antonelli, Terry, Stout & Kraus, LLP Suite 1800

20070015343 - Method for dicing a semiconductor wafer: A method for dicing a semiconductor wafer includes the steps of: forming grooves in an integrated circuit layer of the semiconductor wafer; forming a photoresist layer on the integrated circuit layer; forming V-shaped first notches, each of which is further indented from the integrated circuit layer; thinning the substrate; attaching... Agent: Foley And Lardner LLP Suite 500

20070015344 - Method for making a semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions: A method for making a semiconductor device may include forming a superlattice layer including a plurality of stacked groups of layers, and forming at least one pair of spaced apart stress regions on opposing sides of the superlattice layer to induce a strain therein. Each group of layers of the... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070015345 - Lateral growth method for defect reduction of semipolar nitride films: A lateral growth method for defect reduction of semipolar nitride films. The process steps include selecting a semipolar nitride plane and composition, selecting a suitable substrate for growth of the semipolar nitride plane and composition, and applying a selective growth process in which the semipolar nitride nucleates on some areas... Agent: Gates & Cooper LLP Howard Hughes Center

20070015346 - Mixed orientation and mixed material semiconductor-on-insulator wafer: The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations.... Agent: Duane Morris LLP Suite 700

20070015347 - Strain modulation employing process techniques for cmos technologies: A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the first and second regions. A mask is then formed that... Agent: Texas Instruments Incorporated

20070015348 - Crosspoint resistor memory device with back-to-back schottky diodes: A metal/semiconductor/metal (MSM) back-to-back Schottky diode, a resistance memory device using the MSM diode, and associated fabrication processes are provided. The method includes: providing a substrate; forming a metal bottom electrode overlying the substrate, having a first work function; forming a semiconductor layer overlying the metal bottom electrode, having a... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070015349 - Method of producing a composite multilayer: The invention concerns a method for fabricating a composite multilayer comprising a stack of layers of electrically conductive material alternating with layers of electrically insulating material, said method comprising the following steps: a) depositing a conductive material, in layer form, on a peel-off surface of a deposit substrate, b) bonding,... Agent: Robert E Krebbs Thelen Reid & Priest

20070015350 - Methods of manufacturing carbon nanotubes: An optical antenna collects, modifies and emits energy at light wavelengths. Linear conductors sized to correspond to the light wavelengths are used. Nonlinear junctions of small dimension are used to rectify an alternating waveform induced upon the conductors by the lightwave electromagnetic energy. The optical antenna and junctions are effective... Agent: Donald N. Halgren

20070015351 - Process or making a semiconductor device having a roughened surface: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a... Agent: Young & Thompson

20070015353 - Electrically connecting substrate with electrical device: A substrate is electrically connected with an electrical device mounted on the substrate. A ball bond is formed between a first end of a wire and a bonding pad of the substrate. A reverse-motion loop is formed within the wire. A bond is formed between a second end of the... Agent: Hewlett Packard Company

20070015352 - Method of realizing thermosonic wire bonding between metal wires and copper pads by depositing a thin film to surface of semiconductor chip with copper pads: Disclosed is a method of realizing thermosonic wire bonding between metal wires and copper pads by depositing a thin film to surfaces of semiconductor chips with copper pads, where a thin film that provides the effect of self-passivation to prevent oxidization of the copper pads located thereunder is deposited on... Agent: Adesh Bhargava Dykema Gossett PLLC

20070015354 - Method for manufacturing electronic device and electronic device: A method for manufacturing an electronic device comprises a step for forming a coating film (100) on a surface of a conductor portion-containing body (500), a step for forming a photosensitive film (110) on the conductor (500) on which the coating film (100) has been formed, a step for exposing... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070015355 - Methods for forming interconnect structures: A method for forming an interconnect structure. A substrate is provided with a low-k dielectric layer thereon. At least one conductive feature is then formed in the low-k dielectric layer. A cap layer is formed overlying the low-k dielectric layer, and the conductive feature and the low-k dielectric layer is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070015356 - Method for forming contact hole in semiconductor device: A method for forming a contact hole in a semiconductor device is provided. A method for forming a contact hole in a semiconductor device includes: forming an insulation layer over a bottom structure; forming a hard mask pattern over the insulation layer; etching a portion of the insulation layer using... Agent: Blakely Sokoloff Taylor & Zafman

20070015357 - Process of adhesive bonding with patternable polymers for producing microstructure devices on a wafer assembly: A process for adhesive bonding of polymer layers between silicon substrates is disclosed for forming three-dimensional micro-structures on a silicon wafer. A base substrate such as a silicon wafer is provided and a coating step places at least one polymer thereon. At least one pattern is created in the polymer... Agent: Jack Kenneth Greer, Jr. U.s. Army Aviation And Missile Command

20070015358 - Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a... Agent: Wells St. John P.s.

20070015359 - Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a... Agent: Wells St. John P.s.

20070015360 - Contact clean by remote plasma and repair of silicide surface: Method for recovering treated metal suicide surfaces or layers are provided. In at least one embodiment, a substrate having an at least partially oxidized metal suicide surface disposed thereon is cleaned to remove the oxidized regions to provide an altered metal silicide surface. The altered metal silicide surface is then... Agent: Patterson & Sheridan, LLP

20070015363 - Electronic board and manufacturing method thereof, electro-optical device, and electronic apparatus: An electronic board includes: a substrate; and a wiring pattern provided on the substrate and having a part that forms a resistance element, the part having wiring specifications that are different from those of other parts.... Agent: Harness, Dickey & Pierce, P.L.C

20070015361 - Manufacturing method of micro-electro-mechanical device: A method of forming a microstructure body and a semiconductor element for controlling the microstructure body over the same substrate to reduce manufacturing cost, for mass-production of micromachines having a microstructure. In manufacturing a micromachine, a sacrifice layer is formed using a mask material for forming a pattern of a... Agent: Fish & Richardson P.C.

20070015362 - Semiconductor device having storage nodes and its method of fabrication: Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an... Agent: Marger Johnson & Mccollom, P.C.

20070015365 - Method and apparatus for enhanced cmp planarization using surrounded dummy design: In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one... Agent: Duane Morris, LLPIPDepartment

20070015364 - Method for avoiding exposure of void caused by dielectric gap-filling, and fabricating process and structure of dielectric film: A method for avoiding exposure of a void caused by dielectric gap-filling is described. An etching-resistant layer is formed on only a portion of the dielectric layer over the gap covering at least the dielectric layer over the void, so that the void is not exposed in a subsequent etching... Agent: Jianq Chyun Intellectual Property Office

20070015366 - Semiconductor device and programming method: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the... Agent: James Hao, Esq. Wagner, Murabito & Hao

20070015367 - Electrochemical fabrication methods including use of surface treatments to reduce overplating and/or planarization during formation of multi-layer three-dimensional structures: A method of fabricating three-dimensional structures from a plurality of adhered layers of at least a first and a second material wherein the first material is a conductive material and wherein each of a plurality of layers includes treating a surface of a first material prior to deposition of the... Agent: Microfabrica Inc. Att: Dennis R. Smalley

20070015368 - Method of reducing silicon damage around laser marking region of wafers in sti cmp process: A wafer has thereon a plurality of integrated circuit die areas, scribe line that surrounds each of the integrated circuit die areas, and a laser marking region having therein a laser marking feature. A pad layer is formed on the wafer. AA photoresist pattern is formed on the pad layer.... Agent: North America Intellectual Property Corporation

20070015369 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device, includes forming a lower organic insulating film, inorganic insulating film and upper organic insulating film, making a first hole which has first and second parts passing through the upper organic insulating film and the inorganic insulating film, and performing dry etching on the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070015370 - Manufacturing method for semiconductor device: It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristics with high yield. In a method for manufacturing a semiconductor device according to the present invention, a semiconductor layer... Agent: Nixon Peabody, LLP

20070015371 - Etching radical controlled gas chopped deep reactive ion etching: A method for silicon micromachining techniques based on high aspect ratio reactive ion etching with gas chopping has been developed capable of producing essentially scallop-free, smooth, sidewall surfaces. The method uses precisely controlled, alternated (or chopped) gas flow of the etching and deposition gas precursors to produce a controllable sidewall... Agent: Lawrence Berkeley National Laboratory

20070015372 - Etching solution, method of forming a pattern using the same, method of manufacturing a multiple gate oxide layer using the same and method of manufacturing a flash memory device using the same: Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present... Agent: Harness, Dickey & Pierce, P.L.C

20070015374 - Apparatus and method for atomic layer deposition on substrates: A deposition station allows atomic layer deposition (ALD) of films onto a substrate. The station comprises an upper and a lower substantially flat part between which a substrate is accommodated. The parts are positioned opposite each other and parallel to the substrate during processing. At least one of the parts... Agent: Knobbe Martens Olson & Bear LLP

20070015373 - Semiconductor device and method of processing a semiconductor substrate: A method of processing a semiconductor substrate is provided. The method includes depositing an amorphous hydrogenated carbon film on a semiconductor substrate using a low temperature plasma deposition process and performing at least one high temperature processing step on the semiconductor substrate. The SiC substrate is processed by ion implanting... Agent: General Electric Company Global Research

20070010031 - Method of treating a substrate in manufacturing a magnetoresistive memory cell: A method of treating a substrate in manufacturing a magnetoresistive memory cell includes performing a cleaning operation on the substrate using a mask layer as a protection layer for etching of a peripheral via. Further, an etch stop layer can used as a protection layer in a cleaning operation on... Agent: Edell, Shapiro & Finnan, LLC

20070010032 - Defect identification system and method for repairing killer defects in semiconductor devices: A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action... Agent: Fox Rothschild LLP Princeton Pike Corporate Center

20070010033 - Method and system for deposition tuning in an epitaxial film growth apparatus: A method of calculating a process parameter for a deposition of an epitaxial layer on a substrate. The method includes the steps of measuring an effect of the process parameter on a thickness of the epitaxial layer to determine a gain curve for the process parameter, and calculating, using the... Agent: Townsend And Townsend And Crew LLP / Amat

20070010034 - Deposition stop time detection apparatus and methods for fabricating copper using the same: A method for fabricating copper wiring of a semiconductor device comprises forming a deposition stop time detection pattern having two trench structures positioned with a predetermined distance from each other on a dielectric substrate; positioning a deposition stop time detection apparatus having a plurality of detection electrodes and a guide... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070010035 - Light emitting diode and manufacturing method thereof: A method for fabricating a light emitting diode (LED) is provided. First, a first type doped semiconductor layer, an emitting layer and a second type doped semiconductor layer are sequentially formed on an epitaxy substrate. Then, a first transparent conductive layer is formed on the second type doped semiconductor layer.... Agent: Jianq Chyun Intellectual Property Office

20070010036 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress generation of a crack and peeling in a resin BM and deterioration of coverage of an upper layer of the resin BM, even if a black resin is used as... Agent: Nixon Peabody, LLP

20070010037 - Superlattice nanocrystal si-sio2 electroluminescence device: A superlattice nanocrystal Si—SiO2 electroluminescence (EL) device and fabrication method have been provided. The method comprises: providing a Si substrate; forming an initial SiO2 layer overlying the Si substrate; forming an initial polysilicon layer overlying the initial SiO2 layer; forming SiO2 layer overlying the initial polysilicon layer; repeating the polysilicon... Agent: Sharp Laboratories Of America, Inc

20070010038 - Pattern forming method and wiring pattern forming method, and electro-optic device and electronic equipment: To provide a pattern forming method enabling a thin film to be patterned with high precision by easy and low cost techniques. A thin film 2 is provided on a base material 1 containing a sublimable dyestuff, light is irradiated to the base material 1, and heat generated by the... Agent: Oliff & Berridge, PLC

20070010039 - Organic electroluminescent device and fabricating method thereof: An organic electroluminescent device includes a substrate, a plurality of gate lines on the substrate, a plurality of data lines on the substrate, each of the plurality of data lines crossing the gate lines, a plurality of switching elements and driving elements interconnected on the substrate, and a power line... Agent: Morgan Lewis & Bockius LLP

20070010040 - Method for making a semiconductor device including a strained superlattice layer above a stress layer: A method for making a semiconductor device may include forming a stress layer, and forming a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070010041 - Method of manufacturing optical device having transparent cover and method of manufacturing optical device module using the same: Example embodiments of the present invention relate to a method of manufacturing an optical device having a transparent cover and a method of manufacturing an optical device module using the optical device. According to an example method of manufacturing the optical device, a semiconductor substrate having a plurality of dies... Agent: Harness, Dickey & Pierce, P.L.C

20070010042 - Method of manufacturing a cmos image sensor: The present invention relates to the method of manufacturing an image sensor, the method comprising providing a semiconductor substrate, which comprises a pixel array area and a logic area, a plurality of the photodiodes are formed on the semiconductor substrate of the pixel array area, a multilevel interconnect process is... Agent: North America Intellectual Property Corporation

20070010044 - Method for sensor edge and mask height control for narrow track width devices: A process for defining and controlling the mask height of sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used to form the mask structure.... Agent: Bracewell & Patterson, LLP

20070010043 - Method for sensor edge control and track width definition for narrow track width devices: A process for defining and controlling the track width for sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used to form the mask structure.... Agent: Bracewell & Patterson, LLP

20070010045 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device comprises (a) forming a resin layer that includes at least a plurality of a first and a second resin parts, being separated from each other, over a semiconductor substrate having an electrode pad and a passivation film; (b) forming a resin projection in... Agent: Oliff & Berridge, PLC

20070010046 - Semiconductor device and method for manufacturing the same: In a method of manufacturing a semiconductor device of the invention, a rigid substrate which supports one or more semiconductor elements on a surface of the substrate and is clamped between an upper mold and a lower mold of an encapsulation mold at a time of resin encapsulation is provided,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070010047 - Semiconductor device and manufacturing method thereof: The objectives of the present invention are achieving TFTs having a small off current and TFT structures optimal for the driving conditions of a pixel portion and driver circuits, and providing a technique of making the differently structured TFTs without increasing the number of manufacturing steps and the production costs.... Agent: Eric Robinson

20070010048 - Semiconductor-on-insulator (soi) strained active areas: Differentially strained active regions for forming strained channel semiconductor devices and a method of forming the same, the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; forming a doped area... Agent: Randy W. Tung Tung & Associates

20070010050 - Method for forming semiconductor devices having reduced gate edge leakage current: The present invention provides methods for forming semiconductor FET devices having reduced gate edge leakage current by using plasma or thermal nitridation and low-temperature plasma re-oxidation processes post gate etch.... Agent: International Business Machines Corporation Dept. 18g

20070010051 - Method of forming a mos device with an additional layer: A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain... Agent: Slater & Matsil, L.L.P.

20070010049 - Thermal dissipation structures for finfets: A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070010052 - Creating high voltage fets with low voltage process: An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor (HV-second-conductivity FET). The HV first-conductivity FET has a second-conductivity-well and a field oxide formed over the second-conductivity-well to define an active area. A first-conductivity-well is formed in... Agent: Hewlett Packard Company

20070010057 - Flash memory structure and fabrication method thereof: A flash memory structure comprises a semiconductor substrate, a source region, a drain region, a first insulating dielectric layer, a floating gate, a second insulating dielectric layer, and a control gate. The semiconductor substrate has a first top surface and a second top surface that is lower than the first... Agent: Lowe Hauptman Berner, LLP

20070010053 - Method for fabricating conductive line: A method for fabricating a conductive line is provided. First, a substrate having at least two isolation structures already formed is provided. A first conductive layer is formed between every two isolation structures. Then, a dielectric layer is formed on the substrate. The dielectric layer is patterned to form an... Agent: Jianq Chyun Intellectual Property Office

20070010054 - Method for forming patterned media for a high density data storage device: Systems in accordance with the present invention can include a tip contactable with a media, the media including a substrate and a plurality of cells disposed over the substrate, one or more of the cells being electrically isolated from the other of the cells by a material having insulating properties.... Agent: Fliesler Meyer, LLP

20070010055 - Non-volatile memory and fabricating method thereof: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between... Agent: J C Patents, Inc.

20070010056 - Nor-type flash memory device and manufacturing method thereof: A flash memory device that has a structure capable of preventing gate stack damage, and a method of manufacturing the same, is presented. The method includes forming a first photo resist pattern to open a common source region on a substrate where a shallow trench isolation region, a tunnel oxide... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070010058 - Method and apparatus for a self-aligned recessed access device (rad) transistor gate: A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer.... Agent: Micron Technology, Inc.

20070010059 - Fin field effect transistors (finfets) and methods for making the same: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) forming a first side of a fin of a fin field effect transistor (FinFET); (2) processing the first side of the fin; and (3) forming a second side of... Agent: Ibm Corporation, Intellectual Property Law

20070010060 - Metal-substituted transistor gates: One aspect of this disclosure relates to a method for forming a transistor. According to various method embodiments, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. A desired gate material is substituted for... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070010061 - Metal-substituted transistor gates: One aspect of this disclosure relates to a method for forming an integrated circuit. According to various embodiments of the method, a plurality of transistors is formed. For each transistor, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070010062 - Method to obtain fully silicided poly gate: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer material 160 over gate electrodes 150 that are, in turn, located over a microelectronics substrate 110. The gate electrodes 150 have a doped region 170a located between them. A portion... Agent: Texas Instruments Incorporated

20070010063 - Method for manufacturing capacitor: A method for manufacturing a capacitor includes the steps of: forming a lower electrode above a base substrate; forming a dielectric film composed of ferroelectric material or piezoelectric material above the lower electrode; forming an upper electrode above the dielectric film; forming a silicon oxide film that covers at least... Agent: Harness, Dickey & Pierce, P.L.C

20070010065 - Method of making a capacitive substrate for use as part of a larger circuitized substrate, method of making said circuitized substrate and method of making an information handling system including said circuitized substrate: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20070010064 - Method of making a capacitive substrate using photoimageable dielectric for use as part of a larger circuitized substrate, method of making said circuitized substrate and method of making an information handling system including said circuitized substrate: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two... Agent: Lawrence R. Fraley Hinman, Howard & Kattell, LLP

20070010066 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is disclosed, which comprises the steps of (i) forming a circuit element on a semiconductor substrate, (ii) forming a dielectric that covers the circuit element, (iii) forming a first electrode on the dielectric, (iv) forming a ferroelectric film on the first electrode, (v)... Agent: GlobalIPCounselors, LLP

20070010067 - Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same: A transferring method including providing a substrate, forming a transferred layer over the substrate, joining a transfer member to the transferred layer, and removing the transferred layer from the substrate. The transferring method further includes transferring the transferred layer to the transfer member and reusing the substrate for another transfer.... Agent: Oliff & Berridge, PLC

20070010068 - Methods of manufacturing a semiconductor device: Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor... Agent: Harness, Dickey & Pierce, P.L.C

20070010069 - Hand-held laser cutting apparatus and method using same: A hand-held apparatus is disclosed, where that hand-held apparatus comprises a hand piece having an output end, a switch disposed on that hand piece, wherein that switch includes “on” position and an “off” position, and wherein a laser beam is directed outwardly from the output end of the hand piece... Agent: Dale F. Regelman

20070010070 - Fabrication of strained semiconductor-on-insulator (ssoi) structures by using strained insulating layers: The present invention relates to a method for forming one or more strained semiconductor-on-insulator structures, by first forming a precursor structure that contains an upper layer of unstrained semiconductor material and a lower layer of strained insulating material supported by a semiconductor substrate, and then patterning the upper layer of... Agent: Scully, Scott, Murphy & Pressner, P.C.

20070010071 - Method and apparatus for forming silicon oxynitride film: A silicon oxynitride film is formed on a target substrate by CVD, in a process field configured to be selectively supplied with a first process gas containing a chlorosilane family gas, a second process gas containing an oxidizing gas, and a third process gas containing a nitriding gas. This method... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070010072 - Uniform batch film deposition process and films so produced: A batch of wafer substrates is provided with each wafer substrate having a surface. Each surface is coated with a layer of material applied simultaneously to the surface of each of the batch of wafer substrates. The layer of material is applied to a thickness that varies less than four... Agent: Gifford, Krass, Groh, Sprinkle & Citkowski, P.c

20070010074 - Method and system for facilitating bi-directional growth: A method and system for processing at least one portion of a thin film sample on a substrate, with such portion of the film sample having a first boundary and a second boundary. One or more first areas of the film sample are successively irradiated by first beamlets of an... Agent: Baker & Botts

20070010073 - Method of forming a mos device having a strained channel region: A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer... Agent: Slater & Matsil, L.L.P.

20070010075 - Semiconductor device and method for manufacturing same: Disclosed is a semiconductor device having a driver circuit operable at high speed and a method for manufacturing same. An active matrix liquid crystal display device uses a polysilicon film for its TFT active layer constituting a pixel matrix circuit because of low off current characteristics. On the other hand,... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070010076 - Polycrystalline sige junctions for advanced devices: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused... Agent: George Sai-halasz

20070010077 - Electronic component and a system and method for producing an electronic component: In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at... Agent: Brinks Hofer Gilson & Lione Infineon

20070010078 - Methods of forming integrated circuitry and methods of forming local interconnects: In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the etching, a circuit component is formed in the first... Agent: Wells St. John P.s.

20070010079 - Method for fabricating semiconductor device: According to the present invention, a method for fabricating a semiconductor device includes the steps of: providing a semiconductor substrate; providing a diffusion layer in the semiconductor substrate; providing a first oxide layer on the semiconductor substrate; providing a poly-silicon layer on the first oxide layer; introducing phosphorus into the... Agent: Volentine Francos & Whitt, PLLC One Freedom Square

20070010080 - Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is... Agent: Haynes And Boone, LLP

20070010081 - Mosfet with multiple fully silicided gate and method for making the same: A process is described for forming a fully multiple silicided gate for complementary MOSFET (CMOS) devices. A silicidation process is performed on a gate structure, which includes a gate material overlying a gate dielectric disposed on a substrate. A layer of insulating material is formed which covers the gate structure;... Agent: International Business Machines Corporation Dept. 18g

20070010082 - Structure and method for manufacturing phase change memories with particular switching characteristics: The object of providing a method for manufacturing a phase change memory, as well as a phase change memory so as to better harmonize the contrary requirements for the phase change material is solved by the present invention by a method for manufacturing a phase change memory comprising at least... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070010083 - Method of realizing direct bonding between metal wires and copper pads by means of thermosonic wire bonding using shielding gas spraying device: Discloses is a method of realizing direct bonding between metal wires and copper pads by means of thermosonic wire bonding using a shielding gas spraying device, where a shielding gas is provided between metal wires and a chip with copper pads during thermosonic wire bonding to form a gas shielding... Agent: Schmeiser, Olsen & Watts

20070010084 - Semiconductor processing methods, and semiconductor constructions: The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material... Agent: Wells St. John P.s.

20070010086 - Circuit board with a through hole wire and manufacturing method thereof: An aluminum substrate is drilled to form a first through hole, and is then laminated with copper foils on upper and lower surfaces of the aluminum substrate via a binder. Due to the pressure of the lamination, the binder is partially forced to flow into and fill the first through... Agent: Birch Stewart Kolasch & Birch

20070010087 - Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area: A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070010085 - Semiconductor device and fabrication method thereof: Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070010088 - Semiconductor device and method of fabricating the same: A semiconductor and a method of fabricating the same are provided. The method includes: forming an insulation layer on a substrate; forming a trench by selectively etching the insulation layer; electroplating a copper layer in the trench and on the insulation layer under such conditions that a seam is formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070010089 - Method of forming bit line of semiconductor device: A method of forming a semiconductor device includes forming a contact hole in a first interlayer insulating layer that is provided on a semiconductor substrate. The contact hole has a sidewall defined by the first interlayer insulating layer. A first conductive layer is provided within the contact hole. The first... Agent: Townsend And Townsend And Crew, LLP

20070010090 - Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current: A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An... Agent: Mills & Onello LLP

20070010091 - Method for performing chemical shrink process over barc (bottom anti-reflective coating): A structure and a method for forming the same. The method comprises providing a structure including (a) a hole layer, (b) a BARC (bottom antireflective coating) layer on the top of the hole layer, and (c) a patterned photoresist layer on top of the BARC layer and having a photoresist... Agent: Schmeiser, Olsen & Watts

20070010092 - Method for eliminating bridging defect in via first dual damascene process: A via-first dual damascene process is disclosed. When forming trench lines directly above two small pitched, dense via openings having diameter that is substantially equal to the line width of the trench lines, the trench photoresist is biased on the via openings to partially mask the sidewalls of the two... Agent: North America Intellectual Property Corporation

20070010093 - Method of room temperature growth of siox on silicide as an etch stop layer for metal contact open of semiconductor devices: Silicide is protected during MC RIE etch by first forming an oxide film over the silicide and, after performing MC RIE etch, etching the oxide film. The oxide film is formed from a film of alloyed metal-silicon (M-Si) on the layer of silicide, then wet etching the metal-silicon. An ozone... Agent: International Business Machines Corporation Dept. 18g

20070010094 - Method for depositing a conductive carbon material on a semiconductor for forming a schottky contact and semiconductor contact device: The invention relates to a method for depositing a conductive carbon material (17) on a semiconductor (14) for forming a Schottky contact (16). The inventive method comprises the following steps: introducing a semiconductor (14) into a process chamber (10); heating the interior (10′) of a process chamber (10) to a... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070010096 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: loading a wafer into a chamber including a ceramic dome coated with a material having etch tolerance against a plasma; etching a gate structure formed on the wafer, thereby generating etch remnants; and removing the etch remnants by... Agent: Blakely Sokoloff Taylor & Zafman

20070010095 - Surface treatment method using ion beam and surface treating device: The problems to be solved by the present invention are to provide a novel surface treatment method and a surface treatment apparatus for surface cleaning or surface processing of a solid material, which utilize material that assumes a liquid state at normal temperature and pressure, and the surface treatment method... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070010097 - Apparatus and method for selected site backside unlayering of silicon, gaas, gaxalyasz of soi technologies for scanning probe microscopy and atomic force probing characterization: Apparatus for exposure and probing of features in a semiconductor workpiece includes a hollow concentrator for covering a portion of the workpiece connected by a gas conduit to a supply of etchant gas. A stage supports and positions the semiconductor workpiece. Control means moves the stage and the semiconductor workpiece... Agent: International Business Machines Corporation Dept. 18g

20070010098 - Use of cmp for aluminum mirror and solar cell fabrication: The invention is directed to a method of polishing a surface of a substrate comprising aluminum, comprising contacting a surface of the substrate with a polishing pad and a polishing composition comprising an abrasive, an agent that oxidizes aluminum, and a liquid carrier, and abrading at least a portion of... Agent: Steven Weseman Associate General Counsel, I.p.

20070010099 - Method of pattern etching a silicon-containing hard mask: Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas including CF4 to CHF3, where the volumetric ratio of CF4 to CHF3 is within the range of about 2:3 to about 3:1; more typically, about 1:1 to about... Agent: Shirley L. Church, Esq.

20070010100 - Method of plasma etching transition metals and their compounds: A method of plasma etching comprises using a primary etchant of carbon monoxide gas to etch a transition metal or transition metal compound and to form a volatile by-product of metal carbonyl.... Agent: Matrix Semiconductor, Inc.

20070010102 - Method for forming a semiconductor device having a structure of a single crystal scandium oxide film formed on a silicon substrate: A method for forming a semiconductor device includes placing a Si substrate and an Sc2O3 powder source in an oxide chamber, and vaporizing the Sc2O3 powder source in the oxide chamber so as to form a single crystal Sc2O3 film on the Si substrate through electron beam evaporation techniques.... Agent: Darby & Darby P.C.

20070010101 - Use of expanding material oxides for nano-fabrication: This invention relates to a method of fabricating nano-dimensional structures, comprising: depositing at least one deformable material upon a substrate such that the material includes at least one portion; and creating an oxidizable layer located substantially adjacent to the deposited deformable material such that at least a portion of the... Agent: Hewlett Packard Company

20070010103 - Nitric oxide reoxidation for improved gate leakage reduction of sion gate dielectrics: A method of forming a silicon oxynitride gate dielectric. The method includes providing a structure comprising a silicon film formed on a substrate. The structure is exposed to a first plasma comprising a nitrogen source to incorporate nitrogen into the silicon film. The structure is oxidized in an atmosphere comprising... Agent: Patterson & Sheridan, LLP

20070010104 - Processes and systems for laser crystallization processing of film regions on a substrate utilizing a line-type beam, and structures of such film regions: Process and system for processing a thin film sample, as well as at least one portion of the thin film structure are provided. Irradiation beam pulses can be shaped to define at least one line-type beam pulse, which includes a leading portion, a top portion and a trailing portion, in... Agent: Baker & Botts

20070004047 - Methods and apparatus for molecular data storage, retrieval and analysis: In various aspects, the invention provides molecular systems for storing and retrieving information. In some embodiments, polymers capable of selectively binding metal ions, such as nucleic acids, are used to record information in the form of a particular molecular conformation. Electrochemical assay methods employing nanopores may be used to read... Agent: Ralph A. Dowell Of Dowell & Dowell P.C.

20070004048 - Method for producing mgb2 superconductor: A alloy (Mg—X) of metal (X) and Mg in a liquid phase is made to react with B in a solid phase at a low temperature to manufacture a superconductor, which contains a large amount of MgB2 potential for MRI, linear motorcar, superconducting cavity, electric power transmission cable, high-magnetic field... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070004049 - Semiconductor device having ferroelectric film as gate insulating film and manufacturing method thereof: A semiconductor device includes a gate insulating film which at least includes a first insulating film formed on the main surface of a semiconductor substrate and a first ferroelectric film formed on the first insulating film, containing a compound of a preset metal element and a constituent element of the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070004050 - Method of regenerating substrate: For the purpose of readily and thoroughly removing organic material components, in particular such as alignment film and alignment-control projection component, formed on an inorganic material film while minimizing the number of process steps, and reducing damage possibly exerted on the individual layers under the organic material components as possible,... Agent: Birch Stewart Kolasch & Birch

20070004051 - Processing method and device: A processing system has a processing section for continuously processing a member to be processed; an inspection section for inspecting a processed state of the member processed by the processing section; a processed state determination section for determining whether the processed state is defective/nondefective, on the basis of a result... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner

20070004052 - Processing schedule creaitng method, coating and developing apparatus, pattern forming apparatus and processing system: A coating and developing apparatus having a plurality of cassettes includes at least a step of acquiring, for each of all wafers retained in the cassettes, wafer attribute information associated with a cassette retaining that wafer and a process recipe, a step of acquiring inside-cassette information associated with the retained... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070004053 - Tunable alignment geometry: An alignment targets with geometry designs provides a desired alignment offset for processes (both symmetric and asymmetric) on a wafer substrate. The alignment target includes one or more sub-targets, where each sub-target is defined as having a left portion and a right portion having a different geometric pattern, and where... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070004054 - Mosfet temperature sensing: A MOSFET has its gate voltage controlled to provide a constant drain current of the MOSFET, for example to limit inrush current for charging a capacitance of a power supply arrangement. A decrease in the gate voltage supplied to the MOSFET, corresponding to an increase in the junction temperature of... Agent: Smart & Biggar P.o. Box 2999, Station D

20070004055 - Method for regulating temperature and circuit therefor: A method and circuit for managing thermal performance of an integrated circuit. Temperature sensing circuits and a plurality of power FETs that are coupled together in parallel are manufactured from a semiconductor substrate. Each temperature sensing circuit monitors the temperature of the portion of the semiconductor substrate near or including... Agent: Semiconductor Components Industries, LLC Bradley J. Botsch

20070004059 - Method of measuring alignment of measurement pattern: A resist pattern for alignment measurement being shrunk by a heat flow includes a plurality of positive type or negative type line patterns. Widths of spaces between the line patters are greater than twice those of the line patterns. Alternatively, the resist pattern comprises a box-shaped or slit-shaped measurement pattern... Agent: Takeuchi & Kubotera, LLP

20070004058 - Semiconductor manufacturing device with transfer robot: Semiconductor manufacturing equipment is disclosed and comprises a robot comprising a robotic arm adapted to transfer a wafer from a wafer cassette in a load lock chamber to a processing chamber with proper alignment and positioning without the need to intermediately pass through a support chamber specially adapted to align... Agent: Volentine Francos, & Whitt PLLC

20070004057 - Substrate processing method: A substrate processing method of the present invention includes the steps of placing a substrate inside a vacuum container containing particles and processing the substrate inside the container while moving the substrate at a predetermined relative velocity of the substrate to the container. In this case, an allowable upper limit... Agent: Panasonic Patent Center C/o Mcdermott Will & Emery LLP

20070004056 - Systems and methods for direct silicon epitaxy thickness measuring: Systems and methods for measuring thickness of an epitaxial layer grown on a silicon wafer. An oxide layer is generated on a side of the silicon wafer. One or more posts of oxide are created from the oxide layer by masking and removing unwanted oxide. An epitaxial layer is grown... Agent: Honeywell International Inc.

20070004060 - System and method for matching chip and package terminals: A system and method for matching chip and package terminals and for packaging integrated circuits. Various aspects of the present invention may comprise receiving as input a first list of chip terminal identifiers and a second list of package terminal identifiers. The first and second lists may be analyzed with... Agent: Mcandrews Held & Malloy, Ltd

20070004061 - Method for detecting an end-point for polishing a material: An optical surface analysis system for scanning the surface of a (silicon) wafer and detect if any residual material is still on the wafer surface in order to determine an appropriate end-point in a polishing process. An Optical Surface Analyzer (OSA), of the present invention, is generally used to identify... Agent: Jed Caven And Ramin Aghevli Caven & Aghevli LLC

20070004062 - Display panel, display panel inspection method, and display panel manufacturing method: A method of inspecting a display panel, which is capable of distinguishing between whether an EL panel is a good product or a defective product before sealing of the display panel, is provided. In a first method of inspection, a conductive film is patterned to forming pixel electrodes after measuring... Agent: Eric Robinson

20070004063 - Technique for evaluating a fabrication of a die and wafer: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known... Agent: Shemwell Mahamedi LLP

20070004064 - Electroluminescent device comprising porous silicon: An electroluminescent device comprises a porous silicon region adjacent a bulk silicon region, together with a top electrical contact of transparent indium tin oxide and a bottom electrical contact of aluminium. The device includes a heavily doped region to provide an ohmic contact. The porous silicon region is fabricated by... Agent: Nixon & Vanderhye, PC

20070004065 - Phosphor tape article: A phosphor tape article includes a phosphor layer having a phosphor and a polymeric binder material, a pressure sensitive adhesive layer disposed adjacent the phosphor layer such that light transmitted through the pressure sensitive adhesive layer is received by the phosphor layer, and a release liner disposed on the pressure... Agent: 3m Innovative Properties Company

20070004067 - Floating body germanium phototransistor with photo absorption threshold bias region: A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator... Agent: Sharp Laboratories Of America, Inc. C/o Law Office Of Gerald Maliszewski

20070004068 - Image display device and method of manufacturing the same: An image display device includes an envelope having a first substrate and a second substrate opposed to the first substrate with a gap, and a plurality of pixels arranged in the envelope. A plurality of spacers are arranged between the first substrate and the second substrate in the envelope to... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070004066 - Method for manufacturing a light emitting device and a light emitting device manufactured therefrom: A method for manufacturing a light emitting device includes: preparing a light emitting diode including an epitaxial substrate, an n-type cladding layer, an active layer, a p-type cladding layer, and first and second electrodes; thinning the epitaxial substrate; and forming a reflecting layer and a heat dissipating substrate on the... Agent: Foley And Lardner LLP Suite 500

20070004070 - Array substrate for liquid crystal display and method for fabricating the same: An array substrate for an LCD includes a substrate, a gate line, a data line, a gate electrode extending from the gate line formed on the substrate, a gate insulating layer covering the gate electrode and the substrate, a semiconductor layer formed over the gate insulating layer, a source electrode... Agent: Morgan Lewis & Bockius LLP

20070004071 - Liquid crystal display and method for fabricating the same: A liquid crystal display (LCD) and a method for fabricating the same in which the pixel electrodes of a lower substrate includes sub-pixel electrodes each defining a domain and in which the upper substrate includes a common electrode having openings in a region corresponding to the center of the sub-pixel... Agent: Macpherson Kwok Chen & Heid LLP

20070004069 - Liquid crystal display device and fabricating method thereof: A method of fabricating a liquid crystal display device includes performing a first mask process to form a gate line, a gate pad, and a gate electrode on a substrate. The method of fabricating a liquid crystal display device further includes performing a second mask process to form an active... Agent: Brinks Hofer Gilson & Lione

20070004072 - Semiconductor laser element: A method of producing a semiconductor laser element including, growing a lower cladding layer, an active layer, a first left upper cladding layer, a first etching stopper layer, a second left upper cladding layer, a second etching stopper layer, an upper cladding layer and a contact layer in the order... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070004073 - Optical sending apparatus, optical receiving apparatus, and optical transmission system for supervising fault information and methods thereof: An optical transmission system for transmitting optical signals in which signals at different bit rates coexist, includes an optical sending apparatus for, when one or more faults are detected in a signal for transmission, generating a fault information signal with one frequency set in advance in accordance with the faults,... Agent: Dickstein Shapiro LLP

20070004074 - Fabricating method of flat panel display device: A fabricating method of a flat panel display device according to the present invention includes providing a thin film on a substrate; providing a soft mold having a groove and a projection on the thin film; contacting the projection of the soft mold and the thin film; and spreading a... Agent: Mckenna Long & Aldridge LLP

20070004075 - Photosensitive structure and method of fabricating the same: A photosensitive structure and method of fabricating the same. A substrate with at least an insulator layer formed thereon is provided. The insulator layer comprises a plurality of photoreceiving regions, and a plurality of conductive patterns are formed thereon without covering the photoreceiving regions. A dielectric layer is formed on... Agent: Birch Stewart Kolasch & Birch

20070004076 - Cmos image sensor including two types of device isolation regions and method of fabricating the same: Provided are a complementary metal oxide semiconductor (CMOS) image sensor including two types of device isolation regions and a method of fabricating the same. The CMOS image sensor includes a first active region of a semiconductor substrate in which a photodiode is formed; a second active region of the semiconductor... Agent: F. Chau & Associates, LLC

20070004077 - Solid-state image pickup device and fabrication method thereof: A solid-state image pickup device includes: a plurality of light receiving portions arranged in a matrix, and a vertical transfer register which is four-phase driven by first, second, third and fourth transfer electrodes of a three-layer structure. The vertical transfer register is provided for each of columns of the light... Agent: Sonnenschein Nath & Rosenthal LLP

20070004078 - Method for the preparation of group ib-iiia-via quaternary or higher alloy semiconductor films: This invention relates to a method for producing group IB-IIA-VIA quaternary or higher alloy semiconductor films wherein the method comprises the steps of (i) providing a metal film comprising a mixture of group IB and group IIIA metals; (ii) heat treating the metal film in the presence of a source... Agent: Knobbe Martens Olson & Bear LLP

20070004083 - Arrangement in semiconductor packages for inhibiting adhesion of lid to substrate while providing compression support: In a semiconductor flip-chip package having a semiconductor die as part of a substrate assembly, a lid (or lid assembly) and substrate are supported to prevent tilting and teetering of the lid. The lid and substrate do not adhere, so as to reduce cracking of solder joints due to thermal... Agent: Texas Instruments Incorporated

20070004084 - Chip and multi-chip semiconductor device using thereof and method for manufacturing same: The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process... Agent: Mcginn Intellectual Property Law Group, PLLC

20070004080 - Hermetic seals for micro-electromechanical system devices: The invention is directed to a hermetically sealed device and a method for making such device. The device includes optical, micro-electromechanical, electronic and opto-electronic devices, having a substrate with one or a plurality of optical, opto-electronic, electronic or micro-electromechanical (“MEMS”) elements either singly or in combination that are located on... Agent: Corning Incorporated

20070004079 - Method for making contact through via contact to an offset contactor inside a cap for the wafer level packaging of fbar chips: A device package includes a device substrate and a cap mounted on the device substrate. The device substrate includes a contact pad. The cap defines a via with a slightly sloped sidewall through the cap, a contactor extending from an interior surface of the cap, a contactor pad over the... Agent: Avago Technologies, Ltd.

20070004081 - Method for manufacturing a thermal interface material: An exemplary method for manufacturing a thermal interface material includes the steps of: providing a first substrate having a first surface and an opposite second substrate having an opposite second surface spaced apart a predetermined distance; forming a number of carbon nanotubes from one of the first the second surfaces;... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070004082 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is flexible and superiority in physical strength. As a method for manufacturing a semiconductor device, an element layer including a plurality of integrated circuits is formed over one surface of a substrate;... Agent: Eric Robinson

20070004086 - Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same: A ball-limiting metallurgy (BLM) stack is provided for an electrical device. The BLM stack resists tin migration toward the metallization of the device. A solder system is also provided that includes a eutectic-Pb solder on a substrate that is mated to a high-Pb solder, and that withstands higher temperature reflows... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070004085 - Underfill device and method: An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070004087 - Chip packaging process: A chip packaging process is provided. First, a matrix package substrate having a carrying surface with a plurality of scribe lines thereon is provided. The scribe lines divide the package substrate into a plurality of package substrate units. Then, a sealant is formed on each scribe line. A chip is... Agent: Jianq Chyun Intellectual Property Office

20070004088 - Laser separation of encapsulated submount: In a light emitting package fabrication process, a plurality of light emitting chips (10) are attached on a sub-mount wafer (14). The attached light emitting chips (10) are encapsulated. Fracture-initiating trenches (30, 32) are laser cut into the sub-mount wafer (14) between the attached light emitting chips (10) using a... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070004089 - Stacked memory and manufacturing method thereof: To mount a TSOP on an interposer substrate, leads provided to the TSOP are joined to pads of the interposer substrate by a thermosetting conductive resin, and the TSOP exclusive of the leads is joined to ground layers formed in the interposer substrate by a thermosetting conductive resin. The interposer... Agent: Sughrue Mion, PLLC

20070004090 - Electronic assembly with backplate having at least one thermal insert: A technique for manufacturing an electronic assembly includes a number of steps. Initially, a backplate with a cavity formed into a first side of the backplate is provided. Next, an insert is inserted within the cavity. Then, a substrate, with a first side of an integrated circuit (IC) die mounted... Agent: Delphi Technologies, Inc.

20070004091 - Semiconductor device and manufacturing method thereof: A semiconductor device having high reliability and excellent heat radiation and a method for manufacturing the device at low coat. A semiconductor element and a cover as a heat radiation member are bonded through a solder-containing carbon member having a structure that outside solder layers are formed on a surface... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070004093 - Method of fabricating a high-density lead arrangement package structure: A method of fabricating a high-density lead arrangement package structure is disclosed. The first process of the packaging structure is packaging a chip, a plurality of leads and a plurality of metallic bonding wires by encapsulant such that conducting surfaces are formed at lower surfaces of the leads. The second... Agent: Optimum Care International Tech. Inc.

20070004092 - Semiconductor device manufacturing method: This manufacturing method of a semiconductor device prepares a lead frame to which a heat spreader, and the tip parts of a plurality of inner leads were joined via a thermoplastic insulating binding material, arranges a lead frame on a heat stage, and joins the semiconductor chip to the heat... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070004094 - Method of reducing warpage in an over-molded ic package: A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of... Agent: Vierra Magen/sandisk Corporation

20070004096 - Method for containing a device and a corresponding device: A method of enclosing a micromechanical element formed between a base layer and one or more metallization layers includes forming one or more encapsulating layers over the micromechanical element and providing an encapsulating wall surrounding the element extending between the base layer and the one or more encapsulating layers. An... Agent: Edell, Shapiro & Finnan, LLC

20070004095 - Packaging method and apparatus: A method includes populating a circuit board with components, and encapsulating the circuit board and the components with a material. The method further includes separating the circuit board into a plurality of separate devices.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070004097 - Substrate warpage control and continuous electrical enhancement: A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package. The dummy circuit pattern includes a plurality of straight line segments and a plurality of interrupt patterns to breakup one or more of the straight line segments. The interrupt patterns are provided so as... Agent: Vierra Magen/sandisk Corporation

20070004098 - Method of producing a semiconductor device with an aluminum or aluminum alloy electrode: A method of producing a semiconductor device having a thickness of 90 μm to 200 μm and with an electrode on the rear surface, which achieves a high proportion of non-defective devices by optimizing the silicon concentration and thickness of the aluminum-silicon electrode. A surface device structure is formed on... Agent: Rabin & Berdo, PC

20070004099 - Nand flash memory device and method of manufacturing the same: A method of manufacturing a non-volatile memory device includes forming a first conductive layer over a tunnel dielectric layer that is provided on a semiconductor substrate. A non-conductive layer is formed over the first conductive film. The non-conductive layer is etched to define a stack structure between first and second... Agent: Townsend And Townsend And Crew, LLP

20070004101 - Manufacturing method of array substrate using lift-off method: A method of forming a pattern includes forming a photoresist pattern on a substrate, forming a first material layer on substantially an entire surface of the substrate including the photoresist pattern, heat-treating the substrate including the first material layer and the photoresist pattern, and forming the pattern by removing the... Agent: Brinks Hofer Gilson & Lione

20070004102 - Method for manufacturing semiconductor device: An object is to provide a method for manufacturing a semiconductor device which suppresses an influence on a semiconductor element due to entry of an impurity element, moisture, or the like from outside even in the case of thinning or removing a substrate after forming a semiconductor element over the... Agent: Eric Robinson

20070004100 - Semiconductor device and method for manufacturing the same: An IC card is more expensive than a magnetic card, and an electronic tag is also more expensive as a substitute for bar codes. Therefore, the present invention provides an extremely thin integrated circuit that can be mass-produced at low cost unlike a chip of a conventional silicon wafer, and... Agent: Nixon Peabody, LLP

20070004103 - Thin film transistor array panel and manufacturing method thereof: A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second... Agent: F. Chau & Associates, LLC

20070004104 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device having steps of forming an amorphous semiconductor on a substrate having an insulating surface; patterning the amorphous semiconductor to form plural first island-like semiconductors; irradiating a linearly condensed laser beam on the plural first island-like semiconductors while relatively scanning the substrate, thus crystallizing... Agent: Eric Robinson

20070004105 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: forming a gate insulation layer on a substrate; forming a gate electrode on the gate insulation layer, wherein the gate electrode includes a pattern of a poly-silicon layer and a silicide layer on which a hard mask layer... Agent: Blakely Sokoloff Taylor & Zafman

20070004106 - Technique for perfecting the active regions of wide bandgap semiconductor nitride devices: This invention pertains to electronic/optoelectronic devices with reduced extended defects and to a method for making it. The device includes a substrate, a semiconductor active material deposited on said substrate, and electrical contacts. The semiconductor active material defines raised structures having atomically smooth surfaces. The method includes the steps of... Agent: Naval Research Laboratory Associate Counsel (patents)

20070004107 - Methods for fabricating integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations: Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped... Agent: Myers Bigel Sibley & Sajovec

20070004108 - Method and apparatus of fabricating liquid crystal display device: A method and an apparatus of fabricating a liquid crystal display device adapted to improve a lift-off efficiency are disclosed. The liquid crystal display device is also disclosed. The method includes forming a first thin film on a substrate; forming a photo-resist pattern on the first thin film; etching the... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070004109 - Manufacturing a semiconductor device: A technique of reducing fluctuation between elements is provided in which a semiconductor film having a crystal structure is obtained by using a metal element that accelerates crystallization of a semiconductor film and then the metal element remaining in the film is removed effectively. A barrier layer is formed on... Agent: Eric Robinson

20070004110 - Beam homogenizer, laser irradiation apparatus, semiconductor device, and method of fabricating the semiconductor device: An optical system (in FIGS. 1A and 1B) wherein a rectilinear laser beam of homogeneous energy distribution is defined for annealing a non-single crystalline semiconductor film (a surface to-be-irradiated 1108), is constructed of reflectors (1106, 1107 etc.) easily and inexpensively without including lenses of transmission type. The rectilinear laser beam... Agent: Eric Robinson

20070004111 - Method and apparatus for forming a crystalline silicon thin film: A hydrogen gas is supplied into a deposition chamber (10) accommodating a silicon sputter target (2) and a deposition target substrate (S), a high-frequency power is applied to the gas to generate plasma exhibiting Hα/SiH* from 0.3 to 1.3 in the deposition chamber, and chemical sputtering is effected on the... Agent: Rader Fishman & Grauer PLLC

20070004112 - Method of forming thin film transistor and method of repairing defects in polysilicon layer: A method of forming a thin film transistor is described. A polysilicon layer is formed over a substrate, wherein the polysilicon layer has a first region, a second region and a channel region between the first and second regions. A nitrogen doping process is carried out to dope nitrogen into... Agent: Jianq Chyun Intellectual Property Office

20070004113 - Method of ic production using corrugated substrate: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges... Agent: Bever, Hoffman & Harms, LLP

20070004115 - Nand flash memory device and method of fabricating the same: A NAND flash memory device includes a semiconductor substrate having a drain select transistor; a source select transistor, and memory cell transistors connected in series between the drain select transistor and the source select transistor, and an oxide film formed in the semiconductor substrate at each of a first side... Agent: Marshall, Gerstein & Borun LLP

20070004114 - Sacrificial capping layer for transistor performance enhancement: A process for fabricating an n channel transistor, which results in electron mobility improvement in the channel, is described. Sacrificial capping layers comprising an oxide and nitride layer are conformally formed over a polysilicon gate after source and drain implantation, and remain in place during annealing.... Agent: Blakely Sokoloff Taylor & Zafman

20070004117 - Semiconductor device and method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070004116 - Trenched mosfet termination with tungsten plug structures: A metal oxide semiconductor field effect transistor (MOSFET) device includes a termination area. The termination area has a trenched gate runner electrically connected to a trenched gate of said MOSFET. The MOSFET further includes a gate runner contact trench opened through an insulation layer covering the gate runner and into... Agent: Bo-in Lin

20070004119 - Cmos device with dual polycide gates and method of manufacturing the same: A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well... Agent: Ladas & Parry LLP

20070004120 - Method for fabricating cmos image sensor: A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes performing an ion implantation process onto a photodiode region in a first conductivity type semiconductor layer to form a second conductivity type first impurity region, and performing an annealing process in a gas atmosphere including first conductivity type... Agent: Morgan Lewis & Bockius LLP

20070004118 - Methods of improving drive currents by employing strain inducing sti liners: A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer... Agent: Texas Instruments Incorporated

20070004121 - Electronic assembly and method for producing an electronic assembly: A method for producing an electronic assembly and an electronic assembly which has been correspondingly produced are specified. In this case, CMOS structures are formed in a semiconductor substrate to form a circuit and, after the CMOS structures have been formed, at least one electrical conductor is introduced, in a... Agent: Harness, Dickey & Pierce, P.L.C

20070004122 - Method for fabricating semiconductor memory device: A method for fabricating a semiconductor memory device in which a logic circuit and a nonvolatile memory are provided on a semiconductor substrate includes the steps of: forming an isolation region; forming a protective film made of an insulating material over the semiconductor substrate in a logic circuit region and... Agent: Mcdermott Will & Emery LLP

20070004123 - Transistor with improved tip profile and method of manufacture thereof: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving... Agent: Blakely Sokoloff Taylor & Zafman

20070004124 - Mos field effect transistor having plurality of channels and method of fabricating the same: A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are... Agent: Mills & Onello LLP

20070004125 - Semiconductor device and manufacturing method thereof: It is an object of the present invention to provide a semiconductor device in which a barrier property is improved; a compact size, a thin shape, and lightweight are achieved; and flexibility is provided. By providing a stacked body including a plurality of transistors in a space between a pair... Agent: Eric Robinson

20070004130 - Fabrication method of a dynamic random access memory: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the... Agent: Jianq Chyun Intellectual Property Office

20070004128 - Method for fabricating semiconductor device with recess gate: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form... Agent: Blakely Sokoloff Taylor & Zafman

20070004127 - Method of fabricating a transistor having the round corner recess channel structure: In fabricating a transistor having the round corner recess channel structure, a buffer layer and a hard mask layer are formed in the active area of a semiconductor substrate. The buffer layer and the hard mask layer are etched so as to expose a predetermined channel region of the active... Agent: Ladas & Parry LLP

20070004126 - Semiconductor device having a recess gate for improved reliability: A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain... Agent: Ladas & Parry LLP

20070004129 - Semiconductor device having finfet and method of fabricating the same: In one embodiment, a semiconductor device includes a plurality of fin-shaped active regions defined by a trench formed in a substrate with a predetermined depth; an isolation layer formed inside the trench and comprising a first insulating material; and a plurality of word lines formed on the isolation layer inside... Agent: Marger Johnson & Mccollom, P.C.

20070004133 - Capacitor for a semiconductor device and method of fabricating same: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first... Agent: F. Chau & Associates, LLC

20070004132 - Dram memory device: The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact... Agent: Wells St. John P.s.

20070004131 - Methods for forming shallow trench isolation: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the... Agent: Knobbe Martens Olson & Bear LLP

20070004142 - Asymmetric operation method of non-volatile memory structure: An operation method for a non-volatile memory structure formed between two doping regions serving as bit lines in a semiconductor substrate, the non-volatile memory structure comprising a first conductive line serving as a select gate and being formed above the semiconductor substrate, two conductive blocks serving as floating gates and... Agent: Oliff & Berridge, PLC

20070004139 - Method of manufacturing a non-volatile semiconductor device: In a method of manufacturing a non-volatile semiconductor device, a mask structure is formed on a substrate. A trench is formed by partially etching the substrate using the mask structure. A preliminary isolation layer pattern is formed on the substrate to fill the trench. The preliminary isolation layer has an... Agent: Volentine Francos, & Whitt PLLC

20070004140 - Method of manufacturing a non-volatile semiconductor memory device: In a method of manufacturing a non-volatile semiconductor memory device that includes a first region having a first gate structure and a second region having a second gate structure, the first gate structure may include a tunnel oxide layer pattern, a first conductive layer pattern, a dielectric layer pattern and... Agent: Harness, Dickey & Pierce, P.L.C

20070004138 - Method of manufacturing flash memory device: A method of manufacturing flash memory devices wherein, after gate lines are formed, an HDP oxide film having at least the same height as that of a floating gate is formed between the gate lines. Spacers are formed between the remaining spaces using a nitride film. Accordingly, the capacitance between... Agent: Marshall, Gerstein & Borun LLP

20070004141 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device which can improve capacitance and can reduce the interference phenomenon. According to one embodiment, a method of manufacturing a flash memory device includes the steps of depositing a tunnel oxide layer over a semiconductor substrate having a isolation structure, depositing a conductive... Agent: Marshall, Gerstein & Borun LLP

20070004137 - Method of manufacturing semiconductor device: A flash memory device and method of fabricating the same, wherein a width at the top of a floating gate is narrower than that at the bottom of the floating gate. The area of the floating gate can be reduced while maintaining the overlap area between the control gate and... Agent: Marshall, Gerstein & Borun LLP

20070004143 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory cell region which is disposed on the semiconductor substrate and has a transistor array of a stacked gate structure having a floating gate, a Ti-containing barrier which is disposed in an upper layer of the memory cell region and... Agent: Hogan & Hartson L.L.P.

20070004135 - Source side injection storage device and method therefor: A memory charge storage device has regions of sacrificial material overlying a substrate (12). For each memory cell a first doped region (20) and a second doped region (24) are formed within the substrate and on opposite sides of one (16) of the regions of sacrificial material. A discrete charge... Agent: Freescale Semiconductor, Inc. Law Department

20070004136 - Use of chlorine to fabricate trench dielectric in integrated circuits: Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon... Agent: Macpherson Kwok Chen & Heid LLP

20070004134 - Vertically integrated flash eprom for greater density and lower cost: A nonvolative memory in the form of a vertifcal flash EPROM with high density and low cost. A vertical MOS transistor is formed in well etched into a semiconductor substrate, the substrate having source, body and drain regions formed by ion implantation. A thin gate oxide or oxide-nitride-oxide (ONO) layer... Agent: Ronald Craig Fish Ronald Craig Fish, A Law Corporation

20070004144 - Method of fabricating dual gate oxide layer having different thickness in the cell region and the peripheral region: In fabricating a dual gate oxide layer, a first gate oxide layer is first formed on a semiconductor substrate, which has a cell region and a peripheral region. The first gate oxide layer is removed in the peripheral region. A second gate oxide layer is formed on the substrate using... Agent: Ladas & Parry LLP

20070004145 - Method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length: A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate... Agent: Ladas & Parry LLP

20070004146 - Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types: A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step... Agent: Freescale Semiconductor, Inc.

20070004147 - Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment: A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second... Agent: Mcdermott Will & Emery LLP

20070004148 - Multi-level cell of flash memory device: An embodiment of the present invention relates to a flash memory device with an improved data retention characteristic. A height of a floating gate is set lower than that of the conventional floating gate, or an overlap width between the floating gate and isolation structures is set narrower than those... Agent: Townsend And Townsend And Crew, LLP

20070004149 - Method for producing a vertical field effect transistor: A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.... Agent: Brinks Hofer Gilson & Lione Infineon

20070004150 - Electrostatic discharge protection semiconductor structure: An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit finction and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design... Agent: Jianq Chyun Intellectual Property Office

20070004152 - Method for fabricating semiconductor device with step gated asymmetric recess: A method for fabricating a semiconductor device with a step gated asymmetric recess is provided. The method includes: forming an organic bottom anti-reflective coating (BARC) layer over a substrate; forming a patterned mask over the organic BARC layer that expose selected portions of the organic BARC layer; etching the exposed... Agent: Townsend And Townsend And Crew, LLP

20070004151 - Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same: A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on... Agent: Townsend And Townsend And Crew, LLP

20070004154 - Dielectric structure in nonvolatile memory device and method for fabricating the same: A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070004153 - Method for producing charge-trapping memory cell arrays: A memory layer sequence comprising a lower confinement layer (2), a charge-trapping layer (3), and an upper confinement layer (4) is applied on the main surface of a silicon substrate (1). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active... Agent: Slater & Matsil LLP

20070004155 - Method of producing semiconductor element and nonvolatile semiconductor memory produced by this method: In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas atmosphere after deposition, to mend crystal defects that occurred during... Agent: Volentine Francos, & Whitt PLLC

20070004157 - Method of fabricating a light emitting device: There is provided an inexpensive light emitting device and an electronic instrument using the same. In this invention, photolithography steps relating to manufacture of a transistor are reduced, so that the yield of the light emitting device is improved and the manufacturing period thereof is shortened. A feature is that... Agent: Fish & Richardson P.C.

20070004156 - Novel gate sidewall spacer and method of manufacture therefor: The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer (413, 423) and a gate electrode layer (418,... Agent: Texas Instruments Incorporated

20070004158 - Transistor having a germanium implant region located therein and a method of manufacture therefor: The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of... Agent: Texas Instruments Incorporated

20070004159 - Method of manufacturing semiconductor device using gate-through ion implantation: Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation for formation of source/drain regions, on the entire surface of the semiconductor substrate... Agent: Marshall, Gerstein & Borun LLP

20070004161 - Bipolar transistor with high dynamic performances: A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC

20070004160 - Tunable semiconductor diodes: A diode structure fabrication method. In a P− substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is formed. Then, a P+ region is formed to serve as an anode... Agent: Schmeiser, Olsen & Watts

20070004162 - Capacitor structure for a logic process: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing... Agent: Carrie A. Boone, P.C.

20070004163 - Method for fabricating semiconductor device: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070004164 - Capacitor in semiconductor device and method of manufacturing the same: The present invention relates to a capacitor in semiconductor device and a method of manufacturing the same, wherein, owing to formation of a lower electrode and an upper electrode into a stack structure of a poly-silicon layer and an aluminum (Al) layer and formation of an alumina (Al2O3) film as... Agent: Marshall, Gerstein & Borun LLP

20070004165 - Embedded thin layer capacitor, layered structure, and fabrication method of the same: The present invention relates to a thin layer capacitor including first and second metal electrode layers and a dielectric layer of BiZnNb-based amorphous metal oxide having a dielectric constant of at least 15, interposed between the metal layers, and a layered structure having the same. The layered structure includes a... Agent: Volpe And Koenig, P.C.

20070004166 - Method for fabricating capacitor of semiconductor device: Disclosed herein is a method for fabricating a capacitor of a semiconductor device. The method comprises the steps of forming an interlayer insulating film on a semiconductor substrate, forming contact plugs connected to the semiconductor substrate though the interlayer insulating film, forming a first storage node oxide film include a... Agent: Marshall, Gerstein & Borun LLP

20070004167 - Method of manufacturing semiconductor device: Disclosed herein is a method of manufacturing semiconductor devices. After first isolation trenches are formed in a cell region, second isolation trenches are formed in a peripheral region by an etch process using a photoresist as a mask. As such, top corner portions of an active substrate of the peripheral... Agent: Marshall, Gerstein & Borun LLP

20070004168 - Device for the transmission of data and portable electronic unit and field unit for such a device: The invention relates to a device for the transmission of data between a portable electronic unit and a field unit, whereby a cable is provided, connected at the one end thereof to the portable electronic unit and comprises a cable coupling piece at the other end thereof, for wireless proximity... Agent: Siemens Corporation Intellectual Property Department

20070004169 - Method for manufacturing semiconductor substrate: This method for manufacturing a semiconductor substrate is characterized in that the method includes: a step of ion-implanting light element to a predetermined depth position in a single-crystal wafer of which a surface is a cleavage plane; and a step of heat-treating the single-crystal wafer so as to form light-element... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070004170 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a trench for isolation on a surface of a substrate including a semiconductor substrate, filling the trench with a solution containing a perhydrosilazane polymer by applying the solution on the substrate, converting the solution into a film containing the perhydrosilazane polymer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070004171 - Method of supporting microelectronic wafer during backside processing using carrier having radiation absorbing film thereon: A method of supporting a microelectronic wafer during backside processing. The method comprises: selecting a rigid carrier including a radiation absorbing film thereon, an adhesive, and a radiation source to emit radiation at a predetermined wavelength range; forming a wafer-carrier stack by providing the adhesive between the wafer and the... Agent: Blakely Sokoloff Taylor & Zafman

20070004172 - Method of thinning a wafer: A method of thinning a wafer. A wafer having a front surface and a back surface is provided. Subsequently, a carrier wafer is provided, and the back surface of the wafer is bonded to the carrier wafer with a bonding medium. Following that, a wafer thinning process is performed to... Agent: North America Intellectual Property Corporation

20070004173 - Semiconductor wafers including one or more reinforcement structures and methods of forming the same: Methods of forming semiconductor devices include thinning a region of a semiconductor wafer and forming at least one semiconductor die laterally within a thinned region of the wafer. One or more reinforcement structures may be defined on the wafer. Semiconductor wafers include one or more reinforcement structures that extend laterally... Agent: Trask Britt

20070004178 - Manufacturing method of semiconductor device: To provide a semiconductor device including a thinned substrate with high yield. After forming a protective layer in a predetermined portion (at least a portion covering a side surface of a substrate) of the substrate, grinding and polishing of the substrate are performed. In other words, an element layer including... Agent: Eric Robinson

20070004180 - Manufacturing method of semiconductor integrated circuit device: When reducing the thickness of a semiconductor wafer, so that a crushing layer which is relatively thin and has gettering function of, for example, less than 0.5 □m, less than 0.3 □m or less than 0.1 □m in thickness may be formed at the back surface, and the die strength... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070004175 - Semiconductor wafer cutting blade and method: The invention provides apparatus and methods for sawing and singulating individual devices from a silicon or glass-bonded semiconductor wafer. Using methods of the invention, wafer device singulation includes a step of sawing kerfs approximately coinciding with the peripheries of numerous devices arranged on a wafer. Kerfs are also sawn into... Agent: Texas Instruments Incorporated

20070004174 - Semiconductor wafer sawing system and method: The invention provides methods and systems for sawing and singulating individual semiconductor devices manufactured on a wafer. Pursuant to the systems and methods of the invention, a wafer is secured for sawing and is then presented to a saw blade. At least one parameter associated with sawing the wafer is... Agent: Texas Instruments Incorporated

20070004176 - Thin film splitting method: A method of fabricating thin films of semiconductor materials by implanting ions in a substrate composed of at least two different elements at least one of which can form a gaseous phase on bonding with itself and/or with impurities includes the following steps: (1) bombarding one face of the substrate... Agent: Brinks Hofer Gilson & Lione

20070004179 - Wafer dividing method: A method of dividing a wafer having a plurality of devices, which are formed in a plurality of areas sectioned by streets formed in a lattice pattern on the front surface and test metal patterns which are formed on the streets, comprising: a metal pattern breaking step for forming a... Agent: Smith, Gambrell & Russell

20070004177 - Wafer processing method: To prevent cracks from appearing in a wafer when tape is affixed to or peeled off a wafer in a state where the streets break easily preventing damage to or deterioration in the quality of the devices, in a wafer processing method including steps of performing a pre-process on a... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070004181 - Method for fabricating semiconductor device: A method for fabricating a region in which a fuse is formed is provided. The method includes forming a first insulation layer over a substrate, forming a plurality of fuses over the first insulation layer, forming a second insulation layer to cover the fuses, forming an etch stop layer over... Agent: Blakely Sokoloff Taylor & Zafman

20070004182 - Methods and system for inhibiting immersion lithography defect formation: An immersion lithography system includes an immersion fluid holder for containing an immersion fluid. The system further includes a stage for positioning a resist-coated semiconductor wafer in the immersion fluid holder and a lens proximate to the immersion fluid holder and positionable for projecting an image through the immersion fluid... Agent: Haynes And Boone, LLP

20070004184 - Low dislocation density group iii nitride layers on silicon carbide substrates and methods of making the same: Group III nitride semiconductor device structures are provided that include a silicon carbide (SiC) substrate and a Group III nitride epitaxial layer above the SiC substrate. The Group III nitride epitaxial layer has a dislocation density of less than about 4×108 cm−2 and/or an isolation voltage of at least about... Agent: Summa, Allan & Additon, P.A.

20070004183 - Two-phase thermal method for preparation of cadmium sulfide quantum dots: The present invention relates to a two-phase thermal method for the preparation of cadmium sulfide quantum dots. In the method, cadmium carboxylate containing 2 to 18 carbon atoms or cadmium oxide is selected as cadmium source; thiourea or thioacetamide is selected as sulfur source; oleic acid or trioctylphosphine oxide (TOPO)... Agent: Fliesler Meyer, LLP

20070004185 - Methods of fabricating crystalline silicon film and thin film transistors: A method by which solid phase crystallization (SPC) thermal budget for crystallizing an undoped (or a lightly doped) amorphous Si (a-Si) is significantly reduced. First, a composite layer structure consisting of an undoped (or a lightly doped) a-Si layer and a heavily doped (either p-type or n-type) a-Si layer is... Agent: Brown & Michaels, PC 400 M & T Bank Building

20070004186 - Film forming method: A film forming method is provided for forming a thin film including a metal on a substrate by alternately supplying the substrate with a film forming material including the metal and a reducing gas. At least a part of the film forming material is dissociated or decomposed in vapor phase... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070004187 - Method of forming self-aligned contacts and local interconnects: A method of forming a plurality of self-aligned contacts of a drain region and local interconnect openings of a source region of a semiconductor device is disclosed. A plurality of gate-structures are formed on the drain and source regions of a semiconductor substrate. Sidewall spacers then are formed around the... Agent: Baker & Mckenzie LLP Patent Department

20070004188 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: forming a sacrificial layer over a semiconductor substrate; patterning the sacrificial layer and the substrate to make openings; forming a conductive layer partially buried in the openings to form a gate; and removing the patterned sacrificial layer.... Agent: Blakely Sokoloff Taylor & Zafman

20070004189 - Manufacturing method of semiconductor device: The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070004190 - Multi-step etch for metal bump formation: The present invention uses a two step plasma etch process to create a via contact with an integral bump. After the via and bump have been plated, the semiconductor substrate is planarized to remove the excess metal, using the semiconductor substrate as a planar stop. The bulk silicon substrate surrounding... Agent: Intel/blakely

20070004191 - Novel techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers: A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on... Agent: Lsi Logic Corporation

20070004192 - Metal interconnection of a semiconductor device and method of fabricating the same: Disclosed herein is a metal interconnection structure of a semiconductor device, comprising lower metal interconnection layers disposed on a semiconductor substrate, a buffer layer made of a metal oxide disposed thereon, an intermetallic dielectric layer made of a low-k material disposed on the buffer layer of the metal oxide, and... Agent: Marshall, Gerstein & Borun LLP

20070004194 - Method for fabricating semiconductor device with deep opening: A method for fabricating a semiconductor device with a deep opening is provided. The method includes: forming an insulation layer on a substrate; selectively etching the insulation layer to form first openings; enlarging areas of the first openings; forming anti-bowing spacers on sidewalls of the enlarged first openings; and etching... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070004193 - Method for reworking low-k dual damascene photo resist: A new method of forming a dual damascene structure involves forming a via-level precursor structure on a substrate and spin coating an oxide protective layer over the bottom anti-reflective coating, which is the last layer of the via-level precursor structure. A trench-level photoresist layer is deposited over the oxide protective... Agent: Duane Morris, LLPIPDepartment

20070004195 - Plate-type fluorescent lamp and display device having the same: An exemplary embodiment of a plate-type fluorescent lamp and a display device having the same includes an upper glass substrate; a lower glass substrate adhering opposite to the upper glass substrate; electrodes formed on external surfaces of the upper glass substrate and the lower glass substrate; and a dielectric layer... Agent: Cantor Colburn, LLP

20070004196 - Method for forming storage node contact in semiconductor device using nitride-based hard mask: A method for forming a storage node contact in a semiconductor device using a nitride-based hard mask is provided. The method includes: forming an inter-layer oxide layer on a substrate; forming a hard mask containing a nitride material on the inter-layer oxide layer; forming a mask pattern on the hard... Agent: Blakely Sokoloff Taylor & Zafman

20070004197 - Methods for creating electrophoretically insulated vias in semiconductive substrates: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed... Agent: Trask Britt

20070004198 - Shielded capacitor structure: A method and apparatus if provided for shielding a capacitor structure formed in a semiconductor device. In a capacitor formed in an integrated circuit, one or more shields are disposed around layers of conductive strips to shield the capacitor. The shields confine the electric fields between the limits of the... Agent: Johnson & Associates

20070004199 - Method of making a contact structure: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers... Agent: Trask Britt

20070004200 - Selective activation of aluminum, copper, and tungsten structures: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure... Agent: Trask Britt

20070004201 - Process for electroless copper deposition: Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form... Agent: Patterson & Sheridan, LLP

20070004202 - Semiconductor device and manufacturing method of the same: The manufacturing method of the present invention includes steps of selectively forming a photocatalyst material or a material including an amino group by discharging a composition including the photocatalyst material or the material including an amino group; immersing the photocatalyst material or the material including an amino group in a... Agent: Nixon Peabody, LLP

20070004204 - Method for forming insulation film: A method for forming an insulation film having filling property on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma... Agent: Knobbe Martens Olson & Bear LLP

20070004203 - Technique for forming nickel silicide by depositing nickel from a gaseous precursor: Nickel silicide is formed on the basis of a gaseous precursor, such as nickel tetra carbonyl, wherein the equilibrium of the decomposition of this gas may be controlled to obtain a highly selective nickel silicide formation rate. Moreover, any etch step for removing excess nickel may be avoided, since only... Agent: Williams, Morgan & Amerson

20070004205 - Eliminating metal-rich silicides using an amorphous ni alloy silicide structure: The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation... Agent: Scully Scott Murphy & Presser, PC

20070004206 - Improved hdp-based ild capping layer: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound... Agent: Howard M Cohn Patent Attorney LLC

20070004207 - Full backside etching for pressure sensing silicon: The formation of a semiconductor sensing device is disclosed, where the device can be used to sense pressure, for example. The device is formed by etching the entire backside of a semiconductor substrate or wafer. This streamlines the fabrication process by omitting a number of steps that would otherwise be... Agent: Texas Instruments Incorporated

20070004208 - Plasma etching apparatus and plasma etching method: The plasma processing apparatus is provided with a chamber comprising a dielectric wall at the position opposing an object to be processed. A flat coil arranged exterior of the dielectric wall creates an induction magnetic field for generating the plasma. A plate-shaped electrode capable of functioning as a Faraday shield... Agent: Mcdermott Will & Emery LLP

20070004211 - Methods of fabricating a semiconductor substrate for reducing wafer warpage: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least... Agent: Myers Bigel Sibley & Sajovec

20070004210 - Polishing composition and polishing method: t

20070004209 - Slurry for chemical mechanical polishing of aluminum: Described herein are embodiments of a slurry used for the chemical mechanical polishing a substrate that includes aluminum or an aluminum alloy features having a width of less than 1 um. The slurry includes a precipitated silica abrasive having a diameter of less than or equal to 100 nm and... Agent: Blakely Sokoloff Taylor & Zafman

20070004212 - Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device: A method for manufacturing a semiconductor substrate comprises, forming a first semiconductor layer on a part of a surface of a semiconductor substrate, implanting a speed improvement factor to improve an etching speed and a diffusion inhibitor to inhibit diffusion of the speed improvement factor into the first semiconductor layer,... Agent: Edwards & Angell, LLP

20070004213 - Method for fabricating semiconductor device with gate: A method for fabricating a semiconductor device with a gate is provided. The method includes: forming a gate insulation layer over a substrate; sequentially forming a polysilicon layer, a silicide layer and a hard mask layer over the gate insulation layer; selectively patterning the hard mask layer; etching the silicide... Agent: Blakely Sokoloff Taylor & Zafman

20070004214 - Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics: By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the... Agent: Williams, Morgan & Amerson

20070004215 - Dry etching methods: A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (referred to collectively as “slots”) in the substrates. The process includes applying a first layer to a first surface of substrate to provide an etch mask material layer on the first... Agent: Lexmark International, Inc. Intellectual Property Law Department

20070004216 - Formation of assemblies with a diamond heat spreader: Electronic assemblies and methods for forming assemblies are described. One method of forming a semiconductor device includes providing a support substrate and forming a diamond layer on the support substrate. The diamond layer is detached from the support substrate and diced into a plurality of diamond heat spreader bodies. A... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20070004217 - System and method for critical dimension reduction and pitch reduction: A method of forming a feature includes forming a mask of a first material on an underlying layer, the mask having an incorrect profile. The profile of the mask is corrected and a feature is formed in the underlying layer. A system for forming a feature is also disclosed.... Agent: Martine Penilla & Gencarella, LLP

20070004218 - Method of cleaning a semiconductor device and method of manufacturing a semiconductor device using the same: Example embodiments of the present invention relate to a method of cleaning a semiconductor device and a method of manufacturing a semiconductor device using the same. Other example embodiments of the present invention relate to a method of cleaning a semiconductor device by removing a residual organic compound and a... Agent: Harness, Dickey & Pierce, P.L.C

20070004219 - Semiconductor device fabrication methods employing substantially planar buffer material layers to improve the planarity of subsequent planarazation processes: A method for fabricating a semiconductor device structure includes applying a stress buffer material onto a semiconductor device structure and spreading the stress buffer material. When the stress buffer material is spread, it substantially fills recesses formed in a surface of the semiconductor device structure and imparts the stress buffer... Agent: Trask Britt, P.C.

20070004220 - Method for manufacturing flat substrates: For avoiding the metallic inner surface of a PECVD reactor to influence thickness uniformity and quality uniformity of a μc-Si layer (19) deposited on a large-surface substrate, (15) before each substrate is single treated at least parts of the addressed wall are precoated with a dielectric layer (13).... Agent: Pearne & Gordon LLP

20070004221 - Methods for forming material layers with substantially planar surfaces on semiconductor device structures: Methods for partially or substantially filling recesses (e.g., capacitor containers, shallow trenches for formation of shallow trench isolation (STI) structures, etc.) That communicate with a surface of the semiconductor device structure include applying material to a surface of the semiconductor device structure and spreading the material. The thickness of the... Agent: Trask Britt, P.C.

20070004222 - Fabrication of aligned nanowire lattices: Methodologies associated with fabricating aligned nanowire lattices are described. One exemplary method embodiment includes providing a twist wafer bonded thin single crystal semiconductor film and a bulk single crystal substrate of the same material. Periodic non-uniform elastic strains present on the surface of the film control the positions where nanocrystals... Agent: Hewlett Packard Company

20070004223 - In-line processing for forming a silicon nitride film: A process for manufacturing semiconductor devices in an in-line processing includes the steps of: forming a silicon nitride film on a semiconductor wafer by nitrization in a reactor chamber having an inner pressure at a specific pressure; reducing the inner pressure from the specific pressure; raising the inner pressure up... Agent: Mcginn Intellectual Property Law Group, PLLC

20070004225 - Low-temperature catalyzed formation of segmented nanowire of dielectric material: The present invention discloses a method of forming a segmented nanowire including: providing a substrate; pre-cleaning the substrate; pre-treating the substrate; forming and placing a catalyst over the substrate; and forming the segmented nanowire over the catalyst with recurring pulses of plasma-enhanced chemical vapor deposition (PECVD) of a dielectric material.... Agent: Intel Corporation C/o Intellevate, LLC

20070004224 - Methods for forming dielectrics and metal electrodes: A method for forming a semiconductor structure, the method including forming in a processing chamber a dielectric layer over a substrate; and subsequently forming, in the same processing chamber and without removing the substrate therefrom, an electrode layer directly over and in contact with the dielectric layer.... Agent: Goodwin Procter LLP Patent Administrator

20070004227 - Semiconductor processing methods: In one aspect, the invention encompasses a semiconductor processing method. A layer of material is formed over a semiconductive wafer substrate. Some portions of the layer are exposed to energy while other portions are not exposed. The exposure to energy alters physical properties of the exposed portions relative to the... Agent: Wells St. John P.s.

20070004226 - Strain control of epitaxial oxide films using virtual substrates: A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the... Agent: Sharp Laboratories Of America, Inc

20070004229 - Lamination of organic semiconductors: Low temperature, ambient pressure processes are desired for fabrication of transistors on flexible polymer substrates. Lamination of semiconductors is such a process. The semiconductor is deposited on a donor substrate. The donor is positioned over a receiver substrate, which may be patterned with additional transistor elements. The semiconductor is transferred... Agent: E I Du Pont De Nemours And Company Legal Patent Records Center

20070004228 - Polyamide acid-containing composition for forming antireflective film: There is provided an anti-reflective coating forming composition for use in a lithography and for forming an anti-reflective coating that can be developed with an alkaline developer for photoresist, and a method for forming photoresist pattern by use of the anti-reflective coating forming composition. Concretely, the composition comprises a polyamic... Agent: Oliff & Berridge, PLC

20070004230 - Post polish anneal of atomic layer deposition barrier layers: A method for forming a semiconductor device is disclosed wherein atomic layer deposition (ALD) precursor species and/or by-product absorbed by an ILD are outgassed and/or neutralized prior to subsequently patterning the semiconductor device, thereby improving the ability to accurately define subsequently formed interconnect structures in the ILD.... Agent: Blakely Sokoloff Taylor & Zafman

20070004232 - Laser thermal processing chuck with a thermal compensating heater module: Chuck methods and apparatus for supporting a semiconductor substrate and maintaining it at a substantially constant background temperature even when subject to a spatially and temporally varying thermal load. Chuck includes a thermal compensating heater module having a sealed chamber containing heater elements, a wick, and an alkali metal liquid/vapor.... Agent: Allston L. Jones Peters, Verny, Jones & Schmitt, L.L.P.

20070004233 - Manufacturing method of semiconductor device: A first layer (an insulating layer), a second layer (a metal layer), and a third layer (an insulating layer) are formed over a substrate. Then, a fourth layer including a semiconductor element is formed over the third layer. After applying an organic resin film covering the fourth layer, laser light... Agent: Fish & Richardson P.C.

20070004231 - Method for controlling structure of nano-scale substance, and method for preparing low dimensional quantum structure having nano-scale using the method for controlling structure: A method for controlling a structure of a nano-scale substance, which comprises irradiating a mixture of low-dimensional quantum structures having a nano-scale with an electromagnetic wave in an oxygen atmosphere, to thereby selectively oxidize a low-dimensional quantum structure having a density of states resonating with the electromagnetic wave used for... Agent: Harness, Dickey & Pierce, P.L.C

20070004234 - Fluids for immersion lithography systems: Fluids for use in immersion lithography systems are disclosed. A resistivity-altering substance is introduced into a fluid, making it more conductive. The fluid is then disposed between an immersion head of a projection lens system and a semiconductor wafer during an exposure process. Because the fluid is conductive, electrostatic energy... Agent: Slater & Matsil LLP