Semiconductor device manufacturing: process inventions 12/06

20060292704 - Magnetostactic wave device based on thin metal films, method for making same and application to devices for processing microwave signals: The integrated magnetostatic wave device comprises a substrate (1), a conductive ferromagnetic thin film (2) of thickness lying in the range about 250 nm to 450 nm and preferably being equal to about 300 nm, said thin film (2) being deposited on said substrate (1), a first transducer antenna (10)... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20060292705 - Method and process for fabricating read sensors for read-write heads in mass storage devices: Method and process for fabricating a device structure for a read head of a mass storage device. A polish stop layer formed of a relatively hard material, such as diamond-like carbon, is positioned between a layer stack and a resist mask used to mask regions of the layer stack during... Agent: Wood, Herron & Evans, LLP

20060292706 - Method of manufacturing substrate having periodically poled regions: A current is observed while applying a gradually increasing voltage between electrodes formed front and rear surfaces of a substrate, and then poled regions are formed by applying a DC voltage, which has a voltage value at that time or another voltage value obtained by adding a predetermined value to... Agent: Rankin, Hill, Porter & Clark LLP

20060292707 - Healing detrimental bonds in deposited materials: A method for healing detrimental bonds in deposited materials, for example porous, low-k dielectric materials, including oxydatively processing a deposited material, processing the deposited material with a trialkyl group III compound, and processing in the presence of an alcohol. Also included in embodiments of the invention are materials with bonds... Agent: Blakely Sokoloff Taylor & Zafman

20060292708 - Circuit arrangement, redox recycling sensor, sensor assembly and a method for processing a current signal provided by a sensor electrode: A circuit arrangement has a sensor electrode, a control circuit which is coupled to the sensor electrode via an input, and a current source which is coupled via a control input to a control output of the control circuit. The current source can be controlled by the control circuit. The... Agent: Brinks Hofer Gilson & Lione Infineon

20060292711 - Mechanical integrity evaluation of low-k devices with bump shear: A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104).... Agent: Hamilton & Terrile, LLP

20060292709 - Method for fabricatiing three-dimensional microstructure by fib-cvd and drawing system for three-dimensional microstruture: There are provided a fabrication method of a nanostructure by FIB-CVD which enables fabrication of a three-dimensional nanostructure, especially that without a support such as a terrace structure or a hollow structure, and a drawing system thereof. The three-dimensional nanostructure is fabricated by controlling a focused ion beam to determine... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292712 - Process for the detection of a malfunction in a device for wire sawing and device for practicing said process: The invention relates to a process for the detection of malfunctions, in particular the detection of breakage of a wire in a wire sawing device. The process consists in applying an alternating signal to the layer of wires (4) of the sawing device and measuring the variations of voltage or... Agent: Young & Thompson

20060292713 - Semiconductor integrated circuit device: To provide a semiconductor device which can be down-sized and integrated to a high degree. A semiconductor device including a rewiring mixedly includes an input/output (I/O) cell connected to a probing pad; and another input/output (I/O) cell having no probing pad.... Agent: Mcdermott Will & Emery LLP

20060292710 - Sensor and method for detecting electric contact degradation: A probe cell monitors conditions within electrical power transmission and switchgear apparatus to detect degradation of stressed components. The probe cell is a hardware simulation of components of a specific unit of electrical power apparatus, including electrodes between which an electric field gradient is established. The probe cell electrodes accumulate... Agent: Baker & Hostetler LLP

20060292714 - Semiconductor manufacturing apparatus and wafer processing method: A semiconductor manufacturing apparatus and a wafer processing method are disclosed. The semiconductor manufacturing apparatus, comprises a rotatable device for supporting a wafer. A sensor for irradiating a laser beam onto a surface of the wafer and a detector including a plurality of modules for detecting the laser beam reflected... Agent: Marger Johnson & Mccollom, P.C.

20060292715 - Method for fabricating a metal-insulator-metal capacitor: A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292716 - Use selective growth metallization to improve electrical connection between carbon nanotubes and electrodes: Disclosed is a method of making a CNT device such as a memory switch, a field emission display, interconnect wiring, etc. The method includes steps of providing CNTs in contact with an electrode and selectively growing or depositing a layer of metal on top of the CNTs and the electrode.... Agent: Lsi Logic Corporation

20060292717 - Mounting and adhesive layer for semiconductor components: An assembly and adhesive layer for semiconductor components is arranged between a silicon support (submount) and an electronic functional element for the formation of an electrically-conducting connection between the silicon support and the functional element. The assembly and adhesive layer are arranged on the support. The assembly and adhesive layer... Agent: Slater & Matsil LLP

20060292719 - Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.... Agent: Goodwin Procter LLP Patent Administrator

20060292718 - Method of producing nitride layer and method of fabricating vertical structure nitride semiconductor light emitting device: The present invention provides methods for manufacturing a nitride layer and a vertical nitride semiconductor light emitting device. In manufacturing the nitride layer according to the invention, a sapphire substrate is prepared. A buffer layer made of a material having a melting point and a thermal conductivity higher than those... Agent: Mcdermott Will & Emery LLP

20060292720 - Semiconductor laser device: When a laser irradiation direction is assumed as a forward direction, a front end surface of a die pad (104), a front end surface of a resin mold member (106), and a front end surface of a semiconductor laser element (101) are sequentially disposed in this order from the front... Agent: Steptoe & Johnson LLP

20060292721 - Fabricating method for flat display device: A fabricating method of a flat panel display device can reduce manufacturing costs of the flat panel display device. A fabricating method of a flat panel display device includes providing a conductive nanopowder thin film material having a first conductive nanopowder and a second conductive nanopowder, spreading the conductive nanopowder... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20060292722 - Flexible interconnect structures for electrical devices and light sources incorporating the same: A flexible interconnect structure allows for rapid dissipation of heat generated from an electrical device that includes light-emitting elements, such as light-emitting diodes (“LEDs”) and/or laser diodes. The flexible interconnect structure comprises: (1) at least one flexible dielectric film on which circuit traces and, optionally, electrical circuit components are formed... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060292725 - Method for manufacturing device having optical semiconductor element: The invention provides a method of forming a device having an optical semiconductor element by bonding a cover body, which can cover the optical semiconductor element, to a head portion having the optical semiconductor element. The method comprises the steps of: a short circuit step of shorting terminals of the... Agent: Nixon & Vanderhye, PC

20060292724 - Method of manufacturing organic el display: A method of manufacturing a plurality of organic EL displays, by sealing and cutting an organic EL substrate, controlling the adhesion width and cutting the glass substrate without extending the cutting position. An organic EL substrate, and a sealing glass substrate with recesses opposing each laminate of the organic EL... Agent: Rabin & Berdo, PC

20060292723 - Plasma display device: A plasma display device includes a plasma display 1, a chassis 2 having conductivity that supports the plasma display 1, a tuner circuit 11, a scan driver 12, a sustaining driver 13 and so forth used to display a video on the plasma display 1, a back cover 4 that... Agent: Wenderoth, Lind & Ponack L.L.P.

20060292726 - Method of manufacturing a semiconductor device: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer... Agent: Nixon Peabody, LLP

20060292728 - Nitride crystal, nitride crystal substrate, epilayer-containing nitride crystal substrate, semiconductor device and method of manufacturing the same: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal... Agent: Mcdermott Will & Emery LLP

20060292727 - Photomask plasma etching apparatus, etching method, and photomask forming method: A photomask plasma etching apparatus includes an electrode to generate plasma, and an electrical capacity control unit configured to control an electrical capacity between the electrode and a mask substrate to be held on the electrode.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292729 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate, an actuator provided above the semiconductor substrate to move upwardly, a first electrode layer which is moved by the actuator, and a cap portion provided above the first electrode layer and including a second electrode layer.... Agent: Foley And Lardner LLP Suite 500

20060292731 - Cmos image sensor and manufacturing method thereof: A CMOS image sensor with improved performance through improved uniformity of micro-lens size and a method for manufacturing the same are provided. The CMOS image sensor includes photodiodes formed on a semiconductor substrate for producing charges consistent with a quantity of incident light, an interlayer insulation layer formed on an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292730 - Method and device for cmos image sensing with separate source formation: A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is... Agent: Townsend And Townsend And Crew, LLP

20060292732 - Methods of flip-chip image sensor package fabrication: The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete... Agent: Trask Britt

20060292734 - Method for manufacturing cmos image sensor: Disclosed is a CMOS image sensor and a method for manufacturing a CMOS image sensor. The method includes: (a) forming a resist film on a semiconductor substrate comprising a light sensing part, a protecting layer over the light sensing part, and an exposed bonding pad; (b) forming a color filter... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060292733 - Method of manufacturing cmos image sensor: Provided is a manufacturing method of a CMOS image sensor. The method includes forming an interlayer insulating layer, a color filter layer, and a planarizing layer. A first photoresist is applied on the planarizing layer, and patterning of the first photoresist is performed using a first mask to form a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292735 - Methods for creating gapless inner microlenses, arrays of microlenses, and imagers having same: Methods of fabricating a microlens and/or array of microlenses used to focus light on photosensors, by forming a protective coating over a microlenses precursor material, and etching the protective coating and microlens precursor material to obtain a predetermined shape.... Agent: Dickstein Shapiro LLP

20060292736 - Architecture for high efficiency polymer photovoltaic cells using an optical spacer: High efficiency polymer photovoltaic cells have been fabricated using an optical spacer between the active layer and the electron-collecting electrode. Such cells exhibit approximately 50% enhancement in power conversion efficiency. The spacer layer increases the efficiency by modifying the spatial distribution of the light intensity inside the device, thereby creating... Agent: Foley & Lardner LLP

20060292738 - Flex on suspension with a heat-conducting protective layer for reflowing solder interconnects: A FOS is provided for electrically connecting a data transfer head with a PCCA. The FOS comprises a polymeric layer supporting an electrical trace. The electrical trace comprises an uninsulated pad surface configured for electrically engaging a solder interconnect of the PCCA. The polymeric layer comprises a continuous portion covering... Agent: Derek J. Berger Seagate Technology LLC

20060292737 - Grid array connection device and method: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292741 - Heat-dissipating semiconductor package and fabrication method thereof: A heat-dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a substrate. A heat-dissipating structure includes a heat sink and at least one supporting portion, wherein the supporting portion is attached to the substrate at a position outside a predetermined... Agent: Birch Stewart Kolasch & Birch

20060292740 - High temperature packaging for electronic components, modules and assemblies: A high temperature semiconductor packaging, a method for making the same packaging are providing. The packaging comprises a mounting platform, a semiconductor die positioned above the platform and a layer of high temperature passivation coating.... Agent: Brown Raysman Millstein Felder & Steiner, LLP

20060292742 - Manufacturing method for packaged semiconductor device: A semiconductor device in which moisture penetration into the package interior is suppressed, comprising a rewiring layer formed by plating, with improved reliability of electrical characteristics. On the main surface of a semiconductor chip comprising circuit elements and formed on a wafer, a passivation film opposing the circuit elements is... Agent: Rabin & Berdo, PC

20060292739 - Method and apparatus to boost high-speed i/o signal performance using semi-interleaved transmitter/receiver pairs at silicon die bump and package layout interfaces: A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where transmitters and receivers of the two circuit patterns are positioned so that the two transmitters are adjacent or so that the two receivers... Agent: Blakely Sokoloff Taylor & Zafman

20060292743 - Stacked die in die bga package: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20060292744 - Three dimensional device integration method and integrated device: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292745 - Stacked die in die bga package: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20060292746 - Stacked die in die bga package: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20060292748 - Package having bond-sealed underbump: A package for containing microelectromechanical devices includes a first substrate wafer, and a second substrate wafer made of an optical quality material. An underbump is interposed between the first and second substrate wafers. The underbump is composed of a standoff region and a localized bond region. The first and second... Agent: Hewlett-packard Company Intellectual Property Administration

20060292749 - Photochromic substrate container: A semiconductor wafer, substrate, or reticle storage or shipping device that includes a photochromic indicator of exposure to undesired electromagnetic radiation. The present invention includes the incorporation of a photochromic material into the plastic used to fabricate at least a portion of a semiconductor wafer, disk, or reticle shipping or... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20060292747 - Top-surface-mount power light emitter with integral heat sink: A light emitting apparatus is disclosed. The light emitting apparatus includes a substrate, a heat sink, a dielectric layer, conductive traces, a reflector, and at least one photonic device. The substrate has a top surface and a bottom surface, a portion of the top surface defining a mounting pad. The... Agent: Harness, Dickey & Pierce, P.L.C

20060292750 - Standoffs for centralizing internals in packaging process: A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the semiconductor device comprises a pair of semiconductor dies mounted on opposing sides of a flexible tape substrate, the outer surfaces of the dies having one or more standoffs... Agent: Whyte Hirschboeck Dudek S.c.

20060292751 - Technique for manufacturing an overmolded electronic assembly: A technique for manufacturing an electronic assembly uses a mold that has a first mold portion and a second mold portion. The first mold portion includes a plurality of spaced mold pins extending from an inner surface. A cavity of the first and second mold portions provides a mold cavity,... Agent: Delphi Technologies, Inc.

20060292752 - Method for fabricating board on chip (boc) semiconductor package with circuit side polymer layer: A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the substrate in a... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20060292753 - Semiconductor device and method of manufacturing a semiconductor device: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface... Agent: Texas Instruments Incorporated

20060292754 - Antifuse element and method of manufacture: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060292755 - Tunable antifuse element and method of manufacture: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060292759 - Apparatus for annealing, method for annealing, and method for manufacturing a semiconductor device: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292756 - Flip chip die assembly using thin flexible substrates: Apparatus and methods for flattening thin substrate surfaces by stretching thin flexible substrates to which ICs can be bonded. Various embodiments beneficially maintain the substrate flatness during the assembly process through singulation. According to one embodiment, the use of a window frame type component carrier allows processing of thin laminates... Agent: Guidant Patent Docketing Faegre & Benson, LLP

20060292760 - Method of fabricating a thin film transistor for an array panel: A method for making a thin film transistor, TFT, (306) on a substrate includes a photolithographic process step of patterning three layers of materials to form a TFT (306) and to form a bridging structure (308) crossing over a TFT gate bus-line conductor (202) at a cross over region; followed... Agent: Mark J. Marcelli Duane Morris LLP

20060292758 - Pyrimidopyrimidine derivatives, organic thin film transistors using pyrimidopyrimidine derivatives and method for fabricating the same: Pyrimidopyrimidine derivatives, organic thin film transistors using pyrimidopyrimidine derivatives and method for fabricating the same are provided. Pyrimidopyrimidine derivative structures, along with example syntheses, are provided. The pyrimidopyrimidine derivatives may be pyrimidopyrimidine oligothiophene derivatives in which an oligothiophene having p-type semiconductor characteristics may be bonded to a pyrimidopyrimidine having n-type... Agent: Harness, Dickey & Pierce, P.L.C

20060292757 - Thin-film transistor (tft) for driving organic light-emitting diode (oled) and method for manufacturing the same: A thin-film transistor (TFT) and a method for manufacturing the thin-film transistor using a color filter as a dielectric layer so as to drive an organic light-emitting diode. The thin-film transistor comprises: a substrate; a first poly-silicon mesa formed on the substrate; an insulating layer formed on the substrate and... Agent: Bruce H. Troxell Suite 1404

20060292761 - Method for fabricating semiconductor device: [Problem] To provide technology that allows, by controlling a crystal orientation, forming a crystalline semiconductor film aligned in orientation and obtaining a crystalline semiconductor film whose impurity concentration is reduced. [Means, for Resolution] On an insulating surface, a first semiconductor region made of an amorphous semiconductor is formed, a continuous... Agent: Nixon Peabody, LLP

20060292762 - Replacement gate field effect transistor with germanium or sige channel and manufacturing method for same using gas-cluster ion irradiation: A self-aligned MISFET transistor (500H) on a silicon substrate (502), but having a graded SiGe channel or a Ge channel. The channel (526) is formed using gas-cluster ion beam (524) irradiation and provides higher channel mobility than conventional silicon channel MISFETs. A manufacturing method for such a transistor is based... Agent: Burns & Levinson, LLP (formerly Perkins Smith & Cohen LLP)

20060292763 - Methods of fabricating thin film transistor and organic light emitting display device using the same: Methods of fabricating a TFT and an OLED using the same are provided. The method of fabricating a CMOS TFT includes: preparing a substrate having first and second TFT regions; forming a gate electrode on the substrate; forming a gate insulating layer on the entire surface of the substrate including... Agent: Knobbe Martens Olson & Bear LLP

20060292764 - Method of manufacturing a vertical mos transistor: In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a semiconductor substrate. An intermediate insulating film is deposited over a main surface of the semiconductor substrate... Agent: Bruce L. Adams, Esq. Suite 1231

20060292765 - Method for making a finfet including a superlattice: A method for making a semiconductor device may include forming at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite sides of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20060292766 - Storage devices formed on partially isolated semiconductor substrate islands: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292767 - Storage devices formed on partially isolated semiconductor substrate islands: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292768 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a gate insulating layer, a gate electrode, an oxide layer, and sidewalls. The gate insulating layer is formed on the substrate. The gate electrode includes an upper layer and a lower layer stacked on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292769 - Multilayered structure forming method: A multilayered structure forming method includes disposing a dummy post on a first insulating pattern as a first inkjet process, disposing a second insulating pattern on the first insulating pattern as a second inkjet process so as to allow the second insulating pattern to surround a side surface of the... Agent: Harness, Dickey & Pierce, P.L.C

20060292770 - Cmos on soi substrates with hybrid crystal orientations: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS... Agent: Slater & Matsil, L.L.P.

20060292771 - High voltage depletion fet employing a channel stopping implant: A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop regions and n-type surface channel regions are formed. A... Agent: Texas Instruments Incorporated

20060292772 - Dense pitch bulk finfet process by selective epi and etch: Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20060292780 - Field-effect transistor and method for producing a field-effect transistor: Field-effect transistor is disclosed that includes a gate oxide, a polycrystalline layer applied on the gate oxide, and at least one spacer of polycrystalline silicon, wherein the gate oxide has a first thickness in a first region beneath the polycrystalline silicon layer and a second thickness in a second region... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20060292781 - Finfets, nonvolatile memory devices including finfets, and methods of forming the same: A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected to the device... Agent: Myers Bigel Sibley & Sajovec

20060292777 - Method for making electronic devices using metal oxide nanoparticles: A method of making a thin film transistor comprises (a) solution depositing a dispersion comprising semiconducting metal oxide nanoparticles onto a substrate, (b) sintering the nanoparticles to form a semiconductor layer, and (c) optionally subjecting the resulting semiconductor layer to post-deposition processing.... Agent: 3m Innovative Properties Company

20060292774 - Method for preventing metal line bridging in a semiconductor device: A method for forming a semiconductor device includes providing a substrate, providing aluminum metal lines on the substrate, forming a barrier layer over the aluminum metal lines, and forming a silicon-rich dielectric layer over the barrier layer. An inter-metal dielectric (IMD) layer may be formed to cover at least a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292773 - Method of making a metal gate semiconductor device: A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to form a sidewall spacer... Agent: Freescale Semiconductor, Inc. Law Department

20060292775 - Method of manufacturing dram capable of avoiding bit line leakage: A method to make DRAM capable of avoiding bit line leakage is provided. The method comprise the steps of forming transistors on substrate, forming an insulating layer to cover the substrate and the transistors, forming a poly-silicon layer over the insulating layer, forming contact holes in the poly-silicon layer and... Agent: Birch Stewart Kolasch & Birch

20060292778 - Semiconductor device and method for manufacturing the same: A first resist mask and a second resist mask used for forming a gate electrode for a p-channel TFT and a gate electrode for an n-channel TFT are left, and a third resist mask is formed afterwards over a first area where one of the p-channel TFT and the n-channel... Agent: Nixon Peabody, LLP

20060292776 - Strained field effect transistors: An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer.... Agent: Trop Pruner & Hu, PC

20060292779 - Structure and method for making strained channel field effect transistor using sacrificial spacer: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides... Agent: International Business Machines Corporation Dept. 18g

20060292783 - Cmos transistor and method of manufacturing the same: A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a... Agent: Volentine Francos, & Whitt PLLC

20060292782 - Semiconductor device and method for manufacturing the same: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060292784 - Methods of forming integrated circuit devices including memory cell gates and high voltage transistor gates using plasma re-oxidation: A method of forming an integrated circuit device can include forming a plurality of stacked cell gates in a memory cell region of a semiconductor substrate and a plurality of high-voltage transistor gates in a peripheral circuit region of the semiconductor substrate. The semiconductor substrate including both the plurality of... Agent: Myers Bigel Sibley & Sajovec

20060292785 - Cu-metalized compound semiconductor device: The present invention is a compound semiconductor device characterized in that it is Cu-metalized to improved the reliability of the device and to greatly reduce the cost of production.... Agent: Troxell Law Office PLLC

20060292786 - Semiconductor constructions, and methods of forming semiconductor constructions: The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion.... Agent: Wells St. John P.s.

20060292787 - Semiconductor processing methods, and semiconductor constructions: The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region... Agent: Wells St. John P.s.

20060292788 - Systems and methods of forming refractory metal nitride layers using disilazanes: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound.... Agent: Mueting, Raasch & Gebhardt, P.A.

20060292789 - Structure and method for collar self-aligned to buried plate: A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.... Agent: International Business Machines Corporation Dept. 18g

20060292790 - Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50... Agent: Texas Instruments Incorporated

20060292791 - Semiconductor integrated circuit device and method for manufacturing the same: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060292796 - Flash memory device and method for manufacturing the same: A flash memory device incorporating: a semiconductor substrate having an active region and a field region defined therein; a device isolation layer formed in the field region of the substrate; a floating gate having an edge portion overlapping the device isolation layer, the overlapped portion being etched back a depth... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292798 - Flash memory device and method for manufacturing the same: A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060292792 - Method for the manufacture of a non-volatile memory device and memory device thus obtained: The present invention relates to a method for processing of a non-volatile memory cell (50) which comprises a double gate stack and a single access gate. The method combines a way of processing an access gate with drain implant, separate from source implant, in a self-aligned manner. The method of... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20060292797 - Method of fabricating floating gate of flash memory device: A method of fabricating a floating gate of a flash memory device is provided. The method includes: forming a tunneling oxide layer on a substrate; forming a conductive thin layer on the tunneling oxide layer; applying a photoresist on the conductive thin layer; defining a floating gate region by patterning... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292795 - Method of manufacturing a flash memory device: In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled... Agent: Volentine Francos, & Whitt PLLC

20060292794 - Method of manufacturing dielectric film of flash memory device: A method of manufacturing a dielectric film of a flash memory device, including the steps of providing a semiconductor substrate having floating gates formed therein, performing an oxidization process in a decompression state to form a first oxide film of a thin film on the semiconductor substrate including the floating... Agent: Marshall, Gerstein & Borun LLP

20060292793 - Semiconductor processing methods: The invention includes methods in which common processing steps are utilized during fabrication of components of a memory array region of a semiconductor substrate and components of a peripheral region proximate the memory array region, and yet the components of the peripheral region are built for different performance characteristics than... Agent: Wells St. John P.s.

20060292799 - Memory embedded semiconductor device and method for fabricating the same: A memory embedded semiconductor device according to the present invention has a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate. The logic transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed... Agent: Mcdermott Will & Emery LLP

20060292800 - Ono formation of semiconductor memory device and method of fabricating the same: A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on... Agent: Rabin & Berdo, PC

20060292801 - Bit line of a semiconductor device and method for fabricating the same: A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film... Agent: Townsend And Townsend And Crew, LLP

20060292802 - Semiconductor device and method for forming the same: There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode... Agent: Myers Bigel Sibley & Sajovec

20060292803 - High voltage metal-oxide-semiconductor transistor devices and method of making the same: A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate... Agent: North America Intellectual Property Corporation

20060292804 - Nitride semiconductor light emitting diode and fabrication method thereof: The invention relates to a nitride semiconductor LED and a fabrication method thereof. In the LED, a first nitride semiconductor layer, an active region a second nitride semiconductor layer of a light emitting structure are formed in their order on a transparent substrate. A dielectric mirror layer is formed on... Agent: Lowe Hauptman Berner, LLP

20060292805 - Semiconductor device: A semiconductor device is provided, which includes a first main electrode region having an upper main surface and a lower main surface; a drift layer of a first conductivity type formed on the upper main surface of the first main electrode region; a base layer of a second conductivity type... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292806 - Semiconductor integrated circuit device: To improve a degree of integration and reliability of a semiconductor integrated circuit device. There are included third wire 14 arranged in the same layer as first wire 11 and second wire 12 and arranged in a direction intersecting with the first wire 11 and the second wire 12, first... Agent: Mcginn Intellectual Property Law Group, PLLC

20060292807 - Semiconductor device and method of fabricating the same: A semiconductor device incorporating an alloy layer formed on a substrate; a gate electrode, a source electrode, and a drain electrode formed on the alloy layer at predetermined intervals therebetween; a gate insulating layer formed on the gate electrode in a gate electrode region; a first conductive layer formed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292808 - Absorber layer for dsa processing: A method of processing a substrate comprising depositing a layer comprising amorphous carbon on the substrate and then laser annealing the substrate is provided. Optionally, the layer further comprises a dopant selected from the group consisting of nitrogen, boron, phosphorus, fluorine, and combinations thereof. In one aspect, the layer comprising... Agent: Patterson & Sheridan, LLP

20060292809 - Method for growth and optimization of heterojunction bipolar transistor film stacks by remote injection: A method, and a resulting device, for fabricating a heterojunction bipolar transistor (HBT). HBT devices have a high transconductance typical of bipolar devices and are additionally capable of high-power operation. To achieve the aforementioned characteristics, HBT devices are generally of the npn type, preferably with a thin, heavily doped base.... Agent: Schneck & Schneck

20060292813 - Electronic component and method for manufacturing the same: Electrode layers (1, 2) are arranged on both sides of a dielectric layer (3) facing each other so as to configure a capacitor. Lead electrodes (4, 5) are formed in the electrode layers (1, 2). A penetrating electrode (6) that is insulated from the electrode layers (1, 2) is formed.... Agent: Hamre, Schumann, Mueller & Larson P.C.

20060292812 - Integrated circuit devices including insulating support layers and related methods and structures: An integrated circuit device may include a substrate, a plurality of storage electrode landing pads on the substrate, and a plurality of storage electrodes. Each of the plurality of storage electrodes may be on a portion of a respective one of the plurality of storage electrode landing pads. In addition,... Agent: Myers Bigel Sibley & Sajovec

20060292811 - Method for forming a capacitor in a semiconductor and a capacitor using the same: Disclosed is a capacitor and method for forming a capacitor in a semiconductor. The method includes the steps of: (a forming a lower electrode pattern on a silicon semiconductor substrate; (b etching a portion of the lower electrode pattern to a predetermined depth to form a step in the lower... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060292810 - Method of manufacturing a capacitor: In methods of manufacturing capacitors, a first metal compound may be deposited on a substrate using first and second source gases. The first and the second source gases may be provided onto the substrate by a first flow rate ratio in which a deposition rate of the first metal compound... Agent: Harness, Dickey & Pierce, P.L.C

20060292814 - Methods of forming integrated circuitry: In one implementation, an opening within a capacitor electrode forming layer is formed over a substrate. A spacing layer is deposited over the capacitor electrode forming layer to within the opening over at least upper portions of sidewalls of the opening. The spacing layer is formed to be laterally thicker... Agent: Wells St. John P.s.

20060292815 - Mim capacitor in a semiconductor device and method therefor: A MIM capacitor is formed over one or more metal interconnect layers in a semiconductor device. The capacitor has a lower plate electrode and an upper plate electrode. An insulator is formed between the plate electrodes. Prior to forming the first plate electrode a first insulating layer is deposited over... Agent: Freescale Semiconductor, Inc. Law Department

20060292817 - Methods of processing semiconductor structures and methods of forming capacitors for semiconductor devices using the same: In a method of processing a semiconductor structure and a method of forming a capacitor for a semiconductor device using the same, a semiconductor structure may be cleaned using a cleaning solution having a surface tension lower than that of water. The semiconductor structure may be dried in an isopropyl... Agent: Harness, Dickey & Pierce, P.L.C

20060292816 - Semiconductor device and method for fabricating the same: A semiconductor device comprises: an insulating film formed over a semiconductor substrate and having a first recess; a plurality of capacitor elements each of which is composed of a capacitor lower electrode formed on wall and bottom portions of the first recess and having a second recess, a capacitor insulating... Agent: Mcdermott Will & Emery LLP

20060292818 - Method for making a semiconductor device having a semiconductor-on-insulator (soi) configuration and including a superlattice on a thin semiconductor layer: A method for making a semiconductor device may include forming an insulating layer on a substrate, and forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The method may further include forming a superlattice on the semiconductor layer on a side thereof opposite the... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20060292820 - Isolation layers for semiconductor devices including first and second sub-trenches and methods of forming the same: In a device isolation layer for a p-MOS transistor and a method of forming the same, a trench oxide layer having a first and a second sub-oxide layers is formed in a trench including a first and a second sub-trenches. The first and second sub-oxide layers are formed on side... Agent: Myers Bigel Sibley & Sajovec

20060292819 - Semiconductor device and method for fabricating a semiconductor device: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the... Agent: Blakely Sokoloff Taylor & Zafman

20060292821 - Method of etching silicon: Silicon (12) is etched through a mask (11) comprising a layer of organic resin material (such as novolac) through which openings (32) are formed in the areas to be etched. The layer of organic resin is first deposited over a free surface of the device to be etched. The openings... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20060292823 - Method and apparatus for bonding wafers: Embodiments of a method and apparatus for bonding wafers are disclosed. The bonded wafers may include self-passivating interconnects. Other embodiments are described and claimed.... Agent: Intel Corporation

20060292822 - Method for producing dislocation-free strained crystalline films: A method for forming dislocation-free strained silicon thin film includes the step of providing two curved silicon substrates. One substrate is curved by the presence of silicon dioxide on a back surface. The other substrate is curved by the presence of a silicon nitride layer. One of the substrates is... Agent: VistaIPLaw Group LLP

20060292824 - Methods for bonding and micro-electronic devices produced according to such methods: One inventive aspect is related to a method of bonding two elements. The method comprises producing on a first element a first micropattern, comprising a first metal layer. The method further comprises producing on a second element a second micropattern, comprising a second metal layer. The method further comprises applying... Agent: Knobbe Martens Olson & Bear LLP

20060292825 - Monitoring the reduction in thickness as material is removed from a wafer composite and test structure for monitoring removal of material: The aim of the invention is to create a simple monitoring or testing method for monitoring a reduction in thickness as material is removed from a bonded semiconductor wafer pair, which prevents failure effects as material is removed from wafers (polishing, grinding or lapping). In addition, the costs of the... Agent: Hunton & Williams LLP Intellectual Property Department

20060292826 - Wafer processing method: A method of processing a wafer having a device area where a plurality of devices are formed on the front surface and an extra area surrounding the device area and comprising electrodes which are formed in the device area, comprising: a reinforcement forming step for removing an area, which corresponds... Agent: Smith, Gambrell & Russell

20060292829 - Apparatus and method of wafer dicing: A wafer dicing method includes the following steps. First, the wafer is adhered on an adhesive material. Next, the adhesive material is disposed on a frame. Then, the frame is clamped by a fixture, for fixing the wafer. Afterwards, a roller rotates against the adhesive material, for applying a force... Agent: Bacon & Thomas, PLLC

20060292827 - Chemical die singulation technique: A method is provided for manufacturing a semiconductor device from a substrate (200) having an active surface (204) and a non-active surface (206). The method comprises depositing a backing material (104) onto the non-active surface of the substrate (206) in a pattern (500), the pattern (500) having at least a... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060292830 - Chip dicing: A semiconductor structure and method for chip dicing. The method includes (a) providing a semiconductor substrate and (b) forming first and second device regions in and at top of the substrate. The first and second device regions are separated by a semiconductor border region of the substrate. The method further... Agent: Schmeiser, Olsen & Watts

20060292832 - Method of working nitride semiconductor crystal: In a method of working a crystal, when a nitride semiconductor crystal is worked, voltage is applied between the nitride semiconductor crystal and a tool electrode to cause electrical discharge, so that the crystal is partially removed and worked by local heat generated by the electrical discharge.... Agent: Mcdermott Will & Emery LLP

20060292831 - Spacer die structure and method for attaching: A semiconductor spacer structure comprises in order a backgrinding tape layer, a spacer adhesive layer, a semiconductor spacer layer, an optional second spacer adhesive layer, a dicing tape layer. In a first method a spacer wafer having first and second sides, a backgrinding tape layer and a spacer adhesive layer... Agent: Haynes Beffel & Wolfeld LLP

20060292828 - Wafer and method of cutting the same: A method of cutting a wafer. First, the first substrate and the second substrate are provided. Next, several alignment marks are formed on the backside of the second substrate to form two reference coordinate axes. Then, the first substrate and the second substrate are assembled to form a wafer. The... Agent: Bacon & Thomas, PLLC

20060292833 - Substrate for forming semiconductor layer: A substrate for forming a semiconductor layer includes a plurality of linear convexes or grooves on a surface of the substrate by crystal growth. The plurality of linear convexes or grooves are formed along a direction of a cleavage plane of the semiconductor layer.... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292835 - Element fabrication substrate: A substrate used for fabricating devices thereon includes an insulating film, and a monocrystal Ge thin layer formed on the insulating film in contact therewith, the monocrystal Ge thin layer having a thickness not more than 6 nm. The monocrystal Ge thin layer has a thickness not less than 2... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292834 - High performance transistors with hybrid crystal orientations: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the... Agent: Slater & Matsil, L.L.P.

20060292836 - Manufacturing method of polysilicon: A manufacturing method of polysilicon is provided. First, a substrate is provided, and an amorphous silicon layer is formed on the substrate. Then, a buffer layer is formed on the amorphous silicon layer, and a metal catalysis solution is applied onto the surface of the buffer layer, wherein the metal... Agent: Jianq Chyun Intellectual Property Office

20060292837 - Method and apparatus for modelling film grain patterns in the frequency domain: Film grain patterns can be modeled in the frequency domain by estimating the cut frequencies that define a 2D band-pass filter. The film grain parameters can be conveyed in accordance with the ITU-T H.264|MPEG-4 AVC standard in an SEI message allowing film grain reinsertion at a decoder.... Agent: Thomson Licensing Inc.

20060292838 - Ion implanting methods: An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received over the features and which has an opening therein... Agent: Wells St. John P.s.

20060292839 - Contacts fabric using heterostructure of metal/semiconductor nanorods and fabrication method thereof: Provided are a contact fabric using a heterostructure of metal/semiconductor nanorods and a method of manufacturing the same. An ohmic contact fabric having a low contact resistance or a Schottky contact fabric having a rectification characteristic is formed by selectively depositing metal of nano-sizes onto predetermined portions of zinc oxide/semiconductor... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20060292841 - Atomic layer deposition systems and methods including metal beta-diketiminate compounds: The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one β-diketiminate ligand. Such systems and methods can be useful for depositing metal-containing layers on substrates.... Agent: Mueting, Raasch & Gebhardt, P.A.

20060292840 - Thermally conductive grease and methods and devices in which said grease is used: A thermally conductive grease includes (A) a polyorganosiloxane having a viscosity less than 50 cSt (mm2/s) at 25° C. and (B) a thermally conductive filler. The thermally conductive grease is useful as a thermal interface material for electronic devices.... Agent: Dow Corning Corporation Co1232

20060292842 - Self-aligned gate and method: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then... Agent: Stmicroelectronics, Inc.

20060292843 - Method for fabricating semiconductor device: Provided is a method for fabricating a semiconductor device, capable of increasing a contact open margin and minimizing a shoulder loss of a gate line. The method includes: forming a gate line on a substrate, the gate line including a first hard mask and a second hard mask; forming an... Agent: Blakely Sokoloff Taylor & Zafman

20060292844 - Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric: A method of forming a silicon oxynitride gate dielectric. The method includes incorporating nitrogen into a dielectric film using a plasma nitridation process to form a silicon oxynitride film. The silicon oxynitride film is annealed in a first ambient. The first ambient comprises an inert ambient with a first partial... Agent: Patterson & Sheridan, LLP

20060292846 - Material management in substrate processing: Substrate processing systems and methods are described for processing substrates. The processing includes transferring electronic identification (ID) information of one or more materials contained in one or more processing subsystems. Materials are transferred between one or more material containers and respective one or more process cells during transfer events of... Agent: Courtney Staniford & Gregory LLP

20060292848 - Method for manufacturing nano-gap electrode device: Provided is a method for manufacturing a nano-gap electrode device comprising the steps of: forming a first electrode on a substrate; forming a spacer on a sidewall of the first electrode; forming a second electrode on an exposed substrate at a side of the spacer; and forming a nano-gap between... Agent: Mayer, Brown, Rowe & Maw LLP

20060292845 - Processing substrates using site-isolated processing: Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one... Agent: Courtney Staniford & Gregory LLP

20060292847 - Silver barrier layers to minimize whisker growth in tin electrodeposits: The invention relates to a method of reducing tin whisker formation in a plated substrate that includes a surface layer comprising tin. The method includes providing on electroplatable portions of the substrate (a) an underlayer comprising silver or (b) a barrier layer that passes a mechanical load test when the... Agent: Winston & Strawn LLP Patent Department

20060292849 - Ultrathin semiconductor circuit having contact bumps and corresponding production method: The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor... Agent: Brinks Hofer Gilson & Lione

20060292851 - Circuitry component and method for forming the same: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and... Agent: North America Intellectual Property Corporation

20060292850 - Method for manufacturing semiconductor device and non-volatile memory: A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a... Agent: Jianq Chyun Intellectual Property Office

20060292852 - Back end interconnect with a shaped interface: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner... Agent: International Business Machines Corporation Dept. 18g

20060292855 - Current-aligned auto-generated non-equiaxial hole shape for wiring: A method, system and program product for replacing isotropic hole shapes in a wiring layout with non-equiaxial hole shapes that are arranged in a direction of current flow, which increases current flow along the wire's longitudinal axis while decreasing current flow along the wire's transverse axis. One aspect of the... Agent: Hoffman, Warnick & D'alessandro LLC

20060292854 - Manufacturing method of dual damascene structure: A manufacturing method of a dual damascene structure is provided. First, a barrier layer, a first dielectric layer, a second dielectric layer, a cap layer, a metal-containing hard mask layer, a dielectric hard mask layer, a first bottom anti-reflection coating (BARC) layer and a first photoresist layer are sequentially formed... Agent: Jianq Chyun Intellectual Property Office

20060292853 - Method for fabricating an integrated semiconductor circuit and semiconductor circuit: The present invention relates to a method for fabricating an integrated semiconductor circuit having a conductor structure buried in a semiconductor substrate, and to an integrated semiconductor circuit, in which case the integrated semiconductor circuit may be an application specific semiconductor circuit or a semiconductor circuit that can be adapted... Agent: Morrison & Foerster LLP

20060292856 - Method of patterning a porous dielectric material: A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other... Agent: Intel Corporation

20060292857 - Methods for making integrated-circuit wiring from copper, silver, gold, and other metals: Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292858 - Techniques to create low k ild for beol: One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292859 - Damascene process using dielectic layer containing fluorine and nitrogen: An improved damascene process for fabricating a semiconductor device. A dielectric layer comprising at least both fluorine and nitrogen is formed overlying a substrate, in which a nitrogen content in the dielectric layer is about 5% to 10%. The dielectric layer is subsequently pattered to form at least one damascene... Agent: Birch Stewart Kolasch & Birch

20060292860 - Prevention of post cmp defects in cu/fsg process: A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG... Agent: Haynes And Boone, LLP

20060292861 - Method for making integrated circuit chip having carbon nanotube composite interconnection vias: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20060292862 - Method for forming barrier metal of semiconductor device: A method for forming a barrier metal of a semiconductor device includes forming an insulating layer on a semiconductor substrate and forming an opening in the insulating layer and forming a TiSiN layer having a desired thickness by repeatedly performing a process of forming a TiSiN layer having an atomic... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20060292863 - Preventing damage to metal using clustered processing and at least partially sacrificial encapsulation: Methods are disclosed for metal encapsulation for preventing exposure of metal during semiconductor processing. In one embodiment, the method includes forming an opening in a structure exposing a metal surface in a bottom of the opening, where the opening forming step occurs in a tool including at least one clustered... Agent: Hoffman, Warnick & D'alessandro LLC

20060292864 - Plasma-enhanced cyclic layer deposition process for barrier layers: In one embodiment, a method for forming a metal-containing material on a substrate is provided which includes forming a metal containing barrier layer on a substrate by a plasma-enhanced cyclical vapor deposition process, exposing the substrate to a soak process, and depositing a conductive material on the substrate by a... Agent: Patent Counsel Applied Materials, Inc.

20060292865 - Semiconductor device: A semiconductor device of the present invention has a first conductive layer, a second conductive layer, an insulating layer which is formed between the first conductive layer and the second conductive layer and which has a contact hole, and a third conductive layer which is connected to the first conductive... Agent: Eric Robinson

20060292866 - Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method: Embodiments of the present invention are directed to a process for forming small diameter vias at low temperatures. In preferred embodiments, through-substrate vias are fabricated by forming a through-substrate via; and depositing conductive material into the via by means of a flowing solution plating technique, wherein the conductive material releases... Agent: Koppel, Patrick & Heybl

20060292867 - Method of forming metal line in semiconductor device: The present invention provides a method of forming metal lines in a semiconductor device having advantages of preventing an “explosion” phenomenon during a dual damascene process so as to improve the yield of the device. An exemplary embodiment of the present invention includes removing etching residues by wet cleaning the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060292868 - Surface emitting semiconductor laser: A method of forming a conductive pattern such as an electrode on a compound semiconductor layer includes the steps of forming a first organic layer on the compound semiconductor layer, forming a second layer on the first organic layer, the second layer being resistant to plasma ashing, forming a pattern... Agent: Oliff & Berridge, PLC

20060292869 - Tungsten plug corrosion prevention method using ionized air: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one... Agent: Campbell Stephenson Ascolese, LLP

20060292870 - A method of synthesizing nanoscale filamentary structures and electronic components comprising such structures: A method of synthesizing electronic components incorporating nanoscale filamentary structures in which method a metallic catalyst is deposited in a nanoporous membrane, the catalyst being adapted to penetrate in at least some of the pores of the nanoporous membrane, and filamentary structures are grown on the catalyst in at least... Agent: Miller, Matthis & Hull

20060292872 - Atomic layer deposition of thin films on germanium: Germanium has higher mobility than silicon and therefore is considered to be a good alternative semiconductor for CMOS technology. Surface treatments a can facilitate atomic layer deposition (ALD) of thin films, such as high-k dielectric layers, on germanium substrates. Surface treatment can comprise the formation of a thin layer of... Agent: Knobbe Martens Olson & Bear LLP

20060292871 - Methods of forming titanium-containing materials, and semiconductor processing methods: The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance, the invention can utilize alternating cycles of titanium tetrachloride and activated hydrogen to form... Agent: Wells St. John P.s.

20060292873 - Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same: The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In some embodiments, the metal-containing compounds are homoleptic complexes that include unsymmetrical β-diketiminate ligands. In other embodiments, the metal-containing compounds are heteroleptic complexes including at least one β-diketiminate ligand.... Agent: Mueting, Raasch & Gebhardt, P.A.

20060292874 - method for forming tungsten materials during vapor deposition processes: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to a first reducing gas and a tungsten precursor gas to form a... Agent: Patterson & Sheridan, LLP

20060292875 - Method for enhancing electrode surface area in dram cell capacitors: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode,... Agent: Whyte Hirschboeck Dudek S.c.

20060292876 - Plasma etching method and apparatus, control program and computer-readable storage medium: In a method for plasma etching a wafer laminated with a target layer, a lower organic layer, an intermediate layer and an upper resist layer in that order from bottom, the method includes following steps: patterning the upper resist layer by exposure and development, plasma etching the intermediate layer by... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292878 - Method for fabricating semiconductor element: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes the steps of: preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide... Agent: Volentine Francos, & Whitt PLLC

20060292879 - Method for peeling off semiconductor element and method for manufacturing semiconductor device: A method for peeling off a thin film semiconductor element over an insulating surface by using a void, and a method for manufacturing a semiconductor device by transferring the peeled semiconductor element. According to the peeling method of the invention, a first base layer having a plurality of recessed portions... Agent: Eric Robinson

20060292877 - Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures: Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross section and a second portion in the... Agent: Trask Britt, P.C.

20060292880 - Methods of fabricating p-type transistors including germanium channel regions and related devices: A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-crystalline germanium layer may be selectively locally heated,... Agent: Myers Bigel Sibley & Sajovec

20060292882 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming a hard mask layer on the inter-layer insulation layer; etching the hard mask layer using a contact mask; and etching the inter-layer insulation layer using the hard mask layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292881 - Method of encapsulating an assembly with a low temperature silicone rubber compound: A method for encapsulating an assembly with a methyl phenyl silicone rubber compound is provided. In various embodiments, the method can include exposing the assembly to a solvent, plasma etching the assembly, and producing a potting mixture, wherein the potting mixture comprises a methyl phenyl room temperature vulcanization silicone and... Agent: Kurt A. Luther Honeywell International, Inc.

20060292883 - Etching of silicon nitride with improved nitride-to-oxide selectivity utilizing halogen bromide/chlorine plasma: A method of manufacturing a semiconductor device is disclosed. A gate is formed on a semiconductor substrate. A gate oxide is formed between the gate and the semiconductor substrate. A silicon oxide liner layer is deposited on the gate and on the semiconductor substrate. A silicon nitride layer is then... Agent: North America Intellectual Property Corporation

20060292884 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a polysilicon layer, a silicide layer and a hard mask over a semiconductor substrate, etching the silicide layer using the hard mask as an etch barrier, shaping the silicide layer with a predetermined profile using a mixed gas, and etching the... Agent: Blakely Sokoloff Taylor & Zafman

20060292885 -