Semiconductor device manufacturing: process inventions 12/06

20060292704 - Magnetostactic wave device based on thin metal films, method for making same and application to devices for processing microwave signals: The integrated magnetostatic wave device comprises a substrate (1), a conductive ferromagnetic thin film (2) of thickness lying in the range about 250 nm to 450 nm and preferably being equal to about 300 nm, said thin film (2) being deposited on said substrate (1), a first transducer antenna (10)... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20060292705 - Method and process for fabricating read sensors for read-write heads in mass storage devices: Method and process for fabricating a device structure for a read head of a mass storage device. A polish stop layer formed of a relatively hard material, such as diamond-like carbon, is positioned between a layer stack and a resist mask used to mask regions of the layer stack during... Agent: Wood, Herron & Evans, LLP

20060292706 - Method of manufacturing substrate having periodically poled regions: A current is observed while applying a gradually increasing voltage between electrodes formed front and rear surfaces of a substrate, and then poled regions are formed by applying a DC voltage, which has a voltage value at that time or another voltage value obtained by adding a predetermined value to... Agent: Rankin, Hill, Porter & Clark LLP

20060292707 - Healing detrimental bonds in deposited materials: A method for healing detrimental bonds in deposited materials, for example porous, low-k dielectric materials, including oxydatively processing a deposited material, processing the deposited material with a trialkyl group III compound, and processing in the presence of an alcohol. Also included in embodiments of the invention are materials with bonds... Agent: Blakely Sokoloff Taylor & Zafman

20060292708 - Circuit arrangement, redox recycling sensor, sensor assembly and a method for processing a current signal provided by a sensor electrode: A circuit arrangement has a sensor electrode, a control circuit which is coupled to the sensor electrode via an input, and a current source which is coupled via a control input to a control output of the control circuit. The current source can be controlled by the control circuit. The... Agent: Brinks Hofer Gilson & Lione Infineon

20060292711 - Mechanical integrity evaluation of low-k devices with bump shear: A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104).... Agent: Hamilton & Terrile, LLP

20060292709 - Method for fabricatiing three-dimensional microstructure by fib-cvd and drawing system for three-dimensional microstruture: There are provided a fabrication method of a nanostructure by FIB-CVD which enables fabrication of a three-dimensional nanostructure, especially that without a support such as a terrace structure or a hollow structure, and a drawing system thereof. The three-dimensional nanostructure is fabricated by controlling a focused ion beam to determine... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292712 - Process for the detection of a malfunction in a device for wire sawing and device for practicing said process: The invention relates to a process for the detection of malfunctions, in particular the detection of breakage of a wire in a wire sawing device. The process consists in applying an alternating signal to the layer of wires (4) of the sawing device and measuring the variations of voltage or... Agent: Young & Thompson

20060292713 - Semiconductor integrated circuit device: To provide a semiconductor device which can be down-sized and integrated to a high degree. A semiconductor device including a rewiring mixedly includes an input/output (I/O) cell connected to a probing pad; and another input/output (I/O) cell having no probing pad.... Agent: Mcdermott Will & Emery LLP

20060292710 - Sensor and method for detecting electric contact degradation: A probe cell monitors conditions within electrical power transmission and switchgear apparatus to detect degradation of stressed components. The probe cell is a hardware simulation of components of a specific unit of electrical power apparatus, including electrodes between which an electric field gradient is established. The probe cell electrodes accumulate... Agent: Baker & Hostetler LLP

20060292714 - Semiconductor manufacturing apparatus and wafer processing method: A semiconductor manufacturing apparatus and a wafer processing method are disclosed. The semiconductor manufacturing apparatus, comprises a rotatable device for supporting a wafer. A sensor for irradiating a laser beam onto a surface of the wafer and a detector including a plurality of modules for detecting the laser beam reflected... Agent: Marger Johnson & Mccollom, P.C.

20060292715 - Method for fabricating a metal-insulator-metal capacitor: A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292716 - Use selective growth metallization to improve electrical connection between carbon nanotubes and electrodes: Disclosed is a method of making a CNT device such as a memory switch, a field emission display, interconnect wiring, etc. The method includes steps of providing CNTs in contact with an electrode and selectively growing or depositing a layer of metal on top of the CNTs and the electrode.... Agent: Lsi Logic Corporation

20060292717 - Mounting and adhesive layer for semiconductor components: An assembly and adhesive layer for semiconductor components is arranged between a silicon support (submount) and an electronic functional element for the formation of an electrically-conducting connection between the silicon support and the functional element. The assembly and adhesive layer are arranged on the support. The assembly and adhesive layer... Agent: Slater & Matsil LLP

20060292719 - Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.... Agent: Goodwin Procter LLP Patent Administrator

20060292718 - Method of producing nitride layer and method of fabricating vertical structure nitride semiconductor light emitting device: The present invention provides methods for manufacturing a nitride layer and a vertical nitride semiconductor light emitting device. In manufacturing the nitride layer according to the invention, a sapphire substrate is prepared. A buffer layer made of a material having a melting point and a thermal conductivity higher than those... Agent: Mcdermott Will & Emery LLP

20060292720 - Semiconductor laser device: When a laser irradiation direction is assumed as a forward direction, a front end surface of a die pad (104), a front end surface of a resin mold member (106), and a front end surface of a semiconductor laser element (101) are sequentially disposed in this order from the front... Agent: Steptoe & Johnson LLP

20060292721 - Fabricating method for flat display device: A fabricating method of a flat panel display device can reduce manufacturing costs of the flat panel display device. A fabricating method of a flat panel display device includes providing a conductive nanopowder thin film material having a first conductive nanopowder and a second conductive nanopowder, spreading the conductive nanopowder... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20060292722 - Flexible interconnect structures for electrical devices and light sources incorporating the same: A flexible interconnect structure allows for rapid dissipation of heat generated from an electrical device that includes light-emitting elements, such as light-emitting diodes (“LEDs”) and/or laser diodes. The flexible interconnect structure comprises: (1) at least one flexible dielectric film on which circuit traces and, optionally, electrical circuit components are formed... Agent: Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20060292725 - Method for manufacturing device having optical semiconductor element: The invention provides a method of forming a device having an optical semiconductor element by bonding a cover body, which can cover the optical semiconductor element, to a head portion having the optical semiconductor element. The method comprises the steps of: a short circuit step of shorting terminals of the... Agent: Nixon & Vanderhye, PC

20060292724 - Method of manufacturing organic el display: A method of manufacturing a plurality of organic EL displays, by sealing and cutting an organic EL substrate, controlling the adhesion width and cutting the glass substrate without extending the cutting position. An organic EL substrate, and a sealing glass substrate with recesses opposing each laminate of the organic EL... Agent: Rabin & Berdo, PC

20060292723 - Plasma display device: A plasma display device includes a plasma display 1, a chassis 2 having conductivity that supports the plasma display 1, a tuner circuit 11, a scan driver 12, a sustaining driver 13 and so forth used to display a video on the plasma display 1, a back cover 4 that... Agent: Wenderoth, Lind & Ponack L.L.P.

20060292726 - Method of manufacturing a semiconductor device: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer... Agent: Nixon Peabody, LLP

20060292728 - Nitride crystal, nitride crystal substrate, epilayer-containing nitride crystal substrate, semiconductor device and method of manufacturing the same: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal... Agent: Mcdermott Will & Emery LLP

20060292727 - Photomask plasma etching apparatus, etching method, and photomask forming method: A photomask plasma etching apparatus includes an electrode to generate plasma, and an electrical capacity control unit configured to control an electrical capacity between the electrode and a mask substrate to be held on the electrode.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292729 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate, an actuator provided above the semiconductor substrate to move upwardly, a first electrode layer which is moved by the actuator, and a cap portion provided above the first electrode layer and including a second electrode layer.... Agent: Foley And Lardner LLP Suite 500

20060292731 - Cmos image sensor and manufacturing method thereof: A CMOS image sensor with improved performance through improved uniformity of micro-lens size and a method for manufacturing the same are provided. The CMOS image sensor includes photodiodes formed on a semiconductor substrate for producing charges consistent with a quantity of incident light, an interlayer insulation layer formed on an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292730 - Method and device for cmos image sensing with separate source formation: A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is... Agent: Townsend And Townsend And Crew, LLP

20060292732 - Methods of flip-chip image sensor package fabrication: The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete... Agent: Trask Britt

20060292734 - Method for manufacturing cmos image sensor: Disclosed is a CMOS image sensor and a method for manufacturing a CMOS image sensor. The method includes: (a) forming a resist film on a semiconductor substrate comprising a light sensing part, a protecting layer over the light sensing part, and an exposed bonding pad; (b) forming a color filter... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060292733 - Method of manufacturing cmos image sensor: Provided is a manufacturing method of a CMOS image sensor. The method includes forming an interlayer insulating layer, a color filter layer, and a planarizing layer. A first photoresist is applied on the planarizing layer, and patterning of the first photoresist is performed using a first mask to form a... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292735 - Methods for creating gapless inner microlenses, arrays of microlenses, and imagers having same: Methods of fabricating a microlens and/or array of microlenses used to focus light on photosensors, by forming a protective coating over a microlenses precursor material, and etching the protective coating and microlens precursor material to obtain a predetermined shape.... Agent: Dickstein Shapiro LLP

20060292736 - Architecture for high efficiency polymer photovoltaic cells using an optical spacer: High efficiency polymer photovoltaic cells have been fabricated using an optical spacer between the active layer and the electron-collecting electrode. Such cells exhibit approximately 50% enhancement in power conversion efficiency. The spacer layer increases the efficiency by modifying the spatial distribution of the light intensity inside the device, thereby creating... Agent: Foley & Lardner LLP

20060292738 - Flex on suspension with a heat-conducting protective layer for reflowing solder interconnects: A FOS is provided for electrically connecting a data transfer head with a PCCA. The FOS comprises a polymeric layer supporting an electrical trace. The electrical trace comprises an uninsulated pad surface configured for electrically engaging a solder interconnect of the PCCA. The polymeric layer comprises a continuous portion covering... Agent: Derek J. Berger Seagate Technology LLC

20060292737 - Grid array connection device and method: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292741 - Heat-dissipating semiconductor package and fabrication method thereof: A heat-dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a substrate. A heat-dissipating structure includes a heat sink and at least one supporting portion, wherein the supporting portion is attached to the substrate at a position outside a predetermined... Agent: Birch Stewart Kolasch & Birch

20060292740 - High temperature packaging for electronic components, modules and assemblies: A high temperature semiconductor packaging, a method for making the same packaging are providing. The packaging comprises a mounting platform, a semiconductor die positioned above the platform and a layer of high temperature passivation coating.... Agent: Brown Raysman Millstein Felder & Steiner, LLP

20060292742 - Manufacturing method for packaged semiconductor device: A semiconductor device in which moisture penetration into the package interior is suppressed, comprising a rewiring layer formed by plating, with improved reliability of electrical characteristics. On the main surface of a semiconductor chip comprising circuit elements and formed on a wafer, a passivation film opposing the circuit elements is... Agent: Rabin & Berdo, PC

20060292739 - Method and apparatus to boost high-speed i/o signal performance using semi-interleaved transmitter/receiver pairs at silicon die bump and package layout interfaces: A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where transmitters and receivers of the two circuit patterns are positioned so that the two transmitters are adjacent or so that the two receivers... Agent: Blakely Sokoloff Taylor & Zafman

20060292743 - Stacked die in die bga package: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20060292744 - Three dimensional device integration method and integrated device: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292745 - Stacked die in die bga package: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20060292746 - Stacked die in die bga package: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... Agent: Whyte Hirschboeck Dudek S.c.

20060292748 - Package having bond-sealed underbump: A package for containing microelectromechanical devices includes a first substrate wafer, and a second substrate wafer made of an optical quality material. An underbump is interposed between the first and second substrate wafers. The underbump is composed of a standoff region and a localized bond region. The first and second... Agent: Hewlett-packard Company Intellectual Property Administration

20060292749 - Photochromic substrate container: A semiconductor wafer, substrate, or reticle storage or shipping device that includes a photochromic indicator of exposure to undesired electromagnetic radiation. The present invention includes the incorporation of a photochromic material into the plastic used to fabricate at least a portion of a semiconductor wafer, disk, or reticle shipping or... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20060292747 - Top-surface-mount power light emitter with integral heat sink: A light emitting apparatus is disclosed. The light emitting apparatus includes a substrate, a heat sink, a dielectric layer, conductive traces, a reflector, and at least one photonic device. The substrate has a top surface and a bottom surface, a portion of the top surface defining a mounting pad. The... Agent: Harness, Dickey & Pierce, P.L.C

20060292750 - Standoffs for centralizing internals in packaging process: A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the semiconductor device comprises a pair of semiconductor dies mounted on opposing sides of a flexible tape substrate, the outer surfaces of the dies having one or more standoffs... Agent: Whyte Hirschboeck Dudek S.c.

20060292751 - Technique for manufacturing an overmolded electronic assembly: A technique for manufacturing an electronic assembly uses a mold that has a first mold portion and a second mold portion. The first mold portion includes a plurality of spaced mold pins extending from an inner surface. A cavity of the first and second mold portions provides a mold cavity,... Agent: Delphi Technologies, Inc.

20060292752 - Method for fabricating board on chip (boc) semiconductor package with circuit side polymer layer: A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the substrate in a... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20060292753 - Semiconductor device and method of manufacturing a semiconductor device: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface... Agent: Texas Instruments Incorporated

20060292754 - Antifuse element and method of manufacture: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060292755 - Tunable antifuse element and method of manufacture: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060292759 - Apparatus for annealing, method for annealing, and method for manufacturing a semiconductor device: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292756 - Flip chip die assembly using thin flexible substrates: Apparatus and methods for flattening thin substrate surfaces by stretching thin flexible substrates to which ICs can be bonded. Various embodiments beneficially maintain the substrate flatness during the assembly process through singulation. According to one embodiment, the use of a window frame type component carrier allows processing of thin laminates... Agent: Guidant Patent Docketing Faegre & Benson, LLP

20060292760 - Method of fabricating a thin film transistor for an array panel: A method for making a thin film transistor, TFT, (306) on a substrate includes a photolithographic process step of patterning three layers of materials to form a TFT (306) and to form a bridging structure (308) crossing over a TFT gate bus-line conductor (202) at a cross over region; followed... Agent: Mark J. Marcelli Duane Morris LLP

20060292758 - Pyrimidopyrimidine derivatives, organic thin film transistors using pyrimidopyrimidine derivatives and method for fabricating the same: Pyrimidopyrimidine derivatives, organic thin film transistors using pyrimidopyrimidine derivatives and method for fabricating the same are provided. Pyrimidopyrimidine derivative structures, along with example syntheses, are provided. The pyrimidopyrimidine derivatives may be pyrimidopyrimidine oligothiophene derivatives in which an oligothiophene having p-type semiconductor characteristics may be bonded to a pyrimidopyrimidine having n-type... Agent: Harness, Dickey & Pierce, P.L.C

20060292757 - Thin-film transistor (tft) for driving organic light-emitting diode (oled) and method for manufacturing the same: A thin-film transistor (TFT) and a method for manufacturing the thin-film transistor using a color filter as a dielectric layer so as to drive an organic light-emitting diode. The thin-film transistor comprises: a substrate; a first poly-silicon mesa formed on the substrate; an insulating layer formed on the substrate and... Agent: Bruce H. Troxell Suite 1404

20060292761 - Method for fabricating semiconductor device: [Problem] To provide technology that allows, by controlling a crystal orientation, forming a crystalline semiconductor film aligned in orientation and obtaining a crystalline semiconductor film whose impurity concentration is reduced. [Means, for Resolution] On an insulating surface, a first semiconductor region made of an amorphous semiconductor is formed, a continuous... Agent: Nixon Peabody, LLP

20060292762 - Replacement gate field effect transistor with germanium or sige channel and manufacturing method for same using gas-cluster ion irradiation: A self-aligned MISFET transistor (500H) on a silicon substrate (502), but having a graded SiGe channel or a Ge channel. The channel (526) is formed using gas-cluster ion beam (524) irradiation and provides higher channel mobility than conventional silicon channel MISFETs. A manufacturing method for such a transistor is based... Agent: Burns & Levinson, LLP (formerly Perkins Smith & Cohen LLP)

20060292763 - Methods of fabricating thin film transistor and organic light emitting display device using the same: Methods of fabricating a TFT and an OLED using the same are provided. The method of fabricating a CMOS TFT includes: preparing a substrate having first and second TFT regions; forming a gate electrode on the substrate; forming a gate insulating layer on the entire surface of the substrate including... Agent: Knobbe Martens Olson & Bear LLP

20060292764 - Method of manufacturing a vertical mos transistor: In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a semiconductor substrate. An intermediate insulating film is deposited over a main surface of the semiconductor substrate... Agent: Bruce L. Adams, Esq. Suite 1231

20060292765 - Method for making a finfet including a superlattice: A method for making a semiconductor device may include forming at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite sides of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20060292766 - Storage devices formed on partially isolated semiconductor substrate islands: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292767 - Storage devices formed on partially isolated semiconductor substrate islands: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292768 - Semiconductor device and manufacturing method thereof: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a gate insulating layer, a gate electrode, an oxide layer, and sidewalls. The gate insulating layer is formed on the substrate. The gate electrode includes an upper layer and a lower layer stacked on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292769 - Multilayered structure forming method: A multilayered structure forming method includes disposing a dummy post on a first insulating pattern as a first inkjet process, disposing a second insulating pattern on the first insulating pattern as a second inkjet process so as to allow the second insulating pattern to surround a side surface of the... Agent: Harness, Dickey & Pierce, P.L.C

20060292770 - Cmos on soi substrates with hybrid crystal orientations: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS... Agent: Slater & Matsil, L.L.P.

20060292771 - High voltage depletion fet employing a channel stopping implant: A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop regions and n-type surface channel regions are formed. A... Agent: Texas Instruments Incorporated

20060292772 - Dense pitch bulk finfet process by selective epi and etch: Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20060292780 - Field-effect transistor and method for producing a field-effect transistor: Field-effect transistor is disclosed that includes a gate oxide, a polycrystalline layer applied on the gate oxide, and at least one spacer of polycrystalline silicon, wherein the gate oxide has a first thickness in a first region beneath the polycrystalline silicon layer and a second thickness in a second region... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20060292781 - Finfets, nonvolatile memory devices including finfets, and methods of forming the same: A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected to the device... Agent: Myers Bigel Sibley & Sajovec

20060292777 - Method for making electronic devices using metal oxide nanoparticles: A method of making a thin film transistor comprises (a) solution depositing a dispersion comprising semiconducting metal oxide nanoparticles onto a substrate, (b) sintering the nanoparticles to form a semiconductor layer, and (c) optionally subjecting the resulting semiconductor layer to post-deposition processing.... Agent: 3m Innovative Properties Company

20060292774 - Method for preventing metal line bridging in a semiconductor device: A method for forming a semiconductor device includes providing a substrate, providing aluminum metal lines on the substrate, forming a barrier layer over the aluminum metal lines, and forming a silicon-rich dielectric layer over the barrier layer. An inter-metal dielectric (IMD) layer may be formed to cover at least a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292773 - Method of making a metal gate semiconductor device: A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to form a sidewall spacer... Agent: Freescale Semiconductor, Inc. Law Department

20060292775 - Method of manufacturing dram capable of avoiding bit line leakage: A method to make DRAM capable of avoiding bit line leakage is provided. The method comprise the steps of forming transistors on substrate, forming an insulating layer to cover the substrate and the transistors, forming a poly-silicon layer over the insulating layer, forming contact holes in the poly-silicon layer and... Agent: Birch Stewart Kolasch & Birch

20060292778 - Semiconductor device and method for manufacturing the same: A first resist mask and a second resist mask used for forming a gate electrode for a p-channel TFT and a gate electrode for an n-channel TFT are left, and a third resist mask is formed afterwards over a first area where one of the p-channel TFT and the n-channel... Agent: Nixon Peabody, LLP

20060292776 - Strained field effect transistors: An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer.... Agent: Trop Pruner & Hu, PC

20060292779 - Structure and method for making strained channel field effect transistor using sacrificial spacer: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides... Agent: International Business Machines Corporation Dept. 18g

20060292783 - Cmos transistor and method of manufacturing the same: A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a... Agent: Volentine Francos, & Whitt PLLC

20060292782 - Semiconductor device and method for manufacturing the same: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060292784 - Methods of forming integrated circuit devices including memory cell gates and high voltage transistor gates using plasma re-oxidation: A method of forming an integrated circuit device can include forming a plurality of stacked cell gates in a memory cell region of a semiconductor substrate and a plurality of high-voltage transistor gates in a peripheral circuit region of the semiconductor substrate. The semiconductor substrate including both the plurality of... Agent: Myers Bigel Sibley & Sajovec

20060292785 - Cu-metalized compound semiconductor device: The present invention is a compound semiconductor device characterized in that it is Cu-metalized to improved the reliability of the device and to greatly reduce the cost of production.... Agent: Troxell Law Office PLLC

20060292786 - Semiconductor constructions, and methods of forming semiconductor constructions: The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion.... Agent: Wells St. John P.s.

20060292787 - Semiconductor processing methods, and semiconductor constructions: The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region... Agent: Wells St. John P.s.

20060292788 - Systems and methods of forming refractory metal nitride layers using disilazanes: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound.... Agent: Mueting, Raasch & Gebhardt, P.A.

20060292789 - Structure and method for collar self-aligned to buried plate: A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.... Agent: International Business Machines Corporation Dept. 18g

20060292790 - Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50... Agent: Texas Instruments Incorporated

20060292791 - Semiconductor integrated circuit device and method for manufacturing the same: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060292796 - Flash memory device and method for manufacturing the same: A flash memory device incorporating: a semiconductor substrate having an active region and a field region defined therein; a device isolation layer formed in the field region of the substrate; a floating gate having an edge portion overlapping the device isolation layer, the overlapped portion being etched back a depth... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292798 - Flash memory device and method for manufacturing the same: A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060292792 - Method for the manufacture of a non-volatile memory device and memory device thus obtained: The present invention relates to a method for processing of a non-volatile memory cell (50) which comprises a double gate stack and a single access gate. The method combines a way of processing an access gate with drain implant, separate from source implant, in a self-aligned manner. The method of... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20060292797 - Method of fabricating floating gate of flash memory device: A method of fabricating a floating gate of a flash memory device is provided. The method includes: forming a tunneling oxide layer on a substrate; forming a conductive thin layer on the tunneling oxide layer; applying a photoresist on the conductive thin layer; defining a floating gate region by patterning... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292795 - Method of manufacturing a flash memory device: In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled... Agent: Volentine Francos, & Whitt PLLC

20060292794 - Method of manufacturing dielectric film of flash memory device: A method of manufacturing a dielectric film of a flash memory device, including the steps of providing a semiconductor substrate having floating gates formed therein, performing an oxidization process in a decompression state to form a first oxide film of a thin film on the semiconductor substrate including the floating... Agent: Marshall, Gerstein & Borun LLP

20060292793 - Semiconductor processing methods: The invention includes methods in which common processing steps are utilized during fabrication of components of a memory array region of a semiconductor substrate and components of a peripheral region proximate the memory array region, and yet the components of the peripheral region are built for different performance characteristics than... Agent: Wells St. John P.s.

20060292799 - Memory embedded semiconductor device and method for fabricating the same: A memory embedded semiconductor device according to the present invention has a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate. The logic transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed... Agent: Mcdermott Will & Emery LLP

20060292800 - Ono formation of semiconductor memory device and method of fabricating the same: A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on... Agent: Rabin & Berdo, PC

20060292801 - Bit line of a semiconductor device and method for fabricating the same: A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film... Agent: Townsend And Townsend And Crew, LLP

20060292802 - Semiconductor device and method for forming the same: There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode... Agent: Myers Bigel Sibley & Sajovec

20060292803 - High voltage metal-oxide-semiconductor transistor devices and method of making the same: A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate... Agent: North America Intellectual Property Corporation

20060292804 - Nitride semiconductor light emitting diode and fabrication method thereof: The invention relates to a nitride semiconductor LED and a fabrication method thereof. In the LED, a first nitride semiconductor layer, an active region a second nitride semiconductor layer of a light emitting structure are formed in their order on a transparent substrate. A dielectric mirror layer is formed on... Agent: Lowe Hauptman Berner, LLP

20060292805 - Semiconductor device: A semiconductor device is provided, which includes a first main electrode region having an upper main surface and a lower main surface; a drift layer of a first conductivity type formed on the upper main surface of the first main electrode region; a base layer of a second conductivity type... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292806 - Semiconductor integrated circuit device: To improve a degree of integration and reliability of a semiconductor integrated circuit device. There are included third wire 14 arranged in the same layer as first wire 11 and second wire 12 and arranged in a direction intersecting with the first wire 11 and the second wire 12, first... Agent: Mcginn Intellectual Property Law Group, PLLC

20060292807 - Semiconductor device and method of fabricating the same: A semiconductor device incorporating an alloy layer formed on a substrate; a gate electrode, a source electrode, and a drain electrode formed on the alloy layer at predetermined intervals therebetween; a gate insulating layer formed on the gate electrode in a gate electrode region; a first conductive layer formed on... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060292808 - Absorber layer for dsa processing: A method of processing a substrate comprising depositing a layer comprising amorphous carbon on the substrate and then laser annealing the substrate is provided. Optionally, the layer further comprises a dopant selected from the group consisting of nitrogen, boron, phosphorus, fluorine, and combinations thereof. In one aspect, the layer comprising... Agent: Patterson & Sheridan, LLP

20060292809 - Method for growth and optimization of heterojunction bipolar transistor film stacks by remote injection: A method, and a resulting device, for fabricating a heterojunction bipolar transistor (HBT). HBT devices have a high transconductance typical of bipolar devices and are additionally capable of high-power operation. To achieve the aforementioned characteristics, HBT devices are generally of the npn type, preferably with a thin, heavily doped base.... Agent: Schneck & Schneck

20060292813 - Electronic component and method for manufacturing the same: Electrode layers (1, 2) are arranged on both sides of a dielectric layer (3) facing each other so as to configure a capacitor. Lead electrodes (4, 5) are formed in the electrode layers (1, 2). A penetrating electrode (6) that is insulated from the electrode layers (1, 2) is formed.... Agent: Hamre, Schumann, Mueller & Larson P.C.

20060292812 - Integrated circuit devices including insulating support layers and related methods and structures: An integrated circuit device may include a substrate, a plurality of storage electrode landing pads on the substrate, and a plurality of storage electrodes. Each of the plurality of storage electrodes may be on a portion of a respective one of the plurality of storage electrode landing pads. In addition,... Agent: Myers Bigel Sibley & Sajovec

20060292811 - Method for forming a capacitor in a semiconductor and a capacitor using the same: Disclosed is a capacitor and method for forming a capacitor in a semiconductor. The method includes the steps of: (a forming a lower electrode pattern on a silicon semiconductor substrate; (b etching a portion of the lower electrode pattern to a predetermined depth to form a step in the lower... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060292810 - Method of manufacturing a capacitor: In methods of manufacturing capacitors, a first metal compound may be deposited on a substrate using first and second source gases. The first and the second source gases may be provided onto the substrate by a first flow rate ratio in which a deposition rate of the first metal compound... Agent: Harness, Dickey & Pierce, P.L.C

20060292814 - Methods of forming integrated circuitry: In one implementation, an opening within a capacitor electrode forming layer is formed over a substrate. A spacing layer is deposited over the capacitor electrode forming layer to within the opening over at least upper portions of sidewalls of the opening. The spacing layer is formed to be laterally thicker... Agent: Wells St. John P.s.

20060292815 - Mim capacitor in a semiconductor device and method therefor: A MIM capacitor is formed over one or more metal interconnect layers in a semiconductor device. The capacitor has a lower plate electrode and an upper plate electrode. An insulator is formed between the plate electrodes. Prior to forming the first plate electrode a first insulating layer is deposited over... Agent: Freescale Semiconductor, Inc. Law Department

20060292817 - Methods of processing semiconductor structures and methods of forming capacitors for semiconductor devices using the same: In a method of processing a semiconductor structure and a method of forming a capacitor for a semiconductor device using the same, a semiconductor structure may be cleaned using a cleaning solution having a surface tension lower than that of water. The semiconductor structure may be dried in an isopropyl... Agent: Harness, Dickey & Pierce, P.L.C

20060292816 - Semiconductor device and method for fabricating the same: A semiconductor device comprises: an insulating film formed over a semiconductor substrate and having a first recess; a plurality of capacitor elements each of which is composed of a capacitor lower electrode formed on wall and bottom portions of the first recess and having a second recess, a capacitor insulating... Agent: Mcdermott Will & Emery LLP

20060292818 - Method for making a semiconductor device having a semiconductor-on-insulator (soi) configuration and including a superlattice on a thin semiconductor layer: A method for making a semiconductor device may include forming an insulating layer on a substrate, and forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The method may further include forming a superlattice on the semiconductor layer on a side thereof opposite the... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20060292820 - Isolation layers for semiconductor devices including first and second sub-trenches and methods of forming the same: In a device isolation layer for a p-MOS transistor and a method of forming the same, a trench oxide layer having a first and a second sub-oxide layers is formed in a trench including a first and a second sub-trenches. The first and second sub-oxide layers are formed on side... Agent: Myers Bigel Sibley & Sajovec

20060292819 - Semiconductor device and method for fabricating a semiconductor device: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the... Agent: Blakely Sokoloff Taylor & Zafman

20060292821 - Method of etching silicon: Silicon (12) is etched through a mask (11) comprising a layer of organic resin material (such as novolac) through which openings (32) are formed in the areas to be etched. The layer of organic resin is first deposited over a free surface of the device to be etched. The openings... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20060292823 - Method and apparatus for bonding wafers: Embodiments of a method and apparatus for bonding wafers are disclosed. The bonded wafers may include self-passivating interconnects. Other embodiments are described and claimed.... Agent: Intel Corporation

20060292822 - Method for producing dislocation-free strained crystalline films: A method for forming dislocation-free strained silicon thin film includes the step of providing two curved silicon substrates. One substrate is curved by the presence of silicon dioxide on a back surface. The other substrate is curved by the presence of a silicon nitride layer. One of the substrates is... Agent: VistaIPLaw Group LLP

20060292824 - Methods for bonding and micro-electronic devices produced according to such methods: One inventive aspect is related to a method of bonding two elements. The method comprises producing on a first element a first micropattern, comprising a first metal layer. The method further comprises producing on a second element a second micropattern, comprising a second metal layer. The method further comprises applying... Agent: Knobbe Martens Olson & Bear LLP

20060292825 - Monitoring the reduction in thickness as material is removed from a wafer composite and test structure for monitoring removal of material: The aim of the invention is to create a simple monitoring or testing method for monitoring a reduction in thickness as material is removed from a bonded semiconductor wafer pair, which prevents failure effects as material is removed from wafers (polishing, grinding or lapping). In addition, the costs of the... Agent: Hunton & Williams LLP Intellectual Property Department

20060292826 - Wafer processing method: A method of processing a wafer having a device area where a plurality of devices are formed on the front surface and an extra area surrounding the device area and comprising electrodes which are formed in the device area, comprising: a reinforcement forming step for removing an area, which corresponds... Agent: Smith, Gambrell & Russell

20060292829 - Apparatus and method of wafer dicing: A wafer dicing method includes the following steps. First, the wafer is adhered on an adhesive material. Next, the adhesive material is disposed on a frame. Then, the frame is clamped by a fixture, for fixing the wafer. Afterwards, a roller rotates against the adhesive material, for applying a force... Agent: Bacon & Thomas, PLLC

20060292827 - Chemical die singulation technique: A method is provided for manufacturing a semiconductor device from a substrate (200) having an active surface (204) and a non-active surface (206). The method comprises depositing a backing material (104) onto the non-active surface of the substrate (206) in a pattern (500), the pattern (500) having at least a... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060292830 - Chip dicing: A semiconductor structure and method for chip dicing. The method includes (a) providing a semiconductor substrate and (b) forming first and second device regions in and at top of the substrate. The first and second device regions are separated by a semiconductor border region of the substrate. The method further... Agent: Schmeiser, Olsen & Watts

20060292832 - Method of working nitride semiconductor crystal: In a method of working a crystal, when a nitride semiconductor crystal is worked, voltage is applied between the nitride semiconductor crystal and a tool electrode to cause electrical discharge, so that the crystal is partially removed and worked by local heat generated by the electrical discharge.... Agent: Mcdermott Will & Emery LLP

20060292831 - Spacer die structure and method for attaching: A semiconductor spacer structure comprises in order a backgrinding tape layer, a spacer adhesive layer, a semiconductor spacer layer, an optional second spacer adhesive layer, a dicing tape layer. In a first method a spacer wafer having first and second sides, a backgrinding tape layer and a spacer adhesive layer... Agent: Haynes Beffel & Wolfeld LLP

20060292828 - Wafer and method of cutting the same: A method of cutting a wafer. First, the first substrate and the second substrate are provided. Next, several alignment marks are formed on the backside of the second substrate to form two reference coordinate axes. Then, the first substrate and the second substrate are assembled to form a wafer. The... Agent: Bacon & Thomas, PLLC

20060292833 - Substrate for forming semiconductor layer: A substrate for forming a semiconductor layer includes a plurality of linear convexes or grooves on a surface of the substrate by crystal growth. The plurality of linear convexes or grooves are formed along a direction of a cleavage plane of the semiconductor layer.... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292835 - Element fabrication substrate: A substrate used for fabricating devices thereon includes an insulating film, and a monocrystal Ge thin layer formed on the insulating film in contact therewith, the monocrystal Ge thin layer having a thickness not more than 6 nm. The monocrystal Ge thin layer has a thickness not less than 2... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292834 - High performance transistors with hybrid crystal orientations: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the... Agent: Slater & Matsil, L.L.P.

20060292836 - Manufacturing method of polysilicon: A manufacturing method of polysilicon is provided. First, a substrate is provided, and an amorphous silicon layer is formed on the substrate. Then, a buffer layer is formed on the amorphous silicon layer, and a metal catalysis solution is applied onto the surface of the buffer layer, wherein the metal... Agent: Jianq Chyun Intellectual Property Office

20060292837 - Method and apparatus for modelling film grain patterns in the frequency domain: Film grain patterns can be modeled in the frequency domain by estimating the cut frequencies that define a 2D band-pass filter. The film grain parameters can be conveyed in accordance with the ITU-T H.264|MPEG-4 AVC standard in an SEI message allowing film grain reinsertion at a decoder.... Agent: Thomson Licensing Inc.

20060292838 - Ion implanting methods: An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received over the features and which has an opening therein... Agent: Wells St. John P.s.

20060292839 - Contacts fabric using heterostructure of metal/semiconductor nanorods and fabrication method thereof: Provided are a contact fabric using a heterostructure of metal/semiconductor nanorods and a method of manufacturing the same. An ohmic contact fabric having a low contact resistance or a Schottky contact fabric having a rectification characteristic is formed by selectively depositing metal of nano-sizes onto predetermined portions of zinc oxide/semiconductor... Agent: Rothwell, Figg, Ernst & Manbeck, P.C.

20060292841 - Atomic layer deposition systems and methods including metal beta-diketiminate compounds: The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one β-diketiminate ligand. Such systems and methods can be useful for depositing metal-containing layers on substrates.... Agent: Mueting, Raasch & Gebhardt, P.A.

20060292840 - Thermally conductive grease and methods and devices in which said grease is used: A thermally conductive grease includes (A) a polyorganosiloxane having a viscosity less than 50 cSt (mm2/s) at 25° C. and (B) a thermally conductive filler. The thermally conductive grease is useful as a thermal interface material for electronic devices.... Agent: Dow Corning Corporation Co1232

20060292842 - Self-aligned gate and method: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then... Agent: Stmicroelectronics, Inc.

20060292843 - Method for fabricating semiconductor device: Provided is a method for fabricating a semiconductor device, capable of increasing a contact open margin and minimizing a shoulder loss of a gate line. The method includes: forming a gate line on a substrate, the gate line including a first hard mask and a second hard mask; forming an... Agent: Blakely Sokoloff Taylor & Zafman

20060292844 - Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric: A method of forming a silicon oxynitride gate dielectric. The method includes incorporating nitrogen into a dielectric film using a plasma nitridation process to form a silicon oxynitride film. The silicon oxynitride film is annealed in a first ambient. The first ambient comprises an inert ambient with a first partial... Agent: Patterson & Sheridan, LLP

20060292846 - Material management in substrate processing: Substrate processing systems and methods are described for processing substrates. The processing includes transferring electronic identification (ID) information of one or more materials contained in one or more processing subsystems. Materials are transferred between one or more material containers and respective one or more process cells during transfer events of... Agent: Courtney Staniford & Gregory LLP

20060292848 - Method for manufacturing nano-gap electrode device: Provided is a method for manufacturing a nano-gap electrode device comprising the steps of: forming a first electrode on a substrate; forming a spacer on a sidewall of the first electrode; forming a second electrode on an exposed substrate at a side of the spacer; and forming a nano-gap between... Agent: Mayer, Brown, Rowe & Maw LLP

20060292845 - Processing substrates using site-isolated processing: Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one... Agent: Courtney Staniford & Gregory LLP

20060292847 - Silver barrier layers to minimize whisker growth in tin electrodeposits: The invention relates to a method of reducing tin whisker formation in a plated substrate that includes a surface layer comprising tin. The method includes providing on electroplatable portions of the substrate (a) an underlayer comprising silver or (b) a barrier layer that passes a mechanical load test when the... Agent: Winston & Strawn LLP Patent Department

20060292849 - Ultrathin semiconductor circuit having contact bumps and corresponding production method: The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor... Agent: Brinks Hofer Gilson & Lione

20060292851 - Circuitry component and method for forming the same: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and... Agent: North America Intellectual Property Corporation

20060292850 - Method for manufacturing semiconductor device and non-volatile memory: A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a... Agent: Jianq Chyun Intellectual Property Office

20060292852 - Back end interconnect with a shaped interface: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner... Agent: International Business Machines Corporation Dept. 18g

20060292855 - Current-aligned auto-generated non-equiaxial hole shape for wiring: A method, system and program product for replacing isotropic hole shapes in a wiring layout with non-equiaxial hole shapes that are arranged in a direction of current flow, which increases current flow along the wire's longitudinal axis while decreasing current flow along the wire's transverse axis. One aspect of the... Agent: Hoffman, Warnick & D'alessandro LLC

20060292854 - Manufacturing method of dual damascene structure: A manufacturing method of a dual damascene structure is provided. First, a barrier layer, a first dielectric layer, a second dielectric layer, a cap layer, a metal-containing hard mask layer, a dielectric hard mask layer, a first bottom anti-reflection coating (BARC) layer and a first photoresist layer are sequentially formed... Agent: Jianq Chyun Intellectual Property Office

20060292853 - Method for fabricating an integrated semiconductor circuit and semiconductor circuit: The present invention relates to a method for fabricating an integrated semiconductor circuit having a conductor structure buried in a semiconductor substrate, and to an integrated semiconductor circuit, in which case the integrated semiconductor circuit may be an application specific semiconductor circuit or a semiconductor circuit that can be adapted... Agent: Morrison & Foerster LLP

20060292856 - Method of patterning a porous dielectric material: A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other... Agent: Intel Corporation

20060292857 - Methods for making integrated-circuit wiring from copper, silver, gold, and other metals: Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292858 - Techniques to create low k ild for beol: One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060292859 - Damascene process using dielectic layer containing fluorine and nitrogen: An improved damascene process for fabricating a semiconductor device. A dielectric layer comprising at least both fluorine and nitrogen is formed overlying a substrate, in which a nitrogen content in the dielectric layer is about 5% to 10%. The dielectric layer is subsequently pattered to form at least one damascene... Agent: Birch Stewart Kolasch & Birch

20060292860 - Prevention of post cmp defects in cu/fsg process: A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG... Agent: Haynes And Boone, LLP

20060292861 - Method for making integrated circuit chip having carbon nanotube composite interconnection vias: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20060292862 - Method for forming barrier metal of semiconductor device: A method for forming a barrier metal of a semiconductor device includes forming an insulating layer on a semiconductor substrate and forming an opening in the insulating layer and forming a TiSiN layer having a desired thickness by repeatedly performing a process of forming a TiSiN layer having an atomic... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20060292863 - Preventing damage to metal using clustered processing and at least partially sacrificial encapsulation: Methods are disclosed for metal encapsulation for preventing exposure of metal during semiconductor processing. In one embodiment, the method includes forming an opening in a structure exposing a metal surface in a bottom of the opening, where the opening forming step occurs in a tool including at least one clustered... Agent: Hoffman, Warnick & D'alessandro LLC

20060292864 - Plasma-enhanced cyclic layer deposition process for barrier layers: In one embodiment, a method for forming a metal-containing material on a substrate is provided which includes forming a metal containing barrier layer on a substrate by a plasma-enhanced cyclical vapor deposition process, exposing the substrate to a soak process, and depositing a conductive material on the substrate by a... Agent: Patent Counsel Applied Materials, Inc.

20060292865 - Semiconductor device: A semiconductor device of the present invention has a first conductive layer, a second conductive layer, an insulating layer which is formed between the first conductive layer and the second conductive layer and which has a contact hole, and a third conductive layer which is connected to the first conductive... Agent: Eric Robinson

20060292866 - Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method: Embodiments of the present invention are directed to a process for forming small diameter vias at low temperatures. In preferred embodiments, through-substrate vias are fabricated by forming a through-substrate via; and depositing conductive material into the via by means of a flowing solution plating technique, wherein the conductive material releases... Agent: Koppel, Patrick & Heybl

20060292867 - Method of forming metal line in semiconductor device: The present invention provides a method of forming metal lines in a semiconductor device having advantages of preventing an “explosion” phenomenon during a dual damascene process so as to improve the yield of the device. An exemplary embodiment of the present invention includes removing etching residues by wet cleaning the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20060292868 - Surface emitting semiconductor laser: A method of forming a conductive pattern such as an electrode on a compound semiconductor layer includes the steps of forming a first organic layer on the compound semiconductor layer, forming a second layer on the first organic layer, the second layer being resistant to plasma ashing, forming a pattern... Agent: Oliff & Berridge, PLC

20060292869 - Tungsten plug corrosion prevention method using ionized air: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one... Agent: Campbell Stephenson Ascolese, LLP

20060292870 - A method of synthesizing nanoscale filamentary structures and electronic components comprising such structures: A method of synthesizing electronic components incorporating nanoscale filamentary structures in which method a metallic catalyst is deposited in a nanoporous membrane, the catalyst being adapted to penetrate in at least some of the pores of the nanoporous membrane, and filamentary structures are grown on the catalyst in at least... Agent: Miller, Matthis & Hull

20060292872 - Atomic layer deposition of thin films on germanium: Germanium has higher mobility than silicon and therefore is considered to be a good alternative semiconductor for CMOS technology. Surface treatments a can facilitate atomic layer deposition (ALD) of thin films, such as high-k dielectric layers, on germanium substrates. Surface treatment can comprise the formation of a thin layer of... Agent: Knobbe Martens Olson & Bear LLP

20060292871 - Methods of forming titanium-containing materials, and semiconductor processing methods: The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance, the invention can utilize alternating cycles of titanium tetrachloride and activated hydrogen to form... Agent: Wells St. John P.s.

20060292873 - Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same: The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In some embodiments, the metal-containing compounds are homoleptic complexes that include unsymmetrical β-diketiminate ligands. In other embodiments, the metal-containing compounds are heteroleptic complexes including at least one β-diketiminate ligand.... Agent: Mueting, Raasch & Gebhardt, P.A.

20060292874 - method for forming tungsten materials during vapor deposition processes: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to a first reducing gas and a tungsten precursor gas to form a... Agent: Patterson & Sheridan, LLP

20060292875 - Method for enhancing electrode surface area in dram cell capacitors: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode,... Agent: Whyte Hirschboeck Dudek S.c.

20060292876 - Plasma etching method and apparatus, control program and computer-readable storage medium: In a method for plasma etching a wafer laminated with a target layer, a lower organic layer, an intermediate layer and an upper resist layer in that order from bottom, the method includes following steps: patterning the upper resist layer by exposure and development, plasma etching the intermediate layer by... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060292878 - Method for fabricating semiconductor element: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes the steps of: preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide... Agent: Volentine Francos, & Whitt PLLC

20060292879 - Method for peeling off semiconductor element and method for manufacturing semiconductor device: A method for peeling off a thin film semiconductor element over an insulating surface by using a void, and a method for manufacturing a semiconductor device by transferring the peeled semiconductor element. According to the peeling method of the invention, a first base layer having a plurality of recessed portions... Agent: Eric Robinson

20060292877 - Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures: Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross section and a second portion in the... Agent: Trask Britt, P.C.

20060292880 - Methods of fabricating p-type transistors including germanium channel regions and related devices: A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-crystalline germanium layer may be selectively locally heated,... Agent: Myers Bigel Sibley & Sajovec

20060292882 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming a hard mask layer on the inter-layer insulation layer; etching the hard mask layer using a contact mask; and etching the inter-layer insulation layer using the hard mask layer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060292881 - Method of encapsulating an assembly with a low temperature silicone rubber compound: A method for encapsulating an assembly with a methyl phenyl silicone rubber compound is provided. In various embodiments, the method can include exposing the assembly to a solvent, plasma etching the assembly, and producing a potting mixture, wherein the potting mixture comprises a methyl phenyl room temperature vulcanization silicone and... Agent: Kurt A. Luther Honeywell International, Inc.

20060292883 - Etching of silicon nitride with improved nitride-to-oxide selectivity utilizing halogen bromide/chlorine plasma: A method of manufacturing a semiconductor device is disclosed. A gate is formed on a semiconductor substrate. A gate oxide is formed between the gate and the semiconductor substrate. A silicon oxide liner layer is deposited on the gate and on the semiconductor substrate. A silicon nitride layer is then... Agent: North America Intellectual Property Corporation

20060292884 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a polysilicon layer, a silicide layer and a hard mask over a semiconductor substrate, etching the silicide layer using the hard mask as an etch barrier, shaping the silicide layer with a predetermined profile using a mixed gas, and etching the... Agent: Blakely Sokoloff Taylor & Zafman

20060292885 - Layout modification to eliminate line bending caused by line material shrinkage: A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, such that the patterning comprises at least one support feature... Agent: Texas Instruments Incorporated

20060292886 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes sequentially forming etch target layers, a hard mask layer and an anti-reflective coating layer, selectively etching the anti-reflective coating layer and the hard mask layer using a gas generating polymers, thereby increasing a line width of a bottom... Agent: Blakely Sokoloff Taylor & Zafman

20060292887 - Manufacturing method for a semiconductor device: A manufacturing method for a semiconductor device, includes: preparing a semiconductor wafer having an active surface, a side surface, a rear surface on the side opposite the active surface, and a plurality of semiconductor elements formed on the active surface; forming the side surface of the semiconductor wafer so that... Agent: Harness, Dickey & Pierce, P.L.C

20060292888 - Etchant, method for fabricating interconnection line using the etchant, and method for fabricating thin film transistor substrate using the etchant: An etchant, a method for fabricating a multi-layered interconnection line using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant for the multi-layered line comprised of molybdenum/copper/molybdenum nitride illustratively includes 10-20 wt % hydrogen peroxide, 1-5 wt % organic acid, a... Agent: Macpherson Kwok Chen & Heid LLP

20060292889 - Finfet including a superlattice: A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers. Each group of... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20060292890 - Method and device for the production of a silicon single crystal, silicon single crystal, and silicon semiconductor wafers with determined defect distributions: A method for the production of a silicon single crystal by pulling the single crystal, according to the Czochralski method, from a melt which is held in a rotating crucible, the single crystal growing at a growth front, heat being deliberately supplied to the center of the growth front by... Agent: Brooks Kushman P.C.

20060292891 - Cascade source and a method for controlling the cascade source: A cascade source includes a cathode housing, a number of cascade plates insulated from each other and stacked on top of each other which together bound at least one plasma channel, and an anode plate provided with an outflow opening connecting to the plasma channel. One cathode is provided per... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20060292892 - Sacrificial benzocyclobutene copolymers for making air gap semiconductor devices: A method of forming an air gap within a semiconductor structure by the steps of: (a) using a sacrificial polymer to occupy a space in a semiconductor structure; and (b) heating the semiconductor structure to decompose the sacrificial polymer leaving an air gap within the semiconductor structure, wherein the sacrificial... Agent: The Dow Chemical Company

20060292893 - Masking without photolithography during the formation of a semiconductor device: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely spaced regions, such as a memory transistor array, and widely spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the... Agent: Micron Technology, Inc.

20060292894 - Gapfill using deposition-etch sequence: Methods deposit a film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. Flows of first precursor deposition gases are provided to the substrate processing chamber. A first high-density plasma is formed from the flows of first deposition gases to... Agent: Applied Materials, Inc. Legal Affairs Department

20060292896 - Heater for heating a wafer and method for preventing contamination of the heater: A method for preventing contamination of a heater which is used for heating a wafer with a wafer bevel contains not directly heating the wafer bevel when using the heater to heat the wafer.... Agent: North America Intellectual Property Corporation

20060292895 - Method for thermal processing a semiconductor wafer: A method for thermal processing a semiconductor wafer is disclosed. A rapid thermal processing (RTP) chamber encompasses a heating means, a rotation means, and a cooling system for cooling walls of said RTP chamber. A semiconductor wafer is loaded into the RTP chamber just being cooling down to a first... Agent: North America Intellectual Property Corporation

20060286686 - Integrated light emitting diode displays using biofabrication: A method of manufacturing an integrated light emitting diode display is provided. In one exemplary embodiment, the method includes the step of biologically forming a pn junction over a substrate, the pn junction capable of emitting a light having a predetermined color upon the application of energy thereto. In another... Agent: Honeywell International Inc.

20060286688 - Integrated circuitry and method for manufacturing the same: The integrated circuitry on a semiconductor substrate includes an integrated circuit arranged in a circuit area of the semiconductor substrate and a stress-sensitive structure on the semiconductor substrate for detecting a mechanical stress component in the semiconductor substrate, wherein the stress-sensitive structure is implemented to provide an output signal depending... Agent: Baker Botts, L.L.P.

20060286687 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device includes the steps of forming a circuit element on a semiconductor substrate, forming an insulation film covering the circuit element, forming a first electrode on the insulation film, forming a ferroelectric film on the first electrode, forming a second electrode on the ferroelectric... Agent: GlobalIPCounselors, LLP

20060286689 - Semiconductor device and manufacturing method thereof: A metal wire for inspection and an electrode for inspection are formed on a region of a semiconductor substrate where a metal wire and an electrode for external connection are not formed. The metal wire for inspection and the electrode for inspection electrically detect an open failure, a short-circuit failure... Agent: Steptoe & Johnson LLP

20060286690 - Mask cd correction based on global pattern density: The present disclosure provide a method of forming a photomask layout. In one example, the method comprises selecting a pattern feature on the photomask layout, defining a global area centered at the pattern feature on the photomask layout, calculating a pattern density inside the global area, and correcting the pattern... Agent: Haynes And Boone, LLP

20060286691 - Capacitance modeling: A method of modeling capacitance for all practical 2D on-chip wire structures including coplanar and microstrip structures. The method includes using a field lines approach (600) to obtain capacitance expressions for structure components, combining the expressions (704) for components of the subject structure and obtaining a capacitance expression (705) for... Agent: Stephen C. Kaufman IBM Corporation

20060286693 - Fabrication of three-dimensional photonic crystals in gallium arsenide-based material: The present invention is an efficient method for the fabrication of three-dimensional structures in GaAs-based materials. The method is particularly suitable for the realization of 3D photonic crystals. The method relies on the observation that the oxidation rate of Ga1-xA1xAs in water-vapor atmosphere is a strong function of the aluminum... Agent: Connolly Bove Lodge & Hutz LLP

20060286694 - Method for fabricating led: A high etching selective layer and a light emitting structure are formed subsequently on a semiconductor substrate. Then, a p-type Ohmic contact layer and a metal substrate are formed subsequently on the light emitting structure. The semiconductor substrate and the high etching selective layer are removed. Next, an n-type electrode... Agent: Bacon & Thomas, PLLC

20060286692 - Method for manufacturing semiconductor element, apparatus for manufacturing semiconductor element and semiconductor element: A method for manufacturing a semiconductor element includes an oxidation step of forming an oxidized layer in a semiconductor substrate by an oxidizing gas, wherein the oxidation step is conducted for the semiconductor substrate in a plurality of divided steps.... Agent: Harness, Dickey & Pierce, P.L.C

20060286695 - Method for producing semiconductor light emitting device, method for producing semiconductor device, method for producing device, method for growing nitride type iii-v group compound semiconductor layer, method for growing semiconductor layer, and method: A method for producing a semiconductor light emitting device is disclosed. The method comprises the step of growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality... Agent: Sonnenschein Nath & Rosenthal Sears Tower

20060286697 - Method for manufacturing light emitting diodes: A method for manufacturing the LEDs is disclosed, whereby the light extraction efficiency of the device can be enhanced by forming patterns on a top surface of a substrate, a light emitting structure is formed on the top surface of the substrate formed with the patterns, the substrate is removed... Agent: Song K. Jung Mckenna Long & Aldridge LLP

20060286696 - Passive electrical article: A passive electrical article includes a first electrically conductive substrate having a major surface and a second electrically conductive substrate having a major surface. The major surface of the second substrate faces the major surface of the first substrate. An electrically resistive layer is on at least one of the... Agent: 3m Innovative Properties Company

20060286698 - Electro-optical device, method of manufacturing the same, and electronic apparatus: An electro-optical device includes: a substrate; a plurality of data lines which are formed on the substrate; a plurality of scanning lines which are arranged on the substrate so as to intersect the plurality of data lines; a plurality of pixel electrodes which are provided on the substrate so as... Agent: Advantedge Law Group, LLC

20060286701 - Apparatus for inspecting alignment film and method for fabricating liquid crystal display device using the same: An apparatus for inspecting an alignment film and a method for fabricating a liquid crystal display device using the same are disclosed. By changing a spraying structure of a steam inspecting unit to check whether an alignment film is defective or not, a water splash phenomenon can be prevented and... Agent: Mckenna Long & Aldridge LLP

20060286700 - Apparatus for stacking cassette and a method of fabricating a liquid crystal display device using the same: A cassette stacking apparatus is provided. The cassette stacking apparatus includes a first loading unit that loads or unloads a cassette. The cassette stacking apparatus also has a stacking unit disposed at a side of the loading unit, wherein an upper portion of the stacking unit forms a shelf which... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20060286699 - Fabricating method for flat panel display device: A fabricating method for a flat panel display device having a thin film pattern over a substrate is disclosed. The fabricating method includes depositing a hydrophilic resin over a substrate and patterning the hydrophilic resin to form hydrophilic resin patterns over areas outside where thin film patterns are to be... Agent: Morgan Lewis & Bockius LLP

20060286702 - Method of manufacturing a transparent element including transparent electrodes: f

20060286703 - Thin film transistor array panel and liquid crystal display including the same: A thin film transistor array includes first and second gate lines and a storage electrode line with a storage electrode formed on a substrate, where a gate insulating layer covers the gate and the storage electrode lines, a data line crossing the first and second gate lines in an insulating... Agent: F. Chau & Associates, LLC

20060286704 - Pattern forming method, device, method of manufacture thereof, electro-optical apparatus, and electronic apparatus: A method of forming a predetermined pattern by disposing a functional liquid on a substrate, the method includes the steps of forming banks on the substrate, and disposing the functional liquid on a region divided by the banks, wherein a width of the region is partially formed so as to... Agent: Oliff & Berridge, PLC

20060286705 - Method of passivating compound semiconductor surfaces: The invention discloses a method of passivating compound semiconductor surfaces aligned to the {110} crystal planes, and devices incorporating said passivated surfaces.... Agent: David Garrod, Ph.d., Esq. Goodwin Procter LLP

20060286706 - Method of making a substrate contact for a capped mems at the package level: Methods have been provided for forming a micro-electromechanical systems (“MEMS”) device (100) from a substrate (500) comprising a handle layer (108) and a cap (132) overlying the handle layer (108). In one exemplary embodiment, the method includes cutting through the substrate (500) to separate the substrate (500) into a first... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060286707 - Substrate contact for a capped mems and method of making the substrate contact at the wafer level: A MEMS device (100) is provided that includes a handle layer (108) having a sidewall (138), a cap (132) overlying said handle layer (108), said cap (132) having a sidewall (138), and a conductive material (136) disposed on at least a portion of said sidewall of said cap (138) and... Agent: Ingrassia, Fisher & Lorenz, P.C.

20060286708 - Image sensor and pixel having an optimized floating diffusion: An active pixel includes a a photosensitive element formed in a semiconductor substrate. A transfer transistor is formed between the photosensitive element and a floating diffusion and selectively operative to transfer a signal from the photosensitive element to the floating diffusion. The floating diffusion is formed from an n-type implant... Agent: Perkins Coie LLP Patent-sea

20060286709 - Manufacturing methods for thin film fuse phase change ram: A method for manufacturing a memory device comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures. The electrode layer includes a first electrode and a second electrode, and an insulating member between the first and second electrodes for each phase change memory cell to... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20060286710 - Method for bonding substrates, bonded substrate, and direct bonded substrare: The present invention relates to a method for laminating substrates, including the steps of locating a surface of a first substrate and a surface of a second substrate at positions close to each other or partially bringing them in contact with each other; supplying a volatile liquid between the surface... Agent: Wenderoth, Lind & Ponack L.L.P.

20060286713 - Methods of fabricating semiconductor devices including trench device isolation layers having protective insulating layers and related devices: A method of fabricating a semiconductor device includes forming an active region including opposing sidewalls and a surface therebetween protruding from a substrate. A protective insulating layer is formed on the sidewalls of the active region, and extends away from the substrate to beyond the surface of the active region.... Agent: Myers Bigel Sibley & Sajovec

20060286714 - Semiconductor device and system having semiconductor device mounted thereon: There is provided a semiconductor device that is capable of reducing wring density of the wiring pattern on a mounting board on which it is mounted, thereby facilitating routing of the wiring pattern. Pads are formed which are connected to pads on a bare chip by bonding wires. There are... Agent: Katten Muchin Rosenman LLP

20060286711 - Signal isolation in a package substrate: Signal traces are patterned on a top surface of a substrate. A ground trace is patterned on the top surface of the substrate for at least one pair of the signal traces. A die paddle is patterned on the top surface of the substrate, and the die paddle is connected... Agent: Triquint Semiconductor, Inc.

20060286712 - Thermal interface with a patterned structure: An interface is formed by pressing a patterned first surface and a second surface together, with a particle-loaded interface material in between. The first surface is fabricated with a pattern of channels designed to redistribute the velocity gradients that occur in the interface material during interface formation in order to... Agent: Anne Vachon Dougherty

20060286715 - Manufacturing method of semiconductor integrated circuit device: During probe testing using a prober having probe needles formed by using a manufacturing technology for a semiconductor integrated circuit device, reliable contact is ensured between the probe needles and test pads. A pressing tool having at least one hole portion formed therein and extending therethrough between the main and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060286716 - Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package: A method for producing a flip-chip mounting electronic component having plural terminals (3) dotted on a mounting face (1) and conductors formed on the terminals (3) realizes flip-chip mounting capable of shortening the distance between bumps (7). To realize this, a step of coating the mounting face (1) with a... Agent: Patent Docket Clerk Cowan, Liebowitz & Latman, P.C.

20060286718 - Manufacturing method capable of simultaneously sealing a plurality of electronic parts: A method of manufacturing an electronic part includes a first step of forming a predetermined circuit pattern on a base substrate body 11 having a wafer shape in each device forming region 11a; a second step of disposing a mounting substrate body 12 having a wafer shape to face the... Agent: Beyer Weaver & Thomas, LLP

20060286717 - Stacked microelectronic assemblies having basal compliant layers: A method of making a stacked microelectronic assembly includes providing a flexible substrate having first and second ends, the flexible substrate having a plurality of attachment sites located between the first and second ends thereof including a first one of the attachment sites located adjacent the first end of the... Agent: Tessera Lerner David Et Al.

20060286719 - Semiconductor packages and methods of manufacturing thereof: Described are semiconductor package devices with improved reliability and methods of manufacturing thereof. In one embodiment, a package device is disclosed that includes a chip having an active surface and a coupling surface opposite the active surface, where the chip has one or more integrated circuits and bumps. The device... Agent: Baker & Mckenzie On Behalf Of Tsmc

20060286720 - Method for fabricating nonvolatile semiconductor memory device: An adhesion layer composed of a titanium film and a titanium nitride film is formed by CVD on the inner wall of a contact hole formed in a multilayer film composed of an interlayer insulating film, a silicon nitride film, and a silicon dioxide film. Then, a conductive film made... Agent: Mcdermott Will & Emery LLP

20060286721 - Breakable interconnects and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include placing an anisotropic conductive layer comprising at least one compliant conductive sphere on at least one interconnect structure disposed on a first substrate, applying pressure to contact the compliant conductive spheres to the at least one interconnect... Agent: Blakely Sokoloff Taylor & Zafman

20060286722 - Methods for making microwave circuits: Disclosed are methods for making microwave circuits using thickfilm components. In an embodiment, the method includes depositing a dielectric over a ground plane, and then forming a conductor on the dielectric. The conductor is formed by depositing a conductive thickfilm on the dielectric and then “subsintering” the conductive thickfilm. In... Agent: Agilent Technologies, Inc. Legal Department, Dl429

20060286723 - Electrode structure, fabrication method thereof and pdp utilizing the same: An electrode structure for a front board of a plasma display panel (PDP). The electronic structure connects all the sustain electrodes on the front board to prevent data transformation errors caused by holes. The fabrication method of the electronic structure is also disclosed.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060286724 - Substrate backgate for trigate fet: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20060286726 - Forming interconnects: A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least on insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localized region of the insulating layer so as... Agent: Sughrue Mion, PLLC

20060286725 - Method for manufacturing thin film transistors: A method for manufacturing TFTs is provided. It can be applied to both inverted staggered and co-planar TFT structures. The manufacturing method for the staggered TFT includes the formation of a gate electrode, a gate insulator, an active channel layer, a drain electrode, and a source electrode on a substrate.... Agent: Lin & Associates Intellectual Property

20060286727 - Polycrystalline silicon liquid crystal display device and fabrication method thereof: A method for fabricating a poly-silicon liquid crystal display device includes forming a poly-silicon layer including a TFT region and a storage capacitor region on a substrate, wherein the capacitor region includes an impurity injection region having a N-type impurity injection region and a P-type impurity injection region; forming a... Agent: Mckenna Long & Aldridge LLP

20060286728 - Method for forming recess gate of semiconductor device: A method for forming a recess gate of a semiconductor device secures a sufficient overlap margin between a recess gate region and a gate electrode to prevent a phenomenon resulting from mis-alignment when a recess gate electrode is formed, thereby improving process defects and minimizing Vt movement between cells.... Agent: Heller Ehrman White & Mcauliffe LLP

20060286729 - Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a... Agent: Trop Pruner & Hu, PC

20060286735 - Integrated circuit transistor insulating region fabrication method: A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped... Agent: Slater & Matsil, L.L.P.

20060286733 - Method for manufacturing a semiconductor element: A method for manufacturing a semiconductor element, comprises: (1) forming a first insulating layer for electric field relaxation that is thicker than a first gate insulating layer in a first channel region of a transistor of a first conductive type that is one of P-type and N-type polarity formed on... Agent: Hogan & Hartson L.L.P.

20060286731 - Method of fabricating conductive lines and structure of the same: A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer... Agent: J C Patents, Inc.

20060286734 - Mim/mis structure with praseodymium titanate or praseodymium oxide as insulator material: Disclosed is an electronic device with a layer succession of the metal-insulator-metal (MIM) or metal-insulator-semiconductor (MIS) kind. The insulator layer contains or consists of praseodymium titanate. A metal layer or both metal layers contain titanium nitride (TiN), tantalum nitride (TaN) or ruthenium oxide (RuO2) or consist of one of those... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20060286732 - Power semiconductor device: A power semiconductor device that includes a plurality of gate structure each having a gate insulation of a first thickness, and a termination region, the termination including a field insulation body surrounding the active region and having a recess that includes a bottom insulation thicker than the first thickness.... Agent: Ostrolenk Faber Gerb & Soffen

20060286730 - Semiconductor structure and method for forming thereof: A semiconductor structure and a method for forming the semiconductor structure are provided. The method for forming a semiconductor structure of the present invention may include the following steps. First, a substrate is provided, wherein a gate is formed over the substrate, and a plurality of offspacers are formed over... Agent: J C Patents, Inc.

20060286736 - Method for forming an electronic device: An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer... Agent: Larson Newman Abel Polansky & White, LLP

20060286737 - Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby: A thin film transistor comprises a zinc-oxide-containing semiconductor material. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor device, wherein the substrate temperature is no more than 300° C.... Agent: Paul A. Leipold Patent Legal Staff

20060286738 - Method of forming floating-gate tip for split-gate flash memory process: A split-gate flash memory process for improving sharpness and height of a floating-gate tip has steps as follows. Using a dry etching process, a trench is formed in the first polysilicon layer through the pattern opening. An oxide layer is then deposited on the first polysilicon layer through a CVD... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060286739 - Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures: A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also etched to form a second trench therein overlying... Agent: Hitt Gaines, PC Agere Systems Inc.

20060286740 - A method for forming a device having multiple silicide types: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide... Agent: Haynes And Boone, LLP

20060286742 - Method for fabrication of surface mounted metal foil chip resistors: The present invention provides a method for fabricating metal foil chip resistors, comprising: providing an insulator substrate; forming a conductor layer pattern as a terminal electrode on said insulator substrate; adhering a metal foil having specific resistivity to said insulator substrate; applying the resistor wiring pattern upon said metal foil... Agent: Bacon & Thomas, PLLC

20060286743 - Method for manufacturing a narrow structure on an integrated circuit: A method of manufacturing for providing a narrow line, such as a phase change bridge, on a substrate having a top surface, includes first forming a layer of first material on the substrate. Then, a layer of a pattern material is applied on the layer of first material, and a... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20060286741 - Methods of fabricating high voltage devices: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer... Agent: Texas Instruments Incorporated

20060286744 - Semiconductor device suitable for forming conductive film such as platinum with good coverage, and its manufacture: A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal, nitride of refractory metal, and siliconized nitride of refractory metal. An oxide surface layer is disposed on the surface... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060286745 - Semiconductor device having a capacitor with a stepped cylindrical structure and method of manufacturing the same: According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric... Agent: Marger Johnson & Mccollom, P.C.

20060286746 - Flash memory and fabricating method thereof: A flash memory includes substrate, control gates, trenches, source regions, isolation structures, drain regions, a common source line, floating gates, tunneling dielectric layers, and dielectric layer. The control gates and the trenches are in first and second directions on the substrate, respectively. The source regions are in the substrate and... Agent: J C Patents, Inc.

20060286747 - Floating-gate structure with dielectric component: Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20060286748 - Terraced film stack: A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.... Agent: Dinsmore & Shohl LLP One Dayton Centre

20060286749 - Method of fabricating non-volatile memory: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell comprises a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells.... Agent: Jianq Chyun Intellectual Property Office

20060286750 - Method and system for forming straight word lines in a flash memory array: Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of... Agent: Wagner, Murabito & Hao LLP

20060286751 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate; an element region having a semiconductor element including an impurity layer and a trench, wherein the impurity layer is disposed in the trench, and wherein the trench is disposed on a main surface of the substrate; and a field region disposed around the... Agent: Posz Law Group, PLC

20060286752 - Method of fabricating non-volatile memory: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells.... Agent: Jianq Chyun Intellectual Property Office

20060286753 - Method for producing a stop zone in a semiconductor body and semiconductor component having a stop zone: A method for producing a buried stop zone in a semiconductor body and a semiconductor component having a stop zone, has the method steps of: providing a semiconductor body having a first and a second side and a basic doping of a first conduction type, irradiating the semiconductor body via... Agent: Baker Botts, L.L.P.

20060286754 - Semiconductor device with interface circuit and method of configuring semiconductor devices: Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid... Agent: SprinkleIPLaw Group

20060286755 - Method for fabricating transistor with thinned channel: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.... Agent: Blakely Sokoloff Taylor & Zafman

20060286756 - Semiconductor process and method for reducing parasitic capacitance: A semiconductor processes is described. A substrate having trench isolation structures and dummy trench isolation structures thereon is provided. Gate structures and dummy gate structures are simultaneously formed on the substrate. Spacers are formed on the sidewalls of the gate structures and the dummy gate structures. A patterned blocking layer... Agent: Jianq Chyun Intellectual Property Office

20060286757 - Semiconductor product and method for forming a semiconductor product: The invention provides a semiconductor product (25) and a method for forming the semiconductor product (25), the semiconductor product (25) comprising a transistor (1) having first (11) and second source/drain regions (12) being arranged at bottom surfaces (B) of recesses (R) in a substrate (2). Due to the depth (d)... Agent: Slater & Matsil LLP

20060286758 - Super anneal for process induced strain modulation: A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so... Agent: Slater & Matsil, L.L.P.

20060286759 - Metal oxide semiconductor (mos) device having both an accumulation and a enhancement mode transistor device on a similar substrate and a method of manufacture therefor: The present invention provides a metal oxide semiconductor (MOS) device, a method of manufacture therefore, and an integrated circuit including the same. The metal oxide semiconductor (MOS) device (100), without limitation, may include a first accumulation mode transistor device (120, 160) located over or in a substrate (110), as well... Agent: Texas Instruments Incorporated

20060286760 - Electrode for an electrical component, component with the electrode, and manufacturing method for the electrode and the component: An electrical component, which contains an electrode with an electrically conductive body having a dielectric surface. An amorphous layer comprising SiO2, having a specific surface area of approximately 50 to 500 m2/g, is arranged on the body. An electrically conductive coating is arranged on the amorphous layer. A solid electrolyte... Agent: Cohen, Pontani, Lieberman & Pavane

20060286761 - Wet electrolytic capacitors: A wet electrolytic capacitor that includes an anode, cathode, and a liquid electrolyte disposed therebetween is provided. The cathode contains a metal oxide coating, such as NbO2, in conjunction with other optional coatings to impart improved properties to the capacitor.... Agent: Dority & Manning, P.A.

20060286762 - Method for non-volatile memory fabrication: A method for non-volatile memory fabrication is provided, in which a substrate is provided, a bottom electrode is formed on the substrate, a solution with precursors of Zr and Sr is coated on the bottom electrode, the solution on the bottom electrode surface is dried and then fired to form... Agent: Birch Stewart Kolasch & Birch

20060286763 - Gate electrode dopant activation method for semiconductor manufacturing: Embodiments of the invention generally provide a method for forming a doped silicon-containing material on a substrate. In one embodiment, the method provides depositing a polycrystalline layer on a dielectric layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer having a dopant concentration within... Agent: Patterson & Sheridan, LLP

20060286764 - Deposition-selective etch-deposition process for dielectric film gapfill: A deposition/etching/deposition process is provided for filling a gap in a surface of a substrate. A liner is formed over the substrate so that distinctive reaction products are formed when it is exposed to a chemical etchant. The detection of such reaction products thus indicates that the portion of the... Agent: Townsend And Townsend And Crew LLP / Amat

20060286766 - Isolation structures for preventing photons and carriers from reaching active areas and methods of formation: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching... Agent: Dickstein Shapiro LLP

20060286765 - Method for manufacturing element isolation structural section: A plurality of element forming regions and an element isolation structural section forming region which separates the plurality of element forming regions from one another, are set to a substrate. A first thermal oxide film is formed. An HfSiON film is formed. Heating processing is done. A silicon nitride film... Agent: Volentine Francos, & Whitt PLLC

20060286768 - Method of supporting microelectronic wafer during backside processing: A method of supporting a microelectronic wafer during backside processing. The method comprises: selecting a rigid carrier, an adhesive, and a radiation source to emit radiation at a predetermined wavelength range; forming a wafer-carrier stack by providing the adhesive between the wafer and the carrier and curing the adhesive to... Agent: Blakely Sokoloff Taylor & Zafman

20060286767 - Novel thinning process for 3 - dimensional integration via wafer bonding: First and second semiconductor wafers are bonded together, with at least one of the wafers having a first layer of silicon, an intermediate oxide layer and a second layer of silicon. The first silicon layer is initially mechanically reduced by around 80% to 90% of its thickness. The remaining silicon... Agent: Birch Stewart Kolasch & Birch

20060286771 - Layer transfer technique: A layer transfer technique in which a portion of a donor wafer is doped with positively charged hydrogen ions and positively charged helium ions before it is bonded to a portion of a handle wafer. Furthermore, the bonded wafers are annealed at one of two annealing temperatures, which determines whether... Agent: Blakely Sokoloff Taylor & Zafman

20060286770 - Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate: A method for producing a semiconductor structure that includes at least one useful layer on a substrate. This method includes providing a source substrate with a zone of weakness therein that defines a relatively thick useful layer between the zone of weakness and a front face of the source substrate;... Agent: Winston & Strawn LLP

20060286769 - Wafer demounting method, wafer demounting device, and wafer demounting and transferring machine: It is an object of the present invention to provide a wafer release method capable of releasing a wafer safely, simply and certainly and improving a wafer releasing rate, a wafer release apparatus and a wafer release transfer machine using the wafer release apparatus. A wafer release method of the... Agent: Rader Fishman & Grauer PLLC

20060286772 - Method of cross-section milling with focused ion beam (fib) device: A method of milling a cross section of a wafer and a milling device. The method includes a coarse scanning of at least two milling frames and a fine scanning of at least one milling frame. The milling device is adapted to cross-section milling of a wafer, said milling includes... Agent: Patent Counsel Applied Materials, Inc.

20060286773 - Wafer dicing process for optical electronic packing: A wafer dicing process for optical electronic packing is provided. The process includes: providing a first wafer (glass wafer) and a second wafer (interposer wafer); etching the second wafer to form a reference plane coordinate; laminating the first wafer on the second wafer, providing a third wafer (CMOS wafer); laminating... Agent: Birch Stewart Kolasch & Birch

20060286774 - Method for forming silicon-containing materials during a photoexcitation deposition process: Embodiments of the invention generally provide a method for depositing films or layers using a UV source during a photoexcitation process. The films are deposited on a substrate and usually contain a material, such as silicon (e.g., epitaxy, crystalline, microcrystalline, polysilicon, or amorphous), silicon oxide, silicon nitride, silicon oxynitride, or... Agent: Patterson & Sheridan, LLP

20060286775 - Method for forming silicon-containing materials during a photoexcitation deposition process: Embodiments of the invention generally provide a method for depositing films or layers using a UV source during a photoexcitation process. The films are deposited on a substrate and usually contain a material, such as silicon (e.g., epitaxy, crystalline, microcrystalline, polysilicon, or amorphous), silicon oxide, silicon nitride, silicon oxynitride, or... Agent: Patterson & Sheridan, LLP

20060286776 - Method for forming silicon-containing materials during a photoexcitation deposition process: Embodiments of the invention generally provide a method for depositing films or layers using a UV source during a photoexcitation process. The films are deposited on a substrate and usually contain a material, such as silicon (e.g., epitaxy, crystalline, microcrystalline, polysilicon, or amorphous), silicon oxide, silicon nitride, silicon oxynitride, or... Agent: Patterson & Sheridan, LLP

20060286777 - Method of fabricating nitride-based compound layer, gan substrate and vertical structure nitride-based semiconductor light emitting device: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The... Agent: Mcdermott Will & Emery LLP

20060286778 - Method of manufacturing dual orientation wafers: Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20060286779 - Patterned silicon-on-insulator layers and methods for forming the same: In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20060286781 - Crystal imprinting methods for fabricating subsrates with thin active silicon layers: Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a... Agent: James R. Nock IBM Corporation, Dept. 917

20060286780 - Method for forming silicon thin-film on flexible metal substrate: Disclosed are a method for forming a silicon thin-film on a substrate, and more particularly a method for forming a polycrystalline silicon thin-film of good quality on a flexible metal substrate. A metal substrate (110) is prepared and a surface of the metal substrate (110) is flattened. An insulation film... Agent: Daly, Crowley, Mofford & Durkee, LLP

20060286782 - Layer growth using metal film and/or islands: A solution for manufacturing a nitride-based heterostructure, semiconductor, device, or the like, by growing one or more layers using a metal film and/or nitride islands is provided. In an embodiment of the invention, a group-III nitride film is grown on a surface of a lower layer. The nitride film is... Agent: Hoffman Warnick & D'alessandro, LLC

20060286783 - Post-ion implant cleaning for silicon on insulator substrate preparation: A combination of a dry oxidizing, wet etching, and wet cleaning processes are used to remove particle defects from a wafer after ion implantation, as part of a wafer bonding process to fabricate a SOI wafer. The particle defects on the topside and the backside of the wafer are oxidized,... Agent: Patent Counsel Applied Materials, Inc.

20060286784 - Method for implantation of high dopant concentrations in wide band gap materials: A method that combines alternate low/medium ion dose implantation with rapid thermal annealing at relatively low temperatures. At least one dopant is implanted in one of a single crystal and an epitaxial film of the wide band gap compound by a plurality of implantation cycles. The number of implantation cycles... Agent: Los Alamos National Security, LLC

20060286785 - A stretchable form of single crystal silicon for high performance electronics on rubber substrates: The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant... Agent: Greenlee Winner And Sullivan P C

20060286786 - Method and apparatus for increase strain effect in a transistor channel: A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be preferentially deposited only... Agent: Greenblum & Bernstein, P.L.C

20060286787 - Method of manufacturing semiconductor device and semiconductor device: A semiconductor device comprising a metal silicide film with uniform surface morphology and interface morphology and a method of manufacturing the same are provided. The metal silicide film of the semiconductor device exhibits low sheet resistance and excellent thermal stability. Therefore, by using the semiconductor device fabrication method, high performance,... Agent: Buchanan, Ingersoll & Rooney PC

20060286788 - Method for making a wire nanostructure in a semiconductor film: passage of a current between the first and the second terminals so as to form at least one continuous overthickness (R1, R2, R3) in the thin semiconductor film by migration of a fraction of the semiconductor material, under the action of the current, the continuous overthickness being formed along the... Agent: Thelen Reid & Priest

20060286789 - Semiconductor device having through electrode and method of manufacturing the same: A method of manufacturing a semiconductor device having a through electrode, includes forming through holes 36 in a substrate 31, forming a first metal layer 39 from one surface side of the substrate and pasting a protection film 40 on one surface of the substrate, forming through electrodes by filling... Agent: Rankin, Hill, Porter & Clark LLP

20060286790 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes preparing a semiconductor substrate having an electrode pad, a passivation film having an opening overlapping the electrode pad and an oxidized film formed in the opening, forming a resin projection on the passivation film, forming a metal layer on the passivation film... Agent: Oliff & Berridge, PLC

20060286791 - Semiconductor wafer package and manufacturing method thereof: A manufacturing method of a semiconductor wafer package mainly comprises the following steps. Firstly, a semiconductor wafer having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, under bump metallurgy layers are formed on each of the bonding pads respectively. Then, a mask... Agent: Bacon & Thomas, PLLC

20060286792 - Dual damascene process: A dual damascene process for fabricating a semiconductor device. A dielectric layer is formed on a substrate, comprising at least one via opening therein. A trench opening is formed in the dielectric layer above the via opening and the via opening widened by in-situ etching.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060286795 - Method of manufacturing semiconductor device: A method for manufacturing a semiconductor device is provided, which comprises forming a first metal wiring layer above a semiconductor substrate, forming an inorganic insulating film above the first metal wiring layer, forming an organic insulating film on the inorganic insulating film, forming a recess in the organic insulating film,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060286793 - Stacked structure for forming damascene structure, method of fabricating the stacked structure, and damascene process: A method of fabricating a stacked structure for forming a damascene process is described. A doped dielectric layer is formed on a substrate. A surface treatment is performed to the dielectric layer to make the dopant concentration in an upper surface layer of the dielectric layer lower than that in... Agent: J C Patents, Inc.

20060286794 - Stacked structure for forming damascene structure, method of fabricating the stacked structure, and damascene process: A method of fabricating a stacked structure for forming a damascene process is described. A doped dielectric layer is formed on a substrate. A surface treatment is performed to the dielectric layer to make the dopant concentration in an upper surface layer of the dielectric layer lower than that in... Agent: J.c. Patents Suite 250

20060286796 - Method of forming a contact in a flash memory device: A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may... Agent: Slater & Matsil LLP

20060286797 - Grain boundary blocking for stress migration and electromigration improvement in cu interconnects: Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter... Agent: William Stoffel

20060286798 - Cap for semiconductor device package, and manufacturing method thereof: A cap for a semiconductor device package, including a body formed at a predetermined thickness with a cavity. The cap further includes a first seed layer formed on an inner circumference of a first via hole formed at a predetermined depth from the cavity formation surface of the body, a... Agent: Sughrue Mion, PLLC

20060286799 - Electrode structure for flexible display device and method for forming the same: A method for forming an electrode comprises forming a carbon nano tube of a gel state by mixing a carbon nano tube with an ionic liquid. The method for forming an electrode for a flexible display device further comprises printing the carbon nano tube of a gel state on a... Agent: Brinks Hofer Gilson & Lione

20060286800 - Method for adhesion and deposition of metal films which provide a barrier and permit direct plating: A method for fabricating a barrier layer and a barrier layer is described which employs a metal selected from the group of Ru, Ir, Pd, Pt, Rh, Os, Au, Ag, W, Ta and Ti. A graded region is formed to cause the metal to adhere to an underlying substrate. Direct... Agent: Blakely Sokoloff Taylor & Zafman

20060286801 - Process chamber assembly and apparatus for processing a substrate: In a process chamber assembly and a processing apparatus for processing a substrate using, a process chamber assembly may include a process chamber including a body having a first contact face and a cover for covering the body having a second contact face, the second contact face of the cover... Agent: Harness, Dickey & Pierce, P.L.C

20060286802 - Low work function metal alloy: Low work function metals for use as gate electrode in nMOS devices are provided. The low work function metals include alloys of lanthanide(s), metal and semiconductor. In particular, an alloy of nickel-ytterbium (NiYb) is used to fully silicide (FUSI) a silicon gate. The resulting nickel-ytterbium-silicon gate electrode has a work... Agent: Knobbe Martens Olson & Bear LLP

20060286803 - Method for activating nitride surfaces for amine-reactive chemistry: Provided is a method for controllably activating a surface for stable amine-reactive chemistries. A surface containing nitride is exposed to a plasma having a reactive species containing hydrogen for a period of time sufficient to activate the substrate for amine-reactive chemistries. Amine-reactive chemical processes can then be applied to the... Agent: Naval Research Laboratory Associate Counsel (patents)

20060286804 - Method for forming patterned material layer: A method for forming a patterned material layer comprises the following steps. First, a material layer is formed on a substrate, and then a patterned positive photoresist layer is formed on the material layer. Next, the material layer is etched by using the patterned positive photoresist layer as a mask.... Agent: J C Patents, Inc.

20060286805 - Planarization process for pre-damascene structure including metal hard mask: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP... Agent: Jianq Chyun Intellectual Property Office

20060286806 - Plasma etching method and plasma etching apparatus: The plasma etching method first forms a coating film on the inner surface of the chamber. Next, an etching process is performed on a wafer under a condition in which the coating film is formed, and thereafter a reaction product adhered onto the coating film in the etching process is... Agent: Mcdermott Will & Emery LLP

20060286807 - Use of active temperature control to provide emmisivity independent wafer temperature: Embodiments relate to a substrate or wafer edge support having an emmisivity greater than that of a silicon wafer, where the edge support is for supporting a wafer during processing to form circuit devices on or in the wafer. Embodiments also include temperature sensors, heat conducting gas jets, and photonic... Agent: Blakely Sokoloff Taylor & Zafman

20060286808 - System and method of processing substrates using sonic energy having cavitation control: A system and method for the acoustic-assisted processing of a substrate, such as a semiconductor wafer, that reduces and/or eliminates damage. The invention suppresses cavitation and pressure effects within the cleaning liquid that may damage devices on the wafer by maintaining the liquid under a constant positive pressure. In one... Agent: Wolf, Block, Schorr & Solis-cohen LLP

20060286809 - Method for etching a patterned silicone layyer: A method for reworking semiconductor materials includes: (i) applying a silicone composition to a surface of a substrate to form a film, (ii) exposing a portion of the film to radiation to produce a partially exposed film having non-exposed regions covering a portion of the surface and exposed regions covering... Agent: Dow Corning Corporation Co1232

20060286810 - Atomic layer deposition (ald) method and reactor for producing a high quality layer: One inventive aspect is related to an atomic layer deposition (ALD) method comprising: a) providing a semiconductor substrate in a reactor, b) providing a pulse of a first precursor gas into the reactor at a first temperature, c) providing a first pulse of a second precursor gas into the reactor... Agent: Knobbe Martens Olson & Bear LLP

20060286811 - Method of optically imaging and inspecting a wafer in the context of edge bead removal: The present invention relates to a method of optically imaging a wafer with a photoresist layer, wherein an imaging area on the surface of the wafer is illuminated with light and a fluorescence image is taken in the imaging area based on the fluorescent light irradiated due to the illumination... Agent: Simpson & Simpson, PLLC

20060286812 - Modification of semiconductor surfaces in a liquid: Compositions and methods are provided herein that include modifications to at least one surface of a silicon-based semiconductor material. Modifications occur in a liquid and comprise alterations of surface states, passivation, cleaning and/or etching of the surface, thereby providing an improved surface to the semiconductor material. Modifications of surface states... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20060286813 - Silica and silica-like films and method of production: A method of producing a silica or silica-like coating by forming a precursor formulation from oligomeric organosilicate. The precursor formulation is coated on a substrate as a continuous liquid phase. The precursor formulation is then cured in an ammoniacal atmosphere to produce a continuous, interconnected, nano-porous silica network.... Agent: Harness, Dickey & Pierce, P.L.C

20060286814 - Semiconductor device and method of fabricating the same: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060286815 - Interlayer insulating film formation method and film structure of interlayer insulating film: An interlayer insulating film formation method for forming an interlayer insulating film on a substrate includes the step of forming the interlayer insulating film through plasma CVD by using an organic silicon compound including no oxygen atom and an organic silicon compound including an oxygen atom as materials.... Agent: Mcdermott Will & Emery LLP

20060286816 - Method for fabricating semiconductor device and semiconductor device: A method for fabricating a semiconductor device includes the steps of forming a nitrogen-containing layer in an exposed portion of a copper interconnect formed in an insulating film provided on a substrate; and forming an interlayer insulating film on the nitrogen-containing layer through plasma CVD performed by using, as a... Agent: Mcdermott Will & Emery LLP

20060286817 - Cvd method for forming silicon nitride film: A CVD method for forming a silicon nitride film includes exhausting a process chamber (8) that accommodates a target substrate (W), and supplying a silane family gas (HCD) and ammonia gas (NH3) into the process chamber, thereby forming a silicon nitride film on the target substrate by CVD. Said forming... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060286818 - Method for silicon based dielectric chemical vapor deposition: Embodiments of the invention generally provide a method for depositing silicon-containing films. In one embodiment, a method for depositing silicon-containing material film on a substrate includes flowing a nitrogen and carbon containing chemical into a deposition chamber, flowing a silicon-containing source chemical having silicon-nitrogen bonds into the processing chamber, and... Agent: MoserIPLaw Group / Applied Materials, Inc.

20060286819 - Method for silicon based dielectric deposition and clean with photoexcitation: Embodiments of the invention generally provide a method for depositing films using photoexcitation. The photoexcitation may be utilized for at least one of treating the substrate prior to deposition, treating substrate and/or gases during deposition, treating a deposited film, or for enhancing chamber cleaning. In one embodiment, a method for... Agent: Patterson & Sheridan, LLP Applied Materials Inc

20060286820 - Method for treating substrates and films with photoexcitation: Embodiments of the invention generally provide a method for depositing films using photoexcitation. The photoexcitation may be utilized for at least one of treating the substrate prior to deposition, treating substrate and/or gases during deposition, treating a deposited film, or for enhancing chamber cleaning. In one embodiment, a method for... Agent: Patterson & Sheridan, LLP Applied Materials Inc

20060281196 - Controlled electrochemical polishing method: The invention relates to a method of polishing a substrate comprising at least one metal layer by applying an electrochemical potential between the substrate and at least one electrode in contact with a polishing composition comprising a reducing agent or an oxidizing agent.... Agent: Steven Weseman Associate General Counsel, I.p.

20060281199 - Abnormality cause specifying method, abnormality cause specifying system, and semiconductor device fabrication method: A feature amount is generated by standardizing inspection data related to a fabrication unit for each type, a similar set including fabrication units corresponding to similar feature amounts is formed by comparing the feature amounts, and apparatus difference analysis is performed between a plurality of fabrication units forming the similar... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060281197 - Method and apparatus for completely covering a wafer with a passivating material: A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine... Agent: Ibm Microelectronics Intellectual Property Law

20060281200 - Method and system for using pattern matching to process an integrated circuit design: Disclosed is a method, system, and computer program product for processing design objects, such as vias, for an integrated circuit design. In one approach, pattern matching is employed to perform DRC/LVS for scattering bars and Vias. A library of via combinations can be used to insert scattering bars into design.... Agent: Bingham Mccutchen LLP

20060281198 - Pattern drawing system, electrically charged beam drawing method, photomask manufacturing method, and semiconductor device manufacturing method: A pattern drawing system includes a beam irradiating mechanism which irradiates electrically charged beams on a film to be drawn, a coefficient calculating section which calculates a backward scattering coefficient relevant to a drawing pattern in the film to be drawn, based on an approximating function for approximating a relationship... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060281201 - Damage evaluation method of compound semiconductor member, production method of compound semiconductor member, gallium nitride compound semiconductor member, and gallium nitride compound semiconductor membrane: A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength... Agent: Mcdermott Will & Emery LLP

20060281202 - Method for manufacturing laser devices: A method for manufacturing a laser device includes fixing a laser chip to a holder via a metal having a low melting point by melting the metal at a temperature higher than the melting point, heating the holder to which the laser chip is fixed at a heat treatment temperature... Agent: Harness, Dickey & Pierce, P.L.C

20060281204 - Manufacturing method of a liquid crystal display: A manufacturing method of an LCD comprises forming an insulating substrate; forming a gate line extending in a horizontal direction and a data line insulatively crossing the gate line to define a pixel area on the insulating substrate; forming a TFT disposed at an intersection of the gate line and... Agent: Cantor Colburn LLP

20060281205 - Method for manufacturing nitride-based semiconductor device: In a method for manufacturing a high-quality GaN-based semiconductor layer on a substrate of different material, an AlN nucleation layer is grown on a substrate, a GaN buffer layer is grown on the AlN nucleation layer, and the substrate annealed. The AlN nucleation layer is formed to have a thickness... Agent: Mcdermott Will & Emery LLP

20060281203 - Method of removing the growth substrate of a semiconductor light emitting device: A semiconductor structure formed on a growth substrate and including a light emitting layer disposed between an n-type region and a p-type region is attached to a carrier by a connection that supports the semiconductor structure sufficiently to permit removal of the growth substrate. In some embodiments, the semiconductor structure... Agent: Patent Law Group LLP

20060281206 - Shadow mask deposition of materials using reconfigurable shadow masks: A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are... Agent: The Webb Law Firm, P.C.

20060281207 - Optical device, method of manufacturing the same, optical module, optical transmission system: In a conventional optical device which mounts a semiconductor light emitting element, the processing is difficult and a manufacturing process cost is expensive because of the necessity of forming via holes in a substrate. An optical device comprises a laser diode which needs heat radiation, a glass substrate which is... Agent: Ratnerprestia

20060281208 - Laser process for reliable and low-resistance electrical contacts: Disclosed is a method for manufacturing an organic optoelectronic device. The method comprises providing a substrate, disposing a first electrode on the substrate, disposing a metal pad on the substrate, electrically separated from the first electrode, disposing a first material over the first electrode and at least partially over the... Agent: Fish & Richardson P.C.

20060281209 - Light emitting device and method of manufacturing the same: Provided is a light emitting device and a method of manufacturing the same. The light emitting device comprises a transparent substrate, an n-type compound semiconductor layer formed on the transparent substrate, an active layer, a p-type compound semiconductor layer, and a p-type electrode sequentially formed on a first region of... Agent: Buchanan, Ingersoll & Rooney PC

20060281210 - Semiconductor device manufacturing method: A semiconductor device manufacturing method includes a step of forming an oxidation preventing film 25 on a contact plug 22a on a silicon substrate 10, a step of forming a capacitor Q on the oxidation preventing film 25, a step of forming a second interlayer insulating film 44 to cover... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060281211 - Liquid crystal display panel and fabricating method thereof: A liquid crystal display panel includes an upper substrate, a lower substrate facing the upper substrate, a gate line and a data line on an upper surface of the lower substrate facing the upper substrate, the gate line and the data line cross each other to define a cell area,... Agent: Jenkens & Gilchrist, P.C.

20060281213 - Actuator coupling system and a pipetting module comprising such a coupling system: The present invention is directed a system for coupling a macroactuator to a movable element of a micromachined device. The system includes a micromachined device, a first body for holding a macroactuator, a macroactuator mechanically mounted on the first body, a second body having a bore for receiving the first... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20060281212 - Stacked structure and production method thereof: The invention relates to a method of producing a stacked structure. The inventive method comprises the following steps consisting in: a) using a first plate (1) which is, for example, made from silicon, and a second plate (5) which is also, for example, made from silicon, such that at least... Agent: Brinks Hofer Gilson & Lione

20060281214 - Method of making a soi silicon structure: A process for making a microelectromechanical device having a moveable component defined by a gap pattern in a semiconductor layer of a silicon-on-insulator wafer involves the use of a plurality of deep reactive ion etching steps at various etch depths that are used to allow a buried oxide layer of... Agent: Delphi Technologies, Inc.

20060281215 - Solid-state imaging device and method for manufacturing the same: The solid-state imaging device includes at least a silicon layer formed with a photo sensor portion and a wiring layer formed on the front-surface side of the silicon layer, and in which light L is made to enter from the rear-surface side opposite to the front-surface side of the silicon... Agent: Sonnenschein Nath & Rosenthal LLP

20060281218 - Method of forming a chalcogenide memory cell having a horizontal electrode and a memory cell produced by the method: A horizontal electrode having a small cross-section makes electrical contact with a chalcogenide memory element. The dimensions of the cross-section are controlled by conventional deposit/etch semiconductor processing steps. The resulting memory element can be driven by a CMOS steering element.... Agent: Stout, Uxa, Buyan & Mullins LLP

20060281216 - Method of manufacturing a phase change ram device utilizing reduced phase change current: To effectively lower the current required for changing a phase of a phase change layer in a phase change RAM device, metal pads are formed on a semiconductor substrate, and an oxide layer is formed on the metal pads. Nano-sized copolymer patterns aligned with the metal pads covered by the... Agent: Ladas & Parry LLP

20060281217 - Methods for fabricating phase changeable memory devices: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that includes nitrogen atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have... Agent: Myers Bigel Sibley & Sajovec

20060281219 - Chip-based thermo-stack: A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at... Agent: Morgan & Finnegan, L.L.P.

20060281220 - Semiconductor device packaging substrate and semiconductor device packaging structure: A packaging substrate for a semiconductor device includes: a solder resist on a surface of the packaging substrate, the solder resist having a first opening portion for mounting the semiconductor device; and a speed adjusting opening portion for adjusting a flow speed of an underfill resin when the underfill resin... Agent: Rankin, Hill, Porter & Clark LLP

20060281221 - Enhanced routing grid system and method: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for... Agent: J. Scott Denko

20060281222 - Manufacturing method of semiconductor integrated circuit device: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin... Agent: Antonelli, Terry, Stout & Kraus, LLP

20060281224 - Compliant passivated edge seal for low-k interconnect structures: A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and... Agent: International Business Machines Corporation Dept. 18g

20060281223 - Packaging method and package using the same: The invention achieves the above-identified object by providing a packaging, comprising steps of: (a) providing an integrated circuit unit having an active surface, a plurality of bumps disposed thereon; (b) providing a substrate having a first surface and a second surface, a plurality of pads disposed on the first surface,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20060281225 - Wafer level bumpless method of making a flip chip mounted semiconductor device package: A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact and a plurality of source contacts, patterning a lead... Agent: Fortune Law Group LLP

20060281226 - Wafer dividing method: A method of dividing a wafer having a plurality of devices, which are formed in a plurality of areas sectioned by streets formed in a lattice pattern on the front surface, and having test metal patterns which are formed on the streets, comprising the steps of: a laser beam application... Agent: Smith, Gambrell & Russell

20060281227 - Bond method and structure using selective application of spin on glass: A method for bonding substrate structures. The method includes providing a transparent substrate structure, the transparent substrate structure comprising a face region and an incident light region, providing a spacer structure, the spacer structure comprising a selected thickness of material, the spacer structure having a spacer face region and a... Agent: Townsend And Townsend And Crew, LLP

20060281228 - Lead-frame type semiconductor package and lead frame thereof: A lead-frame type semiconductor package is provided, including: a lead frame having a plurality of long leads and short leads, wherein a chip-attaching area is defined on the plurality of long leads, and at least a portion of each of the long leads within the chip-attaching area is formed with... Agent: Birch Stewart Kolasch & Birch

20060281229 - Method for molding a small form factor digital memory card: A method for molding digital storage memory cards such as, for example, multimedia cards (MMC), secure digital cards (SD), and similar small form factor digital memory cards. A PCA subassembly including, for example, a leadframe (TSOP) package for enclosing a flash IC and a (e.g., land grad array) controller package... Agent: Morland C Fischer

20060281231 - Semiconductor module: An image sensor module is composed of a base, a CCD image sensor, a glass plate, and a frame-shaped moisture permeable member. The base has a depressed chip chamber, in which the CCD image sensor is contained. Top and under surfaces of the moisture permeable member are provided with adhesive... Agent: Sughrue Mion, PLLC

20060281230 - Technique for manufacturing an overmolded electronic assembly: A technique for manufacturing an electronic assembly includes a number of steps. Initially, a backplate with a cavity formed into a first side of the backplate is provided. Next, a substrate with a first side of an integrated circuit (IC) die mounted to a first side of the substrate is... Agent: Delphi Technologies, Inc.

20060281233 - Method for manufacturing simox wafer and simox wafer: This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of... Agent: Kolisch Hartwell, P.C.

20060281232 - Method of growing a germanium epitaxial film on insulator for use in fabrication of a cmos integrated circuit: A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer; patterning... Agent: Sharp Laboratories Of America, Inc

20060281235 - Process for fabricating a thin film semiconductor device, thin film semiconductor device, and liquid crystal display: A process of fabricating a thin film semiconductor device is proposed, which is suitable for mass production and enables to lower the production cost. A first substrate is subject to anodization to form a porous layer thereon. Then, a thin film semiconductor layer is formed on the porous layer. Using... Agent: Rader Fishman & Grauer PLLC

20060281234 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060281236 - Method and apparatus for improving stability of a 6t cmos sram cell: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate... Agent: Blakely Sokoloff Taylor & Zafman

20060281238 - Method of manufacturing an adaptive algan buffer layer: A method of compensating resistivity of a near-surface region of a substrate includes epitaxially growing a buffer layer on the substrate, wherein the buffer is grown as having a dopant concentration as dependent on resistivity and conductivity of the substrate, so as to deplete residual or excess charge within the... Agent: Volentine Francos, & Whitt PLLC

20060281237 - Method of manufacturing junction field effect transistor: A method of manufacturing a junction field-effect transistor which controls variations of p-type impurities in a gate region and obtains a favorable PN junction characteristic includes: depositing ZnO in a thin layer by a sputtering method on a surface of a region in which a gate electrode of an n+-AlGaAs... Agent: Greenblum & Bernstein, P.L.C

20060281239 - Cmos fabrication: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS... Agent: Knobbe Martens Olson & Bear LLP

20060281241 - Cmos fabrication: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS... Agent: Knobbe Martens Olson & Bear LLP

20060281240 - Method of forming an interlayer dielectric: A method for forming a semiconductor device comprises providing a semiconductor substrate; forming a first stressor layer over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer; forming a second stressor layer over the surface of the semiconductor substrate and the first stressor layer; and... Agent: Freescale Semiconductor, Inc. Law Department

20060281242 - Semiconductor device and fabrication method therefor: A semiconductor device of the present invention includes a semiconductor substrate (10) having a bit line (14), an ONO film (16) that is provided on the semiconductor substrate (10) and has an opening (46), an interlayer insulating film (30) that is provided on the ONO film (16) and has a... Agent: Ingrassia Fisher & Lorenz, P.C.

20060281243 - Through chip connection: A method of forming an electrically conductive path through a portion of a semiconductor material, wherein the semiconductor material abuts a substrate and wherein the semiconductor material comprises multiple electronic devices, involves forming an annular trench in the portion, forming an island of semiconductor material within the annular trench, filling... Agent: Morgan & Finnegan, L.L.P.

20060281244 - Nonvolatile semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a semiconductor substrate. Two diffusion layers are separately arranged along a first direction on the surface of the semiconductor substrate and include impurities. Two element separation layers are separately arranged along a second direction in a surface of the semiconductor substrate and define an element... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060281245 - Semiconductor device and method for manufacturing the same: A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060281246 - Semiconductor having structure with openings: A process for producing an insulation structure with openings of a low aspect ratio is disclosed. In one embodiment, a dopant is introduced into the insulation structure with a concentration which on average increases or decreases in the vertical direction from a pre-processed semiconductor surface, the openings are formed in... Agent: Dicke, Billig & Czaja, P.l.l.c.

20060281247 - Non-volitale semiconductor memory: A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20060281248 - Semiconductor device manufacturing method: A semiconductor device manufacturing method, includes a step of forming refractory metal silicide layers 13a to 13c in a partial area of a semiconductor substrate 10, a step of forming an interlayer insulating film 21 on the refractory metal silicide layers 13a to 13c, a step of forming a first... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060281249 - Charge balance field effect transistor: A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant... Agent: Townsend And Townsend And Crew, LLP

20060281250 - 6f2 access transistor arrangement and semiconductor memory device: An access transistor arrangement is provided for a 6F2 stacked capacitor DRAM memory cell layout with shared bit line contacts. The access transistors are arranged in pairs along semiconductor lines. The two transistors of each pair of transistors are arranged laterally reversed opposing the respective common bit line section. Each... Agent: Edell, Shapiro & Finnan, LLC

20060281252 - Metal interconnect for capacitor: A method and implementation for coupling a high current electrode to an energy storage device is disclosed.... Agent: Maxwell Technologies, Inc. Co: Mark Wardas

20060281251 - Method for manufacturing gate dielectric layer: A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A... Agent: Jianq Chyun Intellectual Property Office

20060281253 - Semiconductor local interconnect and contact: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed... Agent: The Law Offices Of Mikio Ishimaru

20060281255 - Method for forming a sealed storage non-volative multiple-bit memory cell: A method of fabricating an array of trapped charge memory cells is described that eliminates bird's beak issues. Implants at a tilt angle form pockets in a substrate that reduce problems resulting from a short channel effect.... Agent: Kenton R. Mullins Stout, Uxa, Buyan & Mullins, LLP

20060281254 - Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory: A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a... Agent: Birch, Stewart, Kolasch & Birch, LLP

20060281256 - Self-aligned cell integration scheme: A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer... Agent: Lsi Logic Corporation

20060281257 - Stack gate structure of flash memory device and fabrication method for the same: A nonvolatile memory device has a floating gate with its top and side surfaces covered by ONO film to improve the data retention of the floating gate. The ONO film has upper and lower silicon dioxide layers interposed by silicon nitride layer thinner than the oxide layers. A method includes... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060281262 - Integrated semiconductor nonvolatile storage device: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current... Agent: Miles & Stockbridge PC

20060281258 - Magnetic tunnel junction device and writing/reading method for said device: The device successively comprises a first electrode (12), a magnetic reference layer (1), a tunnel barrier (3), a magnetic storage layer (4) and a second electrode (13). At least one first thermal barrier is arranged between the storage layer (4) and the second electrode (13) and is formed by a... Agent: Oliff & Berridge, PLC

20060281261 - Method of manufacturing a floating gate of a flash memory device: A method of forming a floating gate of a flash memory device wherein a hard mask nitride film is stripped using two or more etching steps. Accordingly, a seam can be prevented when depositing a floating gate polysilicon film. Furthermore, the floating gate polysilicon film may be blanket-etched to make... Agent: Marshall, Gerstein & Borun LLP

20060281260 - Methods of operating p-channel non-volatile memory devices: Methods of operating non-volatile memory devices are described. The memory devices comprise memory cells having an n-type semiconductor substrate and p-type source and drain regions disposed below a surface of the substrate and separated by a channel region. A tunneling dielectric layer is disposed above the channel region. A charge... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20060281259 - Semiconductor device and method of fabricating the same: A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable of storing charges in bit areas. The... Agent: Paul J. Winters

20060281263 - Semiconductor devices and method of manufacturing them: With conventional device, the quantity of complex defects differs with each semiconductor device because the concentration of impurities intrinsically contained differs for each silicon wafer. Consequently, there is an undesirable variation in characteristics among the semiconductor devices. The invention provides a method for manufacturing PIN type diode which comprises an... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060281265 - Selective nitridation of gate oxides: A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen... Agent: Andrew M. Calderon Greenblum And Bernstein P.L.C

20060281264 - Semiconductor device and method for fabricating the same: A semiconductor device includes: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate and made of a high-dielectric-constant material composed of a plurality of layers stacked perpendicularly to a principal surface of the semiconductor substrate and associated with respective phases; and a gate electrode formed on the... Agent: Mcdermott Will & Emery LLP

20060281266 - Method and apparatus for adjusting feature size and position: Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sideswalls. The critical dimension of the spacers is selected... Agent: Knobbe Martens Olson & Bear LLP

20060281269 - Method and structure of an auxiliary transistor arrangement used for fabricating a semiconductor memory device: Method for fabricating a semiconductor memory device having auxiliary transistor structures which are required for lithography and etching processes. A protective structure for reducing leakage currents between gate conductor and doped zone is provided. The protective structure is formed as a region doped oppositely to the doped zone.... Agent: Slater & Matsil LLP

20060281267 - Method for improving threshold voltage stability of a mos device: This invention provides a method for improving threshold voltage stability of at least one metal-oxide-semiconductor (MOS) device. In one embodiment of the invention, at least one well is formed on a semiconductor substrate. A gate dielectric layer is formed on the well of the semiconductor substrate. A gate conductive layer... Agent: Howard Chen Preston Gates & Ellis LLP

20060281268 - Short channel semiconductor device fabrication: The formation of one or more accumulation mode multi gate transistor devices is disclosed. The devices are formed so that short channel effects are mitigated. In particular, one more types of dopant materials are implanted in a channel region, an extension region and/or source/drain regions to mitigate the establishment of... Agent: Texas Instruments Incorporated

20060281272 - Method and apparatus for increase strain effect in a transistor channel: Method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate. The method utilizes depositing a nitride film along a surface of the substrate and the gate stack. The nitride film is thicker over a surface of the substrate and thinner over a portion of... Agent: Greenblum & Bernstein, P.L.C

20060281271 - Method of forming a semiconductor device having an epitaxial layer and device thereof: Integration schemes are presented which provide for decoupling the placement of deep source/drain (S/D) implants with respect to a selective epitaxial growth (SEG) raised S/D region, as well as decoupling silicide placement relative to a raised S/D feature. These integration schemes may be combined in multiple ways to permit independent... Agent: Larson Newman Abel Polansky & White, LLP

20060281270 - Raised source and drain process with disposable spacers: A method for forming raised source and drain regions in a semiconductor manufacturing process employs double disposable spacers. A deposited oxide is provided between the first and second disposable spacers, and serves to protect the gate electrode, first disposable spacers and a cap layer during the dry etching of the... Agent: Mcdermott Will & Emery LLP

20060281273 - Semiconductor device and manufacturing method of the semiconductor device: A semiconductor device includes a gate electrode disposed on a semiconductor layer via a gate insulating film; a source layer formed in the semiconductor layer to be separated by a first offset length from one end of said gate electrode; a drain layer formed in the semiconductor layer to be... Agent: Oliff & Berridge, PLC

20060281275 - Heterojunction bipolar transistor and manufacturing method thereof: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer,... Agent: Mcdermott Will & Emery LLP

20060281274 - Nonvolatile resistive memory element: A nonvolatile memory element includes a first material region, a second material and an oxidation material region including an oxidation material as a memory material region. The oxidation material includes an oxidized form of the first material and/or an oxidized form of the second material. The first material is selected... Agent: Edell, Shapiro & Finnan, LLC

20060281276 - Method of manufacturing image sensor: A method of manufacturing an image sensor comprises forming an isolation layer defining an active region in a semiconductor substrate using a first mask pattern formed on the semiconductor substrate, forming a first ion implantation mask pattern by reducing a width of the first mask pattern to expose an edge... Agent: F. Chau & Associates, LLC

20060281277 - Manufacturing method for variable resistive element: In the case where a variable resistive element, which is made of a variable resistor provided between a first and second electrodes, and of which the electrical resistance varies by applying a voltage pulse between the two electrodes, is applied to a resistance nonvolatile memory, there is a range of... Agent: Nixon & Vanderhye, PC

20060281278 - Integrated thin-film capacitor with etch-stop layer, process of making same, and packages containing same: A thin-film capacitor assembly includes a first metal bottom electrode, a dielectric layer, a second metal etch-stop layer, and a subsequent metal top electrode. The first metal bottom electrode is in contact with the dielectric layer. The second metal etch-stop layer is in contact with the dielectric layer. The subsequent... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060281279 - Structure and method for iii-nitride monolithic power ic: III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure... Agent: Ostrolenk, Faber, Gerb & Soffen, LLP

20060281280 - Method for producing bonded wafer: A bonded SOI substrate having an active layer which is free from crystal defects is obtained by adding more than 9×1018 atoms/cm3 of boron to a wafer for active layer (10). Since the boron concentration in the wafer for active layer is high, a silicon oxide film is formed at... Agent: Greenblum & Bernstein, P.L.C

20060281281 - Method of inspecting semiconductor wafer: A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060281282 - Method for maching a wafer: The present invention relates to a method for machining a wafer, comprising: (a) providing a wafer having an active surface and a backside surface; (b) attaching a plate substrate to the active surface of the wafer; (c) grinding the backside surface of the wafer; (d) removing the plate substrate; and... Agent: Volentine Francos, & Whitt PLLC

20060281284 - Method of manufacturing gallium nitride based high-electron mobility devices: A method of manufacturing a heterojunction device includes forming a first layer of p-type aluminum gallium nitride; forming a second layer of undoped gallium nitride on the first layer; and forming a third layer of aluminum gallium nitride on the second layer, to provide an electron gas between the second... Agent: Volentine Francos, & Whitt PLLC

20060281283 - Silicon epitaxial wafer, and silicon epitaxial wafer manufacturing method: A silicon epitaxial wafer (W) comprising: a silicon single crystal substrate (1) having a COP (100) on a main surface (11), and a silicon epitaxial layer (2) grown by vapor phase epitaxy on the main surface (11) of the silicon single crystal substrate (1), wherein the main surface (11) is... Agent: Oliff & Berridge, PLC

20060281285 - Semiconductor device and a method of manufacturing the same: A semiconductor device has a semiconductor (e.g., a silicon substrate), an electrically conductive region (e.g., a source region and a drain region) which is in contact with the semiconductor to form a Schottky junction, and an insulator. The insulator is in contact with the semiconductor and the electrically conductive region,... Agent: Birch Stewart Kolasch & Birch

20060281286 - Method for fabricating metal line in semiconductor device: A method for fabricating a metal line in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming a contact hole by etching the inter-layer insulation layer; forming a metal layer on the inter-layer insulation layer and the contact hole; etching a portion... Agent: Blakely Sokoloff Taylor & Zafman

20060281287 - Method of aligning deposited nanotubes onto an etched feature using a spacer: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched... Agent: Lsi Logic Corporation

20060281289 - Method of forming polycide layer and method of manufacturing semiconductor device having polycide layer: In a method of forming a polycide layer and method of manufacturing a semiconductor device having the polycide layer, the method may include forming a preliminary polysilicon layer doped with first type impurities on a substrate having a first region and a second region, implanting second type of impurities into... Agent: Harness, Dickey & Pierce, P.L.C

20060281288 - Semiconductor device fabrication method: The semiconductor device fabrication method comprising the step of forming a gate electrode 54p on a semiconductor substrate 34; the step of forming a source/drain diffused layer 64p in the semiconductor substrate 34 on both sides of the gate electrode 54p; the step of burying a silicon germanium layer 100b... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060281291 - Method for manufacturing a metal-semiconductor contact in semiconductor components: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal-semiconductor or Schottky contact is produced only after the application of a protective layer system,... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20060281290 - Semiconductor device and method of manufacturing the same: In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel... Agent: Volentine Francos, & Whitt PLLC

20060281292 - Rigid-backed, membrane-based chip tooling: An apparatus for use with multiple individual chips having a rigid plate, and a deformable membrane located on the plate, the deformable membrane having a thickness sufficient to allow the deformable membrane to peripherally conform to each of the individual multiple chips irrespective of any difference in height among the... Agent: Morgan & Finnegan, L.L.P.

20060281294 - Method of forming a penetration electrode and substrate having a penetration electrode: A method of forming a penetration electrode in which an electroconductive substance is inserted into a micropore that has one end blocked off only by wiring and a pad formed by an electroconductive substance without the wiring and pad being broken. In this method of forming a penetration electrode, an... Agent: Sughrue Mion, PLLC

20060281293 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device, includes: mounting a semiconductor chip having an electrode on a wiring substrate having a base substrate and a wiring formed on the base substrate; forming a eutectic alloy by contacting the wiring with the electrode and by heating and pressurizing, and; forming the... Agent: Harness, Dickey & Pierce, P.L.C

20060281295 - Methods of manufacturing semiconductor devices and structures thereof: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating... Agent: Slater & Matsil LLP

20060281296 - Routingless chip architecture: A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back-end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the... Agent: Morgan & Finnegan, L.L.P.

20060281299 - Method of fabricating silicon carbide-capped copper damascene interconnect: A dielectric layer overlying a substrate is prepared. A damascene opening is etched into the dielectric layer. The damascene opening is filled with copper or copper alloy. A surface of the copper or copper alloy is treated with hydrogen-containing plasma such as H2 or NH3 plasma. The treated surface of... Agent: North America Intellectual Property Corporation

20060281297 - Multilayer electronic part and structure for mounting multilayer electronic part: A multilayer electronic component includes a multilayer substrate having a first main surface and a second main surface, a resin layer having a mounting surface and a contact surface bonded to the first main surface, a via conductor provided inside the resin layer, and an external terminal electrode disposed on... Agent: Murata Manufacturing Company, Ltd. C/o Keating & Bennett, LLP

20060281298 - Semiconductor device and manufacturing method of the same: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming... Agent: Stanley P. Fisher Reed Smith LLP

20060281300 - Semiconductor substrate and method of fabricating semiconductor device: A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060281301 - Method for manufacturing dual damascene pattern: Normal+Times New Roman, Justified, Line spacing: 1.5 lines A method for forming a dual damascene pattern is provided. According to the method, a diffusion barrier layer and an interlayer insulation layer are formed on a substrate. A surface of the interlayer insulation layer is processed to reduce adhesion and deformation.... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20060281302 - Semiconductor damascene trench and methods thereof: A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and semiconductor devices embodying the cells are also provided. In accordance with one embodiment of the present invention, a memory device cell layout is provided comprising... Agent: Dinsmore & Shohl LLP

20060281303 - Tack & fuse chip bonding: A method of joining contacts on two chips, each having multiple contacts, to each other involves maintaining a first of the chips at a first temperature, the first of the chips having a rigid electrical contact thereon, bringing a second chip, having an electrical contact that is malleable with respect... Agent: Morgan & Finnegan, L.L.P.

20060281304 - Semiconductor device and method of manufacturing the same: m

20060281305 - Methods of forming self-aligned silicide layers using multiple thermal processes: Methods of forming a metal salicide layer can include forming a metal layer on a substrate and forming a metal silicide layer on the metal layer using a first thermal process at a first temperature. Then a second process is performed, in-situ with the first thermal process, on the metal... Agent: Myers Bigel Sibley & Sajovec

20060281306 - Carbon nanotube interconnect contacts: A method for forming an interconnect on a semiconductor substrate comprises providing at least one carbon nanotube within a trench, etching at least one portion of the carbon nanotube to create an opening, conformally depositing a metal layer on the carbon nanotube through the opening, and forming a metallized contact... Agent: Blakely Sokoloff Taylor & Zafman

20060281307 - Post-attachment chip-to-chip connection: A method of forming an electrical connection from a first chip, having a contact pad exposed through an opening in cover glass on the chip, to a second chip having a first side and a second side and involves attaching the second chip to the first chip, etching an annular... Agent: Morgan & Finnegan, L.L.P.

20060281309 - Coaxial through chip connection: A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the annulus trench, making a length of the via trench... Agent: Morgan & Finnegan, L.L.P.

20060281308 - Integration flow to prevent delamination from copper: The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and... Agent: Texas Instruments Incorporated

20060281310 - Rotating substrate support and methods of use: A method and apparatus for processing a substrate utilizing a rotating substrate support are disclosed herein. In one embodiment, an apparatus for processing a substrate includes a chamber having a substrate support assembly disposed within the chamber. The substrate support assembly includes a substrate support having a support surface and... Agent: Patterson & Sheridan, LLP

20060281311 - Integrated circuitry: A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof... Agent: Wells St. John P.s.

20060281313 - Etching method and method for forming contact opening: An etching method is described, including a first etching step and a second etching step. The temperature of the second etching step is higher than that of the first etching step, such that the after-etching-inspection (AEI) critical dimension is smaller than the after-development-inspection (ADI) critical dimension.... Agent: Jianq Chyun Intellectual Property Office

20060281312 - Hydrogen and oxygen based photoresist removal process: The present invention provides a photoresist removal process and a method for manufacturing an interconnect using the same. One embodiment of the photoresist removal process includes, among other steps, providing a low dielectric constant (k) substrate having a photoresist layer located thereover, and removing the photoresist layer using a plasma... Agent: Texas Instruments Incorporated

20060281315 - Process of manufacture of ultra thin semiconductor wafers with bonded conductive hard carrier: A process is described to enable the manufacture of a thinned (<50 μm semiconductor die) which can employ the use of standard equipment for the manufacture of the wafer and the packaging of the die singulated from the wafer. A standard thickness wafer (350 μm) first has junctions formed in... Agent: Ostrolenk Faber Gerb & Soffen

20060281314 - Wafer holder and method of holding a wafer: A wafer holder including a wafer stage and a wafer stage outer-ring surrounding the wafer stage wherein the wafer stage has a diameter smaller than the diameter of a wafer loaded on the wafer stage, the wafer stage outer-ring has an inner diameter at the upper side of the outer-ring... Agent: Buchanan, Ingersoll & Rooney PC

20060281318 - Method of manufacturing semiconductor device: Since sodium contained in glass, or glass itself has low heat resistance; a CPU fabricated using a TFT formed over a glass substrate or the like has not been obtained. In the case of operating a CPU with high-speed, the length of a gate (gate length) of a TFT is... Agent: Fish & Richardson P.C.

20060281316 - Semiconductor device and method of manufacturing the same: A semiconductor device manufacturing method, includes a step of forming a first alumina film (underlying insulating film) 37 on a semiconductor substrate 20, a step of forming a first conductive film 41, a ferroelectric film 42, and a second conductive film 43 in sequence on the first alumina film 37,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20060281317 - Thin film transistor substrate and method of fabricating the same: The invention relates to a thin film transistor substrate for use in a liquid crystal display device and a method of fabricating the same, and an object is to provide a thin film transistor substrate which can ensure high reliability even though a low resistance metal is used in a... Agent: Birch Stewart Kolasch & Birch

20060281319 - Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device: A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the dielectric layer during the etch. The charge buildup along a top and a bottom of the sidewall may reduce the etch rate thereby resulting in... Agent: Micron Technology, Inc.

20060281320 - Method for forming an anti-etching shielding layer of resist patterns in semiconductor fabrication: A method is disclosed for forming a photoresist pattern with enhanced etch resistance on a semiconductor substrate. A photoresist pattern is first formed on the substrate. A silicon-containing polymer layer is deposited over the photoresist pattern on the substrate. A thermal treatment is performed to form a cross-linked anti-etch shielding... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20060281321 - Nanowire sensor device structures: A method of fabricating a nanowire sensor device structure includes preparing a substrate, having a silicon base layer, a buried oxide layer in the silicon base layer, a top silicon layer on the buried oxide layer, and a doped well in the silicon base layer; forming a silicon island from... Agent: Sharp Laboratories Of America, Inc

20060281322 - Epitaxial semiconductor deposition methods and structures: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between... Agent: Knobbe Martens Olson & Bear LLP

20060281323 - Method of cleaning substrate processing apparatus: A method for cleaning a microwave plasma processing apparatus is disclosed wherein a cleaning gas is introduced and then excited with microwave plasma (step 3). By applying high-frequency power to a substrate supporting stage by which a substrate to be processed is supported (step 4), the etching rate is improved,... Agent: Foley And Lardner LLP Suite 500

20060281324 - Method of controlling the pressure in a process chamber: m

20060281325 - Method of defining polysilicon patterns: The present invention provides a method of defining polysilicon patterns. The method forms a polysilicon layer on a substrate, and a patterned mask on the polysilicon layer. Then, a first etching process is performed to remove a portion of the polysilicon layer not covered by the mask, thus forming a... Agent: North America Intellectual Property Corporation

20060281327 - Semiconductor laser element and method of fabrication thereof: A semiconductor laser element having an advantageous vertical light confinement efficiency, a low threshold current and a low element resistance is provided. The semiconductor laser element has a substrate and a stacked structure formed thereon, where the stacked structure comprises a buffer layer, an n-Al0.6Ga0.4As cladding layer, an n-Al0.47Ga0.53As cladding... Agent: Sonnenschein Nath & Rosenthal LLP

20060281326 - Washing apparatus, washing stystem, and washing method: The present invention provides a cleaning apparatus, a cleaning system and a cleaning method for a member used in the semiconductor field, excellent in cleaning capability and good in operation efficiency. The present invention is directed to a cleaning apparatus for cleaning the member used in the semiconductor field, which... Agent: Mcglew & Tuttle, PC

20060281328 - Compound semiconductor substrate, epitaxial substrate, processes for producing compound semiconductor substrate, and epitaxial substrate: A compound semiconductor substrate includes a substrate composed of a p-type compound semiconductor; and a substance containing p-type impurity atoms, the substance being bonded to a surface of the substrate.... Agent: Venable LLP

20060281331 - Charge trapping dielectric structure for non-volatile memory: An integrated circuit structure comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP

20060281330 - Iridium / zirconium oxide structure: Embodiments of an electronic apparatus and embodiments for methods of forming the electronic apparatus include a conductive layer having an iridium-based layer, where the conductive layer is disposed on a dielectric layer containing zirconium oxide. In various embodiments, each of the zirconium oxide layer and the iridium-based layer may be... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20060281329 - Sealing porous dielectric material using plasma-induced surface polymerization: A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectric... Agent: Blakely Sokoloff Taylor & Zafman

20060281334 - Method for forming high-resolution pattern and substrate having prepattern formed thereby: Disclosed is a method for forming a pattern, which comprises the steps of: (a) providing a substrate having a sacrificial layer made of a first material, partially or totally formed on the substrate; (b) forming pattern grooves, which are free from the first material and have a line width of... Agent: Mckenna Long & Aldridge LLP

20060281333 - Method for forming high-resolution pattern with direct writing means: Disclosed is a method for forming a pattern which comprises the steps of: (a) providing a substrate having a sacrificial layer made of a first material, partially or totally formed on the substrate; (b) forming pattern grooves, which are free from the first material and have a line width of... Agent: Mckenna Long & Aldridge LLP

20060281332 - Structure for a semiconductor arrangement and a method of manufacturing a semiconductor arrangement: The invention relates to a structure for a semiconductor arrangement. A resist structure for supporting deposition of a solution containing a semiconductor is directly or through intervening layers coupled to a substrate. The resist structure comprises a depression (301) for depositing of the solution containing the semiconductor (309) and a... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20060281335 - Method of fabricating semiconductor integrated circuits: A method of fabricating semiconductor integrated circuits includes (1) providing a spin-on tool comprising a rotatable platen for holding and spinning a wafer disposed thereon, a fluid supply system for providing spin-on solution onto the wafer, and a detector fixed in a position above the wafer, wherein the wafer has... Agent: North America Intellectual Property Corporation

20060281337 - Method and apparatus for forming silicon oxide film: A silicon oxide film is formed on a target substrate by CVD, in a process field configured to be selectively supplied with a first process gas containing a chlorosilane family gas, a second process gas containing a Cl-replacing gas, and a third process gas containing an oxidizing gas. This method... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20060281336 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20060281338 - Method for prediction of premature dielectric breakdown in a semiconductor: The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of... Agent: International Business Machines Corporation Dept. 18g

20060275926 - Barrier films for plastic substrates fabricated by atomic layer deposition: Gas permeation barriers can be deposited on plastic or glass substrates by atomic layer deposition (ALD). The use of the ALD coatings can reduce permeation by many orders of magnitude at thicknesses of tens of nanometers with low concentrations of coating defects. These thin coatings preserve the flexibility and transparency...

20060275925 - Electrical substrate for use as a carrier of biomolecules: An electrical substrate for use as a carrier of biomolecules in a method for electrochemical detection in an electrolyte solution exhibits an insulating support plate (12) bearing a conductive pattern (20; 20A-20C, 28) having conductor paths (20; 20A-20C) and connecting contact surfaces, and, disposed on the conductor paths (20; 20A-20C),...

20060275927 - Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis: A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die...

20060275929 - Method of fabricating periodic nano-structure arrays with different feature sizes: A method of fabricating a two dimensional nano-structure array of features comprising the steps of providing a substrate (10); forming an intermediate layer on said substrate (20), said intermediate layer having at least two selectively located regions (21, 22) of different uniform thickness; placing at least one layer of elements...

20060275930 - Method of manufacturing ferroelectric layer and method of manufacturing electronic instrument: A method of manufacturing a ferroelectric layer, including: forming a first ferroelectric layer above a base by a vapor phase method; and forming a second ferroelectric layer above the first ferroelectric layer by a liquid phase method....

20060275928 - Semiconductor memory device and operating method for a semiconductor memory device: A magnetoresistive semiconductor memory device is proposed, in which a magnetic field can be applied to memory cells by means of a magnetic field applying device such that a desired magnetization can be impressed on hard-magnetic layers of the memory cells acted on....

20060275931 - Technology of detecting abnormal operation of plasma process: A method of detecting abnormal operation of a plasma process, includes: (i) detecting a potential Vpp1 between an upper electrode and a lower electrode disposed parallel to each other in a reaction camber at a time T1 after the plasma process begins in the reaction chamber; (ii) detecting a Vpp2...

20060275932 - Semiconductor device, function setting method thereof, and evaluation method thereof: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board....

20060275934 - Management of computer processes: It is determined that an amount of total memory utilized by active processes exceeds a memory pressure threshold. There is deactivated at least one active process occupying space in the total memory during a first system cycle based on said determination. There is deactivated a number N of active processes...

20060275933 - Thermally conductive ceramic tipped contact thermocouple: An apparatus for processing a substrate. The apparatus comprising a tubular member with a first end and a second end. The first end comprising an opening; and a temperature sensor disposed in the opening. The temperature sensor comprising a resilient member. The resilient member comprising a surface made of a...

20060275935 - Testing electromigration at multiple points of a single node: Systems and methods for testing the reliability of a semiconductor component are disclosed herein. One embodiment of a method for testing reliability, among others, comprises providing simulation code of a standard cell, wherein the standard cell represents the semiconductor component. The method includes extracting foliage points of a node of...

20060275938 - Display apparatus: A configuration for decreasing the leakage electric current of a transistor for control for controlling an electric potential holding operation of a control electrode of a transistor for drive for flowing an electric current through a display device by adjusting the output electric potential of an electric potential source is...

20060275936 - Method for production of a semiconductor device with auto-aligned metallisations: This invention relates to a process for making a semiconductor device comprising the following steps: a doped region with a first type of conductivity is made on a first principal face of a semiconductor substrate and at least one window is made, a first metallisation area is deposited on the...

20060275937 - Method of fabricating light-emitting semiconductor device: A light-emitting diode having a silicon substrate on which there are successively formed a buffer layer, a p-type nitride semiconductor layer, an active layer, an n-type nitride semiconductor layer, and a current spreading layer. The current spreading layer is a lamination of a first and a second sublayer arranged alternately...

20060275939 - Composition and method for temporarily fixing solids: The present invention relates to a method of temporarily and firmly fixing two solids to each other and to a composition used in the method, which is a method of temporarily fixing, comprising temporarily fixing the two solids to each other with a liquid crystal compound or a composition comprising...

20060275940 - Method for controlling well capacity of a photodiode: A method for controlling well capacity of a photodiode includes providing a reference voltage, which is greater than a voltage of ground, to a gate of a transfer transistor while exposing the photodiode whose one end is connected to ground, so as to control the well capacity of the photodiode....

20060275941 - Methods for manufacturing microelectronic imagers: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device comprises an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry...

20060275942 - Method for fabricating cmos image sensor: A method of fabricating a CMOS image sensor is provided. The fabricating method includes: forming a gate electrode with a gate insulating layer interposed at a transistor region of a semiconductor substrate having an active region defined by a photodiode region and a transistor region; forming a first impurity region...

20060275943 - Substrate structure for an image sensor package and method for manufacturing the same: A substrate structure for an image sensor package, the substrate structure includes a bottom base and a frame layer. The bottom base has an upper surface formed with a plurality of first electrodes, and a lower surface formed with a plurality of second electrodes, an insulation layer is coated between...

20060275944 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor can incorporate one or more photodiodes formed on a substrate at a regular interval, an interlayer insulating layer formed on the substrate; one or more trenches in the interlayer insulating layer at predetermined...

20060275945 - Method of making cmos image sensor - hybrid silicide: Techniques for manufacturing a CMOS image sensor are provided. A semiconductor substrate is provided, and at least one isolation region can be formed between a periphery region of the substrate and a photo-sensing region of the substrate. A first well in the periphery region and a second well in the...

20060275946 - Silicon wafer having through-wafer vias: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A trench is formed in the semiconductor substrate at the first main surface. The trench extends to a first depth position in the semiconductor substrate. The trench is...

20060275947 - Process for forming an electronic device including reflowing a conductive member: A process for forming an electronic device can include providing a first workpiece including an electronic component that includes an electrode and an organic layer, and providing a second workpiece including a conductor. The process can also include reflowing a conductive member. Before reflowing, the conductive member is attached to...

20060275948 - Process for forming zinc oxide film: A process for forming zinc oxide film over a surface of a substrate which comprises a step of vaporising and supplying a materilal prepared by dissolving dimethylzinc or diethylzinc into an organic solvent to a chemical vapor deposition apparatus and a step of simultaneously supplying a gas comprising an oxidizing...

20060275949 - Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors: A semiconductor component includes a thinned semiconductor substrate having protective polymer layers on up to six surfaces. The component also includes contacts on a circuit side of the substrate, conductive vias in electrical contact with the contacts, aNd conductors on a backside of the substrate. A method for fabricating the...

20060275950 - Method of manufacturing a flexible display device: A method of manufacturing a flexible display includes the steps of coating an adhesive on a first surface of a flexible substrate or a supporter, adhering the first surface of the flexible substrate to the supporter using the adhesive, and forming a thin film pattern on a second surface of...

20060275951 - Microelectronic assemblies having low profile connections: A microelectronic assembly includes a first microelectronic element having a first face and contacts accessible at the first face, and a layer of a dielectric material having a bottom surface contacting the first microelectronic element, a top surface facing away from the first microelectronic element and holes extending between the...

20060275952 - Method for making electronic devices: Disclosed are methods for forming an electronic device that comprises a material that functions as an underfill material as well as a thermal interface material simultaneously. The electronic assembly comprising a heat dissipating element, a semiconductor chip, a substrate and a thermally conductive material is also given here, wherein the...

20060275953 - Copper strike plating method: Upon applying a copper strike plating to a surface of a substrate made of a copper alloy that was subjected to a heat treatment after a degreasing process and an electrolytic activating process are applied to the surface, a pulse current by which a current appears like a series of...

20060275954 - Method for removing a cover from a semiconductor wafer: A method of removing a cover from a wafer. A wafer, which includes a cover, is put on a support structure. The wafer is flexed to separate a portion of the wafer from the cover, and an impact force is applied to remove the cover from the wafer....

20060275956 - Cross-linked carbon nanotubes: Cross-linked carbon nanotube arrays forming a three-dimensional structure and methods of use including high thermal conductivity, high strength applications where repeated cycling is known, and chemical storage....

20060275955 - Patterned nanorod arrays and methods of making same: In some embodiments, the present invention addresses the challenges of fabricating nanorod arrays comprising a heterogeneous composition and/or arrangement of the nanorods. In some embodiments, the present invention is directed to multicomponent nanorod arrays comprising nanorods of at least two different chemical compositions, and to methods of making same. In...

20060275957 - Semiconductor device: A semiconductor device formed by mutually connecting a first semiconductor chip with second and third semiconductor chips arranged side by side, with the active surface of the first chip faced to those of the second and third chip. Both the second and third semiconductor chips have functional elements on their...

20060275958 - Fabricating nanoscale and atomic scale devices: This invention concerns the fabrication of nanoscale and atomic scale devices. The method involves creating one or more registration markers. Using a SEM or optical microscope to form an image of the registration markers and the tip of a scanning tunnelling microscope (STM). Using the image to position and reposition...

20060275960 - Integrated circuit device and method for manufacturing integrated circuit device: An object of the present invention is to provide a structure of a thin film circuit portion and a method for manufacturing a thin film circuit portion by which an electrode for connecting to an external portion can be easily formed under a thin film circuit. A stacked body including...

20060275959 - Method for fabricating thin film transistor (tft) display: A method for fabricating a thin film transistor (TFT) display is provided, wherein the processes of a liquid crystal substrate and an organic thin film transistor (OTFT) substrate are separated. The fabrication of liquid crystal substrate employs the technology of polymer encapsulated liquid crystal molecule, and leaves the polymeric layer...

20060275961 - Strained silicon cmos on hybrid crystal orientations: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the...

20060275962 - Three-dimensional integrated circuit structure and method of making same: Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices...

20060275963 - Structure and method for thin film device: Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality...

20060275964 - Semiconductor device and method for fabricating the same: A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides...

20060275965 - Plasma display device with improved heat dissipation efficiency: A plasma display device comprises: a plasma display panel for displaying an image; a chassis base mounted on a rear surface of the plasma display panel; a driving circuit unit mounted on a surface of the chassis base opposite to the plasma display panel; a signal transmitting device which electrically...

20060275966 - Method of manufacturing field emission device: A method of manufacturing a field emission device (FED) using a photoresist for performing multi-patterning processes, whereby different structures can be multi-patterned using a single photoresist mask. The photoresist has a solubility to a solvent by post-exposure heat-treatment, and a complicated structure can be formed using the photoresist....

20060275967 - Display device and manufacturing method thereof: A color filter substrate includes a base substrate, a wall pattern having a lattice structure, a number of pixel regions defined by the wall pattern, a color filter layer formed in the pixel regions, and a dummy element layer. The base substrate includes an active area and an inactive area,...

20060275970 - H-bridge drive utilizing a pair of high and low side mosfets in a common insulation housing: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided...

20060275968 - Method for producing a contact and electronic component comprising said type of contact: The invention relates to a method for the production of passivated defining surfaces (6a, 6b) between a first layer, such as a silicide (5), and an adjacent layer. Passivating elements, such as S, Se and Te are used in said layer structure during said method and the first layer is...

20060275969 - Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device made by its method: Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually...

20060275971 - Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first...

20060275972 - Method of fabricating cmos inverters and integrated circuits utilizing strained surface channel mosfets: A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and...

20060275973 - Dust excluding packing sheet and method of integrating dust excluding sheet: A flexible sheet member having a first dust excluding packing and a first auxiliary piece is tackedly held by an exfoliating sheet by an adhering layer 8 at a back face thereof. When the first dust excluding packing is exfoliated from the exfoliating sheet, and the first auxiliary piece is...

20060275974 - Method of fabricating a bottle trench and a bottle trench capacitor: A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent...

20060275975 - Nitridated gate dielectric layer: A metal-oxide-semiconductor field-effect transistors (MOSFET) with a gate structure having a deuterated layer is provided. In accordance with embodiments of the present invention, a transistor comprises the deuterated layer formed over a gate dielectric layer. A gate electrode is formed over the deuterated layer. The deuterated layer prevents or reduces...

20060275976 - Non-volatile memory and fabrication method thereof: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge...

20060275977 - Selective implementation of barrier layers to achieve threshold voltage control in cmos device fabrication with high k dielectrics: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating...

20060275978 - Deep trench formation in semiconductor device fabrication: A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask...

20060275979 - Semiconductor integrated circuit including a dram and an analog circuit: A semiconductor device including an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part...

20060275981 - Memory and method for fabricating it: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric...

20060275980 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, wherein the substrate has a first conductive type; a first trench extending from the first surface of the semiconductor substrate in a depth direction; and an epitaxial semiconductor layer having a second conductive type, wherein...

20060275982 - Semiconductor memory device, semiconductor device, and method for production thereof: Disclosed are a semiconductor memory device, a semiconductor device, and a method for production thereof. The semiconductor memory device and semiconductor device do not need for a distance for alignment of lithography to make the contact hole with lithography to form the gate electrode. Hence the resulting devices have a...

20060275983 - Methods for enhancing capacitors having roughened features to increase charge-storage capacity: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth...

20060275985 - Flash memory and manufacturing method thereof: A method for manufacturing flash memory is provided. A tunneling dielectric layer, a conductive layer and a patterned mask layer that exposes a portion of the conductive layer are formed on a substrate. An oxide layer is formed on the exposed conductive layer so that the conductive layer is partitioned...

20060275984 - Method for preventing trenching in fabricating split gate flash devices: A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying...

20060275986 - Semiconductor intergrated circuit device and process for producing the same: A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a...

20060275987 - Method of forming stack layer and method of manufacturing electronic device having the same: A method of forming a stacked structure in an electronic device, where a photoresist for performing multi-patterning processes is used. Also, a method of manufacturing a FED in which different structures can be multi-patterned by using a single photoresist mask. The photoresist has a solubility to a solvent by heat-treatment...

20060275988 - Semiconductor device and method of fabricating the same: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and...

20060275989 - Method of manufacturing liquid crystal display: In a method of manufacturing a liquid crystal display, first, a panel assembly structure including a first substrate, a second substrate and several sealants connecting inner surfaces of the first and second substrate is provided. The first substrate includes several third substrates. The second substrate includes several fourth substrates corresponding...

20060275990 - Semiconductor device and method of producing same: A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed in the semiconductor substrate under a conductive portion of the gate electrode and containing a first conductivity type impurity, first source/drain...

20060275991 - Method of manufacturing a semiconductor integrated circuit device: A method of manufacturing a semiconductor integrated circuit device comprising forming a silicon oxide film as thin as 5 nm or less on the surfaces of p type wells and n type wells by wet oxidizing a substrate, heating the substrate in an atmosphere containing about 5% of an NO...

20060275993 - Low ohmic layout technique for mos transistors: A method of making a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one of the...

20060275992 - Method to improve drive current by increasing the effective area of an electrode: The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the...

20060275994 - Thin film transistor, liquid crystal display and manufacturing method thereof: The present invention provides a thin film transistor comprising a drain electrode and a source electrode separated by a channel region formed over a contact portion with an amorphous silicon layer and wherein an impurity from the channel region is removed and a remaining impurity is diffused into the contact...

20060275997 - Method for forming capacitor in semiconductor device: Upon a deep-hole capacitor fabrication, a hole is formed in an insulator layer, and then a film of a conductive material is formed on the insulator layer and on the whole inner surface of the hole. The film and the insulator layer are exposed to a chemical-mechanical polishing process to...

20060275996 - Mounting device for a capacitor: A mounting device for mounting a capacitor on a connector element includes a hollow body defining a continuous through-hole that axially penetrates the body for receiving and mounting the capacitor. The body has a lower region defining a lower through-hole portion with a dimension. The body further has a middle...

20060275995 - Semiconductor integrated circuit device and design method thereof: A semiconductor integrated circuit device which is formed on an area comprises a first storage node which is formed on a first area having a first conductive type of the area, the first storage node having a first level, a second storage node which is formed on a second area...

20060275998 - Optical element and method for manufacturing the same: An optical element includes a columnar section having an upper surface for light emission or light incidence, an electrode that is electrically connected to the upper surface of the columnar section, and a mark formed by using a common resist as a mask that is used for forming the electrode....

20060275999 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so...

20060276000 - Semiconductor wafer marking apparatus having marking interlock system and semiconductor wafer marking method using the same: In a semiconductor wafer marking apparatus having a marking interlock system and a semiconductor wafer marking method using the same, the semiconductor wafer marking apparatus includes a laser head unit including a flowcell having a laser radiation region on an upper surface thereof and a laser source radiating laser energy...

20060276001 - Method for manufacturing a semiconductor device having a sti structure: A method for manufacturing a STI structure includes the steps of anisotropic-etching the surface of a silicon substrate to form a trench, forming a first thermal oxide film on the surface of the trench at a substrate temperature of 1000 degrees C. or above, removing the first oxide film, anisotropic-etching...

20060276002 - Integration of buried oxide layers with crystalline layers: A method of forming a buried oxide/crystalline III-V semiconductor dielectric stack is presented. The method includes providing a substrate and forming a layered structure on the substrate comprising of layers of different materials, one of the different materials is selected to be an oxidizable material to form one or more...

20060276007 - Manufacturing method of thin film device substrate: Method of manufacturing a thin film device substrate wherein no trench fabrication is required to be applied onto the substrate surface, and a material which is impervious to light can be used, and the substrate can be peeled off quickly. Firstly, a peeling-off film, a silicon oxide film and an...

20060276004 - Method of fabricating a substrate for a planar, double-gated, transistor process: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate...

20060276005 - Method of segmenting a wafer: First, a device wafer having a substrate layer and a device layer is provided. Then, a first mask pattern is utilized to remove the device layer uncovered by the first mask pattern. Subsequently, a medium layer is formed on the surface of the device wafer, and the medium layer is...

20060276006 - Method of segmenting a wafer: A method of segmenting a wafer. A device wafer is provided, and a medium layer is formed on the upper surface of the device wafer. Then, a carrier wafer is provided, and the medium layer is mounted on the surface of the carrier wafer. Subsequently, a segment process is performed...

20060276003 - Wafer with diamond layer: A method of manufacturing a wafer using a support substrate of a crystalline material. On the surface of the support substrate, a layer of a diamond is grown to form a first wafer in combination with the support substrate. A further substrate is bonded to the surface of the diamond...

20060276008 - Thinning: A method for thinning a wafer layer to a predetermined thickness comprises two phases of thinning. A first thinning phase and a second thinning phase, wherein the first thinning phase is a preparatory thinning phase and the second thinning phase is a final thinning phase, so performed that the structure...

20060276009 - Method for cutting junction board, and chip: A junction board cutting method includes, upon cutting a junction board formed by bonding a second main surface of a first substrate having a first main surface provided with chip areas and scribe areas demarcating the chip areas from one another and the second main surface, and a fourth main...

20060276010 - Arrangement of electronic semiconductor components on a carrier system for treating said semiconductor components with a liquid medium: The invention relates to an arrangement of electronic semiconductor components on a carrier system for treating the semiconductor components with a liquid medium. A semiconductor component is detachably mounted on the carrier system with the active side thereof in such a way that the arrangement comprises a gap at least...

20060276011 - Amorphization/templated recrystallization method for hybrid orientation substrates: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first...

20060276012 - Method of manufacturing a semiconductor device: When a laser beam is irradiated onto a semiconductor film, a steep temperature gradient is produced between a substrate and the semiconductor film. For this reason, the semiconductor film contracts, so that a warp in the film occurs. Therefore, the quality of a resulting crystalline semiconductor film sometimes deteriorates. According...

20060276013 - Sequential lateral solidification mask: A mask used in a sequential lateral solidification process to fabricate a multi-boundary polysilicon. The mask comprises a first portion, a second portion and a third portion. The first and the third portions are translucent to light, and the second portion is opaque. These three portions have the same shape...

20060276014 - Self-aligned high-energy implantation for deep junction structure: A self-aligned high-energy implantation process of forming a deep junction structure. For exposing a predetermined region of a semiconductor substrate, a masking structure has a gate layer, a hard mask layer patterned on the gate layer, and a photoresist layer covering parts of said semiconductor substrate, said gate layer and...

20060276015 - Method and apparatus for reducing dielectric charging in mems structures: A Micro-Electro-Mechanical system (MEMS) device includes a doped semiconductor layer that is disposed outwardly from a substrate. The MEMS device further includes an insulation layer that is disposed outwardly from and in contact with the doped semiconductor layer. The MEMS device also includes a conductive membrane that is disposed outwardly...

20060276016 - Nickel bonding cap over copper metalized bondpads: A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that...

20060276017 - Mos transistor and fabrication method thereof: Disclosed is a method for fabricating a MOS transistor. The present method includes the steps of: (a) forming a gate electrode including a gate insulating layer and a polysilicon gate conductive layer on an active region in a semiconductor substrate; (b) forming a metal layer over the substrate including the...

20060276018 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: forming a plurality of gate lines on a substrate by performing an etching process; forming an oxide layer on the gate lines and the substrate by employing an atomic layer deposition (ALD) method; and sequentially forming a buffer...

20060276019 - Method for production of contacts on a wafer: The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved...

20060276020 - Deposition methods for barrier and tungsten materials: Embodiments are provided for a method to deposit barrier and tungsten materials on a substrate. In one embodiment, a method provides forming a barrier layer on a substrate and exposing the substrate to a silane gas to form a thin silicon-containing layer on the barrier layer during a soak process....

20060276021 - Method for forming metal line of semiconductor device: A method for forming a metal line of a semiconductor device includes: forming an insulating layer on a substrate; sequentially forming a first barrier metal layer and a metal layer on the insulating layer; forming a second barrier metal layer on the metal layer; coating a photoresist on the second...

20060276022 - Capping copper bumps: A structure including a substrate, a copper bump formed over the substrate, and a barrier layer comprising an alloy of at least one of iron and nickel, formed over the copper bump, and methods to make such a structure....

20060276023 - Method for forming bumps: A method for forming bumps is disclosed. First, a substrate having an under bump metallurgy (UBM) layer thereon is provided. Next, a patterned photoresist is disposed over the surface of the UBM layer, in which an opening is formed within the photoresist to expose part of the UBM layer. Next,...

20060276024 - Process for forming an electronic device including workpieces and a conductive member therebetween: A process for forming an electronic device can include providing a first workpiece including an electronic component that includes an electrode and an organic layer, and providing a second workpiece that includes a conductor. The process can also include reflowing a conductive member between the electrode and conductor. In one...

20060276025 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device comprises forming a laser marking, forming a trench pattern, forming a metal interconnection layer, removing a predetermined portion of the metal interconnection layer, and planarizing the metal interconnection layer. The laser marking is formed in a first region of a wafer, and the...

20060276026 - Semiconductor device and method for fabricating the same: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land...

20060276027 - Interconnects with harmonized stress and methods for fabricating the same: Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A conductive feature in the composite low-k dielectric layer passes through the at least one...

20060276028 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes providing a semiconductor substrate on which a plurality of transistors are defined; forming a wiring pattern over the transistors, the wiring pattern contacting at least one transistor; depositing a first oxide film over the wiring pattern; defining a first contact hole on...

20060276029 - Semiconductor device and method for manufacturing same: The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203...

20060276030 - Novel method to implement stress free polishing: A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal layer having a substantially planar surface over the low-k dielectric layer using spin-on method, and stress free polishing the metal layer. Preferably,...

20060276031 - Method for forming via-hole in semiconductor device: Disclosed is a method for forming a via-hole for interconnection of metallization and/or metal wires in a semiconductor device. The present method may include the steps of: (a) forming an insulating layer on a semiconductor substrate including a lower metallization and/or metal wiring; (b) forming a mask (e.g., a photo-resist...

20060276032 - Fabrication method for a semiconductor device: There is provided a method of fabricating a semiconductor device including forming a first film on a base layer, forming a first mask pattern on the first film, the first mask pattern having mask portions arranged at a given pitch, forming first sidewall films on sidewalls of the first mask...

20060276033 - Adhesion of tungsten nitride films to a silicon surface: A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si—NH2 is formed on the...

20060276035 - Contact structure and contact liner process: A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure...

20060276034 - Forming via contacts in mram cells: A method of forming a via contact in the manufacture of a magnetoresistive memory cell includes providing a semiconductor substrate including at least one metallic region made of metallic material formed upon a main surface of the substrate. A first layer made of first non-conductive material is deposited at least...

20060276036 - Systems and methods for plasma etching: Systems and methods are disclosed for processing a semiconductor substrate by depositing a conductive layer on the substrate; patterning a set of insulating structures on the substrate; selectively back-biasing the substrate; depositing a layer of material on the substrate; and removing a part of the conductive layer selectively biased to...

20060276037 - Plasma enhanced atomic layer deposition (peald) equipment and method of forming a conducting thin film using the same thereof: A plasma enhanced atomic layer deposition (PEALD) apparatus and a method of forming a conductive thin film using the same are disclosed. According to the present invention of a PEALD apparatus and a method, a process gas inlet lube and a process gas outlet tube are installed symmetrically and concentrically...

20060276040 - Ion implanted microscale and nanoscale device method: A method is used for producing nanoscale and microscale devices in a variety of materials, such as silicon dioxide patterned buried films. The method is inexpensive and reliable for making small scale mechanical, optical, or electrical devices and relies upon the implantation of ions into a substrate and subsequent annealing...

20060276039 - Neck height equalization in magnetic write pole mold: An improved mold, for use in the formation of a perpendicular magnetic write head, is described, together with a process for its manufacture. Conventional alumina is replaced by tantalum in the yoke portion of the mold. When both the tantalum and the alumina areas are simultaneously subjected to reactive ion...

20060276038 - Thermal desorption of oxide from surfaces: Disclosed is a method for removing a layer of native oxide from a surface of a substrate without altering the smoothness of the substrate surface comprising: 1) depositing on the substrate surface a thin sacrificial layer of the substrate surface material, having a thickness sufficient to react with all of...

20060276041 - Chemical mechanical polishing aqueous dispersion, chemical mechanical polishing method, and kit for preparing chemical mechanical polishing aqueous dispersion: A chemical mechanical polishing aqueous dispersion, including: (A) inorganic particles; (B) at least one type of particles selected from the group consisting of organic particles and organic-inorganic composite particles; (C) at least one compound selected from the group consisting of quinolinecarboxylic acid, quinolinic acid, a divalent organic acid (excluding quinolinic...

20060276042 - Versatile system for conditioning slurry in cmp process: The present invention provides a system (100) for conditioning multi-component slurries utilized in chemical mechanical polishing (CMP) of semiconductor wafers (140). The system provides a first slurry component (108), and a second slurry component (120). A conditioning component (102) has first and second inlets, and an outlet operatively coupled to...

20060276043 - Method and systems for single- or multi-period edge definition lithography: Methods and systems for multiperiod, edge definition lithography are disclosed. According to one method, a first material is isotropically deposited on a substrate and on a field mesa also located on the substrate. The first masking material is then anisotropically removed from the substrate to leave a nanometer-pitched sidewall adjacent...

20060276044 - Method for manufacturing metal microstructure: A method of manufacturing a metal microstructure (1) by using a resin mold (13). In order to provide a method in which a mild manufacturing condition which causes less damage to the resin mold (13) can be set and the high-precision metal microstructure (1) can be mass-produced by uniform electroforming,...

20060276045 - Hard mask structure for deep trenched super-junction device: A hard mask structure is disclosed. The hard mask structure is used for manufacturing a deep trench of a super-junction device having a substrate and an epitaxial layer formed on the substrate. The hard mask structure comprises an ion barrier layer formed on the epitaxial layer for blocking ions from...

20060276046 - Substrate processing system and substrate processing method: A substrate processing system processes a plurality of substrates in a single-substrate processing mode by a plurality of processes and provided with a plurality of modules respectively for carrying out processes. When a defect is found in a substrate, a defective processing unit that caused the defect can be easily...

20060276047 - Macroporous silicon microcavity with tunable pore size: A biological sensor which includes: a macroporous semiconductor structure comprising a central layer interposed between upper and lower layers, each of the upper and lower layers including strata of alternating porosity; and one or more probes coupled to the porous semiconductor structure, the one or more probes binding to a...

20060276048 - Methods of etching nickel silicide and cobalt silicide and methods of forming conductive lines: The invention includes methods of etching nickel silicide and cobalt silicide, and methods of forming conductive lines. In one implementation, a substrate comprising nickel silicide is exposed to a fluid comprising H3PO4 and H2O at a temperature of at least 50° C. and at a pressure from 350 Torr to...

20060276049 - High efficiency trap for deposition process: The present invention provides a system, apparatus and method for improving the efficiency of a semiconductor processing system, such as a deposition system by decreasing or substantially eliminating the accumulation of by-products in the apparatus components of the semiconductor processing system. The present invention further relates to improving the efficiency...

20060276050 - Method for manufacturing crystalline dielectric film,crystalline dielectric film manufactured thereby and thin film capacitor having the same: The invention provides a method for manufacturing a crystalline dielectric film by which the crystalline dielectric film can be formed at a low temperature of 300° C. or less. In the manufacturing method of the invention, first, an amorphous dielectric film is formed on a substrate. Then, the amorphous dielectric...

20060276051 - Oxidation method and oxidation system: An oxidation method is capable of forming oxide films in an improved interfilm thickness uniformity. The oxidation method includes the steps of supplying an oxidizing gas and a reducing gas into a processing vessel 22 capable of being evacuated and holding a plurality of workpieces W arranged at predetermined pitches,...

20060276052 - Method for producing a component comprising at least one germanium-based element and component obtained by such a method: The method successively comprises production, on a substrate, of a stack of layers comprising at least one first layer made from germanium and silicon compound initially having a germanium concentration comprised between 10% and 50%. The first layer is arranged between second layers having germanium concentrations comprised between 0% and...

20060276053 - Spin-on glass composition, method of preparing the spin-on glass composition and method of forming a porous silicon oxide layer using the spin-on glass composition: e

20060276054 - In situ oxide cap layer development: A method of processing a substrate including depositing a low dielectric constant film comprising silicon, carbon, and oxygen on the substrate and depositing an oxide rich cap on the low dielectric constant film is provided. The low dielectric constant film is deposited in the presence of low frequency RF power...

20060276055 - Method of forming an oxygen- or nitrogen-terminated silicon nanocrystalline structure and an oxygen- or nitrogen-terminated silicon nanocrystalline structure formed by the method: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of...

20060276056 - Nanotube articles with adjustable electrical conductivity and methods of making the same: Nanotube articles having adjustable electrical conductivity, and methods of making the same. A patterned article includes conducting nanotubes that define a plurality of conductive pathways along the article, and also includes nanotubes of modified electrical conductivity. The modified nanotubes may electrically isolate the conducting nanotubes from other conductors. The nanotube...