Semiconductor device manufacturing: process inventions 10/06

20060240574 - Method for manufacturing semiconductor device: A semiconductor manufacturing apparatus A semiconductor manufacturing apparatus comprises a hot plate which heats a sapphire substrate; a support table having a support plate disposed with being spaced away from the hot plate by a predetermined interval, and support portions which respectively support the sapphire substrate with being spaced by...

20060240575 - Thin film optical detectors for retinal implantation and methods for making and using same: The present invention provides a method for capturing optical micro detectors for improved surgical handling during implantation into an eye comprising the steps of providing an optically active thin film heterostructure on a soluble substrate; forming an array comprising individual optical microdetectors from the optically active thin film heterostructure; attaching...

20060240577 - Ferroelectric capacitor and manufacturing method thereof: The present invention provides a method for manufacturing a ferroelectric capacitor, comprising the steps of sequentially forming a first conductive film on a semiconductor substrate, a ferroelectric film on the first conductive film, and a second conductive film on the ferroelectric film respectively; etching the second conductive film to form...

20060240576 - Process for fabricating an integrated circuit including a capacitor with a copper electrode: The process and integrated circuit include at least one capacitor in which at least one of the electrodes is made of copper. The method includes forming a nitrogen-doped silicon carbide film between the copper electrode and the dielectric film of the capacitor....

20060240578 - Device mounting substrate and method of repairing defective device: A method of repairing a defective one of devices mounted on substrate is provided. Devices are arrayed on a substrate and electrically connected to wiring lines connected to a drive circuit, to be thus mounted on the substrate. The devices mounted on the substrate are then subjected to an emission...

20060240579 - Method for reducing threshold voltage variations due to gate length differences: The invention provides a method of reducing threshold voltage variations due to gate length differences. The method comprises: providing a substrate having a plurality of MOS transistors at different gate lengths, pocket implanting these MOS transistors at different angles, establishing a relationship between the threshold voltages and gate lengths on...

20060240581 - Method for assembling testing equipment for semiconductor substrate: Upon an assembly of a probe head unit, the relative positions of the probe pins 28ai to those of the electrode group 24E in the pitch-changing substrate 24 are determined by making the positions of the through-holes 26A, 26B, 26C and 26D in the contact block 26 to coincide with...

20060240580 - Method for evaluating reproduced images of wafers: Method for evaluating recorded images of wafers is disclosed. The recording of an image of at least one reference wafer is followed by the determination and representation, on a user interface, of the radial distribution of the measured values of the reference wafer as a radial homogeneity function. A radially...

20060240582 - Methods relating to the reconstruction of semiconductor wafers for wafer-level processing: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface...

20060240584 - Method of producing nitride-based semiconductor device, and light-emitting device produced thereby: A method of producing a nitride-based semiconductor device includes the steps of growing an InxAlyGa1-x-yN(0≦x, 0≦y, x+y<1) buffer layer (2; 12; 22; 32; 42) on a substrate (1; 11; 21; 31; 41) at a first substrate temperature, and growing a first conductivity type nitride-based semiconductor layer (4; 14; 24; 34;...

20060240585 - Package-integrated thin film led: LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth...

20060240583 - Technique for manufacturing silicon structures: A technique for manufacturing silicon structures includes etching a cavity into a first side of an epitaxial wafer. A thickness of an epitaxial layer is selected, based on a desired depth of the etched cavity and a desired membrane thickness. The first side of the epitaxial wafer is then bonded...

20060240586 - Image pickup device and method of manufacturing the same: The present invention relates to an image pickup device, etc., having a structure such that electrostatic discharge is unlikely to occur when an FOP and a CCD reading part are joined. This image pickup device comprises a semiconductor substrate, provided with the CCD reading part on a front surface that...

20060240587 - Transflective liquid crystal display and manufacturing method of the same: A transflective liquid crystal display (LCD) is disclosed where the liquid crystal layer includes a transmission area and a reflective area. The ratio of the liquid crystal molecules to polymers in the reflection area is lower than in the transmission area through independent exposure of the two areas to light...

20060240588 - Method to fabricate a nanowire chemfet sensor device using selective nanowire deposition: A method of fabricating a nanowire CHEMFET sensor mechanism includes preparing a silicon substrate; depositing a polycrystalline ZnO seed layer on the silicon substrate; patterning and etching the polycrystalline ZnO seed layer; depositing an insulating layer over the polycrystalline ZnO seed layer and the silicon substrate; patterning and etching the...

20060240589 - Manufacturing process of semiconductor device: A method of manufacturing a semiconductor device, includes: forming a resin layer with a resin containing an aromatic compound on a surface, where an electrode is formed, of a semiconductor substrate, by avoiding at least part of the electrode; removing an oxide film from a surface of the electrode using...

20060240590 - Controlled synthesis of nanowires, nanodiscs, and nanostructured materials using liquid crystalline templates: A process for synthesizing nanostructures involving providing a first reactant, forming a liquid crystalline template containing the first reactant and contacting the template with a gas phase composed of a second reactant under conditions effective to form nanostructures is disclosed. A method of making a liquid crystalline template by combining...

20060240591 - System and method for processing nanowires with holographic optical tweezers: A system and method for manipulating and processing nanowires in solution with arrays of holographic optical traps. The system and method of the present invention is capable of creating hundreds of individually controlled optical traps with the ability to manipulate objects in three dimensions. Individual nanowires with cross-sections as small...

20060240592 - Integrated circuit package and method for producing it: An integrated circuit includes a first integrated circuit flip chip (105, 205, 305) is bonded to first electric contacts (102, 202, 302) which are an inner part (104, 204, 304) of a planar array (103, 203, 303) of electric contacts. Second electric contacts (106, 206, 306) on the flip chip...

20060240593 - Solid electrolytic capacitor and method for manufacturing the same: In the present invention, a capacitor element including a valve action metal, an oxide film layer formed on the surface of the valve action metal, and a solid electrolytic layer formed on the oxide film layer is provided with an organic compound having a boiling point of not lower than...

20060240594 - Method of making stacked chip electronic package having laminate carrier: A method of making a multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and...

20060240595 - Method and apparatus for flip-chip packaging providing testing capability: A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second...

20060240596 - Semiconductor device with terminals, and method of manufacturing the same: A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval...

20060240597 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, which includes the steps of: removing an abnormal layer formed on a surface of a wiring substrate, the wiring substrate having a first interlayer insulating film formed on a semiconductor substrate, the first interlayer insulating film having a first recess in which a...

20060240598 - Chip scale package: A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder....

20060240599 - Method of manufacturing a semiconductor device: According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead 1e is smaller than that of a silver plating formed on each lead. Thereafter, a semiconductor...

20060240600 - Semiconductor device and method of manufacturing the same: As a means for promoting the increase of the number of pins in a QFN (Quad Non-leaded package), a semiconductor die mounted on a die pad is arranged at the center of a plastic package, and a plurality of leads made of the same metal as the die pad and...

20060240601 - Selective smile formation under transfer gate in a cmos image sensor pixel: A pixel includes a photodiode and a transfer transistor. The transfer transistor is formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. The transfer transistor has a bird's beak structure formed at the interface of its transfer...

20060240603 - Active matrix circuit substrate, method of manufacturing the same, and active matrix display including the active matrix circuit substrate: An active matrix circuit substrate including data lines, select lines, and pixel circuits electrically coupled with a data line and two adjacent select lines. The pixel circuits include a thin film transistor having a gate electrode coupled with one of the two adjacent select lines and a storage capacitor having...

20060240608 - Method and apparatus for crystallizing silicon, method of forming a thin film transistor, a thin film transistor and a display apparatus using same: A light having a pulse frequency higher than about 300 Hz is generated. The light is irradiated on an amorphous silicon thin film for a predetermined time period to form an initial polysilicon crystal. The light is transported in a predetermined direction to grow the initial polysilicon crystal. A laser...

20060240606 - Method of manufacturing a liquid crystal display device: Disclosed is a photoresist film which is formed in a manner of covering at least a source electrode, a source line, a pixel electrode, a drain electrode, a drain line, a semiconductor film and a protective film, and further covering a gate insulting film in their vicinities. Moreover, wet and...

20060240605 - Organic thin film transistor and method of fabricating the same: An organic thin film transistor (TFT) and a method of fabricating the same are provided. In the method, an organic semiconductor layer is formed by mixing carbon nanotubes with an organic semiconductor material or coating the organic semiconductor material on a carbon nanotube layer. The resulting organic semiconductor layer has...

20060240607 - Sectional field effect devices and method of fabrication: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and...

20060240604 - Thin film transistor, integrated circuit, liquid crystal display, method of producing thin film transistor, and method of exposure using attenuated type mask: A method of producing a thin film transistor comprises irradiating a resist on a glass base plate with a ray from a light source through a mask and, thereafter, developing the resist to form contact holes, using an i-ray as the ray....

20060240602 - Transistor for active matrix display and a method for producing said transistor: A transistor for active matrix display and a method for producing the transistor (1). The transistor (1) includes a microcrystalline silicon film (5) and an insulator (3). The crystalline fraction of the microcrystalline silicon film (5) is above 80%. According to the invention, the transistor (1) includes a plasma treated...

20060240609 - Semiconductor device and method for regional stress control: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried...

20060240610 - Structure and method for dual-gate fet with soi substrate: A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized...

20060240611 - Substrate engineering for optimum cmos device performance: An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has...

20060240612 - Non-volatile memory devices with charge storage insulators and methods of fabricating such devices: A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines...

20060240613 - Methods of operating electrically alterable non-volatile memory cell: A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region....

20060240614 - Field effect transistor: A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor...

20060240621 - Double gate transistors having at least two polysilicon patterns on a thin body used as active region and methods of forming the same: Double gate transistors having at least two polysilicon patterns on a thin body used as an active region and methods of forming the same are provided. Embodiments of the transistors and methods provided are capable of enhancing current drivability of a semiconductor memory device using polysilicon patterns having different impurity...

20060240617 - Formation method of an array source line in nand flash memory: Methods 500 and 550 are disclosed for fabricating an array source line structure in a wafer of a NAND flash memory device. One method aspect 500 comprises forming 510 a first oxide 610 and a nitride layer 611 of an ONO stack 620 over a substrate 604 and an STI...

20060240616 - Memory elements having patterned electrodes and method of forming the same: A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes over a substrate and forming a blanket material stack over the first electrodes. The stack includes a plurality of layers, at least one layer of...

20060240615 - Method of manufacturing a non-volatile memory cell: The present invention relates to a method of manufacturing a non-volatile memory cell. The method comprises forming an ONO stack structure and a mask formed on the ONO stack structure, providing a first etching process to form a first spacer surrounding the mask, removing the first spacer and the ONO...

20060240622 - Multi-channel semiconductor device and method of manufacturing the same: Provided are a multi-channel semiconductor device and a method for manufacturing the semiconductor device through a simplified process. A sacrificial layer and a channel layer are alternately stacked on a semiconductor substrate. Thereafter, the sacrificial layer and the channel layer are etched to form a separated active pattern, and a...

20060240618 - Non-volatile memory and fabricating method thereof and operation thereof: A method of fabricating a non-volatile memory is provided. A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top...

20060240623 - Nonvolatile memory devices having gate structures doped by nitrogen and methods of fabricating the same: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on...

20060240620 - Semiconductor device and method of manufacturing the same: The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the surface of the semiconductor substrate (10) and being located below the control gates (20) and between...

20060240619 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode...

20060240624 - Single transistor ram cell and method of manufacture: A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped...

20060240625 - Power semiconductor device having improved performance and method: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region....

20060240626 - Write once read only memory employing charge trapping in insulators: Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain...

20060240627 - Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics: In a method for manufacturing a MOS transistor, a MOS transistor isolation layer is formed within a semiconductor substrate to surround an area for forming the MOS transistor in the semiconductor substrate. Then, first impurities are introduced into the area of the semiconductor substrate to adjust a threshold voltage of...

20060240628 - High voltage device and method for forming the same: The invention is directed to a method for manufacturing a high voltage device. The method comprises steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type are formed in...

20060240629 - Self correcting suppression of threshold voltage variation in fully depleted transistors: A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second...

20060240630 - Methods of making substitutionally carbon-doped crystalline si-containing materials by chemical vapor deposition: Methods of making Si-containing films that contain relatively high levels of substitutional dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain 2.4 atomic % or greater substitutional carbon. Substitutionally doped Si-containing films may...

20060240631 - Method for manufacturing a solid-state image capturing device and electric information device: A method for manufacturing a solid-state image capturing device, in which at least one electric charge detection section detects each respective one of a plurality of electric charges photoelectrically converted and accumulated at photoelectric conversion sections provided on a semiconductor substrate, each electric charge detection section being shared by a...

20060240632 - Semiconductor device including air gap between semiconductor substrate and l-shaped spacer and method of fabricating the same: A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a vertical portion covering a side wall of the gate pattern, and...

20060240633 - Methods and systems for on-column protein delipidation: Embodiments of the present invention provide a method of chromatographic delipidation comprising separating a lipid-containing sample on a superficially porous stationary phase at greater than about 70° C., at least about 80° C., having at least one mobile phase comprising an ion-pairing agent in water, an ion-pairing agent in an...

20060240634 - Dram access transistor and method of formation: Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions...

20060240637 - Methods of forming semiconductor constructions: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature...

20060240635 - Self-aligned sti sonos: Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402, for example, an ONO stack 420, removing 312 the multi-layer...

20060240636 - Trench isolation methods of semiconductor device: In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A...

20060240638 - Method for the elimination of the effects of defects on wafers: A method eliminates effects of defects on wafers caused by cavities adjacent to the surface of a semiconductor (e.g., silicon) wafer. A first insulating layer is applied to the surface of the semiconductor wafer and into the cavities adjacent to the surface. The applied first insulating layer is covered with...

20060240639 - Fine patterning method for semiconductor device: An insulation film is formed on a semiconductor substrate. A stopper film, which has a large etching selectivity relative to the insulation film and has a first film thickness, is formed on the insulation film. A first mask material, which has a second film thickness that is less than the...

20060240641 - Apparatus and method for making circuitized substrates in a continuous manner: Apparatus and method for making circuitized substrates using a continuous roll format in which layers of conductor and dielectric are fed into the apparatus, bonded, and passed on to other nearby work stations in which various processes such as hole formation, circuitization and, finally, segmentation occur. The resulting substrates can...

20060240640 - Isostatic pressure assisted wafer bonding method: In the invention, wafers are initially weakly bonded. The weak bond is sufficient to impede penetration of an isostatic pressure transmitting media, e.g., a gas or liquid, into any region between the wafers. The weak bond also permits handling. Weak bonds are strengthened, or new bonds formed, by heating and...

20060240645 - Method and system for source switching and in-situ plasma bonding: A system for in-situ plasma treatment. The system has a processing chamber, e.g., plasma chamber. The system has a first susceptor coupled within the chamber and a second susceptor facing the first susceptor and being within the chamber. The system has one or more power sources. Preferably, a first power...

20060240643 - Method for producing a polymer structure on a substrate surface: A method for producing a polymer structure on a patterning region of a substrate surface includes the steps of depositing an adhesion layer having a first polymer material onto the substrate surface, patterning the adhesion layer such that the first polymer material of the adhesion layer is removed in a...

20060240642 - Method of bonding two wafers of semiconductor materials: The invention relates to a method of bonding together two wafers made of materials selected from semiconductor materials by providing two wafers each having a surface that is suitable for molecular bonding; and conducting plasma activation of at least one surface of one of the wafers by directing plasma species...

20060240644 - Substrate with determinate thermal expansion coefficient: A composite support designed to successfully receive a transfer layer made of a crystalline material so that the assembly forms an epitaxy substrate, with the support having a longitudinal plane of symmetry parallel to its principal surfaces and a plurality of layers. The support includes a central first layer having...

20060240646 - Method of removing residual contaminants from an environment: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound...

20060240647 - Film control method and device thereof: The surface of an amorphous silicon film formed on a glass substrate is cleaned by hydrofluoric acid in a spin clean unit. The glass substrate is conveyed to a waiting unit where the glass substrate is made to wait for about 15 minutes. Active fluoride adhered on the amorphous silicon...

20060240648 - Atmospheric glow discharge with concurrent coating deposition: A plasma is produced in a treatment space (58) by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes (54,56) separated by a dielectric material (64), a precursor material is introduced into the treatment space to coat a substrate film...

20060240649 - Method for depositing silicon: The inventive method for depositing silicon onto a substrate firstly involves the introduction of a reactive silicon-containing gas and hydrogen into the plasma chamber and then the initiation of the plasma. After initiating the plasma, only reactive silicon-containing gas or a gas mixture containing hydrogen is supplied to the plasma...

20060240650 - Semiconductor device having a plurality of different layers and method therefor: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried...

20060240651 - Methods and apparatus for adjusting ion implant parameters for improved process control: A method for processing a substrate, such as a semiconductor wafer, includes performing a measurement to determine a substrate parameter distribution to be compensated, determining an adjusted implant parameter distribution to compensate for the substrate parameter distribution, and implanting the substrate in accordance with the adjusted implant parameter distribution. The...

20060240652 - Very low dielectric constant plasma-enhanced cvd films: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced...

20060240653 - One-device non-volatile random access memory cell: One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between the first diffusion region and...

20060240654 - Process of forming a self-aligned contact in a semiconductor device: A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresist pattern on a surface of the...

20060240655 - Semiconductor device having contact plug formed in double structure by using epitaxial stack and metal layer and method for fabricating the same: Disclosed are a contact plug of a semiconductor device and a method for fabricating the same. The semiconductor device includes: an epitaxial stack formed by inserting a heteroepitaxy layer between a pair of homoepitaxy layers; and a contact plug including a metal layer on the epitaxial stack. Accordingly, in accordance...

20060240656 - Method for forming contact of semiconductor device by using solid phase epitaxy process: A method for forming a contact plug of a semiconductor device includes providing a plurality of junctions on a substrate; forming an inter-layer insulation layer over the substrate and the junctions; forming a plurality of contact holes to expose the junctions by etching the inter-layer insulation layer; forming contact layers...

20060240657 - Semiconductor device and method of manufacturing the same: A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along...

20060240658 - Gap control between interposer and substrate in electronic assemblies: Electronic assemblies and methods for forming assemblies are described. One embodiment includes a method of forming an electronic assembly, including forming a plurality of first solder bumps on one of a substrate and an interposer. The substrate and interposer are positioned so that the first solder bumps are located between...

20060240659 - Metal interconnection structure of a semiconductor device having low resistance and method of fabricating the same: Provided is a metal interconnection structure of a semiconductor device, comprising a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and...

20060240660 - Semiconductor stucture and method of manufacturing the same: A semiconductor structure for a substrate having electronic elements formed thereon. The semiconductor structure comprises a dielectric layer and a conductive stuffing material. The dielectric layer is located over the substrate. It should be noticed that the dielectric layer has a plurality of trenched and a border shape of each...

20060240661 - Method of preventing damage to porous low-k materials during resist stripping: A method of forming a feature in a porous low-K dielectric layer is provided. A porous low-K dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the porous low-K dielectric layer. A feature is etched into the porous low-K dielectric layer. A protective layer is...

20060240662 - Method to perform selective atomic layer deposition of zinc oxide: A method for selective ALD of ZnO on a wafer preparing a silicon wafer; patterning the silicon wafer with a blocking agent in selected regions where deposition of ZnO is to be inhibited, wherein the blocking agent is taken from a group of blocking agents includes isopropyl alcohol, acetone and...

20060240663 - Methods of forming a resistance variable element: The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a deposition chamber comprising a sputtering target and a substrate to be depositing upon. The...

20060240664 - Method of manufacturing multi-layered substrate: A method of manufacturing a multi-layered substrate includes providing an electronic component on a surface of a substrate so that a terminal of the electronic component faces upward. The method also includes providing a first insulation pattern on the surface so as to fill a step generated due to a...

20060240665 - Methods of producing integrated circuit devices utilizing tantalum amine derivatives: In a method for forming a field effect transistor, a metal nitride layer is formed on a gate electode insulating layer. Tantalum amine derivatives represented by the chemical formula Ta(NR1)(NR2R3)3, in which R1, R2 and R3 represent H or a C1-C6 alkyl group, may be used to form the metal...

20060240667 - Method for manufacturing semiconductor device: Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is...

20060240666 - Method of forming silicide: A method of forming silicide is described. A layer of refractory metal is deposited on a substrate, and then a first annealing process is performed to form silicide, followed by removal of unreacted metal. Next, a species implanting process is carried out to implant species of neutral atoms into the...

20060240668 - Semiconductor device with metallic electrodes and a method for use in forming such a device: A semiconductor device comprising: a first electrode component; a second electrode component; a first layer comprising at least a portion of the first electrode component and at least a portion of the second electrode component; a second layer having a portion comprising deposited semiconductor material contacting the first and second...

20060240669 - Method of forming vapor-deposited film and method of manufacturing el display device: A method of forming a vapor-deposited film includes the steps of: aligning a mask having a plurality of openings with a substrate; forming a film on the substrate through the openings of the mask by the use of a vapor deposition method; and cleaning the mask in a state that...

20060240670 - Etching of algainassb: The present invention relates to a wet acid etchant for wet acid etching of intrinsic, n-doped or p-doped Al1−x−zGaxInzAs1−ySby with 0<x<1, 0<y<1, 0≦z<1 and 0<x+z<1, a process for wet acid etching of intrinsic, n-doped or p-doped Al1−x−zGaxInzAs1−ySby with 0<x<1, 0<y<1, 0≦z<1 and 0<x+z<1, and a semiconductor structure prepared by wet...

20060240671 - Method of reducing outgassing pollution: A method for reducing outgassing pollution in a semiconductor process includes matching a pressure of a VCE with a pressure of a process chamber before reaction gas is injected into the process chamber, injecting the reaction gas into the process chamber, opening a partitioning door disposed between the VCE and...

20060240672 - Polishing liquid composition: A polishing liquid composition is applicable as a means of forming embedded metal interconnections on a semiconductor substrate. In a surface to be polished comprising an insulating layer and a metal interconnection layer, the polishing liquid composition is capable of maintaining a polishing speed of the metal layer, of suppressing...

20060240673 - Method of forming bit line in semiconductor device: A method of forming a bit line of a semiconductor device wherein an etch-stop nitride film, a trench oxide film and a hard mask nitride film are formed on a semiconductor substrate. The hard mask nitride film and the trench oxide film are etched to a limited etch thickness of...

20060240674 - Method for manufacturing semiconductor device: A gate electrode is formed of a laminate structure comprising a plurality of conductive layers such that the width along the channel of a lower first conductive layer is larger than that of an upper second conductive layer The gate electrode is used as a mask during ion doping for...

20060240675 - Removal of silicon oxycarbide from substrates: A method of treating a substrate comprises depositing silicon oxycarbide on the substrate and removing the silicon oxycarbide from the substrate. The silicon oxycarbide on the substrate is decarbonized by exposure to an energized oxygen-containing gas that heats the substrate and converts the layer of silicon oxycarbide into a layer...

20060240676 - Lawn and garden battery clamp: An improved battery cable clamp provides for toolless attachment of battery cable connectors to lawn and garden-type battery terminal posts utilizing a bossed handle, cam seat and thumbnut, preferably made of non-corrosive materials....

20060240677 - Method for manufacturing semiconductor device and substrate processing apparatus: An oxidizer supply device (30) comprises an ozonizer (31) for generating ozone (32), a bubbler (34) wherein deionized water (35) is kept and an ozone supply pipe (33) for supplying ozone (32) from the ozonizer (31) is immersed in the deionized water (35) so as to bubble ozone, and a...

20060240678 - Method of forming a lp-cvd oxide film without oxidizing an underlying metal film: A method of manufacturing a semiconductor device includes forming a LP-CVD oxide film on sides of a gate including a metal film by means of a LP-CVD method that does not cause oxidization of the metal film. Oxidization of a metal film can be prevented physically, and degradation of the...

20060240679 - Method of manufacturing semiconductor device having reaction barrier layer: A method of manufacturing a semiconductor device comprises forming a lower electrode on a substrate using a titanium chloride pulsed deposition (TPD) process, forming a high-k dielectric layer on the lower electrode, and forming an upper electrode on the dielectric layer using a TPD process. The method further comprises forming...

20060240680 - Substrate processing platform allowing processing in different ambients: A semiconductor wafer processing system including a factory interface operating at atmospheric pressure and mounting plural wafer cassettes and plural wafer processing chambers connected to the factory interface through respective slit valves. A robot in the factory interface can transfer wafers between the cassettes and the processing chambers. At least...

20060240681 - Three-dimensional nanoscale crossbars: Various embodiments of the present invention include three-dimensional, at least partially nanoscale, electronic circuits and devices in which signals can be routed in three independent directions, and in which electronic components can be fabricated at junctions interconnected by internal signal lines. The three-dimensional, at least partially nanoscale, electronic circuits and...

20060234394 - Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo,...

20060234393 - Scalable high density non-volatile memory cells in a contactless memory array: A plurality of split gate non-volatile memory cells are formed vertically in a trench along the sidewalls. Each cell is comprised of a bistable element and an adjacent fixed gate threshold element that share a common respective control gate/access gate. The bistable element has a gate insulator stack that is...

20060234397 - Magnetic annealing sequences for patterned mram synthetic antiferromagnetic pinned layers: A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an antiferromagnetic pinning layer over a substrate and a ferromagnetic pinned layer over the pinning layer, the pinned layer having a first thickness. The fixed layer...

20060234395 - Method for manufacturing perovskite type oxide layer, method for manufacturing ferroelectric memory and method for manufacturing surface acoustic wave element: A method for manufacturing a perovskite type oxide layer includes the steps of: forming, above a substrate, a first oxide layer composed of perovskite type oxide; forming, above the first oxide layer, a second oxide layer composed of at least one of a perovskite type oxide layer crystallized at a...

20060234396 - Method for producing structure: Disclosed is a method for producing a structure having: a stripping step in which an aluminum member including an aluminum substrate and an anodized layer present on the aluminum substrate, which layer contains micropores having an average pore diameter of 10 to 500 nm and a coefficient of variation in...

20060234398 - Single ic-chip design on wafer with an embedded sensor utilizing rf capabilities to enable real-time data transmission: An apparatus and method for real-time monitoring process conditions of a semiconductor wafer processing operation. A semiconductor wafer subject to processing in a wafer processing tool is embedded with one or more sensor devices. In response to receipt of wireless electromagnetic signals, the embedded sensor devices are activated for generating...

20060234399 - Meander metal line under the pad for improved device mm esd performance: A method is disclosed for enhancing ESD protection of integrated circuit devices. The method entails placing a resistor between an I/O pad and an ESD protection device on a semiconductor chip so that one end of the resistor connects to pins on said I/O pad and the other end connects...

20060234401 - Early detection test for identifying defective semiconductor wafers in a front-end manufacturing line: A method and apparatus for identifying defective partially manufactured semiconductor wafers in a manufacturing line is described, wherein defects caused by silicon erosion created by over-etching the wafer can be detected. The method described herein is based on an in-line test of selected structures, such as FETs, located in the...

20060234404 - Method for predicting and optimizing chip performance in cured thermoset coatings: Disclosed is a method for evaluating chip performance of a cured coating system. In one embodiment, the method includes providing a coated substrate comprising a substrate and a cured film of a first coating composition thereon, measuring elastic work energy (We/Wtot) of the cured film, and calculating a % C.P....

20060234400 - Method of judging quality of semiconductor epitaxial crystal wafer and wafer manufacturing method using the same: In a method of determining the quality of a semiconductor epitaxial crystal wafer having a buffer structure portion comprised of epitaxial layers the semiconductor epitaxial crystal wafer (S) is irradiated with pulsed exciting light (5A) to modulate an internal electric field of the buffer structure portion, the electric transport properties...

20060234402 - Method of recipe control operation: An operation method of a recipe control process in which multiple processing targets are processed continuously in a processing apparatus using recipes that specify a set of control parameters specifying the processing conditions of processing targets. The method comprises the steps of: (I) specifying correction coefficients to correct at least...

20060234403 - Wat process to avoid wiring defects: A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer....

20060234405 - Semiconductor device with self-aligning contactless interface: Contactless interconnects between an integrated circuit die and an electrical structure are aligned by charging alignment pads on the integrated circuit die to a first voltage, and charging counterpart alignment pads on the electrical structure to a second voltage. The integrated circuit die is disposed in an initial position relative...

20060234406 - Method of forming protective structure for active matrix triode field emission device: A method for forming a protective structure of active matrix triode field emission device is provided. The method comprises the steps of forming a silicon active region; depositing a gate oxide layer over the silicon active region; depositing and patterning a first metal layer over the gate oxide layer; doping...

20060234408 - Method for manufacturing vertical group iii-nitride light emitting device: The invention provides a vertical group III-nitride light emitting device improved in external extraction efficiency and a method for manufacturing the same. The method includes forming an undoped GaN layer and an insulating layer on a basic substrate. Then, the insulating layer is selectively etched to form an insulating pattern,...

20060234407 - Method of fabricating vertical structure nitride semiconductor light emitting device: A method of fabricating a vertical structure nitride semiconductor light emitting device having a cross-sectional shape of a polygon having five or more sides or a circle. A light emitting structure is formed on a sapphire substrate. A metal layer having a plurality of patterns is formed on the light...

20060234409 - Light emitting device, display apparatus with an array of light emitting devices, and display apparatus method of manufacture: A light emitting device and display apparatus using a plurality of light emitting devices can drastically reduce contrast loss due to light from an external source. The light emitting device has a light emitting chip(s) and a first layer covering the light emitting chip(s). A second layer including a light...

20060234410 - Method for fabricating organic electroluminescent devices: A method for fabricating organic electroluminescent elements comprising an LTPS-TFT as driving circuits. The method comprises providing a substrate, forming an LTPS-TFT on the substrate, and forming an OLED electrically connecting the LTPS-TFT. Specifically, the method for forming a channel region of the LTPS-TFT includes forming a polysilicon layer with...

20060234411 - Method of manufacturing nitride semiconductor light emitting diode: The invention relates to a method of manufacturing a semiconductor light emitting diode. In the method, an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer are formed sequentially on a substrate. Then, a nickel oxide (NiOx) film is directly deposited on the p-type semiconductor layer...

20060234412 - Mems release methods: A packaged MEMS device is fabricated by providing a first substrate, forming the MEMS device on the first substrate (the MEMS device including at least one element initially held immobile by a sacrificial material), optionally removing a portion of the sacrificial material without releasing the element, providing a second substrate,...

20060234413 - Method for forming anti-stiction bumps on a micro-electro mechanical structure: A technique for forming anti-stiction bumps on a bottom surface of a micro-electro mechanical (MEM) structure includes a number of process steps. The MEM structure is fabricated from an assembly that includes a support substrate bonded to a single-crystal semiconductor layer, via an insulator layer. A plurality of holes are...

20060234414 - Calorimetric flow meter: An encapsulated calorimetric flow meter according to the present invention comprises an integrated circuit (104) mounted on a lead frame (102). The integrated circuit has a channel (105) provided in its lower face, the channel being aligned with two holes (103) provided in the lead frame, the holes coinciding with...

20060234415 - Solid state imaging apparatus and driving method of solid state imaging apparatus: A solid state imaging apparatus comprises a semiconductor substrate, photoelectric conversion elements, a vertical electric charge transferring device, a horizontal electric charge transferring device that temporarily stores the signal electric charges transferred from the vertical electric charge transferring device and transfers the signal electric charges to a horizontal direction in...

20060234416 - Light emitting device and manufacturing method therefor: To provide a light emitting element having a top emission structure, which can be easily manufactured without considering an ionization potential of an electrode (particularly an electrode in contact with a substrate) and a manufacturing method therefor. A light emitting device having the top emission structure according to the present...

20060234417 - Composite nanoparticle and process for producing the same: There is provided composite nano-particles comprising nano-crystal particles dispersed stably and individually in suspension in high concentration without mutual aggregation of the nano-particles. A determined amount of pure water or deionized water is poured into a reactor, into which is introduced nitrogen gas at rate of 300 cm3/min for a...

20060234418 - Method for fabricating a nonvolatile memory element and a nonvolatile memory element: In a method for fabricating a nonvolatile memory element a substrate is provided, a nanomask structure is fabricated on the substrate and a self-assembled monolayer of an organic memory molecule is grown on the substrate on a region not covered by the nanomask structure. A surface of the substrate is...

20060234419 - Diamond medical devices: Masked and controlled ion implants, coupled with annealing or etching are used in CVD formed single crystal diamond to create structures for both optical applications, nanoelectromechanical device formation, and medical device formation. Ion implantation is employed to deliver one or more atomic species into and beneath the diamond growth surface...

20060234420 - Electronic device: In an electronic device having an interposer substrate as an MCM structure, heat dissipation properties are enhanced while the reliability of joint between the interposer substrate and a mother board is maintained. In the invention, a metal core base material of great heat capacity and high thermal conductivity is used...

20060234421 - Method of forming a substrateless semiconductor package: A method of forming a substrateless semiconductor package (10) includes forming a carrier (16) on a base plate (12) and attaching an integrated circuit (IC) die (32) to the carrier (16). The IC die (32) then is electrically connected to the carrier (16). A molding operation is performed to encapsulate...

20060234422 - Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers: Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors...

20060234423 - System for providing a redistribution metal layer in an integrated circuit: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder...

20060234425 - Method of manufacture of a pcram memory cell: The invention provides a method of forming a resistance variable memory element and the resulting element. The method includes forming an insulating layer having an opening therein; forming a metal containing layer recessed in the opening; forming a resistance variable material in the opening and over the metal containing layer;...

20060234424 - Technique for compensating for substrate shrinkage during manufacture of an electronic assembly: Substrate shrinkage that occurs during manufacture of an electronic assembly is compensated for by the incorporation of a horizontal line, having a plurality of vertical graduations, across a horizontal portion of a substrate and a vertical line, having a plurality of horizontal graduations, across a vertical portion of the substrate....

20060234426 - Leadframe with encapsulant guide and method for the fabrication thereof: A method for fabricating a leadframe with encapsulant guide is provided, including forming a die attach paddle. Leads are formed around at least portions of the die attach paddle, and encapsulant guides are formed angled on a plurality of the leads to push the leads outwardly when an encapsulant flows...

20060234427 - Underfill dispense at substrate aperture: Disclosed are methods for dispensing underfill material in an IC assembly having a die mounted on a substrate with a gap therebetween. One or more aperture is provided in the substrate for receiving underfill material into the gap. Underfill material is dispensed into the gap through the one or more...

20060234429 - Method for fabricating thin film transistor of liquid crystal display device: A method for fabricating a thin film transistor for an LCD device is presented that uses six mask processes. Portions of a semiconductor layer formed on a substrate are doped with first and second impurities in different regions. A conductive layer is deposited and the conductive and semiconductor layers patterned...

20060234428 - Methods of implementing and enhanced silicon-on-insulator (soi) box structures: Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The...

20060234430 - Tft fabrication process: A process for fabricating a thin film transistor including: (a) depositing a semiconductor layer; and (b) depositing a multilayer gate dielectric prior to or subsequent to the depositing the semiconductor layer, wherein the multilayer dielectric comprises: (i) a first layer comprising a first material selected from the group consisting of...

20060234431 - Doping of semiconductor fin devices: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface....

20060234432 - Soi bottom pre-doping merged e-sige for poly height reduction: Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive...

20060234434 - Pecvd nitride film: A method for forming a semiconductor device is provided. In accordance with the method, a substrate (103) is provided, and a dielectric material (123) is formed on the substrate through plasma enhanced chemical vapor deposition (PECVD). The PECVD is conducted at a temperature of greater than 300° C., and utilizes...

20060234433 - Transistors and methods of manufacture thereof: Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate comprises a layer...

20060234435 - Semiconductor device having one-time programmable rom and method of fabricating the same: A semiconductor device with a one-time programmable (OTP) ROM disposed over a semiconductor substrate including a memory cell area and a peripheral circuit area includes a MOS transistor and an OTP ROM capacitor. The MOS transistor has a floating gate electrode and is disposed at the memory cell area. The...

20060234436 - Method of forming a semiconductor device having a high-k dielectric: A metal oxide is formed over a high quality oxide which has been deposited over a substrate. An anneal drives a reaction to form a metal oxysilicon nitride layer which is then used as a part of a gate stack. The novel integration scheme allows for improved scalablity of devices...

20060234437 - Recessed-type field effect transistor with reduced body effect: For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the...

20060234438 - Self-aligned contact for silicon-on-insulator devices: A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation...

20060234439 - Maskless multiple sheet polysilicon resistor: The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer is patterned to form a polysilicon resistor (108). A poly resistor mask having a selected...

20060234440 - Alignment mark and alignment method for the fabrication of trench-capacitor dram devices: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench...

20060234441 - Method for preparing a deep trench: A method for preparing a deep trench first forms a trench in a semiconductor substrate and a stacked structure in the trench, wherein the stacked structure includes at least one nitrogen-containing layer. A phosphorous oxide layer is then formed on the surface of the nitrogen-containing layer. The phosphorous oxide is...

20060234442 - Semiconductor device and method of fabricating the same: According to an aspect of the invention, there is provided a semiconductor device comprising a capacitor formed above a semiconductor substrate by sandwiching a dielectric film between a lower electrode and an upper electrode including an electrode film which contains an MOx type conductive oxide (M is a metal element,...

20060234443 - Mim capacitor and method of fabricating same: A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a...

20060234449 - Flash gate stack notch to improve coupling ratio: A semiconductor flash memory device with increased gate coupling ratio and a method of preparing this flash memory device. The semiconductor flash memory device includes a notched floating polysilicon gate. The notches are at the interface between the floating polysilicon layer and the tunneling dielectric layer. The notches reduce the...

20060234447 - Methods of fabricating nonvolatile memory devices and related devices: Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate...

20060234445 - Mtj read head with sidewall spacers: Following CMP, a magnetic tunnel junction stack may protrude through the oxide that surrounds it, making it susceptible to possible shorting to its sidewalls. The present invention overcomes this problem by depositing silicon nitride spacers on these sidewalls prior to oxide deposition and CMP. So, even though the stack may...

20060234446 - Non-volatile memory and fabricating method thereof: A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a...

20060234450 - Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel...

20060234448 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an element isolation insulating film, memory cell transistors formed in an element isolation region and having respective gate electrodes, and a stopper film for forming a contact, formed both on a sidewall of the gate electrode of each transistor and on the element isolation insulating film...

20060234444 - Split gate flash memory cell and manufacturing method thereof: A split gate flash memory cell includes a substrate having a device isolation structure; a selective gate structure disposed on the substrate; an interlayer dielectric layer having an opening disposed on the substrate, wherein the opening exposes a portion of the selective gate structure, the substrate and the device isolation...

20060234451 - Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor: The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements...

20060234452 - Non-volatile memory and fabricating method thereof: A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control...

20060234453 - Non-volatile memory and fabrication method thereof: A non-volatile memory cell is provided. The non-volatile memory includes a substrate, a gate stacked layer, an isolation layer and a conductive layer. The gate stacked layer includes a tunneling layer, a charge trapping layer, a barrier layer and a control gate layer sequentially stacked over the substrate, and the...

20060234454 - Method of fabricating nonvolatile semiconductor memory devices with uniform sidewall gate length: After forming a first dielectric film on the main surface of a semiconductor substrate, a first conductive film is formed on the first dielectric film, and then, the surface of the first conductive film is planarized by a CMP method. Subsequently, the first conductive film and the first dielectric film...

20060234455 - Structures and methods for forming a locally strained transistor: Embodiments of the invention provide structures and methods for forming a strained MOS transistor. A preferred embodiment includes creating a compressive strain in a PMOS transistor for improving carrier mobility without the need for source/drain recess formation and SiGe epitaxy. Embodiments comprise forming a gate electrode on a silicon substrate,...

20060234456 - Four-bit finfet nvram memory device: A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and...

20060234457 - Non-volatile memory device and method of fabricating the same: A method of fabricating an a non-volatile memory includes forming trench isolation regions in an inactive region of a semiconductor substrate, adjacent trench isolation regions defining respective protrusions having rounded edges therebetween, wherein upper surfaces of the trench isolation regions are lower than an upper surface of the semiconductor substrate...

20060234458 - Dual wavelength thermal flux laser anneal: A thermal processing apparatus and method in which a first laser source, for example, a CO2 emitting at 10.6 μm is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer...

20060234459 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device in which a plurality of wiring layers are formed includes the steps of (a) preparing a semiconductor device on which a plurality of semiconductor elements are formed on one surface thereof, (b) forming a spiral inductor on the semiconductor substrate astride three or...

20060234460 - Method for making cable with a conductive bump array, and method for connecting the cable to a task object: A cable with conductive bumps is fabricated by forming a photoresist layer with multiple openings on a cable substrate, coating a conductive layer on the photoresist layer whereby the conductive layer in the openings forms the bumps at circuits on the cable substrate, and then removing the photoresist layer. When...

20060234461 - Process for cleaning silicon substrate: In the production process of an SOI substrate using a hydrogen ion implantation method, a process is provided for cleaning the substrate which can prevent formation of voids when bonding substrates and formation of blistering after exfoliation. In the process for cleaning, cleaning of the substrate is performed before performing...

20060234462 - Method of operating a multi-terminal electronic device: A method of operating a multi-terminal electronic device. The device includes an active material in electrical communication with three or more electrical terminals. The active material is able to undergo a transformation from one state to another state, where the two states differ in resistance. The method includes the step...

20060234463 - Method for fabricating an electrical component: An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the...

20060234464 - Method for fabricating an integrated circuit comprising a three-dimensional capacitor: A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form...

20060234466 - Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three...

20060234465 - Methods of forming materials comprising tungsten and nitrogen, and methods of forming capacitors: In one aspect, the invention includes a method of forming a material comprising tungsten and nitrogen, comprising: a) providing a substrate; b) depositing a layer comprising tungsten and nitrogen over the substrate; and c) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a...

20060234469 - A method of forming semiconductor structures: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c)...

20060234468 - Method for manufacturing a semiconductor device, as well as a semiconductor substrate: A method for manufacturing a semiconductor device, includes: forming a recognition mark that defines a well-forming region for forming a well on a semiconductor substrate; forming a mask, using the recognition mark, that is patterned so that the well-forming region is opened; introducing an impurity into the well-forming region; performing...

20060234467 - Method of forming trench isolation in a semiconductor device: Divots (35, 36) may particularly be a problem for isolation trenches (22, 24) that are shallow. These divots (35, 36) may have a negative impact on the performance of the integrated circuit (49). Densification heating may be used to reduce the size and/or depth of these divots (35, 36) during...

20060234470 - Process sequence for doped silicon fill of deep trenches: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way...

20060234471 - Method for manufacturing semiconductor device: A semiconductor device having an improved connecting reliability of an interconnect is presented via a simple and easy process, and further, a semiconductor device having a stable threshold voltage of a transistor that provide a stable electrical characteristic is also presented. A method for manufacturing a semiconductor device according to...

20060234472 - Method and device for pre-treating surfaces of substrates to be bonded: The present invention provides a process and a device for treating the surfaces or bonding surfaces of substrates before bonding the substrates. In accordance with the invention, the surfaces of substrates to be bonded are treated with an atmospheric plasma before bonding. The surfaces of the substrates can thus be...

20060234473 - Thin passivation layer on 3d devices: Embodiments of the invention include a device with stacked substrates. Conducting interconnecting structures of one substrate are bonded to conducting interconnecting structures of another substrate. A passivating layer may be on the conducting interconnecting structures between the substrates and may be formed by an atomic layer deposition process or a...

20060234474 - Method of transferring a thin crystalline semiconductor layer: A method for transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and transfer of the monocrystalline thin layer with the cleaving controlled to happen within...

20060234476 - Electronic component and method for its production: An electronic component includes a semiconductor die which exhibits on its active top side above an active surface area a self-supporting electrically conductive cover layer which is supported by through lines and forms a hollow space to the active surface area. A method for producing the electronic component includes additional...

20060234475 - Method for manufacturing semiconductor device: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a dummy contact hole is formed in a scribe lane by employing a direct polyimide etching (‘DPE’) process reducing the two steps of a masking process to one step and a passivation layer filling up...

20060234477 - Glass-based semiconductor on insulator structures and methods of making same: Methods and apparatus provide for: a semiconductor wafer; at least one porous layer in the semiconductor wafer; an epitaxial semiconductor layer directly or indirectly on the porous layer; and a glass substrate bonded to the epitaxial semiconductor layer via electrolysis....

20060234478 - Semiconductor device substrate and method of manufacturing semiconductor device substrate: A method of manufacturing a semiconductor device substrate includes forming a mask layer pattern on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the...

20060234479 - Implantation-less approach to fabricating strained semiconductor on isolation wafers: A method of fabrication of semiconductor substrate structure comprising the following. A buffer layer is formed on the Si Substrate. We form a SiGe layer on the novel buffer layer. The buffer layer has defects therein so that the buffer layer is oxidized to form a buried isolation layer comprised...

20060234480 - Low temperature melt-processing of organic-inorganic hybrid: The present invention provides a process for preparing a melt-processed organic-inorganic hybrid material including the steps of maintaining a solid organic-inorganic hybrid material at a temperature above the melting point but below the decomposition temperature of the organic-inorganic hybrid material for a period of time sufficient to form a uniform...

20060234481 - Structure for and method of fabricating a high-mobility field-effect transistor: A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping...

20060234482 - Semiconductor chip having a soldering layer sequence, and process for soldering a semiconductor chip: A semiconductor chip (1), to which a layer sequence (2) intended for the production of a soldered connection has been applied. The layer sequence (2) comprises a solder layer (15) and an oxidation prevention layer (17), which follows the solder layer (15) as seen from the semiconductor chip (1). A...

20060234483 - Cpp read sensor fabrication using heat resistant photomask: A method is disclosed for fabricating a CPP read head for a magnetic disk drive having an electrical isolation layer. The method includes providing a first shield layer, depositing a sensor stack on the first shield layer, a CMP stop layer is deposited on the sensor stack, and a release...

20060234484 - Method and structure for ion implantation by ion scattering: A scatter-implant process and device is provided where a bi-level doping pattern is achieved in a single doping step. Additionally, devices having different breakdown voltages can be produced in a single implant process. The scatter-implant is fabricated by scattering implant ions off the edge of a mask, thereby reducing the...

20060234485 - Salicide process: A salicide process is provided. A metal layer selected from a group consisting of titanium, cobalt, platinum, palladium and an alloy thereof is formed over a silicon layer. A first thermal process is performed. Next, a second thermal process is performed, wherein the second thermal process includes a first step...

20060234486 - Wafer separation technique for the fabrication of free-standing (al,in,ga)n wafers: A method of fabricating free-standing (Al, In, Ga)N substrates, by in situ separation of thick epitaxially grown nitride films from their foreign substrates. A suitable substrate for (Al, In, Ga)N film growth is selected, and foreign ions are implanted in the substrate to form a comparatively sharp concentration profile. An...

20060234487 - Method of forming semiconductor device having stacked transistors: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are...

20060234488 - Methods of selective deposition of heavily doped epitaxial sige: The invention generally teaches a method for depositing a silicon film or silicon germanium film on a substrate comprising placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600° C. to about 900° C. while maintaining a pressure in...

20060234489 - Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes: Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed...

20060234490 - Increased stand-off height integrated circuit assemblies, systems, and methods: Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by aligning a die with a substrate and interposing solder between corresponding substrate and die bond pads. A lifting force is applied to the...

20060234491 - Bumping process and bump structure: A bumping process comprises forming a passivation layer having a planarized surface covering a pad on a substrate, forming a hole penetrating through the passivation layer to expose a contact surface of the pad, and forming a bump on the contact surface and planarized surface. The planarized surface will provide...

20060234493 - Method of manufacturing a device, device, non-contact type card medium, and electronic equipment: Wirings 2B1 are formed by application of heat treatment after an ink jet system is used to discharge a conductive liquid L onto a provisional substrate 5 having a predetermined repellent property, bonding an insulating layer 4B1 to the wirings 2B1 with an adhesive material 3B1 therebetween, peeling and removing...

20060234492 - Methods of forming polysilicon-comprising plugs and methods of forming flash memory circuitry: This invention includes methods of forming polysilicon-comprising plugs, and methods of forming FLASH memory circuitry. In one implementation, a method of forming a polysilicon-comprising plug, includes providing a substrate comprising an opening formed therein. Polysilicon is formed within the opening to less than fill the opening. The polysilicon within the...

20060234494 - Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same: In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1-C6 alkyl group are introduced onto the insulating...

20060234496 - Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing: A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in...

20060234495 - Method to assay sacrificial light absorbing materials and spin on glass materials for chemical origin of defectivity: Numerous embodiments of a method to assay sacrificial material are disclosed. In one embodiment, a sacrificial material may be analyzed by high performance liquid chromatography. Chemical markers that correlate with material contaminants in the sacrificial material may be identified....

20060234497 - Interconnect structure and method of fabrication of same: A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing...

20060234498 - Method of performing a surface treatment respectively on the via and the trench in a dual damascene process: The present invention provides a method of performing a surface treatment respectively on the via and the trench in a dual damascene process by the plasma having the inclined angle. The residual and/or the metal surface oxide on the bottom of the via are removed in the via and the...

20060234499 - Substrate processing method and substrate processing apparatus: A substrate processing method forms a plated film which is thin and has a high flatness by covering the surface (outermost surface) of a substrate, excluding interior surfaces of recesses such as trenches, with a plating inhibiting material such as an SAM-forming molecular species. The substrate processing method comprises: preparing...

20060234500 - Method of forming capacitor of semiconductor device by successively forming a dielectric layer and a plate electrode in a single processing chamber: A capacitor in a semiconductor device is formed by successively forming a dielectric layer and a plate electrode in a single chamber according to an ALD process. The method includes the steps of forming a storage electrode on a semiconductor substrate; loading the semiconductor substrate into an ALD chamber with...

20060234501 - Semiconductor device and method of manufacturing the same: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicate formation free energy and carbide formation free energy respectively take negative values. The...

20060234502 - Method of forming titanium nitride layers: The present invention is generally directed to a method of forming titanium nitride layers. In one illustrative embodiment, the method includes forming a layer of titanium nitride by performing a deposition process, performing an anneal process on the layer of titanium nitride in a chlorine scavenging ambient to define an...

20060234503 - Substrate processing apparatus, substrate processing method, and substrate holding apparatus: The present invention relates to a substrate processing apparatus and a substrate processing method for performing a chemical liquid process, a cleaning process, a drying process, or the like while rotating a substrate such as a semiconductor wafer or a liquid crystal substrate. The present invention also relates to a...

20060234504 - Selective deposition of silicon-containing films: Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in...

20060234505 - Method for manufacturing nano-array electrode and photoelectric conversion device using same: The present invention provides a method of manufacturing a nano-array electrode with a controlled nano-structure by filling an electrode material into the fine pores of an anodic-oxide porous alumina film obtained by anodically oxidizing aluminum in electrolyte, or by filling a material into the fine pores of an anodic-oxide porous...

20060234506 - Processing method for protection of backside of a wafer: A temporal protecting layer is employed to a wafer backside for use of micro-electro-mechanical systems (MEMS). The formation of the temporal protecting layer prevents the wafer backside from scratch in process of transferring system for IC manufacturers. In concerning with low cost and easily forming and removing, an oxide layer...

20060234507 - Treatment of semiconductor wafers: A method is described for treating a wafer having at least a surface layer of semiconductor material, with the surface of this surface layer having undergone a chemical-mechanical polishing step followed by an RCA cleaning step. After the polishing step and prior to the RCA cleaning step, the method includes...

20060234508 - Substrate processing apparatus and substrate processing method: There is provided a substrate processing apparatus which can process a substrate by using an electrolytic processing method, while reducing a load upon a CMP processing to the least possible extent. The substrate processing apparatus of the present invention includes: an electrolytic processing unit (36) for electrolytically removing the surface...

20060234509 - Cerium oxide abrasives for chemical mechanical polishing: The use of mixed cerium-containing synthetic solid abrasive materials in chemical mechanical polishing slurries can provide better selectivity, better substrate removal rates, or lower defect rates than conventional ceria slurries. The slurries have abrasive particles that include a plurality of solid cerium-containing phases selected from CeO2, Ce2O3, cerium-nitride material, cerium-fluoride...

20060234510 - Semiconductor memory device and method for manufacturing semiconductor memory device: According to an aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device is provided with an insulator and a capacitor. The capacitor is provided with a lower electrode provided with an inner portion and an outer portion, a dielectric portion on the lower...

20060234511 - Method for forming a semiconductor device including a plasma ashing treatment for removal of photoresist: A method for forming a cylindrical capacitor having a metal-nitride bottom electrode, capacitor insulation film and a top electrode in a DRAM device includes the step of forming a photoresist film on the bottom electrode in a cylindrical hole, removing the photoresist film by using a plasma ashing treatment using...

20060234512 - Plasma processing apparatus and plasma processing method: A plasma processing apparatus and method preferably used when processing a wafer by means of plasma etching, able to prevent contamination of a wafer or a chamber. The plasma processing apparatus converts a process gas into plasma, sprays the process gas from a spray nozzle 24a to a wafer 2...

20060234513 - Method for manufacturing semiconductor device and semiconductor device: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered...

20060234515 - Film forming method: A film forming method for forming an oxide film on a surface of a substrate to be processed in a processing vessel at a predetermined processing temperature, wherein the method includes a temperature elevating step of elevating a temperature of said substrate to a predetermined processing temperature, the step of...

20060234514 - Gas distribution showerhead featuring exhaust apertures: A method of processing a semiconductor workpiece. The method includes flowing a process gas to a semiconductor workpiece through a first plurality of orifices positioned in a gas distribution faceplate. The method also includes removing gas from over the semiconductor workpiece through a chamber exhaust port and a second plurality...

20060234516 - Composition for cleaning semiconductor device and method for cleaning semiconductor device using the same: Provided are compositions for cleaning a semiconductor device that comprises (a) an inorganic acid in an amount ranging from 10 to 90 wt %, (b) a hydrofluoric acid compound in an amount ranging from 0.0001-1 wt %, (c) an additive in an amount ranging from 0-5 wt %, and (d)...

20060234517 - Method of forming material using atomic layer deposition and method of forming capacitor of semiconductor device using the same: Disclosed are methods of forming dielectric materials using atomic layer deposition (ALD) and methods of forming dielectric layers from such materials on a semiconductor device. The ALD process utilizes a first reactant containing at least one alkoxide group that is chemisorbed onto a surface of a substrate and then reacted...

20060234518 - Chemical vapor deposition method preventing particles forming in chamber: Preventing a chemical vapor deposition (CVD) chamber from particle contamination in which a higher low-frequency radio frequency (LFRF) power and longer process time are provided to vacate the chamber and perform a pre-heat process. Following that, a pre-oxide layer is formed on the chamber wall, while a high-frequency radio frequency...

20060234519 - Contact doping and annealing systems and processes for nanowire thin films: Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing...

20060228815 - Inductively coupled plasma chamber attachable to a processing chamber for analysis of process gases: Disclosed herein are exemplary embodiments of an improved Inductively Coupled Plasma (ICP) chamber which is externally coupleable to a processing chamber to monitor processes gases therefrom. The disclosed ICP chamber design is beneficial because it allows for the porting of reference gases for the purpose of performing actinometry, and/or allows...

20060228816 - System and method for overlay measurement in semiconductor manufacturing: A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the location of the...

20060228817 - Dispensable capacitor manufacturing process: A dispensable capacitor manufacturing process allowing easier process, capacity correction facilitating, and reduced production cost essentially involves dispensing conductive epoxy between two soldering points on a PCB, use of laser to cut on the surface of solidified epoxy spaced grooves in different forms, heated dielectric material then permeated, insulation layer...

20060228818 - Edge temperature compensation in thermal processing particularly useful for soi wafers: A retuning process particularly useful with an Ar/H2 smoothing anneal by rapid thermal processing (RTP) of a silicon-on-insulator (SOI) wafer performed after cleavage. The smoothing anneal or other process is optimized including a radial temperature profile accounting for the edge ring and exclusion zone and the vertically structured SOI stack...

20060228819 - Method of making nitride-based compound semiconductor crystal and substrate: A method of making a nitride-based compound semiconductor crystal has the step of growing a nitride-based compound semiconductor crystal with a predetermined thickness by using a nitride-based compound semiconductor substrate as a seed crystal. The nitride-based compound semiconductor substrate as the seed crystal is polished at both surfaces thereof....

20060228820 - Multifunctional metallic bonding: Methods are provided for producing a transfer layer of a semiconductor material on a final substrate. In some embodiments, the transfer layer is produced on the final substrate by forming a layer of semiconductor material on an initial support, assembling that layer and a final substrate by metal bonding, and...

20060228821 - Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to...

20060228822 - Display device and electronic device using the same: A display device having a first light-emitting element, a second light-emitting element, a constant current source, and an amplifier is provided. Each of the first light-emitting element and the second light-emitting element has a first layer including an organic compound and an inorganic compound and a second layer including a...

20060228824 - Anodic bonding apparatus, anodic bonding method, and method of producing acceleration sensor: An anodic bonding apparatus includes a first electrode and a second electrode. The first electrode has a first surface, and the second electrode has a second surface facing the first surface. The first surface includes a first central area; a first substrate placing area for placing a laminated substrate; and...

20060228823 - Mems structure with anodically bonded silicon-on-insulator substrate: A silicon-on-insulator (SOI) substrate is anodically bonded to a glass substrate in a MEMS structure with or without electrically bypassing the insulator layer by electrically comprising the silicon layers. The insulator layer serves as an etch stop to create a well-defined, thin silicon membrane for a sensor. A second glass...

20060228825 - Method and system for fabricating semiconductor components with through wire interconnects: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on...

20060228826 - Method for fabricating image sensor using wafer back grinding: Provided is a method for fabricating an image sensor using a wafer back grinding process. The method includes: forming a microlens protection layer over a substrate structure including a light sensing device and other associated devices; opening a pad open unit of the substrate structure using a mask; removing the...

20060228827 - Method of fabricating organic light emitting device: Methods of fabricating an organic light emitting device using plasma and/or thermal decomposition are provided. An insulating layer is formed by reacting first and second radicals. The first radical is formed by passing a first gas through a plasma generating region and a heating body, and the second radical is...

20060228828 - Versatile system for selective organic structure production: The present invention provides a system for selectively forming an organic structure in a microelectromechanical device (100). According to the present invention, an encoder material is disposed along a surface (102) or substrate, to define a desired organic microstructure (104, 106). The encoder material may then be subjected to one...

20060228829 - Method for fabricating a flip chip package: A flip chip packaging method is disclosed. First, a substrate is provided, in which the substrate comprises a plurality of integrated circuit (IC) package substrate units therein and the surface of each IC package substrate unit comprises a plurality of connecting pads. Next, an insulating layer with patterns is formed...

20060228830 - Chip-embedded support-frame board wrapped by folded flexible circuit for multiplying packing density: The present invention includes a chip-embedded support-frame wrapped-by-flex-circuit package assembly. The package assembly includes a flex circuit having a plurality of patterned connecting-traces. The package assembly further includes a plurality of semiconductor chips mounted on the flex circuits wherein the semiconductor chips having a plurality of contact terminals connected to...

20060228831 - Method and system of releasing a mems structure: A method and system for releasing MEMS cover-structure on a wafer is disclosed. It includes at least one MEMS wafer structure made up of two wafers, one protective cover, and one containing at least one MEMS feature that are bonded together by various standard wafer bonding means. Also, one wafer...

20060228832 - Leadframe semiconductor package stand and method for making the same: A method is disclosed for making a leadframe package stand having application in semiconductor packaging and microelectronic assembly in which an IC device (e.g., a bare chip IC, a wafer level package, or a chipscale package) is received for electrical connection to a PWB or for vertical package over package...

20060228833 - Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein: A lead frame comprises a stage for mounting a semiconductor chip thereon, a plurality of leads arranged in the periphery of the stage, and a plurality of lead interconnection members (e.g., dam bars) for interconnecting the leads, wherein a plurality of through holes are formed to penetrate through the lead...

20060228834 - Fabrication method of image scan module: A method of fabricating a CCDM scan module applied for image scan. A circuit board on which electronic devices are mounted is provided. A photo-detector and an integrated circuit device which is either packaged or unpackaged are also mounted on the circuit board to form an image sensor board. The...

20060228837 - Apparatus and method for laser radiation: There is provided an improvement on homogeneity of annealing performed utilizing radiation of a laser beam on a silicon film having a large area. In a configuration wherein a linear laser beam is applied to a surface to be irradiated, optimization is carried out on the width and number of...

20060228838 - Display device and manufacturing method thereof: Conventionally, photolithography and anisotropic etching are performed to form a plug between an electrode and a wiring, etc., thereby increasing the number of steps, getting the throughput worse, and producing unnecessary materials. To solve the problems, the present invention provides a method for manufacturing a display device, including the formation...

20060228836 - Method and structure for forming strained devices: A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is deposited over portions of the second layer based on the mapping step. The exposed area of the...

20060228835 - Method of doping a gate electrode of a field effect transistor: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface ; forming an island on the top surface of the substrate, a top surface of the island parallel to the...

20060228839 - Methods for fabricating array substrates: Methods for fabricating array substrates are provided. A method for fabricating an array substrate includes forming a first metal layer over a substrate and then patterned by a first photolithography to forming a gate line, a gate electrode connecting the gate line, and a pad over the substrate. An insulating...

20060228841 - Methods of forming a thin-film structure, methods of manufacturing non-volatile semiconductor devices using the same, and resulting non-volatile semiconductor devices: In a method of forming a thin-film structure employed in a non-volatile semiconductor device, an oxide film is formed on a substrate. An upper nitride film is formed on the oxide film by nitrifying an upper portion of the oxide film through a plasma nitration process. A lower nitride film...

20060228840 - Tri-gate devices and methods of fabrication: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode...

20060228842 - Transistor fabrication using double etch/refill process: A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers...

20060228844 - Integration scheme for fully silicided gate: To form a semiconductor device, a silicon (e.g., polysilicon) gate layer is formed over a gate dielectric and a sacrificial layer (preferably titanium nitride) is formed over the silicon gate layer. The silicon gate layer and the sacrificial layer are patterned to form a gate structure. A spacer, such as...

20060228845 - Method for pre-retaining cb opening: Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The LPD oxidation layer and the photo-resist are...

20060228843 - Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel: A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to...

20060228846 - Process for producing soi substrate and process for regeneration of layer transferred wafer in the production: A process for producing an SOI substrate includes the steps of forming an oxide film on at least the front surface of a first silicon substrate, implanting hydrogen ion from the surface of the first silicon substrate and thereby forming an ion implantation area in the inside of the first...

20060228848 - Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals: Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer is protected from photoresist stripping chemicals by using a hard mask as a pattern during etching, rather than using a photoresist. The hard mask prevents exposure of a silicide layer to photoresist stripping chemicals...

20060228849 - Method of forming source/drain region of semiconductor device: A method of forming a source/drain region of a semiconductor device includes forming a photoresist pattern through which an NMOS region of a semiconductor substrate is exposed, and then performing an ion implant process to form NMOS LDD regions in the semiconductor substrate of the NMOS region. An ion implant...

20060228847 - Method of manufacturing mos transistors: First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality...

20060228850 - Pattern loading effect reduction for selective epitaxial growth: A method of reducing the pattern-loading effect for selective epitaxial growth. The method includes the steps of: forming a mask layer over a substrate; forming an isolation region in the substrate isolating an active region and a dummy active region; removing at least a portion of the mask layer in...

20060228851 - Method of making a dual strained channel semiconductor device: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in...

20060228853 - Memory devices including spacers on sidewalls of memory storage elements and related methods: A method of forming a memory device may include forming an insulating layer on a substrate, and forming a first electrode through at least a portion of the insulating layer. A memory storage element may be formed on the first electrode so that the first electrode is between the memory...

20060228852 - Method of forming contact plugs: A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on...

20060228854 - Methods for increasing photo alignment margins: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in...

20060228855 - Capacitor with co-planar electrodes: Methods and structures related to film capacitors are disclosed. The capacitors include electrodes in a side-by-side or laterally offset configuration instead of a usual stacked configuration. The side-by-side configuration allows the interposing of the dielectric layer between the capacitor electrodes to be formed without as stringent a fabrication environment as...

20060228856 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and...

20060228857 - Dram cells: The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over...

20060228859 - Contact scheme for memory array and manufacturing methods thereof: A method of making a memory device and a memory device is described. In one embodiment, a method of manufacturing a memory device is described. The method includes providing a substrate having a tunneling layer deposited on a main surface and having a first conductive lines arranged on the tunneling...

20060228858 - Flash memory cell having reduced floating gate to floating gate coupling: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric...

20060228860 - Semiconductor device and a method of manufacturing the same: Manufacturing method of a semiconductor device for forming a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, including forming a gate insulating film over a semiconductor substrate, a gate...

20060228861 - Partially recessed dram cell structure and method of making the same: A dynamic random access memory (DRAM) cell structure (and method for making a DRAM cell structure) that is more suitable than current DRAM structures for implementation in ever decreasing semiconductor fabrication geometries. The DRAM cell structure comprises a deep trench (DT) capacitor formed in a substrate. A recess is formed...

20060228862 - Fet design with long gate and dense pitch: A complementary metal oxide semiconductor field effect transistor (CMOS FET) design layout and method of fabrication are disclosed that provide a long gate and dense pitch in which gate contacts are positioned directly on top of the gates, and source and drain contacts are made into contact CA bars with...

20060228863 - Method for making a semiconductor device with strain enhancement: A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode...

20060228864 - Semiconductor devices having a bottle-shaped deep trench capacitor and methods for making the same using epi-si growth process: A semiconductor device having a transistor and a storage capacitor. The transistor includes source and drain regions formed on a substrate. The storage capacitor is coupled to the transistor. The storage capacitor is formed from a bottle-shaped trench and having an Epi-Si layer grown inside the trench to form at...

20060228865 - System and method for photolithography in semiconductor manufacturing: A method for photolithography in semiconductor device manufacturing comprises defining test critical dimension target for a photolithography mask, measuring a mask critical dimension, comparing mask critical dimension to the test critical dimension target and determining a critical dimension deviation, determining a photolithography light base energy in response to the critical...

20060228867 - Isolation region formation that controllably induces stress in active regions: A method (10) of forming an isolation structure (140, 142) in a semiconductor substrate (102) is disclosed, wherein the isolation structure (140, 142) can be formed in a controlled manner so as to regulate stresses exerted by the structure on one or more active regions (106) of the substrate (102)...

20060228866 - Methods of filling openings with oxide, and methods of forming trenched isolation regions: The invention includes methods in which oxide is formed within openings in a three-step process. A first step is deposition of oxide under a pressure of greater than 15 mTorr. A second step is removal of a portion of the oxide with an etch. A third step is an oxide...

20060228868 - Ald of amorphous lanthanide doped tiox films: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOx) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium...

20060228869 - Mems packaging structure and methods: A MEMS article is made by forming a MEMS device on a first substrate, providing a second substrate, depositing a layer of etchable dielectric material, forming at least one lateral post-bond release-etch port by a damascene process using a sacrificial material, and bonding the two substrates together....

20060228870 - Method of making group iii-v nitride-based semiconductor crystal: A method of making a group III-V nitride-based semiconductor crystal has: a first step of providing a first semiconductor crystal substrate; a second step of growing a first group III-V nitride-based semiconductor crystal on the first semiconductor crystal substrate in a first crystal axis direction until when reaching a first...

20060228871 - Method and system for forming an oxynitride layer by performing oxidation and nitridation concurrently: A method for preparing an oxynitride film on a substrate comprising forming the oxynitride film by exposing a surface of the substrate to oxygen radicals and nitrogen radicals formed by plasma induced dissociation of a process gas comprising nitrogen and oxygen using plasma based on microwave irradiation via a plane...

20060228872 - Method of making a semiconductor device having an arched structure strained semiconductor layer: A method of forming a semiconductor device includes forming a local strain-inducing structure of a first semiconductor material at a point location within a dielectric layer. The local strain-inducing structure has a prescribed geometry with a surface disposed above a surface of the dielectric layer. A second semiconductor material is...

20060228873 - Electrostatic nanolithography probe actuation device and method: Method and apparatus for selectively actuating a cantilevered probe for applying a compound to a substrate in nanolithography. A probe having a probe electrode and a substrate having a counter electrode are provided. Voltage applied to the probe electrode and/or counter electrode provides electrostatic attraction between them, moving a probe...

20060228874 - Method of inhibiting copper corrosion during supercritical co2 cleaning: A method for the pre-treatment of a wafer substrates with exposed metal surfaces is disclosed. The pre-treatment reduces oxidation of the exposed metal surfaces during subsequent supercritical cleaning processes....

20060228875 - Transistor with shallow germanium implantation region in channel: A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and...

20060228876 - Method of manufacturing a semiconductor device: The invention relates to a method of manufacturing a semiconductor device, in which a substrate is provided, a dielectric layer is formed on top of the substrate, an amorphous semiconductor layer id deposited on top of the dielectric layer, the amorphous semiconductor layer is doped, and a high temperature step...

20060228877 - Patterned material layer, method of forming the same, microdevice, and method of manufacturing the same: A method of forming a patterned material layer, the method comprising: a resist layer forming step of forming a resist layer on a substrate, the resist layer including a first photosensitive resin layer, an intermediate resin layer, and a second photosensitive resin layer; an exposing step; a developing step of...

20060228878 - Semiconductor package repair method: A lower-melting-point solder having a lower melting point than solder balls is used to bond the solder balls with a module substrate. The lower-melting-point solder has a melting point lower than the solder balls. A bonding temperature is at a temperature between the melting point of the lower-melting-point solder and...

20060228879 - Thin film resistor head structure and method for reducing head resistivity variance: A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectric layer, and forming a second dielectric layer (18D) over...

20060228880 - Semiconductor structures, and methods of forming semiconductor constructions: The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines...

20060228881 - Structure and method for minimizing substrate effect on nucleation during sputtering of thin film resistors: A method of improving nucleation during depositing of a film (2) on a surface (18-3) of a wafer, including performing a planarizing operation on the surface (18-3), the planarizing operation resulting in generation of dangling chemical bonding sites on the surface, depositing a dielectric layer (18D) on the planarized surface...

20060228882 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal process to form junction regions between the trenches in the substrate by...

20060228883 - Phase change memory cell defined by a pattern shrink material process: One embodiment of the present invention provides a memory cell device. The memory cell device includes a first electrode, a phase-change material adjacent the first electrode, and a second electrode adjacent the phase-change material. The phase-change material has a sublithographic width defined by a pattern shrink material process....

20060228884 - Unidirectionally conductive materials for interconnection: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may...

20060228885 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a gate insulation film on a semiconductor substrate; forming a gate electrode on the gate insulation film; depositing a metal film on the gate electrode; siliciding an upper part of the gate electrode by carrying out a first heat treating; removing...

20060228886 - Deposition-selective etch-deposition process for dielectric film gapfill: A deposition/etching/deposition process is provided for filling a gap in a surface of a substrate. A liner is formed over the substrate so that distinctive reaction products are formed when it is exposed to a chemical etchant. The detection of such reaction products thus indicates that the portion of the...

20060228887 - System and method for depositing a seed layer: A method for depositing a seed layer for a controllable electric pathway on a substrate includes selectively dispensing a seed material from an inkjet material dispenser onto said substrate....

20060228888 - Atomic layer deposition of high k metal silicates: The present invention relates to the atomic layer deposition (“ALD”) of high k dielectric layers of metal silicates, including hafnium silicate. More particularly, the present invention relates to the ALD formation of metal silicates using metal organic precursors, silicon organic precursors and ozone. Preferably, the metal organic precursor is a...

20060228890 - Cleaning solution and method of forming a metal pattern for a semiconductor device using the same: A cleaning solution includes acetic acid, an inorganic acid, a fluoride compound, and deionized water, and may further include a corrosion inhibitor, a chelating agent, or a combination thereof. The cleaning solution may be used in the formation of a metal pattern in which a metal film including ruthenium is...

20060228891 - Method of exposing a substrate to a surface microwave plasma, etching method, deposition method, surface microwave plasma generating apparatus, semiconductor substrate etching apparatus, semiconductor substrate deposition apparatus, and microwave plasma g: In certain implementations, methods and apparatus include an antenna assembly having at least two overlapping and movable surface microwave plasma antennas. The antennas have respective pluralities of microwave transmissive openings formed therethrough. At least some of the openings of the respective antennas overlap with at least some of the openings...

20060228889 - Methods of removing resist from substrates in resist stripping chambers: Methods for stripping resist from a semiconductor substrate in a resist stripping chamber are provided. The methods include producing a remote plasma containing reactive species and cooling the reactive species inside the chamber prior to removing the resist with the reactive species. The reactive species can be cooled by being...

20060228892 - Anti-reflective surface: A discontinuous layer is formed on a transparent substrate of a semiconductor material. Portions of the transparent substrate are exposed at discontinuities in the discontinuous layer. The discontinuous layer and the exposed portions of the transparent substrate are etched at least until the discontinuous layer is completely removed, thereby forming...

20060228893 - Semiconductor substrates and field effect transistor constructions: The invention includes methods of forming field effect transistor gates. In one implementation, a series of layers is formed proximate a semiconductive material channel region. The layers comprise a gate dielectric layer and a conductive metal-comprising layer having an ion implanted polysilicon layer received therebetween. Patterned masking material is formed...

20060228894 - Method for semiconductor manufacturing using a negative photoresist with thermal flow properties: Provided is a method for manufacturing a semiconductor device. In one example, the method includes forming a negative photoresist layer over an underlying layer, where the negative photoresist layer is soluble by a developer when formed. The negative photoresist layer is patterned using a chromium-less mask. The patterning alters at...

20060228895 - Method of forming fine pitch photoresist patterns using double patterning technique: A method of forming a photoresist pattern comprises providing a semiconductor substrate on which a layer to be etched is formed. The method further comprises forming a first photoresist pattern on the layer to be etched, processing the first photoresist pattern with hydrogen bromide (HBr) plasma, and forming a second...

20060228896 - Fabricating integrated devices using embedded masks: A method of fabricating a device using a multi-layered wafer that has an embedded etch mask adapted to map a desired device structure onto an adjacent (poly)silicon layer. Due to the presence of the embedded mask, it becomes possible to delay the etching that forms the mapped structure in the...

20060228897 - Rapid thermal processing using energy transfer layers: A method that is performed for heat treating a semiconductor wafer in a process chamber, as an intermediate part of an overall multi-step technique for processing the wafer, includes applying an energy transfer layer to at least a portion of the wafer, and exposing the wafer to an energy source...

20060228898 - Method and system for forming a high-k dielectric layer: A method for preparing an interfacial layer for a high-k dielectric layer on a substrate. A surface of said substrate is exposed to oxygen radicals formed by ultraviolet (UV) radiation induced dissociation of a first process gas comprising at least one molecular composition comprising oxygen to form an oxide film....

20060228899 - Semiconductor memory device and method for manufacturing semiconductor device: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film....

20060228900 - Method and system for removing an oxide from a substrate: A method and system for processing a substrate includes providing the substrate in a process chamber, where the substrate contains an oxide layer formed thereon, exciting a hydrogen-containing gas in a remote plasma source coupled to the process chamber, and exposing the substrate to a flow of the excited hydrogen-containing...

20060228901 - Growth method for nitride semiconductor epitaxial layers: The present invention relates to a method for growing a nitride semiconductor epitaxial layer, which comprises the steps of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial...

20060228902 - Method and system for forming an oxynitride layer: The present invention generally provides a method for preparing an oxynitride film on a substrate. A surface of the substrate is exposed to oxygen radicals formed by ultraviolet (UV) radiation induced dissociation of a first process gas comprising at least one molecular composition comprising oxygen to form an oxide film...

20060228905 - Method for conditioning a microelectronics device deposition chamber: The present invention provides, in one aspect, the present invention provides, in one embodiment, a method of conditioning a deposition chamber 100. This method comprises placing an undercoat on the walls of a deposition chamber 100 and depositing a pre-deposition coat over the undercoat with a plasma gas mixture conducted...

20060228903 - Precursors for the deposition of carbon-doped silicon nitride or silicon oxynitride films: A process for fabricating carbon doped silicon nitride layers is described. By adjusting the amount of carbon in adjacent regions, selective etching of the silicon nitride regions can occur. Several precursors for the introduction of carbon into the silicon nitride film, are described....

20060228904 - Protection of silicon from phosphoric acid using thick chemical oxide: A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method...

20060228906 - Method of patterning conductive polymer layer, organic light emitting device, and method of manufacturing the organic light emitting device: A method of patterning a conductive polymer, an organic light emitting device (OLED) manufactured using the method of patterning a conductive polymer, and a method of manufacturing the OLED are provided. The method of patterning a conductive polymer includes forming a conductive polymer layer on a substrate, aligning a shadow...

20060228907 - Method of forming a gate dielectric layer: A method of forming a gate dielectric is described. A plasma treatment process is performed to form a dielectric structure on a substrate, wherein the dielectric structure having a graded dielectric constant value that decreases gradually in a direction toward the substrate....

20060228908 - Method of manufacturing polysilicon thin film and method of manufacturing thin film transistor having the same: In a method of manufacturing a polysilicon thin film and a method of manufacturing a TFT having the thin film, a laser beam is irradiated on a portion of an amorphous silicon thin film to liquefy the portion of the amorphous silicon thin film. The amorphous silicon thin film is...

20060223198 - Semiconductor device and fabricating method of the same: An Al2O3 film with a thickness greater than that of a wiring is formed as a protective film, and then the Al2O3 film is polished by CMP until a conductive barrier film is exposed. Namely, CMP is applied to the Al2O3 film by utilizing the conductive barrier film as a...

20060223199 - Semiconductor device and manufacturing method thereof: By simultaneously forming via holes 35 for forming through electrodes 27 and 28 to be provided in second regions 13 and 14 and isolation trenches 30 for separating a first region 12 from the second regions 13 and 14, positioning of the via holes 35 and the isolation trenches 30...

20060223200 - Semiconductor manufacture method: A semiconductor device manufacture method has the steps of: (a) forming a semiconductor device structure in a chip and alignment marks, respectively in a semiconductor wafer; (b) forming a workpiece layer above the semiconductor wafer; (c) exposing the alignment marks; (d) coating an electron beam resist film on the workpiece...

20060223201 - Body bias compensation for aged transistors: Embodiments of the invention include on-chip transistor degradation detection and compensation. In one embodiment of the invention, an integrated circuit is provided including a circuit with a body bias terminal coupled to a body of one or more transistors to receive a body bias voltage; a programmable degradation monitor to...

20060223203 - Advanced process control model incorporating a target offset term: An advanced process control (APC) architecture comprising a process model that incorporates a target offset term is provided. The APC architecture may be applied to a so-called develop inspect critical dimension (DICD) model using the target offset term to correct at least one exposure parameter on the occurrence of an...

20060223202 - Offline screening of outgas emissions in semiconductor processing: The present description relates to measuring outgas emissions in fabrication chambers used for semiconductors, micromachines and the like. In one embodiment, the invention includes inserting a gas adsorption material into a processing chamber exhaust vent, running a process in the chamber, venting gasses in the chamber through the gas adsorption...

20060223204 - System and method for detecting flow in a mass flow controller: Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention,...

20060223206 - Array substrate for liquid crystal display device and manufacturing method thereof: An array substrate for a liquid crystal display device and manufacturing method thereof is disclosed in the present invention. The liquid crystal display having an array substrate includes a substrate, a gate line and a data line on the substrate, the gate line and the data line crossing each other...

20060223205 - Fluidic heterogeneous microsystems assembly and packaging: Self-assembly of components carried in a fluid is provided. A first component and a second component are obtained and self-assembled together. A third component is obtained and assembled with the first and second components, following the step of assembling the first and second components. The first, second and third components...

20060223207 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the...

20060223208 - Optical device: The disclosure relates to a method of forming an optical device including the steps of (i) providing a substrate carrying a first electrode capable of injecting or accepting charge carriers of a first type; (ii) depositing a polyfluorene over the first electrode; and (iii) forming over the polyfluorene a second...

20060223209 - Surface-emission semiconductor laser device: A method for fabricating a surface-emission semiconductor laser on a p-type substrate includes the step of interposing an Au film between an AuGeNi film or AuGe film of an n-side electrode and a compound semiconductor layer of an n-type DBR, followed by annealing to form an Au alloy in the...

20060223210 - Method of manufacturing a thin film transistor array panel: A method for manufacturing a flexible display, includes forming a gate line including a plurality of gate electrodes with a first interval on a substrate having a coefficient of thermal expansion, sequentially depositing both a gate insulating layer covering the gate line and a semiconductor layer, etching the semiconductor layer...

20060223211 - Semiconductor devices based on coalesced nano-rod arrays: Semiconductor devices are fabricated using semiconductor nano-rod arrays, which are merged through coalescence into a continuous planar layer after the nano-rods in the nano-rod array are fabricated by growth or etching. Merging of the nano-rods through coalescence into a continuous layer is achieved by tuning the growth conditions into a...

20060223212 - Image sensor and method for manufacturing the same: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed...

20060223213 - Image sensor having a charge storage region provided within an implant region: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and...

20060223214 - Optoelectronic component for converting electromagnetic radiation into a intensity-dependent photocurrent: Optoelectronic component for converting electromagnetic radiation into an intensity-dependent photocurrent comprising a substrate formed in CMOS technology, in particular, with an integrated semiconductor structure (ASIC) and an optically active thin-film structure arranged upstream in the direction of light incidence and comprising in each case at least one layer made of...

20060223215 - Method for making a microelectromechanical systems (mems) device including a superlattice: A method for making a microelectromechanical system (MEMS) device may include providing a substrate, and forming at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the...

20060223216 - Sensor module structure and method for fabricating the same: A sensor module structure and a method for fabricating the same are proposed. A chip carrier module plate including a plurality of chip carriers is provided, each chip carrier having a first surface and a second surface. At least one semiconductor chip is mounted on and electrically connected to the...

20060223217 - Photodiode: The invention provides a method of manufacturing an avalanche diode comprising the steps of applying a mask (6) over an active diode region (5) in a wafer (1), and damaging the region the surrounding the active diode region by breaking bonds in the semiconductor lattice to provide gettering sites in...

20060223218 - Field effect transistor arrangement and method of manufacturing a field effect transistor arrangement: Provided is a method of manufacturing a field effect transistor with an organic semiconductor, and particularly a device comprising a plurality of field effect transistors with an interconnect structure. Herein, use is made of three photolithographical masks for four layers. Thereto, the transistor is provided in a top-gate structure, and...

20060223219 - Method of depositing polythiophene semiconductor on a substrate: Provided is a method of depositing a polythiophene semiconductor on a substrate. First, the semiconductor is dissolved in a solvent comprising a halogen-containing aromatic compound. Then, the resulting solution is ink-jet printed onto the substrate. The method is useful in the production of microelectronic components such as thin film transistor...

20060223221 - Method of manufacturing organic electroluminescent device and method of manufacturing device: A method of manufacturing an organic electroluminescent device includes forming partition walls partitioning pixels on a substrate; subjecting a surface of each of the partition walls to a lyophobic treatment; coating a liquid composition on each of regions surrounded by the partition walls, the liquid composition obtained by dissolving and...

20060223220 - Methods and structures to form precisely aligned stacks of 3-dimensional stacks with high resolution vertical interconnect: Methods and structures to form precisely aligned stacks of 3-dimensional stacks with high resolution vertical interconnections, and associated stacks, structures and devices. Viewing ports are formed in a first nanostructure layer through which an alignment pattern on-a second nanostructure layer is visible when the first and second nanostructure layers are...

20060223222 - Organic thin film transistor array panel and method of manufacturing the same: An organic thin film transistor array panel comprises a substrate, a data line formed on the substrate, a gate line intersecting the data line on the substrate, said gate line comprising a gate electrode, a gate insulating layer formed on the gate line, said gate insulating layer including a contact...

20060223223 - Method of production of circuit board utilizing electroplating: A method of production of a circuit board utilizing electroplating which prevents signal reflection and noise due to unnecessary parts in the circuit patterns when electroplating to form circuit patterns on the board to thereby improve the electrical properties and realize higher density layout of the circuit patterns, including the...

20060223229 - Ball grid array package and process for manufacturing same: A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a first surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a...

20060223228 - Ceramic substrate and method of breaking same: A ceramic substrate (100) includes a top surface, a plurality of identification marks (104), a protective compound (110), a bottom surface, and a plurality of grooves (106). The top surface includes a first area and a second area. The first area is defined at one or more edges portions of...

20060223225 - Method, system, and apparatus for transfer of integrated circuit dies using an attractive force: A method, system, and apparatus for transferring integrated circuit dies is described. A die receptacle structure has a first surface. The first surface has a plurality of cells formed therein. Each cell is configured to contain an integrated circuit die. A bottom surface of each cell is configured to attract...

20060223227 - Molding method for foldover package: A method of making a microelectronic assembly including the steps of depositing one or more microelectronic elements onto a flexible substrate and folding the substrate so that a first region of the substrate forms a first run and a second region of the substrate forms a second run overlaying the...

20060223226 - Organic substrates with integral thin-film capacitors, methods of making same, and systems containing same: An organic substrate, thin-film capacitor composite includes two plates that are accessed through deep and shallow vias. The organic substrate, thin-film capacitor composite includes integral structure with at least one trace in the organic substrate. The composite is able to be coupled with an interposer. The composite is also part...

20060223230 - Semiconductor package substrate having contact pad protective layer formed thereon and method for fabricating the same: A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on...

20060223224 - Substrate for reticle and method of manufacturing the substrate, and mask blank and method of manufacturing the mask blank: In a reticle substrate is used for forming a reticle held on a stepper and has main surfaces opposing each other, side faces, and chamfered surfaces formed between main surfaces and side faces, a flatness-measuring area is defined as an area excluding a peripheral area of a width of 3...

20060223231 - Packing method for electronic components: A packaging method which makes possible firm connection of electronic components having bump areas and a wiring board having a pad electrode portion with secure electrical conduction is to be provided. To achieve this object, according to the packaging method which makes possible firm connection of electronic components having bump...

20060223233 - Apparatus and method for heating substrates: An apparatus for processing substrates is disclosed. In one embodiment, the apparatus includes a housing and a plurality of stacked cell structures in the housing. An actuator is adapted to move the plurality of stacked cell structures inside of the housing while substrates in the stacked cell structures are being...

20060223232 - Method for forming laminated structure and method for manufacturing semiconductor device using the method thereof: A method for manufacturing a semiconductor device includes the steps of (a) preparing a wafer including a first circuit formation region and a first surrounding region, (b) laminating a first chip on the first circuit formation region, (c) pouring a first underfill into a first space between the first circuit...

20060223234 - Semiconductor-device manufacturing method: In a manufacturing method of a semiconductor device, a semiconductor substrate having a plurality of semiconductor chips formed on one of principal surfaces of the substrate is cut into the plurality of semiconductor chips through dicing. A first cutting process is formed on one of the principal surfaces of the...

20060223235 - Resin-sealing semiconductor package and method and device for manufacturing the same: The present invention is characterized in that a powdery or granular resin composition stirred and melted in an agitating pot having a heater, the agitated and melted resin composition is taken out and formed in the form of a package under pressure, and the formed resin composition is fitted to...

20060223236 - Method of manufacturing flexible circuit substrate: Connection pads and alignment marks are formed on a long metal thin plate that is carried in a longitudinal direction, and then an insulating layer for covering the connection pads is formed. Then, via holes, which are aligned and arranged on the connection pads by utilizing the alignment marks, are...

20060223237 - Method of manufacturing enhanced thermal dissipation integrated circuit package: The present invention relates to an integrated circuit package having a thermally conductive element thermally coupled to a semiconductor die and a heat sink, and a method of manufacturing said integrated circuit package. The thermally conductive element is integrated into the package to enhance thermal dissipation characteristics of the package....

20060223238 - Leadless semiconductor package and manufacturing method thereof: A leadless semiconductor package mainly includes a semiconductor device securely attached to an upper surface of a die pad by solder paste and a plurality of leads arranged about the periphery of the die pad. The thickness of the leads and the die pad are within a range of 10...

20060223239 - Integrated circuit edge protection method and apparatus: An apparatus, method, and system for providing a mechanical divider adapted to shield at least a portion of an active surface of an integrated circuit from out-gassing from underfill material. The mechanical divider is attached to a mounting substrate. The underfill material is dispensed on the mounting substrate. The integrated...

20060223240 - Method of making substrate for integrated circuit: A method of making an IC substrate includes the steps of: a) preparing a substrate having a front side and a back side and half-etching the substrate to form a filling space in the front side of the substrate subject to a predetermined depth and area, b) putting the substrate...

20060223241 - Electronic device fabrication: A system performs a method including contact printing one of a wetting agent and a non-wetting agent on a semiconductor and inkjet printing an electrically conductive material proximate said one of the wetting agent and the non-wetting agent....

20060223242 - Method of forming a crack stop void in a low-k dielectric layer between adjacent fusees: A crack stop void is formed in a low-k dielectric layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The crack stop void is formed simultaneously with the formation of an interconnect structure....

20060223243 - Carbon nanotube - metal contact with low contact resistance: A metal to Carbon nanotube contact region is described that comprises a chemical bond between the metal and the Carbon nanotube....

20060223244 - Method of manufacturing orientation film and method of manufacturing liquid discharge head: A method of manufacturing an orientation film which method is suitable for manufacturing an orientation film containing a ceramic at low cost. The method includes the steps of: (a) forming a ceramic film on a seed substrate in which crystal orientation is controlled at least on a surface thereof by...

20060223247 - Schottky junction diode devices in cmos: A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that...

20060223246 - Schottky junction diode devices in cmos with multiple wells: A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such...

20060223245 - T-gate formation: Methods of forming T-gate structures on a substrate are provided that use only UV-sensitive photoresists. Such methods provide T-gate structures using two lithographic steps using a single wavelength of radiation....

20060223251 - Field effect transistor and an operation method of the field effect transistor: A field effect transistor includes a silicon substrate, a source electrode and a drain electrode which are formed in upper portions of the silicon substrate, and an insulator film, a PCMO film, and a gate electrode which are formed on part of the silicon substrate sandwiched between the source electrode...

20060223248 - N+ poly on high-k dielectric for semiconductor devices: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped...

20060223253 - Semiconductor device and method of manufacturing the same: Provided is a semiconductor device having a structure in which: a well region of a high resistance p-type semiconductor is disposed in a given depth from a surface of an n-type or p-type semiconductor substrate; a plurality of trenches extend from the surface of the well region to a certain...

20060223249 - Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method: In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. An ohmic contact layer is formed over the diffusion barrier...

20060223252 - Semiconductor device multilayer structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method: In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. After forming the diffusion barrier layer, a heat treatment process...

20060223250 - Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning: By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor...

20060223254 - Display panel drive device: A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate...

20060223255 - Method for selectively stressing mosfets to improve charge carrier mobility: A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress...

20060223256 - Semiconductor memory device and method of manufacturing the same: A method of manufacturing a semiconductor memory device includes the steps of providing a gate insulating film on an active region, depositing a first conductive film on the gate insulating film, processing the first conductive film, the gate insulating film, and the active region to provide an opening of which...

20060223258 - Method of fabricating a semiconductor device having cmos transistors and a bipolar transistor: To reduce electric current concentration and electric field concentration in junction parts even in the case of miniaturization, and to achieve triggering at low voltage, an ESD protection apparatus is installed between an input terminal of a semiconductor integrated circuit chip and a CMOS transistor. The ESD protection apparatus includes...

20060223257 - Method of fabricating isolated semiconductor devices in epi-less substrate: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of...

20060223259 - Method of manufacturing semiconductor device: Disclosed is that in a method of manufacturing a semiconductor device of the present invention, when first and second P type diffusion layers using as a backgate region, these layers are formed in such a way that their impurity concentration peaks are shifted, respectively. Then, in the backgate region, a...

20060223260 - Trench mosfet with sidewall spacer gates: A semiconductor power device includes a semiconductor body with a plurality of gate trenches formed therein. Disposed within each gate trench is a spacer gate that extends along at least a portion of the sidewalls of the gate trench but not along at least a portion of the bottom surface...

20060223261 - Cmos-based low esr capacitor and esd-protection device and method: A method for fabricating a low dynamic resistance capacitor is an integrated circuit using conventional CMOS processing steps, where in one implementation the structure provides the additional feature of a Zener diode capable of offering ESD protection....

20060223263 - Method of forming transistor using step sti profile in memory device: A method of forming a memory device includes forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween; and etching a portion of the semiconductor substrate provided within the active region to define a step profile, so that the...

20060223262 - Vertical memory device and method: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the...

20060223264 - Method of fabricating flash memory device: A method of fabricating a flash memory device includes defining a high voltage region and a low voltage region on a substrate. The high voltage region provides an area for one or more first transistors configured to operation at a first voltage, the low voltage region providing an area for...

20060223265 - Vertical transistor of semiconductor device and method for forming the same: A vertical transistor of a semiconductor device and a method for forming the same are disclosed. The vertical transistor comprises a silicon fin disposed on a semiconductor substrate, a source region disposed in the semiconductor substrate below a lower portion of the silicon fin, a drain region disposed in an...

20060223266 - Method of forming an electronic device: A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during...

20060223267 - Method of production of charge-trapping memory devices: The surfaces of wordline stacks and intermediate areas of a main substrate surface are covered with an oxynitride liner. Either sidewall spacers of BPSG are formed or a further liner of nitride is deposited and spacers of oxide are formed. These spacers are used in a peripheral area of addressing...

20060223268 - Phase-change random access memory and process for producing same: An object of the present invention is to provide a phase-change random access memory which hardly causes the peeling of a phase-change film in a production process. In the present invention, the surface of an insulating film around the phase-change film is positioned to a more substrate side than an...

20060223271 - Method for manufacturing a semiconductor device: Manufacturing a semiconductor device by removing the insulation film in an alignment mark-forming region, depositing a first semiconductor layer, removing the insulation film on the semiconductor substrate after the second semiconductor layer is formed, forming a first exposing region for exposing the semiconductor substrate through the second semiconductor layer and...

20060223269 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having first to fourth active regions and field oxides, the third and fourth active regions sandwiching the second active region, and the field oxides isolating the first to fourth active regions; forming a protective film...

20060223270 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device including a step of forming an insulating film on a semiconductor substrate, a step of removing the insulating film selectively in a first alignment mark forming region and a silicon-on-insulator (SOI) structure forming region that are provided on the semiconductor substrate by patterning...

20060223272 - Semiconductor device and method of manufacturing the same: Each of channel regions 2a and 3b is covered by a gate electrode 6 via a gate insulation film 5 and side wall spacers 9 from its top face to both side faces along an x-direction. In other words, there is no insulation material of an STI element isolation structure...

20060223273 - Surface treatment in preparation for contact placement: A contact is formed on indium-phosphide material. Regions of the indium-phosphide material are exposed. An energetic bombardment is performed on exposed regions of the indium-phosphide material. Metal is deposited on the exposed regions of the indium-phosphide material where energetic bombardment occurred....

20060223274 - Semiconductor device and manufacturing method thereof: In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or...

20060223275 - Structure and method for iii-nitride device isolation: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity...

20060223276 - Mim capacitor structure and fabricating method thereof: A method for fabricating an MIM capacitor is disclosed. First, a substrate is provided having a first dielectric layer thereon. Next at least one first damascene conductor is formed within the first dielectric layer, and a second dielectric layer with a capacitor opening is formed on the first dielectric layer,...

20060223277 - Method of manufacturing a semiconductor memory device: A method of manufacturing a semiconductor device comprises providing a semiconductor substrate, forming trenches in predetermined regions of the semiconductor substrate, forming isolation structures within the trenches that separate active regions and field regions of the device, and etching exposed regions of the semiconductor substrate so that the exposed regions...

20060223278 - Non-critical complementary masking method for poly-1 definition in flash memory device fabrication: A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of...

20060223279 - Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to...

20060223280 - Method for manufacturing semiconductor device and semiconductor device: In the present invention, trenches are formed on a principal surface of a silicon substrate; a first insulating film is formed on an entire surface of the silicon substrate including trenches so as not to bury the trenches; a second insulating film burying the trenches and covering the principal surface...

20060223281 - Manufacturing structure: This utility discloses a manufacturing structure, suitable for at least one component that accomplishes manufacturing structure with high density and high suppleness. This structure comprises a substrate and at least one hole. These holes are arranged to be an array on the substrate. The size of the hole tallies with...

20060223283 - Method for producing a high quality useful layer on a substrate: A method for producing a high quality useful layer of semiconductor material on a substrate. The method includes implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer....

20060223282 - Processes for forming backplanes for electro-optic displays: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second...

20060223284 - Semiconductor wafer coat layers and methods therefor: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps...

20060223285 - Semiconductor wafer treatment method: A semiconductor wafer treatment method for dividing an adhesive tape, which has been stuck to the entire back of a semiconductor wafer, along divided streets of the semiconductor wafer. Before division of the adhesive tape by application of laser beams, the state of the divided streets is detected, and laser...

20060223286 - Atomic layer deposition apparatus: A method and apparatus for atomic layer deposition (ALD) is described. The apparatus comprises a deposition chamber and a wafer support. The deposition chamber is divided into two or more deposition regions that are integrally connected one to another. The wafer support is movable between the two or more interconnected...

20060223288 - Group-iii nitride semiconductor stack, method of manufacturing the same, and group-iii nitride semiconductor device: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III...

20060223287 - Method of forming a low temperature-grown buffer layer, light emitting element, method of making same, and light emitting device: A method of forming a low temperature-grown buffer layer having the steps of: placing a Ga2O3 substrate in a MOCVD apparatus; providing a H2 atmosphere in the MOCVD apparatus and setting a buffer layer growth condition having an atmosphere temperature of 350° C. to 550° C.; and supplying a source...

20060223289 - Method of manufacturing semiconductor device and semiconductor device: A method of manufacturing a semiconductor device includes implanting an impurity into a crystalline semiconductor film that is formed over a base and includes a first part in contact with the base, a second part and a third part, so that at least the second part and the third part...

20060223290 - Method of producing highly strained pecvd silicon nitride thin films at low temperature: A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface of a substrate, said first portion...

20060223291 - Method and apparatus for producing a mems device: A method of producing a MEMS device provides an apparatus having structure on a first layer that is proximate to a substrate. The apparatus has a space proximate to the structure. The method adds doped material to the space. The doped material dopes at least a portion of the first...

20060223292 - Method of manufacturing semiconductor device: In a method of manufacturing a semiconductor device with a MOS transistor, a channel impurity doped layer of a first conductive type is formed in a silicon substrate. First material is implanted into regions for diffusion layers of a second conductive type as sources/drains of the MOS transistor in the...

20060223293 - Semiconductor devices having improved field plates: A field effect transistor device and method, such device having source and drain electrodes in ohmic contact a semiconductor. A gate electrode—field plate structure is disposed between the source and drain electrodes. The gate electrode—field plate structure comprises: a dielectric; a first metal in Schottky contact the semiconductor; and a...

20060223294 - Semiconductor device fabrication method: In a conductive layer fabrication method, a lower resist layer (210) is formed on a semiconductor substrate. A water soluble resin layer (212) is formed over the lower resist layer. Heat treatment is performed so as to produce a cross-linking layer (211) between the lower resist layer and the water...

20060223295 - Nickel silicide including indium and a method of manufacture therefor: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide...

20060223296 - Semiconductor device having self-aligned silicide layer and method thereof: A semiconductor device having a self-aligned silicide layer and a method thereof are provided. The device includes a device isolation layer formed on the substrate to define an active region and a gate pattern crossing over the active region. A spacer insulating layer is formed on both sidewalls of the...

20060223297 - Method for fabricating semiconductor device: First gate lines are formed on a substrate. An insulation layer is formed on the substrate and the first gate lines. The insulation layer disposed between the first gate lines is selectively etched, to thereby form first openings. Landing plugs are buried into the first openings. The insulation layer disposed...

20060223298 - Integrated circuit and methods of redistributing bondpad locations: Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an integrated circuit includes providing an integrated circuit comprising an inner lead bondpad. A first insulative passivation layer is formed over the integrated circuit. A bondpad-redistribution line is formed...

20060223299 - Fabricating process of an electrically conductive structure on a circuit board: The fabricating process of an electrically conductive structure on a circuit board includes: providing a circuit board with a plurality of electrically connecting pads formed thereon; forming a first insulating layer on the circuit board, the first insulating layer covering the electrically connecting pads; forming a conductive layer on the...

20060223301 - Formation of deep via airgaps for three dimensional wafer to wafer interconnect: A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the...

20060223300 - Organometallic precursors for the chemical phase deposition of metal films in interconnect applications: Chemical phase deposition processes utilizing organometallic precursors to form thin films are herein described. The organometallic precursors may include a single metal center or multiple metal centers. The chemical phase deposition may be chemical vapor deposition (CVD), atomic layer deposition (ALD), or hybrid CVD and ALD. The use of these...

20060223302 - Self-aligned contacts for transistors: Self-aligned contacts for transistors and methods for fabricating the contacts are described. An etch resistant material is patterned to create an opening that resides above a transistor gate structure. A selective etch is performed through the opening that does not etch the transistor gate structure but does etch material that...

20060223303 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device includes the step of forming a first insulating section with a protruding section on a semiconductor substrate, the step of forming a first conducting section on the first insulating section so as to pass on a surface of the protruding section, the step...

20060223304 - Semiconductor device and pattern generating method: A first dummy pattern is arranged in the region allowed to generate the first dummy pattern, after that, the second dummy pattern is generated in the region not allowed to generate the first dummy pattern but allowed to generate the second dummy pattern to thereby enable to arrange the dummy...

20060223305 - Etch process for cd reduction of arc material: A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer,...

20060223306 - Method for forming film, method for manufacturing semiconductor device, semiconductor device and substrate treatment system: A film forming method comprise the steps of forming a F-doped carbon film by using a source gas containing C and F, and modifying the F-doped carbon film by radicals, the source gas having a F/C ratio, defined as a ratio of a number of F atoms to a number...

20060223307 - Process for producing electornic component and electronic component: Provided are a process for producing an electronic component which is superior in heat dissipation property, helps to achieve low resistivity, and makes it possible to prevent detachment of the conductor part from the base material, and an electronic component produced by such a process. The electronic component includes: a...

20060223308 - Apparatus for manufacturing a semiconductor device and method of forming the same: An apparatus for manufacturing a semiconductor includes a polyhedral transfer chamber, a first process module for forming a gate dielectric layer by ALD, and a second process module for thermally treating the gate dielectric layer. The first process module is in communication with a first side of the transfer chamber....

20060223309 - Dual-damascene process for manufacturing semiconductor devices: The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to a dual-damascene process for the manufacturing of semiconductor devices. A method of forming a dual-damascene structure includes forming a via hole and filling the via hole at least partially with a first plug material. A...

20060223310 - Method for forming a barrier/seed layer for copper metallization: A method for improving adhesion of Cu to a Ru layer in Cu metallization. The method includes providing a substrate in a process chamber of a deposition system, depositing a Ru layer on the substrate in a chemical vapor deposition process, and forming a Cu seed layer on the Ru...

20060223311 - Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity: By improving the purity of metal lines and the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices may be enhanced. The modification of the crystalline structure of the metal lines may be performed by a heat treatment generating locally restricted heating zones, which...

20060223312 - Method and apparatus for selective deposition of materials to surfaces and substrates: Methods are disclosed for depositing materials selectively and controllably from liquid, near-critical, and/or supercritical fluids to a substrate or surface controlling the location and/or thickness of material(s) deposited to the surface or substrate. In one exemplary process, metals are deposited selectively filling feature patterns (e.g., vias) of substrates. The process...

20060223313 - Copper interconnect post for connecting a semiconductor chip to a substrate and method of fabricating the same: A semiconductor chip comprising at least one contact area for electrically connecting the chip to a substrate, the contact area comprising a metallic contact pad covered by a seed layer and at least one copper interconnect post having a base surface directly contacting the contact area and extending from the...

20060223314 - Method of treating a composite spin-on glass/anti-reflective material prior to cleaning: Methods are provided for cleaning a microelectronic device, and one method includes providing a substrate having a patterned SOG/anti-reflective material; performing a process to cure the patterned SOG/anti-reflective material; and performing a cleaning process to remove the cured SOG/anti-reflective material. An apparatus for cleaning a microelectronic device is provided that...

20060223317 - Plasma processing method and plasma processing apparatus: The plasma processing method comprises the step of removing an organic material film forming an upper layer relative to a patterned SiOCH series film by the processing with a plasma of a process gas containing an O2 gas, wherein the plasma has an O2+ ion density not lower than 1×1011...

20060223318 - Semiconductor device manufacturing method for preventing patterns from inclining in drying process: A method of manufacturing a semiconductor device of the present invention has the steps of forming a pattern made of a processed film or a resist on a substrate, washing the pattern with a washing liquid which is a liquid including at least water, spreading an amphophilic material that has...

20060223316 - Surface treatment method, circuit lines formation method, circuit lines formation apparatus, and printed circuit board formed thereby: The present invention relates to a method of surface treatment, a method for forming circuit lines, a printed circuit board formed thereby, and an apparatus for forming circuit lines on a substrate, wherein fine circuit lines are formed simply, rapidly, and economically. The method for forming circuit lines of the...

20060223315 - Thermal oxidation of silicon using ozone: A method and apparatus for oxidizing materials used in semiconductor integrated circuits, for example, for oxidizing silicon to form a dielectric gate. An ozonator is capable of producing a stream of least 70% ozone. The ozone passes into an RTP chamber through a water-cooled injector projecting into the chamber. Other...

20060223319 - Chemical mechanical polishing method for manufacturing semiconductor device: Disclosed herein is a chemical mechanical polishing (CMP) method for manufacturing a semiconductor device, comprising performing partial ion implantation of dopants at different concentrations into a plurality of at least two divided regions of a wafer having a planarization-target film, and subjecting the partially ion implanted-wafer to a chemical mechanical...

20060223320 - Polishing technique to minimize abrasive removal of material and composition therefor: The present invention provides a composition and a method of polishing a surface that minimizes abrasive removal of material from the surface. To that end, the composition is formulated to maximize dissolution of the material from the surface....

20060223321 - High-density plasma (hdp) chemical vapor deposition (cvd) methods and methods of fabricating semiconductor devices employing the same: In one embodiment, a semiconductor substrate is placed into a process chamber. A gas mixture including a silicon-containing gas, a fluorine-containing gas, an inert gas, and an oxygen gas is introduced into the chamber at a pressure range of from about 30 mTorr to about 90 mTorr. During this time,...

20060223322 - Method of forming a trench structure: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate....

20060223323 - Method of forming an interconnect structure: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate....

20060223324 - Method of fabricating semiconductor device: The method of fabricating a semiconductor device includes subjecting a semiconductor substrate to trench etching by alternately repeating an etching step and a deposition step. The etching step creates a trench structure by dry-etching the exposed surface of the semiconductor substrate. An etching mask is formed on the surface of...

20060223325 - Semiconductor device and method for fabricating the same: A semiconductor device comprises: a lower interconnect formed over a semiconductor substrate; an insulating film formed on the lower interconnect; a via hole penetrating the insulating film to reach the lower interconnect; a first barrier film covering bottom and side surfaces of the via hole; and a metal film filling...

20060223326 - Fabrication method of semiconductor device: A fabrication method of a semiconductor device includes steps of performing any one of O2 ashing, organic processing, and dry etching on a surface of a GaN-based semiconductor layer, etching the surface of the GaN-based semiconductor layer in a mixed solution of acid and an oxidizing agent, and forming an...

20060223327 - Etch with photoresist mask: A method for etching a dielectric layer over a substrate is provided. A photoresist mask is formed over the dielectric layer. The substrate is placed in a plasma processing chamber. An etchant gas comprising NF3 is provided into the plasma chamber. A plasma is formed from the NF3 gas. The...

20060223328 - Apparatus and method for manufacturing semiconductor device, and electronic apparatus: A method for manufacturing a semiconductor device, comprises providing a semiconductor layer deposited on a substrate with heat treatment by using a flame of a gas burner fueled by a hydrogen-and-oxygen mixed gas as a heat source....

20060223329 - Vapor hf etch process mask and method: A method of processing a semiconductor wafer provides a wafer, and then forms an organic mask on at least a portion of the wafer. The method then applies a vapor etching process to the wafer through holes in the organic mask....

20060223330 - Nitride semiconductor device and manufacturing method thereof: A method of manufacturing a nitride semiconductor device includes the steps of forming a groove on a surface of a first substrate by scribing, and forming a nitride semiconductor layer on the surface where the groove is formed. In addition, the method includes the steps of bonding the nitride semiconductor...

20060223331 - Method of forming sheet having foreign material portions used for forming multi-layer wiring board and sheet having foreign portions: The present invention relates to a laminated type electronic part and aims at providing a sheet manufacturing method and a sheet that contribute to high integration, downsizing and enhancement of reliability of the electronic part. To accomplish this object, the manufacturing method according to the present invention involves forming a...

20060223332 - Method of manufacturing semiconductor device: A method of manufacturing semiconductor devices includes forming an interlayer insulation film over a semiconductor substrate, the substrate having a first gate structure for a memory cell and a second gate structure for a control transistor, the interlayer insulation film overlying the first and second gate structures; annealing the interlayer...

20060223333 - Single wafer thermal cvd processes for hemispherical grained silicon and nano-crystalline grain-sized polysilicon: Methods for depositing hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are provided. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are deposited in single substrate chemical vapor deposition chambers. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers may be used as electrode layers in...

20060223334 - System for controlling a plurality of lot processes, method for controlling a plurality of lot processes and method for manufacturing a semiconductor device: A system for controlling lot processes, which are executed in parallel, includes: first and second processing tools processing wafers classified into the lots; a transfer tool transferring the wafers from the first to second processing tools; a recipe storage unit storing recipe data including first and second process periods; a...

20060223335 - Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof: A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent...

20060223336 - Method for forming a resist film on a substrate having non-uniform topography: A preferred embodiment of the invention provides a method of spin coating a liquid, such as a resist, onto a surface of a substrate. An embodiment of the invention comprises dispensing a liquid onto the surface; spinning the substrate at a first rotational velocity at least until the liquid forms...

20060223339 - Ald metal oxide deposition process using direct oxidation: Methods of forming metal compounds such as metal oxides or metal nitrides by sequentially introducing and then reacting metal organic compounds with ozone one or with oxygen radicals or nitrogen radicals formed in a remote plasma chamber. The metal compounds have surprisingly and significantly improved uniformity when deposited by atomic...

20060223337 - Atomic layer deposited titanium silicon oxide films: A dielectric layer containing an atomic layer deposited titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. Embodiments include forming titanium silicates and/or mixtures of titanium oxide and silicon...

20060223338 - Film formation method and recording medium: A method of forming a metal silicate film on a silicon substrate in a processing container is disclosed that includes the steps of (a) forming a base oxide film on the silicon substrate by feeding an oxidation gas into the processing container; and (b) forming the metal silicate film on...

20060223340 - Manufacturing managing method of semiconductor devices and a semiconductor substrate: A managing method of manufacturing semiconductor devices is disclosed. The method comprises the steps of: providing at least one tag region on a semiconductor substrate in which plural semiconductor devices have been formed, the tag region being provided with a tag which can read/write information without making physical contact; writing...