Semiconductor device manufacturing: process inventions 10/06

20060240574 - Method for manufacturing semiconductor device: A semiconductor manufacturing apparatus A semiconductor manufacturing apparatus comprises a hot plate which heats a sapphire substrate; a support table having a support plate disposed with being spaced away from the hot plate by a predetermined interval, and support portions which respectively support the sapphire substrate with being spaced by...

20060240575 - Thin film optical detectors for retinal implantation and methods for making and using same: The present invention provides a method for capturing optical micro detectors for improved surgical handling during implantation into an eye comprising the steps of providing an optically active thin film heterostructure on a soluble substrate; forming an array comprising individual optical microdetectors from the optically active thin film heterostructure; attaching...

20060240577 - Ferroelectric capacitor and manufacturing method thereof: The present invention provides a method for manufacturing a ferroelectric capacitor, comprising the steps of sequentially forming a first conductive film on a semiconductor substrate, a ferroelectric film on the first conductive film, and a second conductive film on the ferroelectric film respectively; etching the second conductive film to form...

20060240576 - Process for fabricating an integrated circuit including a capacitor with a copper electrode: The process and integrated circuit include at least one capacitor in which at least one of the electrodes is made of copper. The method includes forming a nitrogen-doped silicon carbide film between the copper electrode and the dielectric film of the capacitor....

20060240578 - Device mounting substrate and method of repairing defective device: A method of repairing a defective one of devices mounted on substrate is provided. Devices are arrayed on a substrate and electrically connected to wiring lines connected to a drive circuit, to be thus mounted on the substrate. The devices mounted on the substrate are then subjected to an emission...

20060240579 - Method for reducing threshold voltage variations due to gate length differences: The invention provides a method of reducing threshold voltage variations due to gate length differences. The method comprises: providing a substrate having a plurality of MOS transistors at different gate lengths, pocket implanting these MOS transistors at different angles, establishing a relationship between the threshold voltages and gate lengths on...

20060240581 - Method for assembling testing equipment for semiconductor substrate: Upon an assembly of a probe head unit, the relative positions of the probe pins 28ai to those of the electrode group 24E in the pitch-changing substrate 24 are determined by making the positions of the through-holes 26A, 26B, 26C and 26D in the contact block 26 to coincide with...

20060240580 - Method for evaluating reproduced images of wafers: Method for evaluating recorded images of wafers is disclosed. The recording of an image of at least one reference wafer is followed by the determination and representation, on a user interface, of the radial distribution of the measured values of the reference wafer as a radial homogeneity function. A radially...

20060240582 - Methods relating to the reconstruction of semiconductor wafers for wafer-level processing: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface...

20060240584 - Method of producing nitride-based semiconductor device, and light-emitting device produced thereby: A method of producing a nitride-based semiconductor device includes the steps of growing an InxAlyGa1-x-yN(0≦x, 0≦y, x+y<1) buffer layer (2; 12; 22; 32; 42) on a substrate (1; 11; 21; 31; 41) at a first substrate temperature, and growing a first conductivity type nitride-based semiconductor layer (4; 14; 24; 34;...

20060240585 - Package-integrated thin film led: LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth...

20060240583 - Technique for manufacturing silicon structures: A technique for manufacturing silicon structures includes etching a cavity into a first side of an epitaxial wafer. A thickness of an epitaxial layer is selected, based on a desired depth of the etched cavity and a desired membrane thickness. The first side of the epitaxial wafer is then bonded...

20060240586 - Image pickup device and method of manufacturing the same: The present invention relates to an image pickup device, etc., having a structure such that electrostatic discharge is unlikely to occur when an FOP and a CCD reading part are joined. This image pickup device comprises a semiconductor substrate, provided with the CCD reading part on a front surface that...

20060240587 - Transflective liquid crystal display and manufacturing method of the same: A transflective liquid crystal display (LCD) is disclosed where the liquid crystal layer includes a transmission area and a reflective area. The ratio of the liquid crystal molecules to polymers in the reflection area is lower than in the transmission area through independent exposure of the two areas to light...

20060240588 - Method to fabricate a nanowire chemfet sensor device using selective nanowire deposition: A method of fabricating a nanowire CHEMFET sensor mechanism includes preparing a silicon substrate; depositing a polycrystalline ZnO seed layer on the silicon substrate; patterning and etching the polycrystalline ZnO seed layer; depositing an insulating layer over the polycrystalline ZnO seed layer and the silicon substrate; patterning and etching the...

20060240589 - Manufacturing process of semiconductor device: A method of manufacturing a semiconductor device, includes: forming a resin layer with a resin containing an aromatic compound on a surface, where an electrode is formed, of a semiconductor substrate, by avoiding at least part of the electrode; removing an oxide film from a surface of the electrode using...

20060240590 - Controlled synthesis of nanowires, nanodiscs, and nanostructured materials using liquid crystalline templates: A process for synthesizing nanostructures involving providing a first reactant, forming a liquid crystalline template containing the first reactant and contacting the template with a gas phase composed of a second reactant under conditions effective to form nanostructures is disclosed. A method of making a liquid crystalline template by combining...

20060240591 - System and method for processing nanowires with holographic optical tweezers: A system and method for manipulating and processing nanowires in solution with arrays of holographic optical traps. The system and method of the present invention is capable of creating hundreds of individually controlled optical traps with the ability to manipulate objects in three dimensions. Individual nanowires with cross-sections as small...

20060240592 - Integrated circuit package and method for producing it: An integrated circuit includes a first integrated circuit flip chip (105, 205, 305) is bonded to first electric contacts (102, 202, 302) which are an inner part (104, 204, 304) of a planar array (103, 203, 303) of electric contacts. Second electric contacts (106, 206, 306) on the flip chip...

20060240593 - Solid electrolytic capacitor and method for manufacturing the same: In the present invention, a capacitor element including a valve action metal, an oxide film layer formed on the surface of the valve action metal, and a solid electrolytic layer formed on the oxide film layer is provided with an organic compound having a boiling point of not lower than...

20060240594 - Method of making stacked chip electronic package having laminate carrier: A method of making a multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and...

20060240595 - Method and apparatus for flip-chip packaging providing testing capability: A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second...

20060240596 - Semiconductor device with terminals, and method of manufacturing the same: A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval...

20060240597 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device, which includes the steps of: removing an abnormal layer formed on a surface of a wiring substrate, the wiring substrate having a first interlayer insulating film formed on a semiconductor substrate, the first interlayer insulating film having a first recess in which a...

20060240598 - Chip scale package: A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder....

20060240599 - Method of manufacturing a semiconductor device: According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead 1e is smaller than that of a silver plating formed on each lead. Thereafter, a semiconductor...

20060240600 - Semiconductor device and method of manufacturing the same: As a means for promoting the increase of the number of pins in a QFN (Quad Non-leaded package), a semiconductor die mounted on a die pad is arranged at the center of a plastic package, and a plurality of leads made of the same metal as the die pad and...

20060240601 - Selective smile formation under transfer gate in a cmos image sensor pixel: A pixel includes a photodiode and a transfer transistor. The transfer transistor is formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. The transfer transistor has a bird's beak structure formed at the interface of its transfer...

20060240603 - Active matrix circuit substrate, method of manufacturing the same, and active matrix display including the active matrix circuit substrate: An active matrix circuit substrate including data lines, select lines, and pixel circuits electrically coupled with a data line and two adjacent select lines. The pixel circuits include a thin film transistor having a gate electrode coupled with one of the two adjacent select lines and a storage capacitor having...

20060240608 - Method and apparatus for crystallizing silicon, method of forming a thin film transistor, a thin film transistor and a display apparatus using same: A light having a pulse frequency higher than about 300 Hz is generated. The light is irradiated on an amorphous silicon thin film for a predetermined time period to form an initial polysilicon crystal. The light is transported in a predetermined direction to grow the initial polysilicon crystal. A laser...

20060240606 - Method of manufacturing a liquid crystal display device: Disclosed is a photoresist film which is formed in a manner of covering at least a source electrode, a source line, a pixel electrode, a drain electrode, a drain line, a semiconductor film and a protective film, and further covering a gate insulting film in their vicinities. Moreover, wet and...

20060240605 - Organic thin film transistor and method of fabricating the same: An organic thin film transistor (TFT) and a method of fabricating the same are provided. In the method, an organic semiconductor layer is formed by mixing carbon nanotubes with an organic semiconductor material or coating the organic semiconductor material on a carbon nanotube layer. The resulting organic semiconductor layer has...

20060240607 - Sectional field effect devices and method of fabrication: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and...

20060240604 - Thin film transistor, integrated circuit, liquid crystal display, method of producing thin film transistor, and method of exposure using attenuated type mask: A method of producing a thin film transistor comprises irradiating a resist on a glass base plate with a ray from a light source through a mask and, thereafter, developing the resist to form contact holes, using an i-ray as the ray....

20060240602 - Transistor for active matrix display and a method for producing said transistor: A transistor for active matrix display and a method for producing the transistor (1). The transistor (1) includes a microcrystalline silicon film (5) and an insulator (3). The crystalline fraction of the microcrystalline silicon film (5) is above 80%. According to the invention, the transistor (1) includes a plasma treated...

20060240609 - Semiconductor device and method for regional stress control: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried...

20060240610 - Structure and method for dual-gate fet with soi substrate: A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized...

20060240611 - Substrate engineering for optimum cmos device performance: An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has...

20060240612 - Non-volatile memory devices with charge storage insulators and methods of fabricating such devices: A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines...

20060240613 - Methods of operating electrically alterable non-volatile memory cell: A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region....

20060240614 - Field effect transistor: A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor...

20060240621 - Double gate transistors having at least two polysilicon patterns on a thin body used as active region and methods of forming the same: Double gate transistors having at least two polysilicon patterns on a thin body used as an active region and methods of forming the same are provided. Embodiments of the transistors and methods provided are capable of enhancing current drivability of a semiconductor memory device using polysilicon patterns having different impurity...

20060240617 - Formation method of an array source line in nand flash memory: Methods 500 and 550 are disclosed for fabricating an array source line structure in a wafer of a NAND flash memory device. One method aspect 500 comprises forming 510 a first oxide 610 and a nitride layer 611 of an ONO stack 620 over a substrate 604 and an STI...

20060240616 - Memory elements having patterned electrodes and method of forming the same: A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes over a substrate and forming a blanket material stack over the first electrodes. The stack includes a plurality of layers, at least one layer of...

20060240615 - Method of manufacturing a non-volatile memory cell: The present invention relates to a method of manufacturing a non-volatile memory cell. The method comprises forming an ONO stack structure and a mask formed on the ONO stack structure, providing a first etching process to form a first spacer surrounding the mask, removing the first spacer and the ONO...

20060240622 - Multi-channel semiconductor device and method of manufacturing the same: Provided are a multi-channel semiconductor device and a method for manufacturing the semiconductor device through a simplified process. A sacrificial layer and a channel layer are alternately stacked on a semiconductor substrate. Thereafter, the sacrificial layer and the channel layer are etched to form a separated active pattern, and a...

20060240618 - Non-volatile memory and fabricating method thereof and operation thereof: A method of fabricating a non-volatile memory is provided. A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top...

20060240623 - Nonvolatile memory devices having gate structures doped by nitrogen and methods of fabricating the same: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on...

20060240620 - Semiconductor device and method of manufacturing the same: The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the surface of the semiconductor substrate (10) and being located below the control gates (20) and between...

20060240619 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode...

20060240624 - Single transistor ram cell and method of manufacture: A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped...

20060240625 - Power semiconductor device having improved performance and method: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region....

20060240626 - Write once read only memory employing charge trapping in insulators: Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain...

20060240627 - Method for manufacturing semiconductor device capable of improving breakdown voltage characteristics: In a method for manufacturing a MOS transistor, a MOS transistor isolation layer is formed within a semiconductor substrate to surround an area for forming the MOS transistor in the semiconductor substrate. Then, first impurities are introduced into the area of the semiconductor substrate to adjust a threshold voltage of...

20060240628 - High voltage device and method for forming the same: The invention is directed to a method for manufacturing a high voltage device. The method comprises steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type are formed in...

20060240629 - Self correcting suppression of threshold voltage variation in fully depleted transistors: A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second...

20060240630 - Methods of making substitutionally carbon-doped crystalline si-containing materials by chemical vapor deposition: Methods of making Si-containing films that contain relatively high levels of substitutional dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain 2.4 atomic % or greater substitutional carbon. Substitutionally doped Si-containing films may...

20060240631 - Method for manufacturing a solid-state image capturing device and electric information device: A method for manufacturing a solid-state image capturing device, in which at least one electric charge detection section detects each respective one of a plurality of electric charges photoelectrically converted and accumulated at photoelectric conversion sections provided on a semiconductor substrate, each electric charge detection section being shared by a...

20060240632 - Semiconductor device including air gap between semiconductor substrate and l-shaped spacer and method of fabricating the same: A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a vertical portion covering a side wall of the gate pattern, and...

20060240633 - Methods and systems for on-column protein delipidation: Embodiments of the present invention provide a method of chromatographic delipidation comprising separating a lipid-containing sample on a superficially porous stationary phase at greater than about 70° C., at least about 80° C., having at least one mobile phase comprising an ion-pairing agent in water, an ion-pairing agent in an...

20060240634 - Dram access transistor and method of formation: Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions...

20060240637 - Methods of forming semiconductor constructions: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature...

20060240635 - Self-aligned sti sonos: Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402, for example, an ONO stack 420, removing 312 the multi-layer...

20060240636 - Trench isolation methods of semiconductor device: In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A...

20060240638 - Method for the elimination of the effects of defects on wafers: A method eliminates effects of defects on wafers caused by cavities adjacent to the surface of a semiconductor (e.g., silicon) wafer. A first insulating layer is applied to the surface of the semiconductor wafer and into the cavities adjacent to the surface. The applied first insulating layer is covered with...

20060240639 - Fine patterning method for semiconductor device: An insulation film is formed on a semiconductor substrate. A stopper film, which has a large etching selectivity relative to the insulation film and has a first film thickness, is formed on the insulation film. A first mask material, which has a second film thickness that is less than the...

20060240641 - Apparatus and method for making circuitized substrates in a continuous manner: Apparatus and method for making circuitized substrates using a continuous roll format in which layers of conductor and dielectric are fed into the apparatus, bonded, and passed on to other nearby work stations in which various processes such as hole formation, circuitization and, finally, segmentation occur. The resulting substrates can...

20060240640 - Isostatic pressure assisted wafer bonding method: In the invention, wafers are initially weakly bonded. The weak bond is sufficient to impede penetration of an isostatic pressure transmitting media, e.g., a gas or liquid, into any region between the wafers. The weak bond also permits handling. Weak bonds are strengthened, or new bonds formed, by heating and...

20060240645 - Method and system for source switching and in-situ plasma bonding: A system for in-situ plasma treatment. The system has a processing chamber, e.g., plasma chamber. The system has a first susceptor coupled within the chamber and a second susceptor facing the first susceptor and being within the chamber. The system has one or more power sources. Preferably, a first power...

20060240643 - Method for producing a polymer structure on a substrate surface: A method for producing a polymer structure on a patterning region of a substrate surface includes the steps of depositing an adhesion layer having a first polymer material onto the substrate surface, patterning the adhesion layer such that the first polymer material of the adhesion layer is removed in a...

20060240642 - Method of bonding two wafers of semiconductor materials: The invention relates to a method of bonding together two wafers made of materials selected from semiconductor materials by providing two wafers each having a surface that is suitable for molecular bonding; and conducting plasma activation of at least one surface of one of the wafers by directing plasma species...

20060240644 - Substrate with determinate thermal expansion coefficient: A composite support designed to successfully receive a transfer layer made of a crystalline material so that the assembly forms an epitaxy substrate, with the support having a longitudinal plane of symmetry parallel to its principal surfaces and a plurality of layers. The support includes a central first layer having...

20060240646 - Method of removing residual contaminants from an environment: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound...

20060240647 - Film control method and device thereof: The surface of an amorphous silicon film formed on a glass substrate is cleaned by hydrofluoric acid in a spin clean unit. The glass substrate is conveyed to a waiting unit where the glass substrate is made to wait for about 15 minutes. Active fluoride adhered on the amorphous silicon...

20060240648 - Atmospheric glow discharge with concurrent coating deposition: A plasma is produced in a treatment space (58) by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes (54,56) separated by a dielectric material (64), a precursor material is introduced into the treatment space to coat a substrate film...

20060240649 - Method for depositing silicon: The inventive method for depositing silicon onto a substrate firstly involves the introduction of a reactive silicon-containing gas and hydrogen into the plasma chamber and then the initiation of the plasma. After initiating the plasma, only reactive silicon-containing gas or a gas mixture containing hydrogen is supplied to the plasma...

20060240650 - Semiconductor device having a plurality of different layers and method therefor: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried...

20060240651 - Methods and apparatus for adjusting ion implant parameters for improved process control: A method for processing a substrate, such as a semiconductor wafer, includes performing a measurement to determine a substrate parameter distribution to be compensated, determining an adjusted implant parameter distribution to compensate for the substrate parameter distribution, and implanting the substrate in accordance with the adjusted implant parameter distribution. The...

20060240652 - Very low dielectric constant plasma-enhanced cvd films: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced...

20060240653 - One-device non-volatile random access memory cell: One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between the first diffusion region and...

20060240654 - Process of forming a self-aligned contact in a semiconductor device: A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresist pattern on a surface of the...

20060240655 - Semiconductor device having contact plug formed in double structure by using epitaxial stack and metal layer and method for fabricating the same: Disclosed are a contact plug of a semiconductor device and a method for fabricating the same. The semiconductor device includes: an epitaxial stack formed by inserting a heteroepitaxy layer between a pair of homoepitaxy layers; and a contact plug including a metal layer on the epitaxial stack. Accordingly, in accordance...

20060240656 - Method for forming contact of semiconductor device by using solid phase epitaxy process: A method for forming a contact plug of a semiconductor device includes providing a plurality of junctions on a substrate; forming an inter-layer insulation layer over the substrate and the junctions; forming a plurality of contact holes to expose the junctions by etching the inter-layer insulation layer; forming contact layers...

20060240657 - Semiconductor device and method of manufacturing the same: A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along...

20060240658 - Gap control between interposer and substrate in electronic assemblies: Electronic assemblies and methods for forming assemblies are described. One embodiment includes a method of forming an electronic assembly, including forming a plurality of first solder bumps on one of a substrate and an interposer. The substrate and interposer are positioned so that the first solder bumps are located between...

20060240659 - Metal interconnection structure of a semiconductor device having low resistance and method of fabricating the same: Provided is a metal interconnection structure of a semiconductor device, comprising a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and...

20060240660 - Semiconductor stucture and method of manufacturing the same: A semiconductor structure for a substrate having electronic elements formed thereon. The semiconductor structure comprises a dielectric layer and a conductive stuffing material. The dielectric layer is located over the substrate. It should be noticed that the dielectric layer has a plurality of trenched and a border shape of each...

20060240661 - Method of preventing damage to porous low-k materials during resist stripping: A method of forming a feature in a porous low-K dielectric layer is provided. A porous low-K dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the porous low-K dielectric layer. A feature is etched into the porous low-K dielectric layer. A protective layer is...

20060240662 - Method to perform selective atomic layer deposition of zinc oxide: A method for selective ALD of ZnO on a wafer preparing a silicon wafer; patterning the silicon wafer with a blocking agent in selected regions where deposition of ZnO is to be inhibited, wherein the blocking agent is taken from a group of blocking agents includes isopropyl alcohol, acetone and...

20060240663 - Methods of forming a resistance variable element: The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a deposition chamber comprising a sputtering target and a substrate to be depositing upon. The...

20060240664 - Method of manufacturing multi-layered substrate: A method of manufacturing a multi-layered substrate includes providing an electronic component on a surface of a substrate so that a terminal of the electronic component faces upward. The method also includes providing a first insulation pattern on the surface so as to fill a step generated due to a...

20060240665 - Methods of producing integrated circuit devices utilizing tantalum amine derivatives: In a method for forming a field effect transistor, a metal nitride layer is formed on a gate electode insulating layer. Tantalum amine derivatives represented by the chemical formula Ta(NR1)(NR2R3)3, in which R1, R2 and R3 represent H or a C1-C6 alkyl group, may be used to form the metal...

20060240667 - Method for manufacturing semiconductor device: Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is...

20060240666 - Method of forming silicide: A method of forming silicide is described. A layer of refractory metal is deposited on a substrate, and then a first annealing process is performed to form silicide, followed by removal of unreacted metal. Next, a species implanting process is carried out to implant species of neutral atoms into the...

20060240668 - Semiconductor device with metallic electrodes and a method for use in forming such a device: A semiconductor device comprising: a first electrode component; a second electrode component; a first layer comprising at least a portion of the first electrode component and at least a portion of the second electrode component; a second layer having a portion comprising deposited semiconductor material contacting the first and second...

20060240669 - Method of forming vapor-deposited film and method of manufacturing el display device: A method of forming a vapor-deposited film includes the steps of: aligning a mask having a plurality of openings with a substrate; forming a film on the substrate through the openings of the mask by the use of a vapor deposition method; and cleaning the mask in a state that...

20060240670 - Etching of algainassb: The present invention relates to a wet acid etchant for wet acid etching of intrinsic, n-doped or p-doped Al1−x−zGaxInzAs1−ySby with 0<x<1, 0<y<1, 0≦z<1 and 0<x+z<1, a process for wet acid etching of intrinsic, n-doped or p-doped Al1−x−zGaxInzAs1−ySby with 0<x<1, 0<y<1, 0≦z<1 and 0<x+z<1, and a semiconductor structure prepared by wet...

20060240671 - Method of reducing outgassing pollution: A method for reducing outgassing pollution in a semiconductor process includes matching a pressure of a VCE with a pressure of a process chamber before reaction gas is injected into the process chamber, injecting the reaction gas into the process chamber, opening a partitioning door disposed between the VCE and...

20060240672 - Polishing liquid composition: A polishing liquid composition is applicable as a means of forming embedded metal interconnections on a semiconductor substrate. In a surface to be polished comprising an insulating layer and a metal interconnection layer, the polishing liquid composition is capable of maintaining a polishing speed of the metal layer, of suppressing...

20060240673 - Method of forming bit line in semiconductor device: A method of forming a bit line of a semiconductor device wherein an etch-stop nitride film, a trench oxide film and a hard mask nitride film are formed on a semiconductor substrate. The hard mask nitride film and the trench oxide film are etched to a limited etch thickness of...

20060240674 - Method for manufacturing semiconductor device: A gate electrode is formed of a laminate structure comprising a plurality of conductive layers such that the width along the channel of a lower first conductive layer is larger than that of an upper second conductive layer The gate electrode is used as a mask during ion doping for...

20060240675 - Removal of silicon oxycarbide from substrates: A method of treating a substrate comprises depositing silicon oxycarbide on the substrate and removing the silicon oxycarbide from the substrate. The silicon oxycarbide on the substrate is decarbonized by exposure to an energized oxygen-containing gas that heats the substrate and converts the layer of silicon oxycarbide into a layer...

20060240676 - Lawn and garden battery clamp: An improved battery cable clamp provides for toolless attachment of battery cable connectors to lawn and garden-type battery terminal posts utilizing a bossed handle, cam seat and thumbnut, preferably made of non-corrosive materials....

20060240677 - Method for manufacturing semiconductor device and substrate processing apparatus: An oxidizer supply device (30) comprises an ozonizer (31) for generating ozone (32), a bubbler (34) wherein deionized water (35) is kept and an ozone supply pipe (33) for supplying ozone (32) from the ozonizer (31) is immersed in the deionized water (35) so as to bubble ozone, and a...

20060240678 - Method of forming a lp-cvd oxide film without oxidizing an underlying metal film: A method of manufacturing a semiconductor device includes forming a LP-CVD oxide film on sides of a gate including a metal film by means of a LP-CVD method that does not cause oxidization of the metal film. Oxidization of a metal film can be prevented physically, and degradation of the...

20060240679 - Method of manufacturing semiconductor device having reaction barrier layer: A method of manufacturing a semiconductor device comprises forming a lower electrode on a substrate using a titanium chloride pulsed deposition (TPD) process, forming a high-k dielectric layer on the lower electrode, and forming an upper electrode on the dielectric layer using a TPD process. The method further comprises forming...

20060240680 - Substrate processing platform allowing processing in different ambients: A semiconductor wafer processing system including a factory interface operating at atmospheric pressure and mounting plural wafer cassettes and plural wafer processing chambers connected to the factory interface through respective slit valves. A robot in the factory interface can transfer wafers between the cassettes and the processing chambers. At least...

20060240681 - Three-dimensional nanoscale crossbars: Various embodiments of the present invention include three-dimensional, at least partially nanoscale, electronic circuits and devices in which signals can be routed in three independent directions, and in which electronic components can be fabricated at junctions interconnected by internal signal lines. The three-dimensional, at least partially nanoscale, electronic circuits and...

20060234394 - Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo,...

20060234393 - Scalable high density non-volatile memory cells in a contactless memory array: A plurality of split gate non-volatile memory cells are formed vertically in a trench along the sidewalls. Each cell is comprised of a bistable element and an adjacent fixed gate threshold element that share a common respective control gate/access gate. The bistable element has a gate insulator stack that is...

20060234397 - Magnetic annealing sequences for patterned mram synthetic antiferromagnetic pinned layers: A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an antiferromagnetic pinning layer over a substrate and a ferromagnetic pinned layer over the pinning layer, the pinned layer having a first thickness. The fixed layer...

20060234395 - Method for manufacturing perovskite type oxide layer, method for manufacturing ferroelectric memory and method for manufacturing surface acoustic wave element: A method for manufacturing a perovskite type oxide layer includes the steps of: forming, above a substrate, a first oxide layer composed of perovskite type oxide; forming, above the first oxide layer, a second oxide layer composed of at least one of a perovskite type oxide layer crystallized at a...

20060234396 - Method for producing structure: Disclosed is a method for producing a structure having: a stripping step in which an aluminum member including an aluminum substrate and an anodized layer present on the aluminum substrate, which layer contains micropores having an average pore diameter of 10 to 500 nm and a coefficient of variation in...

20060234398 - Single ic-chip design on wafer with an embedded sensor utilizing rf capabilities to enable real-time data transmission: An apparatus and method for real-time monitoring process conditions of a semiconductor wafer processing operation. A semiconductor wafer subject to processing in a wafer processing tool is embedded with one or more sensor devices. In response to receipt of wireless electromagnetic signals, the embedded sensor devices are activated for generating...

20060234399 - Meander metal line under the pad for improved device mm esd performance: A method is disclosed for enhancing ESD protection of integrated circuit devices. The method entails placing a resistor between an I/O pad and an ESD protection device on a semiconductor chip so that one end of the resistor connects to pins on said I/O pad and the other end connects...

20060234401 - Early detection test for identifying defective semiconductor wafers in a front-end manufacturing line: A method and apparatus for identifying defective partially manufactured semiconductor wafers in a manufacturing line is described, wherein defects caused by silicon erosion created by over-etching the wafer can be detected. The method described herein is based on an in-line test of selected structures, such as FETs, located in the...

20060234404 - Method for predicting and optimizing chip performance in cured thermoset coatings: Disclosed is a method for evaluating chip performance of a cured coating system. In one embodiment, the method includes providing a coated substrate comprising a substrate and a cured film of a first coating composition thereon, measuring elastic work energy (We/Wtot) of the cured film, and calculating a % C.P....

20060234400 - Method of judging quality of semiconductor epitaxial crystal wafer and wafer manufacturing method using the same: In a method of determining the quality of a semiconductor epitaxial crystal wafer having a buffer structure portion comprised of epitaxial layers the semiconductor epitaxial crystal wafer (S) is irradiated with pulsed exciting light (5A) to modulate an internal electric field of the buffer structure portion, the electric transport properties...

20060234402 - Method of recipe control operation: An operation method of a recipe control process in which multiple processing targets are processed continuously in a processing apparatus using recipes that specify a set of control parameters specifying the processing conditions of processing targets. The method comprises the steps of: (I) specifying correction coefficients to correct at least...

20060234403 - Wat process to avoid wiring defects: A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer....

20060234405 - Semiconductor device with self-aligning contactless interface: Contactless interconnects between an integrated circuit die and an electrical structure are aligned by charging alignment pads on the integrated circuit die to a first voltage, and charging counterpart alignment pads on the electrical structure to a second voltage. The integrated circuit die is disposed in an initial position relative...

20060234406 - Method of forming protective structure for active matrix triode field emission device: A method for forming a protective structure of active matrix triode field emission device is provided. The method comprises the steps of forming a silicon active region; depositing a gate oxide layer over the silicon active region; depositing and patterning a first metal layer over the gate oxide layer; doping...

20060234408 - Method for manufacturing vertical group iii-nitride light emitting device: The invention provides a vertical group III-nitride light emitting device improved in external extraction efficiency and a method for manufacturing the same. The method includes forming an undoped GaN layer and an insulating layer on a basic substrate. Then, the insulating layer is selectively etched to form an insulating pattern,...

20060234407 - Method of fabricating vertical structure nitride semiconductor light emitting device: A method of fabricating a vertical structure nitride semiconductor light emitting device having a cross-sectional shape of a polygon having five or more sides or a circle. A light emitting structure is formed on a sapphire substrate. A metal layer having a plurality of patterns is formed on the light...

20060234409 - Light emitting device, display apparatus with an array of light emitting devices, and display apparatus method of manufacture: A light emitting device and display apparatus using a plurality of light emitting devices can drastically reduce contrast loss due to light from an external source. The light emitting device has a light emitting chip(s) and a first layer covering the light emitting chip(s). A second layer including a light...

20060234410 - Method for fabricating organic electroluminescent devices: A method for fabricating organic electroluminescent elements comprising an LTPS-TFT as driving circuits. The method comprises providing a substrate, forming an LTPS-TFT on the substrate, and forming an OLED electrically connecting the LTPS-TFT. Specifically, the method for forming a channel region of the LTPS-TFT includes forming a polysilicon layer with...

20060234411 - Method of manufacturing nitride semiconductor light emitting diode: The invention relates to a method of manufacturing a semiconductor light emitting diode. In the method, an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer are formed sequentially on a substrate. Then, a nickel oxide (NiOx) film is directly deposited on the p-type semiconductor layer...

20060234412 - Mems release methods: A packaged MEMS device is fabricated by providing a first substrate, forming the MEMS device on the first substrate (the MEMS device including at least one element initially held immobile by a sacrificial material), optionally removing a portion of the sacrificial material without releasing the element, providing a second substrate,...

20060234413 - Method for forming anti-stiction bumps on a micro-electro mechanical structure: A technique for forming anti-stiction bumps on a bottom surface of a micro-electro mechanical (MEM) structure includes a number of process steps. The MEM structure is fabricated from an assembly that includes a support substrate bonded to a single-crystal semiconductor layer, via an insulator layer. A plurality of holes are...

20060234414 - Calorimetric flow meter: An encapsulated calorimetric flow meter according to the present invention comprises an integrated circuit (104) mounted on a lead frame (102). The integrated circuit has a channel (105) provided in its lower face, the channel being aligned with two holes (103) provided in the lead frame, the holes coinciding with...

20060234415 - Solid state imaging apparatus and driving method of solid state imaging apparatus: A solid state imaging apparatus comprises a semiconductor substrate, photoelectric conversion elements, a vertical electric charge transferring device, a horizontal electric charge transferring device that temporarily stores the signal electric charges transferred from the vertical electric charge transferring device and transfers the signal electric charges to a horizontal direction in...

20060234416 - Light emitting device and manufacturing method therefor: To provide a light emitting element having a top emission structure, which can be easily manufactured without considering an ionization potential of an electrode (particularly an electrode in contact with a substrate) and a manufacturing method therefor. A light emitting device having the top emission structure according to the present...

20060234417 - Composite nanoparticle and process for producing the same: There is provided composite nano-particles comprising nano-crystal particles dispersed stably and individually in suspension in high concentration without mutual aggregation of the nano-particles. A determined amount of pure water or deionized water is poured into a reactor, into which is introduced nitrogen gas at rate of 300 cm3/min for a...

20060234418 - Method for fabricating a nonvolatile memory element and a nonvolatile memory element: In a method for fabricating a nonvolatile memory element a substrate is provided, a nanomask structure is fabricated on the substrate and a self-assembled monolayer of an organic memory molecule is grown on the substrate on a region not covered by the nanomask structure. A surface of the substrate is...

20060234419 - Diamond medical devices: Masked and controlled ion implants, coupled with annealing or etching are used in CVD formed single crystal diamond to create structures for both optical applications, nanoelectromechanical device formation, and medical device formation. Ion implantation is employed to deliver one or more atomic species into and beneath the diamond growth surface...

20060234420 - Electronic device: In an electronic device having an interposer substrate as an MCM structure, heat dissipation properties are enhanced while the reliability of joint between the interposer substrate and a mother board is maintained. In the invention, a metal core base material of great heat capacity and high thermal conductivity is used...

20060234421 - Method of forming a substrateless semiconductor package: A method of forming a substrateless semiconductor package (10) includes forming a carrier (16) on a base plate (12) and attaching an integrated circuit (IC) die (32) to the carrier (16). The IC die (32) then is electrically connected to the carrier (16). A molding operation is performed to encapsulate...

20060234422 - Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers: Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors...

20060234423 - System for providing a redistribution metal layer in an integrated circuit: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder...

20060234425 - Method of manufacture of a pcram memory cell: The invention provides a method of forming a resistance variable memory element and the resulting element. The method includes forming an insulating layer having an opening therein; forming a metal containing layer recessed in the opening; forming a resistance variable material in the opening and over the metal containing layer;...

20060234424 - Technique for compensating for substrate shrinkage during manufacture of an electronic assembly: Substrate shrinkage that occurs during manufacture of an electronic assembly is compensated for by the incorporation of a horizontal line, having a plurality of vertical graduations, across a horizontal portion of a substrate and a vertical line, having a plurality of horizontal graduations, across a vertical portion of the substrate....

20060234426 - Leadframe with encapsulant guide and method for the fabrication thereof: A method for fabricating a leadframe with encapsulant guide is provided, including forming a die attach paddle. Leads are formed around at least portions of the die attach paddle, and encapsulant guides are formed angled on a plurality of the leads to push the leads outwardly when an encapsulant flows...

20060234427 - Underfill dispense at substrate aperture: Disclosed are methods for dispensing underfill material in an IC assembly having a die mounted on a substrate with a gap therebetween. One or more aperture is provided in the substrate for receiving underfill material into the gap. Underfill material is dispensed into the gap through the one or more...

20060234429 - Method for fabricating thin film transistor of liquid crystal display device: A method for fabricating a thin film transistor for an LCD device is presented that uses six mask processes. Portions of a semiconductor layer formed on a substrate are doped with first and second impurities in different regions. A conductive layer is deposited and the conductive and semiconductor layers patterned...

20060234428 - Methods of implementing and enhanced silicon-on-insulator (soi) box structures: Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The...

20060234430 - Tft fabrication process: A process for fabricating a thin film transistor including: (a) depositing a semiconductor layer; and (b) depositing a multilayer gate dielectric prior to or subsequent to the depositing the semiconductor layer, wherein the multilayer dielectric comprises: (i) a first layer comprising a first material selected from the group consisting of...

20060234431 - Doping of semiconductor fin devices: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface....

20060234432 - Soi bottom pre-doping merged e-sige for poly height reduction: Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive...

20060234434 - Pecvd nitride film: A method for forming a semiconductor device is provided. In accordance with the method, a substrate (103) is provided, and a dielectric material (123) is formed on the substrate through plasma enhanced chemical vapor deposition (PECVD). The PECVD is conducted at a temperature of greater than 300° C., and utilizes...

20060234433 - Transistors and methods of manufacture thereof: Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate comprises a layer...

20060234435 - Semiconductor device having one-time programmable rom and method of fabricating the same: A semiconductor device with a one-time programmable (OTP) ROM disposed over a semiconductor substrate including a memory cell area and a peripheral circuit area includes a MOS transistor and an OTP ROM capacitor. The MOS transistor has a floating gate electrode and is disposed at the memory cell area. The...

20060234436 - Method of forming a semiconductor device having a high-k dielectric: A metal oxide is formed over a high quality oxide which has been deposited over a substrate. An anneal drives a reaction to form a metal oxysilicon nitride layer which is then used as a part of a gate stack. The novel integration scheme allows for improved scalablity of devices...

20060234437 - Recessed-type field effect transistor with reduced body effect: For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the...

20060234438 - Self-aligned contact for silicon-on-insulator devices: A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation...

20060234439 - Maskless multiple sheet polysilicon resistor: The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer is patterned to form a polysilicon resistor (108). A poly resistor mask having a selected...

20060234440 - Alignment mark and alignment method for the fabrication of trench-capacitor dram devices: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench...

20060234441 - Method for preparing a deep trench: A method for preparing a deep trench first forms a trench in a semiconductor substrate and a stacked structure in the trench, wherein the stacked structure includes at least one nitrogen-containing layer. A phosphorous oxide layer is then formed on the surface of the nitrogen-containing layer. The phosphorous oxide is...

20060234442 - Semiconductor device and method of fabricating the same: According to an aspect of the invention, there is provided a semiconductor device comprising a capacitor formed above a semiconductor substrate by sandwiching a dielectric film between a lower electrode and an upper electrode including an electrode film which contains an MOx type conductive oxide (M is a metal element,...

20060234443 - Mim capacitor and method of fabricating same: A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a...

20060234449 - Flash gate stack notch to improve coupling ratio: A semiconductor flash memory device with increased gate coupling ratio and a method of preparing this flash memory device. The semiconductor flash memory device includes a notched floating polysilicon gate. The notches are at the interface between the floating polysilicon layer and the tunneling dielectric layer. The notches reduce the...

20060234447 - Methods of fabricating nonvolatile memory devices and related devices: Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate...

20060234445 - Mtj read head with sidewall spacers: Following CMP, a magnetic tunnel junction stack may protrude through the oxide that surrounds it, making it susceptible to possible shorting to its sidewalls. The present invention overcomes this problem by depositing silicon nitride spacers on these sidewalls prior to oxide deposition and CMP. So, even though the stack may...

20060234446 - Non-volatile memory and fabricating method thereof: A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a...

20060234450 - Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel...

20060234448 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an element isolation insulating film, memory cell transistors formed in an element isolation region and having respective gate electrodes, and a stopper film for forming a contact, formed both on a sidewall of the gate electrode of each transistor and on the element isolation insulating film...

20060234444 - Split gate flash memory cell and manufacturing method thereof: A split gate flash memory cell includes a substrate having a device isolation structure; a selective gate structure disposed on the substrate; an interlayer dielectric layer having an opening disposed on the substrate, wherein the opening exposes a portion of the selective gate structure, the substrate and the device isolation...

20060234451 - Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor: The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements...

20060234452 - Non-volatile memory and fabricating method thereof: A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control...

20060234453 - Non-volatile memory and fabrication method thereof: A non-volatile memory cell is provided. The non-volatile memory includes a substrate, a gate stacked layer, an isolation layer and a conductive layer. The gate stacked layer includes a tunneling layer, a charge trapping layer, a barrier layer and a control gate layer sequentially stacked over the substrate, and the...

20060234454 - Method of fabricating nonvolatile semiconductor memory devices with uniform sidewall gate length: After forming a first dielectric film on the main surface of a semiconductor substrate, a first conductive film is formed on the first dielectric film, and then, the surface of the first conductive film is planarized by a CMP method. Subsequently, the first conductive film and the first dielectric film...

20060234455 - Structures and methods for forming a locally strained transistor: Embodiments of the invention provide structures and methods for forming a strained MOS transistor. A preferred embodiment includes creating a compressive strain in a PMOS transistor for improving carrier mobility without the need for source/drain recess formation and SiGe epitaxy. Embodiments comprise forming a gate electrode on a silicon substrate,...

20060234456 - Four-bit finfet nvram memory device: A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and...

20060234457 - Non-volatile memory device and method of fabricating the same: A method of fabricating an a non-volatile memory includes forming trench isolation regions in an inactive region of a semiconductor substrate, adjacent trench isolation regions defining respective protrusions having rounded edges therebetween, wherein upper surfaces of the trench isolation regions are lower than an upper surface of the semiconductor substrate...

20060234458 - Dual wavelength thermal flux laser anneal: A thermal processing apparatus and method in which a first laser source, for example, a CO2 emitting at 10.6 μm is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer...

20060234459 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device in which a plurality of wiring layers are formed includes the steps of (a) preparing a semiconductor device on which a plurality of semiconductor elements are formed on one surface thereof, (b) forming a spiral inductor on the semiconductor substrate astride three or...

20060234460 - Method for making cable with a conductive bump array, and method for connecting the cable to a task object: A cable with conductive bumps is fabricated by forming a photoresist layer with multiple openings on a cable substrate, coating a conductive layer on the photoresist layer whereby the conductive layer in the openings forms the bumps at circuits on the cable substrate, and then removing the photoresist layer. When...

20060234461 - Process for cleaning silicon substrate: In the production process of an SOI substrate using a hydrogen ion implantation method, a process is provided for cleaning the substrate which can prevent formation of voids when bonding substrates and formation of blistering after exfoliation. In the process for cleaning, cleaning of the substrate is performed before performing...

20060234462 - Method of operating a multi-terminal electronic device: A method of operating a multi-terminal electronic device. The device includes an active material in electrical communication with three or more electrical terminals. The active material is able to undergo a transformation from one state to another state, where the two states differ in resistance. The method includes the step...

20060234463 - Method for fabricating an electrical component: An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the...

20060234464 - Method for fabricating an integrated circuit comprising a three-dimensional capacitor: A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form...

20060234466 - Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three...

20060234465 - Methods of forming materials comprising tungsten and nitrogen, and methods of forming capacitors: In one aspect, the invention includes a method of forming a material comprising tungsten and nitrogen, comprising: a) providing a substrate; b) depositing a layer comprising tungsten and nitrogen over the substrate; and c) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a...

20060234469 - A method of forming semiconductor structures: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c)...

20060234468 - Method for manufacturing a semiconductor device, as well as a semiconductor substrate: A method for manufacturing a semiconductor device, includes: forming a recognition mark that defines a well-forming region for forming a well on a semiconductor substrate; forming a mask, using the recognition mark, that is patterned so that the well-forming region is opened; introducing an impurity into the well-forming region; performing...

20060234467 - Method of forming trench isolation in a semiconductor device: Divots (35, 36) may particularly be a problem for isolation trenches (22, 24) that are shallow. These divots (35, 36) may have a negative impact on the performance of the integrated circuit (49). Densification heating may be used to reduce the size and/or depth of these divots (35, 36) during...

20060234470 - Process sequence for doped silicon fill of deep trenches: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way...

20060234471 - Method for manufacturing semiconductor device: A semiconductor device having an improved connecting reliability of an interconnect is presented via a simple and easy process, and further, a semiconductor device having a stable threshold voltage of a transistor that provide a stable electrical characteristic is also presented. A method for manufacturing a semiconductor device according to...

20060234472 - Method and device for pre-treating surfaces of substrates to be bonded: The present invention provides a process and a device for treating the surfaces or bonding surfaces of substrates before bonding the substrates. In accordance with the invention, the surfaces of substrates to be bonded are treated with an atmospheric plasma before bonding. The surfaces of the substrates can thus be...

20060234473 - Thin passivation layer on 3d devices: Embodiments of the invention include a device with stacked substrates. Conducting interconnecting structures of one substrate are bonded to conducting interconnecting structures of another substrate. A passivating layer may be on the conducting interconnecting structures between the substrates and may be formed by an atomic layer deposition process or a...

20060234474 - Method of transferring a thin crystalline semiconductor layer: A method for transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and transfer of the monocrystalline thin layer with the cleaving controlled to happen within...

20060234476 - Electronic component and method for its production: An electronic component includes a semiconductor die which exhibits on its active top side above an active surface area a self-supporting electrically conductive cover layer which is supported by through lines and forms a hollow space to the active surface area. A method for producing the electronic component includes additional...

20060234475 - Method for manufacturing semiconductor device: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a dummy contact hole is formed in a scribe lane by employing a direct polyimide etching (‘DPE’) process reducing the two steps of a masking process to one step and a passivation layer filling up...

20060234477 - Glass-based semiconductor on insulator structures and methods of making same: Methods and apparatus provide for: a semiconductor wafer; at least one porous layer in the semiconductor wafer; an epitaxial semiconductor layer directly or indirectly on the porous layer; and a glass substrate bonded to the epitaxial semiconductor layer via electrolysis....

20060234478 - Semiconductor device substrate and method of manufacturing semiconductor device substrate: A method of manufacturing a semiconductor device substrate includes forming a mask layer pattern on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the...

20060234479 - Implantation-less approach to fabricating strained semiconductor on isolation wafers: A method of fabrication of semiconductor substrate structure comprising the following. A buffer layer is formed on the Si Substrate. We form a SiGe layer on the novel buffer layer. The buffer layer has defects therein so that the buffer layer is oxidized to form a buried isolation layer comprised...

20060234480 - Low temperature melt-processing of organic-inorganic hybrid: The present invention provides a process for preparing a melt-processed organic-inorganic hybrid material including the steps of maintaining a solid organic-inorganic hybrid material at a temperature above the melting point but below the decomposition temperature of the organic-inorganic hybrid material for a period of time sufficient to form a uniform...

20060234481 - Structure for and method of fabricating a high-mobility field-effect transistor: A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping...

20060234482 - Semiconductor chip having a soldering layer sequence, and process for soldering a semiconductor chip: A semiconductor chip (1), to which a layer sequence (2) intended for the production of a soldered connection has been applied. The layer sequence (2) comprises a solder layer (15) and an oxidation prevention layer (17), which follows the solder layer (15) as seen from the semiconductor chip (1). A...

20060234483 - Cpp read sensor fabrication using heat resistant photomask: A method is disclosed for fabricating a CPP read head for a magnetic disk drive having an electrical isolation layer. The method includes providing a first shield layer, depositing a sensor stack on the first shield layer, a CMP stop layer is deposited on the sensor stack, and a release...

20060234484 - Method and structure for ion implantation by ion scattering: A scatter-implant process and device is provided where a bi-level doping pattern is achieved in a single doping step. Additionally, devices having different breakdown voltages can be produced in a single implant process. The scatter-implant is fabricated by scattering implant ions off the edge of a mask, thereby reducing the...

20060234485 - Salicide process: A salicide process is provided. A metal layer selected from a group consisting of titanium, cobalt, platinum, palladium and an alloy thereof is formed over a silicon layer. A first thermal process is performed. Next, a second thermal process is performed, wherein the second thermal process includes a first step...

20060234486 - Wafer separation technique for the fabrication of free-standing (al,in,ga)n wafers: A method of fabricating free-standing (Al, In, Ga)N substrates, by in situ separation of thick epitaxially grown nitride films from their foreign substrates. A suitable substrate for (Al, In, Ga)N film growth is selected, and foreign ions are implanted in the substrate to form a comparatively sharp concentration profile. An...

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