Semiconductor device manufacturing: process inventions 09/06

20060211155 - Magnetic random access memory array with thin conduction electrical read and write lines: An MTJ MRAM cell is formed between ultra-thin orthogonal word and bit lines of high conductivity material whose thickness is less than 100 nm. Lines of this thickness produce switching magnetic fields at the cell free layer that are enhanced by a factor of approximately two for a given current....

20060211154 - Method of manufacturing patterned ferroelectric media: A method of manufacturing patterned ferroelectric media, which includes forming an electrode on a substrate; forming features having a predetermined pattern on the electrode, the features including a precursor for forming a ferroelectric material; and reacting a source material with the precursor features to transform the precursor features into ferroelectric...

20060211153 - Photolithographic techniques for producing angled lines: The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. Various method embodiments relate to forming a magnetic random access memory (MRAM) array. Various...

20060211156 - Semiconductor device and its manufacture method, and measurement fixture for the semiconductor device: A semiconductor device comprises a substrate, a ferroelectric capacitor which includes a ferroelectric film on the substrate, and a stress application layer which applies tensile or compressive stress to the ferroelectric film of the ferroelectric capacitor by applying stress to the substrate....

20060211152 - Synthetic control of metal oxide nanocrystal sizes and shapes: A general, reproducible, and simple synthetic method that employs readily available chemicals permits control of the size, shape, and size distribution of metal oxide nanocrystals. The synthesis entails reacting a metal fatty acid salt, the corresponding fatty acid, and a hydrocarbon solvent, with the reaction product being pyrolyzed to the...

20060211157 - Novel cmp endpoint detection process: The present invention provides a method for polishing a layer of material, a method for manufacturing a damascene interconnect structure, and a method for manufacturing an integrated circuit. The method for polishing a layer of material, among other steps, includes obtaining a substrate (310) having a layer of material (330)...

20060211158 - Method and apparatus for perforating printed circuit board: A method and an apparatus for perforating a printed circuit board are provided so that the processing efficiency and the board densification can be improved. In test processing, a conductor layer 50i is irradiated with a pulsed laser beam 4a whose energy density is set at a value high enough...

20060211159 - Method for the production of semi-conductor chips: m

20060211160 - Emitter, manufacturing method and manufacturing apparatus thereof, electro-optical apparatus and electronic apparatus: An emitter has a plurality of types of light-emitting units with different changes in emission characteristics over time. In addition, the emitter includes a deterioration adjustment device which adjusts the deterioration of the emission characteristics over time in a predetermined type of light-emitting unit. The light-emitting units respectively include a...

20060211161 - Method of making microsensor: A linear accelerometer is provided having a support substrate, fixed electrodes having fixed capacitive plates, and a movable inertial mass having movable capacitive plates capacitively coupled to the fixed capacitive plates. Adjacent capacitive plates vary in height. The accelerometer further includes support tethers for supporting the inertial mass and allowing...

20060211163 - Anhydrous hf release of process for mems devices: A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100° C. and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at...

20060211162 - Crystal-structure-processed devices, methods and systems for making: Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, mechanical devices. Processing is laser-performed in relation to a selected material whose internal crystalline structure becomes appropriately changed thereby to establish the desired mechanical properties for a created device....

20060211164 - Color filter substrate manufacturing method: A method of manufacturing a color filter substrate includes providing a base, forming a reflective film over the base, forming a plurality of banks on the reflective film between such that at least one of the banks has a transmissive portion and a non-transmissive portion, and forming a plurality of...

20060211165 - Methods for forming phase-change memory devices: Phase-change memory devices include a phase-change material layer and a first electrode having a contact area therebetween. The contact area extends into a recess of the first electrode to provide current density concentration....

20060211166 - Methods of producing a package for semiconductor chips: The inventive method is based on the a idea of releasing a mechanical connection between the semiconductor chip and the supporting substrate during the manufacturing of the packing. The mechanical connection required for producing the electrical contacts between the semiconductor chip and the supporting substrate ensues only temporarily. As a...

20060211167 - Methods of producing a package for semiconductor chips: Disclosed are microelectronic structures based on improved design and material combinations to provide improved current capabilities per I/O. The preferred embodiment of the invention uses a combination of one or more of the following: (1) Underbump metallurgy which enhances current per I/O by increasing via diameter or by having multiple...

20060211170 - Semiconductor device and manufacturing method of the same: A semiconductor device includes an N-type semiconductor region formed in a semiconductor substrate; a p-type semiconductor region formed in a region deeper in the semiconductor substrate than the N-type semiconductor region; and a heavy metal capturing region formed in a portion of the p-type semiconductor region to capture heavy metal...

20060211168 - Semiconductor integrated circuit arrangement device and method: An arrangement device including: a photography section, which photographs a first mark and a second mark in a state in which a semiconductor integrated circuit to which the first mark is applied and a member to which the second mark is applied, which member is to be used in combination...

20060211169 - Vacuum packaged single crystal silicon device: A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of...

20060211172 - System and method to increase die stand-off height: In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of separator pedestals disposed between a first face of a die and a second face of a substrate, the substrate positioned generally parallel with,...

20060211171 - Underfill on substrate process and ultra-fine pitch, low standoff chip-to-package interconnections produced thereby: Disclosed are methods and substrates suitable for flip-chip assembly. Underfill processing used to produce the substrates provides for lead-free, eutectic solder, and other alloy reflow based flip-chip interconnects for 10-20 μm peripheral and area array I/O pitch. The methods and substrates utilize underfill materials with tailored properties along with a...

20060211173 - Package of image sensor device and formation thereof: A package of CMOS image sensor device and the formation thereof are provided. The package includes a soft layer between an image sensor device and a substrate. The image sensor device has multitudes of conductive structures distributed around a photo-sensing zone. The substrate has multitudes of conductive pads distributed around...

20060211174 - Flip-chip adaptor package for bare die: A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder...

20060211175 - Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages: A semiconductor package comprising a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die. The package further comprises a thermally-conductive material abutting the die and a heatsink abutting the thermally-conductive material, said heatsink facing a direction opposite from the lead...

20060211176 - Manufacturing method for physical quantity sensor using lead frame and bonding device therefor: A physical quantity sensor is produced using a lead frame having at least one stage for mounting a physical quantity sensor chip and a frame having leads, wherein the physical quantity sensor chip is inclined with respect to the frame. A bonding device performs wire bonding so as to electrically...

20060211177 - Structure and process for packaging rf mems and other devices: A structure and process for packaging RF MEMS and other devices employs a substrate of silicon, for example, and a cap of glass, for example, having cavities to receive the devices. MEMS or other devices are supported on an upper surface of the substrate, into which metal-filled blind vias are...

20060211178 - Fabrication of lean-free stacked capacitors: For fabricating lean-free stacked capacitors, openings are formed through layers of materials including a layer of support material displaced from a bottom of the openings. A respective first electrode is formed for a respective capacitor within each of the openings. The layer of support material is patterned to form support...

20060211179 - Field effect controllable semiconductor component with improved inverse diode and production methods therefor: The invention relates to a semiconductor component, which comprises a semiconductor body having a first and a second terminal zone of a first conduction type (n), a channel zone of a second conduction type (p), which is short circuited with the second terminal zone, a drift zone of the first...

20060211180 - Field effect transistor and method of manufacturing the same: Provided is a field effect transistor having an organic semiconductor layer, in which crystal grains having a maximum diameter of 10 μm or more account for 25% or more of the surface area of the organic semiconductor layer. The organic semiconductor layer preferably contains 7 to 200 crystal grains having...

20060211183 - Large-area nanoenabled macroelectronic substrates and uses therefor: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor...

20060211182 - Laser annealing method and laser annealing device: A laser-annealing method includes the steps of a first step of cleaning a non-monocrystal silicon film formed on a substrate, and a second step of laser-annealing the non-monocrystal silicon film in an atmosphere containing oxygen therein, wherein the first and second steps are conducted continuously without being exposed to the...

20060211181 - Method of manufacturing polysilicon thin film transistor plate and liquid crystal display including polysilicon thin film transistor plate manufactured by the method: Provided are a method of manufacturing a polysilicon thin film transistor plate, which includes leveling the surface of crystallized polysilicon having protruding grains at grain boundaries to improve the electrical characteristics of an active layer, and a liquid crystal display including a polysilicon thin film transistor plate manufactured by the...

20060211184 - Ultra-thin si channel mosfet using a self-aligned oxygen implant and damascene technique: The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located...

20060211185 - Method for manufacturing transistor in semiconductor device: Disclosed herein is a method for manufacturing a transistor in a semiconductor device, which can improve the refresh characteristics of the device. The method comprises the steps of: providing a silicon substrate having active and field regions defined thereon; performing a first channel ion implantation process into the silicon substrate;...

20060211186 - Method for forming gate in semiconductor device: Disclosed herein is a method for forming a gate in a semiconductor device, which can improve the characteristics of the device. The method comprises the steps of: providing a substrate having active and field regions; selectively etching a portion of the active region to form a trench; forming on the...

20060211187 - Mos transistor with laser-patterned metal gate, and method for making the same: A MOS transistor with a laser-patterned metal gate, and methods for its manufacture. The method generally includes forming a layer of metal-containing material on a dielectric film, wherein the dielectric film is on an electrically functional substrate comprising an inorganic semiconductor; laser patterning a metal gate from the metal-containing material...

20060211188 - Non-volatile memory structure and method of fabrication: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least...

20060211189 - Method for producing a buried semiconductor layer: A method for producing a region of increased doping in an n-doped semiconductor layer which is buried in a semiconductor body of a vertical power transistor and which is arranged between a p-doped body region facing the front side contact of the power transistor and an n-doped substrate facing the...

20060211190 - Self-aligned method for defining a semiconductor gate oxide in high voltage device area: A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit...

20060211191 - Method for manufacturing an electrical connecting element, and a connecting element: The method according to the invention is essentially characterised in that a resistance material (5)—for example nickel or a nickel alloy—is attached on a first structured conductor layer (2)—it may be of copper or a copper alloy. Subsequently, the first structured conductor layer (5) is removed again at least at...

20060211192 - Semiconductor memory device including storage nodes and resistors and method of manfacturing the same: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area;...

20060211193 - Capacitor element for solid electrolytic capacitor and method of making the same: The capacitor element includes a porous chip body and an anode wire having an end portion embedded in the chip body. The chip body includes a surface provided with a dielectric film which in turn is formed with a solid electrolyte layer thereon. Further, the solid electrolyte layer is laminated...

20060211194 - Methods of reducing floating body effect: Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into...

20060211195 - Transistor device and methods of manufacture thereof: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material...

20060211196 - Semiconductor memory device and manufacturing method thereof: A semiconductor memory device includes: a semiconductor substrate; a plurality of trench capacitors each including a capacitor dielectric film formed on a sidewall of a first trench to be formed in the semiconductor substrate, a storage node formed so as to bury the first trench via the capacitor dielectric film,...

20060211197 - Mos transistor and method of manufacturing the same: In a MOS transistor and a method of manufacturing the same, a gate structure including a gate insulating layer and a gate electrode is formed on a semiconductor substrate. A first insulating layer is formed to cover the gate structure. A second insulating layer is formed on the substrate that...

20060211201 - High coupling memory cell: A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate....

20060211200 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device has the steps of: preparing a semiconductor substrate having a structure in which first and second active regions are isolated by a field oxide; forming a first insulation film and a first film on the semiconductor substrate; exposing the first active region in...

20060211199 - Method of removing nanoclusters in a semiconductor device: A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400-900 degrees Celsius, and flowing a gas comprising halogen over the semiconductor device a temperature in a...

20060211198 - Novel structure and method to fabricate high performance mtj devices for mram applications: A method of forming a high performance MTJ in an MRAM array is disclosed. A Ta/Ru capping layer in a bottom conductor is sputter etched to remove the Ru layer and form an amorphous Ta capping layer. A key feature is a subsequent surface treatment of the Ta capping layer...

20060211202 - Forming metal silicide on silicon-containing features of a substrate: A metal suicide layer is formed on silicon-containing features of a substrate in a chamber. A metal film is sputter deposited on the substrate and a portion of the sputter deposited metal film is silicided. In the process, sputtering gas is energized by applying an electrical bias potential across the...

20060211204 - Non-volatile memory and method of fabricating the same: A method for fabricating a non-volatile memory is disclosed. First, a semiconductor device is formed in a substrate, and the top of the semiconductor device is higher than the surface of the substrate. Then, a first dielectric layer is formed on the substrate, and the first dielectric layer covers the...

20060211203 - Semiconductor device and method of manufacturing the same: Disclosed herein are a method of manufacturing a semiconductor device, which can prevent a stepped gate from leaning and increase the channel length of the device, thus contributing to an increase in the degree of integration of the device, as well as a semiconductor device manufactured thereby. The method comprises...

20060211205 - Method of manufacturing a memory device having improved erasing characteristics: In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking...

20060211206 - Electronic devices including non-volatile memory and processes for forming the same: A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By...

20060211207 - Semiconductor processing methods of forming integrated circuitry: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the...

20060211208 - methods of forming gatelines and transistor devices: The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of...

20060211209 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device includes the steps of (a) forming a first insulating film pattern, which has a first portion and a second portion separated from the first portion through a first space, above a semiconductor substrate, (b) selectively forming a first impurity diffusion layer in a...

20060211210 - Material for selective deposition and etching: A method of selectively growing silicon carbide is provided. The method includes forming a mask including tantalum carbide that masks a portion of a substrate, and epitaxially growing a crystal including silicon carbide seeded by an exposed surface of the substrate. A method of selectively etching silicon carbide is also...

20060211211 - Methods of forming pluralities of capacitors: The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes within a capacitor array area over a substrate. The capacitor electrodes comprise outer lateral sidewalls. The plurality of capacitor electrodes is supported at...

20060211212 - Capacitive element, semiconductor device, and method of manufacturing the capacitive element: A capacitive element includes a base member 10, an underlying insulating film 11 formed on the base member 10, a capacitor Q constructed by forming a lower electrode 13, a capacitor dielectric film 14, and an upper electrode 15 sequentially on the underlying insulating film 11, a lower protection insulating...

20060211214 - Method of manufacturing a semiconductor device: Even though photolithography with a diameter of 0.20 μm or less is employed, a contact hole having a tapered shape with a required width including a positioning tolerance can be formed in a narrower gap between the gate electrodes. A method forms a minute contact hole between gate electrodes of...

20060211213 - Method of manufacturing semiconductor device having step gate: Disclosed herein is a method of manufacturing a semiconductor device having a step gate, which can improve the refresh characteristics of the device. The method comprises the steps of: forming on a silicon substrate having active and field regions a first hard mask exposing the field region; etching the exposed...

20060211215 - Semiconductor device and method of manufacturing the same: Included are steps of: selectively etching a nitride film and a thermal oxide film in a thick gate insulating film forming region of a silicon substrate on which the thermal oxide film is formed with the nitride film formed on the thermal oxide film, and in which a trench with...

20060211216 - Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus: A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is etched to form an opening defined by first and second cross-sectional sidewalls in the hard mask layer. In one embodiment,...

20060211218 - Baffle wafers and randomly oriented polycrystalline silicon used therefor: Baffle wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. An all-silicon hot zone of a thermal furnace may include...

20060211217 - Methods for making large dimension, flexible piezoelectric ceramic tapes: A method for producing a detection/test tape includes depositing a material onto a surface of at least one first substrate to form a plurality of element structures. Electrodes are deposited on a surface of each of the plurality of element structures, and the element structures are bonded to a second...

20060211219 - Substrate stiffness method and resulting devices for layer transfer process: A method and structures for manufacturing multi-layered substrates. The method includes providing a donor substrate, which has a first deflection characteristic. The donor substrate has a backside, a face, a cleave region, and a thickness of material defined between the cleave region and the face. The method includes bonding the...

20060211220 - Method and device or dividing plate-like member: In a method and an apparatus for dividing a plate-like member related to the present invention, multiple substrates are obtained by forming a linear modified region on a surface of a plate-like member formed from a hard and brittle material or in the interior of the plate-like member and dividing...

20060211221 - Method for producing a strained layer on a substrate and corresponding layer structure: The invention relates to a method for producing a layer structure comprising a strained layer on a substrate. The inventive method comprises the steps of producing a defect area in a layer adjoining the layer to be strained, and relaxing at least one layer adjoining the layer to be strained....

20060211222 - Gallium nitride light emitting devices on diamond: Gallium nitride devices are formed on a diamond substrate, such as for light emitting diodes as a replacement for incandescent light bulbs and fluorescent light bulbs. In one embodiment, gallium nitride diodes (or other devices) are formed on diamond in at least two methods. A first method comprises growing gallium...

20060211223 - Plasma enhanced atomic layer deposition system and method: A method for depositing a film on a substrate using a plasma enhanced atomic layer deposition (PEALD) process includes disposing the substrate in a process chamber configured to facilitate the PEALD process, wherein the process chamber includes a substrate zone proximate the substrate and a peripheral zone proximate to a...

20060211224 - Plasma enhanced atomic layer deposition system and method: A method for depositing a film on a substrate using a plasma enhanced atomic layer deposition (PEALD) process includes disposing the substrate in a process chamber configured to facilitate the PEALD process, introducing a first process material within the process chamber and introducing a second process material within the process...

20060211225 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, includes the steps of: raising a temperature of a sapphire substrate which is included in the semiconductor device from a room temperature to a preheat temperature of 150° C. to 450° C. and keeping the preheat temperature for a first predetermined time, thereby...

20060211226 - Partial implantation method for semiconductor manufacturing: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation...

20060211227 - Schottky diode and method of manufacture: A Schottky diode capable of sustaining a voltage of greater than about 250 volts and a method for its manufacture. An epitaxial layer of N-type conductivity is disposed on a semiconductor substrate of N-type conductivity. A guard ring of P-type conductivity extends into the epitaxial layer from its surface. A...

20060211228 - A method for forming a ruthenium metal layer on a patterned substrate: A method for forming a ruthenium metal layer includes providing a patterned substrate in a process chamber of a deposition system, where the patterned substrate contains one or more vias or trenches, or combinations thereof, depositing a first ruthenium metal layer on the substrate in an atomic layer deposition process,...

20060211229 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes forming a doped polysilicon layer on a semiconductor substrate forming an oxide film for device isolation in a predetermined region of the doped polysilicon layer and the semiconductor substrate, forming an etch stop layer on the oxide film for device isolation and...

20060211230 - Laminated layer structure and method for forming the same: The invention relates to a laminated layer structure that includes a substrate and a stack of a plurality of layers of a material that includes at least two compounds A and B, wherein compound A has a crystalline structure being sufficient to allow a homo- or heteroepitaxial growth of compound...

20060211231 - Memory device and manufacturing method thereof: A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line...

20060211233 - Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure: According to an exemplary embodiment, a method for fabricating a wafer level package includes forming a polymer layer on a device wafer, where the device wafer includes at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected...

20060211232 - Method for manufacturing gold bumps: A method for manufacturing gold bumps includes providing a substrate including a patterned protective layer, which exposes at least a bonding pad, on a surface, covering a photo resist on the surface of the substrate, performing a photolithography process to pattern the photo resist for exposing a portion of the...

20060211234 - Re-assembly process for mems structures: Methods of fabricating an array of aligned microstructures on a substrate are disclosed. The microstructures may be spring contacts or other microelements. The methods disclosed include construction of an alignment substrate, alignment of die elements with the alignment substrate, and fixation of the aligned die elements to a backing substrate....

20060211235 - Semiconductor device and manufacturing process therefor: A semiconductor device 100 has a semiconductor substrate (not shown); a first interconnect 108 made of a copper-containing metal which is formed over the semiconductor substrate; a conductive first plug 114 formed over the first interconnect 108 and connected to the first interconnect 108; a Cu silicide layer 111 over...

20060211236 - Surface-coating method, production of microelectronic interconnections using said method and integrated circuits: The present invention relates to a process for coating a surface of a substrate with a seed film of a metallic material, the said surface being an electrically conductive or semiconductive surface and having recesses and/or projections. The process comprises the following: an organic film is placed on the said...

20060211237 - Method and apparatus for planarizing gap-filling material: A method an apparatus for fabricating an interconnection structure. A substrate is provided with a dielectric layer thereon. The dielectric layer comprises at least one opening therein. A gap-filling material is applied on the substrate filling the at least one opening. The gap-filling material is planarized using a template to...

20060211238 - Manufacture of semiconductor device with good contact holes: A wiring layer having an antireflection film of TiN or the like is formed on an insulating film covering a principal surface of a semiconductor substrate, and thereafter an interlayer insulating film including first to third insulating films is formed covering the wiring layer. The first and third insulating films...

20060211239 - Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules: Methods are provided for robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a polysilicon layer of a container...

20060211240 - Method of enhancing adhesion between dielectric layers: A method for enhancing adhesion between adjacent dielectric layers, particularly in the formation of trenches and vias in the layers during the fabrication of semiconductor integrated circuits on wafer substrates. The method may include providing a via dielectric layer on a substrate above a metal conductive layer in the substrate,...

20060211241 - Protective layer for barrier coating for silicon-containing substrate and process for preparing same: An article comprising a silicon-containing substrate, a steam-resistant barrier coating overlaying the substrate, wherein the steam-resistant barrier coating comprises an outer barrier layer consisting essentially of an alkaline earth aluminate/aluminosilicate, and a corrosion resistant metal silicate protective layer overlaying and adjacent to the outer barrier layer. A process is also...

20060211242 - Method of forming a plug: A method of forming a plug is provided. First, a substrate comprising at least a dielectric layer is provided, and a patterned hard mask is formed on the dielectric layer to define a position of at least a plug hole. Subsequently, the dielectric layer is etched for forming the plug...

20060211243 - Deposition system and method: A method for processing a substrate includes disposing the substrate in a deposition chamber configured to perform a deposition process and depositing a film on the substrate using the deposition process. The substrate having the film thereon is then transferred from the deposition chamber into a treatment chamber and a...

20060211244 - Clustered surface preparation for silicide and metal contacts: A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in...

20060211245 - Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect: A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening...

20060211246 - Plasma enhanced atomic layer deposition system and method: A method for depositing a film on a substrate using a plasma enhanced atomic layer deposition (PEALD) process includes disposing the substrate in a process chamber configured to facilitate the PEALD process. A first process material is introduced within the process chamber, and a second process material is introduced within...

20060211247 - Lapping of gold pads in a liquid medium for work hardening the surface of the pads: A method for work hardening gold contact pads is disclosed. The method includes providing gold contact pads, providing lapping pads, and placing the lapping pads in contact with the gold contact pads to create a contact interface. A liquid medium is then applied to the contact interface while moving the...

20060211248 - Purifier for chemical reactor: A method for purifying a gas stream in a semiconductor process system comprises cooling impurities in the gas stream. The gas stream may comprise an HCl gas having a moisture content. The moisture contacts a cold element onto which the moisture can condense....

20060211249 - Pattern transfer method and exposure system: Multilevel pattern registration is achieved by modifying the shape of an exposure pattern according to deviation of the shape of a microlithographically defined pattern due to distortion produced on a substrate. A substrate to be exposed is pretreated in a given manner. The substrate is photographed to obtain image data...

20060211250 - Scratch reduction for chemical mechanical polishing: A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish...

20060211251 - Removal of copper oxides from integrated interconnects: An apparatus and a method for photoreducing copper oxide layers from semiconductor wafers during the processes of forming interconnects in advanced IC manufacturing. The apparatus comprises a reaction chamber with a high intensity UV light source and a wafer holder in the chamber. The UV light source is made of...

20060211252 - Apparatus and method for modifying an object: A method and apparatus includes positioning a reactant on a surface in specific location and then directing an energy source from a device at the reactant such that it modifies the surface to either remove material or add material....

20060211253 - Method and apparatus for monitoring plasma conditions in an etching plasma processing facility: The present invention relates to a method and system of using downstream sensor elements for determining the plasma conditions (e.g., plasma etching end point) in a semiconductor etching facility that utilizes halogen-containing plasma and/or oxygen-containing plasma. Such sensor elements are capable of exhibiting temperature change in the presence of energetic...

20060211254 - Top patterned hardmask and method for patterning: A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing...

20060211255 - Use of multiple etching steps to reduce lateral etch undercut: In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the...

20060211256 - Porous underlayer film and underlayer film forming composition used for forming the same: There is provided an underlayer coating causing no intermixing with photoresist layer and having a high dry etching rate compared with photoresist, which is used in lithography process of manufacture of semiconductor device. Concretely, it is an underlayer coating forming composition for forming a porous underlayer coating for use in...

20060211257 - Compound, semiconductor component, and method for producing a semiconductor component comprising an organic memory material: The invention relates to a compound comprising at least one memory unit consisting of an organic memory material, especially for use in CMOS structures, said compound being characterized by a) at least one first anchor group (1) provided with a reactive group for covalently bonding to a first electrode (10),...

20060211258 - Two-dimensional patterning method, electronic device using same, and magnetic device fabricating method: A novel two-dimensional patterning method enabling two-dimension patterning without using any photosensitive material and ion milling, wherein a two-dimensional pattern is formed by destroying a blister provided on a substrate by electron or ion irradiation....

20060211259 - Silicon oxide cap over high dielectric constant films: A method for forming an integrated circuit structure on a semiconductor substrate comprises depositing a high k gate dielectric material over the substrate using an atomic layer deposition process. A silicon oxide capping layer is deposited over the gate dielectric material in a rapid thermal chemical vapor deposition process. A...

20060211260 - Pitch reduced patterns relative to photolithography features: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the...

20060211261 - Method for fabricating a semiconductor device: The present invention relates to a method for fabricating a semiconductor device. In order to provide for a high carrier mobility in an active region of the device, germanium atoms are implanted into a surface of a semiconductor substrate such that a germanium-containing layer inside the semiconductor substrate is formed....

20060211262 - Methods of laterally forming single crystalline thin film regions from seed layers: A method of forming an integrated circuit can be provided by successively laterally forming single crystalline thin film regions from an amorphous thin film using a lower single crystalline seed layer....

20060211263 - Surface-emitting type device and its manufacturing method: A surface-emitting type device includes a substrate including a first face and a second face that is tilted with respect to the first face and has a plane index different from a plane index of the first face, an emission section formed above the first face, and a rectification section...

20060211264 - Field effect transisfor, associated use, and associated production method: A vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well...

20060211265 - Method for forming a multiple layer passivation film and a device incorporating the same: A method of forming a multiple layer passivation film on a semiconductor device surface comprises placing a semiconductor device in a chemical vapor deposition reactor, introducing a nitrogen source into the reactor, introducing a carbon source into the reactor, depositing a layer of carbon nitrogen on the semiconductor device surface,...

20060211266 - Semiconductor constructions comprising particle-containing materials: The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second...

20060211267 - Silicon oxide thin-films with embedded nanocrystalline silicon: A method is provided for forming a silicon oxide (SiOx) thin-film with embedded nanocrystalline silicon (Si). The method deposits SiOx, where x is in the range of 1 to 2, overlying a substrate, using a high-density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, the SiOx thin-film is...

20060211268 - Method and apparatus for processing organosiloxane film: There is provided a method and apparatus for processing an organosiloxane film, which allow an inter-level insulating film with a low dielectric constant to be formed at a low heat process temperature. A semiconductor (10) with a coating film formed thereon is loaded into a reaction tube (2) of a...

20060211269 - Semiconductor device and its fabrication method: A fabrication method of a semiconductor device comprises the steps of forming a metal thin film Whose oxide is insulative on sidewall of a hole formed in a semiconductor substrate and forming an insulating metal oxide film by oxidizing the metal thin film....

20060211270 - Methods for improving quality of high temperature oxide (hto) formed from halogen-containing precursor and products thereof and apparatus therefor: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film...

20060211271 - Aerosol misted deposition of low dielectric organosilicate films: This invention relates to an improvement in a deposition process for producing low dielectric films having a dielectric constant of 3, preferably <2.7 and lower. The process comprises the steps: (a) forming a liquid precursor solution comprised of an organosilicon source containing both Si—O and Si—C bonds and solvent; (b)...

20060211272 - Architecture for high efficiency polymer photovoltaic cells using an optical spacer: High efficiency polymer photovoltaic cells have been fabricated using an optical spacer between the active layer and the electron-collecting electrode. Such cells exhibit approximately 50% enhancement in power conversion efficiency. The spacer layer increases the efficiency by modifying the spatial distribution of the light intensity inside the device, thereby creating...

20060211273 - Method of manufacturing an injector plate: A method of manufacturing an injector plate is disclosed. A wafer is provided and a release layer is disposed on the wafer. Then a photo resist is formed over the release layer. After photolithography processing, a plurality of plugs are formed from the photo resist. A titanium layer is sputtered...

20060205095 - Method of producing barium-titanium-based oxide glass using containerless solidification process: Disclosed is a method of producing a barium-titanium-based ferroelectric glass using a containerless solidification process, such as an electrostatic levitation process or a gas levitation process, which comprises the steps of levitating a sample 1 of a barium-titanium-based compound by a levitating force of compressed air, heating the sample up...

20060205096 - Method for manufacturing nonlinear optical element: An insulating film is formed on a first principal surface of the substrate. A periodic structure formation zone corresponding to a periodic structure formation region to be formed in the substrate, a plurality of polarization inversion zones corresponding to polarization inversion regions to be formed in a periodic arrangement in...

20060205097 - Methods of manufacturing a crystal-oriented ceramic and of manufacturing a ceramic laminate: A method for manufacturing a crystal-oriented ceramic comprising a sheet-making step, a crystallization-promoting layer-forming step and a calcining step is provided. At the sheet-making step, a green sheet 1 is made. At the crystallization-promoting layer-forming step, a crystallization-promoting layer 15 containing crystallization-promoting material particles 151 is formed so as to...

20060205098 - Method of determining n-well scattering effects on fets: A process is provided for determining the effects of scattering from the edge of a resist during a doping process. Edges of a resist which has been patterned to create an n-well are simulated and individually stepped across a predetermined region in predetermined step sizes. The step sizes may vary...

20060205099 - Die testing using top surface test pads: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within...

20060205100 - Method and apparatus for cleaning and sealing display packages: A method and apparatus for cleaning and sealing components of a display utilizes continuous isolation of the components between the cleaning step and the sealing step. This limits exposure of the components to contaminants and isolates the components from oxidizing agents which can cause an oxide to form on the...

20060205101 - Laser irradiation device, patterning method and method of fabricating organic light emitting display (oled) using the patterning method: In a laser irradiation device, a patterning method and a method of fabricating an Organic Light Emitting Display (OLED) using the same. The laser irradiation device includes a light source, a mask, a projection lens, and a Fresnel lens formed at a predetermined portion of the mask to change an...

20060205102 - Liquid crystal displays: An active plate for a liquid crystal display has an insulating layer (76) arranged as a plurality of columns, each insulating layer column overlapping the pixel electrodes (12) of two adjacent columns of pixels. An opaque conductor layer is formed over the substrate and patterned to define column conductors (34)...

20060205103 - Methods for repairing and manufacturing display device: For inhibiting generation of pixels that could not be displayed in a line in a display screen of an electron emission display comprising the pixels each provided with an electron source in which a first electrode at a signal line side and a second electrode at a scanning line side...

20060205104 - Semiconductor light-emitting device and a method for manufacturing the same: The present invention is to provide a light-emitting device, a laser diode, formed without using the mechanical cleavage, and a process for manufacturing the device. The process comprises, after stacking semiconductor layers of the first cladding layer, the active layer, and the second cladding layer, a forming of a groove...

20060205105 - Electronic device and it's manufacturing method: A microelectronic device and a method for producing the device can overcome the disadvantages of known electronic devices composed of carbon molecules, and can deliver performance superior to the known devices. An insulated-gate field-effect transistor includes a multi-walled carbon nanotube (10) having an outer semiconductive carbon nanotube layer (1) and...

20060205106 - Integrated micro electro-mechanical system and manufacturing method thereof: In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a...

20060205107 - Solid-state imaging device, manufacturing method of solid-state imaging device, and camera employing same: A solid-state imaging device includes a color filter that selectively transmits incoming light. The color filter includes two λ/4 multilayer films, and an insulation layer sandwiched between the two λ/4 multilayer films. Here, each of the λ/4 multilayer films is constituted by a plurality of dielectric layers, and the optical...

20060205108 - Method for making tapered opening for programmable resistance memory element: A method for making a tapered opening. The defined tapered opening is useful for the fabrication of programmable resistance memory elements. The programmable resistance memory material may be a chalcogenide....

20060205109 - Method and apparatus for fabricating nanoscale structures: An apparatus comprises a scanning electron microscope (SEM) (1) positioned over a manipulation chamber (2) which houses a sample holder (3). The walls of the manipulation chamber (2) support two probes (4, 4a) and the sample holder (3) is able to hold a sample (5), such as carbon nanotubes (10a)...

20060205110 - Method for manufacturing an electrolyte material layer in semiconductor memory devices: A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a...

20060205111 - Method for producing chip stacks and chip stacks formed by integrated devices: The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated structure on a single substrate, an area of the first integrated structure and an area of the second integrated structure adjoining a...

20060205112 - Semiconductor package fabrication: A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module....

20060205113 - Radio frequency identification (rfid) tag lamination process: A method of constructing an RFID unit can include using a protective layer to hold an integrated circuit chip module to a substrate layer with an antenna unit while a conductive adhesive has not yet fully set....

20060205114 - Packing material for wafer: A packing material for wafer packed up by stacking up a plurality of wafers, includes: a protective sheet protecting an optical surface being glued to an entire upper surface of the wafer; a dicing tape being concurrently glued to an entire lower surface of the wafer; and a first buffer...

20060205116 - Methods for packaging microfeature devices and microfeature devices formed by such methods: Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method comprises providing a workpiece including a substrate having a plurality of microelectronic dies on and/or in the substrate. The...

20060205115 - Radio frequency identification (rfid) tag lamination process using liner: A method of constructing an RFID unit can include using a protective layer to hold an integrated circuit chip module to a substrate layer with an antenna unit while a conductive adhesive has not yet fully set....

20060205117 - Solder masks used in encapsulation, assemblies including the solar mask, and methods: A carrier (e.g., a carrier substrate, such as a circuit board, etc.) may be modified to include a solder mask on a surface thereof. The solder mask, which may extend to or beyond an edge of the carrier, includes an opening that exposes at least one contact area of the...

20060205118 - Chip heat dissipation structure and manufacturing method: This invention discloses a manufacturing method and a structure for a chip heat dissipation. This heat dissipation structure includes a bottom plate of circuit structure, a die of central processing unit and a cap. The cover is often used in conducting the waste heat generated from the chip. The cover...

20060205119 - Method for manufacturing a semiconductor package with a laminated chip cavity: A method for manufacturing a semiconductor package with a laminated chip cavity is disclosed. A board and a metal foil having a layer of adhesive resin are provided. The metal foil is laminated with the board to make the adhesive resin be attached to the board. Next, a through opening...

20060205120 - Flash memory cell arrays having dual control gates per memory cell charge storage element: A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory...

20060205121 - Method and system for high-speed, precise micromachining an array of devices: A method and system for high-speed, precise micromachining an array of devices are disclosed wherein improved process throughput and accuracy, such as resistor trimming accuracy, are provided. The number of resistance measurements are limited by using non-measurement cuts, using non-sequential collinear cutting, using spot fan-out parallel cutting, and using a...

20060205122 - Method for fabricating a field stop zone: In a method for fabricating a field stop zone in a semiconductor body of a semiconductor component. According to the method, the semiconductor body is irradiated with protons, and the irradiated semiconductor body is subjected to a heat treatment process. Prior to the irradiation process, the semiconductor body is subjected...

20060205124 - Bottom-gate sonos-type cell having a silicide gate: A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cells. The fabrication methods described avoid photolithography over topography and difficult stack...

20060205123 - Methods for metal plating of gate conductors and semiconductors formed thereby: A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one or more of the activated sites....

20060205125 - Tft substrate and display device having the same: A TFT substrate includes a base substrate, a gate wiring formed on the base substrate, a gate insulation layer, an activation layer, an oxidation-blocking layer, a data wiring, a protection layer and a pixel electrode. The gate wiring includes a gate line and a gate electrode. The gate insulation layer...

20060205126 - Method for fabricating metal oxide semiconductor with lightly doped drain: A method for fabricating metal oxide semiconductor with lightly doped drain. In the method, the gate electrode, the LDD of the n-type MOS TFT, and the source/drain electrode of the p-type MOS TFT are defined simultaneously in one photolithography step. The contact holes and the source/drain electrode of the n-type...

20060205127 - Method of manufacturing photoreceiver: Disclosed is a method of manufacturing a photoreceiver, including sequentially laminating a buffer layer, a channel layer, a barrier layer, and a cap layer on a substrate; forming a mesa for HEMT and MSM PD by removing the buffer layer, the channel layer, the barrier layer, and the cap layer...

20060205128 - Integrated circuits and methods of forming a field effect transistor: Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and...

20060205131 - Method for fabricating semiconductor device: An underlying insulting film of silicon oxide, a gate insulating film of hafnium oxide, a gate electrode of polysilicon, and side walls of silicon oxide are formed above an element formation region of a semiconductor substrate. In the upper portion of the element formation region of the semiconductor substrate, source...

20060205129 - Method for manufacturing semiconductor device: In a gas containing a fluorine atom in the molecule, etching of a SiN film is performed isotropically; therefore, the width of a sidewall gets smaller and it is difficult to widen the width of an LDD region. A silicon nitride film is formed over a gate electrode, a hydrogen...

20060205132 - Scalable integrated logic and non-volatile memory: A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers....

20060205130 - Semiconductor integrated circuit device and its manufacturing method: A semiconductor integrated circuit device has a plurality of rows of pillars, each row being composed of semiconductor pillars and insulator pillars alternately arranged in one direction with no gap therebetween, a plurality of nonvolatile memory elements provided individually in said plurality of semiconductor pillars, said plurality of nonvolatile memory...

20060205134 - Method for manufacturing a semiconductor device and method for regulating speed of forming an insulating film: A method for manufacturing a semiconductor device including sidewall insulating films with different thicknesses includes the steps of (a) selectively forming first and second gate electrode structures on first and second active regions of a silicon substrate respectively, (b) forming a first silicon oxide film on the first and second...

20060205133 - Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same: A method for forming transistor gates having two different work functions comprises forming a first polysilicon layer which may be doped with n-type dopants. The first polysilicon layer comprises an inhibitor material at select locations which retards silicide formation. A second polysilicon layer is formed over the first polysilicon layer....

20060205135 - Silicon rich barrier layers for integrated circuit devices: Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and...

20060205136 - Method of making a floating gate non-volatile mos semiconductor memory device with improved capacitive coupling: A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically...

20060205137 - Methods and apparatus with silicide on conductive structures: Exemplary embodiments of the invention provide pixel circuits having transistors with silicide on top of their gate stacks. In the exemplary embodiments, silicide forming material does not contaminate other components such as the photoconversion devices of an imager integrated circuit (IC). The photoconversion devices are blocked during silicide formation and...

20060205138 - Method to selectively form sige p type electrode and polysilicon n type electrode through planarization: A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer...

20060205139 - Method for forming plural kinds of wells on a single semiconductor substrate: A method is provided for forming plural kinds of wells on a single semiconductor substrate with an improved alignment accuracy and obviating the generation of step height between the wells. The method includes forming a selective etching film on the semiconductor substrate, forming openings on the selective etching film overlying...

20060205140 - Integrated circuit capacitor having antireflective dielectric: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that...

20060205141 - Method of fabricating semiconductor devices having buried contact plugs: A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming...

20060205142 - Methods of forming semiconductor constructions: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is...

20060205143 - Dram with high k dielectric storage capacitor and method of making the same: A memory cell is fabricated by forming a first capacitor electrode including silicon. A metal layer is formed in physical contact with the first capacitor electrode. The metal layer is formed from a material having a high affinity for oxygen and a melting point above about 1000° C. A layer...

20060205144 - Trench capacitor and method for preparing the same: The present invention discloses a trench capacitor formed in a trench in a semiconductor substrate. The trench capacitor comprises a bottom electrode positioned on a lower outer surface of the trench, a dielectric layer positioned on an inner surface of the bottom electrode, a top electrode positioned on the dielectric...

20060205145 - Front-end processing of nickel plated bond pads: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication....

20060205146 - Low resistance peripheral contacts while maintaining dram array integrity: A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium...

20060205147 - Self-aligned buried contact pair: A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls...

20060205153 - A semiconductor device and a method of manufacturing thereof: A method for manufacturing a semiconductor device includes the steps of forming a first insulating film over a semiconductor substrate, forming a laminated body on the first insulating film that includes a polysilicon film and a metal film that is separated from the insulating film by means of the polysilicon...

20060205156 - Isolation structure for a memory cell using al2o3 dielectric: The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure, for example a DRAM memory cell. An aluminum oxide (Al2O3) is used as a gate dielectric, rather than a conventional...

20060205154 - Manufacturing method of an non-volatile memory structure: A non-volatile memory including a substrate, a plurality of gate structures, a plurality of select gate structures, spacers and source region/drain region is provided. Each gate structure on the substrate further includes a bottom dielectric layer, an electron trapping layer, an upper dielectric layer, a control gate and a cap...

20060205155 - Method of fabricating a non-volatile memory element: An interpoly insulating film is modified in the film quality, while preventing generation of trap sites. A floating gate 101 is provided on a channel-forming region in the vicinity of the surface of a silicon substrate 112, an interpoly insulating film 134 is provided so as to contact with the...

20060205149 - Method of fabricating flash memory device: A method of fabricating a flash memory device is disclosed which includes sequentially stacking a tunnel oxide film, a first conductive film, a dielectric film, a second conductive film and a metal silicide film on a semiconductor substrate, and patterning the metal silicide film, the second conductive film, the dielectric...

20060205150 - Method of fabricating flash memory device: A method of fabricating a flash memory devices disclosed wherein, upon formation of sidewall oxide films, a regrown thickness of a screen oxide film is controlled. The width of an element isolation film is reduced by means of an etch process for removing the re-growth oxide film. This allows a...

20060205151 - Method of fabricating flash memory device: A method of fabricating a flash memory device is disclosed wherein, electrode spacers are formed on sides of self-aligned floating gates having a negative slope. Thus, upon etching of a stack gate after an interlayer dielectric film and a control gate are formed, a stringer of a control gate, which...

20060205152 - Method of fabricating flash memory device: The present invention relates to a method of fabricating a flash memory device. The width of an active region (line) is reduced, but the width of a field region (space) is extended. An overlay margin between the floating gates and the active region depending upon increase in the level of...

20060205148 - Semiconductor memory: A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element...

20060205157 - Non-volatile memory and method for fabricating the same: A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive...

20060205158 - Method of forming floating gate electrode in flash memory device: A method of forming a floating gate electrode in a flash memory device. The method includes forming an isolation film in an inactive region so that a step with a predetermined thickness can be generated between an active region and the inactive region, which are defined in a semiconductor substrate,...

20060205159 - Method of forming gate flash memory device: A gate formation method of flash memory devices includes performing a nitrogen anneal process in a Rapid Thermal Processing (RTP) apparatus to crystallized a tungsten silicide film used as a control gate electrode, which results in reduced sheet resistance (Rs) of a control gate electrode. A Rapid Thermal Oxidization (RTO)...

20060205160 - Method of forming gate electrode pattern in semiconductor device: A method of forming a NAND flash memory device includes forming a plurality of first gate electrode patterns having first and second polysilicon layers, a dielectric layer provided between the first and second polysilicon layers, and a sacrificial layer overlying the second polysilicon layer, the first gate electrode patterns defining...

20060205161 - Method for producing a semiconductor device and resulting device: The present invention is related to a method of producing a semiconductor device and the resulting device. The method is suitable in the first place for producing high power devices, such as High Electron Mobility Transistors (HEMT), in particular HEMT-devices with multiples source-gate-drain groups or multiple base bipolar transistors. According...

20060205162 - Method for manufacturing semiconductor device with recess channels and asymmetrical junctions: Disclosed is a method for manufacturing a semiconductor device having recess channels and asymmetrical junctions. The method includes forming an impurity region for adjusting the threshold voltage by implanting ions into a bit line junction of a semiconductor substrate, which includes storage nodes junction, the bit line junction, and channel...

20060205163 - Method of fabricating a non-volatile memory: A method of fabricating a non-volatile memory is provided. A tunneling dielectric layer, a charge trapping layer and a barrier dielectric layer are sequentially formed over a substrate. Then, a pad conductive layer with openings is formed over the barrier dielectric. Thereafter, the barrier dielectric layer, the charge trapping layer,...

20060205164 - Method of forming a shallow trench isolation structure: A method and system for isolation trenches includes forming isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and...

20060205165 - Polysilazane perhydride solution and method of manufacturing a semiconductor device using the same: Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a...

20060205166 - Semiconductor device and method for manufacturing the same: A method for manufacturing a semiconductor device includes the steps of (a) forming a gate insulating film above a semiconductor substrate, (b) forming a first conductive film on the gate insulating film, (c) forming a first insulating film pattern on the first conductive film, (d) selectively forming a first impurity...

20060205167 - Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A...

20060205168 - Method of fabricating a lateral double-diffused mosfet (ldmos) transistor: A method of monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow, is disclosed....

20060205169 - Method for manufacturing a semiconductor device using a sidewall spacer etchback: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing...

20060205170 - Methods of forming self-healing metal-insulator-metal (mim) structures and related devices: Methods of forming metal-insulator-metal structures may include providing a first conductive electrode on a substrate, forming a dielectric layer on the first conductive electrode, and forming a second conductive electrode on the dielectric layer so that the dielectric layer is between the first and second conductive electrodes. In addition, a...

20060205171 - Chip resistor and method for manufacturing same: A chip resistor (R1) includes a resistor element (1) having a first surface (1a) and a second surface (1b) opposite to the first surface. Two main electrodes (21), spaced from each other, are provided on the first surface (1a), while two auxiliary electrodes (22), spaced from each other, are provided...

20060205172 - Perfluoroether acyl oligothiophene compounds: Semiconductor devices are described that include a semiconductor layer that comprises a perfluoroether acyl oligothiophene compound, preferably an α,ω-bis-perfluoroether acyl oligothiophene compound. Additionally, methods of making semiconductor devices are described that include depositing a semiconductor layer that contains a perfluoroether acyl oligothiophene compound, preferably an α,ω-bis(2-perfluoroether acyl oligothiophene compound....

20060205173 - Methods for forming isolation films: A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a...

20060205174 - Method for manufacturing a superjunction device with wide mesas: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the...

20060205175 - Methods of forming silicon dioxide layers, and methods of forming trench isolation regions: A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and while depositing, etching the deposited silicon dioxide with...

20060205178 - Creation of high mobility channels in thin-body soi devices: A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film=and a second layer of strained film. The SOI wafer has a...

20060205176 - Met