Semiconductor device manufacturing: process inventions 08/06

20060194347 - Method for fabricating superlattice semiconductor structure using chemical vapor diposition: The invention provides a method for fabricating a superlattice semiconductor structure capable of achieving excellent interfacial properties and uniformity. For the superlattice semiconductor structure according to the invention, a substrate is mounted on a susceptor within a process chamber. First and second source gases are supplied simultaneously to two different...

20060194348 - Ferroelectric and high dielectric constant integrated circuit capacitors with three-dimensional orientation for high-density memories, and method of making the same: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2...

20060194350 - Control system: A scientific experiment control system includes a main controller for high-level control, an experimental manager for lower-level control of scientific experiments, and a roll-up engine for automatically propagating modifications (or “changes”) within the system to ensure consistency across the system and instruments which are linked to it in an automatic...

20060194349 - Method of reworking a semiconductor structure: The present invention allows correcting malfunctions occurring in the formation of a cap layer on an electrical element in a semiconductor substrate. It is detected whether a malfunction occurred in the formation of the cap layer. If a malfunction in the formation of the cap layer was detected, a rework...

20060194351 - Methods and apparatus for configuring plasma cluster tools: A method for configuring a specific plasma cluster tool having a plurality of modules. The method includes providing a set of module option definition files, the set of module option definition files containing generic configuration definitions for generic plasma cluster tools. The method further includes providing a set of tool-specific...

20060194353 - Method and circuit for the detection of solder-joint failures in a digital electronic package: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a...

20060194352 - Semiconductor device test system: An apparatus for mitigating condensation formation on a device interface board during low-temperature semiconductor device testing includes a nozzle. The nozzle includes an input orifice for receiving gas from a gas source and at least one output orifice for discharging gas from the nozzle against a surface of the device...

20060194354 - Laser irradiation method and apparatus for forming a polycrystalline silicon film: A method for changing an amorphous silicon film to a poly-crystalline silicon film includes the steps of irradiating an elongate pulse laser beam onto the silicon film while scanning in the direction normal to the major axis of the elongate pulse laser beam, to form a plurality of irradiated areas,...

20060194355 - Laser diode bar provided with a parallel connected diode for bridging said laser siode bar in case of failure: A laser diode component comprising a laser diode bar on which a specific operating voltage is impressed during operation and with which a bridging element is connected in parallel, which bridging element is in a current-blocking state when the specific operating voltage is impressed on the associated laser diode bar...

20060194356 - Method for manufacturing multi-wavelength semiconductor laser device: The present invention provides a method for forming a multi-wavelength semiconductor laser device. The method comprises sequentially forming an AlGaAs-based epitaxial layer for a first semiconductor laser diode and an etching stop layer composed of AlxGayIn(1-x-y)P (0≦x≦1, 0≦y≦1) on a substrate and sequentially growing an n-type GaAs flattening buffer layer...

20060194357 - High-density germanium-on-insulator photodiode array: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to...

20060194358 - Tunable semiconductor laser and method thereof: A tunable semiconductor laser including a Fabry-Perot filter and an electrode array is disclosed. The propagation direction of the light beam in the cavity can be consecutively shifted applying electric field or current to the electrode and tuning can consecutively performed over the wide wavelength band by the consecutive shift...

20060194359 - Horizontal emitting, vertical emitting, beam shaped, distributed feedback (dfb) lasers by growth over a patterned substrate: A structure using integrated optical elements is comprised of a substrate, a buffer layer grown on the substrate, one or more patterned layers formed on the buffer layer and one or more active layers formed on or between the patterned layers, for instance by Lateral Epitaxial Overgrowth (LEO), and including...

20060194360 - Method for manufacturing nitride-base semiconductor element and nitride-base semiconductor element: A principal surface at one side of a support substrate has thereon an adjustment layer made of material having a higher thermal expansion coefficient than that of the support substrate. Then, a nitride-base semiconductor element layer and the support substrate on a growth substrate are joined via an adhesion layer....

20060194361 - Mems packaging using a non-silicon substrate for encapsulation and interconnection: A MEMS die is bonded to a cap to form a MEMS device. The cap is non-silicon and has an electrical via extending from one side of the cap to another side of the cap. In one embodiment, a plurality of caps is wafer bonded to a plurality of MEMS...

20060194362 - Sensor including lead frame and method of forming sensor including lead frame: A sensor includes a plurality of leads that have bottom surfaces extending in a first plane, a stage that extends in a second plane that tilts from the first plane, a sensor chip that is supported on the stage, a modified connection lead structure that supports the stage, and at...

20060194363 - Method of manufacturing a flexible electronic device and flexible device: An electrical element, such as a thin-film transistor, is defined on a flexible substrate, in that the substrate is attached to a carrier by an adhesive layer, and is delaminated after definition of the transistor. This is for instance due to illumination by UV-radiation. An opaque coating is provided to...

20060194364 - Micro-component packaging process and set of micro-components resulting from this process: A process for packaging a plurality of micro-components made on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a cover plate; depositing a metal layer on a face of the cover plate or on a face of the wafer; covering the...

20060194365 - Microelectronic assemblies having compliancy: A microelectronic assembly includes a microelectronic element, such as a semiconductor wafer or semiconductor chip, having a first surface and contacts accessible at the first surface, and a compliant layer overlying the first surface of the microelectronic element, the compliant layer having openings in substantial alignment with the contacts of...

20060194366 - Multi-chip ball grid array package: A multi-chip BGA package has two or more rerouted chips, each of which has one or more electrode plates. The electrode plate is coplanar with rerouting lines on the rerouted chip and may act as a decoupling capacitor, reducing simultaneous switching noise from fluctuations in power voltage, without causing an...

20060194367 - Semiconductor device production method and semiconductor device: A semiconductor device production method including: the step of forming a stopper mask layer of a first metal on a semiconductor substrate, the stopper mask layer having an opening at a predetermined position thereof; the metal supplying step of supplying a second metal into the opening of the stopper mask...

20060194368 - Thin film translator array panel and a method for manufacturing the panel: A gate wire including a gate line and a gate electrode is formed on a substrate and a gate insulating layer is formed on the substrate. A semiconductor pattern and an etching assistant pattern are formed on the gate insulating layer and a source/drain conductor pattern and an etching assistant...

20060194369 - Carrier for substrate film: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments...

20060194371 - Method of manufacturing semiconductor device: It is an object of the present invention to provide a technology to manufacture a semiconductor sheet or a semiconductor chip with a high yield using a circuit having a thin film transistor. A manufacturing method for a semiconductor device comprises: attaching a flexible base material to an element layer...

20060194370 - Radio frequency module and fabrication method thereof: The present invention relates to a RF module and a fabrication method thereof, wherein the packaging steps of a SAW component and a module is carried out simultaneously, thereby simplifying the fabrication process and reducing the size of the module. In the invention, a chip component is mounted on a...

20060194372 - Mold cleaning sheet and manufacturing method of a semiconductor device using the same: A cleaning sheet with frame for cleaning a molding die comprising a cleaning heat main body that covers the entire mating surface of a molding die and a reinforcing frame which can be disposed along the peripheral edge to the outside of the plural cavities of the mating surface of...

20060194373 - Methods for assembling semiconductor devices and interposers: A method for assembling one or more semiconductor devices with an interposer includes positioning the one or more semiconductor devices within a receptacle that extends through the interposer, on a retention element that extends over at least a portion of the receptacle. Material may be introduced between at least a...

20060194374 - Method of fabricating thin film transistor substrate for display device: A method of fabricating a thin film transistor substrate for a display device is provided. The method includes the steps of forming a gate line and a gate electrode connected to the gate line; forming a gate insulating film disposed covering the gate line and the gate electrode; forming a...

20060194375 - Semiconductor device and method of manufacturing thereof: To provide a liquid crystal display device having high quality display with a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load....

20060194376 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film...

20060194377 - Laser process: m

20060194378 - Semiconductor device and method of fabricating the same: According to the present invention, there is provided a semiconductor device having: first and second fins formed on a semiconductor substrate to oppose each other, and made of a semiconductor layer; an active region which is formed on the semiconductor substrate so as to be connected to the first and...

20060194382 - Design and simulation methods for electrostatic protection circuits: A physical analysis (S2) of the elements used in an ESD protection circuit is performed; parameters of the elements that have a comparatively large effect on ESD protection characteristics are extracted as key parameters (S4); and a mixed-mode device-circuit simulation of the ESD protection circuit is performed, using the key...

20060194379 - Field effect transistor and method for manufacturing same: A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and...

20060194381 - Gate structure and a transistor having asymmetric spacer elements and methods of forming the same: Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a...

20060194380 - Method for fabricating asymmetric semiconductor device: A method for fabricating an asymmetric semiconductor device is provided. A substrate formed with at least one base structure of MOSFET thereon is provided, wherein the base structure includes a gate over the substrate and a source extension and a drain extension in the substrate beside the gate. The base...

20060194383 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a second semiconductor layer formed on a side surface of a first semiconductor by epitaxial growth; a gate electrode disposed on a film formation surface of the second semiconductor layer; a source layer formed on the semiconductor layer and disposed on one side of the gate...

20060194384 - Semiconductor device with multiple semiconductor layers: A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic...

20060194385 - Method of fabricating flash memory device: A method of fabricating flash memory devices includes the steps of forming a stop nitride film and an oxide film on a semiconductor substrate having a predetermined structure formed therein, forming trenches in the oxide film and the stop nitride film, forming barrier oxide films on lateral faces of the...

20060194387 - High performance transistors with sige strain: A preferred embodiment of the invention comprises a semiconductor device having stress in the source/drain channel. The device comprises a substrate having a lattice constant greater than or equal to silicon and a first layer on the substrate, wherein the first layer has a lattice constant greater than the substrate....

20060194386 - Method and apparatus for supporting port aggregation of serial attached scsi wide ports via virtual ports: An SAS RAID adapter comprises an input-output processor (IOP) and at least two SAS input-output controllers (IOCs). Wherein SAS links coupled to each of the IOCs form “virtual ports” in order to increase performance and maintain availability. The virtual ports across the at least two IOCs have wide port SAS...

20060194389 - Method for fabricating flash memory device: A method is provided for fabricating a flash memory device, preventing particles from spreading around edges of a wafer while pre-cleaning a tunnel oxide film by removing particles at the edges of the wafer. Accordingly, it is able to overcome the problems arising from quality deterioration of the tunnel oxide...

20060194388 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor memory device comprises the steps of: preparing a semiconductor substrate having a gate insulation film and a gate electrode, the gate insulation film being formed on a predetermined active region in the semiconductor substrate, and the gate electrode being formed on the gate insulation...

20060194390 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an interlayer insulation film including an air gap between portions of adjacent wiring layers or isolation pattern layers or both that are distanced from each other by thinning a layered structure of each of the wiring layers or the isolation pattern layers or both selectively from...

20060194392 - Mis-type semiconductor device: A MIS-type semiconductor device has reduced ON-resistance by securing an overlapping area between the gate electrode and the drift region, and has low switching losses by reducing the feedback capacitance. The MIS-type semiconductor device includes a p-type base region, an n-type drift region, a p+-type stopper region in the base...

20060194391 - Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process: A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of...

20060194394 - Mask rom, method for fabricating the same, and method for coding the same: A mask ROM, a method for fabricating the same and a method for coding the same are disclosed. The method for forming the mask ROM maximizes packing density and integration of a device. The mask ROM includes a semiconductor substrate having a device isolation region and an active region, BN...

20060194393 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate having first and second element forming regions, the first and second element forming regions divided by an element separating insulation film; forming a first gate insulation film on the semiconductor substrate; forming a predetermined film...

20060194395 - Metal hard mask method and structure for strained silicon mos transistors: A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the...

20060194396 - Method for depositing a metal gate on a high-k dielectric film and improving high-k dielectric film and metal gate interface, and a substrate treating system: A method to improve a high-k dielectric film and metal gate interface in the fabrication of a MOSFET by depositing a metal gate on a high-k dielectric, the method includes annealing a substrate with a high-k dielectric film deposited thereon in a thermal annealing module and depositing a metal gate...

20060194397 - Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates: In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is...

20060194398 - Semiconductor device and its manufacturing method: A semiconductor device which has a source/drain extension structure suitable for miniaturization, is provided a semiconductor device comprising a gate electrode formed on a semiconductor substrate of a first conductivity type via a gate insulator, a semiconductor region of a second conductivity type comprising first and second semiconductor areas, wherein...

20060194399 - Silicide gate transistors and method of manufacture: A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried...

20060194400 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device includes forming a first semiconductor layer on a front side of the semiconductor substrate. Additional semiconductor layers may be formed on a font side of the first semiconductor layer. The substrate is subsequently removed. In some embodiments, one or more additional semiconductor layers...

20060194401 - Method for manufacturing a semiconductor device having an alignment feature formed using an n-type dopant and a wet oxidation process: The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further...

20060194402 - Chip resistor: The invention relates to a method of making a chip resistor using a material substrate for which are set a plurality of first cutting lines extending in a first direction and a plurality of second cutting lines extending in a second direction perpendicular to the first direction. The method includes...

20060194403 - Pcmo thin film with controlled resistance characteristics: PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1<x<0.6; in response to the selection of x, varying the ratio of Mn and O ions as follows: O2− (3±20%); Mn3+ ((1−x)±20%);...

20060194404 - Method and system for fabricating and cleaning free-standing nanostructures: Systems and methods include introducing a semiconductor wafer into a process chamber. An etching chemistry is injected into the process chamber to etch a patterned layer and to release free-standing nanostructures on the semiconductor wafer. The etching chemistry includes a supercritical or liquid carbon dioxide fluid and an etching solution....

20060194405 - Semiconductor device and method of fabricating the same: A semiconductor device has an element isolating region formed of an insulating film having etching rates different from each other in a side close to an inside wall and a center side of a trench formed on a semiconductor substrate, and a selective epitaxial layer formed in both sides of...

20060194407 - Application of impressed-current cathodic protection to prevent metal corrosion and oxidation: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to...

20060194406 - Semiconductor wafer positioning method, and apparatus using the same: The intensity of light of a predetermined wavelength corresponding to the type of a protective tape joined to the surface of a semiconductor wafer is adjusted by a controller, and a holding stage for holding the semiconductor wafer is scanned rotationally. At this time, at a V notch portion for...

20060194408 - Process and circuit for manufacturing electronic semiconductor devices in a soi substrate: A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region...

20060194409 - Process for manufacturing a soi wafer with improved gettering capability: Manufacturing of a wafer made of semiconductor material on insulator including the steps of: providing a composite wafer having a substrate, an insulating layer and an active layer of semiconductor material, arranged on top of one another; forming at least one deep trench within the active layer of the composite...

20060194410 - Semiconductor device with cavity and method of manufacture thereof: A semiconductor device is provided with a substrate with a cavity inside, the substrate including a device formation area located above the cavity, a plurality of trenches formed in the substrate to communicate with the cavity and surround the device formation area, and an oxide film formed around each of...

20060194411 - Method to fabricate completely isolated silicon regions: The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer in areas designated as active regions. The nitrogen...

20060194414 - Low temperature fusion bonding with high surface energy using a wet chemical treatment: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been...

20060194412 - Method and device for sticking tape: Tapes are attached to a long support film, and the support film is attached to frame member at positions where the tape to be stuck to an adherend such as a semiconductor wafer, is included in a frame of a frame member. The support film is pressed to stick the...

20060194413 - Method of bonding substrates: A method of bonding a first substrate to a second substrate is provided. The method comprises the steps of: (a) providing a first substrate having a plurality of etched trenches defined in a first bonding surface; (b) providing a second substrate having a second bonding surface; and (c) bonding the...

20060194415 - Germanium infrared sensor for cmos imagers: A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+ silicon layer, forming a silicon-germanium interface; cyclic annealing; and implanting hydrogen ions...

20060194416 - Method for producing single crystal ingot from which semiconductor wafer is sliced: A method of manufacturing single-crystal semiconductor blocks is characterized in that a plurality of single-crystal semiconductor blocks of a relatively small diameter desired by users are cut out from a single-crystal semiconductor block of a relatively large diameter. With this method, there can also be obtained a secondary effect that...

20060194417 - Polycrystalline sillicon substrate: A polycrystalline silicon substrate for a solar cell formed by growing a high purity polycrystalline silicon layer on a surface of a base obtained by slicing a polycrystalline silicon ingot obtained by melting metallurgical grade silicon and performing one-direction solidification, wherein one-direction solidification is performed on a melt prepared by...

20060194418 - Smooth surface liquid phase epitaxial germanium: A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region....

20060194419 - Crystalline-si-layer-bearing substrate and its production method, and crystalline si device: A method for producing a substrate having a crystalline Si layer comprising the steps of forming an amorphous Si layer on a plastic substrate, and irradiating the amorphous Si layer with a laser beam to crystallize the amorphous Si, wherein the plastic substrate has light transmittance of 30 to 100%...

20060194420 - Multilayer film: This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film....

20060194421 - Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator cmos devices: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs...

20060194422 - Abrupt \"delta-like\" doping in si and sige films by uhv-cvd: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40...

20060194423 - Method of making a nitrided gate dielectric: A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed....

20060194424 - Microfeature devices and methods for manufacturing microfeature devices: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a...

20060194425 - Anisotropic conductive adhesive, electrode connection structure and method using the adhesive: Anisotropic conductive adhesive has conductive particles dispersed in adhesive and includes hard particles having conductivity, a resin layer that coats the hard particles and a conductive layer that coats the resin layer. A connection structure electrically connects electrodes to each other with the anisotropic conductive adhesive. A connection method includes...

20060194426 - Method for manufacturing dual damascene structure with a trench formed first: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer...

20060194428 - Control of wafer warpage during backend processing: A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer,...

20060194427 - Interconnecting process and method for fabricating complex dielectric barrier layer: An interconnecting process is described. First, a dielectric layer with a plurality of openings is provided. Then, a metallic layer is formed to fill up the openings. A first dielectric barrier layer is formed to cover the dielectric layer and the metallic layer. Thereafter, a second dielectric barrier layer is...

20060194429 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions...

20060194430 - Metal interconnect structure and method: In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric layer. A liner is formed over the dual damascene structure. The liner is selectively removed from above the...

20060194431 - Technique for metal deposition by electroless plating using an activation scheme including a substrate heating process: In an enhanced technique for electroless metal deposition, the substrate is heated to or above the operating temperature for the specific plating solution, while the plating solution may be maintained at a non-critical low temperature to substantially prevent spontaneous self-decomposition within the plating tool. Hence, significant advantages with respect to...

20060194432 - Methods of fabricating integrated circuit devices having self-aligned contact structures: An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a...

20060194433 - Method for production of structure and porous member: An anodized coating suitable for formation of highly regulated pores is provided. A method for production of a structure having pores characterized by including the steps of: forming starting points at predetermined intervals in an aluminum alloy formed on a substrate; and forming pores by anodization with the starting points...

20060194434 - Small grain size, conformal aluminum interconnects and method for their formation: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain...

20060194435 - Method of processing substrate, and method of and program for manufacturing electronic device: A method of processing a substrate that enables the amount removed of a surface damaged layer to be controlled easily, and enable a decrease in wiring reliability to be prevented. A surface damaged layer having a reduced carbon concentration of a carbon-containing low dielectric constant insulating film on a substrate...

20060194436 - Semiconductor device including resistor and method of fabricating the same: In a semiconductor device including a resistor and a method of fabricating the same, the semiconductor device includes an isolation insulating layer disposed in a semiconductor substrate to define at least two active regions spaced from each other. A well resistor pattern is disposed below the isolation insulating layer to...

20060194437 - Use of pulsed grounding source in a plasma reactor: A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor....

20060194438 - Method of forming a nanocluster charge storage device: A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed...

20060194439 - Etch with striation control: A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are...

20060194440 - Semiconductor device and method for producing the same: The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying...

20060194443 - Field effect transistor with gate spacer structure and low-resistance channel coupling: Spacer structures of field effect transistor structures are enhanced at least in sections with immobile charge carriers. The charge accumulated in the spacer structures induces an enhancement zone of mobile charge carriers in the underlying semiconductor substrate. The enhancement zone reduces the resistance of a channel coupling between the respective...

20060194441 - Method for etching a silicon wafer and method for performing differentiation between the obverse and the reverse of a silicon wafer using the same method: The invention is improvement of a silicon wafer etching method of storing an acid etching solution and an alkali etching solution respectively in plural etching tanks, and immersing a silicon wafer having a work-degenerated layer, which has experienced a lapping process and then a cleaning process, in the acid etching...

20060194442 - Procede method for cleaning a semiconductor: A method for removing contaminating particles from the substrate of a semiconductor, comprising a step for depositing a thin film in dielectric material on the substrate. The method is characterized in that the deposition step is immediately followed by a chemical etching step for removing the deposited thin film....

20060194444 - Patterning method for fabricating high resolution structures: Provided is a patterning method capable of fabricating high resolution structures without using a high resolution patterning step. The method comprises the steps of: (i) pre-patterning a layer of material (12) on a substrate (10), (ii) spin-coating a solution of a film-forming substance over the pre-patterned substrate, (iii) drying the...

20060194445 - Semiconductor manufacturing apparatus and method: A semiconductor manufacturing apparatus includes a transfer mechanism including a moving part for holding a substrate to be processed and moving along a longitudinal transferring passage and a plurality of processing units for performing respective processes on the substrate. The processing units are disposed along the transferring passage and the...

20060194446 - Plasma nitridization for adjusting transistor threshold voltage: A method of adjusting the threshold voltage of semiconductor devices by incorporating nitride into the isolation layer so as to decrease the mobility of charge carriers and thereby increase the threshold voltage required to activate the device. The nitrogen incorporation method may comprise of decoupled plasma nitridization (DPN) and the...

20060194447 - Plasma treatment of an etch stop layer: A method of manufacturing an etch stop layer 18, 20, 21 on a semiconductor wafer 2 and the etch stop layer 18, 20, 21 produced by the method. The method includes depositing a dielectric layer 18, 20, 21 and applying a plasma treatment to the semiconductor wafer 2. Also, an...

20060194448 - Replication tools and related fabrication methods and apparatus: Durable seamless replication tools are disclosed for replication of seamless relief patterns in desired media, for example in optical recording or data storage media. Methods of making such durable replication tools are disclosed, including preparing a recording substrate on the inner surface of a support cylinder, recording and developing a...

20060194449 - Resist pattern forming method and method of manufacturing semiconductor device: A resist pattern forming method includes forming a chemically amplified resist film on a substrate, forming a latent image in the resist film by irradiating an energy ray, contacting a liquid to a surface of the resist film, increasing temperature of the resist film to first temperature after the forming...

20060194450 - Semiconductor device and fabrication process of semiconductor device: A method of fabricating a semiconductor device on a Si substrate includes a first step of forming an insulation film containing an oxide of Zr or Hf on a Si substrate, a second step of forming a gate electrode film on the insulation film, a third step of patterning the...

20060194451 - High-k dielectric film, method of forming the same and related semiconductor device: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having...

20060194452 - Plasma nitridization for adjusting transistor threshold voltage: A method of adjusting the threshold voltage of semiconductor devices by incorporating nitride into the isolation layer so as to decrease the mobility of charge carriers and thereby increase the threshold voltage required to activate the device. The nitrogen incorporation method may comprise of decoupled plasma nitridization (DPN) and the...

20060194453 - Silicon dioxide film and process for preparation of the same: A transparent amorphous silicon dioxide film containing many fine voids, characterized in that the refractive index (for light at λ=500 nm) is in the range of 1.01 to 1.40 and that 80 vol. % or more of the fine voids have a diameter of 5 nm or less, has a...

20060194454 - Technique to radiation-harden trench refill oxides: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides....

20060189002 - Biochip platform including dielectric particle layer and optical assay apparatus using the same: Provided are a biochip platform for biochemically analyzing a sample such as DNA or protein, including a dielectric particle layer, and an optical assay apparatus including the same. The biochip platform includes the dielectric particle layer uniformly formed on a substrate. The particle uniformity of the dielectric particle layer enables...

20060189004 - Electronic and optoelectronic devices and methods for preparing same: Disclosed are electronic, plasmonic and opto-electronic components that are prepared using patterned photodeposited nanoparticles on a substrate surface. Also disclosed are ferroelectric nanolithography methods for preparing components, circuits and devices....

20060189003 - Temperature-compensated ferroelectric capacitor device, and its fabrication: A temperature-compensated capacitor device has ferroelectric properties and includes a ferroelectric capacitor using a ferroelectric material such as a metal oxide ferroelectric material, a negative-temperature-variable capacitor using a negative-temperature-coefficient-of-capacitance material such as a metal oxide paraelectric material, and an electrical series connection between the negative-temperature-variable capacitor and the ferroelectric capacitor....

20060189005 - Methods for fabricating semiconductor devices so as to stabilize the same when contact-bearing surfaces thereof face over test substrates: One or more of stabilizers are formed or disposed on the surface of a semiconductor device or test substrate prior to orienting the semiconductor device so that a contact-bearing surface thereof faces the test substrate. Upon assembly of the semiconductor device and test substrate, the stabilizers prevent the semiconductor device...

20060189006 - Method and apparatus for detecting end point: A mask layer and a to-be-processed layer are irradiated with light to measure interference light formed of reflected lights from the mask layer and reflected lights from the to-be-processed layer. Thereafter, an interference component brought by the mask layer is removed from the waveform of the measured interference light, thereby...

20060189009 - Apparatus for controlling semiconductor manufacturing process: An apparatus for controlling a semiconductor manufacturing process includes, a filter which receives from semiconductor processing devices first process parameters for processing a wafer and measured data obtained by measuring the wafer, and removes noise from the first process parameters and the measured data, a model generating unit which receives...

20060189008 - Method for monitoring implantation depth of impurity: The present invention provides a method for measuring an implantation depth of an impurity injected into a wafer by an ion implantation device, using a measurement device and monitoring whether the measured implantation depth of impurity falls within an allowable range, comprising the steps of using, as a measuring wafer,...

20060189010 - Method of testing fpc bonding yield and fpc having testing pads thereon: A flexible printed circuit (FPC) having testing pads thereon is provided. The FPC comprises a plurality of bonding pads and a plurality of testing pads, wherein each of the testing pads is disposed corresponding to each of the bonding pads, and the testing pads are electrically isolated from the bonding...

20060189011 - Semiconductor device and control method: In a semiconductor device for generating complementary PWM signals for, for example, controlling an inverter, a dead time is flexibly added by using a simple architecture. A dead time addition unit adds time elapsing until a value of a timer reaches a set value of a register as a first...

20060189007 - Wirebond crack sensor for low-k die: A sensor for measuring cracks in a semiconductor device, such as a wafer and, more particularly, to a BEOL wirebond crack sensor for low-k dies or wafers, and a method of providing the wirebond crack sensor for low-k wafers or the like structures....

20060189012 - Nitride compound semiconductor light emitting device and method for producing the same: A nitride compound semiconductor light emitting device includes: a GaN substrate having a crystal orientation which is tilted away from a <0001> direction by an angle which is equal to or greater than about 0.05° and which is equal to or less than about 2°, and a semiconductor multilayer structure...

20060189013 - Method of making led encapsulant with undulating surface: An LED package includes an LED die and a light-transmissive material encapsulating the die. The encapsulant is formed by dispensing a curable material onto a substrate, such as a carrier on which is mounted the LED die, to form a liquid mass thereon, the liquid mass having an unconstrained smooth...

20060189014 - High-luminescence silicon electroluminescence device: A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range...

20060189015 - Liquid crystal display and fabrication method thereof: A liquid crystal display includes a first substrate part, a second substrate part, and a sealant for attaching the first substrate part and the second substrate part; a Vcom terminal in the first substrate part and exposed at an edge of a region where the sealant is formed; a common...

20060189016 - Method of fabricating semiconductor optical device: Provided is a method of fabricating a semiconductor optical device for use in a subscriber or a wavelength division multiplexing (WDM) optical communication system, in which a laser diode (LD) and a semiconductor optical amplifier (SOA) are integrated in a single active layer. The laser diode (LD) and the semiconductor...

20060189017 - Method for manufacturing nitride semiconductor wafer or nitride semiconductor device; nitride semiconductor wafer or nitride semiconductor device made by the same; and laser irradiating apparatus used for the same: To remove the disparate substrate from nitride semiconductor layer grown over the disparate substrate, that is made of a material different from nitride semiconductor, by irradiating the disparate substrate with laser beam having a wavelength shorter than the band gap wavelength of the nitride semiconductor layer, while supplying an acidic...

20060189019 - Growth process of a crystalline gallium nitride based compound and semiconductor device including gallium nitride based compound: In a method of forming a crystalline GaN-based material, a first nucleation layer is formed on a substrate at a first temperature, followed with forming a second nucleation layer at a second temperature different from the first temperature. The first and second nucleation layers are composed of AlxInyGa(1-x-y)N. Subsequently, a...

20060189020 - Method for manufacturing nitride based single crystal substrate and method for manufacturing nitride based light emitting diode using the same: A method for manufacturing a nitride based single crystal substrate and a method for manufacturing a nitride based light emitting diode using the same. The method for manufacturing the nitride based single crystal substrate includes forming a ZnO layer on a base substrate; forming a low-temperature nitride buffer layer on...

20060189018 - P-n heterojuction structure of zinc oxide-based nanorod and semiconductor thin film, preparation thereof, and nano-device comprising same: A heterojunction structure composed of a p-type semiconductor thin film and n-type ZnO-based nanorods epitaxially grown thereon exhibits high luminescence efficiency property due to facilitated tunneling of electrons through the nano-sized junction and the use of ZnO having high exciton energy as a light emitting material, and thus it can...

20060189021 - Sample support prepared by semiconductor silicon process technique: A sample support of the present invention is prepared such that a silicon substrate is used as a raw material, the thickness structure having a shape and a thickness of 10 μm or less is prepared using a semiconductor silicon process technique. The sample support of the present invention is...

20060189022 - Mems heat pumps for integrated circuit heat dissipation: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to...

20060189024 - Microlens structure for image sensors: A microlens structure and a method of fabrication thereof are provided. The method comprises forming a layer of microlens material over a substrate, which has photo-sensitive elements formed therein. The microlens material, which comprises a photo-resist material, is exposed in accordance with a desired pattern a plurality of times. The...

20060189023 - Three dimensional structure formed by using an adhesive silicon wafer process: A method of making a MEMS device including providing a first substrate with an insulator layer thereon. A holder is attached to the insulator layer, and the first substrate is thinned. Thereafter, cavities are formed in the first substrate and the first substrate is flipped over and bonded to an...

20060189025 - Electro-optical device and manufacturing method thereoff: To suppress the occurrence of a failure caused by static electricity in the manufacturing process of an active matrix type display device in which an active matrix circuit and peripheral drive circuits are integrated on a glass substrate, a protective capacitor to be connected to a short ring is formed...

20060189026 - Method for manufacturing a display device with low temperature diamond coatings: A display device with multiple low temperature diamond coatings, including a substrate as a base; an anode layer residing on the diamond substrate for emitting holes; a hole drift layer that includes a doped diamond coating residing on the anode layer; an emissive layer for emitting light and residing on...

20060189027 - Method of fabricating avalanche photodiode: A method of fabricating an avalanche photodiode is disclosed. The method includes the steps of growing a plurality of semiconductor layers sequentially on a semiconductor substrate; growing diffusion layer patterns having diffusion coefficients different from that of an amplifying layer on a portion on which a peripheral portion of a...

20060189030 - Heat shrinkable insulated packaging: A method for preparing an insulating packaging material for a container is disclosed. A first layer of insulating material can be placed around a container, a second layer of heat-shrinkable material can be placed around the first layer and heat can be applied to heat-shrink the layer and conform the...

20060189029 - Method for efficient annealing of plated semiconductor package leads: A method for completing an assembled semiconductor device, which has metallic leads for connection to external parts. The method comprises the step (202) of encapsulating the assembled device with a polymeric precursor so that at least portions of the leads remain un-encapsulated. Without significant delay, these un-encapsulated lead portions are...

20060189028 - Wafer having alternating design structure and method for manufacturing semiconductor package using the same: The present invention relates to a wafer having an alternating design structure and a method for manufacturing a semiconductor package using the wafer. The present invention is conceived to solve all the aforementioned problems associated with the related art wafer having the lattice design arrangement and method for manufacturing a...

20060189031 - Semiconductor device and manufacturing method thereof: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package...

20060189033 - Integrated circuit package-in-package system: A package-in-package system is provided including forming a top substrate having a first integrated circuit electrically connected thereto and mounting a second integrated circuit over the first integrated circuit. The system includes forming first electrical connectors on the second integrated circuit and encapsulating the second integrated circuit in a first...

20060189032 - Process for assembling a double-sided circuit component: A process for producing a circuit component having a double-sided circuit device between a pair of substrates. The process entails depositing a solder material on contact areas on surfaces of the substrates, placing a first of the substrates within a cavity in a receptacle, and then placing a lead member...

20060189034 - Thin film processing method and thin film processing apparatus: A thin film processing method for processing the thin film by irradiating an optical beam to the thin film. A unit of the irradiation of the optical beam includes a first and a second optical pulse irradiation to the thin film, and the unit of the irradiation is carried out...

20060189036 - Methods and systems for adhering microfeature workpieces to support members: Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes disposing a first adhesive on a surface of a microfeature workpiece, and disposing a second adhesive on a surface of a support member. The method can further...

20060189035 - Placement of absorbing material in a semiconductor device: A semiconductor device is provided that includes a hermetically sealed housing having a top member and a bottom member. A semiconductor die is enclosed within the housing and absorbing material is positioned under the semiconductor die....

20060189037 - Low cost method to produce high volume lead frames: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material...

20060189038 - Semiconductor component and method of manufacture: A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor...

20060189039 - Fabrication of parascan tunable dielectric chips: An embodiment of the present invention provides a method, comprising fabricating a tunable dielectric chip by defining a critical area on a dielectric material via patterning and metallization and encapsulating said critical area....

20060189040 - Method of manufacturing an electronic device: The existing IC cards have a disadvantage of difficulty of mass production because an IC chip is supplied on a substrate one at a time. The present invention provides a method of manufacturing by placing a positioning jig having a plurality of openings each of which has a size fit...

20060189041 - Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign: An ASIC includes a function layer formed with plural universal logic cells, a common layer formed with conductive strips connected to the universal logic cells and common to other ASICs and a customized layer having at least two metallization layers assigned to conductive strips extending in certain directions parallel to...

20060189042 - Semiconductor chip and method of fabricating the same: There is provided a semiconductor chip having fuses. The semiconductor chip includes fuses each having a first terminal electrically connected to a first logic circuit, a second terminal electrically connected to a second logic circuit, and a blowable region formed between the first terminal and the second terminal; and fuse...

20060189044 - High reliability multilayer circuit substrates and methods for their formation: A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow...

20060189043 - Trench-gate electrode for finfet device: A FinFET device having a trench-gate electrode, and a method of manufacture, is provided. The trench-gate electrode may be fabricated by forming a mask layer on a substrate having a semiconductor layer, e.g., silicon, formed thereon. A trench is formed in the mask layer and fins are formed in the...

20060189045 - Method for fabricating a sublithographic contact structure in a memory cell: A method for fabricating a sublithographic contact structure in a memory cell in a semiconductor component is disclosed. In one embodiment, the method includes forming a trench structure having first spacers on walls of the trench structure, a first sublithographic dimension being formed in a region between the first spacers...

20060189047 - Television, electronic apparatus, and method of fabricating semiconductor device: [Means for Solving the Problem] According to the invention, a semiconductor device is fabricated by forming an inversely staggered TFT which is obtained by forming a gate electrode using a highly heat-resistant material, depositing an amorphous semiconductor film, adding a catalytic element into the amorphous semiconductor film and heating the...

20060189046 - Thin film forming method and forming device therefor: A method of forming a thin film of the present invention comprises: an optical characteristic adjusting step of repeatedly conveying a substrate holder between a zone to perform an intermediate thin film forming step and a zone to perform a film composition converting step while controlling a conveying speed of...

20060189049 - Four-transistor schmitt trigger inverter: A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an...

20060189048 - Method to strain nmos devices while mitigating dopant diffusion for pmos using a capped poly layer: The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the...

20060189050 - Method of forming a semiconductor device and an optical device and structure thereof: An integration process where a first semiconductor protective layer and a second semiconductor protective layer are formed to protect the first and second semiconductor materials, respectfully, during processing to form an optical device, such as a photodetector, and a transistor on the same semiconductor. The first semiconductor protective layer protects...

20060189051 - Semiconductor memory device with high operating current and method of manufacturing the same: In a semiconductor memory device with a high operating current and a method of manufacturing the same, a semiconductor substrate is formed in which a memory cell region and a peripheral circuit region including an N-channel metal oxide semiconductor (NMOS) region and a P-channel metal oxide semiconductor (PMOS) region are...

20060189052 - Method of fabricating polycrystalline silicon thin film for improving crystallization characteristics and method of fabricating liquid crystal display device using the same: A crystallization method of an amorphous semiconductor layer includes providing an amorphous semiconductor layer having a first thickness, crystallizing the amorphous semiconductor layer in a first direction, partially reducing the crystallized semiconductor layer to a second thickness less than the first thickness and crystallizing the etched semiconductor layer in a...

20060189057 - Integrated electronic circuit comprising superposed components: An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top...

20060189055 - Method of forming a composite layer, method of manufacturing a gate structure by using the method of forming the composite layer and method of manufacturing a capacitor by using the method of forming the composite layer: Methods of forming a composite layer, a gate structure and a capacitor are disclosed. In the methods, a first dielectric layer is atomic layer deposited on a substrate by using an oxidation gas and a first precursor gas that includes hafnium precursors. A second dielectric layer is then atomic layer...

20060189053 - Pmos transistor with discontinuous cesl and method of fabrication: A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on...

20060189056 - Strained channel complementary field-effect transistors and methods of manufacture: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A...

20060189054 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and...

20060189058 - Fin type field effect transistors and methods of manufacturing the same: A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction...

20060189061 - Cmos silicide metal gate integration: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height,...

20060189060 - Hdp-cvd methodology for forming pmd layer: A method of forming an HDP-CVD pre-metal dielectric (PMD) layer to reduce plasma damage and/or preferential sputtering at a reduced a thermal budget including providing a semiconductor substrate comprising at least two overlying semiconductor structures separated by a gap; forming a PMD layer according to an HDP-CVD process over the...

20060189059 - Intrinsic decoupling capacitor: A plurality of N-doped strip portions are formed alternating with a plurality of P-doped regions. When a voltage is applied to the N-doped strip portions, a capacitance is created between the N-doped strip portions and the P-doped strip portions. A capacitance is also created between the N-doped strip portions and...

20060189062 - Advance ridge structure for microlens gapless approach: A method of manufacturing a plurality of microlenses on a substrate comprises forming a grid having raised ridges defining a plurality of openings on the substrate and forming a plurality of patterned photoresist features each disposed within one of the plurality of openings. The plurality of patterned photoresist features can...

20060189063 - Insulated gate power semiconductor devices: A trench-gate semiconductor device (100) has a trench network (STR1), ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16...

20060189064 - Method of manufacturing capacitor of semiconductor device: Provided is a method of manufacturing a capacitor of a semiconductor device, which can prevent tilting or an electrical short of a lower electrode. In the method, a mesh-type bridge insulating layer is formed above the contact plug on a mold oxide layer. The mold oxide layer and the bridge...

20060189065 - Method of manufacturing metal-oxide-semiconductor transistor: A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing material layer is formed over the substrate and then the carbon-containing material layer...

20060189066 - Semiconductor device having optimized shallow junction geometries and method for fabrication thereof: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide...

20060189067 - Power converter apparatus using silicon germanium bipolar transistor for power switching: A power converter is composed of a switching circuit including a bipolar transistor for switching a DC power input. A SiGe heterobipolar transistor is used as the aforementioned bipolar transistor. The high speed switching characteristics of the SiGe heterobipolar transistor effectively reduces loss of the power converter....

20060189068 - Integrated high voltage capacitor having a top-level dielectric layer and a method of manufacture therefor: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a substrate (105), and an insulator (130) located over the...

20060189071 - Integrated circuit capacitor and method of manufacturing same: A method for fabricating a capacitor using supercritical CO2 deposition of metal film layers in a reducing environment from precursors, such as metallo-organic precursors is provided. The method can generate conformal growth on a 3-D cell structure at a relatively high speed, while minimizing the occurrence of oxidation of precursors...

20060189070 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, a trench formed in the semiconductor substrate, an island-like element region formed in the semiconductor substrate, having an upper surface, first to third side surfaces, an upper portion, a middle portion and a lower portion, a gate insulating film formed on the first...

20060189069 - Structure and method for integrating mim capacitor in beol wiring levels: A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and forming an interlevel dielectric material on the isolating...

20060189072 - Method and structure for metal-insulator-metal capacitor based memory device: A process for integrally fabricating a memory cell capacitor and a logic device is disclosed. A first conductive layer and second conductive layer are formed above a semiconductor substrate with a logic region and memory cell region. A first photoresist layer is formed to cover the logic region, and expose...

20060189073 - Control gate profile for flash technology: A nonvolatile memory device has a floating gate and a control gate. The floating gate incorporates a substantially vertical profile and provides the charge storage mechanism to set a specific threshold voltage. The control gate incorporates a sloped profile to enhance reliability....

20060189077 - Method for making high-density nonvolatile memory: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor...

20060189075 - Method of manufacturing semiconductor integrated circuit: A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETS, and the memory array part having N-type and P-type FETS, includes the steps of forming N-type and P-type FETs constituting the logic part and the...

20060189076 - Semiconductor device and manufacturing method thereof: In a thin film transistor, a metallic element promoting crystallization of an amorphous silicon film is effectively removed and the productivity is improved. By using a silicon film containing an element belonging to the group 15 such as phosphorus through contact holes reaching a source region and a drain region,...

20060189078 - Semiconductor structures and memory device constructions: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as...

20060189074 - Structure containing self-aligned conductive lines and fabricating method thereof: A method for fabricating self-aligned conductive lines is provided. A substrate with a plurality of isolation structures is provided. The isolation structures are protrusive from the surface of the substrate, and an active region is defined between two adjacent isolation structures. A plurality of semiconductor devices is formed in the...

20060189079 - Method of forming nanoclusters: A method for forming nanoclusters includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate, exposing the semiconductor substrate to a first flux of atoms to form first nuclei on the dielectric layer, exposing the first nuclei to a first inert atmosphere after exposing the semiconductor substrate...

20060189080 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: forming at least two gate patterns over a substrate; forming a first sidewall layer over on entire of the substrate structure including gat patterns; forming an insulation layer over the first sidewall layer; selectively removing the insulation layer...

20060189081 - Ldmos device and method of fabrication of ldmos device: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having...

20060189082 - Standby current reduction over a process window with a trimmable well bias: An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a...

20060189083 - Field effect transistor with etched-back gate dielectric: An ultrathin high-k gate dielectric made for use in a field-effect transistor is provided. The gate dialectric is made by depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to...

20060189084 - Memory element and memory device: The memory element 10 includes a memory layer 4 and an ion source layer 3 positioned between the first electrode 2 and the second electrode 6, in which the ion source layer 3 contains any of elements selected from Cu, Ag, Zn and any of elements selected from Te, S,...

20060189085 - Method of forming dual polysilicon gate of semiconductor device: In a method of forming a dual polysilicon gate of a semiconductor device, a polysilicon layer is formed on a substrate divided into an NMOS region and a PMOS region. Then, a p-type impurity is implanted in the PMOS region. A thermal annealing process is performed that causes generation of...

20060189086 - Son mosfet using a beam structure and method for fabricating thereof: The present invention relates to a SON (Silicon-On-Nothing) MOSFET having a beam structure and an inverter using thereof and the method for fabricating thereof to increase the efficiency and performance of a MOSFET. A method for fabricating the SON MOSFET according to the present invention comprises the steps of (a)...

20060189087 - Semiconductor device and method for fabricating the same: A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing...

20060189088 - Semiconductor device having a merged region and method of fabrication: A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one...

20060189089 - Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over...

20060189090 - Method for fabricating a metal-insulator-metal capacitor: A method for fabricating a capacitor is disclosed. First, a dielectric layer is disposed on a semiconductor substrate. Next, at least one dual damascene opening and at least one capacitor opening are formed in the dielectric layer. Next, a first conductive layer is disposed on the surface of the dielectric...

20060189091 - Method and system for laser hard marking: A method and system for laser hard marking is provided. The laser-marking system produces a hard mark on a semiconductor wafer. The system includes a pulsed laser subsystem that produces a pulsed laser output for marking at a location on the wafer. The pulsed laser subsystem is controlled so that...

20060189092 - Manufacturing method of semiconductor device with filling insulating film into trench: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first...

20060189093 - Adhesive with differential optical properties and its application for substrate processing: An adhesive adapted with particular optical properties, and its use to couple a substrate to a substrate holder during substrate processing are disclosed. After processing the substrate, the optical properties of the adhesive may be exploited to locate and/or remove adhesive residue that may be present on the substrate....

20060189094 - Method for integrating an electronic component or similar into a substrate: A method for integrating an electronic component or the like into a substrate includes following process steps: formation of a dielectric insulating layer on the front side of a substrate; complete back-etching of an area of the substrate from the back of the substrate to form a cavity; formation of...

20060189096 - Creation of high mobility channels in thin-body soi devices: A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film=and a second layer of strained film. The SOI wafer has a...

20060189097 - Method for manufacturing semiconductor device: The present invention is a separation method for easy separation of an allover release layer with a large area. Further, the present invention i