Semiconductor device manufacturing: process inventions 08/06

20060194347 - Method for fabricating superlattice semiconductor structure using chemical vapor diposition: The invention provides a method for fabricating a superlattice semiconductor structure capable of achieving excellent interfacial properties and uniformity. For the superlattice semiconductor structure according to the invention, a substrate is mounted on a susceptor within a process chamber. First and second source gases are supplied simultaneously to two different...

20060194348 - Ferroelectric and high dielectric constant integrated circuit capacitors with three-dimensional orientation for high-density memories, and method of making the same: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2...

20060194350 - Control system: A scientific experiment control system includes a main controller for high-level control, an experimental manager for lower-level control of scientific experiments, and a roll-up engine for automatically propagating modifications (or “changes”) within the system to ensure consistency across the system and instruments which are linked to it in an automatic...

20060194349 - Method of reworking a semiconductor structure: The present invention allows correcting malfunctions occurring in the formation of a cap layer on an electrical element in a semiconductor substrate. It is detected whether a malfunction occurred in the formation of the cap layer. If a malfunction in the formation of the cap layer was detected, a rework...

20060194351 - Methods and apparatus for configuring plasma cluster tools: A method for configuring a specific plasma cluster tool having a plurality of modules. The method includes providing a set of module option definition files, the set of module option definition files containing generic configuration definitions for generic plasma cluster tools. The method further includes providing a set of tool-specific...

20060194353 - Method and circuit for the detection of solder-joint failures in a digital electronic package: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a...

20060194352 - Semiconductor device test system: An apparatus for mitigating condensation formation on a device interface board during low-temperature semiconductor device testing includes a nozzle. The nozzle includes an input orifice for receiving gas from a gas source and at least one output orifice for discharging gas from the nozzle against a surface of the device...

20060194354 - Laser irradiation method and apparatus for forming a polycrystalline silicon film: A method for changing an amorphous silicon film to a poly-crystalline silicon film includes the steps of irradiating an elongate pulse laser beam onto the silicon film while scanning in the direction normal to the major axis of the elongate pulse laser beam, to form a plurality of irradiated areas,...

20060194355 - Laser diode bar provided with a parallel connected diode for bridging said laser siode bar in case of failure: A laser diode component comprising a laser diode bar on which a specific operating voltage is impressed during operation and with which a bridging element is connected in parallel, which bridging element is in a current-blocking state when the specific operating voltage is impressed on the associated laser diode bar...

20060194356 - Method for manufacturing multi-wavelength semiconductor laser device: The present invention provides a method for forming a multi-wavelength semiconductor laser device. The method comprises sequentially forming an AlGaAs-based epitaxial layer for a first semiconductor laser diode and an etching stop layer composed of AlxGayIn(1-x-y)P (0≦x≦1, 0≦y≦1) on a substrate and sequentially growing an n-type GaAs flattening buffer layer...

20060194357 - High-density germanium-on-insulator photodiode array: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to...

20060194358 - Tunable semiconductor laser and method thereof: A tunable semiconductor laser including a Fabry-Perot filter and an electrode array is disclosed. The propagation direction of the light beam in the cavity can be consecutively shifted applying electric field or current to the electrode and tuning can consecutively performed over the wide wavelength band by the consecutive shift...

20060194359 - Horizontal emitting, vertical emitting, beam shaped, distributed feedback (dfb) lasers by growth over a patterned substrate: A structure using integrated optical elements is comprised of a substrate, a buffer layer grown on the substrate, one or more patterned layers formed on the buffer layer and one or more active layers formed on or between the patterned layers, for instance by Lateral Epitaxial Overgrowth (LEO), and including...

20060194360 - Method for manufacturing nitride-base semiconductor element and nitride-base semiconductor element: A principal surface at one side of a support substrate has thereon an adjustment layer made of material having a higher thermal expansion coefficient than that of the support substrate. Then, a nitride-base semiconductor element layer and the support substrate on a growth substrate are joined via an adhesion layer....

20060194361 - Mems packaging using a non-silicon substrate for encapsulation and interconnection: A MEMS die is bonded to a cap to form a MEMS device. The cap is non-silicon and has an electrical via extending from one side of the cap to another side of the cap. In one embodiment, a plurality of caps is wafer bonded to a plurality of MEMS...

20060194362 - Sensor including lead frame and method of forming sensor including lead frame: A sensor includes a plurality of leads that have bottom surfaces extending in a first plane, a stage that extends in a second plane that tilts from the first plane, a sensor chip that is supported on the stage, a modified connection lead structure that supports the stage, and at...

20060194363 - Method of manufacturing a flexible electronic device and flexible device: An electrical element, such as a thin-film transistor, is defined on a flexible substrate, in that the substrate is attached to a carrier by an adhesive layer, and is delaminated after definition of the transistor. This is for instance due to illumination by UV-radiation. An opaque coating is provided to...

20060194364 - Micro-component packaging process and set of micro-components resulting from this process: A process for packaging a plurality of micro-components made on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a cover plate; depositing a metal layer on a face of the cover plate or on a face of the wafer; covering the...

20060194365 - Microelectronic assemblies having compliancy: A microelectronic assembly includes a microelectronic element, such as a semiconductor wafer or semiconductor chip, having a first surface and contacts accessible at the first surface, and a compliant layer overlying the first surface of the microelectronic element, the compliant layer having openings in substantial alignment with the contacts of...

20060194366 - Multi-chip ball grid array package: A multi-chip BGA package has two or more rerouted chips, each of which has one or more electrode plates. The electrode plate is coplanar with rerouting lines on the rerouted chip and may act as a decoupling capacitor, reducing simultaneous switching noise from fluctuations in power voltage, without causing an...

20060194367 - Semiconductor device production method and semiconductor device: A semiconductor device production method including: the step of forming a stopper mask layer of a first metal on a semiconductor substrate, the stopper mask layer having an opening at a predetermined position thereof; the metal supplying step of supplying a second metal into the opening of the stopper mask...

20060194368 - Thin film translator array panel and a method for manufacturing the panel: A gate wire including a gate line and a gate electrode is formed on a substrate and a gate insulating layer is formed on the substrate. A semiconductor pattern and an etching assistant pattern are formed on the gate insulating layer and a source/drain conductor pattern and an etching assistant...

20060194369 - Carrier for substrate film: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments...

20060194371 - Method of manufacturing semiconductor device: It is an object of the present invention to provide a technology to manufacture a semiconductor sheet or a semiconductor chip with a high yield using a circuit having a thin film transistor. A manufacturing method for a semiconductor device comprises: attaching a flexible base material to an element layer...

20060194370 - Radio frequency module and fabrication method thereof: The present invention relates to a RF module and a fabrication method thereof, wherein the packaging steps of a SAW component and a module is carried out simultaneously, thereby simplifying the fabrication process and reducing the size of the module. In the invention, a chip component is mounted on a...

20060194372 - Mold cleaning sheet and manufacturing method of a semiconductor device using the same: A cleaning sheet with frame for cleaning a molding die comprising a cleaning heat main body that covers the entire mating surface of a molding die and a reinforcing frame which can be disposed along the peripheral edge to the outside of the plural cavities of the mating surface of...

20060194373 - Methods for assembling semiconductor devices and interposers: A method for assembling one or more semiconductor devices with an interposer includes positioning the one or more semiconductor devices within a receptacle that extends through the interposer, on a retention element that extends over at least a portion of the receptacle. Material may be introduced between at least a...

20060194374 - Method of fabricating thin film transistor substrate for display device: A method of fabricating a thin film transistor substrate for a display device is provided. The method includes the steps of forming a gate line and a gate electrode connected to the gate line; forming a gate insulating film disposed covering the gate line and the gate electrode; forming a...

20060194375 - Semiconductor device and method of manufacturing thereof: To provide a liquid crystal display device having high quality display with a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load....

20060194376 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film...

20060194377 - Laser process: m

20060194378 - Semiconductor device and method of fabricating the same: According to the present invention, there is provided a semiconductor device having: first and second fins formed on a semiconductor substrate to oppose each other, and made of a semiconductor layer; an active region which is formed on the semiconductor substrate so as to be connected to the first and...

20060194382 - Design and simulation methods for electrostatic protection circuits: A physical analysis (S2) of the elements used in an ESD protection circuit is performed; parameters of the elements that have a comparatively large effect on ESD protection characteristics are extracted as key parameters (S4); and a mixed-mode device-circuit simulation of the ESD protection circuit is performed, using the key...

20060194379 - Field effect transistor and method for manufacturing same: A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and...

20060194381 - Gate structure and a transistor having asymmetric spacer elements and methods of forming the same: Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a...

20060194380 - Method for fabricating asymmetric semiconductor device: A method for fabricating an asymmetric semiconductor device is provided. A substrate formed with at least one base structure of MOSFET thereon is provided, wherein the base structure includes a gate over the substrate and a source extension and a drain extension in the substrate beside the gate. The base...

20060194383 - Semiconductor device and method for manufacturing the same: A semiconductor device includes: a second semiconductor layer formed on a side surface of a first semiconductor by epitaxial growth; a gate electrode disposed on a film formation surface of the second semiconductor layer; a source layer formed on the semiconductor layer and disposed on one side of the gate...

20060194384 - Semiconductor device with multiple semiconductor layers: A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic...

20060194385 - Method of fabricating flash memory device: A method of fabricating flash memory devices includes the steps of forming a stop nitride film and an oxide film on a semiconductor substrate having a predetermined structure formed therein, forming trenches in the oxide film and the stop nitride film, forming barrier oxide films on lateral faces of the...

20060194387 - High performance transistors with sige strain: A preferred embodiment of the invention comprises a semiconductor device having stress in the source/drain channel. The device comprises a substrate having a lattice constant greater than or equal to silicon and a first layer on the substrate, wherein the first layer has a lattice constant greater than the substrate....

20060194386 - Method and apparatus for supporting port aggregation of serial attached scsi wide ports via virtual ports: An SAS RAID adapter comprises an input-output processor (IOP) and at least two SAS input-output controllers (IOCs). Wherein SAS links coupled to each of the IOCs form “virtual ports” in order to increase performance and maintain availability. The virtual ports across the at least two IOCs have wide port SAS...

20060194389 - Method for fabricating flash memory device: A method is provided for fabricating a flash memory device, preventing particles from spreading around edges of a wafer while pre-cleaning a tunnel oxide film by removing particles at the edges of the wafer. Accordingly, it is able to overcome the problems arising from quality deterioration of the tunnel oxide...

20060194388 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor memory device comprises the steps of: preparing a semiconductor substrate having a gate insulation film and a gate electrode, the gate insulation film being formed on a predetermined active region in the semiconductor substrate, and the gate electrode being formed on the gate insulation...

20060194390 - Semiconductor device and method of manufacturing the same: A semiconductor device includes an interlayer insulation film including an air gap between portions of adjacent wiring layers or isolation pattern layers or both that are distanced from each other by thinning a layered structure of each of the wiring layers or the isolation pattern layers or both selectively from...

20060194392 - Mis-type semiconductor device: A MIS-type semiconductor device has reduced ON-resistance by securing an overlapping area between the gate electrode and the drift region, and has low switching losses by reducing the feedback capacitance. The MIS-type semiconductor device includes a p-type base region, an n-type drift region, a p+-type stopper region in the base...

20060194391 - Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process: A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of...

20060194394 - Mask rom, method for fabricating the same, and method for coding the same: A mask ROM, a method for fabricating the same and a method for coding the same are disclosed. The method for forming the mask ROM maximizes packing density and integration of a device. The mask ROM includes a semiconductor substrate having a device isolation region and an active region, BN...

20060194393 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate having first and second element forming regions, the first and second element forming regions divided by an element separating insulation film; forming a first gate insulation film on the semiconductor substrate; forming a predetermined film...

20060194395 - Metal hard mask method and structure for strained silicon mos transistors: A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the...

20060194396 - Method for depositing a metal gate on a high-k dielectric film and improving high-k dielectric film and metal gate interface, and a substrate treating system: A method to improve a high-k dielectric film and metal gate interface in the fabrication of a MOSFET by depositing a metal gate on a high-k dielectric, the method includes annealing a substrate with a high-k dielectric film deposited thereon in a thermal annealing module and depositing a metal gate...

20060194397 - Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates: In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is...

20060194398 - Semiconductor device and its manufacturing method: A semiconductor device which has a source/drain extension structure suitable for miniaturization, is provided a semiconductor device comprising a gate electrode formed on a semiconductor substrate of a first conductivity type via a gate insulator, a semiconductor region of a second conductivity type comprising first and second semiconductor areas, wherein...

20060194399 - Silicide gate transistors and method of manufacture: A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried...

20060194400 - Method for fabricating a semiconductor device: A method for fabricating a semiconductor device includes forming a first semiconductor layer on a front side of the semiconductor substrate. Additional semiconductor layers may be formed on a font side of the first semiconductor layer. The substrate is subsequently removed. In some embodiments, one or more additional semiconductor layers...

20060194401 - Method for manufacturing a semiconductor device having an alignment feature formed using an n-type dopant and a wet oxidation process: The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further...

20060194402 - Chip resistor: The invention relates to a method of making a chip resistor using a material substrate for which are set a plurality of first cutting lines extending in a first direction and a plurality of second cutting lines extending in a second direction perpendicular to the first direction. The method includes...

20060194403 - Pcmo thin film with controlled resistance characteristics: PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1<x<0.6; in response to the selection of x, varying the ratio of Mn and O ions as follows: O2− (3±20%); Mn3+ ((1−x)±20%);...

20060194404 - Method and system for fabricating and cleaning free-standing nanostructures: Systems and methods include introducing a semiconductor wafer into a process chamber. An etching chemistry is injected into the process chamber to etch a patterned layer and to release free-standing nanostructures on the semiconductor wafer. The etching chemistry includes a supercritical or liquid carbon dioxide fluid and an etching solution....

20060194405 - Semiconductor device and method of fabricating the same: A semiconductor device has an element isolating region formed of an insulating film having etching rates different from each other in a side close to an inside wall and a center side of a trench formed on a semiconductor substrate, and a selective epitaxial layer formed in both sides of...

20060194407 - Application of impressed-current cathodic protection to prevent metal corrosion and oxidation: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to...

20060194406 - Semiconductor wafer positioning method, and apparatus using the same: The intensity of light of a predetermined wavelength corresponding to the type of a protective tape joined to the surface of a semiconductor wafer is adjusted by a controller, and a holding stage for holding the semiconductor wafer is scanned rotationally. At this time, at a V notch portion for...

20060194408 - Process and circuit for manufacturing electronic semiconductor devices in a soi substrate: A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region...

20060194409 - Process for manufacturing a soi wafer with improved gettering capability: Manufacturing of a wafer made of semiconductor material on insulator including the steps of: providing a composite wafer having a substrate, an insulating layer and an active layer of semiconductor material, arranged on top of one another; forming at least one deep trench within the active layer of the composite...

20060194410 - Semiconductor device with cavity and method of manufacture thereof: A semiconductor device is provided with a substrate with a cavity inside, the substrate including a device formation area located above the cavity, a plurality of trenches formed in the substrate to communicate with the cavity and surround the device formation area, and an oxide film formed around each of...

20060194411 - Method to fabricate completely isolated silicon regions: The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer in areas designated as active regions. The nitrogen...

20060194414 - Low temperature fusion bonding with high surface energy using a wet chemical treatment: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been...

20060194412 - Method and device for sticking tape: Tapes are attached to a long support film, and the support film is attached to frame member at positions where the tape to be stuck to an adherend such as a semiconductor wafer, is included in a frame of a frame member. The support film is pressed to stick the...

20060194413 - Method of bonding substrates: A method of bonding a first substrate to a second substrate is provided. The method comprises the steps of: (a) providing a first substrate having a plurality of etched trenches defined in a first bonding surface; (b) providing a second substrate having a second bonding surface; and (c) bonding the...

20060194415 - Germanium infrared sensor for cmos imagers: A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+ silicon layer, forming a silicon-germanium interface; cyclic annealing; and implanting hydrogen ions...

20060194416 - Method for producing single crystal ingot from which semiconductor wafer is sliced: A method of manufacturing single-crystal semiconductor blocks is characterized in that a plurality of single-crystal semiconductor blocks of a relatively small diameter desired by users are cut out from a single-crystal semiconductor block of a relatively large diameter. With this method, there can also be obtained a secondary effect that...

20060194417 - Polycrystalline sillicon substrate: A polycrystalline silicon substrate for a solar cell formed by growing a high purity polycrystalline silicon layer on a surface of a base obtained by slicing a polycrystalline silicon ingot obtained by melting metallurgical grade silicon and performing one-direction solidification, wherein one-direction solidification is performed on a melt prepared by...

20060194418 - Smooth surface liquid phase epitaxial germanium: A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region....

20060194419 - Crystalline-si-layer-bearing substrate and its production method, and crystalline si device: A method for producing a substrate having a crystalline Si layer comprising the steps of forming an amorphous Si layer on a plastic substrate, and irradiating the amorphous Si layer with a laser beam to crystallize the amorphous Si, wherein the plastic substrate has light transmittance of 30 to 100%...

20060194420 - Multilayer film: This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film....

20060194421 - Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator cmos devices: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs...

20060194422 - Abrupt \"delta-like\" doping in si and sige films by uhv-cvd: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40...

20060194423 - Method of making a nitrided gate dielectric: A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed....

20060194424 - Microfeature devices and methods for manufacturing microfeature devices: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a...

20060194425 - Anisotropic conductive adhesive, electrode connection structure and method using the adhesive: Anisotropic conductive adhesive has conductive particles dispersed in adhesive and includes hard particles having conductivity, a resin layer that coats the hard particles and a conductive layer that coats the resin layer. A connection structure electrically connects electrodes to each other with the anisotropic conductive adhesive. A connection method includes...

20060194426 - Method for manufacturing dual damascene structure with a trench formed first: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer...

20060194428 - Control of wafer warpage during backend processing: A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer,...

20060194427 - Interconnecting process and method for fabricating complex dielectric barrier layer: An interconnecting process is described. First, a dielectric layer with a plurality of openings is provided. Then, a metallic layer is formed to fill up the openings. A first dielectric barrier layer is formed to cover the dielectric layer and the metallic layer. Thereafter, a second dielectric barrier layer is...

20060194429 - Semiconductor device and method of manufacturing the same: A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions...

20060194430 - Metal interconnect structure and method: In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric layer. A liner is formed over the dual damascene structure. The liner is selectively removed from above the...

20060194431 - Technique for metal deposition by electroless plating using an activation scheme including a substrate heating process: In an enhanced technique for electroless metal deposition, the substrate is heated to or above the operating temperature for the specific plating solution, while the plating solution may be maintained at a non-critical low temperature to substantially prevent spontaneous self-decomposition within the plating tool. Hence, significant advantages with respect to...

20060194432 - Methods of fabricating integrated circuit devices having self-aligned contact structures: An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a...

20060194433 - Method for production of structure and porous member: An anodized coating suitable for formation of highly regulated pores is provided. A method for production of a structure having pores characterized by including the steps of: forming starting points at predetermined intervals in an aluminum alloy formed on a substrate; and forming pores by anodization with the starting points...

20060194434 - Small grain size, conformal aluminum interconnects and method for their formation: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain...

20060194435 - Method of processing substrate, and method of and program for manufacturing electronic device: A method of processing a substrate that enables the amount removed of a surface damaged layer to be controlled easily, and enable a decrease in wiring reliability to be prevented. A surface damaged layer having a reduced carbon concentration of a carbon-containing low dielectric constant insulating film on a substrate...

20060194436 - Semiconductor device including resistor and method of fabricating the same: In a semiconductor device including a resistor and a method of fabricating the same, the semiconductor device includes an isolation insulating layer disposed in a semiconductor substrate to define at least two active regions spaced from each other. A well resistor pattern is disposed below the isolation insulating layer to...

20060194437 - Use of pulsed grounding source in a plasma reactor: A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor....

20060194438 - Method of forming a nanocluster charge storage device: A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed...

20060194439 - Etch with striation control: A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are...

20060194440 - Semiconductor device and method for producing the same: The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying...

20060194443 - Field effect transistor with gate spacer structure and low-resistance channel coupling: Spacer structures of field effect transistor structures are enhanced at least in sections with immobile charge carriers. The charge accumulated in the spacer structures induces an enhancement zone of mobile charge carriers in the underlying semiconductor substrate. The enhancement zone reduces the resistance of a channel coupling between the respective...

20060194441 - Method for etching a silicon wafer and method for performing differentiation between the obverse and the reverse of a silicon wafer using the same method: The invention is improvement of a silicon wafer etching method of storing an acid etching solution and an alkali etching solution respectively in plural etching tanks, and immersing a silicon wafer having a work-degenerated layer, which has experienced a lapping process and then a cleaning process, in the acid etching...

20060194442 - Procede method for cleaning a semiconductor: A method for removing contaminating particles from the substrate of a semiconductor, comprising a step for depositing a thin film in dielectric material on the substrate. The method is characterized in that the deposition step is immediately followed by a chemical etching step for removing the deposited thin film....

20060194444 - Patterning method for fabricating high resolution structures: Provided is a patterning method capable of fabricating high resolution structures without using a high resolution patterning step. The method comprises the steps of: (i) pre-patterning a layer of material (12) on a substrate (10), (ii) spin-coating a solution of a film-forming substance over the pre-patterned substrate, (iii) drying the...

20060194445 - Semiconductor manufacturing apparatus and method: A semiconductor manufacturing apparatus includes a transfer mechanism including a moving part for holding a substrate to be processed and moving along a longitudinal transferring passage and a plurality of processing units for performing respective processes on the substrate. The processing units are disposed along the transferring passage and the...

20060194446 - Plasma nitridization for adjusting transistor threshold voltage: A method of adjusting the threshold voltage of semiconductor devices by incorporating nitride into the isolation layer so as to decrease the mobility of charge carriers and thereby increase the threshold voltage required to activate the device. The nitrogen incorporation method may comprise of decoupled plasma nitridization (DPN) and the...

20060194447 - Plasma treatment of an etch stop layer: A method of manufacturing an etch stop layer 18, 20, 21 on a semiconductor wafer 2 and the etch stop layer 18, 20, 21 produced by the method. The method includes depositing a dielectric layer 18, 20, 21 and applying a plasma treatment to the semiconductor wafer 2. Also, an...

20060194448 - Replication tools and related fabrication methods and apparatus: Durable seamless replication tools are disclosed for replication of seamless relief patterns in desired media, for example in optical recording or data storage media. Methods of making such durable replication tools are disclosed, including preparing a recording substrate on the inner surface of a support cylinder, recording and developing a...

20060194449 - Resist pattern forming method and method of manufacturing semiconductor device: A resist pattern forming method includes forming a chemically amplified resist film on a substrate, forming a latent image in the resist film by irradiating an energy ray, contacting a liquid to a surface of the resist film, increasing temperature of the resist film to first temperature after the forming...

20060194450 - Semiconductor device and fabrication process of semiconductor device: A method of fabricating a semiconductor device on a Si substrate includes a first step of forming an insulation film containing an oxide of Zr or Hf on a Si substrate, a second step of forming a gate electrode film on the insulation film, a third step of patterning the...

20060194451 - High-k dielectric film, method of forming the same and related semiconductor device: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having...

20060194452 - Plasma nitridization for adjusting transistor threshold voltage: A method of adjusting the threshold voltage of semiconductor devices by incorporating nitride into the isolation layer so as to decrease the mobility of charge carriers and thereby increase the threshold voltage required to activate the device. The nitrogen incorporation method may comprise of decoupled plasma nitridization (DPN) and the...

20060194453 - Silicon dioxide film and process for preparation of the same: A transparent amorphous silicon dioxide film containing many fine voids, characterized in that the refractive index (for light at λ=500 nm) is in the range of 1.01 to 1.40 and that 80 vol. % or more of the fine voids have a diameter of 5 nm or less, has a...

20060194454 - Technique to radiation-harden trench refill oxides: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides....

20060189002 - Biochip platform including dielectric particle layer and optical assay apparatus using the same: Provided are a biochip platform for biochemically analyzing a sample such as DNA or protein, including a dielectric particle layer, and an optical assay apparatus including the same. The biochip platform includes the dielectric particle layer uniformly formed on a substrate. The particle uniformity of the dielectric particle layer enables...

20060189004 - Electronic and optoelectronic devices and methods for preparing same: Disclosed are electronic, plasmonic and opto-electronic components that are prepared using patterned photodeposited nanoparticles on a substrate surface. Also disclosed are ferroelectric nanolithography methods for preparing components, circuits and devices....

20060189003 - Temperature-compensated ferroelectric capacitor device, and its fabrication: A temperature-compensated capacitor device has ferroelectric properties and includes a ferroelectric capacitor using a ferroelectric material such as a metal oxide ferroelectric material, a negative-temperature-variable capacitor using a negative-temperature-coefficient-of-capacitance material such as a metal oxide paraelectric material, and an electrical series connection between the negative-temperature-variable capacitor and the ferroelectric capacitor....

20060189005 - Methods for fabricating semiconductor devices so as to stabilize the same when contact-bearing surfaces thereof face over test substrates: One or more of stabilizers are formed or disposed on the surface of a semiconductor device or test substrate prior to orienting the semiconductor device so that a contact-bearing surface thereof faces the test substrate. Upon assembly of the semiconductor device and test substrate, the stabilizers prevent the semiconductor device...

20060189006 - Method and apparatus for detecting end point: A mask layer and a to-be-processed layer are irradiated with light to measure interference light formed of reflected lights from the mask layer and reflected lights from the to-be-processed layer. Thereafter, an interference component brought by the mask layer is removed from the waveform of the measured interference light, thereby...

20060189009 - Apparatus for controlling semiconductor manufacturing process: An apparatus for controlling a semiconductor manufacturing process includes, a filter which receives from semiconductor processing devices first process parameters for processing a wafer and measured data obtained by measuring the wafer, and removes noise from the first process parameters and the measured data, a model generating unit which receives...

20060189008 - Method for monitoring implantation depth of impurity: The present invention provides a method for measuring an implantation depth of an impurity injected into a wafer by an ion implantation device, using a measurement device and monitoring whether the measured implantation depth of impurity falls within an allowable range, comprising the steps of using, as a measuring wafer,...

20060189010 - Method of testing fpc bonding yield and fpc having testing pads thereon: A flexible printed circuit (FPC) having testing pads thereon is provided. The FPC comprises a plurality of bonding pads and a plurality of testing pads, wherein each of the testing pads is disposed corresponding to each of the bonding pads, and the testing pads are electrically isolated from the bonding...

20060189011 - Semiconductor device and control method: In a semiconductor device for generating complementary PWM signals for, for example, controlling an inverter, a dead time is flexibly added by using a simple architecture. A dead time addition unit adds time elapsing until a value of a timer reaches a set value of a register as a first...

20060189007 - Wirebond crack sensor for low-k die: A sensor for measuring cracks in a semiconductor device, such as a wafer and, more particularly, to a BEOL wirebond crack sensor for low-k dies or wafers, and a method of providing the wirebond crack sensor for low-k wafers or the like structures....

20060189012 - Nitride compound semiconductor light emitting device and method for producing the same: A nitride compound semiconductor light emitting device includes: a GaN substrate having a crystal orientation which is tilted away from a <0001> direction by an angle which is equal to or greater than about 0.05° and which is equal to or less than about 2°, and a semiconductor multilayer structure...

20060189013 - Method of making led encapsulant with undulating surface: An LED package includes an LED die and a light-transmissive material encapsulating the die. The encapsulant is formed by dispensing a curable material onto a substrate, such as a carrier on which is mounted the LED die, to form a liquid mass thereon, the liquid mass having an unconstrained smooth...

20060189014 - High-luminescence silicon electroluminescence device: A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range...

20060189015 - Liquid crystal display and fabrication method thereof: A liquid crystal display includes a first substrate part, a second substrate part, and a sealant for attaching the first substrate part and the second substrate part; a Vcom terminal in the first substrate part and exposed at an edge of a region where the sealant is formed; a common...

20060189016 - Method of fabricating semiconductor optical device: Provided is a method of fabricating a semiconductor optical device for use in a subscriber or a wavelength division multiplexing (WDM) optical communication system, in which a laser diode (LD) and a semiconductor optical amplifier (SOA) are integrated in a single active layer. The laser diode (LD) and the semiconductor...

20060189017 - Method for manufacturing nitride semiconductor wafer or nitride semiconductor device; nitride semiconductor wafer or nitride semiconductor device made by the same; and laser irradiating apparatus used for the same: To remove the disparate substrate from nitride semiconductor layer grown over the disparate substrate, that is made of a material different from nitride semiconductor, by irradiating the disparate substrate with laser beam having a wavelength shorter than the band gap wavelength of the nitride semiconductor layer, while supplying an acidic...

20060189019 - Growth process of a crystalline gallium nitride based compound and semiconductor device including gallium nitride based compound: In a method of forming a crystalline GaN-based material, a first nucleation layer is formed on a substrate at a first temperature, followed with forming a second nucleation layer at a second temperature different from the first temperature. The first and second nucleation layers are composed of AlxInyGa(1-x-y)N. Subsequently, a...

20060189020 - Method for manufacturing nitride based single crystal substrate and method for manufacturing nitride based light emitting diode using the same: A method for manufacturing a nitride based single crystal substrate and a method for manufacturing a nitride based light emitting diode using the same. The method for manufacturing the nitride based single crystal substrate includes forming a ZnO layer on a base substrate; forming a low-temperature nitride buffer layer on...

20060189018 - P-n heterojuction structure of zinc oxide-based nanorod and semiconductor thin film, preparation thereof, and nano-device comprising same: A heterojunction structure composed of a p-type semiconductor thin film and n-type ZnO-based nanorods epitaxially grown thereon exhibits high luminescence efficiency property due to facilitated tunneling of electrons through the nano-sized junction and the use of ZnO having high exciton energy as a light emitting material, and thus it can...

20060189021 - Sample support prepared by semiconductor silicon process technique: A sample support of the present invention is prepared such that a silicon substrate is used as a raw material, the thickness structure having a shape and a thickness of 10 μm or less is prepared using a semiconductor silicon process technique. The sample support of the present invention is...

20060189022 - Mems heat pumps for integrated circuit heat dissipation: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to...

20060189024 - Microlens structure for image sensors: A microlens structure and a method of fabrication thereof are provided. The method comprises forming a layer of microlens material over a substrate, which has photo-sensitive elements formed therein. The microlens material, which comprises a photo-resist material, is exposed in accordance with a desired pattern a plurality of times. The...

20060189023 - Three dimensional structure formed by using an adhesive silicon wafer process: A method of making a MEMS device including providing a first substrate with an insulator layer thereon. A holder is attached to the insulator layer, and the first substrate is thinned. Thereafter, cavities are formed in the first substrate and the first substrate is flipped over and bonded to an...

20060189025 - Electro-optical device and manufacturing method thereoff: To suppress the occurrence of a failure caused by static electricity in the manufacturing process of an active matrix type display device in which an active matrix circuit and peripheral drive circuits are integrated on a glass substrate, a protective capacitor to be connected to a short ring is formed...

20060189026 - Method for manufacturing a display device with low temperature diamond coatings: A display device with multiple low temperature diamond coatings, including a substrate as a base; an anode layer residing on the diamond substrate for emitting holes; a hole drift layer that includes a doped diamond coating residing on the anode layer; an emissive layer for emitting light and residing on...

20060189027 - Method of fabricating avalanche photodiode: A method of fabricating an avalanche photodiode is disclosed. The method includes the steps of growing a plurality of semiconductor layers sequentially on a semiconductor substrate; growing diffusion layer patterns having diffusion coefficients different from that of an amplifying layer on a portion on which a peripheral portion of a...

20060189030 - Heat shrinkable insulated packaging: A method for preparing an insulating packaging material for a container is disclosed. A first layer of insulating material can be placed around a container, a second layer of heat-shrinkable material can be placed around the first layer and heat can be applied to heat-shrink the layer and conform the...

20060189029 - Method for efficient annealing of plated semiconductor package leads: A method for completing an assembled semiconductor device, which has metallic leads for connection to external parts. The method comprises the step (202) of encapsulating the assembled device with a polymeric precursor so that at least portions of the leads remain un-encapsulated. Without significant delay, these un-encapsulated lead portions are...

20060189028 - Wafer having alternating design structure and method for manufacturing semiconductor package using the same: The present invention relates to a wafer having an alternating design structure and a method for manufacturing a semiconductor package using the wafer. The present invention is conceived to solve all the aforementioned problems associated with the related art wafer having the lattice design arrangement and method for manufacturing a...

20060189031 - Semiconductor device and manufacturing method thereof: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package...

20060189033 - Integrated circuit package-in-package system: A package-in-package system is provided including forming a top substrate having a first integrated circuit electrically connected thereto and mounting a second integrated circuit over the first integrated circuit. The system includes forming first electrical connectors on the second integrated circuit and encapsulating the second integrated circuit in a first...

20060189032 - Process for assembling a double-sided circuit component: A process for producing a circuit component having a double-sided circuit device between a pair of substrates. The process entails depositing a solder material on contact areas on surfaces of the substrates, placing a first of the substrates within a cavity in a receptacle, and then placing a lead member...

20060189034 - Thin film processing method and thin film processing apparatus: A thin film processing method for processing the thin film by irradiating an optical beam to the thin film. A unit of the irradiation of the optical beam includes a first and a second optical pulse irradiation to the thin film, and the unit of the irradiation is carried out...

20060189036 - Methods and systems for adhering microfeature workpieces to support members: Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes disposing a first adhesive on a surface of a microfeature workpiece, and disposing a second adhesive on a surface of a support member. The method can further...

20060189035 - Placement of absorbing material in a semiconductor device: A semiconductor device is provided that includes a hermetically sealed housing having a top member and a bottom member. A semiconductor die is enclosed within the housing and absorbing material is positioned under the semiconductor die....

20060189037 - Low cost method to produce high volume lead frames: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material...

20060189038 - Semiconductor component and method of manufacture: A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor...

20060189039 - Fabrication of parascan tunable dielectric chips: An embodiment of the present invention provides a method, comprising fabricating a tunable dielectric chip by defining a critical area on a dielectric material via patterning and metallization and encapsulating said critical area....

20060189040 - Method of manufacturing an electronic device: The existing IC cards have a disadvantage of difficulty of mass production because an IC chip is supplied on a substrate one at a time. The present invention provides a method of manufacturing by placing a positioning jig having a plurality of openings each of which has a size fit...

20060189041 - Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign: An ASIC includes a function layer formed with plural universal logic cells, a common layer formed with conductive strips connected to the universal logic cells and common to other ASICs and a customized layer having at least two metallization layers assigned to conductive strips extending in certain directions parallel to...

20060189042 - Semiconductor chip and method of fabricating the same: There is provided a semiconductor chip having fuses. The semiconductor chip includes fuses each having a first terminal electrically connected to a first logic circuit, a second terminal electrically connected to a second logic circuit, and a blowable region formed between the first terminal and the second terminal; and fuse...

20060189044 - High reliability multilayer circuit substrates and methods for their formation: A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow...

20060189043 - Trench-gate electrode for finfet device: A FinFET device having a trench-gate electrode, and a method of manufacture, is provided. The trench-gate electrode may be fabricated by forming a mask layer on a substrate having a semiconductor layer, e.g., silicon, formed thereon. A trench is formed in the mask layer and fins are formed in the...

20060189045 - Method for fabricating a sublithographic contact structure in a memory cell: A method for fabricating a sublithographic contact structure in a memory cell in a semiconductor component is disclosed. In one embodiment, the method includes forming a trench structure having first spacers on walls of the trench structure, a first sublithographic dimension being formed in a region between the first spacers...

20060189047 - Television, electronic apparatus, and method of fabricating semiconductor device: [Means for Solving the Problem] According to the invention, a semiconductor device is fabricated by forming an inversely staggered TFT which is obtained by forming a gate electrode using a highly heat-resistant material, depositing an amorphous semiconductor film, adding a catalytic element into the amorphous semiconductor film and heating the...

20060189046 - Thin film forming method and forming device therefor: A method of forming a thin film of the present invention comprises: an optical characteristic adjusting step of repeatedly conveying a substrate holder between a zone to perform an intermediate thin film forming step and a zone to perform a film composition converting step while controlling a conveying speed of...

20060189049 - Four-transistor schmitt trigger inverter: A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an...

20060189048 - Method to strain nmos devices while mitigating dopant diffusion for pmos using a capped poly layer: The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the...

20060189050 - Method of forming a semiconductor device and an optical device and structure thereof: An integration process where a first semiconductor protective layer and a second semiconductor protective layer are formed to protect the first and second semiconductor materials, respectfully, during processing to form an optical device, such as a photodetector, and a transistor on the same semiconductor. The first semiconductor protective layer protects...

20060189051 - Semiconductor memory device with high operating current and method of manufacturing the same: In a semiconductor memory device with a high operating current and a method of manufacturing the same, a semiconductor substrate is formed in which a memory cell region and a peripheral circuit region including an N-channel metal oxide semiconductor (NMOS) region and a P-channel metal oxide semiconductor (PMOS) region are...

20060189052 - Method of fabricating polycrystalline silicon thin film for improving crystallization characteristics and method of fabricating liquid crystal display device using the same: A crystallization method of an amorphous semiconductor layer includes providing an amorphous semiconductor layer having a first thickness, crystallizing the amorphous semiconductor layer in a first direction, partially reducing the crystallized semiconductor layer to a second thickness less than the first thickness and crystallizing the etched semiconductor layer in a...

20060189057 - Integrated electronic circuit comprising superposed components: An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top...

20060189055 - Method of forming a composite layer, method of manufacturing a gate structure by using the method of forming the composite layer and method of manufacturing a capacitor by using the method of forming the composite layer: Methods of forming a composite layer, a gate structure and a capacitor are disclosed. In the methods, a first dielectric layer is atomic layer deposited on a substrate by using an oxidation gas and a first precursor gas that includes hafnium precursors. A second dielectric layer is then atomic layer...

20060189053 - Pmos transistor with discontinuous cesl and method of fabrication: A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on...

20060189056 - Strained channel complementary field-effect transistors and methods of manufacture: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A...

20060189054 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and...

20060189058 - Fin type field effect transistors and methods of manufacturing the same: A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction...

20060189061 - Cmos silicide metal gate integration: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height,...

20060189060 - Hdp-cvd methodology for forming pmd layer: A method of forming an HDP-CVD pre-metal dielectric (PMD) layer to reduce plasma damage and/or preferential sputtering at a reduced a thermal budget including providing a semiconductor substrate comprising at least two overlying semiconductor structures separated by a gap; forming a PMD layer according to an HDP-CVD process over the...

20060189059 - Intrinsic decoupling capacitor: A plurality of N-doped strip portions are formed alternating with a plurality of P-doped regions. When a voltage is applied to the N-doped strip portions, a capacitance is created between the N-doped strip portions and the P-doped strip portions. A capacitance is also created between the N-doped strip portions and...

20060189062 - Advance ridge structure for microlens gapless approach: A method of manufacturing a plurality of microlenses on a substrate comprises forming a grid having raised ridges defining a plurality of openings on the substrate and forming a plurality of patterned photoresist features each disposed within one of the plurality of openings. The plurality of patterned photoresist features can...

20060189063 - Insulated gate power semiconductor devices: A trench-gate semiconductor device (100) has a trench network (STR1), ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16...

20060189064 - Method of manufacturing capacitor of semiconductor device: Provided is a method of manufacturing a capacitor of a semiconductor device, which can prevent tilting or an electrical short of a lower electrode. In the method, a mesh-type bridge insulating layer is formed above the contact plug on a mold oxide layer. The mold oxide layer and the bridge...

20060189065 - Method of manufacturing metal-oxide-semiconductor transistor: A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing material layer is formed over the substrate and then the carbon-containing material layer...

20060189066 - Semiconductor device having optimized shallow junction geometries and method for fabrication thereof: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide...

20060189067 - Power converter apparatus using silicon germanium bipolar transistor for power switching: A power converter is composed of a switching circuit including a bipolar transistor for switching a DC power input. A SiGe heterobipolar transistor is used as the aforementioned bipolar transistor. The high speed switching characteristics of the SiGe heterobipolar transistor effectively reduces loss of the power converter....

20060189068 - Integrated high voltage capacitor having a top-level dielectric layer and a method of manufacture therefor: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a substrate (105), and an insulator (130) located over the...

20060189071 - Integrated circuit capacitor and method of manufacturing same: A method for fabricating a capacitor using supercritical CO2 deposition of metal film layers in a reducing environment from precursors, such as metallo-organic precursors is provided. The method can generate conformal growth on a 3-D cell structure at a relatively high speed, while minimizing the occurrence of oxidation of precursors...

20060189070 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a semiconductor substrate, a trench formed in the semiconductor substrate, an island-like element region formed in the semiconductor substrate, having an upper surface, first to third side surfaces, an upper portion, a middle portion and a lower portion, a gate insulating film formed on the first...

20060189069 - Structure and method for integrating mim capacitor in beol wiring levels: A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and forming an interlevel dielectric material on the isolating...

20060189072 - Method and structure for metal-insulator-metal capacitor based memory device: A process for integrally fabricating a memory cell capacitor and a logic device is disclosed. A first conductive layer and second conductive layer are formed above a semiconductor substrate with a logic region and memory cell region. A first photoresist layer is formed to cover the logic region, and expose...

20060189073 - Control gate profile for flash technology: A nonvolatile memory device has a floating gate and a control gate. The floating gate incorporates a substantially vertical profile and provides the charge storage mechanism to set a specific threshold voltage. The control gate incorporates a sloped profile to enhance reliability....

20060189077 - Method for making high-density nonvolatile memory: An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor...

20060189075 - Method of manufacturing semiconductor integrated circuit: A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETS, and the memory array part having N-type and P-type FETS, includes the steps of forming N-type and P-type FETs constituting the logic part and the...

20060189076 - Semiconductor device and manufacturing method thereof: In a thin film transistor, a metallic element promoting crystallization of an amorphous silicon film is effectively removed and the productivity is improved. By using a silicon film containing an element belonging to the group 15 such as phosphorus through contact holes reaching a source region and a drain region,...

20060189078 - Semiconductor structures and memory device constructions: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as...

20060189074 - Structure containing self-aligned conductive lines and fabricating method thereof: A method for fabricating self-aligned conductive lines is provided. A substrate with a plurality of isolation structures is provided. The isolation structures are protrusive from the surface of the substrate, and an active region is defined between two adjacent isolation structures. A plurality of semiconductor devices is formed in the...

20060189079 - Method of forming nanoclusters: A method for forming nanoclusters includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate, exposing the semiconductor substrate to a first flux of atoms to form first nuclei on the dielectric layer, exposing the first nuclei to a first inert atmosphere after exposing the semiconductor substrate...

20060189080 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: forming at least two gate patterns over a substrate; forming a first sidewall layer over on entire of the substrate structure including gat patterns; forming an insulation layer over the first sidewall layer; selectively removing the insulation layer...

20060189081 - Ldmos device and method of fabrication of ldmos device: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having...

20060189082 - Standby current reduction over a process window with a trimmable well bias: An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a...

20060189083 - Field effect transistor with etched-back gate dielectric: An ultrathin high-k gate dielectric made for use in a field-effect transistor is provided. The gate dialectric is made by depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to...

20060189084 - Memory element and memory device: The memory element 10 includes a memory layer 4 and an ion source layer 3 positioned between the first electrode 2 and the second electrode 6, in which the ion source layer 3 contains any of elements selected from Cu, Ag, Zn and any of elements selected from Te, S,...

20060189085 - Method of forming dual polysilicon gate of semiconductor device: In a method of forming a dual polysilicon gate of a semiconductor device, a polysilicon layer is formed on a substrate divided into an NMOS region and a PMOS region. Then, a p-type impurity is implanted in the PMOS region. A thermal annealing process is performed that causes generation of...

20060189086 - Son mosfet using a beam structure and method for fabricating thereof: The present invention relates to a SON (Silicon-On-Nothing) MOSFET having a beam structure and an inverter using thereof and the method for fabricating thereof to increase the efficiency and performance of a MOSFET. A method for fabricating the SON MOSFET according to the present invention comprises the steps of (a)...

20060189087 - Semiconductor device and method for fabricating the same: A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing...

20060189088 - Semiconductor device having a merged region and method of fabrication: A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one...

20060189089 - Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over...

20060189090 - Method for fabricating a metal-insulator-metal capacitor: A method for fabricating a capacitor is disclosed. First, a dielectric layer is disposed on a semiconductor substrate. Next, at least one dual damascene opening and at least one capacitor opening are formed in the dielectric layer. Next, a first conductive layer is disposed on the surface of the dielectric...

20060189091 - Method and system for laser hard marking: A method and system for laser hard marking is provided. The laser-marking system produces a hard mark on a semiconductor wafer. The system includes a pulsed laser subsystem that produces a pulsed laser output for marking at a location on the wafer. The pulsed laser subsystem is controlled so that...

20060189092 - Manufacturing method of semiconductor device with filling insulating film into trench: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first...

20060189093 - Adhesive with differential optical properties and its application for substrate processing: An adhesive adapted with particular optical properties, and its use to couple a substrate to a substrate holder during substrate processing are disclosed. After processing the substrate, the optical properties of the adhesive may be exploited to locate and/or remove adhesive residue that may be present on the substrate....

20060189094 - Method for integrating an electronic component or similar into a substrate: A method for integrating an electronic component or the like into a substrate includes following process steps: formation of a dielectric insulating layer on the front side of a substrate; complete back-etching of an area of the substrate from the back of the substrate to form a cavity; formation of...

20060189096 - Creation of high mobility channels in thin-body soi devices: A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film=and a second layer of strained film. The SOI wafer has a...

20060189097 - Method for manufacturing semiconductor device: The present invention is a separation method for easy separation of an allover release layer with a large area. Further, the present invention is the separating method that is not subjected to restrictions in the use of substrates, such as a kind of substrate, during forming a release layer. A...

20060189095 - Semiconductor substrates having useful and transfer layers: Methods for fabricating final substrates for use in optics, electronics, or optoelectronics are described. The method includes forming a zone of weakness beneath a surface of a source substrate to define a transfer layer; detaching the transfer layer from the source substrate along the zone of weakness; depositing a useful...

20060189101 - Dbg system and method with adhesive layer severing: An array of grooves (23) is formed in a first side (12) of a wafer (10) during a wafer processing method. A back grinding tape (16) is adhered to the first side. An amount of material is removed from the second side (20) of the wafer. An adhesive layer (30)...

20060189100 - Method for cutting a wafer using a protection sheet: The method for dicing a wafer comprising the steps of: reducing a thickness of a wafer to at least 0.1 mm or less; forming a protection sheet tightly on one side of the wafer, the protection sheet having a Vickers hardness of 2 or more; and dicing the wafer by...

20060189099 - Method of cutting integrated circuit chips from wafer by ablating with laser and cutting with saw blade: A method of cutting an integrated circuit chip from a wafer having a plurality of integrated circuit chips is provided. An upper portion of the wafer is ablated using two laser beams to form two substantially parallel trenches that extend into the wafer from a top surface of the wafer...

20060189098 - Substrate removal process for high light extraction leds: A method for fabricating light emitting diode (LEDs) comprises providing a plurality of LEDs on a substrate wafer, each of which has an n-type and p-type layer of Group-III nitride material formed on a SiC substrate with the n-type layer sandwiched between the substrate and p-type layer. A conductive carrier...

20060189102 - Process for treating substrates for the microelectronics industry, and substrates obtained by this process: A process for treating substrates for the microelectronics or optoelectronics industry, wherein the substrates include on at least one of their faces a working layer in which components are intended to be formed. The process includes a step of annealing under a reductive atmosphere followed by a step of chemical-mechanical...

20060189105 - Drive circuit of active matrix device and manufacturing method thereof: A data holding control signal for each data line is supplied to a plurality of source followers that are connected together in parallel. The parallel-connected source followers are a combination of at least one first follower that is illuminated with laser light only once and at least one second follower...

20060189104 - Method for forming a quantum dot pattern: A method of forming at least one quantum dot is disclosed. A substrate having a single crystal structure is provided. An insulating layer is formed on the substrate. At least one opening is defined in the insulating layer, thereby exposing at least one corresponding portion of the substrate. At least...

20060189103 - Solution treatment apparatus and solution treatment method: In the present invention, a plurality of exhaust paths connected to a plurality of cup bodies surrounding substrate holding portions respectively are joined together for common use, and the openings of exhaust rate adjustment sections provided on the exhaust paths are adjusted with reference to data in which combinations of...

20060189106 - Manufacture method for semiconductor device having field oxide film: On the principal surface of a silicon substrate, a side spacer made of silicon nitride is formed on the side wall of a lamination including a silicon oxide film, a silicon nitride film and a silicon oxide film. Thereafter, a channel stopper ion doped region is formed by implanting impurity...

20060189107 - Merged p-i-n schottky structure: Merged P-i-N Schottky device in which the oppositely doped diffusions extend to a depth and have been spaced apart such that the device is capable of absorbing a reverse avalanche energy comparable to a Fast Recovery Epitaxial Diode having a comparatively deeper oppositely doped diffusion region....

20060189108 - Suppressing formation of metal silicides on semiconductor surfaces: The present invention provides for compositions and methods of modifying a semiconductor structure, the structure including a semiconductor material, silicon, or germanium. The methods include modifying at the atomic scale at least one surface of the structure and forming a low-reactivity surface, contacting the at least one surface with at...

20060189109 - Methods of fabricating contact regions for fet incorporating sige: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried,...

20060189110 - Body capacitor for soi memory description: A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the...

20060189112 - Electronic devices fabricated by use of random connections: Embodiments of the present invention are directed to methods for fabricating microscale-to-nanoscale interfaces. In numerous embodiments of the present invention, hybrid microscale/nanoscale crossbar multiplexers/demultiplexers provide for selection and control of individual nanowires through a set of microscale signal lines. In order to overcome the difficulty of aligning nanowires with submicroscale...

20060189113 - Metal nanoparticle compositions: A metal nanoparticle composition for the fabrication of conductive features. The metal nanoparticle composition advantageously has a low viscosity permitting deposition of the composition by direct-write tools. The metal nanoparticle composition advantageously also has a low conversion temperature, permitting its deposition and conversion to an electrical feature on polymeric substrates....

20060189111 - Method of making cmos devices on strained silicon on glass: A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer;...

20060189114 - Method of manufacturing semiconductor device and semiconductor device: According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric...

20060189115 - Wiring structure forming method and semiconductor device: After a via hole (102) to connect a lower wiring (101) and an upper wiring not shown is formed in an insulating film (103) using an etching stopper film (104) and a hard mask (105), a base film (106) made from Ta is formed over the insulating film (103) so...

20060189116 - Dual metal stud bumping for flip chip applications: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive...

20060189117 - Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment: A tip of a first wire is bonded to a first electrode. The first wire is drawn from the first electrode to a bump on a second electrode. A part of the first wire is deformed and bonded to the bump. A tip of a second wire formed in the...

20060189118 - Microfeature devices and methods for manufacturing microfeature devices: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a...

20060189119 - Encapsulation of circuit components to reduce thermal cycling stress: A method of encapsulating materials to protect circuit components from the stress of thermal cycling includes applying a first substance to cover Wire bonds on a first layer, applying a second substance to wire bonds on a second layer, and curing the first and second substances by application of heat...

20060189120 - Method of making reinforced semiconductor package: A method of making a reinforced semiconductor package includes forming a semiconductor interconnect tablet (24). Formation of the tablet includes providing a plurality of conductive metal tabs (10), positioning a first end (12) of the tabs (10) in a first section of a mold chase (14), positioning a second section...

20060189121 - Thin silicon based substrate: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die....

20060189123 - Etchant and method of etching: A fine wiring line profile with satisfactory precision is formed from a multilayer film containing a first layer made of an aluminum alloy and a second layer formed thereon made of a molybdenum-niobium alloy, by simultaneously etching the two layers constituting the multilayer film through only one etching operation while...

20060189122 - Method of forming isolated features of semiconductor devices: A method of forming isolated features of semiconductor devices is disclosed. A first hard mask is deposited over a material layer to be patterned, and a second hard mask is deposited over the first hard mask. The second hard mask is patterned with a pattern for an array of features...

20060189125 - Multilayer wiring substrate, and method of producing same: A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up...

20060189124 - Semiconductor device having a through contact through a housing composition and method for producing the same: A semiconductor device includes a housing composition and a through contact extending through the housing composition. The through contact is provided in a contact hole formed through the housing composition and having an asymmetrical funnel form with at least two opposite inner wall sides oriented substantially perpendicular to the top...

20060189126 - Method of forming semiconductor device having epitaxial contact plug connecting stacked transistors: A method of forming an epitaxial contact plug in a semiconductor device comprises forming an insulating interlayer on a semiconductor substrate, forming a mushroom-shaped epitaxial plug in an opening of the insulating interlayer, forming a buffer layer on the epitaxial plug and the insulating interlayer, and planarizing epitaxial plug and...

20060189127 - Method to improve palanarity of electroplated copper: Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling...

20060189128 - Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from a conductive line: This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative material over a semiconductive substrate. The conductive line is laterally spaced...

20060189129 - Method for applying metal features onto barrier layers using ion permeable barriers: The methods described are directed to processes for producing structures containing metallized features for use in microelectronic workpieces. The processes treat a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and metallized features include an acid...

20060189130 - Method of forming metal line in semiconductor device: A method of forming a line a semiconductor device, including the steps of forming an interlayer insulating film on a semiconductor substrate in which predetermined structures are formed, forming a trench through which a predetermined region of the semiconductor substrate is exposed in the interlayer insulating film, sequentially forming a...

20060189131 - Composition and process for element displacement metal passivation: A composition and process suitable for the passivation of metal lines, layers or surfaces, particularly for the passivation of copper in the fabrication of integrated circuit devices on wafer substrates. The process includes providing a novel composition solution in contact with a copper line, layer or surface on a substrate...

20060189132 - Method for forming porous thin film: A method for forming a porous thin film is characterized by formation of a composite thin film on a substrate, in which film a metal portion composed of a first metal component and a metal compound portion composed of a compound of a second metal component which is different from...

20060189133 - Reliable beol integration process with direct cmp of porous sicoh dielectric: The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of...

20060189134 - Ta-tan selective removal process for integrated device fabrication: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the...

20060189135 - Trench interconnect structure and formation method: Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in reduced interconnect resistance, I2R losses, and defects or variations due to cusping. Embodiments of the methods involve forming an opening in an insulating layer, where the opening forms a...

20060189136 - Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit: A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate....

20060189137 - Method of forming damascene filament wires and the structure so formed: A method of forming a semiconductor device, and the device so formed. Depositing a low dielectric constant material on a substrate. Depositing a hard mask on the low dielectric constant material. Forming an at least one first feature within the low dielectric constant material and the hard mask. Depositing a...

20060189140 - Insulated pad conditioner and method of using same: A wafer planarization process with a conditioning tool having an electrical insulator that electrically insulates the abrasive surface of the conditioning tool. The electrical insulator extends the useful life of the abrasive surface of the conditioning tool by reducing the level of electrochemically driven corrosion....

20060189138 - Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device: A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has...

20060189139 - Methods and apparatuses for electrochemical-mechanical polishing: Methods and apparatuses for removing material from a microfeature workpiece are disclosed. In one embodiment, the microfeature workpiece is contacted with a polishing surface of a polishing medium, and is placed in electrical communication with first and second electrodes, at least one of which is spaced apart from the workpiece....

20060189142 - Method for making a sub-micron solid oxide electrolyte membrane: This document describes fabrication method for a thin film electrolyte membrane and electrochemical devices including the membrane. As an electrolyte becomes thinner, the conductance of the electrolyte increases. Consequently, the performances of solid-state ionic devices like fuel cells, gas sensors and catalytic supporters, can be improved and operating temperature can...

20060189141 - Solution for etching copper surfaces and method of depositing metal on copper surfaces: A solution for etching copper or a copper alloy for producing a copper surface having the brightest possible finish for a metallization that is to follow is described. The solution has a pH on the order of 4 or less and is free of sulfate ions. It comprises: a) at...

20060189143 - Metal structure with sidewall passivation and method: A passivated metal structure and a method of forming the metal structure is disclosed. According to one embodiment, the patterned metal structure, such as conductive lines, are formed on a substrate. The copper lines are passivated by a polymer liner between the copper lines and a low k dielectric filling...

20060189145 - Method of manufacturing a semiconductor device from which damage layers and native oxide films in connection holes have been removed: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection...

20060189144 - Multiple layer etch stop and etching method: A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (hereinafter “slots”) in the substrates. The process includes applying a first layer to a back side of a substrate as a first etch stop material. The first layer is a relatively...

20060189146 - Method for patterning micro features by using developable bottom anti-reflection coating: In the manufacture of a semiconductor, a DBARC layer is deposited upon a wafer to prevent reflection. A photo resist layer is deposited upon the DBARC layer and the wafer is selectively exposed to irradiation. The irradiation generates photo acid (H+ ions) in the exposed areas of the photo resist...

20060189147 - Pattern forming method and semiconductor device manufacturing method: A pattern forming method includes the following teps. A resist pattern is formed on a to-be-processed film. A mask pattern including the resist pattern and a resin film formed on a surface of the resist pattern is formed. Slimming of the mask pattern is executed....

20060189148 - Transistor having a metal nitride layer pattern, etchant and methods of forming the same: A transistor having a metal nitride layer pattern, etchant and methods of forming the same is provided. A gate insulating layer and/or a metal nitride layer may be formed on a semiconductor substrate. A mask layer may be formed on the metal nitride layer. Using the mask layer as an...

20060189150 - Composition for an organic hard mask and method for forming a pattern on a semiconductor device using the same: A composition for the organic hard mask includes a polyamic acid compound, and a method for forming a pattern is used in a manufacturing process of semiconductor devices by coating the composition for organic hard mask film on an underlying layer, and depositing a second hard mask film with a...

20060189151 - Method for forming an infrared photodetector with a vertical optical path: Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and,...

20060189149 - Method of smoothening dielectric layer: A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas....

20060189152 - Slurry composition, method of polishing an object and method of forming a contact in a semiconductor device using the slurry composition: In a slurry composition preventing damage to an insulation layer, and uniformly polishing a metal layer, the slurry composition includes an acidic aqueous solution having a first pH and an anionic surfactant having a second pH lower than or equal to the first pH. Irregular polishing of the metal layer...

20060189153 - Structures with improved interfacial strength of sicoh dielectrics and method for preparing the same: A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive...

20060189154 - Atomic layer deposition of hf3n4/hfo2 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf3N4) and hafnium oxide (HfO2) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing...

20060189155 - Method of forming semiconductor compound film for fabrication of electronic device and film produced by same: A process of forming a compound film includes formulating a nano-powder material with a controlled overall composition and including particles of one solid solution The nano-powder material is deposited on a substrate to form a layer on the substrate, and the layer is reacted in at least one suitable atmosphere...

20060189157 - Method for forming an integrated circuit semiconductor substrate: An integrated circuit semiconductor substrate includes an active silicon layer separated from a silicon substrate layer by a buried insulating material layer. The active silicon layer, however, locally includes at least one over-thickness on the side of the buried layer, while maintaining a flat surface state of the semiconductor layer...

20060189156 - Method for making a semiconductor device having a high-k gate dielectric: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer....

20060189158 - Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing...

20060189159 - Methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and methods of forming trench isolation in the fabrication of integrated circuitry: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing...

20060189162 - Adhesion improvement for low k dielectrics: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including introducing an organosilicon compound and an oxidizing gas at a first ratio of organosilicon...

20060189161 - Method and apparatus for treating organosiloxane coating film: A method for processing an organosiloxane film includes loading a target substrate (W) with a coating film formed thereon into a reaction chamber (2), and performing a heat process on the target substrate (W) within the reaction chamber (2) to bake the coating film. The coating film contains a polysiloxane...

20060189160 - Method for producing a pattern formation mold: The method for producing a pattern formation mold includes: a first step of applying to a substrate a radiation-sensitive negative-type resist composition containing an epoxy resin represented by formula (I): (wherein R1 represents a moiety derived from an organic compound having k active hydrogen atoms (k represents an integer of...

20060189163 - Method of forming thick silica-based film: The present invention provides a process for forming a silica-based coating film, characterized by heating a reaction mixture comprising a silicon compound (A) represented by Si(OR)4 and/or a silicon compound (B) represented by R1nSi (OR2)4-n (wherein n is an integer of from 1 to 3), an alcohol (C) represented by...

20060189164 - Hafnium alloy target and process for producing the same: Provided is a hafnium alloy target containing either or both of Zr and Ti in a gross amount of 100 wtppm-10 wt % in Hf, wherein the average crystal grain size is 1-100 μm, the impurities of Fe, Cr and Ni are respectively 1 wtppm or less, and the habit...

20060189165 - Method and apparatus for non-aggressive plasma-enhanced vapor deposition of dielectric films: While performing plasma-enhanced chemical vapor deposition on a substrate by exposing the substrate in a vacuum to a flow of particles generated by a plasma, which particles react to form a passivation layer on the substrate, a grid is interposed between the plasma and the substrate, thereby reducing the flow...

20060189166 - Process for performing an isolated pd(ii)-mediated oxidation reaction: There is disclosed a process for performing an isolated Pd(II) mediated oxidation reaction electrochemically. The inventive process is performed on an electrode array device having a plurality of separately addressable electrodes. Preferably, the Pd(II) mediated oxidation is a Wacker reaction. Specifically, there is disclosed a process for conducting an isolated...

20060189167 - Method for fabricating silicon nitride film: A method for fabricating a silicon nitride film is disclosed. The method is adapted for a substrate comprising a transistor device. A self-aligned silicide film is formed over the transistor device. A silicon nitride film is then formed over the substrate. A thermal process is performed to the silicon nitride...

20060189169 - Method for heat treatment of silicon wafers: A method is provided for the heat treatment of low oxygen concentration silicon wafers obtained from a silicon single crystal produced by the Czochralski process. The method comprises high-temperature oxidation heat treatment for the formation of a high oxygen concentration region under the wafer surface and the subsequent oxygen precipitation...

20060189168 - Plasma generator, ozone generator, substrate processing apparatus and manufacturing method of semiconductor device: To provide a generator capable of generating plasma and ozone with high efficiency and easy to handle, with a simple structure. An electrode part 10 is formed of electrodes 11 and 12 without dielectric material interposed therebetween. An arc-extinguishing capacitor 13 as a charge storage part for storing charge is...

20060189170 - Plasma treatment apparatus and method for plasma treatment: A plasma treatment apparatus and a method for plasma treatment are provided that made possible to control accurately a distance between plasma and an object to be treated (hereinafter referred to as an object), and that facilitated a transportation of a substrate that a width is thin and grown in...

20060189172 - Method using specific contact angle for immersion lithography: A method for performing immersion lithography on a semiconductor wafer is disclosed. The method includes positioning the semiconductor wafer beneath a lens and applying a fluid between a top surface of the semiconductor wafer and the lens. An additive can be provided to the top surface so that any droplet...

20060189171 - Seasoning process for a deposition chamber: A seasoning process for a deposition chamber, the process comprising providing a silicon-containing seasoning gas inside the deposition chamber; and forming a silicon-based seasoning film on at least one surface inside the deposition chamber, the seasoning film having a refractive index of about 1.48 or more....

20060183248 - Semiconductor cleaning using superacids: A method of cleaning a substrate includes contacting a surface of a semiconductor substrate with a composition comprising a superacid. The semiconductor substrate may be a wafer....

20060183251 - Double density mram with planar processing: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated magnetic memory structures. In one aspect, the present teachings relate to magnetic memory structure fabrication techniques...

20060183252 - Ferroelectric memory devices: Forming a ferroelectric memory device can include forming an insulating layer on a substrate, forming a sacrificial layer on the first insulating layer so that the insulating layer is between the sacrificial layer and the substrate, and forming a contact hole extending through the sacrificial layer and the insulating layer....

20060183250 - Methods of fabricating ferroelectric capacitors utilizing a partial chemical mechanical polishing process: The invention provides methods for fabricating ferroelectric capacitors and ferroelectric memory devices incorporating such capacitors. The methods according to the invention each include a partial chemical mechanical polishing process by which a planarized surface may be formed on a material layer formed between a buried contact plug and a ferroelectric...

20060183249 - Thin films of ferroelectric materials and a method for preparing same: Thin films of ferroelectric material with a high mole fraction of Pb(A2+1/3B5+2/3)O3 substantially in a perovskite phase, wherein A is zinc or a combination of zinc and magnesium, and B is a valence 5 element such as niobium or tantalum, have been prepared. Typically, the mole fraction of Pb(A2+1/3B5+2/3)O3 in...

20060183254 - Method of fabricating and/or repairing a light emitting device: A method of repairing a light emitting device which makes high quality image display possible even if a pin hole is formed during formation of an EL layer is provided. The method of repairing a light emitting device is characterized in that a reverse bias voltage is applied to an...

20060183253 - Repairing method of a thin film transistor array: A repairing method of thin film transistor array is provided. The repairing method of thin film transistor array can remove a residue between pixel electrodes so as to prevent the residue from electrically connecting pixel electrodes adjacent to each other. The repairing method of thin film transistor array can also...

20060183255 - Capacitance probe for thin dielectric film characterization: A capacitance probe for thin dielectric film characterization provides a highly sensitive capacitance measurement method and reduces the contact area needed to obtain such a measurement. Preferably, the capacitance probe is connected to a measurement system by a transmission line and comprises a center conductive tip and RLC components between...

20060183256 - Method of piping defect detection: A method of piping defect detection is provided. A semiconductor substrate having an active region and an isolation region is provided, a plurality of semiconductor elements are formed on the semiconductor substrate, a dielectric layer is deposited on the semiconductor substrate and the semiconductor elements, and first and second contact...

20060183257 - Method for analyzing electrolytic copper plating solution, and analyzing device therefor and production method for semi-conductor product: Effective fillability and the uniformity electrodeposition of a copper electroplating solution is judged by determining the time-dependent potential change thereof at a cathode current density of 0.1-20 A/dm2. The potential change is determined at a working electrode rotation of 100-7500 rpm, and the fillability with the solution is judged from...

20060183258 - Imaging system and method for producing semiconductor structures on a wafer by imaging a mask on the wafer with a dipole diaphragm: An imaging system having a dipole diaphragm (2) having two diaphragm openings (2b) arranged one behind the other in a dipole axis (y), and a mask having mask structures (20, 23) is used for producing semiconductor structures (10′, 13′) on a wafer (15′) by imaging the mask (25) onto the...

20060183259 - Method of forming a wear-resistant dielectric layer: A substrate is provided. The substrate includes a plurality of devices disposed in the substrate, a plurality of contact pads disposed on a surface of the substrate and electrically connected to the devices, and a surface dielectric layer positioned on the surface of the substrate. Thereafter, a surface treatment process...

20060183260 - P-type nitride semiconductor and method of manufacturing the same: A method for manufacturing p-type nitride semiconductor comprising a semiconductor layer forming process where a low resistivity p-type nitride semiconductor layer is formed on a substrate by introducing the sources of p-type dopant, nitrogen and Group III sources on a substrate held at a temperature of 600° C. or higher...

20060183261 - Method of forming a biological sensor: A method of forming a biological sensor on a predetermined area of a substrate. The method includes dispensing a plurality of layers on the predetermined area of the substrate. Each of the plurality of layers is formed of a substantially different fluid having a substantially different function. The dispensing of...

20060183262 - Thin film encapsulation of mems devices: A method of manufacturing a miniature electromechanical system (MEMS) device includes the steps of forming a moving member on a first substrate such that a first sacrificial layer is disposed between the moving member and the substrate, encapsulating the moving member, including the first sacrificial layer, with a second sacrificial...

20060183264 - Photodiode with fiber mode dispersion compensation: A photodiode and a method of fabricating a photodiode for reducing modal dispersion and increasing travel distance. The central region of the photodiode is made less responsive to incident light than a peripheral region of the photodiode. The less responsive central region discriminates the lower order modes such that only...

20060183263 - Structure and manufacturing method of an image tft array: The present invention provides a manufacturing method of an image TFT array, which includes providing a substrate including a thin film transistor region, a storage capacitor region, a pad region, and a common electrode region, forming a photoresist layer on the substrate, and performing a photolithographic and etching process by...

20060183265 - Image sensor having improved sensitivity and method for making same: An image sensor having improved sensitivity and method for making same include a substrate having an active pixel region with a peripheral circuit region surrounding the active pixel region; a plurality of photo conversion elements disposed in the active pixel region, each photodiode is configured for receiving light through a...

20060183266 - Method of fabricating cmos image sensor: A method of fabricating an image sensor includes the steps of sequentially stacking a metal layer and a nitride layer over a semiconductor substrate divided into an active area and a pad area; forming a metal pad on the pad area by selectively patterning the nitride layer and the metal...

20060183267 - Process for manufacturing a schottky contact on a semiconductor substrate: A process realizes a Schottky contact on an epitaxial layer of a semiconductor substrate. The process includes depositing a conductive metallic layer on a surface of the epitaxial layer, with achievement of a interface region of conductive metallic layer/semiconductor. The process further comprises a ionic irradiation step directed towards the...

20060183268 - Salicide process for image sensor: A self-aligned silicide (salicide) process is used to form a metal salicide for a CMOS image sensor consistent with a conventional CMOS image sensor process flow. An insulator layer is deposited over the pixel array of the image sensor. Portions of the insulator layer are removed using a photoresist mask...

20060183269 - Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method: A process for producing a semiconductor component having a plastic housing in which at least one semiconductor chip is arranged includes providing a semiconductor wafer having semiconductor chips which are arranged in rows and columns and have active top surfaces and back surfaces, the active top surfaces being provided with...

20060183270 - Tools and methods for forming conductive bumps on microelectronic elements: A method of making a microelectronic assembly includes providing a microelectronic element having a front face and contact pads accessible at the front face, providing a dispensing tool containing a molten metal and having a discharge port for dispensing the molten metal, and aligning the discharge port of the dispensing...

20060183271 - High density stepped, non-planar nitride read only memory: A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells in a column. The...

20060183272 - Atomic layer deposition of zr3n4/zro2 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr3N4) and zirconium oxide (ZrO2) and a method of fabricating such a dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing zirconium oxide using...

20060183273 - Thin film transistor and method of fabricating the same: A thin film transistor and method of fabricating the same are provided. In the thin film transistor, a seed or a grain boundary exists in a semiconductor layer pattern but not in a junction region. The method includes forming a semiconductor layer pattern. Forming the semiconductor layer pattern includes: forming...

20060183274 - Transparent oxide semiconductor thin film transistors: This invention relates to novel, transparent oxide semiconductor thin film transistors (TFT's) and a process for making them....

20060183275 - Method and system for implementing film grain insertion: Aspects of a system and method for processing video data may comprise, for each line of a field of an image, generating noise based on a current seed, inserting the generated noise in a current line of the field, and generating a new seed for processing a subsequent line of...

20060183276 - Method of manufacturing a semiconductor device: After crystallization of a semiconductor film is performed by irradiating first laser light (energy density of 400 to 500 mJ/cm2) in an atmosphere containing oxygen, an oxide film formed by irradiating the first laser light is removed. It is next performed to irradiate second laser light under an atmosphere that...

20060183278 - Field effect device having a channel of nanofabric and methods of making same: Field effect devices having channels of nanofabric and methods of making same. A nanotube field effect transistor is made to have a substrate, and a drain region and a source region in spaced relation relative to each other. A channel region is formed from a fabric of nanotubes, in which...

20060183277 - Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer....

20060183279 - Method for selectively stressing mosfets to improve charge carrier mobility: A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress...

20060183280 - Metal-insulator-metal capacitors and methods of forming the same: There are provided metal-insulator-metal (MIM) capacitors and methods of forming the same. The capacitors and the formation methods thereof provide a way of simplifying semiconductor fabrication processes, using component elements of the capacitor and insulating layers around the capacitor. To this end, lower and upper electrodes are sequentially stacked on...

20060183281 - Method for manufacturing non-volatile memory devices integrated in a semiconductor substrate: A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, each electrode including a first dielectric layer, a first conductive layer, a second dielectric...

20060183282 - Method for patterning submicron pillars: The present invention provides for a method to pattern and etch very small dimension pillars, for example in a memory array. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using...

20060183285 - Method of fabricating a nonvolatile semiconductor memory: In a process for fabricating a nonvolatile semiconductor memory of the tunneling type, when tunnel windows are formed in an oxide film on a semiconductor substrate, the oxide film is etched first by a dry etching process, then by a wet etching process. The dry etching process quickly removes most...

20060183284 - Non-volatile semiconductor storage device and the manufacturing method thereof: High integration and making a non-volatile semiconductor memory efficient have been promoted. The memory cell consists of a floating gate, a control gate constituting a word line WL and a MOS transistor having an assist gate. The thickness of the gate oxide film of the assist gate is thinner than...

20060183283 - One time programmable eprom for advanced cmos technology: A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM (100) will breakdown during a programming operation by maintaining a breakdown voltage above a programming voltage. The breakdown...

20060183286 - Transistor having enlarged contact surface area and manufacturing method therefor: In a transistor in which a contact surface area between a contact and a source/drain region is enlarged and a method of manufacturing the same, a lower insulating layer is formed on a substrate. Then, a semiconductor layer is formed on the lower insulating layer and selectively recessed to form...

20060183287 - Methods and apparatus for transmitting layered and non-layered data via layered modulation: A media access control (MAC) layer controller can manage base layer data and enhancement layer data in a layered modulation system. The MAC layer controller can process both base layer data and enhancement layer data and map the encoded symbols to a layered modulation constellation when both are present. If...

20060183288 - Processes for forming electronic devices including a semiconductor layer: An impurity can be introduced into a semiconductor layer of a workpiece to affect the oxidation and the relative concentration of one element with respect to another element within the semiconductor layer. The impurity can be selectively implanted using one or more masks, manipulating the beam line of an ion...

20060183289 - Back gate finfet sram: A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a...

20060183290 - Manufacturing method for semiconductor device and rapid thermal annealing apparatus: During a manufacturing process for a semiconductor device, the size of gate electrodes is measured within the wafer surface. The gained measurement data is compared with the data which depends on the gate length-electrical properties of the semiconductor elements, and thus, distribution in the electrical properties within the wafer surface...

20060183291 - Methods of forming capacitor structures: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in...

20060183292 - Sti liner modification method: A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of...

20060183293 - Method of forming alignment mark and method of manufacturing semiconductor device: A method of forming an alignment mark for specifying an optimum exposing position includes the steps of: preparing a substrate having a semiconductor element and an insulation film covering the semiconductor element; forming a resist pattern having a first opening on the insulation film, the first opening having a first...

20060183296 - Isolation method for semiconductor device: An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask...

20060183294 - Methods of forming integrated circuitry: The invention includes methods of forming integrated circuitry. In one implementation, a method of forming an integrated circuit includes forming a plurality of isolation trenches within semiconductive silicon-comprising material. The isolation trenches comprise sidewalls comprising exposed semiconductive silicon-comprising material. An epitaxial silicon-comprising layer is grown from the exposed semiconductive silicon-comprising...

20060183295 - Semiconductor device having self-aligned contact and manufacturing method thereof: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on...

20060183297 - Etching solution for removal of oxide film, method for preparing the same, and method of fabricating semiconductor device: Provided are an anionic surfactant-containing etching solution for removal of an oxide film, preparation methods thereof, and methods of fabricating a semiconductor device using the etching solution. The etching solution includes a hydrofluoric acid (HF), deionized water, and an anionic surfactant. The anionic surfactant is a compound in which an...

20060183298 - Method for manufacturing a ceramic/metal substrate: The invention relates to a novel method for producing a metal/ceramic substrate, which is characterized by applying at least one metal area to at least one top surface of a ceramic layer. At least one metal area is applied to at least one surface side of a ceramic layer, wherein...

20060183299 - Electronic device sealed under vacuum containing a getter and method of operation: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a...

20060183301 - Method for forming thin film: A method for forming a thin film by using an atomic layer deposition (ALD) method and a method for fabricating a capacitor using the same includes: supplying a source gas, a reaction gas, and a purge gas, then discontinuing the supply of the reaction gas and the source gas, followed...

20060183300 - Porous structures useful as bipolar plates and methods for preparing same: The invention relates to a porous structure, characterized in that it comprises a porous matrix (15) made of carbon fabric, said porous matrix being bounded on at least one of its faces (17, 21) by an impermeable layer (19, 23) made of an element chosen from carbon fibres, carbon nanotubes...

20060183302 - Highly conductive shallow junction formation: The invention relates to a method of forming a shallow junction. The method (100) comprises forming source/drain extension regions with a non-amorphizing tail implant (105) which is annealed conventionally (spike/RTP) and amorphizing implant which is re-grown epitaxially (SPER) (110). The non-amorphizing tail implant is generally annealed (106) before a doped...

20060183303 - Crystallized semiconductor device, method for producing same and crystallization apparatus: In a method of manufacturing a crystallized semiconductor device of the present invention, a thermal diffusion layer (1) having higher thermal conductivity than that of a substrate (4) is formed on a surface of a semiconductor layer (2), and then laser light is applied to the semiconductor layer (2) from...

20060183304 - Semiconductor device and method for producing the same: A method for producing a semiconductor device includes irradiating an amorphous semiconductor film on an insulating material with a pulsed laser beam having a rectangular irradiation area, while scanning in a direction intersecting a longitudinal direction of the irradiation area, thereby forming a first polycrystalline semiconductor film, and irradiating a...

20060183305 - Sputter-deposited rare earth element-doped silicon oxide film with silicon nanocrystals for electroluminescence applications: A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a...

20060183306 - Method for producing an electronic component with shielding: An electronic component with shielding is described. The component has a semiconductor chip with a semiconductor substrate. Disposed in a region of a rear side of the semiconductor substrate is an electrically conductive buried layer. The buried layer is connected via a ground lead, disposed within the semiconductor substrate, to...

20060183307 - Boron diffusion in silicon devices: Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat...

20060183308 - Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gases additions: A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and...

20060183309 - Method for manufacturing a patterned structure: A method for forming a micro- or nano-pattern of a material on a substrate is presented. The method utilizes a buffer layer assisted laser patterning (BLALP). A layered structure is formed on the substrate, this layered structure being in the form of spaced-apart regions of the substrate defined by the...

20060183311 - Method for manufacturing semiconductor devices and plug: A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first...

20060183310 - Process for fabricating semiconductor device and method for generating mask pattern data: A method of fabricating a semiconductor device including a first wiring pattern extending in a vertical direction and a second wiring pattern identical in geometry to the first wiring pattern and extending in a (horizontal) direction orthogonal to the vertical direction, including the steps of: employing linearly polarized illumination to...

20060183312 - Method of forming chip-type low-k dielectric layer: A substrate including a plurality of contact pads is provided. Thereafter, a photosensitive dielectric layer is formed on a surface of the substrate. Subsequently, an exposure-and-development process is preformed to partially remove the photosensitive dielectric layer so as to form a plurality of openings. The openings at least expose the...

20060183313 - Semiconductor package and method for manufacturing the same: A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers...

20060183314 - Method for fabricating interconnect structures with reduced plasma damage: Methods to form interconnect structures utilizing sacrificial filling material layers are described herein. Utilizing the sacrificial filling material makes it possible to reduce damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability....

20060183315 - Method to create air gaps using non-plasma processes to damage ild materials: A method of forming airgaps is provided where a blocking mask is applied to a substrate to shield a portion of the substrate from a beam of energy. After irradiation, the blocking mask is removed and a capping material is applied to the substrate. Alternatively, the capping material may be...

20060183316 - Method of providing printed circuit board with conductive holes and board resulting therefrom: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by...

20060183317 - Semiconductor device and a method of manufacturing the same: Provided are a semiconductor device comprising a semiconductor substrate, a first insulating film formed thereover, interconnects formed over the first insulating film and having copper as a main component, a second insulating film formed over the upper surface and side surfaces of each of the interconnects and over the first...

20060183318 - Magnetic memory cells and manufacturing methods: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the...

20060183319 - Method for manufacturing a semiconductor device: In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures are filled with a first insulation film, etch stop film patterns having...

20060183320 - Methods of filling trenches using high-density plasma deposition (hdp): Methods of filling trenches/gaps defined by circuit elements on an integrated circuit substrate are provided. The methods include forming a first high-density plasma layer on an integrated circuit substrate including at least one trench thereon using a first reaction gas. The first high-density plasma layer is etched using an etch...

20060183321 - Method for reduction of gap fill defects: A method of electrodepositing a conductor to form a defect-free conductor layer on a wafer surface including features. The wafer surface including the features is lined with a nucleation film. The conductor is electrodeposited onto the nucleation layer from a process solution having an additive that adsorbs strongly on the...

20060183322 - Deposition methods and apparatuses providing surface activation: A deposition method includes, at a first temperature, contacting a substrate with a surface activation agent and adsorbing a first layer over the substrate. At a second temperature greater than the first temperature, the first layer may be contacted with a first precursor, chemisorbing a second layer at least one...

20060183323 - Salicide process using cmp for image sensor: A self-aligned silicide (salicide) process is used to form a silicide for a CMOS image sensor consistent with a conventional CMOS image sensor process flow. An insulator layer is deposited over the pixel array of the image sensor. An organic layer is deposited over the insulator layer. A chemical mechanical...

20060183324 - Semiconductor device and method for producing the same: Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the...

20060183325 - Lift-off method: A lift-off method includes providing a material structure, applying photoresist on a surface of the material structure, partially exposing the photoresist, baking the material structure with the partially exposed photoresist applied on the surface of the material structure, developing the photoresist with an organic, polar developer, so that the photoresist...

20060183328 - Electrolytic copper plating solutions: The present invention provides inter alia copper electroplating compositions, methods for use of the compositions and products formed by the compositions. Electroplating compositions of the invention contain an increased brightener concentration that can provide effective copper plate on difficult-to-plate aperture walls, including high aspect ratio, small diameter microvias....

20060183326 - High pressure treatment for improved grain growth and void reduction: A copper film is annealed at high pressure to enhance grain growth and remove voids. Other films, such as dielectrics, may also be suitable. High pressure can be used in conjunction with temperatures lower than room temperature for annealing or higher temperatures may be used to further enhance grain growth....

20060183327 - Nitrogen rich barrier layers and methods of fabrication thereof: Methods of forming barrier layers and structures thereof are disclosed. A nitrogen rich region is formed at a top surface of a barrier layer by exposing the barrier layer to a nitridation treatment. The nitrogen rich region increases the oxidation resistance of the barrier layer. The barrier layers have improved...

20060183329 - Apparatus and method for reducing impurities in a semiconductor material: An apparatus and method of treating multiple wafers to reduce the density of impurities as well as to improve the uniformity of substrate electrical characteristics without any thermal stress. The wafers are chemically treated, and heat treated in a sealed reaction tube under arsenic overpressure with a controlled thermal profile...

20060183330 - Laser assisted chemical etching method for release of microscale and nanoscale devices: A method using an etchant and a laser for localized precise heating enables precise etching and release of MEMS devices with improved process control while expanding the number of materials used to make MEMS, including silicon-dioxide patterned films buried in and subsequently released from bulk silicon, as a direct write...

20060183331 - Methods for patterning dielectric material, and methods for aligning semiconductor fabrication molds and semiconductor substrates: The invention includes methods of forming patterns in low-k dielectric materials by contact lithography. In a particular application, a mold having a first pattern is pressed into a low-k dielectric material to form a second pattern within the material. The second pattern is substantially complementary to the first pattern. The...

20060183332 - Method of manufacturing floating structure: A method of manufacturing a floating structure capable of providing increased device yield. The method includes: a) forming an insulation film, a predetermined area of which is removed, between a first substrate and a second substrate; and b) forming a floating structure in the removed predetermined area....

20060183334 - Methods for planarization of group viii metal-containing surfaces using oxidizing gases: A planarization method includes providing a second and/or third Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes an oxidizing gas....

20060183333 - Methods of fabricating semiconductor device using sacrificial layer: There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a...

20060183335 - Using an electron beam to write phase change memory devices: Phase change memories may be made with relatively small pore sizes using electron beam lithography. An electrode may be covered with a relatively thin insulator, which may be patterned using direct write electron beam lithography....

20060183336 - Method of optimized stitching for digital micro-mirror device: A method of providing a reticle layout for a die having at least three patterns, namely a right pattern, a center pattern, and a left pattern, where the center pattern is oversized relative to the photolithography step size. To avoid the non-uniformity effects resulting from stitching the center pattern, the...

20060183337 - Post high voltage gate dielectric pattern plasma surface treatment: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within...

20060183338 - Etchant composition and manufacturing method for thin film transistor array panel: The present invention provides an etchant composition containing 60 to 75 wt % of phosphoric acid (H3PO4), 0.5 to 15 wt % of nitric acid (HNO3), 2 to 15 wt % of acetic acid (CH3COOH), and 0.1 to 15 wt % of aluminum nitrate (Al(NO3)3)....

20060183340 - Coating and developing apparatus and coating and developing method: A coating and developing apparatus comprises a process block which includes a unit block for coating-film formation which applies a resist, and a unit block for development which performs a developing process, and is separately provided with a coating-film-formation-unit-block transfer mechanism and a developing-process-unit-block transfer mechanism. After a substrate after...

20060183341 - Method of forming silicon-containing insulation film having low dielectric constant and low diffusion coefficient: A method for fabricating a semiconductor device includes: forming on a substrate a silicon-containing insulation film having a diffusion coefficient of about 250 μm2/min or less as measured using isopropyl alcohol, by plasma reaction using a reaction gas comprising (i) a source gas comprising a silicon-containing hydrocarbon compound containing plural...

20060183339 - Stressed semiconductor using carbon and method for producing the same: A stressed semiconductor using carbon is provided. At least one carbon layer containing diamond is formed either below a semiconductor layer or above a semiconductor device. The carbon layer induces stress in the semiconductor layer, thereby increasing carrier mobility in the device channel region. The carbon layer may be selectively...

20060183342 - Metal and metal oxide patterned device: The invention relates to a patterned device comprising a substrate covered by a pattern of metal and oxidized metal surrounding said pattern of metal....

20060183343 - Oxidizing method and oxidizing unit of object for object to be processed: An oxidizing method for an object to be processed according to the present invention includes: an arranging step of arranging a plurality of objects to be processed in a processing container whose inside can be vacuumed, the processing container having a predetermined length, a supplying unit of an oxidative gas...

20060183344 - Barrier layer for a processing element and a method of forming the same: In order to mitigate erosion of exposed processing elements in a processing system by the process and any subsequent contamination of the substrate in the processing system, processing elements exposed to the process are coated with a protective barrier. The protective barrier comprises a protective layer that is resistant to...

20060183345 - Advanced low dielectric constant organosilicon plasma chemical vapor deposition films: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and...

20060183347 - Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing...

20060183346 - Multilayer anti-reflective coating for semiconductor lithography and the method for forming the same: An interconnect structure has a dielectric layer having a dielectric constant less than 3.9 overlying a substrate with a conductive region, a silicon oxycarbide layer overlying the dielectric layer, and a silicon oxynitride layer overlying the silicon oxycarbide layer. A conductive layer is inlaid the silicon oxynitride layer, the silicon...

20060183348 - Layered films formed by controlled phase segregation: Multiple-layer films in integrated circuit processing may be formed by the phase segregation of a single composition formed above a semiconductor substrate. The composition is then induced to phase segregate into at least a first continuous phase and a second continuous phase. The composition may be formed of two or...

20060183349 - Semiconductor component having thinned die with polymer layers: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the...

20060183351 - Apparatus for manufacturing liquid crystal display device: An apparatus for manufacturing a liquid crystal display device is disclosed. A first robot arm at a loading side of the thru-conveyor receives a substrate coated with photoresist and conveys the substrate to a thru-conveyor. A softbake hot plate (SHP) at the unloading side of the thru-conveyor removes solvent from...

20060183350 - Process for fabricating semiconductor device: A laser annealing process capable of suppressing a variation in sheet resistance. A surface layer formed shallower than 100 nm in a substrate of semiconductor material is added with impurities. The substrate is irradiated with a laser beam or its harmonic beam emitted from a laser diode pumped to solid-state...

20060177946 - Method to assemble structures from nano-materials: Numerous embodiments of a method to assemble nano-materials on a platform are described. In one embodiment, a nano-material is functionalized with a first bondable group. The functionalized nano-material is disposed on an assembly platform having an electrode to form a first layer. Additional layers of the nano-material may be formed...

20060177948 - Airtight terminal and method for producing the same, a piezoelectric vibrator and a method for producing the same, an oscillator, an electronic unit and a wave timepiece: An airtight terminal that is small but provides good yield and a method for producing the same, an airtight terminal best suited for use in a piezoelectric vibrator and a method for producing the same, and a small piezoelectric vibrator with a small change in properties that uses these airtight...

20060177947 - Magnetoresistive random-access memory device: Disclosed is a new type of magnetoresistive random-access memory (MRAM) device using a magnetic semiconductor, which is capable of achieving high-integration and energy saving in a simplified structure without any MOS transistor, based on a rectification effect derived from a p-i-n type low-resistance tunneling-magnetoresistance-effect (low-resistance TMR) diode with a structure...

20060177949 - Method for monitoring oxide film deposition: A method for monitoring oxide film deposition is disclosed. The method utilizes silicon wafers having silicon nitride films thereon instead of bare silicon wafers to monitor the growth of silicon oxide/dioxide films in a furnace. The method for monitoring oxide film deposition comprises the following steps. First of all, a...

20060177950 - Method of manufacturing optical interferance color display: The method of manufacturing an optical interference color display is described. A first electrode structure is formed over a substrate first. At least one first area, second area and third area are defined on the first electrode structure. A first sacrificial layer is formed over the first electrode structure of...

20060177951 - Method of forming film pattern, device, method of manufacturing the same, electro-optical apparatus, and electronic apparatus: A method of forming a film pattern by disposing a functional liquid on a substrate, includes: forming banks on the substrate; disposing the functional liquid in areas partitioned by the banks; and drying the functional liquid disposed on the substrate, wherein the forming of the banks including: forming a plurality...

20060177953 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device includes the steps of forming a step region having a mesa shape in a direction of <011> or <0-11> on a (100) plane of an InP-based compound semiconductor crystal, and burying the step region with InP-based buried layers grown by vapor-phase growth by...

20060177952 - Process to make nano-structurated components: In a process to make a nano-structured component, such as a photonic crystal or an emitter (10) which can be led to incandescence through the passage of electric current, at least one layer made of anodized porous alumina (1) is used as sacrificial element for the structuring of at least...

20060177954 - Dicing tape attaching unit that can attach pre-cut dicing tape and general dicing tape to wafer and in-line system having the dicing tape attaching unit: A dicing tape attaching unit that can attach both a pre-cut dicing tape and a general dicing tape to a wafer in a semiconductor package assembling process, and an in-line system used in a semiconductor package process including the dicing tape attaching unit are provided. The dicing tape attaching unit...

20060177955 - Process for making a cmos image sensor: An image sensor includes a semi-conducting substrate having a photo-sensitive region and doping for forming a path to a charge-to-voltage mechanism; a dielectric spanning the substrate; and a semi-conducting layer, which is less than approximately 1 micrometer, spanning the dielectric which contains electrodes and circuit elements that control flow of...

20060177956 - Method of manufacturing a hermetic chamber with electrical feedthroughs: A method of manufacturing a hermetically-sealed chamber with an electrical feedthrough includes the step of hermetically fixing an electrode to a substrate in a predetermined location on the substrate. A passage is formed through the substrate through the predetermined location such that at least a portion of the electrode is...

20060177957 - Micromirror array device with a small pitch size: A spatial light modulator is disclosed, along with a method for making such a modulator that comprises an array of micromirror devices. The center-to-center distance and the gap between adjacent micromirror devices are determined corresponding to the light source being used so as to optimize optical efficiency and performance quality....

20060177958 - Method for producing an imaging device: The invention relates to a method for making an imagery device comprising at least one matrix of pixels made of a photon detecting semiconducting material (43), deposited on a substrate in which electronic devices are integrated and with metallic surfaces (42), in which a material capable of improving bond of...

20060177959 - Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces: Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces are disclosed herein. In one embodiment, a method for forming microlenses includes forming a plurality of shaping members on a microfeature workpiece between adjacent pixels, reflowing the shaping members to form a shaping structure between adjacent pixels, depositing...

20060177960 - Control module assembly: A control module assembly (100) includes a module housing (1) defining a receiving cavity (14) therein having a front opening, a printed circuit board (3) adapted to be housed in the receiving cavity, a header connector (2) including a number of contacts (6) mounted on the printed circuit board and...

20060177961 - Method for fabricating organic thin film transistor by application of electric field: A method for fabricating an organic thin film transistor by application of an electric field. The method includes the steps of fabricating a common organic thin film transistor including a gate electrode, a gate insulating layer, an organic semiconductor layer and source/drain electrodes laminated on a substrate, and applying a...

20060177962 - Process for producing n-type semiconductor diamond and n-type semiconductor diamond: A method of manufacturing n-type semiconductor diamond by the present invention is characterized in producing diamond incorporating Li and N by implanting Li ions into, so that 10 ppm thereof will be contained in, single-crystal diamond incorporating 10 ppm or more N, or else, in doping single-crystal diamond with Li...

20060177963 - Process for producing copy protection for an electronic circuit: It has proven particularly advantageous for the copy-protect layer (4) to be produced by applying a silicate glass by evaporation coating, since this means that an etching process which dissolves the copy-protect layer also attacks the substrate (1), in such a manner that the semiconductor structures (2) are at least...

20060177964 - Semiconductor module and method for producing a semiconductor module: The present invention provides a semiconductor module having: a semiconductor device (10) having a contact device (11) for making electrical contact with a connection device (17; 20) via a rewiring device (15, 15′, 15″); and a carrier device (12, 13, 14) for mechanically coupling the semiconductor device (10) to a...

20060177966 - Package or pre-applied foamable underfill for lead-free process: A B-stageable or pre-formed film underfill encapsulant composition that is used in the application of lead-free electronic components to substrates. The composition comprises an expandable microsphere, thermoplastic resin, thermoset resin, a latent catalyst, and a solvent. Various other additives, such as adhesion promoters, flow additives and rheology modifiers may also...

20060177965 - Semiconductor device and process for producing the same: Before a semiconductor chip having a plurality of bumps is mounted on a mount substrate (3) having a plurality of bumps (4) by flip chip bonding, a resist layer (5) having a thickness larger than that of the bumps (4) is formed on the mount substrate (3) with the bumps....

20060177967 - Manufacturing method of semiconductor device: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a...

20060177968 - Method for fabricating semiconductor packages with semiconductor chips: A method for fabricating semiconductor packages with semiconductor chips includes: providing a reel tape capable of being rolled up, the reel tape for accommodating at least one row of carriers; mounting at least one semiconductor chip in each of the carriers, wherein a plurality of electrode pads are provided on...

20060177969 - Method for interconnecting semiconductor components with substrates and contact means: A semiconductor component includes a substrate having a plurality of compliant contact bumps formed over a surface thereof. A semiconductor chip has a plurality of contact regions formed over a surface thereof. The compliant contact bumps of the substrate are electrically connected with the contact regions of the semiconductor chip...

20060177970 - Methods of adhering microfeature workpieces, including a chip, to a support member: Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes disposing a first adhesive on a surface of a microfeature workpiece, and disposing a second adhesive on a surface of a support member. The method can further...

20060177971 - Anisotropically conductive connector, production process thereof and application product thereof: Disclosed herein are an anisotropically conductive connector, by which positioning, and holding and fixing to a circuit device can be conducted with ease even when the pitch of electrodes of the circuit device to be connected is small, and moreover good conductivity can be achieved as to all conductive parts,...

20060177972 - Thin-film transistor and method for manufacturing the same: A thin-film transistor (100) of the present invention comprises a semiconductor layer (4), and a source region (5), a drain region (6), and a gate region (2) which formed on the semiconductor layer to be separated from each other. Said semiconductor layer is made of composite material, and said composite...

20060177973 - Generation method of light intensity distribution, generation apparatus of light intensity distribution, and light modulation element assembly: A generation method of a light intensity distribution uses a first light modulation element and a second light modulation element which are arranged to be apart from each other by a distance D and face each other in parallel to optically modulate a light beam which enters the light modulation...

20060177974 - Semiconductor thin film, thin film transistor, method for manufacturing same, and manufacturing equipment of semiconductor thin film: A method for manufacturing a semiconductor thin film is provided which can form its crystal grains having a uniform direction of crystal growth and being large in size and a manufacturing equipment using the above method, and a method for manufacturing a thin film transistor. In the above method, by...

20060177975 - Atomic layer deposition of ceo2/al2o3 films as gate dielectrics: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric...

20060177976 - Mos transistor forming method: A method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying the surface regions, including the step of negatively biasing the substrate placed in the vicinity of a plasma...

20060177978 - Manufacturing method of semiconductor device: A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is processed to form...

20060177977 - Method for patterning fins and gates in a finfet device using trimmed hard-mask capped with imaging layer: A capped trimming hard-mask patterning process to form ultra-thin structures can include depositing a hard-mask layer over a layer of patterning material, depositing an imaging layer over the hard-mask layer, patterning the imaging layer and the hard-mask layer, selectively trim etching the hard-mask layer to form a pattern hard mask,...

20060177980 - Capacitorless 1-transistor dram cell and fabrication method: A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor material such that a vertical...

20060177979 - Method of manufacturing a capacitor and a metal gate on a semiconductor device: A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom electrode layer in the capacitor...

20060177981 - Capacitors and methods of manufacture thereof: Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially...

20060177982 - Method of forming an eprom cell and structure therefor: An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate....

20060177983 - Method for forming a notched gate: Methods for forming notched gates and semiconductor devices utilizing the notched gates are provided. The methods utilize the formation of a dummy gate on a substrate. The dummy gate is etched to form notches in the dummy gate, and sidewall spacers are formed on the sidewalls of the notched dummy...

20060177984 - Method for manufacturing semiconductor elemental device: The present invention provides a method for manufacturing a semiconductor elemental device wherein a first gate oxide film and a second gate oxide film thicker than the first gate oxide film are formed on a substrate provided with a device forming region comprised of silicon, comprising the steps of implanting...

20060177985 - Source/drain extension implant process for use with short time anneals: The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135)...

20060177986 - High ft and fmax bipolar transistor and method of making same: A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion...

20060177987 - Methods for forming thin oxide layers on semiconductor wafers: An oxide layer on a silicon wafer may be removed by applying a process chemical such as hydrofluoric acid to the wafer. This will typically remove substantially all of the existing oxide layer, leaving a bare silicon surface. A high quality self-terminating chemical oxide layer may then be grown on...

20060177988 - Semiconductor fabrication processes: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide...

20060177989 - Substrate before insulation, method of manufacturing substrate, method of manufacturing surface acoustic wave transducer, surface acoustic wave device, and electronic equipment: A substrate before an insulation process, which is provided with a protection film to prevent a part of a surface area, which has electrical conductivity from being insulated, the substrate comprises: a base including the surface area, which has electrical conductivity; a protection film covering over the part of the...

20060177990 - Methods for selective integration of airgaps and devices made by such methods: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and...

20060177991 - Soi wafer production method: By using, in the so-called Smart Cut process comprising the steps of bonding an ion-implanted active layer wafer to a base wafer and later splitting off the base wafer to produce a SOI wafer, a wafer doped with C in a single crystal ingot growing process (desirably to a carbon...

20060177992 - Backside coating for mems wafer: A transparent substrate has a micro electromechanical system (MEMS) on a first side of the substrate. An opaque layer is formed on a second side of the transparent substrate opposite the first side. The opaque layer comprises a first material that is removable by a MEMS release process. A second...

20060177993 - Method for manufacturing soi substrate: The object of the invention is to provide a method for manufacturing an SOI layer which is devoid of damages, has a reduced variation in thickness, and is uniform in thickness. The object is met by providing a method for manufacturing an SOI substrate comprising the steps of forming an...

20060177994 - Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices: Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer...

20060177995 - Voltage sustaining layer with opposite-doped islands for semiconductor power devices: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when...

20060177996 - Doping method and method of manufacturing field effect transistor: A doping method comprising the steps of; obtaining a proportion X of ions of a compound including a donor or an acceptor impurity in total ions from mass spectrum by using a first source gas of a first concentration; analyzing a peak concentration Y of the compound in a first...

20060177997 - Methods of forming semiconductor devices with high-k gate dielectric: A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate...

20060177998 - Fully silicided gate structure for finfet devices: A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top...

20060177999 - Microelectronic workpieces and methods for forming interconnects in microelectronic workpieces: Methods for forming interconnects in blind holes and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having microelectronic dies with integrated circuits and terminals electrically coupled to the integrated circuits. In one embodiment, the method...

20060178000 - Epitaxial growth process: An epitaxial growth method forming a semiconductor thin film including a heterojunction of a group III-V compound semiconductor by means of molecular beam epitaxy. The method is configured to include: a first step of irradiating a molecular beam of at least one of group III elements and a molecular beam...

20060178001 - Method for fabricating interconnection in an insulating layer on a wafer and structure thereof: A method for fabricating an interconnection in an insulating layer on a wafer is described. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive...

20060178002 - Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer: Exemplary embodiments of the invention generally include methods for forming multilayer metal interconnect structures using dual damascene methods that incorporate a via capping process to protect lower interconnection lines from etching damage or oxidation, for example, that may be caused by inadvertent exposure of lower interconnection lines to etching atmospheres....

20060178003 - Use of germanium dioxide and/or alloys of geo2 with silicon dioxide for semiconductor dielectric applications: A method is disclosed for depositing a dielectric film on a substrate having a plurality of gaps formed between adjacent raised surfaces disposed in a high density plasma substrate processing chamber substrate. In one embodiment the method comprises flowing a process gas comprising a germanium source, a silicon source and...

20060178004 - Method of obtaining release-standing micro structures and devices by selective etch removal of protective and sacrificial layer using the same: A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film...

20060178005 - Pattern formation method: A resist film is first formed on a substrate. Subsequently, a first barrier film including a water-soluble solvent is formed on the resist film, and a second barrier film including an alcoholic solvent is formed on the first barrier film. Thereafter, with a liquid provided on the second barrier film,...

20060178006 - Supercritical fluid-assisted deposition of materials on semiconductor substrates: Supercritical fluid-assisted deposition of materials on substrates, such as semiconductor substrates for integrated circuit device manufacture. The deposition is effected using a supercritical fluid-based composition containing the precursor(s) of the material to be deposited on the substrate surface. Such approach permits use of precursors that otherwise would be wholly unsuitable...

20060178007 - Method of forming copper wiring layer: A method of forming a copper wiring layer, which includes forming a pattern of copper seed layer on a substrate, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating. At least one component of semiconductor device selected from the group consisting...

20060178008 - Post etch copper cleaning using dry plasma: A method for post-etch copper cleaning uses a hydrogen plasma with a trace gas additive constituting about 3-10 percent of the plasma by volume to clean a copper surface exposed by etching. The trace gas may be atomic nitrogen or other species having an atomic mass of 15 or greater....

20060178009 - Wafer stage with wafer positioning and alignment: Stage devices are disclosed for positioning a wafer or other substrate. Also disclosed are exposure systems that include such a stage device. The stage devices improve the accuracy and precision with which the wafer, adhesion-chucked to a chuck mounted to the stage device, is positioned. The stage devices also facilitate...

20060178010 - Member having plasma-resistance for semiconductor manufacturing apparatus and method for producing the same: In order to control and reduce generation of disjoined grains from a plasma-resistant member, the present invention provides a plasma-resistant member having no pores and boundary layers. In a layer structure made of yttria polycrystal and formed on a surface of a member for a semiconductor manufacturing apparatus on a...

20060178011 - Method of forming si tip by single etching process and its application for forming floating gate: The invention provides a method of forming a silicon tip by a single etching process, as well as a method of forming a tip floating gate to increase erase speed. Etching gases comprising (1) chlorine and/or (2) oxygen/helium are performed to form a silicon tip without bottom dimple. The invention...

20060178013 - Method of forming film pattern, device, method of manufacturing device, electro-optical device, and electronic apparatus: A method of forming a film pattern by disposing functional liquid on a substrate includes: forming banks on the substrate; disposing the functional liquid in regions partitioned by the banks; and drying the functional liquid disposed on the substrate. A material for forming the banks contains one of polysilazane, polysilane,...

20060178014 - Method of forming film pattern, device, method of manufacturing device, electro-optical device, and electronic apparatus: A method of forming a film pattern by disposing functional liquid on a substrate includes: forming banks on the substrate; disposing the functional liquid in regions partitioned by the banks; and drying the functional liquid disposed on the substrate. The forming of the banks includes forming a thin film on...

20060178012 - Method of forming semiconductor compound film for fabrication of electronic device and film produced by same: A process of forming a compound film includes formulating a nano-powder material with a controlled overall composition and including particles of one solid solution The nano-powder material is deposited on a substrate to form a layer on the substrate, and the layer is reacted in at least one suitable atmosphere...

20060178017 - Method for forming insulating film, method for forming multilayer structure and method for manufacturing semiconductor device: Disclosed is a method for effectively forming a Low-k insulating film. The method comprises the steps of: spin-coating on an underlying layer a precursor solution formed by dispersing Low-k materials in a solvent to form a coating film, subjecting the coating film to a baking treatment under heating for about...

20060178016 - Silicon carbide-based device contact and contact fabrication method: A silicon carbide-based device contact and contact fabrication method employ a layer of poly-silicon on a SiC substrate, with the contact's metal layer deposited on top of the poly-silicon. Both Schottky and ohmic contacts can be formed. The poly-silicon layer can be continuous or patterned, and can be undoped or...

20060178015 - Wet chemical treatment to form a thin oxide for high k gate dielectrics: Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms may be formed by two different...

20060178018 - Silicon oxynitride gate dielectric formation using multiple annealing steps: A method for processing a semiconductor substrate in a chamber includes forming a silicon oxynitride film using a two-step anneal process. The first anneal step includes annealing the silicon oxynitride film in the presence of an oxidizing gas that has a partial pressure of about 1 to about 100 mTorr,...

20060178019 - Low temperature deposition of silicon oxides and oxynitrides: The present invention relates to low temperature (i.e., less than about 450° C.) chemical vapor deposition (CVD) and low temperature atomic layer deposition (ALD) processes for forming silicon oxide and/or silicon oxynitride derived from silicon organic precursors and ozone. The processes of the invention provide good step coverage. The invention...

20060178020 - Semiconductor device fabrication method: According to the present invention, there is provided a semiconductor device fabrication method having: coating a semiconductor substrate with a silazane perhydride polymer solution prepared by dispersing a silazane perhydride polymer in a solvent containing carbon, thereby forming a coating film; forming a polysilazane film by volatilizing the solvent by...

20060172439 - Method of fabricating mram cells: A method of fabricating an MRAM cell including providing a workpiece having at least one magnetic tunnel junction (MTJ) formed thereon, forming an insulating layer made of non-conductive, isolating material over the at least one MTJ, using a damascene process to form at least two adjacent first trenches in the...

20060172440 - Transistor-level signal cutting method and structure: A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a...

20060172441 - Resist application method and device: The resist application method comprises the steps of: thermal processing for evaporating water from the surface of a wafer 10; making the surface of the wafer 10 hydrophobic with a hydrophobic processing material; and applying a resist onto the wafer 10, and the step of thermal processing to the step...

20060172444 - Efficient method of forming and assembling a microelectronic chip including solder bumps: The present invention provides a new technology approach for forming a contact layer in a microelectronic chip, which includes a plurality of solder bumps that are directly to be connected with a correspondingly designed carrier substrate. In the process flow, a plasma-based process for patterning the underbump metallization layer is...

20060172443 - Method to detect and predict metal silicide defects in a microelectronic device during the manufacture of an integrated circuit: The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning (110) a portion of a semiconductor substrate in a field of view of an inspection tool. The method also comprises producing (120) a voltage contrast image of the portion, wherein the image...

20060172442 - Semiconductor production system and semiconductor production process: A semiconductor manufacturing apparatus according to the present invention comprises: a treating unit that treats a substrate to manufacture thereon a semiconductor device; a fluid supplying channel for supplying a fluid required for a treatment of the substrate to the treating unit; a set voltage outputting unit that outputs a...

20060172445 - Method for determining properties of a film, and apparatus for realizing the method: A method for determining properties or a thin film includes the steps of: providing a piezoelectric substrate; providing a slanted finger interdigital transducer unit that includes a transmitter port and a receiver port on the piezoelectric substrate; forming the thin film on the piezoelectric substrate between the transmitter port and...

20060172446 - Semiconductor laser with a weakly coupled grating: A semiconductor laser with a semiconductor substrate, a laser layer arranged on the semiconductor substrate, a waveguide arranged parallel to the laser layer and a strip shaped grating structure is disclosed. The laser layer, the waveguide and the grating are arranged a configuration which results in weak coupling between the...

20060172447 - Multi-layer registration and dimensional test mark for scatterometrical measurement: A layered test pattern for measuring registration and critical dimension (CD) for multi-layer semiconductor integrated circuits is disclosed. A first layer includes a first pattern having vertical and horizontal portions. A second layer is formed over the first layer and includes a second pattern having vertical and horizontal portions having...

20060172448 - Screen printable electrode for light emitting polymer device: A screen printed light emitting polymer device is fabricated by depositing an electroluminescent polymer layer between a transparent electrode and an air stable screen printed top electrode. This invention describes advantageous methods and materials for printed top electrodes for polymer light emitting devices including composite electrode inks containing conducting particles,...

20060172449 - Method for manufacturing semiconductor laser diode: The present invention provides a semiconductor laser diode and a method for forming a semiconductor laser diode. After forming a first mask on a ridge structure forming region of a second conductivity type clad layer, ridge structure having vertical side surfaces is formed on an upper portion of the second...

20060172451 - Image sensor and related method of fabrication: An image sensor and related method of fabrication are disclosed. The image sensor comprises a plurality of photoelectric conversion regions disposed in a predetermined field of a semiconductor substrate, color filters arranged on the photoelectric conversion regions, and a reflection protection structure disposed between the photoelectric conversion regions and the...

20060172450 - Manufacturing method for image pickup apparatus: In an image pickup device, a step of forming an embedded plug includes a step of forming a connecting hole in the insulation film in which the embedded plug is to be formed, a metal layer deposition step of depositing a metal layer on the insulation film in which the...

20060172452 - Detector: A detector includes a CCD arrangement having at least one CCD, and a focusing device. The focusing device focuses spectrally separated light onto the CCD arrangement. The focusing device is located in an optical path before the CCD arrangement, and includes a microlens arrangement having at least one microlens....

20060172453 - Image sensor and manufacturing method of image sensor: In a manufacturing method of an image sensor, a lightproof film (an antireflective film for avoiding flares) is formed over a wiring area; a transparent film is formed over an imaging area using a material capable of patterning; a transparent film, for forming micro lenses on top, is formed on...

20060172454 - Molybdenum alloy: The invention relates to a molybdenum alloy that includes: 94 to 99 weight % of molybdenum; 0.5 to 6 weight % of niobium; and 0.01 to 1 weight % of zirconium. The invention also relates to metal substrates that include such a molybdenum alloy, and anode disks for rotating anode...

20060172455 - Making multicolor oled displays: A method of making an OLED display having at least first, second, and third differently colored pixels includes providing a first light-emitting layer over a substrate for the first and second pixels and a providing a second light-emitting layer over the substrate for the third pixel wherein the first and...

20060172457 - Chip-stacked semiconductor package and method for fabricating the same: A chip-stacked semiconductor package and a method for fabricating the same are proposed. A chip carrier module plate including a plurality of chip carriers, and a heat sink module plate including a plurality of heat sinks are provided, wherein a plurality of through holes are formed around each of the...

20060172456 - Device packages having stable wirebonds: A method of making a packaged electrical device comprises the steps of (a) connecting one end of a wire to a first point (e.g., a first electrical node) in the package, and (b) connecting the other end of the wire to a second point (e.g., a second electrical node) in...

20060172458 - Placement method of an electronic module on a substrate and device produced by said method: The aim the disclosed process is to ensure maximum precision both at the level of the manufacturing of an electronic assembly from a chip with small dimensions as well as the level of the placement of such an assembly on an insulating substrate. This aim is achieved by a placement...

20060172459 - Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (bga) package: A semiconductor multi-package module has stacked first and second packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid...

20060172460 - Semiconductor device and method of manufacture thereof, circuit board and electronic instrument: A method of manufacturing a semiconductor device comprises: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern...

20060172462 - Semiconductor multi-package module having inverted land grid array (lga) package stacked over ball grid array (bga) package: A semiconductor multi-package module has a second package inverted and stacked over a first package, each of the packages having a die attached to a substrate, in which the second package substrate and the first package substrate are interconnected by wire bonding, and in which the first package includes a...

20060172463 - Semiconductor multi-package module having wire bond interconnect between stacked packages: A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate...

20060172461 - Semiconductor stacked multi-package module having inverted second package: A semiconductor multi-package module has stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding, and in which the upper package is inverted. Also, a method for making a semiconductor multi-package module, by providing...

20060172464 - Method of embedding semiconductor element in carrier and embedded structure thereof: A method of embedding a semiconductor element in a carrier and an embedded structure thereof are proposed. First, a carrier having a hole is provided and an auxiliary material is attached to a side of the carrier. A semiconductor element is placed in the hole of the carrier. Then, a...

20060172465 - Device packages: Devices such as amplifiers are built on a heat sink having a perimeter wall surrounding active electronic devices. Surprisingly formation of wire bonds to such devices tends to be degraded if they have an aspect ratio greater than 2:1. This problem is overcome by forming wire bonds before such walls...

20060172466 - Semiconductor device and a method of manufacturing the same: A semiconductor device having improved performance and improvement manufacturing yield is provided. After a semiconductor integrated circuit including a phase change memory and a nonvolatile memory other than a phase change memory is formed in a semiconductor substrate, an inspection step such as a probe inspection is performed. In accordance...

20060172469 - Method of fabricating a polycrystalline silicon thin film transistor: An amorphous silicon (a-Si) layer is first formed on a substrate, and the a-Si layer is next patterned to form silicon islands for defining device active regions. Then, a single shot laser beam with long pulse is utilized to irradiate each silicon island, and lateral growth crystallization is induced in...

20060172468 - Method of making a planar double-gated transistor: A silicon layer interposed between the top silicon nitride layer (SiN) and a silicon germanium layer (SiGe) which in turn is over a thick oxide (BOX) is selectively etched to leave a stack with a width that sets the gate length. A sidewall insulating layer is formed on the SiGe...

20060172470 - Method of manufacturing thin film element: A method of manufacturing a thin film element is proposed, which can prevent the decrease in TFT manufacturing yield caused by the cracks occurring in an isolation layer at the time of the removing of an element formation substrate. A protection layer is formed between a plurality of TFTs, and...

20060172471 - Semiconductor device: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film...

20060172467 - Strained silicon devices transfer to glass for display applications: A method of fabricating strained silicon devices for transfer to glass for display applications includes preparing a wafer having a silicon substrate thereon; forming a relaxed SiGe layer on the silicon substrate; forming a strained silicon layer on the relaxed SiGe layer; fabricating an IC device on the strained silicon...

20060172472 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer;...

20060172474 - Method for fabricating a semiconductor device: A method for treating a gate stack in the fabrication of a semiconductor device by providing a substrate containing a gate stack having a dielectric layer formed on the substrate and a metal-containing gate electrode layer formed on the high-k dielectric layer, forming low-energy excited dopant species from a process...

20060172473 - Method of forming a two-layer gate dielectric: A substrate is provided, and a silicon dioxide thin film is formed thereon. Subsequently, an amorphous silicon thin film is formed over the silicon dioxide thin film, and a low temperature plasma nitridation process is preformed to form a nitrogen-containing amorphous silicon thin film. Following that, an oxygen annealing process...

20060172475 - Ultrathin soi transistor and method of making the same: A method of fabricating an ultrathin SOI memory transistor includes preparing a substrate, including forming an ultrathin SOI layer of the substrate; adjusting the threshold voltage of the SOI layer; depositing a layer of silicon oxide on the SOI layer; patterning and etching the silicon oxide layer to form a...

20060172476 - Fin field effect transistor and method for manufacturing fin field effect transistor: The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the...

20060172478 - Method for manufacturing integrated circuit having at least one silicon-germanium heterobipolar transistor: A method for manufacturing integrated circuits having at least one silicon-germanium heterobipolar transistor is provided, wherein a dielectric applied to the surface of the wafer is planarized. The dielectric having elevations produced by the thickness of monocrystalline semiconductor regions structured below the dielectric, wherein the semiconductor regions are covered by...

20060172479 - Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions: Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated....

20060172477 - Mos field effect transistor and manufacture method therefor: An MOS field effect transistor which improves the mobility of electrons and holes of an nMOS and a pMOS by applying larger tensile stress to a stressed Si channel in a lateral direction than that applied to a conventional structure without increasing a Ge composition of a buffer SiGe layer,...

20060172480 - Single metal gate cmos device design: A semiconductor device includes a PMOS transistor formed on a substrate structure. The PMOS transistor includes a source and a drain each including a diffusion region in the substrate structure, a channel region defined between the source and the drain, a gate dielectric over the channel region, and a gate...

20060172481 - Systems and methods that selectively modify liner induced stress: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a...

20060172482 - Semiconductor integrated circuit device having single-element type non-volatile memory elements: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is...

20060172483 - Dram arrays, vertical transistor structures and methods of forming transistor structures and dram arrays: The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to...

20060172484 - Method of forming a thin layer and method of manufacturing a flash memory device and a capacitor using the same: In a method of forming a thin layer and a method of manufacturing a flash memory and a capacitor using the same, a first thin layer may be formed on a substrate, and the thin layer may include one of metal, metal nitride and a combination thereof. A binding inhibitor...

20060172485 - Systems and methods for forming metal oxides using alcohols: A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process, one or more alcohols, and one or more metal-containing precursor compounds....

20060172486 - Selective etching to increase trench surface area: The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant...

20060172487 - High density fet with self-aligned source atop the trench: A method for manufacturing a power semiconductor device which includes forming a semiconductor region such as a polysilicon layer or epitaxially grown silicon over a region implanted with source implants and applying heat in a thermal step to cause the source implants to diffuse into the semiconductor region....

20060172488 - Semiconductor device manufacturing method: The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface...

20060172489 - Method for producing a dielectric material on a semiconductor device and semiconductor device: Method for producing a dielectric material on a semiconductor device with an atomic layer deposition procedure, whereby an aluminum oxide nitride or a silicon oxide nitride or an aluminum silicon oxide nitride layer is deposited comprising a rare earth metal-element. The invention describes a semiconductor device with a dielectric layer...

20060172493 - Forming multi-layer memory arrays: A method of forming a memory array includes forming a stack of two or more layers of memory material on a substrate, each layer of memory material having an array of memory cells, and forming one or more contacts that pass through each of the layers of memory material....

20060172490 - Method of improving flash memory performance: A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure,...

20060172492 - Mos transistor with fully silicided gate: An MOS transistor with a fully silicided gate is produced by forming a silicide compound in the gate separately and independently of silicide portions located in source and drain zones of the transistor. To this end, the silicide portions of the source and drain zones are covered by substantially impermeable...

20060172491 - Non-volatile memory structure and method of fabricating non-volatile memory: A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of...

20060172494 - Method for the production of a semiconductor component: To produce such a semiconductor component, at least one trench (2), which completely encompasses at least one part area of the front side and then is filled with an insulation (4) is etched into a silicon substrate (1). In the further course of the method, the entire area of the...

20060172495 - Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels: The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation...

20060172496 - Double-gate fets (field effect transistors): A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from...

20060172497 - Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top...

20060172498 - Semiconductor device having high dielectric constant gate insulating layer and its manufacture method: A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon...

20060172501 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a high-quality silicon epitaxial growth. (SEG) layer on a highly doped silicon substrate. The method includes providing a semiconductor substrate including dopant areas with a predetermined concentration, implanting group IV ions into the substrate, cleaning the substrate using a chlorine-based gas, and forming a...

20060172499 - Structure and method for thin box soi device: A method of forming a semiconductor device, comprising providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of...

20060172500 - Stucture and method to induce strain in a semiconductor device channel with stressed film under the gate: A semiconductor device is provided with a stressed channel region, where the stresses film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surround the channel region, and may apply...

20060172502 - Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps: A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embodiments, including but not limited to, the formation of recess, strained device...

20060172503 - Methods of forming silicide: Methods of fully siliciding semiconductive materials of semiconductor devices are disclosed. A preferred embodiment comprises depositing an alloy comprised of a first metal and a second metal over a semiconductive material. The device is heated, causing atoms of the semiconductive material to move towards and bond to the atoms of...

20060172504 - Fabrication process for increased capacitance in an embedded dram memory: An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a...

20060172507 - Method and system for 3d aligment in wafer scale integration: A substrate bonding system has a first and a second substrate table for holding a first substrate and a second substrate, respectively, and a controller. The first substrate includes a first device having first contact pads and the second substrate a second device having second contact pads. The wafer bonding...

20060172506 - Process for producing a semiconductor chip: In a process for producing a semiconductor chip, a functional semiconductor layer sequence (2) is grown epitaxially on a growth substrate (1). Then, a separating zone (4), which lies parallel to a main surface (8) of the growth substrate (1), is formed in the growth substrate (1) by ion implantation,...

20060172505 - Structure and method of integrating compound and elemental semiconductors for high-performace cmos: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such...

20060172508 - Process for transfer of a thin layer formed in a substrate with vacancy clusters: Processes for forming semiconductor structure comprising a transfer layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor on insulator (“SeOI”) structure can be formed using a donor substrate, a support substrate...

20060172509 - Method for reducing stress concentrations on a semiconductor wafer by surface laser treatment: A method for treating an area of a semiconductor wafer surface with a laser for reducing stress concentrations is disclosed. The wafer treatment method discloses treating an area of a wafer surface with a laser beam, wherein the treated area is ablated or melted by the beam and re-solidifies into...

20060172510 - Fabrication of stacked microelectronic devices: Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of microelectronic components in a batch fashion. In one embodiment, an adhesive payer is applied on a rear surface of a wafer. A plurality of spaced-apart adhesive pads...

20060172511 - In situ formed halo region in a transistor device: By performing a sequence of selective epitaxial growth processes with at least two different species, or by introducing a first dopant species prior to the epitaxial growth of a drain and source region, a halo region may be formed in a highly efficient manner, while at the same time the...

20060172513 - Method for producing semiconductor light emitting device, method for producing semiconductor device, method for producing device, method for growing nitride type iii-v group compound semiconductor layer, method for growing semiconductor layer, and method: A method for producing a semiconductor light emitting device is disclosed. The method comprises the step of growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality...

20060172512 - Substrate of gallium nitride single crystal and process for producing the same: The present invention relates to a method for producing an epitaxial substrate having a III-V group compound semiconductor crystal represented by the general formula InxGayAlzN (wherein, x+y+z=1, 0≦x≦1, 0≦y≦1, 0≦z≦1) having reduced dislocation density, comprising a first step of covering with a mask made of a different material from the...

20060172514 - Reducing wire erosion during damascene processing: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may...

20060172515 - Method of fabricating a structure in a material: A method of fabricating a structure in a material....

20060172516 - Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to...

20060172517 - Method for plasma-enhanced physical vapor deposition of copper with rf source power applied to the target: A method of performing physical vapor deposition of copper onto an integrated circuit in a vacuum chamber of a plasma reactor, includes providing a copper target near a ceiling of the chamber, placing an integrated circuit wafer on a wafer support pedestal facing the target, introducing a carrier gas into...

20060172518 - Method of patterning a layer of a material: The present invention reduces problems resulting from an incomplete removal of photoresist in a photolithographic process which are caused by a diffusion of contaminants from an anti-reflective coating into a layer of photoresist. A protective layer is formed over the anti-reflective coating, and the layer of photoresist is formed over...

20060172519 - Method for eliminating polycide voids through nitrogen implantation: A method of manufacturing a semiconductor device includes providing a first layer over a wafer substrate, providing a polysilicon layer over the first layer, implanting nitrogen ions into the polysilicon layer, forming a polycide layer over the polysilicon layer, and forming source and drain regions....

20060172520 - System and method for photolithography in semiconductor manufacturing: A method for forming a semiconductor device includes forming a photoresist layer over a substrate and patterning the photoresist layer to form photoresist portions. A second layer is formed over the substrate in areas not covered by the photoresist portions and the photoresist portions are removed. After removing the photoresist...

20060172521 - Method for allocating resources in heterogeneous nanowire crossbars having defective nanowisre junctions: Various embodiments of the present invention provide methods for allocating nanowire junctions in a nanowire crossbar having one or more randomly distributed non-functional crossbar nanowire junctions. In certain embodiments, the method constructs a circuit graph based on the circuit and constructs a crossbar graph based on the nanowire crossbar. A...

20060172522 - Method of fine patterning a metal layer: A method of fine patterning a metal layer which includes depositing a metal layer on a substrate; depositing, on the metal layer, a mask layer having a different degree of electrolytic dissociation than that of the metal layer; making a patterned substrate body; and dipping the substrate body into an...

20060172523 - Method for delineating a conducting element which is disposed on an insulating layer, and device and transistor thus obtained: A conducting layer is deposited on an insulating layer disposed on a substrate. A mask is formed on at least one area of the conducting layer, thus delineating in the conducting layer at least one complementary area not covered by the mask. The complementary areas of the conducting layer are...

20060172524 - Methods and apparatus for integrated circuit ball bonding with substantially perpendicular wire bond profiles: Techniques for ball bonding wires in an integrated circuit are provided which allow formation of desired wire bond profile shapes for optimal performance. A wire is ball bonded to a first bond site in the integrated circuit with a bonding tool and at least one bend is formed in the...

20060172525 - Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics: In an etch process for forming via openings and trench openings in a low-k dielectric layer, the material removal of an underlying etch stop layer is decoupled from the etching through the low-k dielectric in that the reduction in thickness is substantially achieved during the resist removal. For this purpose,...

20060172526 - Method for preventing edge peeling defect: A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming...

20060172527 - Method for forming a defined recess in a damascene structure using a cmp process and a damascene structure: The present invention provides a technique that enables the formation of a recessed upper surface of an interconnect line to form an inlaid barrier cap layer on top of an inter-connect line to exhibit improved characteristics with respect to electromigration, electrical conductivity, device reliability and performance. The recessed upper surface...

20060172528 - Methods of manufacturing semiconductor devices: Methods of manufacturing semiconductors are disclosed. One example method includes forming a trench through a dual damascene process, depositing a barrier metal layer on the overall surface, and depositing copper in the trench to form a copper line. The example method may also include performing a wet etching process to...

20060172530 - Cxhy sacrificial layer for cu/low-k interconnects: A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition CxHy on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3, using a PECVD process. In accordance with embodiments...

20060172531 - Sealing pores of low-k dielectrics using cxhy: A semiconductor method of manufacturing involving porous and/or carbon containing, low-k dielectrics is provided. The method includes forming a hydrocarbon of the general composition CxHy on the surface of the low-k dielectric. The hydrocarbon layer includes depositing a precursor material, preferably C2H4 or (CH3)2CHC6H6CH3. In accordance with embodiments of this...

20060172529 - Uniform passivation method for conductive features: The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the...

20060172532 - Method of manufacturing a magnetic head: In forming a narrow pattern, it is difficult to form a lift-off resist pattern with an overhang shape. Accordingly, it results in a phenomenon in which the angle at the end of the GMR layer is reduced to 45° or less. It is necessary to provide a lift-off resist pattern...

20060172533 - Method of fabricating printed circuit board: A method of fabricating a printed circuit board having a fine circuit pattern and a via hole having no residue by forming the circuit pattern using an imprinting process and forming the via hole using a laser....

20060172534 - Atomic layer deposition methods: A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber...

20060172535 - Etch process for improving yield of dielectric contacts on nickel silicides: The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer,...

20060172536 - Apparatus for plasma-enhanced physical vapor deposition of copper with rf source power applied through the workpiece: A method of performing physical vapor deposition of copper onto an integrated circuit in a vacuum chamber of a plasma reactor includes providing a copper target near a ceiling of the chamber, placing an integrated circuit wafer on a wafer support pedestal facing the target near a floor of the...

20060172537 - Method of forming thin film and method of fabricating oled: A method of forming a thin film and a method of fabricating an organic light emitting display device are provided. The method includes depositing a film formation material mixed with a deposition material and an additive material to form the thin film, and the additive material has a eutectic melting...

20060172538 - Wet etching the edge and bevel of a silicon wafer: A method and apparatus to selectively etch layers of various materials from the edge and bevel areas of the active side of a silicon wafer, as well as from the inactive side of a wafer are disclosed. The width of the etched edge generally varies from about 0.5 to about...

20060172539 - Method of treating a structured surface: The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and...

20060172540 - Reduction of feature critical dimensions using multiple masks: A method for forming features in an etch layer is provided. A first mask is formed over the etch layer wherein the first mask defines a plurality of spaces with widths. A sidewall layer is formed over the first mask. Features are etched into the etch layer through the sidewall...

20060172541 - Method of fabricating micro-needle array: A method of fabricating a micro-needle array is provided. The method of fabricating a micro-needle array having a substrate having a first surface and a second surface spaced in a predetermined interval apart from the first surface, includes patterning on the first surface, thereby forming a shape of micro-needle bodies....

20060172542 - Method and apparatus to confine plasma and to enhance flow conductance: The embodiments of the present invention generally relate to a method and an apparatus to confine a plasma within a processing region in a plasma processing chamber. The apparatus may include an annular ring with a gap distance with the chamber wall at between about 0.8 inch to about 1.5...

20060172543 - Graded junction termination extensions for electronic devices: A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated...

20060172546 - Dry-etching method: A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and...

20060172544 - Member for plasma etching device and method for manufacture thereof: A member for a plasma etching device, which comprises a device substrate comprising quartz glass, aluminum, alumite or a combination thereof and, formed on the surface thereof, a coating film of yttrium oxide or YAG having a film thickness of 10 μm or more and a variation in the thickness...

20060172545 - Purge process conducted in the presence of a purge plasma: The present invention provides, in one embodiment, a method for reducing defects associated with a plasma deposition or etching process. In this particular embodiment, the method includes creating a plasma in a deposition or etching chamber (140) and purging undesirable species from the deposition or etching chamber (150) in the...

20060172547 - Implantation of gate regions in semiconductor device fabrication: A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric...

20060172548 - Method of cleaning wafer and method of manufacturing gate structure: A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that...

20060172549 - Method of separating a mold from a solidified layer disposed on a substrate: The present invention is directed towards a method of separating a mold, included in a template, from a layer disposed on a substrate, the method including, inter alia, applying a separation force to the template to separate the template from the layer; and facilitating localized deformation in the substrate to...

20060172551 - Plasma gate oxidation process using pulsed rf source power: A method of fabricating a gate of a transistor device on a semiconductor substrate, includes the steps of placing the substrate in a vacuum chamber of a plasma reactor and introducing into the chamber a process gas that includes oxygen while maintaining a vacuum pressure in the chamber. An oxide...

20060172550 - Selective plasma re-oxidation process using pulsed rf source power: A transistor gate selective re-oxidation process includes the steps of introducing into the vacuum chamber containing the semiconductor substrate a process gas that includes oxygen while maintaining a vacuum pressure in the chamber. An oxide insulating layer on the order of several Angstroms in thickness is formed by generating a...

20060172552 - N2 based plasma treatment for enhanced sidewall smoothing and pore sealing porous low-k dielectric films: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner....

20060172553 - Method of retaining a substrate to a wafer chuck: The present invention is directed towards a method of retaining a substrate to a wafer chuck. The method features accelerating a portion of the substrate toward the wafer chuck, generating a velocity of travel of the substrate toward the wafer chuck, and reducing the velocity before the substrate reaches the...

20060172554 - Method of forming gate dielectric layer: A method for forming a gate dielectric layer is described. A silicon oxide layer is formed on a semiconductor substrate. Then, a first and a second nitrogen doping processes are performed in sequence to the silicon oxide layer using plasma comprising inert gas and gaseous nitrogen to form a gate...

20060172555 - Method to make silicon nanoparticle from silicon rich-oxide by dc reactive sputtering for electroluminescence application: A method of forming a silicon-rich silicon oxide layer having nanometer sized silicon particles therein includes preparing a substrate; preparing a target; placing the substrate and the target in a sputtering chamber; setting the sputtering chamber parameters; depositing material from the target onto the substrate to form a silicon-rich silicon...

20060172556 - Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor: The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure (230) over a substrate (210), and forming a strain inducing film (330, 520, 530 or 810) over the substrate (210) and proximate...