Semiconductor device manufacturing: process inventions 07/06

20060166379 - Method for manufacturing ferroelectric capacitor: A method for manufacturing a ferroelectric capacitor having a lower electrode, a ferroelectric film, and an upper electrode stacked on one another comprises the steps of performing batch dry-etching thereto, processing and forming the upper electrode, the ferroelectric film, and lower electrode, performing a process for removing reactive products adhered...

20060166378 - Method of producing semiconductor device: A semiconductor device incorporating a capacitor structure that includes a ferroelectric thin film is obtained by forming, on a single crystalline substrate 10 having a surface suited for growing thereon a thin film layer of ferroelectric single crystal having a plane (111), a ferroelectric single crystalline thin film 12′ containing...

20060166382 - Method and apparatus for detecting backside particles during wafer processing: A method and apparatus for detecting backside particles during wafer processing is provided. The method includes holding a wafer with vacuum pressure, detecting the presence of particles on a backside of the wafer while holding the wafer with vacuum pressure, transferring the wafer into a process chamber and performing a...

20060166380 - Method of integration testing for packaged electronic components: A method of integration testing for packaged electronic components is capable of improving a conventional testing for packaged electronic components. In this method, non-tested sides of the packaged electronic components are stuck with a downward exposure onto a testing carrier board so that conductive pins are oriented to test spaces...

20060166381 - Mold cavity identification markings for ic packages: The invention provides small-feature identifying markings for tracing completed IC packages to individual mold cavities. Preferred embodiments of the invention include IC packages and associated methods for forming indicia in a surface of an integrated circuit package in an arrangement indicative of a particular mold cavity. The indicia may be...

20060166383 - Semiconductor substrate having reference semiconductor chip and method of assembling semiconductor chip using the same: A semiconductor substrate having a reference semiconductor chip and a method of assembling semiconductor chips using the same are provided. According to the method, a semiconductor substrate having a plurality of semiconductor chips is provided. An identification mark is made on a reference semiconductor chip among the semiconductor chips. The...

20060166384 - Method for manufacturing industrial products and combination of masks for manufacturing the same: A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product...

20060166385 - Method for measuring peak carrier concentration in ultra-shallow junctions: A method is disclosed for determining peak carrier concentration in ultra shallow junctions of semiconductor samples. A region of the surface of the sample is periodically excited. The effects of the excitation are monitored by a probe beam. Synchronous detection produces in-phase (I) and quadrature (Q) signals. These signals are...

20060166388 - Led package structure and mass production method of making the same: An LED package structure includes a lower substrate, an upper substrate disposed on the lower substrate and having a though hole exposing a portion of the upper surface of the lower substrate; an individual LED unit disposed within the through hole in the upper substrate, a conductive pattern layer disposed...

20060166389 - Method for producing solid-state imaging device, solid-state imaging device, and camera: To provide a method for producing a solid-state imaging device enabling an improvement of a light sensitivity characteristic in a light receiving unit, a solid-state imaging device in which the light sensitivity characteristic is improved, and a camera provided with the solid-state imaging device. A shield film projected around the...

20060166386 - Optical semiconductor device and its manufacturing method: An optical semiconductor device (1) has a semiconductor substrate (2) made of InP, an active layer (7) which is formed in parallel with a top surface (2a) of the semiconductor substrate (2) above the semiconductor substrate (2), an n-type first cladding layer (6) made of InGaAsP which is formed under...

20060166387 - Optical transmission and/or receiving device: The invention relates to an optical transmitting and/or receiving device, having: a semiconductor component with a first contact for connection with a reference voltage and a second contact for applying or leading away a high-frequency electrical signal; an electrically conducting carrier substrate with a first surface and a second surface,...

20060166390 - Optoelectronic substrate and methods of making same: A method of producing an optoelectronic substrate by detaching a thin layer from a semi-conducting nitride substrate and transferring it to an auxiliary substrate to provide at least one semi-conducting nitride layer thereon, metallizing at least a portion of the surface of the auxiliary substrate that includes the transferred nitride...

20060166391 - Method of production of semiconductor light emission device and method of production of light emission apparatus: A method of production of semiconductor light emission devices for forming stripes of two multilayers having different emission wavelengths on a substrate, including the steps of: depositing a first multilayer including an active layer on the substrate; selectively etching the first multilayer to form a plurality of adjoining pairs of...

20060166392 - Semiconductor light emitting device and manufacturing method thereof: The present invention provides a semiconductor light emitting device where a spatial change in an In composition ratio is small within a plane of an active layer and device properties such as efficiency of light emission are excellent, and a manufacturing method thereof. An active layer having an InGaN quantum...

20060166393 - Manufacturing method of a mems structure, a cantilever-type mems structure, and a sealed fluidic channel: A method of manufacturing a MEMS structure including forming a porous layer having a predetermined thickness on the top surface of a substrate over an area where a cavity is to be formed; forming the cavity by etching the substrate below the porous layer; forming a membrane layer on the...

20060166394 - Solar cell structure with solar cells having reverse-bias protection using an implanted current shunt: A solar cell structure includes a solar cell of two or more semiconductor layers in facing contact with each other. The semiconductor layers constitute a semiconductor junction producing a voltage between the semiconductor layers when illuminated. A shunt formed of an altered material extends between and at least partially through...

20060166395 - High-density inter-die interconnect structure: An interconnect architecture for connecting a plurality of closely-spaced electrical elements on a first integrated circuit fabricated structure with operative circuits on a second integrated circuit fabricated structure. In one embodiment, the first integrated circuit fabricated structure comprises a plurality of photo sensors. Conductive interconnect elements on the first integrated...

20060166396 - Organic semiconductor structure, process for producing the same, and organic semiconductor device: There are provided an organic semiconductor structure comprising an organic semiconductor layer, which is large in size and homogeneous and has high charge transfer characteristics, a process for producing the same, and an organic semiconductor device. The organic semiconductor structure has, in at least a part thereof, an organic semiconductor...

20060166400 - Electronic assembly with integrated io and power contacts: In some example embodiments, an integrated circuit, electronic assembly and method provide a current path for supplying power to a processor. As an example, the integrated circuit includes a base having power contacts that extend from an upper surface of base. The integrated circuit further includes a substrate that is...

20060166401 - Hybrid package with non-insertable and insertable conductive features, complementary receptacle, and methods of fabrication therefor: A hybrid electronic circuit package (102, FIG. 1) includes non-insertable conductive features (110) and insertable conductive features (112) at a surface of the package. A hybrid receptacle (120), such as a socket, for example, includes non-insertable contacts (124) and insertable contacts (126), which are positioned in a complementary manner with...

20060166399 - Integrated circuit die connection methods and apparatus: This invention generally relates to methods and apparatus for connecting to an integrated circuit die, in particular where the die includes both analogue/microwave radio frequency (rf) circuitry and digital circuitry. A method of connecting a die having both microwave radio frequency (rf) circuitry and digital circuitry to a substrate of...

20060166398 - Off-grid decoupling of ball grid array (bga) devices and method: A multilayered printed wiring board having a ball grid array (BGA) land pattern in which each land in the pattern is connected to a respective via by a link connector, a method of adapting spacing between selected adjacent via and respective link pairs to receive decoupling capacitor pads, comprising rotating,...

20060166397 - Thermal enhanced package for block mold assembly: A heat spreader (20) is added to a package to enhance thermal and advantageously electrical performance. In manufacture a heat spreader precursor (24) is advantageously placed over a group of dies and secured after bonding (e.g., wire or tape bonding or flip-chip bonding) and before matrix/block mold. For example, a...

20060166402 - Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures: A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the...

20060166403 - Fabrication of advanced silicon-based mems devices: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a...

20060166405 - Manufacturing method of semiconductor device: A method of manufacturing a semiconductor device including a die pad section, a first semiconductor chip having a surface on which a first electrode section is formed, a second semiconductor chip having a surface on which a second electrode section is formed, a support member having a surface, lead terminal...

20060166404 - Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for assembling semiconductor devices: A rerouting element for a semiconductor device includes a substantially planar member that carries at least one contact location, at least one conductive, at least one rerouted bond pad. The contact location is positioned adjacent to a first periphered edge of the substantially planar member and at a location that...

20060166406 - Method of making a semiconductor chip assembly using multiple etch steps to form a pillar after forming a routing line: A method of making a semiconductor chip assembly includes providing a metal base that includes a metal plate and a metal layer, providing a routing line that contacts the metal layer and an etch mask that contacts the metal plate, providing a semiconductor chip that includes a conductive pad, mechanically...

20060166407 - Hermetic packaging: A method of hermetically packaging an electronic device (8), in an enclosure (2) comprising mutually inter-engageable first and second housing members (4, 6), comprising the steps of securing the electronic device (8) to the first housing member (4), engaging the first (4) and second (6) housing members such that an...

20060166408 - Method for encapsulating an electronic component using a foil layer: The invention relates to a method for encapsulating an electronic component, in particular a semiconductor, fixed on a carrier, comprising the processing steps of: a) placing at least one foil layer in a mould, b) placing the carrier in contact with the foil layer with the side remote from the...

20060166410 - Manufacturing method of semiconductor device: Before applying a resist on a first gate insulating film, a thinner is provided on an entire surface including a surface of the first gate insulating film to wash the surface of the first gate insulating film. Specifically, while a semiconductor substrate is being rotated, onto a central part thereof...

20060166412 - Method for manufacturing semiconductor elemental device: The present invention provides a method for manufacturing a semiconductor elemental device comprising an SOI structure in which an SOI layer is laminated, comprising the steps of setting transistor forming regions and a device isolation region to the SOI layer, forming a pad oxide film over the SOI layer and...

20060166409 - Method of preparation of a precursor oligocene: The synthesis of a precursor oligocene, particularly pentacene, is a two-step process. In the fist step the Diels-Alder adduct of the a,b-dihydro-a,b-etheno-oligocene with a 1,1-dialkoxy-cyclopentadiene is formed. In the second step this Diels-Alder adduct is converted into the precursor oligocene, in that first the corresponding keto-compound is formed, which may...

20060166414 - Selective deposition: A method for epitaxially forming a silicon-containing material on a substrate surface utilizes a halogen containing gas as both an etching gas as well as a carrier gas through adjustments of the process chamber temperature and pressure. It is beneficial to utilize HCl as the halogen containing gas because converting...

20060166411 - Semiconductor device and manufacturing method thereof: An object of the invention is to provide a semiconductor device and a display device which can be manufactured with improved material efficiency through a simplified manufacturing process, and a manufacturing method thereof. Another object is to provide a technique capable of forming a pattern such as a wiring included...

20060166413 - Thin film transistor device and method of manufacturing the same: A semiconductor film is formed on a substrate. Subsequently, a resist film is formed on the semiconductor film, and dry etching is performed to the semiconductor film using the resist film as a mask. Due to the dry etching, the edge portion of the semiconductor film protrudes from the resist...

20060166415 - Two-transistor tri-state inverter: A two-transistor tri-state inverter is provided, made from a NMOS dual-gate thin-film transistor (DG-TFT) having a top gate, a back gate, and source/drain regions. A PMOS DG-TFT also has a top gate, a back gate, and S/D regions, and the NMOS first S/D region is connected to a PMOS first...

20060166416 - Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar...

20060166417 - Transistor having high mobility channel and methods: Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is...

20060166418 - Method of fabricating semiconductor device: Provided is a method of fabricating a semiconductor device, the method including: forming an insulating layer on a single crystal substrate; etching the insulating layer in a predetermined pattern to expose the surface of the single crystal substrate; depositing an amorphous material on the insulating layer and the exposed surface...

20060166419 - Method for manufacturing semiconductor device: The method for manufacturing a semiconductor device according to the invention includes forming a thick silicon oxide film uniformly in a trench. Argon ions or the like implanted obliquely into the trench to form an ion implanted damaged region selectively in the portion of the silicon oxide film on the...

20060166420 - Method of manufacturing a semiconductor device: In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel...

20060166421 - Semiconductor device fabrication method: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a conductive layer on the first insulating film; exposing the first insulating film by removing a portion of the conductive layer; forming a second insulating film...

20060166424 - Metal gate transistor cmos process and method for making: A method for forming a semiconductor device (100) includes a semiconductor substrate (102) having a first region (104), forming a gate dielectric (108) over the first region, forming a conductive metal oxide (110) over the gate dielectric, forming an oxidation resistant barrier layer (111) over the conductive metal oxide, and...

20060166427 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprises: forming a device isolation, a first conductivity type region, and a second conductivity type region on a semiconductor substrate; depositing a gate insulating film on an entire surface of the semiconductor substrate; forming a first metal film on the gate insulating film;...

20060166426 - Methodology for placement based on circuit function and latchup sensitivity: A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element attributes of elements associated with the at least one functional circuit block. An element density function parameterized from the element attributes...

20060166425 - Novel gate dielectric and metal gate integration: A CMOS device is provided which comprises (a) a substrate (103); (b) a gate dielectric layer (107) disposed on the substrate, the gate dielectric comprising a metal oxide; (c) an NMOS electrode (105) disposed on a first region of said gate dielectric; and (d) a PMOS electrode (115) disposed on...

20060166423 - Removal spacer formation with carbon film: A method of making a CMOS device, and a product made by the process. The process includes applying a layer of a carbon film or carbon-containing compound to a substrate. A section of the carbon is etched with a plasma, e.g., an O2, Ar, N2, or He plasma. Ion-implantation, e.g.,...

20060166422 - Sige nickel barrier structure employed in a cmos device to prevent excess diffusion of nickel used in the silicide material: A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate...

20060166428 - Semiconductor device and method of fabricating the same: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the first insulating film; forming a second insulating film on the first conductive layer in a first processing chamber isolated from...

20060166429 - Vertical replacement-gate junction field-effect transistor: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is...

20060166430 - Conductive memory stack with non-uniform width: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face...

20060166431 - Methods to form electronic devices and methods to form a material over a semiconductive substrate: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure...

20060166432 - Process for oxide cap formation in semiconductor manufacturing: A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are then exposed...

20060166433 - Recessed collar etch for buried strap window formation without poly2: A method for manufacturing a trench capacitor with a reduced resistance in a buried strap window for use in a memory circuit such as a dynamic random access memory circuit may be realized by reducing the number of polysilicon layers that are deposited. The method includes the deposition of a...

20060166434 - Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit: A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first...

20060166436 - Forming integrated circuit devices: Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask layer further overlies a second mask layer overlying a second portion of the semiconductor substrate. The first mask layer overlying the first portion of the...

20060166437 - Isolation regions for semiconductor devices and their formation: A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas of the substrate for future isolation regions of the semiconductor device. Portions of the substrate are removed in the areas for future isolation regions,...

20060166439 - Method for manufacturing electronic non-volatile memory devices integrated in a semiconductor substrate: A method manufactures a non-volatile memory device on a semiconductor substrate that includes a matrix of memory cells and associated circuitry. The method includes: forming a filling dielectric layer on the whole substrate until gates of the cells and a conductive layer of the circuitry are completely covered, removing the...

20060166438 - Method of making a floating gate non-volatile mos semiconductor memory device with improved capacitive coupling and device thus obtained: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode...

20060166441 - Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same: A non-volatile memory device with a non-planar gate insulating layer and a method of fabricating the same are provided. The device includes a tunnel insulating pattern, a charge storage layer, an upper insulating layer and a control gate electrode which are sequentially stacked. A lower insulating pattern, which is covered...

20060166440 - Semiconductor nonvolatile memory device, and manufacturing method thereof: The present invention realizes a semiconductor nonvolatile memory device where a leak current does not easily flow through a tunnel insulating film, and a manufacturing method thereof A silicon nitride oxide film constituting a tunnel insulating film is formed by radically nitriding a surface of a silicon oxide film. The...

20060166435 - Synthesis of ge nanocrystal memory cell and using a block layer to control oxidation kinetics: A structure and a method of manufacturing a memory devices using nanoncrystals. A first embodiment is characterized as follows. We form a first gate insulator over the substrate. The first gate insulator is comprised of an oxide layer and blocking layer. We form a SiGe layer over the first gate...

20060166442 - Method for manufacturing semiconductor device: In a method for manufacturing a semiconductor device, a mask layer is formed on a semiconductor substrate. The mask layer and the substrate are patterned to form a device isolation layer defining an active region. The mask layer and the substrate are patterned in the active region to form a...

20060166443 - Multi-state nrom device: An array of NROM flash memory cells configured to store at least two bits per four F2. Split vertical channels are generated along each side of adjacent pillars. A single control gate is formed over the pillars and in the trench between the pillars. The split channels can be connected...

20060166444 - Mems scanning mirror with trenched surface and i-beam like cross-section for reducing inertia and deformation: A micro-electro-mechanical system (MEMS) device includes a mirror having a top surface with trenches, a beam connected to the mirror, rotational comb teeth connected to the beam, and one or more springs connecting the beam to a bonding pad. The mirror can have a bottom surface for reflecting light. The...

20060166445 - Methods of fabricating multiple sets of field effect transistors: The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate...

20060166446 - Manufacturing method of semiconductor device, semiconductor manufacturing apparatus, plasma nitridation method, computer recording medium, and program: An object of the present invention is to prevent an increase in film thickness and inhibit a reduction in capacity of a capacitor. In a semiconductor device having a capacitor, the capacitor includes a lower electrode, an upper electrode, and an insulating film interposed between the lower electrode and the...

20060166447 - Method for making a semiconductor device having a high-k gate dielectric: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate...

20060166448 - Apparatus for depositing seed layers: One embodiment of the present invention is an apparatus for depositing seed layers over a substrate, said substrate includes at least one opening surrounded by a field, the apparatus includes: (a) a CVD chamber adapted to deposit a CVD seed layer over the substrate; (b) a PVD chamber adapted to...

20060166449 - Nonvolatile memory device for storing multi-bit data: A semiconductor nonvolatile memory device for storing multi-bit data has a memory cell having a source region S and a drain region D formed at the surface of a semiconductor substrate, a gate insulator film and a control gate CG formed on a channel region CH between the source region...

20060166450 - Method for manufacturing substrate: A substrate including an SOI region and a bulk region having an improved flatness is provided. In the process for manufacturing the patterned SOI substrate 100, a concave portion is previously produced by the bulk region 103 in silicon substrate 104. Therefore, the height of the step produced in the...

20060166451 - Process for manufacturing a multilayer structure made from semiconducting materials: The invention relates to a process for manufacturing a multilayer structure made from semiconducting materials that include an active layer, a support layer and an electrically insulating layer between the active layer and the support layer. The process includes the step of modifying the density of carrier traps or the...

20060166452 - Non-volatile nanocrystal memory and method therefor: A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals...

20060166453 - Method and apparatus for forming patterned photosensitive material layer: A method for forming a patterned photosensitive material layer over a substrate is described. A photosensitive material layer is formed on a substrate and then exposed. The selected parameters of the photosensitive material layer or between the photosensitive material layer and the predetermined layer are measured for determining whether the...

20060166454 - Low tolerance polysilicon resistor for low temperature silicide processing: Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation....

20060166455 - Multilevel programming of phase change memory cells: A method for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase...

20060166456 - Semiconductor device and manufacturing method thereof: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area...

20060166457 - Method of making transistors and non-silicided polysilicon resistors for mixed signal circuits: A method for manufacturing a semiconductor wafer 10 that includes implanting source/drain regions 75 within a top surface of the semiconductor substrate 20, forming a dielectric capping layer 170 over the semiconductor wafer 20, and annealing the semiconductor wafer 10 to activate sources/drains 70. The method further includes forming a...

20060166458 - Method for forming shallow trench isolation structures: A shallow trench isolation (STI) structure for semiconductor devices is formed using a deposited silicon layer formed over a polish stop layer formed over an oxide formed on a substrate. The polish stop layer may be nitride. An opening is formed extending through the deposited silicon layer and the nitride...

20060166459 - Semiconductor apparatus and method of producing the same: the inner wall oxidizing step being performed by wet oxidization with a low concentration of moisture mixed in oxygen to form the oxide film so that a stress caused between the oxide film and the silicon substrate is not greater than 3.5×109 (dyne/cm2) and a radius at a corner of...

20060166460 - Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process...

20060166461 - Method of producing mixed substrates and structure thus obtained: The inventive method includes a preparation step during which the substrate is covered with a layer, a pressing step in which a mould including a pattern of recesses and protrusions is pressed into part of the thickness of the aforementioned layer, at least one etching step in which the layer...

20060166462 - Method for manufacturing semiconductor wafer: A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first...

20060166463 - Method of producing a device with a movable portion: A method of producing a device with a movable portion spaced apart from a support wafer comprises a step of providing the support wafer having a structured surface and a further step of providing a device wafer with a backing layer and a device layer disposed thereon. Further, the method...

20060166464 - Method and device for machining a wafer, in addition to a wafer comprising a separation layer and a support layer: A process and an apparatus are described for the treatment of wafers, in particular for the thinning of wafers. A wafer with a carrier layer and an interlayer arranged between the carrier layer and the wafer is also described, in which the interlayer is a plasmapolymeric layer that adheres to...

20060166465 - Method of dividing wafer: To eliminate necessity of separation of a resist film in dicing by etching and thus improve productivity and die strength of a device, thickness of the resist film is adjusted such that when street-correspondent-areas are separated by etching, resist films coated on portions other than the street-correspondent-areas are not remained....

20060166466 - Semiconductor manufacturing method of die-pick-up from wafer: A manufacturing method of a semiconductor device comprising the steps of: affixing a die attach film and a dicing film to a back surface of a semiconductor wafer: thereafter dicing the semiconductor wafer and the die attach film to divide the semiconductor wafer into a plurality of semiconductor chips: thereafter...

20060166467 - Method of producing microcrystalline silicon germanium suitable for micromachining: A method of depositing a structural SiGe layer is presented. The structural SiGe layer may be located on top of a sacrificial layer above a substrate. The substrate may contain a semiconductor device such as a CMOS electronic circuit. The presented method uses a silicon source and a germanium source...

20060166468 - Semiconductor substrate, semiconductor device, light emitting diode and producing method therefor: A semiconductor substrate including a gallium arsenide layer is obtained by executing a step of preparing a first substrate having a separating layer constituted of germanium and a gallium arsenide layer on the separating layer, a step of preparing a bonded substrate by bonding the first substrate and a second...

20060166470 - Method of irradiating a laser beam, apparatus for irradiating a laser beam and method of fabricating semiconductor devices: When a CW laser is irradiated to a semiconductor film while scanning relatively during a production process of a semiconductor device, elongated crystalline particles extending in the scanning direction are formed. The semiconductor film thus formed has characteristics substantially equal to a single crystal in the scanning direction. However, since...

20060166469 - Method of laser beam maching and laser beam machining apparatus: An object of the invention is to credibly crystallize an amorphous material for use as a semiconductor material and effect crystallization to a region of desired scope. A first region drawn on a surface of a layer of amorphous material formed on the surface layer of sample (21) is irradiated...

20060166471 - Memory apparatus and production method: The memory apparatus according to the invention and having a cell 14 has a high electrical resistance in a first state and a low electrical resistance in a second state. The cell 14 has an edge area 16 and a core area 15, in which the electrical resistivity in the...

20060166472 - Cleaving process to fabricate multilayered substrates using low implantation doses: A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave...

20060166473 - Method of forming schottky diode with charge balance structure: a Schottky diode having a semiconductor region is formed as follows. A plurality of charge control electrodes are formed in the semiconductor region so as to influence an electric field in the semiconductor region, wherein at least two of the charge control electrodes are adapted to be biased differently from...

20060166474 - Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow: A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt...

20060166475 - Method for the production of stree-relaxed layer structure on a non-lattice adapted substrate and utilization of said layer system in electronic and/or optoelectronic components: The invention relates to a method for the production of a monocrystalline, stress-relaxed layer structure having one or several layers on a substrate with different grid structure. In a special embodiment, the method can be advantageously used for the production of relaxed silicon on a stress-related Si—Ge layer structure. The...

20060166476 - Method of forming a dielectric structure having a high dielectric constant and method of manufacturing a semiconductor device having the dielectric structure: In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference...

20060166477 - Wafer level electro-optical semiconductor manufacture fabrication mechanism and a method for the same: A wafer-level electro-optical semiconductor fabrication mechanism and method for the same which improves upon traditional electro-optical semiconductor grain packaging methods. The present invention electrically connects semiconductor grains to the grains on a top surface of a wafer. this is done by either screen-printing or steel board-printing solder or silver paste...

20060166478 - Nitride semiconductor device and its manufacturing method: A method for fabricating nitride semiconductor devices according to the present invention includes the steps of: (A) providing a nitride semiconductor substrate, which will be split into chip substrates, which includes device portions that will function as the respective chip substrates when the substrate is split and interdevice portions that...

20060166479 - Interconnection device for a printed circuit board, a method of manufacturing the same, and an interconnection assembly having the same: The present invention relates to an interconnect device for a printed circuit board, a method of manufacturing the same and an inter-connect assembly having the same. According to one aspect of the present invention, the interconnect device for a printed circuit board comprises: a first contact section 10 having a...

20060166480 - Interconnection of through-wafer vias using bridge structures: Bridge structures provide a surface on which to form interconnections to components through through-hole vias. The bridge structures at least partially, and preferably fully, span the gap between two wafers, and, more specifically, between a through-hole via in one wafer and a corresponding component on the other wafer. Bridge structure...

20060166481 - Method of forming metal layer pattern and method of manufacturing image sensor using the same: A method of forming a metal layer pattern comprises forming an interlayer insulating layer on a semiconductor substrate, forming a metal layer on the interlayer insulating layer, forming a mask pattern to expose a predetermined area of the metal layer, and forming a metal layer pattern by dry etching the...

20060166482 - Semiconductor device manufacturing device: A process for production of a semiconductor device having a multi-layer wiring of dual damascene structure in a low-dielectric constant interlayer insulating film. The process consists of the following steps. A first insulating film (6) and a second insulating film (7) are formed. A first to third mask forming layers...

20060166484 - Method for cu metallization of highly reliable dual damascene structures: The present invention provides a method for forming a void-free copper damascene structure comprising a substrate having a conductive structure, a first dielectric layer on the substrate, a diffusion barrier layer on the first dielectric layer, and a second dielectric layer on the barrier layer. The method comprises forming via...

20060166486 - Method of forming a semiconductor device having air gaps and the structure so formed: A method of forming a semiconductor device. Depositing alternating layers of a first and a second dielectric material, wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material...

20060166483 - Method of manufacturing a semiconductor device and semiconductor device obtained by using such a method: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) and a substrate (2) comprising at least one semiconductor element (3) and provided with at least one connection region (4) and an overlying stripe-shaped connection conductor (5) which is connected to the connection...

20060166485 - Methods for making dual-damascene dielectric structures: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In...

20060166487 - Method and apparatus for chemical mechanical polishing of semiconductor substrates: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a...

20060166488 - Semiconductor device and method for manufacturing the same: An object of the present invention is to improve the inter-layer adhesiveness of the diffusion barrier film while maintaining the lower dielectric constant of the diffusion barrier film. A diffusion barrier film for a copper interconnect comprises an insulating material containing silicon, carbon, hydrogen and nitrogen as constituent elements, and...

20060166490 - Forming buried via hole substrates: A preformed copper plug may be inserted into a via hole in a package substrate. The opposed surfaces of the copper preform may be covered with a solder material. Copper foils may then be applied over the core and over the preformed plug. A vacuum hot press method may be...

20060166489 - Semiconductor constructions: The invention includes methods of forming openings extending through electrically insulative layers to electrically conductive materials. In an exemplary aspect, a substrate is provided which supports a stack and an electrical node. The stack comprises an electrically insulative cap over an electrically conductive material. An electrically insulative layer is formed...

20060166491 - Dual damascene interconnection having low k layer and cap layer formed in a common pecvd process: A method of fabricating dual damascene interconnections begins by forming on a substrate a dielectric layer by a PECVD process that employs a first precursor gas. A capping layer is formed on the dielectric layer by a PECVD process that also employs the first precursor gas such that deposition of...

20060166493 - Semiconductor device having nitridated oxide layer and method therefor: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to...

20060166492 - Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration: A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably...

20060166494 - Method of manufacturing a semiconductor device that includes a contact plug: A method of manufacturing a semiconductor device including a contact plug includes forming an insulation interlayer pattern and a protection pattern for protecting the insulation interlayer pattern using a mask pattern. The insulation interlayer includes a contact hole through which a surface of the substrate is partially exposed. A spacer...

20060166495 - Contact structure formed using supercritical cleaning fluid and alcvd: A supercritical fluid such as CO2 cleans an opening formed in a Si-containing dielectric material and removes polymeric and organic residue produced by the etching process used to form the opening. The opening may be a contact, via or other opening and may include a cross-sectional area of less than...

20060166496 - Incorporating dopants to enhance the dielectric properties of metal silicates: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a...

20060166497 - Method of fabricating conductive lines: A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and...

20060166498 - Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same: A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than the second opening. A first conductive material is formed over the semiconductor wafer to...

20060166499 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures...

20060166500 - Electroprocessing profile control: A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a first electroprocessing zone between the electrode and the substrate, and biasing a second electrode disposed radially outward of substrate with...

20060166501 - Method and apparatus for monolayer deposition: An adaptive real time thermal processing system is presented that includes a multivariable controller. The method includes creating a dynamic model of the MLD processing system and incorporating virtual sensors in the dynamic model. The method includes using process recipes comprising intelligent set points, dynamic models, and/or virtual sensors....

20060166502 - Semiconductor constructions: The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and a peripheral region proximate the memory array region. The memory array region has a higher average elevational height than the peripheral region. Polysilazane is formed...

20060166503 - Polishing apparatus and polishing method: A polishing apparatus has a polishing section (302) configured to polish a substrate and a measurement section (307) configured to measure a thickness of a film formed on the substrate. The polishing apparatus also has an interface (310) configured to input a desired thickness of a film formed on a...

20060166504 - Profiled standoff structure and method for optical display package: A method for forming a standoff structure for devices, e.g., optical devices, integrated circuit devices, micro-electrical mechanical systems (i.e., MEMS). The method includes providing a substrate (e.g., silicon wafer), which has a first surface region characterized by a <100> crystal orientation, a second surface region, and a thickness defined between...

20060166505 - Integrated process for thin film resistors with silicides: The formation of devices in semiconductor material. In one embodiment, a method of forming a semiconductor device is provided. The method comprises forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of...

20060166506 - Mask material for reactive ion etching, mask and dry etching method: To provide a dry etching method and the like that can precisely process regions targeted for etching of objects to be processed using reactive ion etching that uses carbon monoxide gas, to which a nitrogen-containing compound gas is added, as a reactive gas. A material containing silicon and tantalum is...

20060166507 - Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean: Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to a plasma containing the same dopant species as in the semiconductor material so as to partially, completely, or...

20060166508 - Topography transfer method with aspect ratio scaling: The present invention is a method of applying a topographical surface to a part such as a substrate without the need for low temperature softening of that part while retaining high aspect ratios and densely packed features in that topography. A substrate, selected for its ability to be processed at...

20060166509 - Method to avoid alpha-si damage during wet stripping processes in the manufacture of mems devices: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of...

20060166510 - Semiconductor manufacturing method for die bonding: The present invention has a pump system having a gear pump to which a gear structure, having a pump gear and a driving gear concentrically and integrally formed with each other, is incorporated; a main control section for controlling this pump system; and a stage that can support a plate-like...

20060166511 - Method for treatment of film or sheet: A film or sheet containing an optionally crosslinked organic polymer having a high degree of crosslinking and having a little amount of residual solvent is obtained within a short period of time under a low pressure by bringing a film or sheet containing an organic polymer into contact with a...

20060166512 - Methods of forming a thin film and methods of manufacturing a capacitor and a gate structure using the same: wherein M represents a metal in listed in Group 4A of the periodic table of elements, R1, R2 and R3 independently represent hydrogen or an alkyl group having a carbon number from 1 to 5, and X represents hydrogen or an alkyl group having a carbon number from 1 to...

20060166513 - Method and apparatus for forming thin film of semiconductor device: A method of forming a high quality thin film on a semiconductor substrate includes supplying a first gas to change a crystal structure of a semiconductor substrate, and a second gas to form a thin film on the semiconductor substrate; sputtering the first gas in a plasma state to the...

20060166515 - In-situ-etch-assisted hdp deposition: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of...

20060166514 - Teos deposition method: A TEOS deposition method. A mixture of gases is introduced into a process chamber, in which the mixture of gases comprises tetra-ethyl-ortho-silicate (TEOS) and N2. Compressive stress of a TEOS oxide film is increased by activating the mixture of gases....

20060166516 - Nitride film forming method, semiconductor device fabrication method, capacitor fabrication method and nitride film forming apparatus: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of...

20060166517 - Phase-shifting mask and semiconductor device: Disclosed is a phase-shifting mask having a pattern comprising a plurality of substantially transparent regions and a plurality of substantially opaque regions wherein the mask pattern phase-shifts at least a portion of incident radiation and wherein the phases are substantially equally spaced, thereby increasing resolution of a given lithographic system....

20060166518 - Subtractive-additive edge defined lithography: A subtractive-additive, differential lithography technique capable of generating sub-half micron geometries using a larger feature parent mask is described. The basic technique is defect tolerant with respect to electrical shorting, can fabricate T-shaped conductors of optimum geometry to minimize electrical RC time constant, and can be extended to very small,...

20060160249 - Method for fabricating biochips or biosensors using cd/dvd making compatible processes: A method of manufacturing a plastic biochip or a biosensor test strip, which is compatible with standard CD/DVD making processes. The method includes substrate injection press molding, followed by seamless magnetic biosensor sputtering. If necessary, the sputtered biosensor is cut off from the substrate....

20060160250 - Modular fabrication systems and methods: The present invention relates to an article fabrication system having a plurality of material deposition tools containing one or more materials useful in fabricating the article, and a material deposition device having a tool interface for receiving one of the material deposition tools. A system controller is operably connected to...

20060160248 - N-glycoside type glycolipids and hollow fiber type organic nanotubes made of the same: (In the formula, G represents a saccharide radical other than a hemiacetal hydroxyl group bonded to the anomer carbon atom of the saccharide, and R represents an unsaturated hydrocarbon group containing ten to 39 carbon atoms.) This molecule self-aggregates and forms hollow fiber shaped organic nanotubes in water when this...

20060160247 - Unsaturated carboxylic acid hemicacetal ester, polymeric compound and photoresist resin composition: wherein Ra is a hydrogen atom, a halogen atom, an alkyl group of carbon number 1 to 6 or a haloalkyl group of carbon number 1 to 6, Rb is a hydrocarbon group having a hydrogen atom at a first poison, Rc is a hydrogen atom or a hydrocarbon group...

20060160251 - Method in the fabrication of a memory device: In a method for fabricating a memory device based on an electrically polarizable memory material in the form of an electret or ferroelectric material, the memory device comprises one or more layers with circuit structures provided exclusively or partially in a printing process. At least one protective interlayer is provided...

20060160252 - Methods for fabricating ferroelectric memory devices with improved ferroelectric properties: Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one...

20060160253 - Method and apparatus for wafer temperature regulation: A method and apparatus for regulating the temperature a wafer is provided. The apparatus may include a temperature controlling unit provided within the chamber and regulating the temperature of the wafer; a wafer support pin for adjusting the position of the wafer with respect to the temperature controlling unit; and/or...

20060160255 - Driving circuit for amoled display and driving method thereof: A driving circuit and method for an active matrix organic light emitting diode (AMOLED) display are provided. The driving circuit comprises a power circuit, a linear thermistor, and a pixel circuit. The power circuit provides an equivalent current. The linear thermistor coupled to the power circuit adjusts the equivalent current...

20060160256 - Method of inspecting substrate processing apparatus, and storage medium storing inspection program for executing the method: A method of inspecting a substrate processing apparatus that enables a reduction in operator labor time to be achieved. A host computer instructs a substrate processing apparatus to prohibit transfer of a product wafer into the substrate processing apparatus during a period of cleaning the substrate processing apparatus. The substrate...

20060160254 - System and method for detection of spatial signature yield loss: A method and system are provided for identifying systematic yield losses. The method comprising testing produced products using a test sequence, the testing sequence producing yield data, the yield data related to a wafer. For each zone of each wafer size calculating and storing a first data series R1, wherein...

20060160258 - Process for producing microelectromechanical components and a housed microelectromechanical component: A process produces microelectromechanical components from a substrate that has a first side and a second side which is substantially opposite from the first side, and at least the first side has at least one microelectromechanical element. The process includes the step of providing at least one conductive passage into...

20060160257 - White-light emitting devices and methods for manufacturing the same: White-light emitting devices and methods for manufacturing the same. The white-light emitting device emits white light comprising a first color component with first wavelength, a second color component with a second wavelength, and a third color component with a third wavelength. The first wavelength is shorter than the second wavelength....

20060160259 - Sealant region pattern for liquid crystal display and method for fabricating the same: A sealant region pattern for a liquid crystal display apparatus and a method for fabricating the same. The method comprises providing a first substrate and a second substrate opposite thereto, forming a predetermined material layer on the first substrate, forming an organic material pattern layer having openings of a saw...

20060160260 - Thin film transistor array panel and method of manufacturing the same: The present invention provides a method of manufacturing a TFT array panel in a cost-effective manner. The method includes: forming thin film transistors each having a gate electrode, a source electrode, and a drain electrode; forming an insulating layer on the thin film transistors; forming a first conductive layer electrically...

20060160261 - Series interconnected optoelectronic device module assembly: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One...

20060160262 - Microelectromechanical devices and their fabrication: A method of fabricating microelectromechanical (MEMs) systems and in particular for producing silicon carbide (SiC) MEMs devices with improved mechanical properties. The method comprises reacting a dry etch plasma with a layered microstructure; the layered microstructure having an etch mask, a sacrificial layer and a device layer arranged between the...

20060160263 - Method for manufacturing pressure sensor: A method for manufacturing a pressure sensor includes the steps of: preparing a semiconductor substrate; forming an insulation film on the substrate; forming a first metal film on the insulation film; forming a first protection film on the first metal film and the insulation film; forming a second protection film...

20060160264 - Methods and apparatus having wafer level chip scale package for sensing elements: Methods are provided for manufacturing a sensor. The method comprises depositing a sacrificial material at a first predetermined thickness onto a wafer having at least one sense element mounted thereon, the sacrificial material deposited at least partially onto the at least one sense element, forming an encapsulating layer at a...

20060160265 - Method of manufacturing photoelectric conversion element, photoelectric conversion element, and electronic apparatus: A method of manufacturing a photoelectric conversion element, in which a first carrier transport layer, a dye layer, and a second carrier transport layer are interposed between an anode and a cathode, includes forming the first carrier transport layer, forming the dye layer so as to come into contact with...

20060160266 - Organic electronic component and method for producing organic electronic devices: The invention relates to an organic electronic component and a process for low-cost and large-scale production of organic electronics, wherein roll-to-roll compatible coating techniques are used in conjunction with printing processes....

20060160268 - Exposure equipment and control method of the same: A controller controls a wafer carrier to move from a SMIF-POD to transfer and collect a wafer between a space of a transfer unit through a thermal chamber. The wafer carrier is returned into the SMIF-POD, when the wafer is exposed, to be kept waiting in the SMIF-POD until the...

20060160269 - Method and apparatus for avoiding dicing chip-outs in integrated circuit die: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the...

20060160267 - Under bump metallurgy in integrated circuits: An integrated circuit package and method of manufacture is provided. A substrate having a number of contact pads exposed through a passivation layer thereon has a first under bump metallurgy layer over at least one of the contact pads. A top under bump metallurgy layer of copper having a thickness...

20060160270 - Method for producing an anisotropic conductive film on a substrate: This invention relates to a process for manufacturing an anisotropic conducting film comprising a layer of electrically insulating material and conducting through inserts, the said process comprising the following steps: a) formation on a substrate of at least one layer of material with through holes, the said layer being called...

20060160271 - Stacked semiconductor module: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable...

20060160272 - Synthesis method for a compound used to form a self-assembled monolayer, compound for forming a self-assembled monolayer, and layer structure for a semiconductor component: A synthesis method of a compound used to form a self-assembled monolayer used in a semiconductor component is provided. A method includes a first step of replacing a terminal halogen of an ω-haloalk-1-ene with a compound having at least one aromatic group, and a second step of hydrosilylating the reaction...

20060160273 - Method for wafer level packaging: A device wafer including a plurality of devices and a plurality of contact pads positioned on a top surface of the device wafer and electrically connected to the devices is provided. Subsequently, a cap wafer is provided. Following that, a plurality of bonding patterns and a plurality of cavity patterns...

20060160274 - Methods relating to forming interconnects: Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component substrate, such as a semiconductor die or other substrate, has dielectric material disposed on a surface thereof, surrounding but not covering interconnect elements, such as bond pads, on...

20060160275 - Device and method for encapsulating with encapsulating material and electronic component fixed on a carrier: The invention relates to a device for encapsulating with encapsulating material an electronic component, in particular a semiconductor, fixed on a carrier, comprising: two co-acting mould parts which are displaceable relative to each other between an encapsulating position, in which the mould parts, when closing onto the carrier, occupy a...

20060160277 - Active layer island: A method for forming an electronic device including at least one electrically conductive and one semiconductive material deposited from solution, the method comprising: forming on the substrate a confinement structure consisting of a least a first zone and a second zone, depositing the electrically conductive material on the substrate, wherein...

20060160276 - Electronic devices: A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and...

20060160281 - Method of fabricating a thin film transistor: A method of fabricating a thin film transistor is disclosed. The method comprises forming an amorphous silicon layer overlying a substrate. A first heat treatment is then performed to reduce the hydrogen atom concentration of the amorphous silicon layer. Next, the amorphous silicon layer is patterned to form an island-shaped...

20060160279 - Optical mask and manufacturing method of thin film transistor array panel using the optical mask: A photo mask is provided. The mask includes: a transmitting area and a translucent area, wherein the translucent area includes a plurality of light blocking portions blocking light, and wherein the light blocking portions have a plurality of areas blocking different amounts of light. By using this type of photo...

20060160278 - Thin film device active matrix by pattern reversal process: This invention provides a method of fabricating an active matrix of thin film devices through a pattern reversal self aligned imprint lithography (SAIL) process. The method includes providing a substrate and depositing at least one layer of material upon the substrate. A pattern is then established upon the layer of...

20060160282 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, The method includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming a data line and a drain electrode on the...

20060160280 - Thin film transistor, a method for preparing the same and a flat panel display employing the same: Provided are a thin film transistor, a method for preparing the same and a flat panel display employing the same. The thin film transistor includes a gate electrode, source and drain electrodes insulated from the gate electrode, a semiconductor layer insulated from the gate electrode and electrically connected to the...

20060160283 - Method of fabricating a liquid crystal display device: A method of fabricating a liquid crystal display device comprises the following steps. A first N-type LDD (Lightly Doped Drain) and a second N-type LDD are formed in a semiconductor layer by tilted ion implantation with a gate electrode serving as a mask. The two N-type LDDs are adjacent to...

20060160284 - Switching device for a pixel electrode and methods for fabricating the same: The invention discloses a switching device for a pixel electrode of display device and methods for fabricating the same. A gate is formed on a portion of a substrate. A semiconductor layer is formed on the gate. A source and a drain are formed on a portion of the semiconductor...

20060160286 - Memory device and method for fabricating the same: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being...

20060160285 - Semiconductor device having mosfet with offset-spacer, and manufacturing method thereof: A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first offset-spacer which is formed in contact with one side surface of the gate electrode, a first spacer which...

20060160287 - Method of fabricating semiconductor device: There has been a problem of damaging a diffusion layer 4 occasionally in etching of a nitride film 5 in a wide gate pitch P1 region. First, a plurality of diffusion layers 4, gates 2 and sidewalls 3 are formed on a silicon substrate 1, so as to be adjacent...

20060160288 - Micro-feature fill process and apparatus using hexachlorodisilane or other chlorine-containing silicon precursor: A method is provided for depositing a silicon-containing film in a micro-feature on a substrate by a low pressure deposition process in a processing system. A silicon-containing film can be formed in a micro-feature by providing a substrate in a process chamber of a processing system, and exposing a hexachlorodisilane...

20060160289 - Semiconductor device and method of manufacturing the same: A semiconductor device is proposed which includes: a semiconductor substrate of a first conductivity type; a channel region formed at a surface of the semiconductor substrate; source and drain regions of a second conductivity type formed at both sides of the channel region in the semiconductor substrate; an insulating layer...

20060160293 - Cell structure of eprom device and method for fabricating the same: Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes...

20060160291 - Integration of biaxial tensile strained nmos and uniaxial compressive strained pmos on the same wafer: A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a...

20060160290 - Method to fabricate variable work function gates for fusi devices: An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si...

20060160292 - Nfet and pfet devices and methods of fabricating same: A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on...

20060160295 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the...

20060160294 - Soi device with body contact self-aligned to gate: A region of a semiconductor wafer is converted to an SOI structure by etching a set of isolation trenches for each transistor active area and oxidizing the sidewalls of the trenches to a depth that leaves a pillar of semiconductor that forms a body contact extending from the active area...

20060160296 - Methods of forming cmos constructions: The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has...

20060160297 - Semiconductor integrated circuit device and process for manufacturing the same: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of...

20060160298 - Self-aligned, silicided, trench-based, dram/edram processes with improved retention: A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond...

20060160299 - Single mask mim capacitor and resistor with in trench copper drift barrier: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion...

20060160300 - Storage capacitor and method of manufacturing a storage capacitor: A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor....

20060160301 - Method for fabricating a metal-insulator-metal capacitor: Disclosed are: (i) a method for fabricating a MIM capacitor in a semiconductor device, which can produce a MIM capacitor in fewer process steps; and (ii) a semiconductor device in which a MIM capacitor having a larger capacitance relative to conventional approaches is formed. The method comprises the steps of:...

20060160302 - Method of fabricating a fin field effect transistor having a plurality of protruding channels: In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate having an active region pattern, forming...

20060160303 - Method for forming high-k charge storage device: Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking...

20060160304 - Non-volatile memory resistor cell with nanotip electrode: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between...

20060160305 - Pillar cell flash memory technology: An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon...

20060160306 - Method for forming trench gate dielectric layer: A method for forming a trench gate dielectric layer is described. First, a substrate having a trench therein is provided. An in-situ steam generated oxidation process is performed to form a sacrificial layer on the surface of the trench. Then, the sacrificial layer is removed. Next, a low-pressure chemical vapor...

20060160307 - Method of driving memory device to implement multiple states: A method of driving a multi-state organic memory device which includes an organic memory layer between upper and lower electrodes. The method comprises continuously applying voltages having different polarities to conduct switching into a low resistance state, and applying a single pulse to conduct switching into a high resistance state....

20060160308 - Method of forming a gate of a flash memory device: The present invention provides a method of forming a gate in a flash memory device. The method includes: forming a oxide layer on a semiconductor substrate; forming a stacked structure including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate by patterning them on the...

20060160309 - Method of manufacturing a superjunction device with conventional terminations: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a heavily doped region of a first conductivity and has a lightly doped region of the first conductivity. The semiconductor substrate a plurality of trenches etched into an active region of the substrate forming a plurality of...

20060160310 - Semiconductor device and method for fabricating the same: After forming a first semiconductor region of a first conductivity type in a semiconductor substrate, a trench reaching a given portion of the first semiconductor region is formed in the semiconductor substrate. Then, after forming a gate insulating film on an inner wall of the trench, a second semiconductor region...

20060160311 - Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices: An integrated circuit is formed by identifying multiple regions, each having transistors that have a gate oxide thickness that differs between the multiple regions. One of the regions includes transistors having a nanocluster layer and another of the regions includes transistors with a thin gate oxide used for logic functions....

20060160312 - Gate electrode for finfet device: In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having...

20060160313 - Semiconductor device and method of manufacturing the same: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulation layer on a semiconductor substrate; forming a plurality of gate electrodes on the gate insulation layer; forming pocket regions by a pocket ion implantation process using the gate electrode...

20060160314 - Substrate having silicon germanium material and stressed silicon nitride layer: A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the...

20060160315 - Semiconductor device manufacturing method, wiring and semiconductor device: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a...

20060160316 - Silicon carbide and related wide-bandgap transistors on semi-insulating epitaxy for high-speed, high-power applications: A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating...

20060160317 - Structure and method to enhance stress in a channel of cmos devices using a thin gate: A method and structure for producing CMOS devices having thin gates with enhanced stress in a stressed channel is provided. The method allows for producing a CMOS device with a relatively thin gate to provide improved gate response characteristics. Additionally, the structure includes a first stressed film having a raised...

20060160318 - Transistor antifuse device: In one embodiment, a method provides a bipolar junction transistor that is coupled to a first power supply. A second power supply is utilized to turn on the bipolar junction transistor. And, the bipolar junction transistor is overdriven....

20060160319 - Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit: A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an...

20060160320 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device includes: forming an insulating film on a semiconductor body to cover a termination area surrounding a cell area; forming a mask material film to cover the cell area and the insulating film; forming a resist film to cover the mask material film; patterning...

20060160324 - Deglaze route to compensate for film non-uniformities after sti oxide processing: A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the spin processing unit to direct...

20060160323 - Memory array buried digit line: A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer...

20060160326 - Method for rounding top corners of isolation trench in semiconductor device: A method for forming an isolation trench in a semiconductor device includes the steps of: forming a pad oxide layer over a semiconductor substrate; forming a pad nitride layer over the pad oxide layer; forming a photoresist pattern defining an isolation area on the pad nitride layer; forming a trench...

20060160321 - Method of forming trench isolation structure: There is provided a method for trench isolation structure formation, which produces neither voids nor cracks within a groove. This method comprises the steps of: forming a groove on a surface of a silicon substrate; coating a polysilazane solution; prebaking the coating at a prebaking temperature regulated so that the...

20060160325 - Method of manufacturing semiconductor device: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an insulation layer on a silicon substrate; forming a shallow trench isolation (STI) pattern by a photolithography and etching process; forming a high density plasma (HDP) oxide layer on the STI pattern;...

20060160322 - Nitridation of sti fill oxide to prevent the loss of sti fill oxide during manufacturing process: A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride...

20060160327 - Soi wafer with cooling channels and a method of manufacture thereof: A method (100) of forming a silicon-on-insulator (SOI) wafer includes forming one or more channels in a top surface of a first wafer (104), and forming an insulator layer on a second wafer (106). The second wafer is treated (108) to generate a structural weakness therein, and the first and...

20060160328 - Treatment of a removed layer of silicon-germanium: The invention relates to a method of forming a structure comprising a removed layer taken from a donor wafer, the donor wafer including a first layer formed of Si1-xGex and a second layer of Si1-yGey on the first layer, where x and y, respectively, are in the range of 0...

20060160329 - Method and system for fabricating strained layers for the manufacture of integrated circuits: A method for forming a strained layer of semiconductor material, e.g., silicon, germanium, Group III/V, silicon germanium alloy. The method includes providing a non-deformable surface region having a first predetermined radius of curvature, which is defined by R(1) and is defined normal to the surface region. The method includes providing...

20060160330 - Semiconductor device and manufacturing method thereof: A method of manufacturing a semiconductor device includes: preparing a semiconductor element having a first metal layer made of first metal on a surface thereof, and a metal substrate made of second metal, the metal substrate having a fourth metal layer made of fourth metal on a surface thereof, and...

20060160331 - Laser processing method and laser processing apparatus: A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface...

20060160332 - Method and system for high-speed precise laser trimming, scan lens system for use therein and electrical device produced thereby: A method, system and scan lens system are provided for high-speed, laser-based, precise laser trimming at least one electrical element. The method includes generating a pulsed laser output having one or more laser pulses at a repetition rate. Each laser pulse has a pulse energy, a laser wavelength within a...

20060160333 - Thermal treatment equipment and method for heat-treating: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating. The thermal treatment equipment comprises treatment rooms of n pieces (n>2) performing heat-treating, a preparatory heating room, and a...

20060160334 - Epitaxial growth method: Provided is an epitaxial growth method for forming a high-quality crystalline growth semiconductor wafer. The method includes forming a buffer layer on a single crystalline wafer using a single crystalline material; forming a mask layer on the buffer layer; forming a plurality of holes in the mask layer using a...

20060160335 - Rare earth element-doped silicon/silicon dioxide lattice structure: Provided are an electroluminescence (EL) device and corresponding method for forming a rare earth element-doped silicon (Si)/Si dioxide (SiO2) lattice structure. The method comprises: providing a substrate; DC sputtering a layer of amorphous Si overlying the substrate; DC sputtering a rare earth element; in response, doping the Si layer with...

20060160336 - Silicon layer production method and solar cell production method: A solar cell is produced by dipping a multicrystalline silicon substrate 28 in a solution 24 containing silicon, growing a silicon layer on the substrate 28 while decreasing with time the temperature drop rate of the solution during the dipping of the substrate in the solution, and forming a pn...

20060160337 - Method of manufacturing a hemisperical grain silicon layer and method of manufacturing a semiconductor device using the same: In a method of manufacturing a capacitor including a hemispherical grain (HSG) silicon layer, after forming a storage electrode electrically coupled to a contact region of a substrate, the HSG silicon layer is formed on the storage electrode by providing a first gas including silicon and a second gas onto...

20060160338 - Method of ion implantation to reduce transient enhanced diffusion: A method of ion implantation comprises the steps of: providing a semiconductor substrate; performing a pre-amorphisation implant in the semiconductor substrate in a direction of implant at an angle in the range of 20-60° to a normal to a surface of the semiconductor substrate, and performing an implant of a...

20060160339 - Soi contact structure(s) and corresponding production method: Disclosed are an arrangement and a production method for electrically connecting active semiconductor structures in or on a monocrystalline silicon layer (12) located on the front face (V) of silicon-on-insulator semiconductor wafers (SOI, 10) to the substrate (13). The electrical connection (20) is made through an insulator layer (11). A...

20060160340 - Method and apparatus for processing a conductive thin film: A method and apparatus for processing a thin film able to easily form grooves in a conductive thin film on an insulating substrate, comprising bringing a first electrode into contact with the conductive thin film, maintaining a conductive state between a tip of a second electrode with a voltage applied...

20060160341 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the...

20060160342 - Forming dual metal complementary metal oxide semiconductor integrated circuits: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal,...

20060160343 - Laser activation of implanted contact plug for memory bitline fabrication: An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of...

20060160344 - Rhodium film and method of formation: A method for the formation of rhodium films with good step coverage is disclosed. Rhodium films are formed by a low temperature atomic layer deposition technique using a first gas of rhodium group metal precursor followed by an oxygen exposure. The invention provides, therefore, a method for forming smooth and...

20060160345 - Innovative growth method to achieve high quality iii-nitride layers for wide band gap optoelectronic and electronic devices: A method to achieve high quality III-nitride epitaxial layers including AlN, AlGaN, GaN, InGaN, and AlInGaN, by supplying group III precursors constantly and group V precursors periodically with the epitaxial growth systems including metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (MBE)....

20060160347 - Method of manufacturing semiconductor device and method of treating electrical connection section: A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section....

20060160346 - Substrate bump formation: A layer of metal may be formed under a layer of solder in forming solder bumps. The metal may reduce the amount of solder necessary and may result in a corresponding reduction in solder defects....

20060160348 - Semiconductor element with under bump metallurgy structure and fabrication method thereof: A semiconductor element with under bump metallurgy (UBM) structures and a fabrication method thereof are proposed. When UBM structures are formed on signal pads and ground pads on a surface of the semiconductor element that is completely fabricated with a circuit layout, a metallic layer for defining the UBM structures...

20060160349 - Interconnect structures with encasing cap and methods of making thereof: A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure....

20060160351 - Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer: A metal interconnect layer of a semiconductor device, and a method for forming a metal interconnect layer of a semiconductor device are provided. The lower portion of a metal interconnect layer is wider than the upper portion of the metal interconnect layer. In another interconnect structure in accordance with the...

20060160350 - On-chip cu interconnection using 1 to 5 nm thick metal cap: Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion...

20060160352 - Method of forming interconnection in semiconductor device: A multilayer interconnection structure is formed by a method comprising the steps of: Forming a low dielectric constant film on a substrate, curing the low dielectric constant film by irradiating it with UV light, laminating a UV blocking film, laminating a next low dielectric constant film, and curing the next...

20060160353 - Methods for selective integration of airgaps and devices made by such methods: Damascene stacks for use in semiconductor devices and methods for making such stacks are disclosed. An example damascene stack includes a substantially planar lower liner layer and a patterned sacrificial dielectric layer disposed on top of the lower liner layer, where the patterned sacrificial dielectric layer includes an interconnect structure...

20060160354 - Via electromigration improvement by changing the via bottom geometric profile: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal...

20060160356 - Method for fabricating self-aligned contact hole: Disclosed are: (i) a method for fabricating self-aligned contact hole in a semiconductor device, and (ii) a semiconductor device having a self-aligned contact. The method comprises the steps of: (a) forming an oxide layer covering a gate structure on a semiconductor substrate, the gate structure including a gate oxide pattern,...

20060160355 - Semiconductor device with a metal line and method of forming the same: A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the lower insulation layer; sequentially forming a first oxide layer, an FSG (Fluorine-doped Silicate Glass) layer, and...

20060160357 - Semiconductor device and method for manufacturing the same: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the...

20060160358 - Method of fabricating semiconductor device including removing impurities from silicon nitride layer: A method of fabricating a semiconductor device having a silicon nitride layer substantially free of impurities includes forming a silicon nitride layer on a semiconductor substrate and annealing the semiconductor substrate having the silicon nitride layer in an atmosphere of ammonia (NH3) gas to remove impurities from the silicon nitride...

20060160359 - Vacuum processing apparatus: A vacuum processing apparatus is constituted of the following portions: a processing container with the bottom, capable of drawing vacuum; a placement platform installed in the container; a heating portion for heating a substrate on the platform; a processing gas-feeding portion for feeding a processing gas into the container; a...

20060160360 - Evaporation method and evaporator: A vaporization method and a vaporizer capable of greatly reducing the number of fine particles scattered in a film after film formation. A raw material solution is brought into contact with a heated carrier gas and carried to a subsequent step. The vaporizer includes: a vaporization chamber; a carrier gas...

20060160361 - Nickel salicide process and method of fabricating a semiconductor device using the same: A method of forming a silicide layer includes forming a metal layer on a substrate having a silicon region, the metal layer including nickel, annealing the substrate and the metal layer to form the silicide layer on the silicon region, the silicide layer including nickel, and cooling the substrate and...

20060160362 - Via hole and trench structures and fabrication methods thereof and dual damascene structures and fabrication methods thereof: Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive...

20060160364 - Refreshing wafers having low-k dielectric materials: A low-k dielectric layer having a composition of silicon, oxygen and carbon is removed from a wafer. The low-k dielectric layer is removed by exposing a surface of the low-k dielectric layer to an oxygen-containing gas to oxidized the surface. The oxidized surface is immersed in an etching solution having...

20060160363 - Shallow trench isolation formation: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is...

20060160365 - Water-cooling apparatus for semiconductor thermal processing: A water-cooling apparatus for semiconductor thermal processing compring two supply pipes and two recycle pipes for respectively connecting to two chambers for performing the semiconductor processing. Each chamber has one set of pipes for supplying and recycling the cooling water in order to adjust the temperature in the chambers and...

20060160366 - Method for preparing a structure with high aspect ratio: The present invention discloses a method for preparing a structure with high aspect ratio, which can be a trench or a conductor. A first mask is formed on a substrate, and a first etching process is performed to remove the substrate uncovered by the first mask to form at least...

20060160367 - Methods of treating semiconductor substrates: The invention includes methods of treating semiconductor substrates with one or more reactants dispersed in supercritical fluid. A substrate can be provided within a reaction chamber having an interior periphery. The interior periphery can include a bottom region, a top region, and one or more sidewall regions between the bottom...

20060160368 - Substrate processing apparatus and substrate processing method: A substrate processing apparatus (12) for processing a substrate (W) by feeding a processing liquid comprises: a temperature regulator (133) to regulate the temperature of said processing liquid; and a underplate temperature adjuster (115) to adjust the temperature of an underplate (77) which is placed in proximity to the backside...

20060160369 - Method of fabricating semiconductor electric heating film: Disclosed is method of fabricating semiconductor heater film which is formed on a substrate with excellent heat resistant and electrical insulation property by depositing atomized particles of coating material essentially formed of powdered metallic (Sn,V) chlorides and silicide mixed with one of Fe, Sb or In compound and solvent such...

20060160370 - Solid material gasification method, thin film formation process and apparatuses: Solid material gasification method comprises a solution preparation step wherein a first solid material is dissolved in a solvent to prepare a gasification solution, a solvent removal step wherein a second solid material is separated by removing the solvent used to prepare the gasification solution from that solution, and a...

20060160371 - Inhibiting growth under high dielectric constant films: Oxidation between a higher dielectric constant material such as a rare earth oxide and a substrate may be reduced by providing a seal layer over the gate dielectric. In some embodiments, the seal layer may be isolated from the gate dielectric by a buffer layer....

20060160372 - Method and apparatus for fabricating low-k dielectrics, conducting films, and strain-controlling conformable silica-carbon materials: A method for fabricating a semiconductor device having a plurality of layers, depositing a first layer comprising a medium-k dielectric barrier layer on one of the plurality of layers, depositing a second layer comprising a low-k dielectric layer on the first layer, and depositing a third layer comprising a medium-k...

20060160373 - Processes for planarizing substrates and encapsulating printable electronic features: Processes for planarizing a substrate, for encapsulating a printed electronic feature and for forming a ramp feature. In various embodiments, the processes include the steps of: (a) applying a planarizing agent, an encapsulating agent or a ramping feature to a substrate or to an electronic feature disposed thereon, preferably through...

20060160374 - Formation of low k material utilizing process having readily cleaned by-products: Nano-porous low dielectric constant films are deposited utilizing materials having reactive by-products readily removed from a processing chamber by plasma cleaning. In accordance with one embodiment, an oxidizable silicon containing compound is reacted with an oxidizable non-silicon component having thermally labile groups, in a reactive oxygen ambient and in the...

20060160375 - Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry, methods of forming trench isolation in the fabrication of integrated circuitry, method of depositing silicon dioxide-comprising layers in the fabrication o: This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming bit line over capacitor arrays of memory cells. In one implementation, a semiconductor substrate having an exposed outer first surface comprising silicon-nitrogen bonds and an...

20060160376 - Interface engineering to improve adhesion between low k stacks: A method of depositing a organosilicate dielectric layer exhibiting high adhesion strength to an underlying substrate disposed within a single processing chamber without plasma arcing. The method includes positioning a substrate within a processing chamber having a powered electrode, flowing an interface gas mixture into the processing chamber, the interface...

20060154380 - Synthesis of ordered arrays from gold clusters: A nanocluster includes 1 to 7 metal atoms and has at least one ligand, which is associated with at least one of the metal atoms. A method of making a nanocluster consists of combining a nanoparticle, a ligand and a high boiling point solvent to provide a mixture and heating...

20060154382 - Capacitor with high dielectric constant materials and method of making: Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1-x)TiO3, and methods of making such capacitors and DRAM cells are provided. One method includes providing a conductive oxide electrode, oxidizing at least the upper surface of the conductive oxide electrode, depositing a first...

20060154381 - Method and structure for generating offset fields for use in mram devices: A method for generating an offset field for a magnetic random access memory (MRAM) device includes forming a first pinned layer integrally with a wordline, and forming a second pinned layer integrally with a bitline. An MRAM cell is disposed between the wordline and the bitline, the MRAM cell including...

20060154383 - Processing apparatus and processing method: In a processing apparatus, a process gas including a source gas (TiCl4, NH3) and an inert gas (N2) is supplied into a process chamber (2). A pressure meter (6) detects a pressure in the process chamber (2) so as to control an amount of flow of the process gas supplied...

20060154384 - Optical device: A method of forming an optical device comprising the steps of: providing a substrate comprising a first electrode capable of injecting or accepting charge carriers of a first type; forming over the first electrode a first layer that is at least partially insoluble in a solvent by depositing a first...

20060154385 - Fabrication pathway integrated metrology device: An in-line, non-freestanding substrate measurement system is integrated into the substrate fabrication pathway. One embodiment includes a metrology device integrated into a guided vehicle. Another embodiment provides a system for simultaneously measuring both sides of a substrate. A metrology device may be integrated into the front handling chamber of a...

20060154386 - Apparatus and method for aligning devices on carriers: An apparatus and method are provided for aligning a plurality of semiconductor devices placed on a carrier. Alignment guides are located adjacent to each device in use, and arranged such that they correspond to a desired alignment of each semiconductor device. For alignment, the semiconductor devices are held by a...

20060154387 - Method for calibration of a photodiode, semiconductor chip and operating method: The present invention relates to a method for setting a wavelength-dependent output signal of a light-sensitive integrated circuit (1) in which the output signals of the integrated circuit are measured at different measured wavelengths (λ1, λ2, λ3), the measured values (31, 32, 33) are compared to setpoint values (21, 22),...

20060154388 - Integrated metrology chamber for transparent substrates: The embodiments of the invention relate to a method and apparatus for measuring the etch depth between etching for an alternate phase shift photomask in a semiconductor photomask processing system. The apparatus for measuring the etch depth of a substrate in an etch processing system comprises a measurement cell coupled...

20060154389 - Light emitting diode with conducting metal substrate: Systems and methods for fabricating a light emitting diode include forming a multilayer epitaxial structure above a carrier substrate; depositing at least one metal layer above the multilayer epitaxial structure; removing the carrier substrate....

20060154391 - Light emitting diodes (leds) with improved light extraction by roughening: Systems and methods are disclosed for fabricating a semiconductor light emitting diode (LED) device by forming an n-gallium nitride (n-GaN) layer on the LED device; and roughening the surface of the n-GaN layer to extract light from an interior of the LED device....

20060154392 - Method of making a vertical light emitting diode: Methods are disclosed for forming a vertical semiconductor light emitting diode (VLED) device having an active layer between an n-doped layer and a p-doped layer; and securing a plurality of balls on a surface of the n-doped layer of the VLED device....

20060154390 - Systems and methods for producing light emitting diode array: Systems and methods are disclosed for producing vertical LED array on a metal substrate; evaluating said array of LEDs for defects; destroying one or more defective LEDs; forming good LEDs only LED array suitable for wafer level package....

20060154394 - Plasma display panel and manufacturing method of the same: The manufacturing method includes the step of forming a dielectric layer on a substrate where electrodes are formed so as to coat the electrodes in accordance with a vapor phase growth method, the step of carrying out a process for planarization on the dielectric layer, and the step of forming...

20060154393 - Systems and methods for removing operating heat from a light emitting diode: Systems and methods for fabricating a light emitting diode include forming a multilayer epitaxial structure above a carrier substrate; depositing at least one metal layer above the multilayer epitaxial structure and forming heat removal fins thereon; removing the carrier substrate....

20060154395 - Heat conductive sheet, manufacturing method of the same, and manufacturing method of a liquid crystal display using the same: The present invention relates to a heat conductive sheet including: a glass fiber and a coating layer surrounding the glass fiber. The coating layer includes silicon, fluoropolymer resin, and metal. Thus, a heat conductive sheet having high durability and high heat conductivity is provided....

20060154396 - Polarizing element and optical member and liquid crystal display device: A polarizing member is constituted by an absorption type polarizing film, and one polymer material layer or two or more polymer material layers provided on one or both of opposite surfaces of the absorption type polarizing film, wherein each polymer material layer does not have any extraordinary refractive index area...

20060154397 - Method for manufacturing a display device and method for forming a pattern: A method for manufacturing a display device is provided in which an a-Si semiconductor layer including signal terminal regions is formed in an island manner and the total parasitic capacitance is minimized while the increase of the number of process steps for photolithography is restricted. Signal lines, signal lead wires,...

20060154398 - Method of manufacturing a structural health monitoring layer: Methods of manufacturing a diagnostic layer containing an array of sensing elements. The sensing elements, associated wires, and any accompanying circuit elements, are incorporated various layers of a thin, flexible substrate. This substrate can then be affixed to a structure so that the array of sensing elements can analyze the...

20060154399 - Ultra-fast nucleic acid sequencing device and a method for making and using the same: A system and method employing at least one semiconductor device, or an arrangement of insulating and metal layers, having at least one detecting region which can include, for example, a recess or opening therein, for detecting a charge representative of a component of a polymer, such as a nucleic acid...

20060154400 - Method of forming a nanogap and method of manufacturing a nano field effect transitor for molecular device and bio-sensor, and molecular device and bio-sensor manufactured using the same: The present invention relates to a method of forming a nanogap, a method of manufacturing a nano field effect transistor for a molecular device or a bio-sensor, and a fabrication thereof, and more particularly, to a method of forming a high reproductive nanogap using a thin layer with a molecular...

20060154401 - Gas-sensing semiconductor devices: A gas-sensing semiconductor device is fabricated on a silicon substrate having a thin silicon oxide insulating layer in which a resistive heater made of a CMOS compatible high temperature metal is embedded. The high temperature metal is tungsten. The device includes at least one sensing area provided with a gas-sensitive...

20060154402 - Tile-based routing method of a multi-layer circuit board and related structure: A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned...

20060154403 - Thin array plastic package without die attach pad and process for fabricating the same: A process for fabricating an integrated circuit package. Metal is plated up on a substrate to provide a plurality of contacts pads and a plurality of fiducial markings on a periphery of the contacts. A transparent mask is selectively deposited on the substrate, over the fiducial markings. A semiconductor die...

20060154404 - Die paddle clamping method for wire bond enhancement: A leadframe configuration for a semiconductor device that has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping...

20060154405 - Methods of fabrication for flip-chip image sensor packages: The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete...

20060154406 - Method of manufacturing transistor, method of manufacturing electro-optical device, and method of manufacturing electronic device: A method of manufacturing a transistor includes disposing a droplet containing a bank material as a solute or a dispersoid on a substrate, drying the droplet to form a bank, ejecting a conductive material on a part of the bank to form a first conductive region and a second conductive...

20060154407 - Chuck plate assembly with cooling means: The invention provides a chuck plate assembly that includes a shadow mask formed with a predetermined pattern; a shadow mask frame holding the shadow mask and having heat-radiating and cooling functions; a substrate aligned with the shadow mask and onto which deposition materials from a deposition source are deposited; and...

20060154408 - Method of forming channel region of tft composed of single crystal si: A method of forming a high quality channel region of a TFT by forming a large size monocrystalline silicon thin film using a patterned metal mask and a grain boundary filtering region is provided. The method includes sequentially stacking a first buffer layer and an amorphous silicon layer on a...

20060154409 - Method for fabricating non-volatile memory: A method of fabricating a non-volatile memory is described. A substrate is provided and a first dielectric layer, an electron trapping layer and a second dielectric layer are sequentially formed thereon. Each of the stacked gate structures includes a first gate and a cap layer having a gap between every...

20060154411 - Cmos transistors and methods of forming same: The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the...

20060154410 - Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same: A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick...

20060154412 - Method for post lithographic critical dimension shrinking using thermal reflow process: A method for reducing the size of a patterned semiconductor feature includes forming a first layer over a substrate to be patterned, and forming a photoresist layer over the first layer. The photoresist layer is patterned so as to expose portions of the first layer, and the exposed portions of...

20060154413 - Self-forming metal silicide gate for cmos devices: A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon)...

20060154414 - Sensor for detecting compounds: A chemical sensor having a sol-gel material affixable to a predetermined surface, and an indicator within the sol-gel, for detecting and signaling the presence of at least one chemical is provided. Also provided is an indicator for detecting and indicating a presence of at least one chemical. The indicator includes...

20060154415 - Method for manufacturing semiconductor substrate and semiconductor substrate: A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking oxygen on the major surface, performing annealing, and then...

20060154416 - Method of pad printing in the manufacture of capacitors: Deposition of a metal-containing reagent solution or suspension or a carbon nanotube-containing suspension onto a conductive substrate by various pad-printing techniques is described. In the case of a metal-containing solution or suspension, a pseudocapacitive oxide coating, nitride coating, carbon nitride coating, carbide coating, or carbon nanotube coating results. In any...

20060154417 - Semiconductor memory device: The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower...

20060154419 - Flash memory and method of fabricating the same: A method of fabricating a flash memory device produces a device that has a small cell area and yet a high coupling ratio. First, a basic structure is provided that includes a substrate, a field isolation film protruding from the substrate, and floating gates disposed on the substrate on opposite...

20060154418 - Method for manufacturing one-time electrically programmable read only memory: A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined...

20060154420 - Method of manufacturing flash memory device: Provided is a method of manufacturing a flash memory device. In accordance with the present invention, an undoped polysilicon layer is formed over a semiconductor substrate where a floating gate and a dielectric layer are formed. By performing N2 plasma process with respect to the undoped polysilicon layer, a heavily...

20060154421 - Method of manufacturing semiconductor device having notched gate mosfet: Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed .on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized...

20060154422 - Driving transistor and organic light emitting diode display having the same: Embodiments of a transistor capable of outputting uniform driving current despite deviations in manufacturing processes, and an organic light emitting diode display (OLED) capable of displaying high picture quality by employing the transistor are disclosed. The transistor comprises a semiconductor layer formed on a substrate and including a source connected...

20060154424 - Method of manufacturing a split-gate flash memory device: A method of manufacturing a split-gate flash memory device is disclosed. On a semiconductor substrate having a plurality of parallel conductive lines, a plurality of doped regions are formed by an ion implantation using the conductive lines as mask. Then, the conductive lines are trimmed for thinning the cover area....

20060154423 - Methods of forming structure and spacer and related finfet: Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top...

20060154425 - Semiconductor device and method for fabricating the same: A semiconductor device and method for fabricating the same. The semiconductor device comprises a substrate with a gate stack thereon, wherein the gate stack comprises a high-k dielectric layer and a conductive layer sequentially overlying a portion of the substrate. An oxidation-proof layer overlies sidewalls of the gate stack. A...

20060154426 - Finfets with long gate length at high density: A method of manufacturing fin-type field effect transistors (FinFETs) forms a silicon layer above a substrate, forms a mask pattern above the silicon layer using a multi-step mask formation process, patterns the silicon layer into silicon fins using the mask pattern such that the silicon fins only remain below the...

20060154427 - Method of thermally treating a wafer and method of fabricating a semiconductor device using the same: A method of thermally treating a semiconductor wafer is disclosed. The method comprises loading a wafer into a chamber, adjusting the vacuum pressure in the chamber, increasing the temperature of the wafer, and maintaining the vacuum pressure and temperature for a period of time sufficient to activate conductive impurities that...

20060154428 - Method of thermally treating a wafer and method of fabricating a semiconductor device using the same: Methods and resulting structure of implementing a compensating implant that creates more compensation doping as the gate length is increased are disclosed. In particular, the invention performs an angled compensation implant through a gate opening during the damascene process such that the compensating dopant concentration increases as the gate length...

20060154429 - Method for fabricating low-defect-density changed orientation si: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention...

20060154430 - Soi structure comprising substrate contacts on both sides of the box, and method for the production of such a structure: Disclosed are an arrangement and a production method for electrically connecting (20) active semiconductor structures (40) in the monocrystalline silicon layer (12) located on the front face of silicon-on-insulator semiconductor wafers (SOI; 10) to the substrate (13) located on the rear side and additional structures (13a) that are disposed therein....

20060154431 - Method of fabricating a silicon-on-insulator device with a channel stop: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two...

20060154432 - Variable resistance functional body and its manufacturing method: A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode...

20060154434 - Method of making an internal capacitive substrate for use in a circuitized substrate and method of making said circuitized substrate: A method of forming a capacitive substrate in which first and second conductors are formed opposite a dielectric, with one of these electrically coupled to a thru-hole connection. Each functions as an electrode for the resulting capacitor. The substrate is then adapted for being incorporated within a larger structure to...

20060154433 - Semiconductor device having mim element: A semiconductor device having: a semiconductor substrate; a plurality of semiconductor elements formed in the semiconductor substrate; a metal wiring made of a first metal layer and formed above the semiconductor substrate; a lower electrode made of the first metal layer and formed above the semiconductor substrate; a dielectric film...

20060154437 - Capacitor for semiconductor device and fabricating method thereof: A capacitor for a semiconductor device includes a first inter metal dielectric layer is disposed on a substrate. A first electrode is disposed on the first inter metal dielectric layer. A second electrode partially overlaps the first electrode. A first dielectric layer is disposed between the first and second electrodes....

20060154436 - Metal-insulator-metal capacitor and a fabricating method thereof: The present invention disclosed herein is a semiconductor capacitor and a method for fabricating the same. A semiconductor capacitor with multitiered metal oxide layers, including at least one metal oxide layer, wherein oxygen ions are implanted therein using a rapid thermal oxidation process in the presence of oxygen gars. Consequently,...

20060154435 - Method of fabricating trench isolation for trench-capacitor dram devices: A method of fabricating trench isolation for trench-capacitor DRAM devices. After the formation of deep trench capacitors, an isolation trench is etched into a substrate. The isolation trench is initially filled with a first insulating layer, which is then recessed into the isolation trench to a depth that is lower...

20060154438 - Method for manufacturing semiconductor device with trenches in substrate surface: In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on...

20060154439 - Method of fabricating semiconductor device: In a method of fabricating a semiconductor device, trenches are formed defining active regions at predetermined portions of a semiconductor substrate. A thermal oxide layer and a liner layer are sequentially formed covering inner walls of the trenches and upper surfaces of the active regions. Device isolation patterns are formed...

20060154440 - Forming channel stop for deep trench isolation prior to deep trench etch: Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion,...

20060154441 - Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate: A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on...

20060154443 - Bonding system having stress control: An approach where items of different temperatures are bonded to each other such that upon cooling down they contract in size resulting in zero residual stress between the bonded items at an ambient temperature. If materials of the bonded items have different thermal expansion coefficients and the items are put...

20060154444 - Method of forming wiring: A method for forming via holes includes placing an insulating layer on a first wiring layer, forming opening portions in the insulating layer, and forming a second wiring layer on the insulating layer. At the time of forming the opening portions, the insulating layer is irradiated with a laser beam...

20060154442 - Quasi-hydrophobic si-si wafer bonding using hydrophilic si surfaces and dissolution of interfacial bonding oxide: The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable...

20060154445 - Method for manufacturing soi wafer: The present invention provides a method for manufacturing an SOI wafer with high productivity in which generation of voids is suppressed in manufacturing the SOI wafer. The present invention comprises the steps of: forming an insulating layer on at least one wafer of two starting wafers; and adhering the one...

20060154446 - Method for fabricating semiconductor component with thnned substrate having pin contacts: A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In addition, the pin contacts are formed...

20060154447 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device comprises the steps of forming protruded electrodes on a plurality chip areas of a semiconductor wafer having the plurality of chip areas and boundary regions formed among the chip areas, both being provided in a surface of the semiconductor wafer, forming a surface-side...

20060154449 - Method of laser processing a wafer: A method of laser processing a wafer having a plurality of devices that are composed of a laminate layer laminated on the front surface of a substrate, along a plurality of streets for sectioning the devices, comprising a first groove forming step for applying a first laser beam having absorptivity...

20060154448 - Soi component comprising margins for separation: A method for producing a component is provided, in particular a deformation sensor, having a sensor element which includes at least one region that is sensitive with respect to expansion or compression, as well as electrical structures which are in connection therewith. To this end, a sacrificial layer is produced...

20060154450 - Semiconductor device and manufacturing method thereof: A manufacturing method of a semiconductor device in which the oxygen and carbon concentrations are reduced at the interface of each layer making up the semiconductor multilayer film. A first semiconductor layer is formed on a single-crystal substrate in a first reactor; the substrate is transferred from the first reactor...

20060154451 - Epitaxial growth method: An epitaxial growth method for forming a high-quality epitaxial growth semiconductor wafer is provided. The method includes forming a single crystalline layer on a single crystalline wafer; forming a mask layer having nano-sized dots on the single crystalline layer; forming a porous buffer layer having nano-sized pores by etching the...

20060154452 - Silicon film, crystalline film and method for manufacturing the same: A silicon film, crystalline film and method for manufacturing the same are provided. The silicon film and/or crystalline film may be an epitaxy-formed layer. A method for manufacturing a silicon film and/or crystalline film may include forming a insulating substrate, forming a buffer layer using a material selected from the...

20060154453 - Method(s) of forming a thin layer: A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a...

20060154455 - Gallium nitride-based devices and manufacturing process: A nitride semiconductor is grown on a silicon substrate by depositing a few mono-layers of aluminum to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer from aluminum nitride and a buffer structure including multiple superlattices of AlRGa(1-R)N semiconductors having different compositions...

20060154454 - Method for fabricating gan-based nitride layer: The present invention relates to a method for fabricating a gallium nitride(GaN) based nitride layer including a step of forming a wetting layer having of forming a wetting layer having a composition of In(x1)Ga(y1)N (0<x1≦1, 0≦y1<1, x1+y1=1) on the silicon carbide buffer layer, and a step of forming a nitride...

20060154456 - Crystallized semicoductor thin film manufacturing method and its manufacturing apparatus: A fabrication method of a crystallized semiconductor thin film is such that: by performing pulse irradiation of energy beams in a minute slit shape to a semiconductor thin film (5), the semiconductor thin film (5) of an region to which the energy beams are irradiated is fused and solidified over...

20060154457 - Method for varying the uniformity of a dopant as it is placed in a substrate by varying the speed of the implant across the substrate: The present invention provides a method for placing a dopant in a substrate and a method for manufacturing an integrated circuit. The method for placing a dopant in a substrate, among other steps, includes providing a substrate (340) and implanting a dopant within the substrate (340) using an implant (370),...

20060154458 - Method of forming ultra shallow junctions: A method of forming ultra shallow junctions in p-type devices uses aluminum ion to implant n-doped silicon, followed a low temperature anneal to activate and diffuse the aluminum. The use of aluminum provides numerous advantages over boron such as the ability to form shallower junctions, lower resistivity, and the ability...

20060154459 - Manufacturing method which prevents abnormal gate oxidation: A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, includes forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on the insulating film; forming an impurity diffusion preventing film on...

20060154460 - Self-aligned contact method: In one aspect, a self-aligned contact method is provided in which a substrate having a plurality of structures are spaced apart over a surface of the substrate, and a sacrificial film is deposited over and between the plurality of structures, where a material of the sacrificial film has a given...

20060154461 - Fully silicided field effect transistors: Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching...

20060154462 - Method of manufacturing semiconductor device: A silicon film is formed on a first region and a second region, respectively of a semiconductor substrate; P-type impurities are selectively ion-implanted into the silicon film in the first region; a first annealing is carried out, thereby the P-type impurities implanted in the silicon film are activated; N-type impurities...

20060154463 - Wiring patterns formed by selective metal plating: Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is...

20060154465 - Method for fabricating interconnection line in semiconductor device: Provided is a method for fabricating an interconnection line in a semiconductor device. The method includes forming a dielectric layer pattern including a region for forming the interconnection line on a semiconductor substrate, forming a diffusion barrier layer on the dielectric layer pattern, forming a first adhesion layer on the...

20060154464 - Semiconductor device and a method of fabricating a semiconductor device: A semiconductor device includes a semiconductor substrate; a porous low k dielectric disposed on the semiconductor substrate having a plurality of trenches therein, the porous low k dielectric having an effective dielectric constant of 3.0 or less; a plurality of barrier layers provided on each surface of the trenches, each...

20060154466 - Fabrication method for arranging ultra-fine particles: A method and resultant device, in which metal nanoparticles are self-assembled into two-dimensional lattices. A periodic hole pattern (wells) is fabricated on a photoresist substrate, the wells having an aspect ratio of less than 0.37. The nanoparticles are synthesized within inverse micelles of a polymer, preferably a block copolymer, and...

20060154467 - Method for the production of a memory cell, memory cell and memory cell arrangement: The invention relates to a method for the production of a memory cell, a memory cell and a memory cell arrangement. According to the inventive method for the production of a memory cell, a first electrically conductive area is formed in and/or on a substrate. A second electrically conductive area...

20060154468 - Manufacturing method of semiconductor device, semiconductor device, circuit board, electro-optic device, and electronic apparatus: A method for manufacturing a semiconductor device with a bump electrode wherein the bump electrode includes a resin material as a core and at least a top surface covered with a conductive film. The method includes placing the resin material on a substrate on which an electrode terminal is formed...

20060154471 - Dual damascene interconnections having low k layer with reduced damage arising from photoresist stripping: A method and apparatus is provided for fabricating a dual damascene interconnection. The method begins by forming on a substrate a dielectric layer that includes an organosilicon material, forming a via photoresist pattern over the dielectric layer, and etching a via in the dielectric layer using the via photoresist pattern...

20060154470 - Integrated circuit having structural support for a flip-chip interconnect pad and method therefor: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more...

20060154469 - Method and apparatus for providing structural support for interconnect pad while allowing signal conductance: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the...

20060154472 - Etching method, program, computer readable storage medium and plasma processing apparatus: A difference in etching rate between the coated silicon based insulating film and any of other kinds of silicon-based insulating films is reduced by using nitrogen gas as a part of the etching gas. Therefore, the underlying film may not be exposed to the etching gas for a long time,...

20060154473 - Semiconductor device and method of manufacturing the same: The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a...

20060154474 - Method of fabricating metal silicide layer: A method of fabricating a metal silicide layer over a substrate is provided. First, a hard mask layer is formed over a gate formed on a substrate and a portion of the substrate is exposed. Thereafter, a first metal silicide layer, which is a cobalt silicide or a titanium silicide...

20060154475 - Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the...

20060154476 - Bipolar transistor with collector having an epitaxial si:c region: A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region...

20060154478 - Contact hole structures and contact structures and fabrication methods thereof: Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without...

20060154477 - Polymer spacer formation: A polymer spacer material may increase the dimensions of the patterned photoresist that is used as a mask to etch the layers below the photoresist, which in turn translates into smaller dimensions etched into the underlying materials. This allows for the formation of integrated circuits having smaller features, smaller overall...

20060154479 - Baking apparatus used in photolithography process, and method for controlling critical dimension of photoresist patterns using the same: A baking apparatus used in a photolithography process of a semiconductor device, and a method for controlling critical dimension of a photoresist pattern using the same. The baking apparatus comprises: a processing chamber; a chuck disposed in the processing chamber on which a semiconductor wafer can be loaded; and a...

20060154480 - Vaporizer for cvd, solution voporizing cvd system and voporization method for cvd: The vaporizer for CVD of the present invention comprises: the pipes for the plurality of raw-material solutions, each pipe supplying the plurality of raw-material solutions separately from one another; the pipe for the carrier gas provided in a manner covering outwards of the pipes for the raw-material solutions, the pipe...

20060154481 - Decreasing metal-silicide oxidation during wafer queue time: Disclosed herein are various embodiments of semiconductor devices and related methods of manufacturing a semiconductor device. In one embodiment, a method includes providing a semiconductor substrate and forming a metal silicide on the semiconductor substrate. In addition, the method includes treating an exposed surface of the metal silicide with a...

20060154483 - Method of providing a structure using self-aligned features: In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the...

20060154482 - Semiconductor device: An object of the invention is to make it possible to perform the embedding of a Cu diffusion preventing film and a Cu film to a fine pattern of a high aspect ratio by using a medium of a supercritical state in a manufacturing process of a semiconductor device. The...

20060154484 - Method of removing a low-k layer and method of recycling a wafer using the same: In one embodiment, a method of removing a low-k layer at a low cost and a method of recycling a wafer using the same, is described. A fluoride treatment is performed on the low-k layer formed on an object using an aqueous hydrogen fluoride solution, and the low-k layer is...

20060154485 - Sacrificial layers comprising water-soluble compounds, uses and methods of production thereof: Sacrificial composition and/or coating materials contemplated herein for use in semiconductor and electronic applications comprise at least one water-soluble compound and/or at least one water-soluble compound precursor and at least one solvent. Sacrificial materials and/or compositions may be produced by a method, comprising: a) providing at least one water-soluble compound...

20060154486 - Low-pressure removal of photoresist and etch residue: A method is provided for plasma ashing to remove photoresist remnants and etch residues formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving a hydrogen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to...

20060154487 - Etching process to avoid polysilicon notching: A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the...

20060154488 - Semiconductor device and fabrication process thereof: A method of fabricating a semiconductor device includes a dry etching process of a silicon surface. The dry etching process is conducted by an etching gas containing at least one gas species selected from the group consisting of: HBr, HCl, Cl2, Br2 and HI, wherein the dry etching process includes...

20060154490 - Liquid treating apparatus: A liquid treating apparatus includes an etchant discharging nozzle for discharging a treating solution (E) onto an upper surface of a film carrier tape for mounting an electronic component (T) from above and a treating solution contact prevention chamber disposed on an upstream side of a liquid treating start position...

20060154489 - Semiconductor base structure for molecular electronics and molecular electronic-based biosensor devices and a method for producing such a semiconductor base structure: The invention concerns a structured semiconductor surface as basis for molecular electronics or molecular electronics-based bio-sensors. The starting point is a heterostructure consisting of two undoped layers of a semiconductor material that are separated by an extremely thin (a few nm) layer of a different semiconductor material. This material stack...

20060154491 - Method for reducing argon diffusion from high density plasma films: A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used for generating the high density plasma. The first step deposition uses high argon concentration and low sputter etch-to-deposition (E/D) ratio. High...

20060154492 - Forming method of low dielectric constant insulating film of semiconductor device, semiconductor device, and low dielectric constant insulating film forming apparatus: It is an object of the present invention to cure an insulating film of a semiconductor device in a short time while keeping a low dielectric constant. In the present invention, a coating film made of porous MSQ is formed on a substrate, the substrate on which the porous MSQ...

20060154493 - Method for producing gate stack sidewall spacers: A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materials may be silicon carbide,...

20060154494 - High-throughput hdp-cvd processes for advanced gapfill applications: Methods are provided of depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A silicon-containing gas, an oxygen-containing gas, and a fluent gas are flowed into the substrate processing chamber. The fluent gas has an...

20060154495 - Device for cleaning the surface of a component: A detached particle capture means by laser (4) allows them to be attracted and prevented from dropping back better than a traditional blow-off flushing means would. Various categories of attractive forces may be implemented. It will also be possible to use a particle destruction means, like a second high-power laser...

20060148105 - Ferromagnetic material: A method is provided for producing a doped dilute ferromagnetic semiconductor material, by doping Zinc Oxide in bulk form with manganese to a maximum level of 5 atomic percent concentration. The material is preferably sintered at a maximum temperature of 650° C. The result of this process is a semiconductor...

20060148107 - Method for fabricating semiconductor device: A material of low viscosity is applied to a ferroelectric film 32 formed by MOCVD to form a buried layer 34. Then, anisotropic etching is made on the entire surface to remove the tops of convexities on the surface of the ferroelectric film 32, and the buried layer 34 remaining...

20060148108 - Method for fabricating semiconductor device: A conduction film 36 is formed in a larger design thickness value on a ferroelectric film 32 by MOCVD, and the entire surface of the conduction film 36 is anisotropically etched back, whereby the surface morphology of the conduction film 36 can be improved. The conduction film 36, whose surface...

20060148106 - On-chip signal transformer for ground noise isolation: A mixed-signal chip having a signal transformer located between analog circuitry and digital circuitry. The signal transformer includes a primary winding electrically coupled to the analog circuitry and a secondary winding electrically coupled to the digital circuitry. The primary and secondary windings are magnetically coupled with one another via a...

20060148109 - Novel wafer repair method using direct-writing: A method of wafer repairing comprises identifying locations and patterns of defective regions in a semiconductor wafer; communicating the locations and patterns of defective regions to a direct-writing tool; forming a photoresist layer on the semiconductor wafer; locally exposing the photoresist layer within the defective regions using an energy beam;...

20060148110 - Method for forming locos layer in semiconductor device: A method for forming a LOCOS layer in a semiconductor device includes steps of oxidizing a high voltage region of the semiconductor device to form a LOCOS layer in the high voltage region; and etching the LOCOS layer according to a pattern....

20060148111 - Method for automatic measurement of failure in subthreshold region of metal-oxide-semiconductor transistor: A method for detecting an abnormal condition of a MOS transistor in a subthreshold region. The method includes measuring a variation in a drain current with respect to a variation of a gate voltage of the MOS transistor to obtain a characteristics curve, and calculating, with reference to the obtained...

20060148113 - Chain resistance pattern and method of forming the same: A chain resistance pattern and a method of forming the same enable a test pattern to obtain maximum measurement results using minimum area and enable accurate detection of process errors. The chain resistance pattern includes an active layer for receiving an externally applied optical signal, a plurality of conductive layers...

20060148112 - Electrode design: Electrodes of a double-layer capacitor are designed so that sub-capacitors formed at each electrode are stressed substantially equally at the rated voltage of the double-layer capacitor. In an exemplary embodiment, each electrode includes a current collector and an active electrode layer, such as a layer of activated carbon. The electrodes...

20060148114 - Method of forming mask and mask: A method of forming a mask, in which a film pattern is formed on a substrate by using a mask, includes sequentially arranging the mask, the substrate and a first member having a flat surface contacting with the substrate in this order from a supply source of film forming material;...

20060148115 - Method of fabricating vertical structure compound semiconductor devices: A method of fabricating a vertical structure opto-electronic device includes fabricating a plurality of vertical structure opto-electronic devices on a crystal substrate, and then removing the substrate using a laser lift-off process. The method then fabricates a metal support structure in place of the substrate. In one aspect, the step...

20060148116 - Method of making a support for light emitting diodes which are interconnected in a three-dimensional environment: The present invention relates to a method of making supports for light emitting diodes, wherein rigid substrates are used as supports for light emitting diodes, it being proposed, in particular, to render the substrates more fragile in order to make certain zones of a lower layer of the said substrate...

20060148117 - Process for producing a thin film with mems probe circuits: A process for producing a thin film with MEMS probe circuits by using semiconductor process technology comprises steps of providing a flatted process substrate; forming a separable interface on the flatted process substrate; forming a probe circuit thin film with electric circuits, probes and circuit contacts on the separable interface;...

20060148118 - Fabrication of array ph sensitive egfet and its readout circuit: A method for fabricating an array pH sensor and a readout circuit device of such array pH sensor are implemented by utilizing an extended ion sensitive field effect transistor to construct the array pH sensor and related readout circuit. The structure of the array sensor having this extended ion sensitive...

20060148119 - Quantum efficiency enhancement for cmos imaging sensor with borderless contact: The present invention is CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS type photodiode with borderless contact. The image sensor comprises a N-well/P-substrate type photodiode with borderless contact and dielectric structure covering the photodiode region. The...

20060148120 - Deuterium alloy process for image sensors: A method of alloying an image sensor is disclosed. The method comprises forming various semiconductor devices in a semiconductor substrate. Then, an insulator layer is formed over the semiconductor devices. Finally, deuterium gas is used to alloy said image sensor after the insulator oxide layer has been formed and prior...

20060148121 - Method and structure for forming an integrated spatial light modulator: A method of fabricating an integrated spatial light modulator. The method includes providing a first substrate including a bonding surface, processing a device substrate to form at least an electrode layer, the electrode layer including a plurality of electrodes, and depositing a standoff layer on the electrode layer. The method...

20060148122 - Cmos image sensor and method for manufacturing the same: A CMOS image sensor and a method for manufacturing the same are provided, in which a pad opening is formed simultaneously with the formation of a microlens. The CMOS image sensor includes a nitride layer for passivation deposited on an oxide layer, wherein a sacrificial microlens having a microlens structure...

20060148123 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor includes forming a metal pad on a pad region of a semiconductor substrate having an active region and the pad region, forming an insulating film on an entire surface of the semiconductor substrate including the metal pad, forming an opening to expose...

20060148124 - Nanoparticle conjugates and method of production thereof: The present invention provides a method for the preparation of nanoparticle conjugates comprising: protocols for synthesizing intermediate product molecules by introducing known numbers of two or more substituents into a flexible hydrophilic polymer, where one substituent is capable, optionally after deprotection, of binding to a nanoparticle, and where the other...

20060148125 - Phase changable memory device structures: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole...

20060148126 - Method for manufacturing printed wiring board: There is provided a method for manufacturing a flat printed wiring board in which spaces between circuit patterns are filled with a resin. The method comprises: laminating via a mold release film a plurality of sets of laminated bodies formed by superposing a semi-cured resin sheet on a printed wiring...

20060148127 - Method of manufacturing a cavity package: A method of making a package for an integrated circuit die. In one embodiment the method comprises providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of...

20060148128 - Signal transfer film, display apparatus having the same and method of manufacturing the same: A signal transfer film includes a base film, a lead line formed on the base film and a passivation layer protecting the lead line. The passivation layer includes a nonlinear edge portion formed at a boundary region between the lead line and the passivation layer. The nonlinear edge portion of...

20060148129 - Silicon direct bonding method: A silicon direct bonding method including preparing two silicon substrates having corresponding bonding surfaces, forming a trench in at least one bonding surface of the two silicon substrates, and thermally bonding the two silicon substrates to one another. The trench may be along a dicing line. The trench may communicate...

20060148130 - Memory chip and semiconductor device using the memory chip and manufacturing method of those: In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A...

20060148131 - Dicing/die-bonding film, method of fixing chipped work and semiconductor device: A dicing/die-bonding film including a pressure-sensitive adhesive layer (2) on a supporting base material (1) and a die-bonding adhesive layer (3) on the pressure-sensitive adhesive layer (2), wherein a releasability in an interface between the pressure-sensitive adhesive layer (2) and the die-bonding adhesive layer (3) is different between an interface...

20060148132 - Method of fabricating a vacuum sealed microdevice package with getters: One embodiment of the invention relates to a microdevice package containing getters for maintaining a constant vacuum level within the sealed microdevice package. A stacked wafer assembly, containing a plurality of microdevice packages, is formed by aligning a bottom cover wafer with a center wafer. The bottom cover wafer includes...

20060148133 - Method of forming a mems device: A method of forming a MEMS device first releases structure, relative to a substrate, to form a space between the structure and the substrate. The process then adds material to the space between the structure and the substrate to substantially stabilize the structure relative to the substrate. Then, at some...

20060148134 - Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby: In a method of fabricating a semiconductor device capable of reducing parasitic capacitance between bit lines and a semiconductor device fabricated by the method, the semiconductor device includes a semiconductor substrate having buried contact landing pads and direct contact landing pads. A lower interlayer insulating layer is disposed on the...

20060148136 - Patterned plasma treatment to improve distribution of underfill material: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate...

20060148135 - Semiconductor memory cell and method of forming same: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is...

20060148138 - Field transistor monitoring pattern for shallow trench isolation defects in semiconductor device: A field transistor monitoring pattern has two active areas, i.e., a source region and a drain region, spaced apart from each other by an STI area intervening therebetween. The STI area is generally narrower than each active area. The monitoring pattern further has two gate patterns, each having a gate...

20060148137 - Integrated mems packaging: An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall...

20060148140 - Method for forming a silicon oxynitride layer: A method for forming a silicon oxynitride layer, suitable to be used in the production of semiconductor devices, e.g. poly-silicon thin film transistors, is provided. A plasma surface treatment is performed over a substrate after a silicon nitride/silicon oxide layer has been formed on the substrate by a glow discharge...

20060148141 - Method of manufacturing a flexible thin film transistor array panel including plastic substrate: A method of manufacturing a flexible display is provided, which includes forming a gate line including a gate electrode on a substrate, sequentially depositing a gate insulating layer covering the gate line, and a semiconductor layer, firstly etching the semiconductor layer; secondly etching the semiconductor layer, forming a data line...

20060148139 - Selective second gate oxide growth: The invention comprises a method of dual oxide gate formation comprising the steps of forming a first gate oxide and forming a second gate oxide using in-situ steam generation oxidation....

20060148142 - High-sensitivity image sensor and fabrication method thereof: A method of fabricating a high-sensitivity image sensor and the same are disclosed. The disclosed method comprises: etching predetermined regions of active silicon and a buried oxide layer of a SOI substrate by using a mask to expose an N-type silicon substrate; implanting P-type ions into the exposed N-type silicon...

20060148143 - Method of creating a ge-rich channel layer for high-performance cmos circuits: A method of forming a surface Ge-containing channel which can be used to fabricate a Ge-based field effect transistor (FET) which can be applied to semiconductor-on-insulator substrates (SOIs) is provided. The disclosed method uses Ge-containing ion beams, such as cluster ion beams, to create a strained Ge-containing rich region at...

20060148144 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device providing insulation between a plurality of MOS transistors without device isolation regions. The method includes forming a first insulation layer on a substrate, exposing a portion of the substrate by etching the first insulation layer using a resist, growing an epitaxial layer on...

20060148146 - Method for forming a transistor for reducing a channel length: A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorphous region at a lower part of both sidewalls...

20060148145 - Method of manufacturing an rf mos semiconductor device: A method of manufacturing an RF MOS semiconductor device includes: forming a gate stack including a gate oxide layer and a gate polysilicon layer on a silicon substrate; forming source/drain regions aligned with both sidewalls of the gate stack in the silicon substrate; forming spacers on both sidewalls of the...

20060148147 - Mobility enhanced cmos devices: Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the...

20060148148 - Semiconductor device manufacturing method: A method of forming a semiconductor device in which a native oxide film is removed is disclosed. The native oxide film is initially formed by a damaging double ion implantation process. Thus, the method provides for the formation of a uniform salicidation layer, by forming regions where an ion implantation...

20060148149 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is disclosed. The method provides etching a predetermined region of a semiconductor substrate prior to formation of a device isolation film defining an active region and forming a gate having a stepped gate channel....

20060148151 - Cmos transistor junction regions formed by a cvd etching and deposition sequence: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching...

20060148152 - Method of manufacturing semiconductor devices: A method of manufacturing a semiconductor device including forming a dummy gate electrode which is divided into first and second areas, selectively implanting N-type ions and P-type ions into the first and second areas of the dummy gate electrode respectively and then implanting impurity ions into a boundary region between...

20060148153 - Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses and related devices: Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided...

20060148150 - Tailoring channel dopant profiles: Higher mobility transistors may be achieved by removing a dummy metal gate electrode as part of a replacement metal gate process and doping the exposed channel region after source and drains have already been formed. As a result, a retrograde doping profile may be achieved in some embodiments in the...

20060148154 - Semiconductor devices having faceted channels and methods of fabricating such devices: Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure...

20060148159 - Cmos image sensor and fabricating method thereof: A CMOS image sensor and fabricating method thereof are disclosed, by which a light condensing effect is enhanced by providing an inner microlens to a semiconductor substrate. The present invention includes a plurality of photodiodes on a semiconductor substrate, a plurality of inner microlenses on a plurality of the photodiodes,...

20060148156 - Gan-based permeable base transistor and method of fabrication: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same....

20060148157 - Geometrically optimized spacer to improve device performance: A CMOS device with trapezoid shaped spacers and a method for forming the same with improved critical dimension control and improved salicide formation, the CMOS device including a semiconductor substrate; a gate structure comprising a gate dielectric on the semiconductor substrate and a gate electrode on the gate dielectric; trapezoid...

20060148160 - Method for fabricating cmos image sensor: In a method for fabricating a CMOS image sensor, microlenses are formed with a silicon nitride layer formed on a pad such that it is possible to decrease a height of microlens and to improve a refraction ratio. In addition to main lenses in shape of curved surface, inner lenses...

20060148158 - Method for forming gate of semiconductor device: There is provided a method for forming a gate using a gate layout of a semiconductor device. The layout includes an active region with a stepped side boundary, a plurality of gates crossing over the active region, and tabs attached to the gates on the side boundary of the active...

20060148161 - Method for reducing poly-depletion in dual gate cmos fabrication process: Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical...

20060148155 - Semiconductor fabrication and structure for field-effect and bipolar transistor devices: Semiconductor devices have device regions in which semiconductor properties such as spreading resistivity and its profile are significant. In making a p-type device region on a semiconductor wafer, an initial semiconductor device region is defined by a buried region, and an initial spreading resistivity profile is developed by annealing. After...

20060148162 - Soi sram device structure with increased w and full depletion: An SOI device, and a method for producing the SOI device, for use in an SRAM memory having enhanced stability. The SRAM is formed with a wider W and a fully-depleted FET. The wider FET is extended by an expitaxial silicon sidewall, and the performance of the FET is improved....

20060148164 - Method of fabricating fin field-effect transistors: A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming a first insulating layer and a second insulating...

20060148163 - Method of forming gate insulation layers of different characteristics: The present invention describes a method for forming different types of gate insulation layers, wherein the formation of one type of gate insulation layer is highly decoupled from the formation of the other type of gate insulation layer. Thus, in some embodiments, critical oxidation processes may finely be tuned on...

20060148166 - Assembly comprising functional devices and method of making same: Methods and apparatuses for an electronic assembly. A material is selectively printed on a web substrate at one or more selected areas. The web substrate includes a plurality of functional components having integrated circuits. A local printing system equipped with a print head that dispenses the selected material is used...

20060148165 - Crystallization apparatus and method of amorphous silicon: A silicon crystallization system includes a beam generator generating a laser beam, first and second optical units for controlling the laser beam from the beam generator; and a stage for mounting a panel including an amorphous silicon layer to be polycrystallized by the laser beam from the optical units. The...

20060148167 - Electronic devices: A method for forming an electronic device in a multilayer structure comprising the steps of: defining a topographic profile in a laterally extending first layer; depositing at least one non-planarizing layer on top of the first layer such that the topographic profile of the surface of the or each non-planarizing...

20060148168 - Process for fabricating dynamic random access memory: A method of fabricating a dynamic random access memory is provided. A word line structure is formed on a substrate. A source region and a drain region are formed in the substrate on each side of the word line structure. Spacers are formed on the sidewalls of the word line...

20060148170 - Fabricating method of semiconductor device: A fabricating method of a semiconductor device includes: forming a first metal layer on a substrate and patterning the first metal layer to form a bottom metal line and a bottom electrode of a capacitor; forming an interlayer insulating layer on the resulting structure; forming a via hole in the...

20060148169 - Mehods of fabricating mim capacitors: Methods of fabricating MIM capacitors are provided. One example method includes forming an insulating layer including a void on a semiconductor substrate, forming a first hole connected to the void by patterning the insulating layer, forming a lower electrode by forming a tungsten layer filling in the first hole such...

20060148172 - Local sonos-type nonvolatile memory device and method of manufacturing the same: Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer...

20060148171 - Method of fabricating a flash memory device: A method of fabricating a flash memory device, having a double gate structure, including an oxide/nitride/oxide (ONO) layer, provides more stable operation by using a dummy pattern upon forming the ONO layer and using a control gate after forming a floating gate. The method includes steps of forming a floating...

20060148173 - Method for manufacturing electronic memory devices integrated in a semiconductor substrate including non-volatile memory matrix and associated circuitry: The method is for manufacturing electronic memory devices on a semiconductor substrate including a non-volatile memory matrix and associated circuitry. The method includes forming a first insulation layer, a conductive layer and a second insulation layer. A resist mask is formed corresponding with the memory matrix to define a predetermined...

20060148174 - Method for forming recess gate of semiconductor device: A method for forming a recess gate of a semiconductor device is disclosed. The method for forming a recess gate of a semiconductor device comprises forming a polysilicon layer pattern covering a contact region on a semiconductor substrate, etching a predetermined thickness of the semiconductor substrate in the active region...

20060148175 - Method of manufacturing a flash memory device: A method of manufacturing a semiconductor device includes forming a polysilicon layer on a trench isolation layer and a tunnel oxide layer formed on a semiconductor substrate, and doping the polysilicon layer with germanium or argon. The doped polysilicon layer is patterned to form a floating gate electrode layer pattern....

20060148176 - Method of manufacturing a gate in a flash memory device: A method of manufacturing a gate in a flash memory device. The method includes forming a stacking structure including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate on a semiconductor substrate. The further includes removing a remaining portion of the tunnel oxide layer exposed...

20060148177 - Method for forming split gate flash nonvolatile memory devices: Disclosed is a method for forming a non-volatile memory device, comprising the steps of: successively depositing a gate oxide and a floating gate material on a semiconductor substrate; depositing and selectively etching a first dielectric on the floating gate material to form a first dielectric pattern; forming a first floating...

20060148178 - Method for producing a vertical transistor: The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably reduce or entirely avoid negative effects that normally result...

20060148180 - Atomic layer deposited hafnium tantalum oxide dielectrics: A dielectric layer containing an atomic layer deposited hafnium tantalum film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. In an embodiment, a hafnium tantalum oxide film is formed by depositing hafnium and tantalum by atomic layer...

20060148179 - Method of fabricating nitrogen-containing gate dielectric layer and semiconductor device: A method of fabricating a nitrogen-containing gate dielectric layer is described. First, a gate dielectric layer is formed on a substrate by performing a dilute wet oxidation process. Then, a nitridation step is performed for doping nitrogen into the gate dielectric layer. After that, a re-oxidation step is performed for...

20060148182 - Quantum well transistor using high dielectric constant dielectric layer: A quantum well transistor or high electron mobility transistor may be formed using a replacement metal gate process. A dummy gate electrode may be used to define sidewall spacers and source drain contact metallizations. The dummy gate electrode may be removed and the remaining structure used as a mask to...

20060148181 - Strained channel cmos device with fully silicided gate electrode: A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region...

20060148183 - Semiconductor device having high voltage mos transistor and fabrication method thereof: A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an...

20060148184 - Method for forming ldmos channel: A method of forming an LDMOS channel is provided. The method includes forming a conductive epitaxial layer on a semiconductor substrate, forming a photoresist pattern, implanting P-type and N-type ions with a first level of energy by using a tilt implantation method onto the semiconductor substrate, and implanting P-type ions...

20060148185 - Method for manufacturing high voltage transistor: A method for manufacturing a high voltage transistor is disclosed. The method includes sequentially forming gate oxide films, polysilicon layers, and silicon nitride films on a semiconductor substrate; patterning the silicon nitride films, the polysilicon layers, and the gate oxide films using photolithographic and isotropic etching processes to form nitride...

20060148186 - Method and apparatus for manufacturing gallium nitride based single crystal substrate: A method and apparatus for manufacturing a nitride based single crystal substrate. The method includes placing a preliminary substrate on a susceptor installed in a reaction chamber; growing a nitride single crystal layer on the preliminary substrate; and irradiating a laser beam to separate the nitride single crystal layer from...

20060148187 - Self-aligned bipolar semiconductor device and fabrication method thereof: A self-aligned bipolar semiconductor device and a fabrication method thereof are provided. After a silicon layer and a collector contact are formed on a buried collector layer, an oxide dummy pattern is formed on the silicon layer to define both an extrinsic base and an intrinsic base. A polycide layer...

20060148188 - Fabrication method for bipolar integrated circuits: A fabrication method is applied to the bipolar integrated circuit, which combines with various patterns of the masks using in the different processes to form a combination mask. By using the combination mask, a silicon dioxide layer is etched to produce the open windows required in the different processes. Thereafter,...

20060148189 - Method for forming resistors in semiconductor integrated circuit devices: Disclosed is a method for forming resistors in semiconductor integrated circuit device, comprising the steps of: depositing a pad oxide on a semiconductor substrate; depositing silicon nitride on the pad oxide; depositing photoresist on entire surface of the substrate; transferring patterns of trenches to the photoresist to form photoresist pattern,...

20060148190 - Methods of forming a plurality of capacitors: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining...

20060148192 - Damascene mim capacitor structure with self-aligned oxidation fabrication process: A self aligned MIM capacitor structure and method for forming the same, the method including forming a metal filled damascene having an exposed surface in a dielectric insulating layer; forming a metal precursor layer on the exposed surface; carrying out a process on the metal precursor layer selected from the...

20060148193 - Methods for forming ruthenium films with beta-diketone containing ruthenium complexes and method for manufacturing metal-insulator-metal capacitor using the same: Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium...

20060148191 - Self aligning electrode and method of making the same: Electrodes are constructed with pressure-bonding techniques that simplify alignment of various electrode components during lamination. In an exemplary embodiment, a current collector is made from aluminum foil that has been roughed or pitted on both surfaces. The surfaces of the current collector can be further treated to enhance adhesion properties...

20060148194 - Method of fabricating a semiconductor device: A method of fabricating a semiconductor device includes steps of forming at least one shallow-trench isolation region in a semiconductor substrate; forming a photoresist pattern for blocking a photodiode region; sequentially implanting dopant ions and boron ions into the at least one shallow-trench isolation region; and activating the implanted ions....

20060148195 - Manufacturing isolation layer in cmos image sensor: A method of manufacturing an isolation layer in a CMOS image sensor injects oxygen and P-type ions into a device isolation region without etching damage and performs a heating process to form a device isolation layer in a semiconductor substrate. An ion injection mask layer is formed that exposes a...

20060148199 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device includes the steps of sequentially forming a pad oxide layer and a pad nitride layer on a substrate, the pad oxide layer including a first oxide layer formed on an upper surface of the substrate and a second oxide layer formed on a...

20060148201 - Method for forming an sti in a flash memory device: The present invention provides a method of forming an STI region in a flash memory device. The method includes: forming a pad oxide layer on a semiconductor substrate; forming a hard mask on the pad oxide layer; forming a recess groove below the hard mask by etching a portion of...

20060148198 - Method for forming device isolation region in semiconductor device: An exemplary method of forming a device isolation region in a semiconductor device according to an embodiment of the present invention includes forming a sacrificial layer and a hard mask on a substrate; selectively etching the hard mask, the sacrificial layer, and the substrate so as to form a trench;...

20060148202 - Method for forming shallow trench isolation in semiconductor device: A method for forming shallow trench isolation in a semiconductor device including forming a pad oxide, a pad nitride, and a pore-generating layer on an entire surface of a semiconductor substrate in successive order; etching the pore-generating layer, the pad nitride, the pad oxide and the substrate to form a...

20060148197 - Method for forming shallow trench isolation with rounded corners by using a clean process: In a method for forming STI in a silicon substrate having a pad oxide over the substrate, a hard mask is formed over the pad oxide, the hard mask and the pad oxide are patterned to form an opening, the silicon substrate is etched through the opening to form a...

20060148200 - Method of forming isolation oxide layer in semiconductor integrated circuit device: A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming first active regions, a second oxide layer is deposited thereon, and the first and second...

20060148204 - Monitoring pattern for optimization of chemical mechanical polishing process of trench isolation layer and related methods: A monitoring pattern includes unique active area arrays, each having at least two active areas separated and defined by a trench isolation area filled with a trench isolation layer. Each active area array differs from the others in shape, size, spaced distance, extending direction, and/or density. In a monitoring method,...

20060148203 - Semiconductor device and fabricating method thereof: A semiconductor device and fabricating method thereof are provided. A dual gate oxide layer is formed by thermal oxidation after carrying out a prescribed pre-processing on an STI edge, which results in a high quality oxide layer by thermal oxidation and a uniformly maintained gate oxide layer thickness of a...

20060148196 - Semiconductor fabrication process including recessed source/drain regions in an soi wafer: A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is...

20060148205 - Semiconductor manufacturing method for device isolation: Provided is a manufacturing step of an element isolation by forming an isolation trench in an element isolation region of a semiconductor substrate, forming an HDP film over the semiconductor substrate including the inside of the isolation trench, and then polishing the HDP film by CMP to remove the HDP...

20060148206 - Valve operating assembly and method of manufacturing: The present invention relates to a leakdown plunger, comprising a first plunger opening, a second plunger opening, and an outer plunger surface that is provided with an axis and encloses an inner plunger surface, the first plunger opening is provided with a first annular plunger surface shaped to accommodate a...

20060148207 - Method of dual bird's beak locos isolation: A method of dual bird's beak LOCOS may reduce a design rule for a more cost-effective logic device formation. The method may also form a LOCOS layer having a smooth bird's beak to fabricate a stable high-voltage device. The method includes steps of defining a low-voltage device area for a...

20060148208 - Method for producing a silicon-on-insulator structure: The inventive method for producing a silicon-on insulator structure consists in implanting hydrogen is a silicon plate (1), chemically treating said silicon plate (1) and a substrate (3), in connecting and grafting the silicon plate (1) and the substrate (3) and in layering along the implanted layer (2) of the...

20060148209 - Methods for manufacturing porous dielectric substrates including patterned electrodes: A method for manufacturing a porous dielectric substrate including patterned electrodes includes a patterned electrode-forming step of preparing a support plate having a releasable flat face and then forming the patterned electrodes on the flat face, a porous dielectric substrate-forming step of feeding a material for forming the porous dielectric...

20060148210 - Laser beam processing machine: A laser beam processing machine comprising a chuck table for holding a workpiece, a laser beam application means for applying a laser beam to the workpiece held on the chuck table, and a processing-feed means for moving the chuck table and the laser beam application means relative to each other,...

20060148211 - Wafer dividing method: A wafer dividing method for cutting a wafer having devices which are composed of a laminate laminated on the front surface of a substrate with a cutting blade along a plurality of streets for sectioning the devices, comprising the steps of a groove forming step for forming two grooves deeper...

20060148212 - Method for cutting semiconductor substrate: Multiphoton absorption is generated, so as to form a part which is intended to be cut 9 due to a molten processed region 13 within a silicon wafer 11, and then an adhesive sheet 20 bonded to the silicon wafer 11 is expanded. This cuts the silicon wafer 11 along...

20060148213 - Method of manufacturing display device: Y-scribe lines are successively formed substantially in parallel in a first direction of a work that constitutes a display device. An X-scribe line is formed in a second direction that intersects the first direction of the work. The X-scribe line is formed between the Y-scribe lines and is spaced apart...

20060148214 - Method for manufacturing strained silicon: In accordance with a particular embodiment of the present invention, a method for manufacturing strained silicon is provided. In one embodiment, the method for manufacturing strained silicon includes inducing a curvature in a silicon wafer, depositing an epitaxial layer of silicon upon an upper surface of the silicon water while...

20060148215 - Method of fabricating a field effect transistor having improved junctions: A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of...

20060148216 - Semiconductor film, semiconductor device and method for manufacturing same: Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method,...

20060148218 - Method for manufacturing a semiconductor thin film: A little amount of nickel is introduced into an amorphous silicon film formed on a glass substrate to crystallize the amorphous silicon film by heating. In this situation, nickel elements remain in a crystallized silicon film. An amorphous silicon film is formed on the surface of the crystallized silicon film...

20060148217 - Method of annealing polycrystalline silicon using solid-state laser and devices built thereon: The invention provides a method of forming polycrystalline silicon comprising the steps of: forming a layer of amorphous silicon, forming a layer of metal or metal-containing compound on the layer of amorphous silicon, annealing the layer of amorphous silicon and said layer of metal to form a polycrystalline silicon layer,...

20060148219 - Method for photomask processing: A method for photomask processing including the formation of a photoresist pattern for a P-Well. The method further includes implanting ions for the P-well using the photoresist pattern as an ion implantation mask, coating another photoresist for the N-well that has a higher etch resistance than that of the photoresist...

20060148222 - Method for manufacturing semiconductor device: A method of manufacturing a semiconductor device prevents a shadow effect from occurring at the time of ion implantation by additionally performing a process of flowing a photoresist layer, which is used as a mask for ion implantation. The method includes forming a photoresist pattern over a strained silicon layer,...

20060148221 - Method of forming a stable transistor by dual source/drain implantation: A method of forming a transistor includes: forming a gate oxide layer and a gate polysilicon layer on a silicon substrate; forming low-energy ion implantation regions in the silicon substrate and in alignment with both sidewalls of the gate polysilicon layer; forming gate spacers on both sidewalls of the gate...

20060148220 - Plasma implantation of impurities in junction region recesses: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped...

20060148223 - Wafer surface pre-treatment with hydrogen for gate oxide formation: A method of pre-treating a wafer surface including loading the wafer into a furnace, purging the furnace to discharge oxygen gas by supplying nitrogen gas, and baking the wafer while hydrogen gas is supplied into the furnace at a defined temperature and for a defined time....

20060148224 - Method of forming ultra shallow junctions: A method of forming ultra shallow junctions in p-type devices uses aluminum ion to implant n-doped silicon, followed a low temperature anneal to activate and diffuse the aluminum. The use of aluminum provides numerous advantages over boron such as the ability to form shallower junctions, lower resistivity, and the ability...

20060148225 - Methods for fabricating strained layers on semiconductor substrates: Methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in...

20060148226 - Method of forming fine patterns in semiconductor device and method of forming gate using the same: There are provided a method of forming fine patterns in a semiconductor device, and a method of forming a gate with a fine critical dimension using the same. In the method of forming fine patterns in a semiconductor device, a plurality of sidewall buffer patterns are formed on a gate...

20060148227 - Method for fabricating a first contact hole plane in a memory module: A silicon dioxide layer is formed and a mask layer is deposited and then patterned to produce openings in the mask layer in the region around the gate contacts onto the gate electrode tracks in the logic region. The surface is uncovered around the gate contacts to the gate electrode...

20060148228 - Method for forming salicide layer in semiconductor device: A method for forming a silicide layer in a semiconductor device selectively forms a self-aligned layer of silicide in a salicidation area only, without having to use a salicide blocking material such as an oxide or a nitride. The method includes steps of defining a salicidation area and a non-salicidation...

20060148229 - Phase change memory device and method of manufacturing: A method of manufacturing a memory device including forming an electrode over a substrate, then forming a dielectric feature proximate a contact region of a sidewall of the electrode, and then forming a phase change feature proximate the contact region....

20060148230 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device reduces or prevents copper contamination. The method includes forming a gate electrode on a substrate; forming a first oxide layer on a front surface of the substrate including the gate electrode; depositing a nitride layer (simultaneously) on the first oxide layer and a...

20060148231 - Integrated die bumping process: An integrated die bumping process includes providing a load board, defining a plurality of die regions on a surface of the load board for placing dice of a plurality of die specifications, affixing a plurality of dice respectively on the die regions according to the plurality of die specifications, and...

20060148232 - Method for fabricating module of semiconductor chip: A method for fabricating a module of a semiconductor chip is provided. The method includes the steps of: forming a bump on a substrate provided with a pad; forming a protection layer over the bump; performing a grinding process on a rear surface of the substrate to reduce a thickness...

20060148233 - Copper-containing c4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device....

20060148234 - Non-via method of connecting magnetoelectric elements with conductive line: A non-via method of connecting a magnetoelectric element with a conductive line. A magnetoelectric element is formed on a substrate, and spacers are formed on side walls of the magnetoelectric element. A dielectric layer is deposited over the substrate and magnetoelectric element and planarized to a level above the magnetoelectric...

20060148235 - Devices and methods of preventing plasma charging damage in semiconductor devices: Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one predetermined structure; depositing a premetallic dielectric layer and a charge preservation layer on the entire surface of the etching stop layer; depositing...

20060148236 - Semiconductor device with a metal line and method of forming the same: A semiconductor device with a metal line and a method of forming the same. The method includes forming an insulation layer on a semiconductor substrate including a predetermined lower structure, forming a vertical hole and a horizontal hole by etching the insulation layer, forming a supporting part by filling the...

20060148237 - Method for fabricating a semiconductor device: A method of fabricating a semiconductor device wherein the step difference of an insulating layer surface is effectively eliminated to completely planarize a surface of the insulating layer by DHF dipping treatment after completion of the insulating layer planarization....

20060148238 - Metallization method of semiconductor device: A method for forming a metallization contact in a semiconductor device includes (a) forming an insulating layer on a semiconductor substrate including an active device region or a lower metal wire; (b) forming a contact hole to expose a portion of the active device region or lower metal wire by...

20060148239 - Method of manufacturing a semiconductor device: For a semiconductor device having copper wiring, an exemplary method according to an embodiment of the present invention may include forming a first insulation layer on a silicon substrate having a transistor thereon; forming a contact hole by etching the first insulation layer; forming a metal plug so as to...

20060148240 - System and method for filling openings in semiconductor products: Explosive forces are used to fill interconnect material into trenches, via holes and other openings in semiconductor products. The interconnect material may be formed of metal. The metal may be heated prior to the force filling step. The explosive forces may be generated, for example, by igniting mixtures of gases...

20060148242 - Metallization method of semiconductor device: A method for forming a metallization contact in a semiconductor device includes the steps of: (a) forming an insulating layer on a semiconductor substrate including an active device region; (b) forming a contact hole to expose a portion of the active device region by etching a portion of the insulating...

20060148241 - System for and method of forming via holes by use of selective plasma etching in a continuous inline shadow mask deposition process: In a shadow mask vapor deposition system, a first conductor is vapor deposited on a substrate and an insulator is vapor deposited on the first conductor. A second conductor is then vapor deposited on at least the insulator. The insulator layer is plasma etched either before or after the vapor...

20060148243 - Method for fabricating a dual damascene and polymer removal: A method for fabricating a dual damascene includes a partial etching process, a photoresist layer stripping process, and a blanket etching process. After the blanket etching process, an in-situ dry cleaning process is performed to remove residual polymers resulting from the etching processes....

20060148244 - Method for cleaning a semiconductor substrate: A method for cleaning a semiconductor substrate, on which a semiconductor device is formed having a damascene structure using a copper line, that may prevent an abrasion of the substrate by using a simplified cleaning process. The method includes cleaning a surface of the semiconductor substrate having a copper line...

20060148245 - Semiconductor devices and methods of manufacturing the same: Shorting of a copper line with an adjacent line in a semiconductor device during chemical mechanical polishing may be prevented and thus reliability of the semiconductor device may be improved, when the semiconductor device includes a substrate, an interlayer insulating layer formed on the substrate and having a dual trench,...

20060148246 - Method of forming a diffusion barrier layer using a tasin layer and method of forming a metal interconnection line using the same: The present invention provides a method of forming a diffusion barrier layer comprising a TaSiN layer. The method includes depositing a TaN layer into a via hole which penetrates an insulation layer exposing a first metal line layer, and transforming the TaN layer into a TaSiN layer using a radio...

20060148247 - Method of metal sputtering for integrated circuit metal routing: A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more...

20060148248 - Electrode structures and method to form electrode structures that minimize electrode work function variation: Electrode structures, variable resistance memory devices, and methods of making the same, which minimize electrode work function variation. Methods of forming an electrode having a minimized work function variation include methods of eliminating concentric circles of material having different work functions. Exemplary electrodes include electrode structures having concentric circles of...

20060148249 - Method of eliminating boron contamination in annealed wafer: A method by which a silicon wafer is prevented from increasing boron concentration near the surface and difference in the boron concentration does not arise between the surface of the annealed wafer and the silicon bulk to eliminate boron contamination in the silicon wafer caused by an annealing treatment is...

20060148250 - Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit and a terminal electrically coupled to...

20060148251 - Metal etching method for an interconnect structure and metal interconnect structure obtained by such method: A metal interconnects structure, comprises a substrate (11), a dielectric layer (12) lying above the substrate, a stop layer (13) for metal etching lying above the dielectric layer, a metal layer (15′) lying above the stop layer, said metal layer being patterned according to a desired pattern....

20060148252 - Method for producing hydrogenated silicon-oxycarbide films: A method for producing hydrogenated silicon oxycarbide (H:SiOC) films having low dielectric constant. The method comprises using plasma-assisted polymerization to react a cyclic silane compound containing at least one strained silicon bond to produce the films. The resulting films are useful in the formation of semiconductor devices....

20060148253 - Integration of ald tantalum nitride for copper metallization: A method and apparatus for depositing a tantalum nitride barrier layer is provided for use in an integrated processing tool. The tantalum nitride is deposited by atomic layer deposition. The tantalum nitride is removed from the bottom of features in dielectric layers to reveal the conductive material under the deposited...

20060148254 - Activated iridium oxide electrodes and methods for their fabrication: A technique for activating iridium to produce iridium oxide is provided. In a device in which an iridium layer is electrically coupled to a semiconductor junction, a current is generated within the junction and an activation current is applied to the iridium layer via the conductive semiconductor junction. In a...

20060148255 - Method for cuo reduction by using two step nitrogen oxygen and reducing plasma treatment: A method for cleaning a copper interconnect after a chemical-mechanical polishing that comprises: a) treating the surface of said copper interconnect with a nitrogen and oxygen containing treatment; and b) without breaking vacuum, treating the copper interconnect with a NH3 or H2 plasma treatment. Next a cap layer is formed...

20060148256 - Method for forming patterns aligned on either side of a thin film: m

20060148257 - Method of manufacturing a semiconductor device: Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the...

20060148258 - Method of planarizing an inter-metal insulation film: A method for forming a planarized inter-metal insulation film is provided. The method includes applying a CMP process to an insulation film as controlled by a polish-stop layer pattern formed on an underlying metal wiring pattern. A PAE based material may be used to form the polish-stop layer....

20060148259 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention provides performing a CMP process using high selectivity slurry until the hard mask nitride film is exposed so as to reduce the thickness to be removed in a subsequent CMP process, forming an landing...

20060148261 - Methods and apparatus for polishing control: A CMP station can be closed loop controlled by using data obtained by an inline metrology station from a first polished wafer to affect the processing of subsequent polished wafers. The first wafer is polished and measured by the inline metrology station. The metrology station measures at various points the...

20060148260 - Selective polish for fabricating electronic devices: A selective polish for fabricating electronic devices is disclosed. The selective polish may include the use of a slurry that facilitates the selective polish of a first component but does not substantially polish a second component....

20060148262 - Method for fabricating microelectromechanical optical display devices: A Method of forming microelectromechanical optical display devices is provided. A sacrificial layer is formed above a substrate. A plurality of posts penetrating the sacrificial layer is formed. A reflective layer and a flexible layer are sequentially formed above the sacrificial layer and the posts. A photoresist layer is formed...

20060148263 - Dry etching apparatus having particle removing device and method of fabricating phase shift mask using the same: A dry etching apparatus may include a dry etching chamber and a door chamber. The apparatus may further include a load lock chamber configured to connect the dry etching chamber and the door chamber in a vacuum state. A gas injector and an ionizer may be configured inside the door...

20060148264 - Method of fabricating semiconductor device: A method of fabricating a semiconductor device is provided. The method includes forming a low-k dielectric layer on a semiconductor substrate, forming a mask pattern on the low-k dielectric layer, and dry etching the low-k dielectric layer using the mask pattern as an etch mask. A dry etching gas is...

20060148265 - After deposition method of thinning film to reduce pinhole defects: A method of forming a thin film is provided in which a film having a first thickness is deposited over a substrate, wherein the first thickness is greater than a thickness at which the initially deposited film begins to dewet from the substrate. The initially deposited film is then stabilized...

20060148266 - Pattern formation method: In a pattern formation method, a resist film is formed on a substrate and a barrier film including a plasticizer is then formed on the resist film. Thereafter, with a liquid provided on the barrier film, pattern exposure is carried out by selectively irradiating the resist film with exposing light...

20060148267 - Apparatus and method for single-or double-substrate processing: In a method for treating semiconductor substrates, one or two substrates are positioned in a substrate process chamber and subjected to wet etching, cleaning, rinsing and/or drying steps. During cleaning or rinsing a band of megasonic energy is created within the process chamber to create an active rinse or cleaning...

20060148268 - In-situ thin-film deposition method: Provided is an in-situ thin-film deposition method in which a TiSix/Ti layer or TiSix/Ti/TiN layer can be continuously deposited. The method serves to deposit a thin layer as a resistive contact and barrier on a loaded wafer and is performed in a thin-film deposition apparatus including a transfer chamber having...

20060148269 - Semiconductor devices and methods for depositing a dielectric film: Embodiments provide methods and apparatuses for chemical vapor depositing a dielectric film, and various structures, devices, and systems, which incorporate dielectric elements formed from the dielectric film. The method includes heating a chamber, within which a substrate is located, to a temperature sufficient to thermally decompose an oxidizing component. A...

20060148270 - High density plasma and bias rf power process to make stable fsg with less free f and sin with less h to enhance the fsg/sin integration reliability: An embodiment of the invention is a HDP CVD FSG layer and an HDP CVD SIN layer with more stability (e.g., less free F and less free H). A feature is that the FSG and SIN are formed using a HDP CVD process with a high plasma density between 1E12...

20060148271 - Silicon source reagent compositions, and method of making and using same for microelectronic device structure: A CVD Method of forming gate dielectric thin films on a substrate using metalloamide compounds of the formula M(NR1R2)x, wherein M is selected from the group consisting of: Zr, Hf, Y, La, Lanthanide series elements, Ta, Ti, Al; N is nitrogen; each of R1 and R2 is same or different...

20060148272 - Fabrication of light emitting film coated fullerenes and their application for in-vivo light emission: A nanoparticle coated with a semiconducting material and a method for making the same. In one embodiment, the method comprises making a semiconductor coated nanoparticle comprising a layer of at least one semiconducting material covering at least a portion of at least one surface of a nanoparticle, comprising: (A) dispersing...

20060148273 - Method using teos ramp-up during teos/ozone cvd for improved gap-fill: Embodiments of the present invention provide methods, apparatuses, and devices related to chemical vapor deposition of silicon oxide. In one embodiment, a single-step deposition process is used to efficiently form a silicon oxide layer exhibiting high conformality and favorable gap-filling properties. During a pre-deposition gas flow stabilization phase and an...

20060148274 - Device for fabricating a mask by plasma etching a semiconductor substrate: A device for fabricating a mask by plasma etching a semiconductor substrate comprises a semiconductor substrate part of the area whereof is partially covered by a mask for protecting at least one area that must not be etched and for exposing at least one area including a pattern to be...

20060148275 - Method of forming an alignment mark and manufacturing a semiconductor device using the same: Embodiments of the present invention provide, among other things, a method of forming an alignment mark having a stepped structure without an additional process. The alignment mark may be used to prevent formation of a defect source in a semiconductor device....