Semiconductor device manufacturing: process inventions 07/06

20060166379 - Method for manufacturing ferroelectric capacitor: A method for manufacturing a ferroelectric capacitor having a lower electrode, a ferroelectric film, and an upper electrode stacked on one another comprises the steps of performing batch dry-etching thereto, processing and forming the upper electrode, the ferroelectric film, and lower electrode, performing a process for removing reactive products adhered...

20060166378 - Method of producing semiconductor device: A semiconductor device incorporating a capacitor structure that includes a ferroelectric thin film is obtained by forming, on a single crystalline substrate 10 having a surface suited for growing thereon a thin film layer of ferroelectric single crystal having a plane (111), a ferroelectric single crystalline thin film 12′ containing...

20060166382 - Method and apparatus for detecting backside particles during wafer processing: A method and apparatus for detecting backside particles during wafer processing is provided. The method includes holding a wafer with vacuum pressure, detecting the presence of particles on a backside of the wafer while holding the wafer with vacuum pressure, transferring the wafer into a process chamber and performing a...

20060166380 - Method of integration testing for packaged electronic components: A method of integration testing for packaged electronic components is capable of improving a conventional testing for packaged electronic components. In this method, non-tested sides of the packaged electronic components are stuck with a downward exposure onto a testing carrier board so that conductive pins are oriented to test spaces...

20060166381 - Mold cavity identification markings for ic packages: The invention provides small-feature identifying markings for tracing completed IC packages to individual mold cavities. Preferred embodiments of the invention include IC packages and associated methods for forming indicia in a surface of an integrated circuit package in an arrangement indicative of a particular mold cavity. The indicia may be...

20060166383 - Semiconductor substrate having reference semiconductor chip and method of assembling semiconductor chip using the same: A semiconductor substrate having a reference semiconductor chip and a method of assembling semiconductor chips using the same are provided. According to the method, a semiconductor substrate having a plurality of semiconductor chips is provided. An identification mark is made on a reference semiconductor chip among the semiconductor chips. The...

20060166384 - Method for manufacturing industrial products and combination of masks for manufacturing the same: A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product...

20060166385 - Method for measuring peak carrier concentration in ultra-shallow junctions: A method is disclosed for determining peak carrier concentration in ultra shallow junctions of semiconductor samples. A region of the surface of the sample is periodically excited. The effects of the excitation are monitored by a probe beam. Synchronous detection produces in-phase (I) and quadrature (Q) signals. These signals are...

20060166388 - Led package structure and mass production method of making the same: An LED package structure includes a lower substrate, an upper substrate disposed on the lower substrate and having a though hole exposing a portion of the upper surface of the lower substrate; an individual LED unit disposed within the through hole in the upper substrate, a conductive pattern layer disposed...

20060166389 - Method for producing solid-state imaging device, solid-state imaging device, and camera: To provide a method for producing a solid-state imaging device enabling an improvement of a light sensitivity characteristic in a light receiving unit, a solid-state imaging device in which the light sensitivity characteristic is improved, and a camera provided with the solid-state imaging device. A shield film projected around the...

20060166386 - Optical semiconductor device and its manufacturing method: An optical semiconductor device (1) has a semiconductor substrate (2) made of InP, an active layer (7) which is formed in parallel with a top surface (2a) of the semiconductor substrate (2) above the semiconductor substrate (2), an n-type first cladding layer (6) made of InGaAsP which is formed under...

20060166387 - Optical transmission and/or receiving device: The invention relates to an optical transmitting and/or receiving device, having: a semiconductor component with a first contact for connection with a reference voltage and a second contact for applying or leading away a high-frequency electrical signal; an electrically conducting carrier substrate with a first surface and a second surface,...

20060166390 - Optoelectronic substrate and methods of making same: A method of producing an optoelectronic substrate by detaching a thin layer from a semi-conducting nitride substrate and transferring it to an auxiliary substrate to provide at least one semi-conducting nitride layer thereon, metallizing at least a portion of the surface of the auxiliary substrate that includes the transferred nitride...

20060166391 - Method of production of semiconductor light emission device and method of production of light emission apparatus: A method of production of semiconductor light emission devices for forming stripes of two multilayers having different emission wavelengths on a substrate, including the steps of: depositing a first multilayer including an active layer on the substrate; selectively etching the first multilayer to form a plurality of adjoining pairs of...

20060166392 - Semiconductor light emitting device and manufacturing method thereof: The present invention provides a semiconductor light emitting device where a spatial change in an In composition ratio is small within a plane of an active layer and device properties such as efficiency of light emission are excellent, and a manufacturing method thereof. An active layer having an InGaN quantum...

20060166393 - Manufacturing method of a mems structure, a cantilever-type mems structure, and a sealed fluidic channel: A method of manufacturing a MEMS structure including forming a porous layer having a predetermined thickness on the top surface of a substrate over an area where a cavity is to be formed; forming the cavity by etching the substrate below the porous layer; forming a membrane layer on the...

20060166394 - Solar cell structure with solar cells having reverse-bias protection using an implanted current shunt: A solar cell structure includes a solar cell of two or more semiconductor layers in facing contact with each other. The semiconductor layers constitute a semiconductor junction producing a voltage between the semiconductor layers when illuminated. A shunt formed of an altered material extends between and at least partially through...

20060166395 - High-density inter-die interconnect structure: An interconnect architecture for connecting a plurality of closely-spaced electrical elements on a first integrated circuit fabricated structure with operative circuits on a second integrated circuit fabricated structure. In one embodiment, the first integrated circuit fabricated structure comprises a plurality of photo sensors. Conductive interconnect elements on the first integrated...

20060166396 - Organic semiconductor structure, process for producing the same, and organic semiconductor device: There are provided an organic semiconductor structure comprising an organic semiconductor layer, which is large in size and homogeneous and has high charge transfer characteristics, a process for producing the same, and an organic semiconductor device. The organic semiconductor structure has, in at least a part thereof, an organic semiconductor...

20060166400 - Electronic assembly with integrated io and power contacts: In some example embodiments, an integrated circuit, electronic assembly and method provide a current path for supplying power to a processor. As an example, the integrated circuit includes a base having power contacts that extend from an upper surface of base. The integrated circuit further includes a substrate that is...

20060166401 - Hybrid package with non-insertable and insertable conductive features, complementary receptacle, and methods of fabrication therefor: A hybrid electronic circuit package (102, FIG. 1) includes non-insertable conductive features (110) and insertable conductive features (112) at a surface of the package. A hybrid receptacle (120), such as a socket, for example, includes non-insertable contacts (124) and insertable contacts (126), which are positioned in a complementary manner with...

20060166399 - Integrated circuit die connection methods and apparatus: This invention generally relates to methods and apparatus for connecting to an integrated circuit die, in particular where the die includes both analogue/microwave radio frequency (rf) circuitry and digital circuitry. A method of connecting a die having both microwave radio frequency (rf) circuitry and digital circuitry to a substrate of...

20060166398 - Off-grid decoupling of ball grid array (bga) devices and method: A multilayered printed wiring board having a ball grid array (BGA) land pattern in which each land in the pattern is connected to a respective via by a link connector, a method of adapting spacing between selected adjacent via and respective link pairs to receive decoupling capacitor pads, comprising rotating,...

20060166397 - Thermal enhanced package for block mold assembly: A heat spreader (20) is added to a package to enhance thermal and advantageously electrical performance. In manufacture a heat spreader precursor (24) is advantageously placed over a group of dies and secured after bonding (e.g., wire or tape bonding or flip-chip bonding) and before matrix/block mold. For example, a...

20060166402 - Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures: A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the...

20060166403 - Fabrication of advanced silicon-based mems devices: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a...

20060166405 - Manufacturing method of semiconductor device: A method of manufacturing a semiconductor device including a die pad section, a first semiconductor chip having a surface on which a first electrode section is formed, a second semiconductor chip having a surface on which a second electrode section is formed, a support member having a surface, lead terminal...

20060166404 - Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for assembling semiconductor devices: A rerouting element for a semiconductor device includes a substantially planar member that carries at least one contact location, at least one conductive, at least one rerouted bond pad. The contact location is positioned adjacent to a first periphered edge of the substantially planar member and at a location that...

20060166406 - Method of making a semiconductor chip assembly using multiple etch steps to form a pillar after forming a routing line: A method of making a semiconductor chip assembly includes providing a metal base that includes a metal plate and a metal layer, providing a routing line that contacts the metal layer and an etch mask that contacts the metal plate, providing a semiconductor chip that includes a conductive pad, mechanically...

20060166407 - Hermetic packaging: A method of hermetically packaging an electronic device (8), in an enclosure (2) comprising mutually inter-engageable first and second housing members (4, 6), comprising the steps of securing the electronic device (8) to the first housing member (4), engaging the first (4) and second (6) housing members such that an...

20060166408 - Method for encapsulating an electronic component using a foil layer: The invention relates to a method for encapsulating an electronic component, in particular a semiconductor, fixed on a carrier, comprising the processing steps of: a) placing at least one foil layer in a mould, b) placing the carrier in contact with the foil layer with the side remote from the...

20060166410 - Manufacturing method of semiconductor device: Before applying a resist on a first gate insulating film, a thinner is provided on an entire surface including a surface of the first gate insulating film to wash the surface of the first gate insulating film. Specifically, while a semiconductor substrate is being rotated, onto a central part thereof...

20060166412 - Method for manufacturing semiconductor elemental device: The present invention provides a method for manufacturing a semiconductor elemental device comprising an SOI structure in which an SOI layer is laminated, comprising the steps of setting transistor forming regions and a device isolation region to the SOI layer, forming a pad oxide film over the SOI layer and...

20060166409 - Method of preparation of a precursor oligocene: The synthesis of a precursor oligocene, particularly pentacene, is a two-step process. In the fist step the Diels-Alder adduct of the a,b-dihydro-a,b-etheno-oligocene with a 1,1-dialkoxy-cyclopentadiene is formed. In the second step this Diels-Alder adduct is converted into the precursor oligocene, in that first the corresponding keto-compound is formed, which may...

20060166414 - Selective deposition: A method for epitaxially forming a silicon-containing material on a substrate surface utilizes a halogen containing gas as both an etching gas as well as a carrier gas through adjustments of the process chamber temperature and pressure. It is beneficial to utilize HCl as the halogen containing gas because converting...

20060166411 - Semiconductor device and manufacturing method thereof: An object of the invention is to provide a semiconductor device and a display device which can be manufactured with improved material efficiency through a simplified manufacturing process, and a manufacturing method thereof. Another object is to provide a technique capable of forming a pattern such as a wiring included...

20060166413 - Thin film transistor device and method of manufacturing the same: A semiconductor film is formed on a substrate. Subsequently, a resist film is formed on the semiconductor film, and dry etching is performed to the semiconductor film using the resist film as a mask. Due to the dry etching, the edge portion of the semiconductor film protrudes from the resist...

20060166415 - Two-transistor tri-state inverter: A two-transistor tri-state inverter is provided, made from a NMOS dual-gate thin-film transistor (DG-TFT) having a top gate, a back gate, and source/drain regions. A PMOS DG-TFT also has a top gate, a back gate, and S/D regions, and the NMOS first S/D region is connected to a PMOS first...

20060166416 - Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar...

20060166417 - Transistor having high mobility channel and methods: Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is...

20060166418 - Method of fabricating semiconductor device: Provided is a method of fabricating a semiconductor device, the method including: forming an insulating layer on a single crystal substrate; etching the insulating layer in a predetermined pattern to expose the surface of the single crystal substrate; depositing an amorphous material on the insulating layer and the exposed surface...

20060166419 - Method for manufacturing semiconductor device: The method for manufacturing a semiconductor device according to the invention includes forming a thick silicon oxide film uniformly in a trench. Argon ions or the like implanted obliquely into the trench to form an ion implanted damaged region selectively in the portion of the silicon oxide film on the...

20060166420 - Method of manufacturing a semiconductor device: In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel...

20060166421 - Semiconductor device fabrication method: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a conductive layer on the first insulating film; exposing the first insulating film by removing a portion of the conductive layer; forming a second insulating film...

20060166424 - Metal gate transistor cmos process and method for making: A method for forming a semiconductor device (100) includes a semiconductor substrate (102) having a first region (104), forming a gate dielectric (108) over the first region, forming a conductive metal oxide (110) over the gate dielectric, forming an oxidation resistant barrier layer (111) over the conductive metal oxide, and...

20060166427 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device comprises: forming a device isolation, a first conductivity type region, and a second conductivity type region on a semiconductor substrate; depositing a gate insulating film on an entire surface of the semiconductor substrate; forming a first metal film on the gate insulating film;...

20060166426 - Methodology for placement based on circuit function and latchup sensitivity: A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element attributes of elements associated with the at least one functional circuit block. An element density function parameterized from the element attributes...

20060166425 - Novel gate dielectric and metal gate integration: A CMOS device is provided which comprises (a) a substrate (103); (b) a gate dielectric layer (107) disposed on the substrate, the gate dielectric comprising a metal oxide; (c) an NMOS electrode (105) disposed on a first region of said gate dielectric; and (d) a PMOS electrode (115) disposed on...

20060166423 - Removal spacer formation with carbon film: A method of making a CMOS device, and a product made by the process. The process includes applying a layer of a carbon film or carbon-containing compound to a substrate. A section of the carbon is etched with a plasma, e.g., an O2, Ar, N2, or He plasma. Ion-implantation, e.g.,...

20060166422 - Sige nickel barrier structure employed in a cmos device to prevent excess diffusion of nickel used in the silicide material: A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate...

20060166428 - Semiconductor device and method of fabricating the same: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the first insulating film; forming a second insulating film on the first conductive layer in a first processing chamber isolated from...

20060166429 - Vertical replacement-gate junction field-effect transistor: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is...

20060166430 - Conductive memory stack with non-uniform width: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face...

20060166431 - Methods to form electronic devices and methods to form a material over a semiconductive substrate: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure...

20060166432 - Process for oxide cap formation in semiconductor manufacturing: A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are then exposed...

20060166433 - Recessed collar etch for buried strap window formation without poly2: A method for manufacturing a trench capacitor with a reduced resistance in a buried strap window for use in a memory circuit such as a dynamic random access memory circuit may be realized by reducing the number of polysilicon layers that are deposited. The method includes the deposition of a...

20060166434 - Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit: A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first...

20060166436 - Forming integrated circuit devices: Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask layer further overlies a second mask layer overlying a second portion of the semiconductor substrate. The first mask layer overlying the first portion of the...

20060166437 - Isolation regions for semiconductor devices and their formation: A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas of the substrate for future isolation regions of the semiconductor device. Portions of the substrate are removed in the areas for future isolation regions,...

20060166439 - Method for manufacturing electronic non-volatile memory devices integrated in a semiconductor substrate: A method manufactures a non-volatile memory device on a semiconductor substrate that includes a matrix of memory cells and associated circuitry. The method includes: forming a filling dielectric layer on the whole substrate until gates of the cells and a conductive layer of the circuitry are completely covered, removing the...

20060166438 - Method of making a floating gate non-volatile mos semiconductor memory device with improved capacitive coupling and device thus obtained: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode...

20060166441 - Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same: A non-volatile memory device with a non-planar gate insulating layer and a method of fabricating the same are provided. The device includes a tunnel insulating pattern, a charge storage layer, an upper insulating layer and a control gate electrode which are sequentially stacked. A lower insulating pattern, which is covered...

20060166440 - Semiconductor nonvolatile memory device, and manufacturing method thereof: The present invention realizes a semiconductor nonvolatile memory device where a leak current does not easily flow through a tunnel insulating film, and a manufacturing method thereof A silicon nitride oxide film constituting a tunnel insulating film is formed by radically nitriding a surface of a silicon oxide film. The...

20060166435 - Synthesis of ge nanocrystal memory cell and using a block layer to control oxidation kinetics: A structure and a method of manufacturing a memory devices using nanoncrystals. A first embodiment is characterized as follows. We form a first gate insulator over the substrate. The first gate insulator is comprised of an oxide layer and blocking layer. We form a SiGe layer over the first gate...

20060166442 - Method for manufacturing semiconductor device: In a method for manufacturing a semiconductor device, a mask layer is formed on a semiconductor substrate. The mask layer and the substrate are patterned to form a device isolation layer defining an active region. The mask layer and the substrate are patterned in the active region to form a...

20060166443 - Multi-state nrom device: An array of NROM flash memory cells configured to store at least two bits per four F2. Split vertical channels are generated along each side of adjacent pillars. A single control gate is formed over the pillars and in the trench between the pillars. The split channels can be connected...

20060166444 - Mems scanning mirror with trenched surface and i-beam like cross-section for reducing inertia and deformation: A micro-electro-mechanical system (MEMS) device includes a mirror having a top surface with trenches, a beam connected to the mirror, rotational comb teeth connected to the beam, and one or more springs connecting the beam to a bonding pad. The mirror can have a bottom surface for reflecting light. The...

20060166445 - Methods of fabricating multiple sets of field effect transistors: The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate...

20060166446 - Manufacturing method of semiconductor device, semiconductor manufacturing apparatus, plasma nitridation method, computer recording medium, and program: An object of the present invention is to prevent an increase in film thickness and inhibit a reduction in capacity of a capacitor. In a semiconductor device having a capacitor, the capacitor includes a lower electrode, an upper electrode, and an insulating film interposed between the lower electrode and the...

20060166447 - Method for making a semiconductor device having a high-k gate dielectric: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate...

20060166448 - Apparatus for depositing seed layers: One embodiment of the present invention is an apparatus for depositing seed layers over a substrate, said substrate includes at least one opening surrounded by a field, the apparatus includes: (a) a CVD chamber adapted to deposit a CVD seed layer over the substrate; (b) a PVD chamber adapted to...

20060166449 - Nonvolatile memory device for storing multi-bit data: A semiconductor nonvolatile memory device for storing multi-bit data has a memory cell having a source region S and a drain region D formed at the surface of a semiconductor substrate, a gate insulator film and a control gate CG formed on a channel region CH between the source region...

20060166450 - Method for manufacturing substrate: A substrate including an SOI region and a bulk region having an improved flatness is provided. In the process for manufacturing the patterned SOI substrate 100, a concave portion is previously produced by the bulk region 103 in silicon substrate 104. Therefore, the height of the step produced in the...

20060166451 - Process for manufacturing a multilayer structure made from semiconducting materials: The invention relates to a process for manufacturing a multilayer structure made from semiconducting materials that include an active layer, a support layer and an electrically insulating layer between the active layer and the support layer. The process includes the step of modifying the density of carrier traps or the...

20060166452 - Non-volatile nanocrystal memory and method therefor: A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals...

20060166453 - Method and apparatus for forming patterned photosensitive material layer: A method for forming a patterned photosensitive material layer over a substrate is described. A photosensitive material layer is formed on a substrate and then exposed. The selected parameters of the photosensitive material layer or between the photosensitive material layer and the predetermined layer are measured for determining whether the...

20060166454 - Low tolerance polysilicon resistor for low temperature silicide processing: Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation....

20060166455 - Multilevel programming of phase change memory cells: A method for programming a phase change memory cell is disclosed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase...

20060166456 - Semiconductor device and manufacturing method thereof: A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area...

20060166457 - Method of making transistors and non-silicided polysilicon resistors for mixed signal circuits: A method for manufacturing a semiconductor wafer 10 that includes implanting source/drain regions 75 within a top surface of the semiconductor substrate 20, forming a dielectric capping layer 170 over the semiconductor wafer 20, and annealing the semiconductor wafer 10 to activate sources/drains 70. The method further includes forming a...

20060166458 - Method for forming shallow trench isolation structures: A shallow trench isolation (STI) structure for semiconductor devices is formed using a deposited silicon layer formed over a polish stop layer formed over an oxide formed on a substrate. The polish stop layer may be nitride. An opening is formed extending through the deposited silicon layer and the nitride...

20060166459 - Semiconductor apparatus and method of producing the same: the inner wall oxidizing step being performed by wet oxidization with a low concentration of moisture mixed in oxygen to form the oxide film so that a stress caused between the oxide film and the silicon substrate is not greater than 3.5×109 (dyne/cm2) and a radius at a corner of...

20060166460 - Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process...

20060166461 - Method of producing mixed substrates and structure thus obtained: The inventive method includes a preparation step during which the substrate is covered with a layer, a pressing step in which a mould including a pattern of recesses and protrusions is pressed into part of the thickness of the aforementioned layer, at least one etching step in which the layer...

20060166462 - Method for manufacturing semiconductor wafer: A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first...

20060166463 - Method of producing a device with a movable portion: A method of producing a device with a movable portion spaced apart from a support wafer comprises a step of providing the support wafer having a structured surface and a further step of providing a device wafer with a backing layer and a device layer disposed thereon. Further, the method...

20060166464 - Method and device for machining a wafer, in addition to a wafer comprising a separation layer and a support layer: A process and an apparatus are described for the treatment of wafers, in particular for the thinning of wafers. A wafer with a carrier layer and an interlayer arranged between the carrier layer and the wafer is also described, in which the interlayer is a plasmapolymeric layer that adheres to...

20060166465 - Method of dividing wafer: To eliminate necessity of separation of a resist film in dicing by etching and thus improve productivity and die strength of a device, thickness of the resist film is adjusted such that when street-correspondent-areas are separated by etching, resist films coated on portions other than the street-correspondent-areas are not remained....

20060166466 - Semiconductor manufacturing method of die-pick-up from wafer: A manufacturing method of a semiconductor device comprising the steps of: affixing a die attach film and a dicing film to a back surface of a semiconductor wafer: thereafter dicing the semiconductor wafer and the die attach film to divide the semiconductor wafer into a plurality of semiconductor chips: thereafter...

20060166467 - Method of producing microcrystalline silicon germanium suitable for micromachining: A method of depositing a structural SiGe layer is presented. The structural SiGe layer may be located on top of a sacrificial layer above a substrate. The substrate may contain a semiconductor device such as a CMOS electronic circuit. The presented method uses a silicon source and a germanium source...

20060166468 - Semiconductor substrate, semiconductor device, light emitting diode and producing method therefor: A semiconductor substrate including a gallium arsenide layer is obtained by executing a step of preparing a first substrate having a separating layer constituted of germanium and a gallium arsenide layer on the separating layer, a step of preparing a bonded substrate by bonding the first substrate and a second...

20060166470 - Method of irradiating a laser beam, apparatus for irradiating a laser beam and method of fabricating semiconductor devices: When a CW laser is irradiated to a semiconductor film while scanning relatively during a production process of a semiconductor device, elongated crystalline particles extending in the scanning direction are formed. The semiconductor film thus formed has characteristics substantially equal to a single crystal in the scanning direction. However, since...

20060166469 - Method of laser beam maching and laser beam machining apparatus: An object of the invention is to credibly crystallize an amorphous material for use as a semiconductor material and effect crystallization to a region of desired scope. A first region drawn on a surface of a layer of amorphous material formed on the surface layer of sample (21) is irradiated...

20060166471 - Memory apparatus and production method: The memory apparatus according to the invention and having a cell 14 has a high electrical resistance in a first state and a low electrical resistance in a second state. The cell 14 has an edge area 16 and a core area 15, in which the electrical resistivity in the...

20060166472 - Cleaving process to fabricate multilayered substrates using low implantation doses: A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave...

20060166473 - Method of forming schottky diode with charge balance structure: a Schottky diode having a semiconductor region is formed as follows. A plurality of charge control electrodes are formed in the semiconductor region so as to influence an electric field in the semiconductor region, wherein at least two of the charge control electrodes are adapted to be biased differently from...

20060166474 - Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow: A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt...

20060166475 - Method for the production of stree-relaxed layer structure on a non-lattice adapted substrate and utilization of said layer system in electronic and/or optoelectronic components: The invention relates to a method for the production of a monocrystalline, stress-relaxed layer structure having one or several layers on a substrate with different grid structure. In a special embodiment, the method can be advantageously used for the production of relaxed silicon on a stress-related Si—Ge layer structure. The...

20060166476 - Method of forming a dielectric structure having a high dielectric constant and method of manufacturing a semiconductor device having the dielectric structure: In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference...

20060166477 - Wafer level electro-optical semiconductor manufacture fabrication mechanism and a method for the same: A wafer-level electro-optical semiconductor fabrication mechanism and method for the same which improves upon traditional electro-optical semiconductor grain packaging methods. The present invention electrically connects semiconductor grains to the grains on a top surface of a wafer. this is done by either screen-printing or steel board-printing solder or silver paste...

20060166478 - Nitride semiconductor device and its manufacturing method: A method for fabricating nitride semiconductor devices according to the present invention includes the steps of: (A) providing a nitride semiconductor substrate, which will be split into chip substrates, which includes device portions that will function as the respective chip substrates when the substrate is split and interdevice portions that...

20060166479 - Interconnection device for a printed circuit board, a method of manufacturing the same, and an interconnection assembly having the same: The present invention relates to an interconnect device for a printed circuit board, a method of manufacturing the same and an inter-connect assembly having the same. According to one aspect of the present invention, the interconnect device for a printed circuit board comprises: a first contact section 10 having a...

20060166480 - Interconnection of through-wafer vias using bridge structures: Bridge structures provide a surface on which to form interconnections to components through through-hole vias. The bridge structures at least partially, and preferably fully, span the gap between two wafers, and, more specifically, between a through-hole via in one wafer and a corresponding component on the other wafer. Bridge structure...

20060166481 - Method of forming metal layer pattern and method of manufacturing image sensor using the same: A method of forming a metal layer pattern comprises forming an interlayer insulating layer on a semiconductor substrate, forming a metal layer on the interlayer insulating layer, forming a mask pattern to expose a predetermined area of the metal layer, and forming a metal layer pattern by dry etching the...

20060166482 - Semiconductor device manufacturing device: A process for production of a semiconductor device having a multi-layer wiring of dual damascene structure in a low-dielectric constant interlayer insulating film. The process consists of the following steps. A first insulating film (6) and a second insulating film (7) are formed. A first to third mask forming layers...

20060166484 - Method for cu metallization of highly reliable dual damascene structures: The present invention provides a method for forming a void-free copper damascene structure comprising a substrate having a conductive structure, a first dielectric layer on the substrate, a diffusion barrier layer on the first dielectric layer, and a second dielectric layer on the barrier layer. The method comprises forming via...

20060166486 - Method of forming a semiconductor device having air gaps and the structure so formed: A method of forming a semiconductor device. Depositing alternating layers of a first and a second dielectric material, wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material...

20060166483 - Method of manufacturing a semiconductor device and semiconductor device obtained by using such a method: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) and a substrate (2) comprising at least one semiconductor element (3) and provided with at least one connection region (4) and an overlying stripe-shaped connection conductor (5) which is connected to the connection...

20060166485 - Methods for making dual-damascene dielectric structures: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In...

20060166487 - Method and apparatus for chemical mechanical polishing of semiconductor substrates: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a...

20060166488 - Semiconductor device and method for manufacturing the same: An object of the present invention is to improve the inter-layer adhesiveness of the diffusion barrier film while maintaining the lower dielectric constant of the diffusion barrier film. A diffusion barrier film for a copper interconnect comprises an insulating material containing silicon, carbon, hydrogen and nitrogen as constituent elements, and...

20060166490 - Forming buried via hole substrates: A preformed copper plug may be inserted into a via hole in a package substrate. The opposed surfaces of the copper preform may be covered with a solder material. Copper foils may then be applied over the core and over the preformed plug. A vacuum hot press method may be...

20060166489 - Semiconductor constructions: The invention includes methods of forming openings extending through electrically insulative layers to electrically conductive materials. In an exemplary aspect, a substrate is provided which supports a stack and an electrical node. The stack comprises an electrically insulative cap over an electrically conductive material. An electrically insulative layer is formed...

20060166491 - Dual damascene interconnection having low k layer and cap layer formed in a common pecvd process: A method of fabricating dual damascene interconnections begins by forming on a substrate a dielectric layer by a PECVD process that employs a first precursor gas. A capping layer is formed on the dielectric layer by a PECVD process that also employs the first precursor gas such that deposition of...

20060166493 - Semiconductor device having nitridated oxide layer and method therefor: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to...

20060166492 - Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration: A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably...

20060166494 - Method of manufacturing a semiconductor device that includes a contact plug: A method of manufacturing a semiconductor device including a contact plug includes forming an insulation interlayer pattern and a protection pattern for protecting the insulation interlayer pattern using a mask pattern. The insulation interlayer includes a contact hole through which a surface of the substrate is partially exposed. A spacer...

20060166495 - Contact structure formed using supercritical cleaning fluid and alcvd: A supercritical fluid such as CO2 cleans an opening formed in a Si-containing dielectric material and removes polymeric and organic residue produced by the etching process used to form the opening. The opening may be a contact, via or other opening and may include a cross-sectional area of less than...

20060166496 - Incorporating dopants to enhance the dielectric properties of metal silicates: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a...

20060166497 - Method of fabricating conductive lines: A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and...

20060166498 - Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same: A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than the second opening. A first conductive material is formed over the semiconductor wafer to...

20060166499 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures...

20060166500 - Electroprocessing profile control: A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a first electroprocessing zone between the electrode and the substrate, and biasing a second electrode disposed radially outward of substrate with...

20060166501 - Method and apparatus for monolayer deposition: An adaptive real time thermal processing system is presented that includes a multivariable controller. The method includes creating a dynamic model of the MLD processing system and incorporating virtual sensors in the dynamic model. The method includes using process recipes comprising intelligent set points, dynamic models, and/or virtual sensors....

20060166502 - Semiconductor constructions: The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and a peripheral region proximate the memory array region. The memory array region has a higher average elevational height than the peripheral region. Polysilazane is formed...

20060166503 - Polishing apparatus and polishing method: A polishing apparatus has a polishing section (302) configured to polish a substrate and a measurement section (307) configured to measure a thickness of a film formed on the substrate. The polishing apparatus also has an interface (310) configured to input a desired thickness of a film formed on a...

20060166504 - Profiled standoff structure and method for optical display package: A method for forming a standoff structure for devices, e.g., optical devices, integrated circuit devices, micro-electrical mechanical systems (i.e., MEMS). The method includes providing a substrate (e.g., silicon wafer), which has a first surface region characterized by a <100> crystal orientation, a second surface region, and a thickness defined between...

20060166505 - Integrated process for thin film resistors with silicides: The formation of devices in semiconductor material. In one embodiment, a method of forming a semiconductor device is provided. The method comprises forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of...

20060166506 - Mask material for reactive ion etching, mask and dry etching method: To provide a dry etching method and the like that can precisely process regions targeted for etching of objects to be processed using reactive ion etching that uses carbon monoxide gas, to which a nitrogen-containing compound gas is added, as a reactive gas. A material containing silicon and tantalum is...

20060166507 - Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean: Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to a plasma containing the same dopant species as in the semiconductor material so as to partially, completely, or...

20060166508 - Topography transfer method with aspect ratio scaling: The present invention is a method of applying a topographical surface to a part such as a substrate without the need for low temperature softening of that part while retaining high aspect ratios and densely packed features in that topography. A substrate, selected for its ability to be processed at...

20060166509 - Method to avoid alpha-si damage during wet stripping processes in the manufacture of mems devices: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of...

20060166510 - Semiconductor manufacturing method for die bonding: The present invention has a pump system having a gear pump to which a gear structure, having a pump gear and a driving gear concentrically and integrally formed with each other, is incorporated; a main control section for controlling this pump system; and a stage that can support a plate-like...

20060166511 - Method for treatment of film or sheet: A film or sheet containing an optionally crosslinked organic polymer having a high degree of crosslinking and having a little amount of residual solvent is obtained within a short period of time under a low pressure by bringing a film or sheet containing an organic polymer into contact with a...

20060166512 - Methods of forming a thin film and methods of manufacturing a capacitor and a gate structure using the same: wherein M represents a metal in listed in Group 4A of the periodic table of elements, R1, R2 and R3 independently represent hydrogen or an alkyl group having a carbon number from 1 to 5, and X represents hydrogen or an alkyl group having a carbon number from 1 to...

20060166513 - Method and apparatus for forming thin film of semiconductor device: A method of forming a high quality thin film on a semiconductor substrate includes supplying a first gas to change a crystal structure of a semiconductor substrate, and a second gas to form a thin film on the semiconductor substrate; sputtering the first gas in a plasma state to the...

20060166515 - In-situ-etch-assisted hdp deposition: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of...

20060166514 - Teos deposition method: A TEOS deposition method. A mixture of gases is introduced into a process chamber, in which the mixture of gases comprises tetra-ethyl-ortho-silicate (TEOS) and N2. Compressive stress of a TEOS oxide film is increased by activating the mixture of gases....

20060166516 - Nitride film forming method, semiconductor device fabrication method, capacitor fabrication method and nitride film forming apparatus: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of...

20060166517 - Phase-shifting mask and semiconductor device: Disclosed is a phase-shifting mask having a pattern comprising a plurality of substantially transparent regions and a plurality of substantially opaque regions wherein the mask pattern phase-shifts at least a portion of incident radiation and wherein the phases are substantially equally spaced, thereby increasing resolution of a given lithographic system....

20060166518 - Subtractive-additive edge defined lithography: A subtractive-additive, differential lithography technique capable of generating sub-half micron geometries using a larger feature parent mask is described. The basic technique is defect tolerant with respect to electrical shorting, can fabricate T-shaped conductors of optimum geometry to minimize electrical RC time constant, and can be extended to very small,...

20060160249 - Method for fabricating biochips or biosensors using cd/dvd making compatible processes: A method of manufacturing a plastic biochip or a biosensor test strip, which is compatible with standard CD/DVD making processes. The method includes substrate injection press molding, followed by seamless magnetic biosensor sputtering. If necessary, the sputtered biosensor is cut off from the substrate....

20060160250 - Modular fabrication systems and methods: The present invention relates to an article fabrication system having a plurality of material deposition tools containing one or more materials useful in fabricating the article, and a material deposition device having a tool interface for receiving one of the material deposition tools. A system controller is operably connected to...

20060160248 - N-glycoside type glycolipids and hollow fiber type organic nanotubes made of the same: (In the formula, G represents a saccharide radical other than a hemiacetal hydroxyl group bonded to the anomer carbon atom of the saccharide, and R represents an unsaturated hydrocarbon group containing ten to 39 carbon atoms.) This molecule self-aggregates and forms hollow fiber shaped organic nanotubes in water when this...

20060160247 - Unsaturated carboxylic acid hemicacetal ester, polymeric compound and photoresist resin composition: wherein Ra is a hydrogen atom, a halogen atom, an alkyl group of carbon number 1 to 6 or a haloalkyl group of carbon number 1 to 6, Rb is a hydrocarbon group having a hydrogen atom at a first poison, Rc is a hydrogen atom or a hydrocarbon group...

20060160251 - Method in the fabrication of a memory device: In a method for fabricating a memory device based on an electrically polarizable memory material in the form of an electret or ferroelectric material, the memory device comprises one or more layers with circuit structures provided exclusively or partially in a printing process. At least one protective interlayer is provided...

20060160252 - Methods for fabricating ferroelectric memory devices with improved ferroelectric properties: Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one...

20060160253 - Method and apparatus for wafer temperature regulation: A method and apparatus for regulating the temperature a wafer is provided. The apparatus may include a temperature controlling unit provided within the chamber and regulating the temperature of the wafer; a wafer support pin for adjusting the position of the wafer with respect to the temperature controlling unit; and/or...

20060160255 - Driving circuit for amoled display and driving method thereof: A driving circuit and method for an active matrix organic light emitting diode (AMOLED) display are provided. The driving circuit comprises a power circuit, a linear thermistor, and a pixel circuit. The power circuit provides an equivalent current. The linear thermistor coupled to the power circuit adjusts the equivalent current...

20060160256 - Method of inspecting substrate processing apparatus, and storage medium storing inspection program for executing the method: A method of inspecting a substrate processing apparatus that enables a reduction in operator labor time to be achieved. A host computer instructs a substrate processing apparatus to prohibit transfer of a product wafer into the substrate processing apparatus during a period of cleaning the substrate processing apparatus. The substrate...

20060160254 - System and method for detection of spatial signature yield loss: A method and system are provided for identifying systematic yield losses. The method comprising testing produced products using a test sequence, the testing sequence producing yield data, the yield data related to a wafer. For each zone of each wafer size calculating and storing a first data series R1, wherein...

20060160258 - Process for producing microelectromechanical components and a housed microelectromechanical component: A process produces microelectromechanical components from a substrate that has a first side and a second side which is substantially opposite from the first side, and at least the first side has at least one microelectromechanical element. The process includes the step of providing at least one conductive passage into...

20060160257 - White-light emitting devices and methods for manufacturing the same: White-light emitting devices and methods for manufacturing the same. The white-light emitting device emits white light comprising a first color component with first wavelength, a second color component with a second wavelength, and a third color component with a third wavelength. The first wavelength is shorter than the second wavelength....

20060160259 - Sealant region pattern for liquid crystal display and method for fabricating the same: A sealant region pattern for a liquid crystal display apparatus and a method for fabricating the same. The method comprises providing a first substrate and a second substrate opposite thereto, forming a predetermined material layer on the first substrate, forming an organic material pattern layer having openings of a saw...

20060160260 - Thin film transistor array panel and method of manufacturing the same: The present invention provides a method of manufacturing a TFT array panel in a cost-effective manner. The method includes: forming thin film transistors each having a gate electrode, a source electrode, and a drain electrode; forming an insulating layer on the thin film transistors; forming a first conductive layer electrically...

20060160261 - Series interconnected optoelectronic device module assembly: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One...

20060160262 - Microelectromechanical devices and their fabrication: A method of fabricating microelectromechanical (MEMs) systems and in particular for producing silicon carbide (SiC) MEMs devices with improved mechanical properties. The method comprises reacting a dry etch plasma with a layered microstructure; the layered microstructure having an etch mask, a sacrificial layer and a device layer arranged between the...

20060160263 - Method for manufacturing pressure sensor: A method for manufacturing a pressure sensor includes the steps of: preparing a semiconductor substrate; forming an insulation film on the substrate; forming a first metal film on the insulation film; forming a first protection film on the first metal film and the insulation film; forming a second protection film...

20060160264 - Methods and apparatus having wafer level chip scale package for sensing elements: Methods are provided for manufacturing a sensor. The method comprises depositing a sacrificial material at a first predetermined thickness onto a wafer having at least one sense element mounted thereon, the sacrificial material deposited at least partially onto the at least one sense element, forming an encapsulating layer at a...

20060160265 - Method of manufacturing photoelectric conversion element, photoelectric conversion element, and electronic apparatus: A method of manufacturing a photoelectric conversion element, in which a first carrier transport layer, a dye layer, and a second carrier transport layer are interposed between an anode and a cathode, includes forming the first carrier transport layer, forming the dye layer so as to come into contact with...

20060160266 - Organic electronic component and method for producing organic electronic devices: The invention relates to an organic electronic component and a process for low-cost and large-scale production of organic electronics, wherein roll-to-roll compatible coating techniques are used in conjunction with printing processes....

20060160268 - Exposure equipment and control method of the same: A controller controls a wafer carrier to move from a SMIF-POD to transfer and collect a wafer between a space of a transfer unit through a thermal chamber. The wafer carrier is returned into the SMIF-POD, when the wafer is exposed, to be kept waiting in the SMIF-POD until the...

20060160269 - Method and apparatus for avoiding dicing chip-outs in integrated circuit die: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the...

20060160267 - Under bump metallurgy in integrated circuits: An integrated circuit package and method of manufacture is provided. A substrate having a number of contact pads exposed through a passivation layer thereon has a first under bump metallurgy layer over at least one of the contact pads. A top under bump metallurgy layer of copper having a thickness...

20060160270 - Method for producing an anisotropic conductive film on a substrate: This invention relates to a process for manufacturing an anisotropic conducting film comprising a layer of electrically insulating material and conducting through inserts, the said process comprising the following steps: a) formation on a substrate of at least one layer of material with through holes, the said layer being called...

20060160271 - Stacked semiconductor module: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable...

20060160272 - Synthesis method for a compound used to form a self-assembled monolayer, compound for forming a self-assembled monolayer, and layer structure for a semiconductor component: A synthesis method of a compound used to form a self-assembled monolayer used in a semiconductor component is provided. A method includes a first step of replacing a terminal halogen of an ω-haloalk-1-ene with a compound having at least one aromatic group, and a second step of hydrosilylating the reaction...

20060160273 - Method for wafer level packaging: A device wafer including a plurality of devices and a plurality of contact pads positioned on a top surface of the device wafer and electrically connected to the devices is provided. Subsequently, a cap wafer is provided. Following that, a plurality of bonding patterns and a plurality of cavity patterns...

20060160274 - Methods relating to forming interconnects: Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component substrate, such as a semiconductor die or other substrate, has dielectric material disposed on a surface thereof, surrounding but not covering interconnect elements, such as bond pads, on...

20060160275 - Device and method for encapsulating with encapsulating material and electronic component fixed on a carrier: The invention relates to a device for encapsulating with encapsulating material an electronic component, in particular a semiconductor, fixed on a carrier, comprising: two co-acting mould parts which are displaceable relative to each other between an encapsulating position, in which the mould parts, when closing onto the carrier, occupy a...

20060160277 - Active layer island: A method for forming an electronic device including at least one electrically conductive and one semiconductive material deposited from solution, the method comprising: forming on the substrate a confinement structure consisting of a least a first zone and a second zone, depositing the electrically conductive material on the substrate, wherein...

20060160276 - Electronic devices: A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and...

20060160281 - Method of fabricating a thin film transistor: A method of fabricating a thin film transistor is disclosed. The method comprises forming an amorphous silicon layer overlying a substrate. A first heat treatment is then performed to reduce the hydrogen atom concentration of the amorphous silicon layer. Next, the amorphous silicon layer is patterned to form an island-shaped...

20060160279 - Optical mask and manufacturing method of thin film transistor array panel using the optical mask: A photo mask is provided. The mask includes: a transmitting area and a translucent area, wherein the translucent area includes a plurality of light blocking portions blocking light, and wherein the light blocking portions have a plurality of areas blocking different amounts of light. By using this type of photo...

20060160278 - Thin film device active matrix by pattern reversal process: This invention provides a method of fabricating an active matrix of thin film devices through a pattern reversal self aligned imprint lithography (SAIL) process. The method includes providing a substrate and depositing at least one layer of material upon the substrate. A pattern is then established upon the layer of...

20060160282 - Thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel is provided, The method includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming a data line and a drain electrode on the...

20060160280 - Thin film transistor, a method for preparing the same and a flat panel display employing the same: Provided are a thin film transistor, a method for preparing the same and a flat panel display employing the same. The thin film transistor includes a gate electrode, source and drain electrodes insulated from the gate electrode, a semiconductor layer insulated from the gate electrode and electrically connected to the...

20060160283 - Method of fabricating a liquid crystal display device: A method of fabricating a liquid crystal display device comprises the following steps. A first N-type LDD (Lightly Doped Drain) and a second N-type LDD are formed in a semiconductor layer by tilted ion implantation with a gate electrode serving as a mask. The two N-type LDDs are adjacent to...

20060160284 - Switching device for a pixel electrode and methods for fabricating the same: The invention discloses a switching device for a pixel electrode of display device and methods for fabricating the same. A gate is formed on a portion of a substrate. A semiconductor layer is formed on the gate. A source and a drain are formed on a portion of the semiconductor...

20060160286 - Memory device and method for fabricating the same: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being...

20060160285 - Semiconductor device having mosfet with offset-spacer, and manufacturing method thereof: A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first offset-spacer which is formed in contact with one side surface of the gate electrode, a first spacer which...

20060160287 - Method of fabricating semiconductor device: There has been a problem of damaging a diffusion layer 4 occasionally in etching of a nitride film 5 in a wide gate pitch P1 region. First, a plurality of diffusion layers 4, gates 2 and sidewalls 3 are formed on a silicon substrate 1, so as to be adjacent...

20060160288 - Micro-feature fill process and apparatus using hexachlorodisilane or other chlorine-containing silicon precursor: A method is provided for depositing a silicon-containing film in a micro-feature on a substrate by a low pressure deposition process in a processing system. A silicon-containing film can be formed in a micro-feature by providing a substrate in a process chamber of a processing system, and exposing a hexachlorodisilane...

20060160289 - Semiconductor device and method of manufacturing the same: A semiconductor device is proposed which includes: a semiconductor substrate of a first conductivity type; a channel region formed at a surface of the semiconductor substrate; source and drain regions of a second conductivity type formed at both sides of the channel region in the semiconductor substrate; an insulating layer...

20060160293 - Cell structure of eprom device and method for fabricating the same: Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes...

20060160291 - Integration of biaxial tensile strained nmos and uniaxial compressive strained pmos on the same wafer: A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a...

20060160290 - Method to fabricate variable work function gates for fusi devices: An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si...

20060160292 - Nfet and pfet devices and methods of fabricating same: A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on...

20060160295 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the...

20060160294 - Soi device with body contact self-aligned to gate: A region of a semiconductor wafer is converted to an SOI structure by etching a set of isolation trenches for each transistor active area and oxidizing the sidewalls of the trenches to a depth that leaves a pillar of semiconductor that forms a body contact extending from the active area...

20060160296 - Methods of forming cmos constructions: The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has...

20060160297 - Semiconductor integrated circuit device and process for manufacturing the same: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of...

20060160298 - Self-aligned, silicided, trench-based, dram/edram processes with improved retention: A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond...

20060160299 - Single mask mim capacitor and resistor with in trench copper drift barrier: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion...

20060160300 - Storage capacitor and method of manufacturing a storage capacitor: A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor....

20060160301 - Method for fabricating a metal-insulator-metal capacitor: Disclosed are: (i) a method for fabricating a MIM capacitor in a semiconductor device, which can produce a MIM capacitor in fewer process steps; and (ii) a semiconductor device in which a MIM capacitor having a larger capacitance relative to conventional approaches is formed. The method comprises the steps of:...

20060160302 - Method of fabricating a fin field effect transistor having a plurality of protruding channels: In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate having an active region pattern, forming...

20060160303 - Method for forming high-k charge storage device: Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking...

20060160304 - Non-volatile memory resistor cell with nanotip electrode: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between...

20060160305 - Pillar cell flash memory technology: An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon...

20060160306 - Method for forming trench gate dielectric layer: A method for forming a trench gate dielectric layer is described. First, a substrate having a trench therein is provided. An in-situ steam generated oxidation process is performed to form a sacrificial layer on the surface of the trench. Then, the sacrificial layer is removed. Next, a low-pressure chemical vapor...

20060160307 -