Semiconductor device manufacturing: process inventions 06/06

20060141640 - Mtj elements with high spin polarization layers configured for spin-transfer switching and spintronics devices using the magnetic elements: A method and system for providing a magnetic element are disclosed. The method and system include providing first and second pinned layers, a free layer, and first and second barrier layers between the first and second pinned layers, respectively, and the free layer. The first barrier layer is preferably crystalline...

20060141641 - Repair and restoration of damaged dielectric materials and films: Methods of repairing voids in a material are described herein that include: a) providing a material having a plurality of reactive silanol groups; b) providing at least one reactive surface modification agent; and c) chemically capping at least some of the plurality of reactive silanol groups with the at least...

20060141642 - Method for making mask in process of fabricating semiconductor device: A method for making a mask in a process of fabricating a semiconductor device is disclosed, in which one database is classified into an SRAM block and a random logic block so that OPC is separately performed for the SRAM block and the random logic block, thereby improving performance of...

20060141645 - Light emitting device and manufacturing method thereof: The concentration of oxygen, which causes problems such as decreases in brightness and dark spots through degradation of electrode materials, is lowered in an organic light emitting element having a layer made from an organic compound between a cathode and an anode, and in a light emitting device structured using...

20060141644 - Light emitting diode and fabricating method thereof: A method for fabricating a light emitting diode (LED) is provided. Successively forming a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer on an epitaxy substrate; forming a bonding layer thereon; bonding a transferring substrate with the bonding layer; removing the epitaxy...

20060141643 - Manufacturing method of pixel structure of thin film transistor liquid crystal display: A method of fabricating a pixel structure of TFT LCD is provided. First, a gate pattern, pixel electrode pattern, gate isolating layer and semiconductor layer are formed over the substrate sequentially. Then, a patterning process is performed to remove the first metal layer over the pixel electrode pattern, wherein the...

20060141646 - Organic electroluminescent device and method of manufacturing the same: The invention provides an organic electroluminescent device and a method of manufacturing the same which conveniently reduce or suppress the transfer of ionic impurities into a light-emitting layer, and reduce or prevent the light-emitting property in the light-emitting layer from degrading, which promotes life extension. An organic electroluminescent device includes...

20060141647 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor forms silicon nitride (SiN) layer on a pad. Microlenses, having a minimum height and footprint according to a desired packing density of the lenses, are fabricated of an oxide film and a nitride film deposited on the silicon nitride. Since the lenses...

20060141648 - Light emitting device methods: Light-emitting device methods are disclosed....

20060141649 - Method of reducing insertion loss in a transition region between a plurality of input or output waveguides to a free space coupler region: A method for reducing insertion loss in a transition region between a plurality of input or output waveguides to a free space coupler region in a photonic integrated circuit (PIC) includes the steps of forming a passivation layer over the waveguides and region and forming the passivation overlayer such that...

20060141650 - Mems device package and method for manufacturing the same: A micro electromechanical system (MEMS) device package and a method of manufacturing the same are provided. The inventive MEMS device package includes: a device substrate with a MEMS active device being formed on the top surface thereof; internal electrode pads, each of which is positioned on the opposite side of...

20060141651 - Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation: A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure,...

20060141657 - Field emission device and manufacturing method thereof: It is an object to provide techniques for forming a field emission device of a field emission display device with the use of an inexpensive large-sized substrate according to the process that enables improving productivity. A field emission device according to the present invention includes a cathode electrode formed on...

20060141652 - Mems device package and method for manufacturing the same: A micro electromechanical system (MEMS) device package and a method of manufacturing the same are provided. The MEMS device package includes: a device substrate with a MEMS active device being formed on the top surface thereof; internal electrode pads, each of which is positioned on the opposite side of the...

20060141654 - Method for fabricating a cmos image sensor: A method for fabricating a CMOS image sensor in which an electron shower is performed for microlenses whose surfaces are charged to a positive potential, so as to neutralize the positive potential, thereby improving performance and yield of the image sensor....

20060141653 - Methods of manufacturing an image device: In methods of manufacturing an image device, a first structure including a transparent lower portion and an opaque upper portion is formed on a substrate having a photodiode. An etch stop layer pattern positioned over the photodiode is formed on the first structure. A second structure having at least one...

20060141656 - Micromechanical sensors and methods of manufacturing same: A micromechanical sensor and, in particular, a silicon microphone, includes a movable membrane and a counter element in which perforation openings are formed, opposite to the movable membrane via a cavity. The perforation openings are formed by slots, the width of which maximally corresponds to double the spacing defined by...

20060141655 - Photoelectric conversion device, its manufacturing method, and image pickup device: It is an object of the present invention to provide a manufacturing method of a photoelectric conversion device in which no plane channeling is produced even if ions are injected at a certain elevation angle into a semiconductor substrate surface made of silicon. A manufacturing method of a photoelectric conversion...

20060141658 - Corrugated diaphragm: A diaphragm includes a substrate having a hole and a sheet of material formed on the substrate and covering the hole. The sheet of material includes one or more corrugations that are substantially free of defects. A method of forming the diaphragm includes forming a corrugated surface free of stringers...

20060141659 - Single-crystal-silicon 3d micromirror: In a 3D free space micromirror device, a mirror plate is joined with actuators through flexible springs where the other ends of the actuators have fixed support on the substrate. Single crystal silicon and aluminum are used as bi-morph materials with silicon dioxide providing electrical isolation between the two. Thickness...

20060141660 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same prevent a lifting phenomenon of a microlens. The CMOS image sensor includes a semiconductor substrate structure in which at least one photodiode is disposed, an insulating interlayer formed on the semiconductor substrate structure, a patterned metal layer formed on...

20060141661 - Cmos image sensor and method of fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. The image sensor includes a blocking layer protecting a photodiode at a diode region. The blocking layer is formed to cover a top of the diode region and extended to an active region so as to cover...

20060141662 - Photovoltaic component and production method therefor: The invention relates to an organic component comprising an improved top electrode and to a production method therefor. The top electrode is made of an organic material that is applied by means of printing techniques....

20060141663 - Method for forming metal interconnection of semiconductor device: A method for forming a metal interconnection of a semiconductor device avoids over-etching and under-etching through the use of the “self-stop” function of a nitridation layer, to prevent the occurrence of openings and voids in a copper interconnection and to obtain a constant trench depth. The method includes forming nitride...

20060141664 - Semiconductor devices having regions of induced high and low conductivity, and methods of making the same: Semiconductor apparatus comprising: a substrate having a substrate surface; a layer of a first material overlying a first region of the substrate surface; a layer of a semiconductor overlying the layer of first material and overlying a second region of the substrate surface; a first region of the layer of...

20060141665 - Substrate having a plurality of i/o routing arrangements for a microelectronic device: A substrate is provided for packaging a microelectronic device having a pattern of contacts on the surface thereof. The substrate is formed from a support member having a substantially planar surface, and first, second, and third electrically conductive paths. The electrically conductive paths each extends from a corresponding device-attachable region...

20060141667 - Bare die socket: A socket for removably mounting a bare die to a substrate, such as a printed circuit board. This socket is formed by insert molding signal conductors in an insulative housing. A ground structure is separately provided to control the impedance of the signal conductors and to reduce cross talk. The...

20060141666 - Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby: The present invention relates to a method for producing a module including an integrated circuit die on a substrate. A substrate is provided, a metallization structure is provided which includes a conductive path and a metallization contact pad on the substrate. The integrated circuit die is placed onto the substrate,...

20060141668 - Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the upper and lower substrates are interconnected by wire bonding; and further in which at least one of the packages...

20060141669 - Semiconductor package having semiconductor constructing body and method of manufacturing the same: A semiconductor package includes at least one semiconductor constructing body which has a semiconductor substrate and a plurality of external connection electrodes formed thereon. An insulating film covers the semiconductor constructing body. Each of interconnections which has a projecting electrode is formed on the insulating film. The projecting electrodes of...

20060141670 - Method of forming fine metal pattern and method of forming metal line using the same: There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first interlayer insulating layer is formed. A via plug is formed on the...

20060141671 - Thermal interface structure with integrated liquid cooling and methods: A method and device for thermal conduction is provided. A thermal interface device and method of formation is described that includes advantages such as improved interfacial strength, and improved interfacial contact. Embodiments of thermal conduction structures are shown that provide composite thermal conduction and circulated liquid cooling. Embodiments are further...

20060141673 - Integrated circuit device having reduced bow and method for making same: An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A...

20060141672 - Method for cutting lead terminal of package type electronic component: In an electronic component comprising a semiconductor chip packaged in a molded part from which the lead terminals of the semiconductor chip project, a main cutting notch is formed on the obverse surface of each lead terminal before molding the molded part while leaving unnotched portions adjoining both ends of...

20060141674 - Windowed package having embedded frame: An integrated circuit (IC) package includes a mold compound, a die, and a window. The mold compound has a frame embedded within it. The frame has a top surface, a bottom surface, and a top-to-bottom opening therein. The die is attached to the mold compound, wherein the embedded frame lies...

20060141675 - Method of manufacturing heat spreader having vapor chamber defined therein: A method for manufacturing a vapor chamber-based heat spreader includes the following steps: (1) providing a mold, the mold having a surface; (2) electrodepositing a layer of metal coating on the surface of the mold; (3) removing the mold from the coating layer, wherein the coating layer defines therein a...

20060141676 - Method for producing semiconductor substrate: To provide a method for producing a semiconductor substrate able to uniformly and quickly fill through-holes in the semiconductor substrate with conductive material. This method comprises a process for forming through-holes (14) in a substrate (10), a process for disposing solder (42) on one surface of the substrate, and a...

20060141677 - Method of manufacturing a semiconductor device: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing...

20060141678 - Forming a nanotube switch and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a substrate comprising a power pad, and attaching a nanotube comprising at least one side chain to the power pad....

20060141679 - Vertically stacked field programmable nonvolatile memory and method of fabrication: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum...

20060141680 - Processing a memory link with a set of at least two laser pulses: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within...

20060141681 - Processing a memory link with a set of at least two laser pulses: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within...

20060141682 - Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation: A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure,...

20060141685 - Liquid crystal display device and fabrication method thereof: A method for fabricating a liquid crystal display includes providing a first substrate having a pixel part and a driving circuit part, forming a gate electrode in the pixel part of the first substrate, forming a first insulation film, a first amorphous silicon thin film and a second amorphous silicon...

20060141684 - Polysilicon film, thin film transistor using the same, and method for forming the same: A crystallizing method for forming a poly-Si film is described as follows. First, forming an activated layer on a substrate, and the molecule structure of the activated layer includes carbon, hydrogen, oxygen and silicon. And then, forming an amorphous silicon film on the activated layer. Finally, performing an annealing process...

20060141683 - Production method for thin-film semiconductor: A method of fabricating a thin-film of a semiconductor material includes: a scanning irradiation step of, in order to form a polycrystalline silicon film on the surface of a substrate, focusing first pulse laser light having a visible wavelength into a line shape having an intensity distribution of an approximately...

20060141686 - Copper gate electrode of liquid crystal display device and method of fabricating the same: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (TFT-LCD) device, at least comprises an adhesive layer formed on a glass substrate, and a patterned copper layer formed on the adhesive layer. The adhesive layer at least comprises one of nitrogen and phosphorus (for example, polysilazane) for enhancing...

20060141687 - Methods of forming semiconductor constructions: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of...

20060141688 - Method for producing insulated gate thin film semiconductor device: An amorphous semiconductor film is etched so that a width of a narrowest portion thereof is 100 μm or less, thereby forming island semiconductor regions. By irradiating an intense light such as a laser into the island semiconductor regions, photo-annealing is performed to crystallize it. Then, of end portions (peripheral...

20060141689 - Semiconductor device and method of manufacturing the semiconductor device: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on...

20060141691 - Method for fabricating semiconductor device: A method for fabricating a semiconductor memory device is provided. The method includes: forming a trench in a portion of a substrate, defined as a cell region; forming a first polysilicon layer doped with N-type impurities on regions where N-type metal-oxide-semiconductor (MOS) transistors are to be formed in the cell...

20060141690 - Method for manufacturing a semiconductor device: Provided is a method for manufacturing a semiconductor device comprising forming a device isolation layer on a semiconductor substrate; forming gate insulating layers on the upper part of the semiconductor substrate having the device isolation layers formed thereon; forming an undoped layer for a gate electrode; implanting mixed dopant ions...

20060141692 - Method of fabricating cmos image sensor: A method of fabricating a CMOS image sensor can minimize a dark current by avoiding a dry etch process of a photodiode surface. The method can also reduce a contact resistance and variation of the contact resistance of a read-out circuit unit within a unit pixel. The method includes steps...

20060141694 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same are provided. The method includes: forming a plurality of protruded patterns smaller than gate structures by selectively removing predetermined portions of a substrate; and forming the gate structures over the protruded patterns. The semiconductor device includes: a plurality of protruded...

20060141693 - Semiconductor multilayer interconnection forming method: In a method for forming a wiring using a dual damascene process in which a multilayer wiring structure is formed by embedding a first etching space formed in an interlayer insulating layer and a second etching space which communicates thereto with a conductor material, a number of steps may be...

20060141695 - Methods of forming thin layers including zirconium hafnium oxide and methods of forming gate structures, capacitors, and flash memory devices using the same: Methods of forming a zirconium hafnium oxide thin layer on a semiconductor substrate by supplying tetrakis(ethylmethylamino)zirconium ([Zr{N(C2H5)(CH3)}4], TEMAZ) and tetrakis(ethylmethylamino)hafnium ([Hf{N(C2H5)(CH3)}4], TEMAH) to a substrate are provided. The TEMAZ and the TEMAH may be reacted with an oxidizing agent. The thin layer including zirconium hafnium oxide may be used for...

20060141697 - Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a...

20060141696 - Method for forming landing plug contact in semiconductor device: A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation...

20060141698 - Method of improved high k dielectric - polysilicon interface for cmos devices: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide...

20060141699 - Method for fabricating semiconductor memory device: A method for fabricating a semiconductor memory device is provided. The method includes: forming an inter-layer insulation layer with a storage node contact hole on a substrate; forming storage node contact spacers on sidewalls of the inter-layer insulation layer in the storage node contact hole; forming a storage node contact...

20060141700 - Method for fabricating semiconductor memory device having recessed storage node contact plug: A semiconductor memory device and a method for fabricating a semiconductor memory device are provided. The method includes forming an inter-layer insulation layer having a storage node contact hole on a substrate; forming a pair of storage node contact spacers on sidewalls of the storage node contact hole; forming a...

20060141701 - Semiconductor device having trench capacitors and method for making the trench capacitors: A semiconductor device having a trench capacitor is disclosed. The trench is formed on the surface of a semiconductor substrate. A first insulating film is formed on the side wall of the trench and a semiconductor film is buried in the trench. The first insulating film and the semiconductor film...

20060141704 - Manufacturing method of semiconductor device: A method of manufacturing a semiconductor device including forming a gate oxide layer, a first conductive layer, a capacitor dielectric layer, and a second conductive layer on a semiconductor substrate. The method also includes patterning the first and second conductive layers, the gate oxide layer, and the field oxide layer...

20060141702 - Method for depositing titanium oxide layer and method for fabricating capacitor by using the same: Disclosed are a method for depositing a titanium oxide (TiO2) layer and a method for fabricating a capacitor by using the same. The method for forming the TiO2 layer includes the steps of: a) adsorbing titanium hydride (TiH2) on a wafer loaded into a chamber by supplying TiH2 to the...

20060141703 - Method of manufacturing nonvolatile organic memory device and nonvolatile organic memory device manufactured by the same: A method of manufacturing a nonvolatile organic memory device including a memory layer interposed between an upper electrode layer and a lower electrode layer, which includes dispersing ions of conductive nanoparticles in an organic material disposed between the two electrode layers and then reducing the ions of conductive nanoparticles into...

20060141705 - Method for fabricating metal-insulator-metal capacitor of semiconductor device: A method for fabricating a metal-insulator-metal (MIM) capacitor of a semiconductor device is provided. The method includes simultaneously patterning a lower metal film pattern and a dielectric film pattern to form a first structure in a MIM capacitor region and a second structure in a metal line region, removing the...

20060141706 - Methods of forming non-volatile semiconductor memory devices using prominences and trenches, and devices so formed: A semiconductor substrate is patterned to form a depression and prominence. A floating gate is formed so as to cover at least both sidewalls of the prominence of the depression and prominence, and is then etched to form a trench for a device isolation self-aligned with the floating gate. Related...

20060141707 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device and a method for fabricating a semiconductor memory device are provided. A semiconductor memory device includes a substrate, an inter-layer insulation layer including a storage node contact hole and formed on the substrate, a pair of storage node contact spacers formed on sidewalls of the storage...

20060141708 - Non-volatile memory device with buried control gate and method of fabricating the same: In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a...

20060141709 - Method for programming multi-level nitride read-only memory cells: A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low Vt value. A data region that is to be programmed to a highest Vt value is programmed first. Remaining data regions in the nitride...

20060141710 - Nor-type flash memory device of twin bit cell structure and method of fabricating the same: A NOR-type flash memory device comprises a plurality twin-bit memory cells arranged so that pairs of adjacent memory cells share a source/drain region and groups of four adjacent memory cells are electrically connected to each other by a single bitline contact....

20060141711 - Method of manufacturing flash memory device: The present invention relates to a method of manufacturing flash memory devices. According to the present invention, an inter-gate insulating film formed between a floating gate and a control gate is formed to have an NONON structure, thus removing the interface of polysilicon and an oxide film. It is thus...

20060141712 - Method for manufacturing pmosfet: A method for manufacturing a PMOSFET uses a trench-type gate structure only in a PMOSFET region of a peripheral circuit, except for a cell, to overcome the shortcomings of a MOSFET caused by reduction in design rule, realize stable threshold voltage, and improve the characteristics and reliability of a PMOSFET...

20060141713 - Manufacturing method with self-aligned arrangement of solid body electrolyte memory cells of minimum structure size: The object of providing a method for manufacturing solid body electrolyte memory cells or CB memory cells, respectively, which is suited for the simplified manufacturing of highly dense arrays with crosspoint architecture is solved by the present invention in that the solid body electrolyte memory cells are manufactured by self-aligned...

20060141714 - Method for manufacturing a semiconductor device: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, in a semiconductor substrate; simultaneously forming a...

20060141715 - Integrated circuit devices having contact holes exposing gate electrodes in active regions and methods of fabricating the same: Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion...

20060141716 - Method for manufacturing a cell transistor of a semiconductor memory device: Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device. The method comprises the steps of: forming device isolation films and a well on a semiconductor substrate; forming a threshold voltage adjust region by ion-implanting a first conductive impurity dopant into the well of the semiconductor...

20060141717 - Method of forming isolation film in semiconductor device: The present invention relates to a method of forming isolation films of a semiconductor device. According to the present invention, an oxidization process is performed to oxidize inner walls of trenches in a pre-heating period where temperature is raised in order to deposit an insulating material within a chamber so...

20060141718 - Method of manufacturing flash memory device: The present invention relates to a method of manufacturing a flash memory device. According to the method of manufacturing the flash memory device, a gate line is formed to have a structure in which a tunnel oxide film, a polysilicon layer for floating gate, dielectric films and a polysilicon layer...

20060141720 - Method of fabricating mos transistor: A method for fabricating a MOS transistor is suitable for modifying the configuration of a gate electrode. The method includes coating a first oxide layer on a semiconductor substrate and removing a predetermined width of the first oxide layer; forming an LDD region in the substrate; forming a gate spacer...

20060141719 - Method of fabricating semiconductor device: A gate is formed on a predetermined area of a substrate. A spacer insulating layer is formed on sidewalls of the gate. An insulating interlayer is formed over the substrate including the gate and the spacer insulating layer. Polymer generation is simultaneously carried out on a lateral side of the...

20060141722 - Method of sequentially forming silicide layer and contact barrier in semiconductor integrated circuit device: A method of sequentially forming a silicide layer and a contact barrier in a semiconductor device is provided. In the method, a pre-metal dielectric layer is deposited over an underlying structure that has a silicon substrate, a gate electrode on the substrate, and source/drain regions in the substrate. Contact holes...

20060141721 - Semiconductor transistor device and method for manufacturing the same: A semiconductor transistor device and a method for manufacturing the same are provided. The method includes forming a silicon epitaxial layer having a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate and forming a source and drain junction by ion implantation and rapid annealing in...

20060141723 - Method for manufacturing semiconductor device: A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor...

20060141726 - Field effect transistor with a high breakdown voltage and method of manufacturing the same: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer...

20060141725 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device wherein before an insulating film spacer of a contact region is removed after a gate line and source/drain are formed, a high quality buffer oxide film formed between the gate line and the insulating film spacer is made dense by means of...

20060141724 - Method of manufacturing mos transistor: A method of manufacturing a MOS transistor capable of suppressing a short channel effect by suppressing boron (B) ion diffusion in the MOS transistor. The method includes steps of: forming an impurity diffusion suppressing layer in an active region of a semiconductor substrate; forming an impurity layer containing boron ions...

20060141727 - Method of fabricating low-power cmos device: A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The method includes forming a shallow trench in a...

20060141728 - Formation of junctions and silicides with reduced thermal budget: Method of formation of a metal-silicide layer (12, 13, 14, 18, 19) an a semiconductor substrate (1), the semiconductor substrate (1) including at least a dopant region (5); the dopant region (5) including an ultra-shallow junction region; the method including as a first step at least one impurity implantation process...

20060141729 - System and method for suppressing oxide formation: A system and method for suppressing sub-oxide formation during the manufacturing of semiconductor devices (such as MOSFET transistor) with high-k gate dielectric is disclosed. In one example, the MOSFET transistor includes a gate structure including a high-k gate dielectric and a gate electrode. In this example, the gate structure is...

20060141730 - Process for manufacturing integrated resistive elements with silicidation protection: In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a predetermined resistivity is then formed in the active area (15). Prior to forming the resistive...

20060141731 - Method for forming shallow trench isolation in semiconductor device: A method for forming shallow trench isolation in a semiconductor device. The method includes forming a pad oxide and a pad nitride on a semiconductor substrate in successive order, forming a trench in the substrate by etching the pad nitride, the pad oxide and the substrate, removing a portion of...

20060141732 - Method for forming isolation region in semiconductor device: A method for forming an isolation region in a semiconductor device such as a photodiode forms depletion layers at boundary regions between N-type regions of the photodiode and an ion injection layer in which P-type impurity ions are injected. Depletion layers are also formed between the N-type regions of the...

20060141733 - Capacitors having a horizontally folded dielectric layer and methods for manufacturing the same: Capacitors having a horizontally folded dielectric layer and methods of manufacturing is the same are provided. An example method for manufacturing a capacitor includes forming a first insulating layer pattern above a substrate, forming a first silicon epitaxial growth layer above a region of the silicon substrate exposed by the...

20060141734 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided, wherein a large MIM capacitor including an uneven surface if formed to increase capacitance. The method includes forming a polysilicon layer on a lower metal layer by plasma-enhanced chemical vapor deposition; forming an uneven surface in the polysilicon layer by etching...

20060141735 - Method for forming a mim capacitor in a semiconductor device: In a method of forming a metal-insulator-metal (MIM) capacitor in a semiconductor device, after forming a capacitor insulation layer on a lower metal layer of the MIM capacitor, an upper electrode is formed by ion implantation into the capacitor insulation layer and silicidation, without a typical reactive ion etching process....

20060141736 - Method for fabricating capacitor of semiconductor memory device using amorphous carbon: A method for fabricating a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming storage node contact plugs penetrating into the inter-layer insulation layer; forming a stack structure formed by stacking a first protective barrier layer and a sacrificial layer on the inter-layer...

20060141738 - Method for measuring bonding quality of bonded substrates, metrology apparatus, and method of producing a device from a bonded substrate: In a method for measuring the bonding quality of bonded substrates, such as bonded SOI wafers, a plurality of marks are created at a first side of a top substrate after, or before, the bonding of the top substrate onto a bottom substrate. Then, the positions of the plurality of...

20060141737 - Planar magnetic tunnel junction substrate having recessed alignment marks: A method for forming an alignment mark structure for a semiconductor device includes forming an alignment recess at a selected level of the semiconductor device substrate. A first metal layer is formed over the selected substrate level and within the alignment recess, wherein the alignment recess is formed at a...

20060141741 - Adjuvant for chemical mechanical polishing slurry: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms a adsorption layer on the cationically charged material in order to increase the polishing selectivity of the anionically charged material to cationically charged material, wherein the adjuvant comprises a...

20060141739 - Method for fabricating contact holes in a semiconductor body and a semiconductor structure: A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa regions are provided in the semiconductor body, and electrodes are provided in the trenches, which electrodes are electrically insulated from the semiconductor body by...

20060141740 - Semiconductor device with shallow trench isolation and a manufacturing method thereof: An exemplary method of manufacturing a shallow trench isolation structure in a semiconductor device includes forming a first trench region by etching the semiconductor substrate to a predetermined depth, forming a first oxide layer on the entire surface of the semiconductor substrate so as to fill the first trench region,...

20060141749 - Adhesive of folder package: A package includes a flexible substrate with a first region and a second region, an encapsulated die supported by the first region, and a conformable fold adhesive introduced between the encapsulated die and the flexible substrate. The second region of the flexible substrate is folded over the surface of the...

20060141747 - Controlled cleaving process: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define...

20060141743 - Method and system for 3d alignment in wafer scale integration: A substrate bonding system has a first and a second substrate table for holding a first substrate and a second substrate, respectively, and a controller. The first substrate includes a first device having first contact pads and the second substrate a second device having second contact pads. The wafer bonding...

20060141745 - Method and system for wafer bonding of structured substrates for electro-mechanical devices: A method for forming a composite substrate structure. The method includes providing a first substrate, the first substrate having a surface region and a backside region, providing a handling substrate, the handling substrate having a bonding surface and a handling surface, and activating at least one of the surface region...

20060141742 - Method of producing a complex structure by assembling stressed structures: The invention relates to a method of producing a complex microelectronic structure, in which two basic microelectronic structures (1, 3) are assembled at the two respective connecting faces (3) thereof. The invention is characterised in that, before assembly, a difference is created in the tangential stress state between the two...

20060141746 - Methods for forming semiconductor structures: The invention concerns a method of treating one or both bonding surfaces of first and second substrates and in particular, the surfaces of donor and receiver wafers that are intended to be bonded together. A simultaneous cleaning and activation step is carried out immediately prior to bonding the wafers together,...

20060141744 - System and method of forming a bonded substrate and a bonded substrate product: The invention provides a method of forming a bonded substrate that includes providing a first substrate having a first substrate shape and at least one first alignment mark positioned at a first surface side. A second substrate is providing having a second substrate shape. The second substrate is oriented relative...

20060141748 - Thermal treament of a semiconductor layer: A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer...

20060141750 - Semiconductor integrated device and method for manufacturing same: A method for manufacturing a semiconductor integrated device includes steps of forming an integrated circuit element on a semiconductor substrate, forming internal wiring, forming a groove along a scribe line on a back surface of the semiconductor substrate to expose a portion of the internal wiring, forming a metal film...

20060141751 - Method for making a silicon dioxide layer on a silicon substrate by anodic oxidation: A method for forming silicon dioxide layer on a silicon substrate by anodic oxidation includes: providing a silicon substrate which has a polished face; providing an anodic oxidation apparatus which is filled with an electrolyte; providing a platinum piece and placing the platinum piece in the electrolyte as a cathode;...

20060141753 - Epitaxial structure of gallium nitride series semiconductor device and process of manufacturing the same: An epitaxial stricture of a gallium nitride series semiconductor device and a process of forming the same are described. A first buffer layer of gallium nitride is epitaxially formed on a substrate at a first temperature. A second buffer layer of indium gallium nitride is formed on the first buffer...

20060141752 - Methods for forming a p-type polysilicon layer in a semiconductor device: A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and thereafter forming a P-type polysilicon layer by thermally diffusing the plurality...

20060141754 - Laser treatment apparatus, laser treatment method, and manufacturing method of semiconductor device: The invention relates to a laser treatment apparatus including a laser oscillator, an interlock provided in the laser oscillator, a movable table which moves with a certain movement period, a timer, an interlock provided in the timer, a sensor which can detect movement of the movable table, and a computer,...

20060141755 - Method of configuring a process to obtain a thin layer with a low density of holes: A method for configuring a process for treating a semiconductor wafer. A minimum layer thickness of a transferred layer to be provided is determined to obtain a processed layer that has a preselected target thickness and target maximum density of through holes that extend completely therethrough, by conducting a predetermined...

20060141756 - Method for producing a semiconductor structure: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a...

20060141757 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. The method includes the steps of preparing a semiconductor substrate, forming a buffer oxide layer, forming a hard mask layer on the buffer oxide layer, etching an exposed portion of the buffer oxide layer by using the hard mask layer, etching...

20060141758 - Method of forming contact pads: In a method of forming a semiconductor structure, a substrate comprising at least one contact pad is provided. A passivation layer is formed over the substrate. A mask which does not cover a portion of the passivation layer located over the at least one contact pad is formed over the...

20060141759 - Method of forming pad and fuse in semiconductor device: A method of forming a pad and a fuse in a semiconductor device. A copper layer located in both a fuse region and a pad region is formed in a dielectric layer. A first insulating layer is formed on the dielectric layer to cover the copper layer and selectively etched...

20060141760 - Method for producing an electrical component: To expose a submerged bondable terminal pad in a component that includes at least two substrates which are joined with each other, it is proposed that grooves of relatively shallow depth be provided on the connecting surface of the second substrate before the two substrates are joined. After the two...

20060141762 - Interlocking via for package via integrity: A method of forming an interconnection structure in a microelectronic package, and an interconnection structure of a microelectronic package formed according to the method. The method includes: providing a combination including a first conductive layer and a dielectric layer fixed to the conductive layer; providing a hole through the dielectric...

20060141765 - Metal wiring pattern for memory devices: A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on...

20060141764 - Method of manufacturing wiring board: A method of manufacturing a wiring board is disclosed. The wiring board has: a capacitor, having multiple electrode layers which oppose each other with a dielectric layer in between, that is connected to a semiconductor chip; one or more via wirings which pierce the electrode layers and which are connected...

20060141761 - System for and method of forming via holes by multiple deposition events in a continuous inline shadow mask deposition process: Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its...

20060141763 - System for and method of planarizing the contact region of a via by use of a continuous inline vacuum deposition: A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316)...

20060141767 - Metal wiring for semiconductor device and method for forming the same: A metal wiring for a semiconductor device and a method for forming the same are provided. The metal wiring includes a first insulating layer and a second insulating layer; an interlayer insulating film formed between the first and second insulating layers, wherein the interlayer insulating film is provided with holes...

20060141766 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device in which an etching process for forming a M1 trench for a bit line is stopped on a nitride etch-stop film and the bit line is formed on the nitride film....

20060141769 - Method for forming metal line of semiconductor device: A method for forming a metal line of a semiconductor device is provided, in which a Cu residue and a mixture of different materials generated after a planarization process are completely removed to improve reliability of the metal line. The method includes removing copper residue on a semiconductor substrate by...

20060141768 - Method to eliminate plating copper defect: A method of forming a metal layer with reduced defects comprising providing a structure having a dielectric layer formed over it, forming a dielectric layer having an opening, lining the opening with a metal seed layer, treating the metal seed layer with a cleaning process to remove contaminates from it,...

20060141770 - Method for fabricating storage node contact in semiconductor device: Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused during a storage node contact isolation process. In accordance with the present invention, a chemical mechanical polishing (CMP) process that...

20060141771 - Semiconductor device with a metal line and method of forming the same: A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on the planarized substrate. The method further includes depositing a...

20060141773 - Method of forming metal line in semiconductor device: A method of forming a metal line in a semiconductor device reduces production costs through a simplified fabricating process. The method includes steps of forming a first metal line on a semiconductor substrate; forming an insulating layer over the semiconductor substrate including the first metal line; coating a photoresist on...

20060141772 - Methods of forming interconnection lines in semiconductor devices: The present disclosure improves characteristics and reliability of a device by preventing seams within a copper layer, wherein seams are created when forming a copper line by a damascene process. Such seams created within a first and a second copper layer are prevented by a process in which the first...

20060141774 - Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure: A mask pattern (110) of a pattern transfer mask (101) includes a light shielding pattern (111) and a light transmitting pattern (112). The light shielding pattern (111) has a shape (pattern) subjected to undersizing near portions corresponding to via holes (51H). It is desirable to make undersizing to a greater...

20060141778 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a...

20060141775 - Method of forming electrical connections in a semiconductor structure: A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a material formed on a first surface of the substrate. At least one recess is formed in the layer of material. The formation of the at least one recess comprises performing a dry etching process....

20060141776 - Method of manufacturing a semiconductor device: Electrical characteristics of a semiconductor device may be enhanced by completely removing a residue such as a polymer formed in a trench when the semiconductor device is manufactured by a method including: forming a via hole and a trench on a semiconductor substrate by an etching process; coating a photoresist...

20060141777 - Methods for patterning a layer of a semiconductor device: A patterning layer of a single or multiple layer structure formed on a lower layer may be etched to form one or more steps therein, when the patterning layer is first dry etched to a partial depth thereof using a first resist pattern and then the patterning layer is etched...

20060141779 - Method for forming an aluminum contact: A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes forming a photoresist pattern for ion...

20060141780 - Methods for the plasma formation of a microelectronic barrier layer: The fabrication of an interconnect for a microelectronic device through the use of a nitrogen plasma to form a barrier layer. In one embodiment, an opening is formed in a dielectric layer and a metal layer is formed on the sidewalls and bottom of the opening. The metal layer, such...

20060141781 - Method for forming metal line of semiconductor device: A method for forming a metal line of a semiconductor device forms an aluminum line having an excellent orientation. A specific resistance of a metal line is reduced, thereby enabling sufficient supply of a desired electric current. The method includes steps of forming a lower reflection preventing layer on a...

20060141782 - Film forming method, film forming system and recording medium: A wafer boat 25 holding a plurality of wafers W is loaded into a reaction vessel 2, and the wafers W are processed by a film forming process specified by a film forming recipe 1 specifying, for example, Si2Cl2 gas and NH3 gas as film forming gases. Subsequently, a purging...

20060141783 - Sputtering apparatus and method for forming metal silicide layer using the same: A sputtering apparatus for forming a low-resistance uniform metal silicide layer without additional heat treatment and a metal silicide layer forming method using the same are provided. The sputtering apparatus includes a sputtering chamber; a gas introduction port formed at an upper location of a lateral wall of the sputtering...

20060141784 - Copper electrodeposition in microelectronics: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu...

20060141785 - Inter-metal dielectric of semiconductor device and manufacturing method thereof: An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper line layer therein, forming a plasma enhanced fluorosilicate glass (PEFSG) layer...

20060141787 - Cleaning methods for silicon electrode assembly surface contamination removal: Silicon electrode assembly decontamination cleaning methods and solutions, which control or eliminate possible chemical attacks of electrode assembly bonding materials, comprise ammonium fluoride, hydrogen peroxide, acetic acid, optionally ammonium acetate, and deionized water....

20060141789 - Method for etching and for forming a contact hole using thereof: A method for forming a structure formed by etching which is typified by a contact hole in the semiconductor and a method for manufacturing a display device using the structure. The etching method includes at least, forming an organic mask having a first opening portion and a second opening portion...

20060141788 - Method for fabricating semiconductor device capable of preventing scratch: Disclosed is a method for fabricating a semiconductor device capable of preventing scratches. The method includes the steps of: forming a substrate divided into a peripheral region and a cell region where a capacitor including a metal plate electrode on which particles with a pointed shape are generated is formed;...

20060141786 - Method of manufacturing an electronic device and electronic device: A method of manufacturing an electronic device, particularly an acceleration sensor, comprising providing a wafer (10) having first and second semiconductor layers (12, 16) with a buried oxide layer (14) therebetween and forming a semiconductor device (such as a detection circuit) on one side of the wafer (10) in the...

20060141790 - Chemical mechanical polishing method: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer...

20060141791 - Method for fabricating a semiconductor device: The method includes chemical-mechanical polishing to planarize an insulating interlayer deposited on a lower pattern. The insulating interlayer is polished using a surfactant. The chemical-mechanical polishing includes at least two separate polishing steps of different fluxes of the surfactant. The first polishing step is performed for touching up an upper...

20060141792 - Process for manufacturing semiconductor integrated circuit device: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP). method, a process for manufacturing. a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main...

20060141793 - Forming of trenches or wells having different destinations in a semiconductor substrate: A method for forming, in a semiconductor substrate, wells and/or trenches having different destinations, including the steps of at least partly simultaneously etching cavities according to the pattern of the trenches and/or wells; closing the openings of the cavities with at least one first non-conformal thick layer, and selectively opening...

20060141795 - Method for fabrication semiconductor device: The object of this invention is to provide a method for fabricating a semiconductor device in which the yield and productivity are improved. In the method for fabricating a semiconductor device according to the invention, a plasma etching system is prepared which includes a vacuum chamber 1, a susceptor 7...

20060141796 - Method of manufacturing semiconductor device: The method includes forming an isolation film on a silicon substrate to define an active region; forming an antireflective film on an entire surface of the substrate containing the isolation film; forming a photosensitive film pattern on the antireflective film while exposing a portion of the isolation film or the...

20060141794 - Plasma system and method for anisotropically etching structures into a substrate: A method and a plasma system are provided for anisotropically etching structures into a substrate positioned in an etching chamber, e.g., structures defined using an etching mask in a silicon substrate, using a plasma. For this purpose, the etching chamber is supplied at least intermittently with an etching gas and...

20060141797 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: forming device isolation layers on a substrate; sequentially forming an anti-reflective coating layer and a photoresist layer on the substrate; patterning the anti-reflective coating layer and the photoresist layer to expose substrate regions in which active regions of...

20060141798 - Device and method of performing a seasoning process for a semiconductor device manufacturing apparatus: A method of performing a seasoning process for a semiconductor device processing apparatus is provided by the present invention. The method includes: forming a material layer on a test wafer; coating a photoresist on the material layer; patterning the photoresist so as to expose a central region of the wafer...

20060141799 - Method of manufacturing a semiconductor device: A semiconductor device may be manufactured by employing an ashing process for removing a photoresist in a process chamber, wherein the ashing process comprises: removing the photoresist for a first predetermined process time by flowing one or more oxygen and nitrogen source gases into the process chamber at first predetermined...

20060141800 - Method for forming step channel of semiconductor device: A method for forming a step channel of a semiconductor device is disclosed. The method for forming a step channel of a semiconductor device comprises forming a hard mask layer pattern defining a step channel region on a semiconductor substrate, forming a spacer on a sidewall of the hard mask...

20060141801 - Semiconductor device manufacturing method, wafer, and wafer manufacturing method: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with...

20060141802 - Silicon electrode assembly surface decontamination by acidic solution: Methods for cleaning silicon surfaces of electrode assemblies by efficiently removing contaminants from the silicon surfaces without discoloring the silicon surfaces using an acidic solution comprising hydrofluoric acid, nitric acid, acetic acid, and balance deionized water....

20060141803 - Method of cleaning silicon nitride layer: A method of cleaning a silicon nitride layer on a substrate is provided to effectively remove negative-charged impurities such as polymer and particle from the silicon nitride layer. In the method, the zeta potential of the silicon nitride layer is changed from positive to negative, and then the silicon nitride...

20060141804 - Method and apparatus to facilitate electrostatic discharge resiliency: A circuit element (such as an asperity sensor circuit (11)) as is formed (21) using semiconductor fabrication processing has a high resistance layer formed (22) thereover. The high resistance layer is preferably formed using semiconductor fabrication processing. The high resistance layer can be comprised of a variety of materials and...

20060141805 - Method of depositing dielectric films: A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer...

20060141806 - Apparatus and process for treating dielectric materials: Apparatuses and processes for treating dielectric materials such as low k dielectric materials, premetal dielectric materials, barrier layers, and the like, generally comprise a radiation source module, a process chamber module coupled to the radiation source module; and a loadlock chamber module in operative communication with the process chamber and...

20060141807 - Seal hardening furnace of liquid crystal display device having rack bar: A seal hardening furnace is presented in which seal lines in a liquid crystal display panel are hardened. The seal hardening furnace includes a cassette having a rack bar structure. The rack bar structure has rack bars for supporting the substrate along one direction and rack bar supports at ends...

20060141808 - Method for the heat treatment of substrates: A substrate undergoes a semiconductor fabrication process at different temperatures in a reactor without changing the temperature of the reactor. The substrate is held suspended by flowing gas between two heated surfaces of the reactor. Moving the two heated surfaces in close proximity with the substrate for a particular time...

20060141809 - Single side workpiece processing: A centrifugal workpiece processor for processing semiconductor wafers and similar workpieces includes a head which holds and spins the workpiece. The head includes a rotor having a gas system. Gas is sprayed or jetted from inlets in the rotor to create a rotational gas flow. The rotational gas flow causes...

20060134807 - Method of manufacturing solid image pickup apparatus: A first gate electrode and a second gate electrode are formed on a semiconductor substrate, and then a resist pattern is formed so as to selectively leave open a portion including an overlap between the first and second gate electrodes. Next, the overlap between the gate electrodes is removed through...

20060134809 - Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step: An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250′, and a ferromagnetic top plate 20a. Also, a method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil...

20060134808 - Ferroelectric capacitor stack etch cleaning methods: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define...

20060134810 - Apparatus and method for voltage contrast analysis of a wafer using a titled pre-charging beam: A method for electrically testing a wafer that includes: receiving a wafer having a first layer that is at least partly conductive and a second layer formed over the first layer, following production of openings in the second layer; directing towards the wafer a first set of beams of charged...

20060134811 - Semiconductor processing apparatus and method: A semiconductor processing apparatus includes a process chamber to accommodate a target substrate, a gas supply system to supply a process gas into the process chamber, an exhaust unit to exhaust the process chamber, and an exhaust line connecting the process chamber to the exhaust unit. An opening variable valve...

20060134812 - Inspection methods for a semiconductor device: An inspection method for a semiconductor device is disclosed. The method includes providing a semiconductor device, performing heat treatment on the semiconductor device, and inspecting the semiconductor device utilizing electron beam to acquire an analysis image. The semiconductor device comprises a substrate, a plurality of gate electrodes protruding on the...

20060134813 - Organic light-emitting panel, package process for organic light-emitting panel and coating apparatus thereof: An organic light-emitting panel, a process for packaging an organic light-emitting panel and a coating apparatus applied thereto are described. A patterned desiccant with large surface area is formed on a cover plate by an ink-jet printing process. The process for packaging an organic light-emitting panel and the coating process...

20060134814 - Self-alignment manufacturing method of the microlens and the aperture using in optical devices: The present invention discloses a self-alignment manufacturing method of a microlens and an aperture using in an optical device. The method manufactures the aperture and the circular opening in the opaque film on a transparent substrate, and utilizes the self-alignment backside exposure technology to precisely integrate the aperture and the...

20060134815 - Method of producing a diffraction grating: In an embodiment, a method of producing a diffraction grating comprises steps of: forming, on a man surface of a first member, a first mask having a plurality of resist patterns arranged at a Bragg diffraction period; etching the first member by use of the first mask, thereby providing the...

20060134816 - Semiconductor laser device of iii-v group compound and fabrication method therefor: A semiconductor laser device of a III-V group compound includes a substrate including a main surface having an inclination angle of less than 20° toward a [011] direction from a (100) plane and an inclined facet further inclined toward the [011] direction from the main surface, a light emitting stacked-layered...

20060134817 - Vertical-cavity surface-emission type laser diode and fabrication process thereof: A vertical-cavity, surface-emission-type laser diode includes an optical cavity formed of an active region sandwiched by upper and lower reflectors, wherein the lower reflector is formed of a distributed Bragg reflector and a non-optical recombination elimination layer is provided between an active layer in the active region and the lower...

20060134818 - Method for fabricating micro-mechanical devices: A method of fabricating micro-mechanical devices. A mesa is etched in a homogeneous wafer. The wafer is bonded to a patterned substrate with the mesa defining device elements suspended above the substrate. A portion of the wafer is removed until a desired device thickness is achieved. Discrete elements of the...

20060134819 - Process for forming mems: The present invention relates to a process for forming microstructures on a substrate. A plating surface is applied to a substrate. A first layer of photoresist is applied on top of the plating base. The first layer of photoresist is exposed to radiation in a pattern to render the first...

20060134820 - Process for forming microstructures: The present invention relates to a process for forming microstructures on a substrate. A plating surface is applied to a substrate. A first layer of photoresist is applied on top of the plating base. The first layer of photoresist is exposed to radiation in a pattern to render the first...

20060134821 - Manufacturing method of a microelectromechanical switch: The method for manufacturing a micromechanical switch includes manufacturing a hanging bar, on a first semiconductor substrate, equipped at an end thereof with a contact electrode, and a frame projecting from the first semiconductor substrate. A second semiconductor substrate with conductive tracks includes a second input/output electrode and a third...

20060134823 - N,n'-di(phenylalky)-substituted perylene-based tetracarboxylic diimide compounds as n-type semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide 3,4,9,10-perylene-based compound having, attached to each of the imide nitrogen atoms a substituted or unsubsitituted phenylalkyl group. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said...

20060134824 - P-type ofet with fluorinated channels: The present invention provides an organic field-effect transistor (OFET) and a method of fabricating the OFET. The OFET, configured to function as a p-type semiconductor, includes a substrate having a top surface and a semiconductor layer located over the top surface. The semiconductor layer comprises organic semiconductor molecules. Each of...

20060134822 - Vertical interconnect for organic electronic devices: A device includes a plurality of organic electronic devices disposed on a substrate, wherein each of the organic electronic devices comprises a first electrode and a second electrode. Furthermore, the device includes an organic layer disposed between the first and second electrodes of each of the plurality of organic electronic...

20060134825 - Injection-molded package for mems inertial sensor: Methods of packaging devices such as MEMS devices are disclosed. An illustrative method of packaging a device in accordance with an illustrative embodiment of the present invention can include the steps of providing a substrate having an device provided therein or thereon, attaching a cap to the substrate and sealing...

20060134826 - Methods of forming semiconductor packages: The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods...

20060134827 - Microlenses including a plurality of mutually adhered layers of optically transmissive material and systems including the same: Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material. Systems include at least one microprocessor, a substrate including an array of microlenses formed thereon in electrical communication with the at least one microprocessor. At least one...

20060134828 - Package that integrates passive and active devices with or without a lead frame: According to an embodiment of the invention, a component package comprises a plurality of components and mold compound. The plurality of components are disposed on a zero plane of a removable substrate. The removal substrate is operable to hold the plurality of components in position. At least one of the...

20060134831 - Integrated circuit packaging using electrochemically fabricated structures: Embodiments of the invention provide methods for packaging integrated circuits and/or other electronic components with electrochemically fabricated structures which include conductive interconnection elements. In some embodiments the electrochemically produced structures are fabricated on substrates that include conductive vias while in other embodiments, the substrates are solid blocks of conductive material,...

20060134832 - Manufacturing method of semiconductor device: The manufacturing method of the semiconductor device of the present invention has a step forming solder balls on the circuit face of a mother chip, a step making flip chip bonding of the daughter chip after the step forming solder balls on the circuit face of the mother chip, and...

20060134830 - Method and system for performing die attach using a flame: Embodiments of a method for attaching a die to a substrate using a flame or other heat source are disclosed. The flame may be produced by combustible gas. Also disclosed are embodiments of a system for performing die attach using a flame. Other embodiments are described and claimed....

20060134833 - Packaged semiconductor die and manufacturing method thereof: Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the...

20060134834 - Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and saw device: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in...

20060134829 - Wafer scale integration of electroplate 3d structures using successive lithography, electroplated sacrifical layers, and flip-chip bonding: Wafer scale fabrication of three dimentional substantially enclosed structures on a MEMS/IC die use a combination of electrodeposition of structural and sacrificial layers and flip-chip alignment and bonding technology. A first wafer contains a die with MEMS and/or IC structures. On this MEMS/IC processed die, a first three dimensional structural...

20060134835 - Method for making a neo-layer comprising embedded discrete components: A stackable neo-layer comprising one or more embedded discrete electrical components is provided. A plurality of conductive traces, some of which terminate at a peripheral edge of the layer, are formed on sacrificial substrate in a series of process steps and discrete electrical components such as thick film components or...

20060134836 - Method of marking a low profile packaged semiconductor device: A semiconductor device (10) is made by mounting the bottom surfaces (31, 44, 54) of a semiconductor die (14) and a lead (15, 17) on a tape (12) and over a hole (19) in the tape. A vacuum is drawn through the hole to secure the die in place when...

20060134837 - Vertically stacked field programmable nonvolatile memory and method of fabrication: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum...

20060134839 - Low voltage non-volatile memory transistor: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor...

20060134838 - Processing a memory link with a set of at least two laser pulses: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within...

20060134840 - Electro-optical device and semiconductor circuit: A high performance circuit is formed by using a TFT with less fluctuation in characteristics, and a semiconductor device including such a circuit is formed. When the TFT is formed, first, a base film and a semiconductor film are continuously formed on a quartz substrate without expos