SEARCH:      Monitor Keywords |  Custom RSS

Semiconductor device manufacturing: process June invention type 06/06

20060141640 - Mtj elements with high spin polarization layers configured for spin-transfer switching and spintronics devices using the magnetic elements: A method and system for providing a magnetic element are disclosed. The method and system include providing first and second pinned layers, a free layer, and first and second barrier layers between the first and second pinned layers, respectively, and the free layer. The first barrier layer is preferably crystalline...

20060141641 - Repair and restoration of damaged dielectric materials and films: Methods of repairing voids in a material are described herein that include: a) providing a material having a plurality of reactive silanol groups; b) providing at least one reactive surface modification agent; and c) chemically capping at least some of the plurality of reactive silanol groups with the at least...

20060141642 - Method for making mask in process of fabricating semiconductor device: A method for making a mask in a process of fabricating a semiconductor device is disclosed, in which one database is classified into an SRAM block and a random logic block so that OPC is separately performed for the SRAM block and the random logic block, thereby improving performance of...

20060141645 - Light emitting device and manufacturing method thereof: The concentration of oxygen, which causes problems such as decreases in brightness and dark spots through degradation of electrode materials, is lowered in an organic light emitting element having a layer made from an organic compound between a cathode and an anode, and in a light emitting device structured using...

20060141644 - Light emitting diode and fabricating method thereof: A method for fabricating a light emitting diode (LED) is provided. Successively forming a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer on an epitaxy substrate; forming a bonding layer thereon; bonding a transferring substrate with the bonding layer; removing the epitaxy...

20060141643 - Manufacturing method of pixel structure of thin film transistor liquid crystal display: A method of fabricating a pixel structure of TFT LCD is provided. First, a gate pattern, pixel electrode pattern, gate isolating layer and semiconductor layer are formed over the substrate sequentially. Then, a patterning process is performed to remove the first metal layer over the pixel electrode pattern, wherein the...

20060141646 - Organic electroluminescent device and method of manufacturing the same: The invention provides an organic electroluminescent device and a method of manufacturing the same which conveniently reduce or suppress the transfer of ionic impurities into a light-emitting layer, and reduce or prevent the light-emitting property in the light-emitting layer from degrading, which promotes life extension. An organic electroluminescent device includes...

20060141647 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor forms silicon nitride (SiN) layer on a pad. Microlenses, having a minimum height and footprint according to a desired packing density of the lenses, are fabricated of an oxide film and a nitride film deposited on the silicon nitride. Since the lenses...

20060141648 - Light emitting device methods: Light-emitting device methods are disclosed....

20060141649 - Method of reducing insertion loss in a transition region between a plurality of input or output waveguides to a free space coupler region: A method for reducing insertion loss in a transition region between a plurality of input or output waveguides to a free space coupler region in a photonic integrated circuit (PIC) includes the steps of forming a passivation layer over the waveguides and region and forming the passivation overlayer such that...

20060141650 - Mems device package and method for manufacturing the same: A micro electromechanical system (MEMS) device package and a method of manufacturing the same are provided. The inventive MEMS device package includes: a device substrate with a MEMS active device being formed on the top surface thereof; internal electrode pads, each of which is positioned on the opposite side of...

20060141651 - Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation: A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure,...

20060141657 - Field emission device and manufacturing method thereof: It is an object to provide techniques for forming a field emission device of a field emission display device with the use of an inexpensive large-sized substrate according to the process that enables improving productivity. A field emission device according to the present invention includes a cathode electrode formed on...

20060141652 - Mems device package and method for manufacturing the same: A micro electromechanical system (MEMS) device package and a method of manufacturing the same are provided. The MEMS device package includes: a device substrate with a MEMS active device being formed on the top surface thereof; internal electrode pads, each of which is positioned on the opposite side of the...

20060141654 - Method for fabricating a cmos image sensor: A method for fabricating a CMOS image sensor in which an electron shower is performed for microlenses whose surfaces are charged to a positive potential, so as to neutralize the positive potential, thereby improving performance and yield of the image sensor....

20060141653 - Methods of manufacturing an image device: In methods of manufacturing an image device, a first structure including a transparent lower portion and an opaque upper portion is formed on a substrate having a photodiode. An etch stop layer pattern positioned over the photodiode is formed on the first structure. A second structure having at least one...

20060141656 - Micromechanical sensors and methods of manufacturing same: A micromechanical sensor and, in particular, a silicon microphone, includes a movable membrane and a counter element in which perforation openings are formed, opposite to the movable membrane via a cavity. The perforation openings are formed by slots, the width of which maximally corresponds to double the spacing defined by...

20060141655 - Photoelectric conversion device, its manufacturing method, and image pickup device: It is an object of the present invention to provide a manufacturing method of a photoelectric conversion device in which no plane channeling is produced even if ions are injected at a certain elevation angle into a semiconductor substrate surface made of silicon. A manufacturing method of a photoelectric conversion...

20060141658 - Corrugated diaphragm: A diaphragm includes a substrate having a hole and a sheet of material formed on the substrate and covering the hole. The sheet of material includes one or more corrugations that are substantially free of defects. A method of forming the diaphragm includes forming a corrugated surface free of stringers...

20060141659 - Single-crystal-silicon 3d micromirror: In a 3D free space micromirror device, a mirror plate is joined with actuators through flexible springs where the other ends of the actuators have fixed support on the substrate. Single crystal silicon and aluminum are used as bi-morph materials with silicon dioxide providing electrical isolation between the two. Thickness...

20060141660 - Cmos image sensor and method for fabricating the same: A CMOS image sensor and a method for fabricating the same prevent a lifting phenomenon of a microlens. The CMOS image sensor includes a semiconductor substrate structure in which at least one photodiode is disposed, an insulating interlayer formed on the semiconductor substrate structure, a patterned metal layer formed on...

20060141661 - Cmos image sensor and method of fabricating the same: A CMOS image sensor and a method of fabricating the same are provided. The image sensor includes a blocking layer protecting a photodiode at a diode region. The blocking layer is formed to cover a top of the diode region and extended to an active region so as to cover...

20060141662 - Photovoltaic component and production method therefor: The invention relates to an organic component comprising an improved top electrode and to a production method therefor. The top electrode is made of an organic material that is applied by means of printing techniques....

20060141663 - Method for forming metal interconnection of semiconductor device: A method for forming a metal interconnection of a semiconductor device avoids over-etching and under-etching through the use of the “self-stop” function of a nitridation layer, to prevent the occurrence of openings and voids in a copper interconnection and to obtain a constant trench depth. The method includes forming nitride...

20060141664 - Semiconductor devices having regions of induced high and low conductivity, and methods of making the same: Semiconductor apparatus comprising: a substrate having a substrate surface; a layer of a first material overlying a first region of the substrate surface; a layer of a semiconductor overlying the layer of first material and overlying a second region of the substrate surface; a first region of the layer of...

20060141665 - Substrate having a plurality of i/o routing arrangements for a microelectronic device: A substrate is provided for packaging a microelectronic device having a pattern of contacts on the surface thereof. The substrate is formed from a support member having a substantially planar surface, and first, second, and third electrically conductive paths. The electrically conductive paths each extends from a corresponding device-attachable region...

20060141667 - Bare die socket: A socket for removably mounting a bare die to a substrate, such as a printed circuit board. This socket is formed by insert molding signal conductors in an insulative housing. A ground structure is separately provided to control the impedance of the signal conductors and to reduce cross talk. The...

20060141666 - Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby: The present invention relates to a method for producing a module including an integrated circuit die on a substrate. A substrate is provided, a metallization structure is provided which includes a conductive path and a metallization contact pad on the substrate. The integrated circuit die is placed onto the substrate,...

20060141668 - Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the upper and lower substrates are interconnected by wire bonding; and further in which at least one of the packages...

20060141669 - Semiconductor package having semiconductor constructing body and method of manufacturing the same: A semiconductor package includes at least one semiconductor constructing body which has a semiconductor substrate and a plurality of external connection electrodes formed thereon. An insulating film covers the semiconductor constructing body. Each of interconnections which has a projecting electrode is formed on the insulating film. The projecting electrodes of...

20060141670 - Method of forming fine metal pattern and method of forming metal line using the same: There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first interlayer insulating layer is formed. A via plug is formed on the...

20060141671 - Thermal interface structure with integrated liquid cooling and methods: A method and device for thermal conduction is provided. A thermal interface device and method of formation is described that includes advantages such as improved interfacial strength, and improved interfacial contact. Embodiments of thermal conduction structures are shown that provide composite thermal conduction and circulated liquid cooling. Embodiments are further...

20060141673 - Integrated circuit device having reduced bow and method for making same: An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A...

20060141672 - Method for cutting lead terminal of package type electronic component: In an electronic component comprising a semiconductor chip packaged in a molded part from which the lead terminals of the semiconductor chip project, a main cutting notch is formed on the obverse surface of each lead terminal before molding the molded part while leaving unnotched portions adjoining both ends of...

20060141674 - Windowed package having embedded frame: An integrated circuit (IC) package includes a mold compound, a die, and a window. The mold compound has a frame embedded within it. The frame has a top surface, a bottom surface, and a top-to-bottom opening therein. The die is attached to the mold compound, wherein the embedded frame lies...

20060141675 - Method of manufacturing heat spreader having vapor chamber defined therein: A method for manufacturing a vapor chamber-based heat spreader includes the following steps: (1) providing a mold, the mold having a surface; (2) electrodepositing a layer of metal coating on the surface of the mold; (3) removing the mold from the coating layer, wherein the coating layer defines therein a...

20060141676 - Method for producing semiconductor substrate: To provide a method for producing a semiconductor substrate able to uniformly and quickly fill through-holes in the semiconductor substrate with conductive material. This method comprises a process for forming through-holes (14) in a substrate (10), a process for disposing solder (42) on one surface of the substrate, and a...

20060141677 - Method of manufacturing a semiconductor device: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing...

20060141678 - Forming a nanotube switch and structures formed thereby: Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a substrate comprising a power pad, and attaching a nanotube comprising at least one side chain to the power pad....

20060141679 - Vertically stacked field programmable nonvolatile memory and method of fabrication: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum...

20060141680 - Processing a memory link with a set of at least two laser pulses: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within...

20060141681 - Processing a memory link with a set of at least two laser pulses: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within...

20060141682 - Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation: A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure,...

20060141685 - Liquid crystal display device and fabrication method thereof: A method for fabricating a liquid crystal display includes providing a first substrate having a pixel part and a driving circuit part, forming a gate electrode in the pixel part of the first substrate, forming a first insulation film, a first amorphous silicon thin film and a second amorphous silicon...

20060141684 - Polysilicon film, thin film transistor using the same, and method for forming the same: A crystallizing method for forming a poly-Si film is described as follows. First, forming an activated layer on a substrate, and the molecule structure of the activated layer includes carbon, hydrogen, oxygen and silicon. And then, forming an amorphous silicon film on the activated layer. Finally, performing an annealing process...

20060141683 - Production method for thin-film semiconductor: A method of fabricating a thin-film of a semiconductor material includes: a scanning irradiation step of, in order to form a polycrystalline silicon film on the surface of a substrate, focusing first pulse laser light having a visible wavelength into a line shape having an intensity distribution of an approximately...

20060141686 - Copper gate electrode of liquid crystal display device and method of fabricating the same: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (TFT-LCD) device, at least comprises an adhesive layer formed on a glass substrate, and a patterned copper layer formed on the adhesive layer. The adhesive layer at least comprises one of nitrogen and phosphorus (for example, polysilazane) for enhancing...

20060141687 - Methods of forming semiconductor constructions: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of...

20060141688 - Method for producing insulated gate thin film semiconductor device: An amorphous semiconductor film is etched so that a width of a narrowest portion thereof is 100 μm or less, thereby forming island semiconductor regions. By irradiating an intense light such as a laser into the island semiconductor regions, photo-annealing is performed to crystallize it. Then, of end portions (peripheral...

20060141689 - Semiconductor device and method of manufacturing the semiconductor device: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on...

20060141691 - Method for fabricating semiconductor device: A method for fabricating a semiconductor memory device is provided. The method includes: forming a trench in a portion of a substrate, defined as a cell region; forming a first polysilicon layer doped with N-type impurities on regions where N-type metal-oxide-semiconductor (MOS) transistors are to be formed in the cell...

20060141690 - Method for manufacturing a semiconductor device: Provided is a method for manufacturing a semiconductor device comprising forming a device isolation layer on a semiconductor substrate; forming gate insulating layers on the upper part of the semiconductor substrate having the device isolation layers formed thereon; forming an undoped layer for a gate electrode; implanting mixed dopant ions...

20060141692 - Method of fabricating cmos image sensor: A method of fabricating a CMOS image sensor can minimize a dark current by avoiding a dry etch process of a photodiode surface. The method can also reduce a contact resistance and variation of the contact resistance of a read-out circuit unit within a unit pixel. The method includes steps...

20060141694 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same are provided. The method includes: forming a plurality of protruded patterns smaller than gate structures by selectively removing predetermined portions of a substrate; and forming the gate structures over the protruded patterns. The semiconductor device includes: a plurality of protruded...

20060141693 - Semiconductor multilayer interconnection forming method: In a method for forming a wiring using a dual damascene process in which a multilayer wiring structure is formed by embedding a first etching space formed in an interlayer insulating layer and a second etching space which communicates thereto with a conductor material, a number of steps may be...

20060141695 - Methods of forming thin layers including zirconium hafnium oxide and methods of forming gate structures, capacitors, and flash memory devices using the same: Methods of forming a zirconium hafnium oxide thin layer on a semiconductor substrate by supplying tetrakis(ethylmethylamino)zirconium ([Zr{N(C2H5)(CH3)}4], TEMAZ) and tetrakis(ethylmethylamino)hafnium ([Hf{N(C2H5)(CH3)}4], TEMAH) to a substrate are provided. The TEMAZ and the TEMAH may be reacted with an oxidizing agent. The thin layer including zirconium hafnium oxide may be used for...

20060141697 - Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a...

20060141696 - Method for forming landing plug contact in semiconductor device: A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation...

20060141698 - Method of improved high k dielectric - polysilicon interface for cmos devices: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide...

20060141699 - Method for fabricating semiconductor memory device: A method for fabricating a semiconductor memory device is provided. The method includes: forming an inter-layer insulation layer with a storage node contact hole on a substrate; forming storage node contact spacers on sidewalls of the inter-layer insulation layer in the storage node contact hole; forming a storage node contact...

20060141700 - Method for fabricating semiconductor memory device having recessed storage node contact plug: A semiconductor memory device and a method for fabricating a semiconductor memory device are provided. The method includes forming an inter-layer insulation layer having a storage node contact hole on a substrate; forming a pair of storage node contact spacers on sidewalls of the storage node contact hole; forming a...

20060141701 - Semiconductor device having trench capacitors and method for making the trench capacitors: A semiconductor device having a trench capacitor is disclosed. The trench is formed on the surface of a semiconductor substrate. A first insulating film is formed on the side wall of the trench and a semiconductor film is buried in the trench. The first insulating film and the semiconductor film...

20060141704 - Manufacturing method of semiconductor device: A method of manufacturing a semiconductor device including forming a gate oxide layer, a first conductive layer, a capacitor dielectric layer, and a second conductive layer on a semiconductor substrate. The method also includes patterning the first and second conductive layers, the gate oxide layer, and the field oxide layer...

20060141702 - Method for depositing titanium oxide layer and method for fabricating capacitor by using the same: Disclosed are a method for depositing a titanium oxide (TiO2) layer and a method for fabricating a capacitor by using the same. The method for forming the TiO2 layer includes the steps of: a) adsorbing titanium hydride (TiH2) on a wafer loaded into a chamber by supplying TiH2 to the...

20060141703 - Method of manufacturing nonvolatile organic memory device and nonvolatile organic memory device manufactured by the same: A method of manufacturing a nonvolatile organic memory device including a memory layer interposed between an upper electrode layer and a lower electrode layer, which includes dispersing ions of conductive nanoparticles in an organic material disposed between the two electrode layers and then reducing the ions of conductive nanoparticles into...

20060141705 - Method for fabricating metal-insulator-metal capacitor of semiconductor device: A method for fabricating a metal-insulator-metal (MIM) capacitor of a semiconductor device is provided. The method includes simultaneously patterning a lower metal film pattern and a dielectric film pattern to form a first structure in a MIM capacitor region and a second structure in a metal line region, removing the...

20060141706 - Methods of forming non-volatile semiconductor memory devices using prominences and trenches, and devices so formed: A semiconductor substrate is patterned to form a depression and prominence. A floating gate is formed so as to cover at least both sidewalls of the prominence of the depression and prominence, and is then etched to form a trench for a device isolation self-aligned with the floating gate. Related...

20060141707 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device and a method for fabricating a semiconductor memory device are provided. A semiconductor memory device includes a substrate, an inter-layer insulation layer including a storage node contact hole and formed on the substrate, a pair of storage node contact spacers formed on sidewalls of the storage...

20060141708 - Non-volatile memory device with buried control gate and method of fabricating the same: In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a...

20060141709 - Method for programming multi-level nitride read-only memory cells: A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low Vt value. A data region that is to be programmed to a highest Vt value is programmed first. Remaining data regions in the nitride...

20060141710 - Nor-type flash memory device of twin bit cell structure and method of fabricating the same: A NOR-type flash memory device comprises a plurality twin-bit memory cells arranged so that pairs of adjacent memory cells share a source/drain region and groups of four adjacent memory cells are electrically connected to each other by a single bitline contact....

20060141711 - Method of manufacturing flash memory device: The present invention relates to a method of manufacturing flash memory devices. According to the present invention, an inter-gate insulating film formed between a floating gate and a control gate is formed to have an NONON structure, thus removing the interface of polysilicon and an oxide film. It is thus...

20060141712 - Method for manufacturing pmosfet: A method for manufacturing a PMOSFET uses a trench-type gate structure only in a PMOSFET region of a peripheral circuit, except for a cell, to overcome the shortcomings of a MOSFET caused by reduction in design rule, realize stable threshold voltage, and improve the characteristics and reliability of a PMOSFET...

20060141713 - Manufacturing method with self-aligned arrangement of solid body electrolyte memory cells of minimum structure size: The object of providing a method for manufacturing solid body electrolyte memory cells or CB memory cells, respectively, which is suited for the simplified manufacturing of highly dense arrays with crosspoint architecture is solved by the present invention in that the solid body electrolyte memory cells are manufactured by self-aligned...

20060141714 - Method for manufacturing a semiconductor device: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, in a semiconductor substrate; simultaneously forming a...

20060141715 - Integrated circuit devices having contact holes exposing gate electrodes in active regions and methods of fabricating the same: Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion...

20060141716 - Method for manufacturing a cell transistor of a semiconductor memory device: Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device. The method comprises the steps of: forming device isolation films and a well on a semiconductor substrate; forming a threshold voltage adjust region by ion-implanting a first conductive impurity dopant into the well of the semiconductor...

20060141717 - Method of forming isolation film in semiconductor device: The present invention relates to a method of forming isolation films of a semiconductor device. According to the present invention, an oxidization process is performed to oxidize inner walls of trenches in a pre-heating period where temperature is raised in order to deposit an insulating material within a chamber so...

20060141718 - Method of manufacturing flash memory device: The present invention relates to a method of manufacturing a flash memory device. According to the method of manufacturing the flash memory device, a gate line is formed to have a structure in which a tunnel oxide film, a polysilicon layer for floating gate, dielectric films and a polysilicon layer...

20060141720 - Method of fabricating mos transistor: A method for fabricating a MOS transistor is suitable for modifying the configuration of a gate electrode. The method includes coating a first oxide layer on a semiconductor substrate and removing a predetermined width of the first oxide layer; forming an LDD region in the substrate; forming a gate spacer...

20060141719 - Method of fabricating semiconductor device: A gate is formed on a predetermined area of a substrate. A spacer insulating layer is formed on sidewalls of the gate. An insulating interlayer is formed over the substrate including the gate and the spacer insulating layer. Polymer generation is simultaneously carried out on a lateral side of the...

20060141722 - Method of sequentially forming silicide layer and contact barrier in semiconductor integrated circuit device: A method of sequentially forming a silicide layer and a contact barrier in a semiconductor device is provided. In the method, a pre-metal dielectric layer is deposited over an underlying structure that has a silicon substrate, a gate electrode on the substrate, and source/drain regions in the substrate. Contact holes...

20060141721 - Semiconductor transistor device and method for manufacturing the same: A semiconductor transistor device and a method for manufacturing the same are provided. The method includes forming a silicon epitaxial layer having a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate and forming a source and drain junction by ion implantation and rapid annealing in...

20060141723 - Method for manufacturing semiconductor device: A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor...

20060141726 - Field effect transistor with a high breakdown voltage and method of manufacturing the same: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer...

20060141725 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device wherein before an insulating film spacer of a contact region is removed after a gate line and source/drain are formed, a high quality buffer oxide film formed between the gate line and the insulating film spacer is made dense by means of...

20060141724 - Method of manufacturing mos transistor: A method of manufacturing a MOS transistor capable of suppressing a short channel effect by suppressing boron (B) ion diffusion in the MOS transistor. The method includes steps of: forming an impurity diffusion suppressing layer in an active region of a semiconductor substrate; forming an impurity layer containing boron ions...

20060141727 - Method of fabricating low-power cmos device: A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The method includes forming a shallow trench in a...

20060141728 - Formation of junctions and silicides with reduced thermal budget: Method of formation of a metal-silicide layer (12, 13, 14, 18, 19) an a semiconductor substrate (1), the semiconductor substrate (1) including at least a dopant region (5); the dopant region (5) including an ultra-shallow junction region; the method including as a first step at least one impurity implantation process...

20060141729 - System and method for suppressing oxide formation: A system and method for suppressing sub-oxide formation during the manufacturing of semiconductor devices (such as MOSFET transistor) with high-k gate dielectric is disclosed. In one example, the MOSFET transistor includes a gate structure including a high-k gate dielectric and a gate electrode. In this example, the gate structure is...

20060141730 - Process for manufacturing integrated resistive elements with silicidation protection: In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a predetermined resistivity is then formed in the active area (15). Prior to forming the resistive...

20060141731 - Method for forming shallow trench isolation in semiconductor device: A method for forming shallow trench isolation in a semiconductor device. The method includes forming a pad oxide and a pad nitride on a semiconductor substrate in successive order, forming a trench in the substrate by etching the pad nitride, the pad oxide and the substrate, removing a portion of...

20060141732 - Method for forming isolation region in semiconductor device: A method for forming an isolation region in a semiconductor device such as a photodiode forms depletion layers at boundary regions between N-type regions of the photodiode and an ion injection layer in which P-type impurity ions are injected. Depletion layers are also formed between the N-type regions of the...

20060141733 - Capacitors having a horizontally folded dielectric layer and methods for manufacturing the same: Capacitors having a horizontally folded dielectric layer and methods of manufacturing is the same are provided. An example method for manufacturing a capacitor includes forming a first insulating layer pattern above a substrate, forming a first silicon epitaxial growth layer above a region of the silicon substrate exposed by the...

20060141734 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided, wherein a large MIM capacitor including an uneven surface if formed to increase capacitance. The method includes forming a polysilicon layer on a lower metal layer by plasma-enhanced chemical vapor deposition; forming an uneven surface in the polysilicon layer by etching...

20060141735 - Method for forming a mim capacitor in a semiconductor device: In a method of forming a metal-insulator-metal (MIM) capacitor in a semiconductor device, after forming a capacitor insulation layer on a lower metal layer of the MIM capacitor, an upper electrode is formed by ion implantation into the capacitor insulation layer and silicidation, without a typical reactive ion etching process....

20060141736 - Method for fabricating capacitor of semiconductor memory device using amorphous carbon: A method for fabricating a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming storage node contact plugs penetrating into the inter-layer insulation layer; forming a stack structure formed by stacking a first protective barrier layer and a sacrificial layer on the inter-layer...

20060141738 - Method for measuring bonding quality of bonded substrates, metrology apparatus, and method of producing a device from a bonded substrate: In a method for measuring the bonding quality of bonded substrates, such as bonded SOI wafers, a plurality of marks are created at a first side of a top substrate after, or before, the bonding of the top substrate onto a bottom substrate. Then, the positions of the plurality of...

20060141737 - Planar magnetic tunnel junction substrate having recessed alignment marks: A method for forming an alignment mark structure for a semiconductor device includes forming an alignment recess at a selected level of the semiconductor device substrate. A first metal layer is formed over the selected substrate level and within the alignment recess, wherein the alignment recess is formed at a...

20060141741 - Adjuvant for chemical mechanical polishing slurry: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms a adsorption layer on the cationically charged material in order to increase the polishing selectivity of the anionically charged material to cationically charged material, wherein the adjuvant comprises a...

20060141739 - Method for fabricating contact holes in a semiconductor body and a semiconductor structure: A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa regions are provided in the semiconductor body, and electrodes are provided in the trenches, which electrodes are electrically insulated from the semiconductor body by...

20060141740 - Semiconductor device with shallow trench isolation and a manufacturing method thereof: An exemplary method of manufacturing a shallow trench isolation structure in a semiconductor device includes forming a first trench region by etching the semiconductor substrate to a predetermined depth, forming a first oxide layer on the entire surface of the semiconductor substrate so as to fill the first trench region,...

20060141749 - Adhesive of folder package: A package includes a flexible substrate with a first region and a second region, an encapsulated die supported by the first region, and a conformable fold adhesive introduced between the encapsulated die and the flexible substrate. The second region of the flexible substrate is folded over the surface of the...

20060141747 - Controlled cleaving process: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define...

20060141743 - Method and system for 3d alignment in wafer scale integration: A substrate bonding system has a first and a second substrate table for holding a first substrate and a second substrate, respectively, and a controller. The first substrate includes a first device having first contact pads and the second substrate a second device having second contact pads. The wafer bonding...

20060141745 - Method and system for wafer bonding of structured substrates for electro-mechanical devices: A method for forming a composite substrate structure. The method includes providing a first substrate, the first substrate having a surface region and a backside region, providing a handling substrate, the handling substrate having a bonding surface and a handling surface, and activating at least one of the surface region...

20060141742 - Method of producing a complex structure by assembling stressed structures: The invention relates to a method of producing a complex microelectronic structure, in which two basic microelectronic structures (1, 3) are assembled at the two respective connecting faces (3) thereof. The invention is characterised in that, before assembly, a difference is created in the tangential stress state between the two...

20060141746 - Methods for forming semiconductor structures: The invention concerns a method of treating one or both bonding surfaces of first and second substrates and in particular, the surfaces of donor and receiver wafers that are intended to be bonded together. A simultaneous cleaning and activation step is carried out immediately prior to bonding the wafers together,...

20060141744 - System and method of forming a bonded substrate and a bonded substrate product: The invention provides a method of forming a bonded substrate that includes providing a first substrate having a first substrate shape and at least one first alignment mark positioned at a first surface side. A second substrate is providing having a second substrate shape. The second substrate is oriented relative...

20060141748 - Thermal treament of a semiconductor layer: A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer...

20060141750 - Semiconductor integrated device and method for manufacturing same: A method for manufacturing a semiconductor integrated device includes steps of forming an integrated circuit element on a semiconductor substrate, forming internal wiring, forming a groove along a scribe line on a back surface of the semiconductor substrate to expose a portion of the internal wiring, forming a metal film...

20060141751 - Method for making a silicon dioxide layer on a silicon substrate by anodic oxidation: A method for forming silicon dioxide layer on a silicon substrate by anodic oxidation includes: providing a silicon substrate which has a polished face; providing an anodic oxidation apparatus which is filled with an electrolyte; providing a platinum piece and placing the platinum piece in the electrolyte as a cathode;...

20060141753 - Epitaxial structure of gallium nitride series semiconductor device and process of manufacturing the same: An epitaxial stricture of a gallium nitride series semiconductor device and a process of forming the same are described. A first buffer layer of gallium nitride is epitaxially formed on a substrate at a first temperature. A second buffer layer of indium gallium nitride is formed on the first buffer...

20060141752 - Methods for forming a p-type polysilicon layer in a semiconductor device: A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and thereafter forming a P-type polysilicon layer by thermally diffusing the plurality...

20060141754 - Laser treatment apparatus, laser treatment method, and manufacturing method of semiconductor device: The invention relates to a laser treatment apparatus including a laser oscillator, an interlock provided in the laser oscillator, a movable table which moves with a certain movement period, a timer, an interlock provided in the timer, a sensor which can detect movement of the movable table, and a computer,...

20060141755 - Method of configuring a process to obtain a thin layer with a low density of holes: A method for configuring a process for treating a semiconductor wafer. A minimum layer thickness of a transferred layer to be provided is determined to obtain a processed layer that has a preselected target thickness and target maximum density of through holes that extend completely therethrough, by conducting a predetermined...

20060141756 - Method for producing a semiconductor structure: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a...

20060141757 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. The method includes the steps of preparing a semiconductor substrate, forming a buffer oxide layer, forming a hard mask layer on the buffer oxide layer, etching an exposed portion of the buffer oxide layer by using the hard mask layer, etching...

20060141758 - Method of forming contact pads: In a method of forming a semiconductor structure, a substrate comprising at least one contact pad is provided. A passivation layer is formed over the substrate. A mask which does not cover a portion of the passivation layer located over the at least one contact pad is formed over the...

20060141759 - Method of forming pad and fuse in semiconductor device: A method of forming a pad and a fuse in a semiconductor device. A copper layer located in both a fuse region and a pad region is formed in a dielectric layer. A first insulating layer is formed on the dielectric layer to cover the copper layer and selectively etched...

20060141760 - Method for producing an electrical component: To expose a submerged bondable terminal pad in a component that includes at least two substrates which are joined with each other, it is proposed that grooves of relatively shallow depth be provided on the connecting surface of the second substrate before the two substrates are joined. After the two...

20060141762 - Interlocking via for package via integrity: A method of forming an interconnection structure in a microelectronic package, and an interconnection structure of a microelectronic package formed according to the method. The method includes: providing a combination including a first conductive layer and a dielectric layer fixed to the conductive layer; providing a hole through the dielectric...

20060141765 - Metal wiring pattern for memory devices: A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on...

20060141764 - Method of manufacturing wiring board: A method of manufacturing a wiring board is disclosed. The wiring board has: a capacitor, having multiple electrode layers which oppose each other with a dielectric layer in between, that is connected to a semiconductor chip; one or more via wirings which pierce the electrode layers and which are connected...

20060141761 - System for and method of forming via holes by multiple deposition events in a continuous inline shadow mask deposition process: Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its...

20060141763 - System for and method of planarizing the contact region of a via by use of a continuous inline vacuum deposition: A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316)...

20060141767 - Metal wiring for semiconductor device and method for forming the same: A metal wiring for a semiconductor device and a method for forming the same are provided. The metal wiring includes a first insulating layer and a second insulating layer; an interlayer insulating film formed between the first and second insulating layers, wherein the interlayer insulating film is provided with holes...

20060141766 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device in which an etching process for forming a M1 trench for a bit line is stopped on a nitride etch-stop film and the bit line is formed on the nitride film....

20060141769 - Method for forming metal line of semiconductor device: A method for forming a metal line of a semiconductor device is provided, in which a Cu residue and a mixture of different materials generated after a planarization process are completely removed to improve reliability of the metal line. The method includes removing copper residue on a semiconductor substrate by...

20060141768 - Method to eliminate plating copper defect: A method of forming a metal layer with reduced defects comprising providing a structure having a dielectric layer formed over it, forming a dielectric layer having an opening, lining the opening with a metal seed layer, treating the metal seed layer with a cleaning process to remove contaminates from it,...

20060141770 - Method for fabricating storage node contact in semiconductor device: Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused during a storage node contact isolation process. In accordance with the present invention, a chemical mechanical polishing (CMP) process that...

20060141771 - Semiconductor device with a metal line and method of forming the same: A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on the planarized substrate. The method further includes depositing a...

20060141773 - Method of forming metal line in semiconductor device: A method of forming a metal line in a semiconductor device reduces production costs through a simplified fabricating process. The method includes steps of forming a first metal line on a semiconductor substrate; forming an insulating layer over the semiconductor substrate including the first metal line; coating a photoresist on...

20060141772 - Methods of forming interconnection lines in semiconductor devices: The present disclosure improves characteristics and reliability of a device by preventing seams within a copper layer, wherein seams are created when forming a copper line by a damascene process. Such seams created within a first and a second copper layer are prevented by a process in which the first...

20060141774 - Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure: A mask pattern (110) of a pattern transfer mask (101) includes a light shielding pattern (111) and a light transmitting pattern (112). The light shielding pattern (111) has a shape (pattern) subjected to undersizing near portions corresponding to via holes (51H). It is desirable to make undersizing to a greater...

20060141778 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a...

20060141775 - Method of forming electrical connections in a semiconductor structure: A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a material formed on a first surface of the substrate. At least one recess is formed in the layer of material. The formation of the at least one recess comprises performing a dry etching process....

20060141776 - Method of manufacturing a semiconductor device: Electrical characteristics of a semiconductor device may be enhanced by completely removing a residue such as a polymer formed in a trench when the semiconductor device is manufactured by a method including: forming a via hole and a trench on a semiconductor substrate by an etching process; coating a photoresist...

20060141777 - Methods for patterning a layer of a semiconductor device: A patterning layer of a single or multiple layer structure formed on a lower layer may be etched to form one or more steps therein, when the patterning layer is first dry etched to a partial depth thereof using a first resist pattern and then the patterning layer is etched...

20060141779 - Method for forming an aluminum contact: A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes forming a photoresist pattern for ion...

20060141780 - Methods for the plasma formation of a microelectronic barrier layer: The fabrication of an interconnect for a microelectronic device through the use of a nitrogen plasma to form a barrier layer. In one embodiment, an opening is formed in a dielectric layer and a metal layer is formed on the sidewalls and bottom of the opening. The metal layer, such...

20060141781 - Method for forming metal line of semiconductor device: A method for forming a metal line of a semiconductor device forms an aluminum line having an excellent orientation. A specific resistance of a metal line is reduced, thereby enabling sufficient supply of a desired electric current. The method includes steps of forming a lower reflection preventing layer on a...

20060141782 - Film forming method, film forming system and recording medium: A wafer boat 25 holding a plurality of wafers W is loaded into a reaction vessel 2, and the wafers W are processed by a film forming process specified by a film forming recipe 1 specifying, for example, Si2Cl2 gas and NH3 gas as film forming gases. Subsequently, a purging...

20060141783 - Sputtering apparatus and method for forming metal silicide layer using the same: A sputtering apparatus for forming a low-resistance uniform metal silicide layer without additional heat treatment and a metal silicide layer forming method using the same are provided. The sputtering apparatus includes a sputtering chamber; a gas introduction port formed at an upper location of a lateral wall of the sputtering...

20060141784 - Copper electrodeposition in microelectronics: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu...

20060141785 - Inter-metal dielectric of semiconductor device and manufacturing method thereof: An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper line layer therein, forming a plasma enhanced fluorosilicate glass (PEFSG) layer...

20060141787 - Cleaning methods for silicon electrode assembly surface contamination removal: Silicon electrode assembly decontamination cleaning methods and solutions, which control or eliminate possible chemical attacks of electrode assembly bonding materials, comprise ammonium fluoride, hydrogen peroxide, acetic acid, optionally ammonium acetate, and deionized water....

20060141789 - Method for etching and for forming a contact hole using thereof: A method for forming a structure formed by etching which is typified by a contact hole in the semiconductor and a method for manufacturing a display device using the structure. The etching method includes at least, forming an organic mask having a first opening portion and a second opening portion...

20060141788 - Method for fabricating semiconductor device capable of preventing scratch: Disclosed is a method for fabricating a semiconductor device capable of preventing scratches. The method includes the steps of: forming a substrate divided into a peripheral region and a cell region where a capacitor including a metal plate electrode on which particles with a pointed shape are generated is formed;...

20060141786 - Method of manufacturing an electronic device and electronic device: A method of manufacturing an electronic device, particularly an acceleration sensor, comprising providing a wafer (10) having first and second semiconductor layers (12, 16) with a buried oxide layer (14) therebetween and forming a semiconductor device (such as a detection circuit) on one side of the wafer (10) in the...

20060141790 - Chemical mechanical polishing method: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer...

20060141791 - Method for fabricating a semiconductor device: The method includes chemical-mechanical polishing to planarize an insulating interlayer deposited on a lower pattern. The insulating interlayer is polished using a surfactant. The chemical-mechanical polishing includes at least two separate polishing steps of different fluxes of the surfactant. The first polishing step is performed for touching up an upper...

20060141792 - Process for manufacturing semiconductor integrated circuit device: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP). method, a process for manufacturing. a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main...

20060141793 - Forming of trenches or wells having different destinations in a semiconductor substrate: A method for forming, in a semiconductor substrate, wells and/or trenches having different destinations, including the steps of at least partly simultaneously etching cavities according to the pattern of the trenches and/or wells; closing the openings of the cavities with at least one first non-conformal thick layer, and selectively opening...

20060141795 - Method for fabrication semiconductor device: The object of this invention is to provide a method for fabricating a semiconductor device in which the yield and productivity are improved. In the method for fabricating a semiconductor device according to the invention, a plasma etching system is prepared which includes a vacuum chamber 1, a susceptor 7...

20060141796 - Method of manufacturing semiconductor device: The method includes forming an isolation film on a silicon substrate to define an active region; forming an antireflective film on an entire surface of the substrate containing the isolation film; forming a photosensitive film pattern on the antireflective film while exposing a portion of the isolation film or the...

20060141794 - Plasma system and method for anisotropically etching structures into a substrate: A method and a plasma system are provided for anisotropically etching structures into a substrate positioned in an etching chamber, e.g., structures defined using an etching mask in a silicon substrate, using a plasma. For this purpose, the etching chamber is supplied at least intermittently with an etching gas and...

20060141797 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device is provided. The method includes: forming device isolation layers on a substrate; sequentially forming an anti-reflective coating layer and a photoresist layer on the substrate; patterning the anti-reflective coating layer and the photoresist layer to expose substrate regions in which active regions of...

20060141798 - Device and method of performing a seasoning process for a semiconductor device manufacturing apparatus: A method of performing a seasoning process for a semiconductor device processing apparatus is provided by the present invention. The method includes: forming a material layer on a test wafer; coating a photoresist on the material layer; patterning the photoresist so as to expose a central region of the wafer...

20060141799 - Method of manufacturing a semiconductor device: A semiconductor device may be manufactured by employing an ashing process for removing a photoresist in a process chamber, wherein the ashing process comprises: removing the photoresist for a first predetermined process time by flowing one or more oxygen and nitrogen source gases into the process chamber at first predetermined...

20060141800 - Method for forming step channel of semiconductor device: A method for forming a step channel of a semiconductor device is disclosed. The method for forming a step channel of a semiconductor device comprises forming a hard mask layer pattern defining a step channel region on a semiconductor substrate, forming a spacer on a sidewall of the hard mask...

20060141801 - Semiconductor device manufacturing method, wafer, and wafer manufacturing method: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with...

20060141802 - Silicon electrode assembly surface decontamination by acidic solution: Methods for cleaning silicon surfaces of electrode assemblies by efficiently removing contaminants from the silicon surfaces without discoloring the silicon surfaces using an acidic solution comprising hydrofluoric acid, nitric acid, acetic acid, and balance deionized water....

20060141803 - Method of cleaning silicon nitride layer: A method of cleaning a silicon nitride layer on a substrate is provided to effectively remove negative-charged impurities such as polymer and particle from the silicon nitride layer. In the method, the zeta potential of the silicon nitride layer is changed from positive to negative, and then the silicon nitride...

20060141804 - Method and apparatus to facilitate electrostatic discharge resiliency: A circuit element (such as an asperity sensor circuit (11)) as is formed (21) using semiconductor fabrication processing has a high resistance layer formed (22) thereover. The high resistance layer is preferably formed using semiconductor fabrication processing. The high resistance layer can be comprised of a variety of materials and...

20060141805 - Method of depositing dielectric films: A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer...

20060141806 - Apparatus and process for treating dielectric materials: Apparatuses and processes for treating dielectric materials such as low k dielectric materials, premetal dielectric materials, barrier layers, and the like, generally comprise a radiation source module, a process chamber module coupled to the radiation source module; and a loadlock chamber module in operative communication with the process chamber and...

20060141807 - Seal hardening furnace of liquid crystal display device having rack bar: A seal hardening furnace is presented in which seal lines in a liquid crystal display panel are hardened. The seal hardening furnace includes a cassette having a rack bar structure. The rack bar structure has rack bars for supporting the substrate along one direction and rack bar supports at ends...

20060141808 - Method for the heat treatment of substrates: A substrate undergoes a semiconductor fabrication process at different temperatures in a reactor without changing the temperature of the reactor. The substrate is held suspended by flowing gas between two heated surfaces of the reactor. Moving the two heated surfaces in close proximity with the substrate for a particular time...

20060141809 - Single side workpiece processing: A centrifugal workpiece processor for processing semiconductor wafers and similar workpieces includes a head which holds and spins the workpiece. The head includes a rotor having a gas system. Gas is sprayed or jetted from inlets in the rotor to create a rotational gas flow. The rotational gas flow causes...

20060134807 - Method of manufacturing solid image pickup apparatus: A first gate electrode and a second gate electrode are formed on a semiconductor substrate, and then a resist pattern is formed so as to selectively leave open a portion including an overlap between the first and second gate electrodes. Next, the overlap between the gate electrodes is removed through...

20060134809 - Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step: An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250′, and a ferromagnetic top plate 20a. Also, a method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil...

20060134808 - Ferroelectric capacitor stack etch cleaning methods: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define...

20060134810 - Apparatus and method for voltage contrast analysis of a wafer using a titled pre-charging beam: A method for electrically testing a wafer that includes: receiving a wafer having a first layer that is at least partly conductive and a second layer formed over the first layer, following production of openings in the second layer; directing towards the wafer a first set of beams of charged...

20060134811 - Semiconductor processing apparatus and method: A semiconductor processing apparatus includes a process chamber to accommodate a target substrate, a gas supply system to supply a process gas into the process chamber, an exhaust unit to exhaust the process chamber, and an exhaust line connecting the process chamber to the exhaust unit. An opening variable valve...

20060134812 - Inspection methods for a semiconductor device: An inspection method for a semiconductor device is disclosed. The method includes providing a semiconductor device, performing heat treatment on the semiconductor device, and inspecting the semiconductor device utilizing electron beam to acquire an analysis image. The semiconductor device comprises a substrate, a plurality of gate electrodes protruding on the...

20060134813 - Organic light-emitting panel, package process for organic light-emitting panel and coating apparatus thereof: An organic light-emitting panel, a process for packaging an organic light-emitting panel and a coating apparatus applied thereto are described. A patterned desiccant with large surface area is formed on a cover plate by an ink-jet printing process. The process for packaging an organic light-emitting panel and the coating process...

20060134814 - Self-alignment manufacturing method of the microlens and the aperture using in optical devices: The present invention discloses a self-alignment manufacturing method of a microlens and an aperture using in an optical device. The method manufactures the aperture and the circular opening in the opaque film on a transparent substrate, and utilizes the self-alignment backside exposure technology to precisely integrate the aperture and the...

20060134815 - Method of producing a diffraction grating: In an embodiment, a method of producing a diffraction grating comprises steps of: forming, on a man surface of a first member, a first mask having a plurality of resist patterns arranged at a Bragg diffraction period; etching the first member by use of the first mask, thereby providing the...

20060134816 - Semiconductor laser device of iii-v group compound and fabrication method therefor: A semiconductor laser device of a III-V group compound includes a substrate including a main surface having an inclination angle of less than 20° toward a [011] direction from a (100) plane and an inclined facet further inclined toward the [011] direction from the main surface, a light emitting stacked-layered...

20060134817 - Vertical-cavity surface-emission type laser diode and fabrication process thereof: A vertical-cavity, surface-emission-type laser diode includes an optical cavity formed of an active region sandwiched by upper and lower reflectors, wherein the lower reflector is formed of a distributed Bragg reflector and a non-optical recombination elimination layer is provided between an active layer in the active region and the lower...

20060134818 - Method for fabricating micro-mechanical devices: A method of fabricating micro-mechanical devices. A mesa is etched in a homogeneous wafer. The wafer is bonded to a patterned substrate with the mesa defining device elements suspended above the substrate. A portion of the wafer is removed until a desired device thickness is achieved. Discrete elements of the...

20060134819 - Process for forming mems: The present invention relates to a process for forming microstructures on a substrate. A plating surface is applied to a substrate. A first layer of photoresist is applied on top of the plating base. The first layer of photoresist is exposed to radiation in a pattern to render the first...

20060134820 - Process for forming microstructures: The present invention relates to a process for forming microstructures on a substrate. A plating surface is applied to a substrate. A first layer of photoresist is applied on top of the plating base. The first layer of photoresist is exposed to radiation in a pattern to render the first...

20060134821 - Manufacturing method of a microelectromechanical switch: The method for manufacturing a micromechanical switch includes manufacturing a hanging bar, on a first semiconductor substrate, equipped at an end thereof with a contact electrode, and a frame projecting from the first semiconductor substrate. A second semiconductor substrate with conductive tracks includes a second input/output electrode and a third...

20060134823 - N,n'-di(phenylalky)-substituted perylene-based tetracarboxylic diimide compounds as n-type semiconductor materials for thin film transistors: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide 3,4,9,10-perylene-based compound having, attached to each of the imide nitrogen atoms a substituted or unsubsitituted phenylalkyl group. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said...

20060134824 - P-type ofet with fluorinated channels: The present invention provides an organic field-effect transistor (OFET) and a method of fabricating the OFET. The OFET, configured to function as a p-type semiconductor, includes a substrate having a top surface and a semiconductor layer located over the top surface. The semiconductor layer comprises organic semiconductor molecules. Each of...

20060134822 - Vertical interconnect for organic electronic devices: A device includes a plurality of organic electronic devices disposed on a substrate, wherein each of the organic electronic devices comprises a first electrode and a second electrode. Furthermore, the device includes an organic layer disposed between the first and second electrodes of each of the plurality of organic electronic...

20060134825 - Injection-molded package for mems inertial sensor: Methods of packaging devices such as MEMS devices are disclosed. An illustrative method of packaging a device in accordance with an illustrative embodiment of the present invention can include the steps of providing a substrate having an device provided therein or thereon, attaching a cap to the substrate and sealing...

20060134826 - Methods of forming semiconductor packages: The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circuit traces and also contacting the die. The invention also includes methods...

20060134827 - Microlenses including a plurality of mutually adhered layers of optically transmissive material and systems including the same: Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material. Systems include at least one microprocessor, a substrate including an array of microlenses formed thereon in electrical communication with the at least one microprocessor. At least one...

20060134828 - Package that integrates passive and active devices with or without a lead frame: According to an embodiment of the invention, a component package comprises a plurality of components and mold compound. The plurality of components are disposed on a zero plane of a removable substrate. The removal substrate is operable to hold the plurality of components in position. At least one of the...

20060134831 - Integrated circuit packaging using electrochemically fabricated structures: Embodiments of the invention provide methods for packaging integrated circuits and/or other electronic components with electrochemically fabricated structures which include conductive interconnection elements. In some embodiments the electrochemically produced structures are fabricated on substrates that include conductive vias while in other embodiments, the substrates are solid blocks of conductive material,...

20060134832 - Manufacturing method of semiconductor device: The manufacturing method of the semiconductor device of the present invention has a step forming solder balls on the circuit face of a mother chip, a step making flip chip bonding of the daughter chip after the step forming solder balls on the circuit face of the mother chip, and...

20060134830 - Method and system for performing die attach using a flame: Embodiments of a method for attaching a die to a substrate using a flame or other heat source are disclosed. The flame may be produced by combustible gas. Also disclosed are embodiments of a system for performing die attach using a flame. Other embodiments are described and claimed....

20060134833 - Packaged semiconductor die and manufacturing method thereof: Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the...

20060134834 - Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and saw device: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in...

20060134829 - Wafer scale integration of electroplate 3d structures using successive lithography, electroplated sacrifical layers, and flip-chip bonding: Wafer scale fabrication of three dimentional substantially enclosed structures on a MEMS/IC die use a combination of electrodeposition of structural and sacrificial layers and flip-chip alignment and bonding technology. A first wafer contains a die with MEMS and/or IC structures. On this MEMS/IC processed die, a first three dimensional structural...

20060134835 - Method for making a neo-layer comprising embedded discrete components: A stackable neo-layer comprising one or more embedded discrete electrical components is provided. A plurality of conductive traces, some of which terminate at a peripheral edge of the layer, are formed on sacrificial substrate in a series of process steps and discrete electrical components such as thick film components or...

20060134836 - Method of marking a low profile packaged semiconductor device: A semiconductor device (10) is made by mounting the bottom surfaces (31, 44, 54) of a semiconductor die (14) and a lead (15, 17) on a tape (12) and over a hole (19) in the tape. A vacuum is drawn through the hole to secure the die in place when...

20060134837 - Vertically stacked field programmable nonvolatile memory and method of fabrication: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum...

20060134839 - Low voltage non-volatile memory transistor: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor...

20060134838 - Processing a memory link with a set of at least two laser pulses: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within...

20060134840 - Electro-optical device and semiconductor circuit: A high performance circuit is formed by using a TFT with less fluctuation in characteristics, and a semiconductor device including such a circuit is formed. When the TFT is formed, first, a base film and a semiconductor film are continuously formed on a quartz substrate without exposing to the air....

20060134841 - Method of forming pattern having step difference and method of making thin film transistor and liquid crystal display using the same: A method of forming a pattern having a step difference and a method of making a thin film transistor and an LCD device using the method of forming the pattern. The method of forming a pattern having a step difference includes forming a first pattern having a predetermined shape in...

20060134842 - Method of fabricating gates: A method of fabricating gates is provided. A first sacrificial layer having a first and a second gate openings therein is formed on a substrate. Next, a gate dielectric layer is formed on the substrate exposed by the first sacrificial layer. Thereafter, a second sacrificial layer is filled in the...

20060134843 - Mos transistor on an soi substrate with a body contact and a gate insulating film with variable thickness: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate...

20060134844 - Method for fabricating dual work function metal gates: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming...

20060134845 - Low-voltage, multiple thin-gate oxide and low-resistance gate electrode: A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in...

20060134846 - Method of fabricating a semiconductor structure: A method of fabricating a semiconductor structure is disclosed. The method comprises the steps of: providing an intermediate structure, the intermediate structure comprising a substrate having an insulating layer thereon and an overlying gate structure; depositing an oxidation barrier layer on the intermediate structure; and exposing the oxidation barrier layer...

20060134847 - Method of manufacturing a sic vertical mosfet: A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that...

20060134848 - Method of manufacturing a semiconductor device with mos transistors comprising gate electrodes formed in a packet of metal layers deposited upon one another: Method of manufacturing a semiconductor device comprising MOS transistors having gate electrodes (15, 16) formed in a number of metal layers (8, 9, 13; 8, 12, 13) deposited upon one another. In this method, active silicon regions (4, 5) provided with a layer of a gate dielectric (7) and field-isolation...

20060134849 - Methods of manufacturing a thin film including zirconium titanium oxide and methods of manufacturing a gate structure, a capacitor and a flash memory device including the same: A method of forming a thin film including zirconium titanium oxide including introducing a reactant including a mixture of a zirconium precursor and a titanium precursor onto a substrate, and introducing an oxidizing agent onto the substrate to form a solid material including zirconium titanium oxide on the substrate is...

20060134850 - Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously: A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface...

20060134851 - Method of forming a semiconductor laser chip having a marker: A method of manufacturing a semiconductor laser chip has following steps. First, a semiconductor substrate including an active layer and a block layer is provided. An electrode line pattern and a marker are formed on the semiconductor substrate. The semiconductor substrate is etched to form a W channel. Then, an...

20060134852 - Interconnect and head gimbal assembly with the same: An interconnect for connecting a magnetic head slider and a flexible printed circuit, and a head gimbal assembly having the interconnect are provided. The interconnect includes a ground layer, a first insulation layer formed on the ground layer, and a pair of signal transferring layers formed on the first insulation...

20060134853 - Standard cell back bias architecture: An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with...

20060134854 - Capacitor of semiconductor device and method for forming the same: In a method for forming a capacitor for use in a semiconductor device, a nitride film for stopping etching, a first mold oxide film, an insulating film, deposited on a substrate are etched to expose the respective storage node contacts and thereby to form a plurality of contact holes arrayed...

20060134855 - Method for fabricating capacitor of semiconductor device: A method for forming a capacitor of a semiconductor device includes forming a first insulation layer having a storage node plug on a semiconductor substrate; forming an etch stop layer and a second insulation layer sequentially on the substrate having the first insulation layer; forming a hole exposing a portion...

20060134856 - Method for manufacturing capacitor of semiconductor element: A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace...

20060134857 - Memory device and fabrication thereof: A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface...

20060134858 - Method of manufacturing semiconductor device: A silicon nitride film is formed on a P-type silicon substrate; an opening of a predetermined pattern is formed in the silicon nitride film; a gate trench is formed on the semiconductor substrate using a silicon nitride film as a mask; and then a polycrystalline silicon film is embedded inside...

20060134859 - Mask for forming landing plug contact hole and plug forming method using the same: Disclosed herein are a mask for forming a landing plug contact hole to vertically expose an active region of a semiconductor substrate to a bit line or storage node contact, and a plug forming method using the same. Through the use of the crescent-shaped masks, it is possible to increase...

20060134861 - Semiconductor memory device and method for fabricating the same: The present invention relates to a semiconductor memory device and a method for fabricating the same. Particularly, the semiconductor memory device includes at least more than two capacitors to decrease the thickness of an insulation layer and increase the size of each capacitor, wherein the thickness of the insulation layer...

20060134860 - Semiconductor processing methods: Semiconductor processing methods are described which can be used to reduce the chances of an inadvertent contamination during processing. In one implementation, a semiconductor wafer backside is mechanically scrubbed to remove an undesired material prior to forming a final passivation layer over an oppositely facing semiconductor wafer frontside. In another...

20060134862 - Cmos nvm bitcell and integrated circuit: A non-volatile memory bitcell structure is disclosed that includes a dual capacitor structure. A first metal-insulator-metal (MIM) capacitor having a first capacitance value includes a first top plate, a first bottom plate, and a first dielectric disposed in-between the first top plate and the first bottom plate. A second metal-insulator-metal...

20060134865 - Method of manufacturing a semiconductor device: According to the present invention, a method of manufacturing a semiconductor device which comprises a matrix of memory cells of the floating gate type is provided in which the silicon nitride layer is deposited as an etching stop layer on a control gate electrode for bottom borderless contact process with...

20060134863 - Methods for reducing wordline sheet resistance: The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A second poly-Si portion is deposited using a second precursor gas flow rate, where the...

20060134864 - Multi-thickness dielectric for semiconductor memory: A process provides a gate dielectric layer of a first thickness for a memory array and for certain peripheral circuits on the same substrate as the memory array. High-voltage peripheral circuits are provided with a gate dielectric layer of a second thickness. Low-voltage peripheral circuits are provided with a gate...

20060134866 - Non-volatile memory and method for fabricating the same: A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive...

20060134867 - Technique for forming the deep doped columns in superjunction: A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench...

20060134868 - Double gate field effect transistor and method of manufacturing the same: Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming...

20060134869 - Systems and methods for rectifying and detecting signals: A first device has a surface and includes a plurality of at largest micrometer-scale geometry structures extending along its surface. The structures have a first portion and a second portion. A plurality of at largest micrometer-scale geometry conductors are coupled to the first portion of respective structures. A converter converts...

20060134871 - Charge-trapping memory device and method of production: Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath...

20060134870 - Transistor device and method of manufacture thereof: Methods of forming CMOS devices and structures thereof. A workpiece is provided having a first region and a second region. A high k gate dielectric material is formed over the workpiece. A first gate material comprising a first metal is formed over the high k gate dielectric material. The first...

20060134872 - Strained nmos transistor featuring deep carbon doped regions and raised donor doped source and drain: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels....

20060134873 - Tailoring channel strain profile by recessed material composition control: The present invention facilitates semiconductor fabrication by providing methods of fabrication that tailor applied strain profiles to channel regions of transistor devices. A strain profile is selected for the channel regions (104). Recessed regions are formed (106) in active regions of a semiconductor device after formation of gate structures according...

20060134874 - Manufacture method of mos semiconductor device having extension and pocket: A gate insulating film is formed on the surface of a semiconductor substrate in an opening of a field insulating film, and thereafter a gate electrode and a capacitor lower electrode made of doped polysilicon or the like are formed on the insulating film. Pocket regions are formed by an...

20060134875 - Method of forming storage node of capacitor: A method of forming a storage node of a capacitor includes defining a cell region and a peripheral circuit region in a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate of the cell region and the peripheral circuit region. Buried contact plugs are formed to penetrate...

20060134876 - Sram cell: A method for forming a resistor of high value in a semiconductor substrate including forming a stack of a first insulating layer, a first conductive layer, a second insulating layer, and a third insulating layer, the third insulating layer being selectively etchable with respect to the second insulating layer; etching...

20060134877 - Method for fabricating a buried conductive connection to a trench capacitor and a memory cell with such a connection: A buried conductive connection to a trench capacitor is formed in such a way that a contact area is provided between a conductive material layer which is arranged in the trench of the trench capacitor and contains a dopant and a semiconductor substrate between a first and a second predetermined...

20060134878 - Method of fabricating metal-insulator-metal capacitor: A method for fabricating a metal-insulator-metal (MIM) capacitor includes providing a semiconductor substrate having a region where the metal-insulator-metal capacitor is formed; forming an insulating film on the substrate; forming a sacrificial insulating film on the insulating film; forming a mask pattern having a plurality of openings on the sacrificial...

20060134879 - Methods of manufacturing a metal-insulator-metal capacitor: Methods of manufacturing a metal-insulator-metal capacitor are provided. An illustrated method includes: forming a lower metal electrode layer pattern for a metal-insulator-metal capacitor and a lower metal line layer pattern for a metal line on a first insulating layer on a semiconductor substrate; forming a second insulating layer covering the...

20060134880 - Methods of manufacturing a metal-insulator-metal capacitor: Methods of manufacturing a metal-insulator-metal capacitor are provided. An illustrated method includes: forming a lower metal electrode layer pattern in a metal-insulator-metal capacitor region and a lower metal line layer pattern in a metal line region above an insulating layer above a semiconductor substrate; forming an intermetal insulating layer covering...

20060134881 - Method of forming trench isolation device capable of reducing corner recess: A method of forming a trench isolation device capable of reducing corner recess comprising forming a pad oxide layer and a silicon nitride mask layer on a semiconductor base, and forming a trench by etching. Next, a liner oxide layer is formed on the semiconductor base and on the surface...

20060134882 - Method to improve device isolation via fabrication of deeper shallow trench isolation regions: A method of forming a shallow trench isolation (STI) structure wherein the depth of the STI structure has been extended via formation of an underlying silicon oxide region, has been developed. After definition of a shallow trench isolation shape in a top portion of a semiconductor substrate a self-aligned ion...

20060134883 - Systems and methods for electrical contacts to arrays of vertically aligned nanorods: Systems and methods may provide electrical contacts to an array of substantially vertically aligned nanorods. The nanorod array may be fabricated on top of a conducting layer that serves as a bottom contact to the nanorods. A top metal contact may be applied to a plurality of nanorods of the...

20060134885 - Method of machining substrate and method of manufacturing element: A method of machining a substrate etches a substrate according to a predetermined length and depth from an intersection between a first predetermined dividing line and a second predetermined dividing line, which cross each other in a T-shaped line, along the second predetermined dividing line of the predetermined dividing lines...

20060134884 - Wafer structure, chip structure, and fabricating process thereof: A chip fabricating process with the following steps is provided. Firstly, an under ball metal (UBM) layer is formed on a plurality of bump pads and wire pads of a wafer. Then, a portion of the thickness of the UBM layer on the wire pads is removed so as to...

20060134886 - Manufacturing method of semiconductor device: Island-like semiconductor films and markers are formed prior to laser irradiation. Markers are used as positional references so as not to perform laser irradiation all over the semiconductor within a substrate surface, but to perform a minimum crystallization on at least indispensable portion. Since the time required for laser crystallization...

20060134888 - Method for cutting printed circuit board: A method for cutting a printed circuit board includes providing a printed circuit board including a cutting region having a plurality of metal conducting wires, disposing a patterned first protection layer on the printed circuit board surface and exposing the metal conducting wires in the cutting region, forming a conducting...

20060134887 - Method of manufacturing a slice of semiconductor: A method of manufacturing an integrated circuit element from a silicon wafer, the silicon wafer having an active face and an inactive face, a passivation layer being deposited on the active face, where the method includes: an organic-layer-depositing step, in which an organic layer is deposited on the inactive face...

20060134889 - Application of post-pattern resist trim for reducing pocket-shadowing in srams: Methods (600, 700) are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant (32) extending underlying a gate region (21) of a transistor (10), particularly in SRAM devices (400). The pocket shadowing is minimized by initially forming a relatively thick resist layer (810)...

20060134890 - System and process for processing a plurality of semiconductor thin films which are crystallized using sequential lateral solidification techniques: A process and system are provided for processing at least one section of each of a plurality of semiconductor film samples. In these process and system, the irradiation beam source is controlled to emit successive irradiation beam pulses at a predetermined predetermined repetition rate. Using such emitted beam pulses, at...

20060134891 - Method for manufacturing semiconductor device: An object of the present invention is to provide a method for manufacturing a semiconductor device in which, after crystallizing by using an element that promotes crystallization, holes are prevented from being generated in a crystalline semiconductor film with a concentration of the element in the crystalline semiconductor film decreased...

20060134893 - Fabrication of strained heterojunction structures: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a...

20060134892 - Method of enhancing the photoconductive properities of a semiconductor and method of producing a semiconductor with enhanced photoconductive properties: A semiconductor material with photoconductive properties and a method of the semiconductor, wherein a base material is grown and then annealed post-growth at a temperature of 475° C. or less. It has been found that be annealing at temperatures of 475° C., or less the carrier lifetime of the material...

20060134894 - Method of manufacturing polycrystalline si film and manufacturing stacked transistor using the same: A method of manufacturing a polycrystalline Si film and a method of manufacturing a stacked transistor are provided. The method of manufacturing the polycrystalline Si film includes preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate,...

20060134895 - Method for preparing ge1-x-ysnxey (e=p, as, sb) semiconductors and related si-ge-sn-e and si-ge-e analogs: A process for is provided for synthesizing a compound having the formula E(GeH3)3 wherein E is selected from the group consisting of arsenic (As), antimony (Sb) and phosphorus (P). GeH3Br and [CH3)3Si]3E are combined under conditions whereby E(GeH3)3 is obtained. The E(GeH3)3 is purified by trap-to-trap fractionation. Yields from about...

20060134897 - Ethyleneoxide-silane and bridged silane precursors for forming low k films: p

20060134896 - Process for manufacturing liquid ejection head: A process includes forming a protective layer in a region of a substrate including a PAD electrode; forming a soluble resin layer in a region including a region on the substrate where an energy generating element has been formed, for forming a liquid chamber; forming a coating resin layer in...

20060134898 - Semiconductor damascene trench and methods thereof: A method is provided for forming damascene gates and local interconnects a single process. By combining the formation of a damascene gate and local interconnect into a single process, a low cost solution is provided, having the advantages of low resistance wordlines and reduced gate length while reducing or eliminating...

20060134899 - Method of removing spacers and fabricating mos transistor: A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing...

20060134900 - Method of forming a metal interconnection line in a semiconductor device using an fsg layer: A method of forming a metal line in a semiconductor device using a fluorine doped silica glass (FSG) insulation layer. The method includes forming a lower metal layer on a insulation layer on a semiconductor substrate, forming a metal oxide layer on a sidewall of the lower metal layer, forming...

20060134901 - Hot-melt underfill composition and methos of application: This invention provides a process for applying a wafer level underfill comprising: providing a solvent-free hot-melt underfill composition; melting the underfill; applying the underfill in a uniform layer to the active side of a semiconductor wafer; returning the underfill to a solid state; optionally B-staging the underfill; optionally removing any...

20060134902 - Method for constructing contact formations: According to one aspect of the invention, a method for forming contact formations is provided. A substrate may be placed in an electrolytic solution. The substrate may have an exposed conductive portion and the electrolytic solution may include a plurality of metallic ions and an accelerator. The accelerator may include...

20060134903 - Connection ball positioning method and device for integrated circuits: Forming conductive bumps on an integrated circuit wafer by sucking in conductive balls into cavities of a mask, placing the mask supporting the balls on the integrated circuit wafer, temporarily attaching the mask and the wafer together, cutting the suction, and submitting the mask and wafer assembly to a thermal...

20060134904 - Microelecromechanical system microphone fabrication including signal processing circuitry on common substrate: A MEMS microphone is formed on a single substrate that also includes microelectronic circuitry. High-temperature tolerance metals are used to form contacts in a metallization step before performing deep reactive ion etching and back patterning steps to form a MEMS microphone. High-temperature tolerant metals such as titanium, tungsten, chromium, etc....

20060134905 - Multilevel fabrication processing by functional regrouping of material deposition, lithography, and etching: A method of multilevel microfabrication processing is provided. The method includes providing a planar substrate that comprises one or more material layers. A first hardmask layer placed on top of the substrate is patterned into the lithographic pattern desired for the top lithographic layer. Subsequent hardmask layers are patterned until...

20060134906 - Post-esl porogen burn-out for copper elk integration: A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene...

20060134907 - Process for substrate incorporating component: In a process for producing the component-embedded substrate, a first electronic component is connected and fixed onto a first electrode pattern with a conductive bonding material, the first electrode pattern being provided on a first supporting layer. A second supporting layer including a second electrode pattern is press-bonded onto the...

20060134908 - Polishing method: A method for polishing an object to form wiring for a semiconductor device includes: removing part of an outside portion of a conductor layer through chemical and mechanical polishing to expose an upper surface of a barrier layer; and removing a remaining part of the outside portion of the conductor...

20060134909 - Method for fabricating semiconductor device: The method for fabricating the semiconductor device comprises the step of forming an insulating film 14 having an opening 18; the step of forming an organic resist film 20a; the step of forming over the organic resist film 20a a mask film 20b having etching characteristics different from those of...

20060134910 - Method of forming contact hole and method of fabricating semiconductor device: A method of forming contact holes is provided. A substrate having a plurality of device structures is provided. A first dielectric layer and a conductive layer sequentially cover the device structures and the surface of the substrate. A recess is formed in the conductive layer between every two neighboring device...

20060134911 - Manufacturable cowp metal cap process for copper interconnects: A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing...

20060134912 - Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants: A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5....

20060134913 - Method for fabricating semiconductor device having stacked-gate structure: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the...

20060134914 - Flexible circuits and method of making same: Disclosed is a method for making flexible circuits in which portions of a tie layer are removed by etching the underlying polymer. Also disclosed are flexible circuits made by this method....

20060134915 - Polishing apparatus and two-step method of polishing a metal layer of an integrated circuit: The method of manufacturing an integrated circuit (IC) according to the invention starts with providing a pre-fabricated integrated circuit (10) comprising an electrical device (2) and having a surface (11) coated with a dielectric material (12) and a metal (15). The dielectric material (12), which may be separated from the...

20060134916 - Poly open polish process: A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with high selectivity to an interlevel dielectric layer used...

20060134918 - Manufacturing method of substrate having conductive layer and manufacturing method of semiconductor device: The manufacturing method of a substrate having a conductive layer has the steps of: forming an inorganic insulating layer over a substrate; forming an organic resin layer with a desired shape over the inorganic insulating layer, forming a low wettability layer with respect to a composition containing conductive particles on...

20060134917 - Reduction of etch mask feature critical dimensions: A method for forming features in an etch layer in an etch stack with an etch mask over the etch layer, wherein the etch mask has etch mask features with sidewalls, where the etch mask features have a first critical dimension, is provided. A cyclical critical dimension reduction is performed...

20060134919 - Processing system and method for treating a substrate: A processing system and method for chemical oxide removal (COR), wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled...

20060134920 - Passivating metal etch structures: A method to passivate a freshly etched metal structure comprises providing a metal surface on a substrate that has been etched by a first particle beam, exposing the metal surface to a passivation gas, and exposing the freshly etched metal structures to a second particle beam in the presence of...

20060134921 - Plasma etching process: A plasma etching process is described. A substrate having a low-k material layer and a metal hard mask layer sequentially formed thereon is provided, wherein the metal hard mask layer exposes a portion of the low-k material layer. The low-k material layer is then etched with plasma of a gas...

20060134922 - Method of forming at least one thin film device: This invention provides a method of forming at least one thin film device, such as for example a thin film transistor. The method includes providing a substrate and depositing a plurality of thin film device layers upon the substrate. An imprinted 3D template structure is provided upon the plurality of...

20060134923 - Semiconductor substrate cleaning apparatus and method: According to the present invention, there is provided a semiconductor substrate cleaning apparatus comprising: a support which supports a semiconductor substrate; a rotating mechanism which rotates the semiconductor substrate; a first supply unit which supplies a first treatment liquid to which an ultrasonic wave is added, to a surface, on...

20060134924 - Method of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of...

20060134925 - Method of forming a gate insulating layer of a semiconductor device using deuterium gas: In an exemplary embodiment of the invention a method of forming a gate oxide layer of a semiconductor device uses deuterium gas. The method includes introducing a semiconductor substrate, and depositing an insulating layer on the semiconductor substrate by supplying an oxidation reaction gas and a deuterium gas to the...

20060134926 - Method for increasing polysilicon grain size: The present invention relates to a method for increasing the grain size of a polysilicon layer, which includes exposing a silicon oxide wafer in a deposition chamber to an amount, effective for the purpose, of nitrogen at a flow rate of at least about 240 standard liters per minute (slm)....

20060134927 - Method for forming ultra thin oxide layer by ozonated water: The present invention relates to a method for forming an ultra thin oxide layer by using an ozonated water, which comprises the steps of dissolving an ozone-containing gas in deionized water to form an ozonated water, and immersing a silicon wafer in the ozonated water to from an ultra thin...

20060134928 - Semiconductor manufacturing apparatus, liquid container, and semiconductor device manufacturing method: A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid...

20060134929 - Heating treatment device, heating treatment method and fabrication method of semiconductor device: To provide a method and a device for subjecting a film to be treated to a heating treatment effectively by a lamp annealing process, ultraviolet light is irradiated from the upper face side of a substrate where the film o be treated is formed and infrared light is irradiated from...

20060134930 - Method for forming a metal contact in a semiconductor device having a barrier metal layer formed by homogeneous deposition: Low resistance, high performance, and a longer lifetime of a semiconductor device may be achieved when a metal contact is formed in a semiconductor device by a method including: forming a lower metal layer on a semiconductor substrate; forming an interlayer insulating layer having a via hole on the lower...

20060134931 - Method for forming quantum dots: A method for forming quantum dots includes the following steps: (a) depositing a metal layer (4) on a substrate (2); (b) using an atomic force microscope (AFM) probe (6) to form a plurality of nanopores (42) in the metal layer (4); (c) depositing a semiconductor layer (3) on the metal...

20060128036 - Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step: An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250′, and a ferromagnetic top plate 20a. Also, a method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil...

20060128037 - Method of manufacturing a magnetic tunnel junction device: A method of manufacturing a magnetic tunnel junction device, in which a stack (1) comprising two magnetic layers (3, 7) and a barrier layer (5) extending in between is formed. One of the magnetic layers is structured by means of etching, in which, during etching, a part of this layer...

20060128038 - Method and system for providing a highly textured magnetoresistance element and magnetic memory: A method and system for providing a magnetic element are disclosed. The method and system include providing a pinned layer, a free layer, and a spacer layer between the pinned layer and the free layer. The spacer layer is insulating and has an ordered crystal structure. The spacer layer is...

20060128039 - Yield analysis method: A yield analysis method. First, a wafer having multiple dies is inspected to obtain wafer defect data containing defect information for every die in the wafer. Then a wafer map and an overall yield are generated according to the wafer defect data. The wafer map displays defective dies and defect-free...

20060128040 - Bond positioning method for wire-bonding process and substrate for the bond positioning method: A bond positioning method for a wire-bonding process and a substrate for the bond positioning method are provided. At least one solder mask mark is formed in a solder mask layer on the substrate, such that during the wire-bonding process, the solder mask mark serves as a reference point for...

20060128041 - Misalignment test structure and method thereof: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The...

20060128042 - Method for encapsulating at least one organic light-emitting (oled) device and oled device: A method for encapsulating at least one organic light-emitting (OLED) device (22) comprising the step of forming a concave region (24) on a plate (6) by applying a negative pressure to a predetermined area of the plate. The plate is attached to a substrate (1) comprising at least one active...

20060128043 - Method of mounting light emitting element: The present invention provides a method of mounting a light emitting element, in which a light emission point can be positioned at high accuracy with respect to the mounting member. A semiconductor laser element is placed on a matching stage. Next, a position and an azimuth of a laser stripe...

20060128044 - Solid state imaging device and producing method thereof: A semiconductor substrate of a solid state imaging device is connected to a cover glass, and then a backgrind is performed so as to make the thickness smaller. On a first face of the semiconductor substrate is formed plural units which is constructed of image sensors and plural contact terminals....

20060128045 - Method for selective laser crystallization and display panel fabricated by using the same: A display panel comprises a substrate having a displaying region (such as active organic light emitting region) and a circuit driving region; and a polysilicon layer formed on the substrate and having a first polysilicon portion and a second polysilicon portion respectively corresponding to the displaying region and circuit driving...

20060128046 - Semiconductor laser device and method for fabricating the same: A semiconductor laser device according to the present invention has a semiconductor substrate, an active layer formed on the semiconductor substrate and made of a compound semiconductor containing phosphorus, a guide layer formed on the active layer and made of a compound semiconductor a dopant diffusion preventing layer formed on...

20060128047 - Array substrate for liquid crystal display device and manufacturing method thereof: A fabricating method of an array substrate for a liquid crystal display device includes forming a gate line on a substrate; forming an ohmic contact layer on the substrate; forming a data line and source and drain electrodes on the ohmic contact layer, the source electrode being connected to the...

20060128048 - Pyramid socket suspension: An apparatus and method for flexibly suspending a sensing mechanism between a pair of cover plates, including a sensing mechanism formed in a crystalline silicon substrate; a pair of cover plates formed in crystalline silicon substrates; a first plurality of complementary interfaces in fixed relation between the sensing mechanism and...

20060128049 - Devices having vertically-disposed nanofabric articles and methods of making the same: Electro-mechanical switches and memory cells using vertically-disposed nanofabric articles and methods of making the same are described. An electro-mechanical device, includes a structure having a major horizontal surface and a channel formed therein. A conductive trace is in the channel; and a nanotube article vertically suspended in the channel, in...

20060128050 - Methods of fabricating image sensors including local interconnections: A pixel of a semiconductor-based image detector includes a photodetector, at least one switching device serially connected to the photodetector and a bypass device interposed between the photodetector and a power supply voltage. Accordingly, even though excess charges may be generated in the photodetector, the excess charges flow into the...

20060128051 - Method of fabricating cmos image sensor: A method of fabricating a CMOS image sensor is disclosed that enhances device robustness. The method includes the steps of forming a metal pad on a pad area of a substrate, forming a planarizing layer on the substrate including the metal pad, removing a portion of the planarizing layer to...

20060128052 - Solid-state imaging device and method of manufacturing the same: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a...

20060128053 - Increased mobility from organic semiconducting polymers field-effect transistors: Organic FETs are produced having high mobilities in the accumulation mode and in the depletion mode. Significantly higher mobility is obtained from FETs in which RR-P3HT film is applied by dip-coating to a thickness of only about 20 Å to 1 μm. It was found that the structural order of...

20060128054 - Mask and manufacturing method of a semiconductor device and a thin film transistor array panel using the mask: An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about −70° to about +70°....

20060128055 - Replacement gate with tera cap: A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patterning, a hardmask for etching...

20060128056 - Method of fabricating organic field effect transistor: Provided is a method of fabricating an organic field effect transistor (OFET). The method includes: forming an OFET pattern on a substrate, the OFET pattern having a gate electrode, a dielectric layer, a source electrode, a drain electrode, and an organic semiconductor layer; attaching a junction layer covered with a...

20060128058 - Wafer bonding of micro-electro mechanical systems to active circuitry: A single integrated wafer package includes a micro electromechanical system (MEMS) wafer, an active device wafer, and a seal ring. The MEMS wafer has a first surface and includes at least one MEMS component on its first surface. The active device wafer has a first surface and includes an active...

20060128057 - Xerographic micro-assembler: Xerographic micro-assembler systems and methods are disclosed. The systems and methods involve manipulating charge-encoded micro-objects. The charge encoding identifies each micro-object and specifies its orientation for sorting. The micro-objects are sorted in a sorting unit so that they have defined positions and orientations. The sorting unit has the capability of...

20060128059 - Compact system module with built-in thermoelectric cooling: An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The...

20060128061 - Fabrication of stacked die and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, wherein forming the bond between the non-device side of the first die and the non-device side of the second die...

20060128060 - Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same: A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided...

20060128062 - Electrical or electronic component and method of producing same: To refine an electrical or electronic component (100) having at least one discrete or integrated device (20) formed from a wafer (10), in plate or disk form, of semiconductive or insulating material, the front face (20v) of which device (20) has at least one overhanging and/or protruding and in particular...

20060128063 - Method of manufacturing semiconductor device and support structure for semiconductor substrate: A method of manufacturing a semiconductor device is disclosed. The method comprises a first step of grinding a second principle surface of a semiconductor substrate opposite to a first principle surface of the semiconductor substrate on which semiconductor device elements are formed, a second step of attaching a support structure...

20060128064 - Wafer packaging and singulation method: A multi-device lid for a micro device wafer has a plurality of micro devices. The multi-device lid includes a multi-lid substrate configured to cover the plurality of micro devices of the micro device wafer. The multi-lid substrate has a trench pattern with intersection portions and non-intersection portions on a first...

20060128065 - Adhesive sheet, dicing tape intergrated type adhesive sheet, and semiconductor device producing method: The invention provides an adhesive sheet which can be stuck to a wafer at low temperatures of 100° C. or below, which is soft to the extent that it can be handled at room temperature, and which can be cut simultaneously with a wafer under usual cutting conditions; a dicing...

20060128066 - Flexible carrier and release method for high volume electronic package fabrication: Methods and apparatus are provided for use in manufacturing a device packaging comprising the steps of: positioning a metal substrate such as spring steel on a magnetic plate so as to expose a surface of the metal substrate; placing a first tape layer on the exposed surface of a metal...

20060128067 - Semiconductor device package: A semiconductor package that includes two circuit boards and at least one semiconductor device which is disposed between the two circuit boards and connected to external connectors disposed on at least one of the circuit boards....

20060128068 - Methods of using sonication to couple a heat sink to a heat-generating component: Methods of using subsonic and/or sonic forces to couple a heat sink to a heat-generating component are described. Heat sinks coupled to heat-generating components via thermal interface materials are also described....

20060128069 - Package structure with embedded chip and method for fabricating the same: A package structure with embedded chip and a fabrication method thereof are proposed. A carrier board is provided, and at least one semiconductor chip is mounted on the carrier board. A core board having a cavity corresponding in position to the semiconductor chip and an insulating layer are pressed on...

20060128070 - Non-volatile memory device and fabricating method thereof: A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern....

20060128071 - Integrated antifuse structure for finfet and cmos devices: A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in...

20060128072 - Method of protecting fuses in an integrated circuit die: A fuse formed in an integrated circuit die includes: a length of an electrically conductive material for connecting two points of a circuit on the integrated circuit die and for selectively breaking the connection by a pulse of electrical current sufficient to dissolve a portion of the electrically conductive material;...

20060128073 - Multiple-wavelength laser micromachining of semiconductor devices: A specially shaped laser pulse energy profile characterized by different laser wavelengths at different times of the profile provides reduced, controlled jitter to enable semiconductor device micromachining that achieves high quality processing and a smaller possible spot size....

20060128074 - Combined fully-depleted silicon-on-insulator (fd-soi) and partially-depleted silicon-on-insulator (pd-soi)devices: A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epitaxial growth process (110)....

20060128075 - Manufacturing method of silicon on insulator wafer: Provided is a method of manufacturing a silicon on insulator (SOI) substrate, which includes the steps of (a) forming a buried oxidation layer to a predetermined depth of a first wafer and forming an oxidation layer on a surface of the first wafer; (b) bonding a second wafer onto the...

20060128079 - Method for manufacturing a thin film transistor: A method for manufacturing a thin film transistor (TFT) includes the steps of: providing a substrate (1); and forming a TFT circuit on the substrate using laser-induced chemical vapor deposition (LCVD). Detailedly, the method includes providing the bare substrate, cleaning the substrate with cleaning liquid, and successively forming a gate...

20060128076 - Self-aligning patterning method: The method comprises firstly forming a patterned mask 20 on the surface of a sacrificial layer 18 which is part of a multi-layer structure 10 which comprises the substrate 12, a conductive layer 14, an insulating layer 16 and the sacrificial layer 18. Unpatterned areas are then etched to remove...

20060128078 - Soi substrate manufacturing method: This invention makes it possible to simplify a process of manufacturing an SOI substrate whose insulator is not exposed to the side surface. The SOI substrate manufacturing method includes a first step of forming a structure (230) in which an insulating layer (204b) and semiconductor layer (203b) are in turn...

20060128077 - Thin film transistor and method for manufacturing the same: A method for manufacturing a thin film transistor includes forming a gate oxide film on a substrate, forming a first nitride layer on the gate oxide film, forming a polysilicon layer on the first nitride layer, forming a second nitride layer on sidewalls of the gate oxide film, first nitride...

20060128080 - Manufacturing method of semiconductor device: The present invention makes it is possible to provide a manufacturing method of a semiconductor device by which damage by plasma process or doping process during a LDD formation process can be reduced as much as possible. Charge density to be stored in a gate electrode and the damage of...

20060128081 - Mis semiconductor device and method of fabricating the same: The invention is concerned with the fabrication of a MIS semiconductor device of high reliability by using a low-temperature process. Disclosed is a method of fabricating a MIS semiconductor device, wherein doped regions are selectively formed in a semiconductor substrate or a semiconductor thin film, provisions are then made so...

20060128082 - Gate control and endcap improvement: A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric...

20060128085 - Metal-oxide-semiconductor device having improved performance and reliability: A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and second source/drain regions of the...

20060128083 - Method for fabricating organic thin film transistor: Disclosed herein is a method for fabricating an organic thin film transistor comprising a gate electrode, a gate insulating film, source/drain electrodes and an organic semiconductor layer formed in this order on a substrate wherein the surface of the gate insulating film on which source/drain electrodes are formed is impregnated...

20060128084 - Method of forming a gate pattern in a semiconductor device: A gate pattern having a critical dimension after an etching process of 60-70 nm may be formed using an ArF photoresist as an etching mask by a method including sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a...

20060128086 - Device having dual etch stop liner and protective layer and related methods: The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device...

20060128087 - Methods and devices for improved charge management for three-dimensional and color sensing: TOF and color sensing detector structures have x-axis spaced-apart y-axis extending finger-shaped gate structures with adjacent source collection regions. X-dimension structures are smaller than y-dimension structure and govern performance, characterized by high x-axis electric fields and rapid charge movement, contrasted with lower y-axis electric fields and slower charge movement. Preferably...

20060128089 - Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method: The invention relates to the manufacture of a semiconductor device (10) with a semiconductor body (1) and a substrate (2) and comprising at least one semiconductor element (3), which semiconductor device is equipped with at least one connection region (4) and a superjacent strip-shaped connection conductor (5) which is connected...

20060128088 - Vertical integrated component, component arrangement and method for production of a vertical integrated component: The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer...

20060128090 - Latch-up prevention for memory cells: A method of fabricating a memory cell and corresponding memory cell structure are provided. According to the method, a pull-up transistor and a pull-down transistor are formed in a semiconductor structure of the memory cell. The pull-up transistor is coupled to the pull down transistor. The pull-up transistor is coupled...

20060128091 - Device having enhanced stress state and related methods: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device...

20060128092 - Wafer bonded mos decoupling capacitor: A technique for forming a MOS capacitor (100) that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor (100) is formed separately from the particular circuit device (170) that it is to service. As such, the capacitor (100) and its fabrication process can be optimized in terms...

20060128093 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is provided. The method comprises forming a mask member on a surface of a semiconductor substrate; and forming a trench in the semiconductor substrate by selectively etching the semiconductor substrate with a mask of the mask member under a certain pressure. The pressure...

20060128094 - Semiconductor integrated circuit device and method of manufacturing the same: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel...

20060128096 - Methods of forming semiconductor devices: The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The source/drain regions can extend into the Si/Ge. The memory or logic devices...

20060128097 - Nonvolatile memory cells with buried channel transistors: In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current....

20060128095 - Semiconductor device comprising a highly-reliable, constant capacitance capacitor: A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in...

20060128098 - Split gate type nonvolatile semiconductor memory device, and method of fabricating the same: A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to...

20060128099 - Method of fabricating flash memory device including control gate extensions: A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch...

20060128100 - Semiconductor device and a method of producing the same: A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to...

20060128101 - Memory package: A memory chip package with a controller die on a first side of a printed circuit board and a memory die on a second side of the same printed circuit board. The memory chip package is integrated into a microprocessor controlled device or alternatively is integrated into a portable memory...

20060128102 - Manufacturing method of an non-volatile memory cell: A manufacturing method of a non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first...

20060128103 - Nrom memory cell, memory array, related devices and methods: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store...

20060128104 - Nrom memory cell, memory array, related devices and methods: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store...

20060128105 - High mobility heterojunction complementary field effect transistors and methods thereof: A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the...

20060128106 - Transistor and method for manufacturing thereof: A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing...

20060128107 - Methods of forming memory devices: The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is configured to provide both area and perimeter components of capacitance for capacitive enhancement. The capacitor includes a reference plate which splits into at least...

20060128108 - Method for forming a titanium nitride layer and method for forming a lower electrode of a mim capacitor using the titanium nitride layer: A method is provided for forming a titanium nitride layer in a metal-insulator-metal (MIM) capacitor. The deposition of a titanium nitride layer is carried out by means of an MOCVD method using a metallo-organic material as a source gas, followed by a rapid thermal process (RTP) at a high temperature....

20060128109 - Method of manufacturing a metal-insulator-metal capacitor: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory...

20060128111 - Raised sti process for multiple gate ox and sidewall protection on strained si/sgoi structure with elevated source/drain: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric...

20060128110 - Semiconductor device and a method of manufacturing the same: A technique is provided which permits formation within a single chip both a field effect transistor of high reliability capable of suppressing the occurrence of a crystal defect and a field effect transistor of a high integration degree. In a mask ROM section having an element isolation region with an...

20060128112 - Technique and methodology to passivate inductively coupled surface currents: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch...

20060128113 - Technique and methodology to passivate inductively or capacitively coupled surface currents under capacitor structures: A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch...

20060128114 - Trench isolation type semiconductor device and method of fabricating the same: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed...

20060128115 - Method for forming a shallow trench isolation structure with reduced stress: A method for forming a shallow trench isolation (STI) structure with reduced stress is described. An amorphous silicon layer is deposited on a trench surface of a shallow trench isolation structure, and the amorphous silicon is then oxidized by thermal oxidation to form a liner oxide. The thickness of the...

20060128117 - Forming structures that include a relaxed or pseudo-relaxed layer on a substrate: A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a material that becomes viscous above a certain viscosity...

20060128116 - Manufacturing method of silicon on insulator wafer: Provided is a method of manufacturing a silicon on insulator (SOI) substrate. The method includes the steps of: (a) forming a buried oxidation layer to a predetermined depth of a first wafer and forming an oxidation layer on the first wafer; (b) forming a buried hydrogen layer in the first...

20060128118 - Nitride semiconductor device comprising bonded substrate and fabrication method of the same: A substrate 1 for growing nitride semiconductor has a first and second face and has a thermal expansion coefficient that is larger than that of the nitride semiconductor. At least n-type nitride semiconductor layers 3 to 5, an active layer 6 and p-type nitride semiconductor layers 7 to 8 are...

20060128119 - Semiconductor device fabrication method: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a circuit pattern of a semiconductor element and a ground pad connected to a ground interconnection of said circuit pattern, in a semiconductor chip region divided into a plurality of portions on a main surface...

20060128120 - Short-wavelength laser dicing apparatus for a diamond wafer and dicing method thereof: The present invention discloses a short-wavelength laser dicing apparatus for a diamond wafer and a dicing method thereof, wherein a diamond wafer is disposed on a working table; the diamond wafer has multiple scribed lines; a control device is used to position the working table and a short-wavelength laser so...

20060128121 - Laser dicing apparatus for a gallium arsenide wafer and method thereof: The present invention discloses a laser dicing apparatus for a gallium arsenide wafer and a method thereof, wherein firstly, a gallium arsenide wafer is stuck onto a holding film; next, the gallium arsenide wafer together with the holding film is disposed on a working table; the gallium arsenide wafer has...

20060128122 - Mbe growth of a semiconductor layer structure: A method of MBE growth of a semiconductor layer structure comprises growing a first (Al,Ga)N layer (step 13) over a substrate at the first substrate temperature (T1) using ammonia as the nitrogen precursor. The substrate is then cooled (step 14) to a second-substrate temperature (T2) which is lower than the...

20060128123 - Methods of forming integrated circuits structures including epitaxial silicon layers in a active regions: An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active region. An epitaxial silicon layer extends from the active region through the...

20060128125 - Gate electrodes and the formation thereof: A method of fabricating a gate electrode for a semiconductor comprising the steps of: providing a substrate; providing on the substrate a layer of a first material of thickness tp, the first material being selected from the group consisting of Si, Si1-x—Gex alloy, Ge and mixtures thereof and a layer...

20060128124 - Growth of reduced dislocation density non-polar gallium nitride by hydride vapor phase epitaxy: Lateral epitaxial overgrowth (LEO) of non-polar a-plane gallium nitride (GaN) films by hydride vapor phase epitaxy (HVPE) results in significantly reduced defect density....

20060128126 - Masked sidewall implant for image sensor: A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a...

20060128128 - Method for producing a conductive layer: In a method for producing a conductive layer a substrate is provided. On the substrate, a layer comprised of at least two different metal nitrides is provided. Especially, on a surface of the substrate a first metal nitride layer, on a surface of the first metal nitride layer a second...

20060128127 - Method of depositing a metal compound layer and apparatus for depositing a metal compound layer: In a method and an apparatus for depositing a metal compound layer, a first source gas and a second source gas may be provided onto a substrate to deposit a first metal compound layer on the substrate. The first source gas may include a metal and halogen elements, and the...

20060128129 - Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making: A memory device including a substrate, and multiple self-aligned nano-rectifying elements disposed over the substrate. Each nano-rectifying element has multiple first electrode lines, and multiple device structures disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less...

20060128130 - Method for fabricating recessed gate structure: The present invention relates to a method for fabricating a recessed gate structure. The method includes the steps of: selectively etching a substrate to form a plurality of openings; forming a gate oxide layer on the openings and the substrate; forming a first conductive silicon layer on the gate oxide...

20060128131 - Independently accessed double-gate and tri-gate transistors in same process flow: A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member...

20060128132 - Method and system for controlling the presence of fluorine in refractory metal layers: A method and system to reduce the resistance of refractory metal layers by controlling the presence of fluorine contained therein. The present invention is based upon the discovery that when employing ALD techniques to form refractory metal layers on a substrate, the carrier gas employed impacts the presence of fluorine...

20060128133 - Reagent activator for electroless plating: A method for electroless plating of a substrate is provided that comprises exposing an electroless plating reagent comprising a metal to be plated and at least one reducing agent to a solid phase Activation Material to form an activated electroless plating reagent prior to application of the electroless plating reagent...

20060128134 - Method for re-routing lithography-free microelectronic devices: A method for producing a chip-scale electronic package produced at a substrate level, the substrate including at least one chip having input/output pads on a substrate face. The method a) forms, using a complex mold or stencil, an insulating stress relaxation layer on the front face, the relaxation layer covering...

20060128135 - Solder bump composition for flip chip: It is an object of the present invention to provide a method for solder bump formation using a combination of eutectic and high lead solders. The present invention provides a method for improving a solder bump composition for a flip chip....

20060128136 - Systems and methods for solder bonding: Systems and methods for solder bonding that employ an equilibrium solidification process in which the solder is solidified by dissolving and alloying metals that raise the melting point temperature of the solder. Two or more structure surfaces may be solder bonded, for example, by employing heating to melt the solder...

20060128137 - Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes: A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill...

20060128138 - Gate structure having diffusion barrier layer: The present invention provides a gate structure having a diffusion barrier layer and the process for fabrication thereof. A diffusion barrier layer is formed between the polysilicon layer and the tungsten silicide metal layer by using ion implantation, thereby preventing silicon ion diffusion between the polysilicon layer and the tungsten...

20060128140 - Method of forming a contact hole in a semiconductor device: An exemplary method of forming a contact hole in a semiconductor device includes: forming a first insulation layer on a lower substrate; forming a first conductive layer on the first insulation layer; forming a second insulation layer on the first insulation layer and the first conductive layer; forming a second...

20060128139 - Process sequence for doped silicon fill of deep trenches: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way...

20060128141 - Semiconductor device and method for fabricating the same: An insulating film is formed of a carbon-containing silicon dioxide film on a semiconductor substrate. In the insulating film, an interconnect groove is formed. A silicon dioxide layer with a density high enough to allow almost no oxygen to pass therethrough is formed on the bottom and side faces of...

20060128142 - Method for selective deposition of a thin self-assembled monolayer: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface...

20060128143 - Production method for electronic component and electronic component: The present invention provides a method of manufacturing an electronic part in which on the upper surface of an insulating member covering lower layer wiring, a conductor portion connected from the lower layer wiring is exposed. In this method, electric power supplying film is formed on the upper surface of...

20060128144 - Interconnects having a recessed capping layer and methods of fabricating the same: Apparatus and methods of fabricating an interconnect having a recessed capping layer. An embodiment of the present invention relates to the fabrication of an interconnect for a microelectronic device which includes a recessed capping layer, which substantially eliminates topography issues present in the known devices and provides improved encapsulation of...

20060128145 - Device having dual etch stop liner and reformed silicide layer and related methods: The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual...

20060128146 - Method of forming barrier layer and method of fabricating interconnect: A method of fabricating a barrier layer is described. A material layer having an opening formed therein is provided. Then, the material layer is disposed inside a physical vapor deposition chamber and a first deposition process is performed to form a first barrier layer on the surface of the opening....

20060128147 - Method of fabricating electrically conducting vias in a silicon wafer: One or more electrically conducting vias are formed through a silicon substrate having a first surface, an opposite second surface, and a thickness between the first and second surfaces. A conductive metallic material is deposited on the first surface of the silicon substrate. For example, the metallic material may be...

20060128148 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device by forming an alloy layer in a connection hole provided in a layer insulation film on a substrate, including a first step of forming a first Cu layer in the state of covering the inside wall of the connection hole, a second step...

20060128149 - Method for forming a metal wiring in a semiconductor device: A method for forming a metal wiring in a semiconductor device is disclosed. The method comprises the steps of: forming an interlevel dielectric layer over a semiconductor substrate; forming a metal layer on an upper surface of the interlevel dielectric layer; forming a metal wiring including a plurality of metal...

20060128150 - Ruthenium as an underlayer for tungsten film deposition: In one embodiment, a method for depositing a tungsten-containing film on a substrate is provided which includes depositing a barrier layer on the substrate, such as a titanium or tantalum containing barrier layer and depositing a ruthenium layer on the barrier layer. The method further includes depositing a tungsten nucleation...

20060128151 - Method for removing photoresist layer and method for forming metal line in semiconductor device using the same: Disclosed are a method for removing a photoresist layer and a method for forming a metal line using the same. The method for removing a photoresist pattern, including the steps of: forming a bottom layer on a substrate by using the photoresist pattern as a mask; and removing the photoresist...

20060128152 - Plasma oxidation and removal of oxidized material: A method of etching a conductive layer includes converting at least a portion of the conductive layer and etching the conductive layer to substantially remove the converted portion of the conductive layer and thereby expose a remaining surface. The remaining surface has an average surface roughness of less than about...

20060128154 - Glass substrate for magnetic disk and its production process: A doughnut-type glass substrate for a magnetic disk having a circular hole at its center, characterized in that its inner peripheral edge surface is an etched surface with a large number of pits having different curvature radii adjacent to one another, and the proportion of pits having curvature radii r...

20060128153 - Method for cleaning slurry particles from a surface polished by chemical mechanical polishing: A method is provided to clean slurry particles from a surface in which tungsten and dielectric are coexposed after a dielectric CMP step. Such a surface is formed when tungsten features are patterned and etched, the tungsten features are covered with dielectric, and the dielectric is planarized to expose tops...

20060128155 - Columnar structured material, electrode having columnar structured material, and production method therefor: To obtain a microcolumnar structured material having a desired material. The columnar structured material includes columnar members 15 obtained by introducing a filler into columnar holes formed in a porous material. The porous material has the columnar holes 14 formed by removing columnar substances from a structured material in which...

20060128156 - Self-patterning of photo-active dielectric materials for interconnect isolation: In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an...

20060128157 - Semiconductor structure with partially etched gate and method of fabricating the same: A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining...

20060128159 - Method of removing etch residues: Organic etch residues are often left within vias formed by etching through resist masks. Since the etch is designed to expose an underlying metal layer and is directional in order to produce vertical via sidewalls, the residue often incorporates metal. The present invention discloses a method of removing such etch...

20060128158 - Micro-structure manufacturing method: A method of manufacturing a micro-structure includes dry-etching a sacrificial layer provided to a silicon substrate to form structures the sacrificial layer reacting with etching gas to generate reaction products including H2O, wherein the dry-etching includes etching the sacrificial layer and removing H2O as one of the reaction products generated...

20060128160 - Photoresist strip using solvent vapor: Photoresist is removed from a wafer or substrate during various stages of processing by introducing a solvent vapor, along with heat, into the processing chamber. The solvent vapor chemically reacts with the photoresist to quickly and cleanly strip away the exposed photoresist....

20060128161 - Film formation method and apparatus for semiconductor process: A film formation method for a semiconductor process for forming a silicon oxynitride film on a target substrate within a reaction chamber includes a step of performing a pre-process on members inside the reaction chamber without the target substrate loaded therein, and a step of then forming a silicon oxynitride...

20060128162 - Process for fabricating a semiconductor device having an rtcvd layer: A process of fabricating a semiconductor device includes forming a device region including a non-volatile memory element and forming a utility layer overlying the device region, where the utility layer is a dielectric material formed by RTCVD. The utility layer preferably has a hydrogen content below that necessary to reduce...

20060128163 - Surface treatment of post-rie-damaged p-osg and other damaged materials: Damaged porous OSG layers and other damage may be chemically healed. Chemical healing is particularly advantageous in a porous OSG layer in a sub 90 nm ILD. For example, chemical healing may be by reacting the damage with an adhesion promoter having a “k” value comparable to the “k” value...

20060128164 - Chemical treatment of semiconductor substrates: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is...

20060128165 - Method for patterning surface modification: A method of patterning surface modification by (a) positioning a repositionable aperture mask in proximity to a substrate, and (b) selectively exposing a portion of the substrate to a surface modification treatment, wherein the exposed portion is defined by one or more apertures in the aperture mask....

20060128166 - Semiconductor device fabrication method: The semiconductor device fabrication method comprises the step of forming a first porous insulation film 38 over a semiconductor substrate 10; the step of forming a second insulation film 40 whose density is higher than that of the first porous insulation film 38; and the step of applying electron beams,...

20060128167 - Semiconductor device fabrication method: The semiconductor device fabrication method comprises the step of forming a first porous insulation film 38 over a semiconductor substrate 10; the step of forming a second insulation film 40 whose density is higher than that of the first porous insulation film 38; and the step of applying electron beams,...

20060128168 - Atomic layer deposited lanthanum hafnium oxide dielectrics: Atomic layer deposited dielectric layers containing a lanthanum hafnium oxide layer and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices. In an embodiment, a lanthanum hafnium oxide layer is formed by depositing hafnium and...

20060115909 - Method for manufacturing a resistively switching memory cell, manufactured memory cell, and memory device based thereon: The invention relates to a method for manufacturing at least one resistively switching memory cell, in particular a phase change memory cell, said method comprising at least the steps of (a) structuring a hardmask applied above a layer and (b) etching back at least part of the structured hardmask, in...

20060115910 - Method for predicting lifetime of insulating film: e

20060115911 - Layout verification method and method for designing semiconductor integrated circuit device using the same: To provide a layout verification method capable of accurately detecting damage to be given to a gate, and to provide a higher-workability and higher-reliability design method to accurately detect damage to be given to a gate and to determine an approach for design correction to avoid damage, the layout verification...

20060115912 - Manufacturing method and luminance adjustment method of light emitting element array, exposure head, and electrophotographic apparatus: As for a light emitting array and an exposure head provided with a plurality of light emitting elements capable of emitting light by the supplying power respectively, the electrical stress is given only to the light emitting element selected based on the luminance of each light emitting element, whereby the...

20060115914 - Method of fabricating one-way transparent optical system: A method of fabricating a one-way transparent optical system by which external light is effectively intercepted and internal light passes nearly without loss is provided. The method includes: forming a photoresist on an upper surface of a transparent substrate; heating and carbonizing the photoresist to form a black body layer;...

20060115913 - Optical fiber preform, method of manufacturing optical fiber preform, and method of manufacturing optical fiber: A porous layer is formed by depositing a silica glass particle around a core rod. The porous layer is dehydrated. The dehydrated porous layer is sintered under a decreased pressure until the dehydrated porous layer becomes a translucent glass layer containing a closed pore. The translucent glass layer is vitrified...

20060115915 - Method of manufacturing electrooptical device and image forming device: A method of manufacturing an electrooptical device includes a step of forming a luminous element on a luminous element forming face of a transparent substrate, a step of forming an attach face by grinding a face of the transparent substrate that opposes the luminous element forming face toward the luminous...

20060115916 - Method of manufacturing silicon optoelectronic device, silicon optoelectronic device manufacture by the method, and image input and/or output apparatus using the silicon optoelectronic device: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method, and an image input and/or output apparatus including the silicon optoelectronic device are provided. The method includes preparing an n- or p-type silicon-based substrate, forming a microdefect pattern along a surface of the substrate...

20060115917 - Precision synthesis of quantum dot nanostructures for fluorescent and optoelectronic devices: Methods are disclosed generally directed to design and synthesis of quantum dot nanoparticles having improved uniformity and size. In a preferred embodiment, a release layer is deposited on a semiconductor wafer. A heterostructure is grown on the release layer using epitaxial deposition techniques. The heterostructure has at least one layer...

20060115918 - Method for manufacturing a magnetic field detecting element: A method for manufacturing a magnetic field detecting element having a soft magnetic core formed on a substrate, first and second coils, each having coil lines, arranged above and below the core, the method including forming a seed film on the substrate, removing a portion of the seed film using...

20060115919 - Method of making a microelectromechanical (mem) device using porous material as a sacrificial layer: A method of making a microelectromechanical (MEM) device using a standard silicon wafer, rather than an SOI wafer, includes selectively implanting a dopant in regions of the standard wafer, to thereby form heavily doped regions therein. The heavily doped regions are then converted to porous silicon regions. An electrical isolation...

20060115920 - Semiconductor device having mems: In a semiconductor device having a MEMS according to this invention, a plurality of units having movable portions for constituting a MEMS are monolithically mounted on a semiconductor substrate on which an integrated circuit including a driving circuit, sensor circuit, memory, and processor is formed. Each unit has a processor,...

20060115921 - Micro-fluid ejection head containing reentrant fluid feed slots: Methods of micro-machining a semiconductor substrate to form through fluid feed slots therein. One method includes providing a semiconductor substrate wafer having a thickness greater than about 500 microns and having a device side and a back side opposite the device side. The back side of the wafer is mechanically...

20060115922 - Photo movie creating method, apparatus, and program: A photo movie creating apparatus stores a photo movie creating program. When the photo movie creating program is started, a position detecting section and an image editing section are generated in the CPU. The position detecting section detects a distance L1 from the center to the edge of a cropping...

20060115923 - Micromirror-based projection system and a method of making the same: A projection system is disclosed herein. The projection system employs a spatial light modulator comprising an array of individually addressable pixels for modulating the incident light based on image data. The modulated light is projected on a screen for viewing....

20060115924 - Method of forming a deformed pattern over a substrate: A method of deforming a pattern comprising the steps of forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively...

20060115925 - Methods of fabricating a microlens including selectively curing flowable, uncured optically trasmissive material: A microlens for use in an imaging device may be fabricated by disposing a flowable, uncured optically transmissive material in at least one layer onto a surface of a substrate, selectively curing at least a portion of the flowable, uncured optically transmissive material, and removing the flowable, uncured optically transmissive...

20060115926 - Methods of forming conductive elements using organometallic layers and flowable, curable conductive materials: A conductive element is formed on a substrate by forming an organometallic layer on at least a portion of a surface of the substrate, heating a portion of the organometallic layer, and removing an unheated portion of the organometallic layer. In other methods, a flowable, uncured conductive material may be...

20060115927 - Attachment of flip chips to substrates: An anisotropic conductive layer is formed between a substrate and a flip chip having multiple contacts. Insulating layers are formed on the lateral surfaces of the electrical contacts. When the flip chip is attached to a substrate, the insulating layers reduce the chance of an electrical path being formed in...

20060115928 - Methods for assembling a stack package for high density integrated circuits: Methods for assembling a stack package for a high density IC module on a PCB include the steps of assembling a first layer of the stack package on the PCB, assembling a second layer of the stack package on the first layer and assembling a third layer of the stack...

20060115929 - Die-to-die connection method and assemblies and packages including dice so connected: A method for assembling semiconductor dice includes orienting at least one second semiconductor die with the active surface thereof facing the active surface of a first semiconductor die. A structure on an active surface of one of the semiconductor dice may interact with a peripheral edge or other feature of...

20060115930 - Semiconductor device and method of fabricating the same, circuit board, and electronic instrument: A method of fabricating a semiconductor device, including: preparing a wiring board on which is mounted a first semiconductor chip having a plurality of first pads; electrically connecting each of the first pads to an interconnecting pattern of the first semiconductor chip by a wire; providing resin paste on the...

20060115931 - Semiconductor package substrate with embedded chip and fabrication method thereof: A semiconductor package substrate with embedded chip and a fabrication method thereof are provided. A first insulating layer is applied on a metallic board, and formed with at least one opening for exposing a portion of the metallic board. At least one semiconductor chip is mounted on the exposed portion...

20060115932 - Method for fabricating semiconductor components with conductive vias: A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions...

20060115933 - Use of cl2 and/or hcl during silicon epitaxial film formation: In a first aspect, a first method of forming an epitaxial film on a substrate is provided. The first method includes (a) providing a substrate; (b) exposing the substrate to at least a silicon source so as to form an epitaxial film on at least a portion of the substrate;...

20060115934 - Selective epitaxy process with alternating gas supply: In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is...

20060115937 - Devices for an insulated dielectric interface between high-k material and silicon: Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide...

20060115936 - Method of manufacturing semiconductor device with reduced junction leakage current and gate electrode resistance of transistor: After a gate electrode made of a material containing a refractory metal is formed, the gate electrode is oxidized to form an oxide film for covering an exposed side surface of the gate electrode, at a predetermined temperature in an initial oxidization phase, and thereafter, the gate electrode is oxidized...

20060115935 - Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device: There is provided a method of manufacturing a semiconductor device, the method including: forming a γ-aluminum oxide layer on a semiconductor substrate; forming a semiconductor layer on the γ-aluminum oxide layer; forming an exposed portion for exposing a part of the γ-aluminum oxide layer through the semiconductor layer; forming a...

20060115938 - Method for forming an improved t-shaped gate structure: A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at...

20060115940 - Dual work function metal gate structure and related method of manufacture: A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine....

20060115939 - Dual-gate device and method: A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material...

20060115942 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. In a manufacturing method comprising the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second...

20060115943 - Method of fabricating semiconductor device using low dielectric constant material film: The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element...

20060115941 - Method of fabricating transistor including buried insulating layer and transistor fabricated using the same: In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer...

20060115944 - Methods of fabricating a semiconductor device having a node contact structure of a cmos inverter: In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern is formed on the lower insulating layer using the intrinsic...

20060115945 - Printed transistors: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For...

20060115946 - Method of forming a lower electrode of a capacitor: In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface...

20060115947 - Planarizing method for forming fin-fet device: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket...

20060115948 - Manufacturing method of semiconductor device: Ni silicide is formed through simple steps. After forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited...

20060115949 - Semiconductor fabrication process including source/drain recessing and filling: A semiconductor fabrication process includes forming a gate dielectric overlying a silicon substrate and forming a gate electrode overlying the gate dielectric. Source/drain recesses are then formed in the substrate on either side of the gate electrode using an NH4OH-based wet etch. A silicon-bearing semiconductor compound is then formed epitaxially...

20060115951 - Capacitor having an anodic metal oxide substrate: A structure and method including an anodic metal oxide substrate used to form a capacitor are described herein....

20060115950 - Methods of fabricating trench type capacitors including protective layers for electrodes and capacitors so formed: A method of forming a capacitor can include forming a protective layer on a metal layer in a trench in an insulating layer and outside thereof. A surface of the protective layer and the metal layer beneath can be planarized using a chemical mechanical polishing (CMP) process to expose a...

20060115952 - Method for forming multilayer electrode capacitor: A method of forming a multilayer electrode capacitor is described. A trench is formed in a substrate or in an insulator layer. Two sets of conductive layers are deposited on the inner surface of the trench. The first set of conductive layers is electrically connected to each other, and so...

20060115953 - Method for forming capacitor of semiconductor device: Disclosed is a method for forming a capacitor of a semiconductor device, which can secure wanted charging capacity and also improve leakage current characteristics. The method comprises the steps of: forming a storage electrode on a semiconductor substrate; forming a dielectric layer formed of Ti(1-x)TbxO on the storage electrode; and...

20060115954 - Methods of manufacturing a capacitor and a semiconductor device: In methods of manufacturing a capacitor and a semiconductor device, a mold layer is formed on a substrate having a contact plug. The mold layer includes an opening exposing the contact plug. A conductive layer is formed on the contact plug, an inner sidewall of the opening and the mold...

20060115955 - Method for manufacturing anti-punch through semiconductor device: A method for manufacturing an anti-punch through semiconductor device is described. The method is applied to a substrate having a plurality of device isolation structures in parallel arrangements and the upper surface of the device isolation structures is protruded from the surface of the substrate. A plurality of conductive layers...

20060115956 - System and method using visible and infrared light to align and measure alignment patterns on multiple layers: A system and method are used to increase alignment accuracy of feature patterns through detection of alignment patterns on both a surface layer and at least one below surface layers of an object. Visible light is used to detect alignment patterns on the surface layer and infrared light is used...

20060115957 - Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces: The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second...

20060115958 - Method and apparatus for forming buried oxygen precipitate layers in multi-layer wafers: A method of forming a SOI wafer obtains an intermediate apparatus having a first wafer, a second wafer, and an insulator material bonding the first and second wafers together. The first wafer has an oxygen precipitate concentration sufficient for gettering. The method reduces the profile of at least a portion...

20060115959 - Flexible mems thin film without manufactured substrate and process for producing the same: A process for producing flexible MEMS thin film without a manufactured substrate applied in a MEMS manufacture specially includes a method of forming a component interface in the middle between a manufactured substrate and a MEMS thin film formed on the manufactured substrate as a basis, which component interface is...

20060115960 - Method of forming component interface in semiconductor or mems manufacture: A method of forming component interface in semiconductor or MEMS manufacture is by way of a bad adhesion material or manufacture, or an easy etching and removable material, to form an easily removed component interface in the middle between a manufactured substrate and a layer of semiconductor circuit or MEMS...

20060115961 - Method of producing a thin layer of semiconductor material: m

20060115962 - Method for manufacturing semiconductor device: The inventive method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device using irradiation with laser light to partition a substrate having semiconductor layers formed thereon, with gallium contained in at least one of the substrate and the semiconductor layers, wherein the method comprises: forming grooves...

20060115963 - Semiconductor device and method of manufacturing the same: An object of the invention is to provide a semiconductor device which includes a barrier metal having high adhesiveness and diffusion barrier properties and a method of manufacturing the semiconductor device. The invention provides a semiconductor device manufacturing method including forming a first layer made of a material containing silicon...

20060115964 - Near single-crystalline, high-carrier-mobility silicon thin film on a polycrystalline/amorphous substrate: A template article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the...

20060115965 - Ion implanted microscale and nanoscale device method: A method is used for producing nanoscale and microscale devices in a variety of materials, such as silicon dioxide patterned buried films. The method is inexpensive and reliable for making small scale mechanical, optical, or electrical devices and relies upon the implantation of ions into a substrate and subsequent annealing...

20060115966 - Method and apparatus for the improvement of material/voltage contrast: A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal...

20060115967 - Methods of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device including a polysilicon layer on which a heat treatment is performed in hydrogen atmosphere, a preliminary polysilicon layer is formed on a semiconductor substrate. Fluorine (F) impurities are implanted onto the preliminary polysilicon layer, so that the preliminary polysilicon layer is formed...

20060115968 - Method and apparatus for thermally treating disk-shaped substrates: A method and apparatus for thermally treating disk-shaped substrates, especially semiconductor wafers, in a rapid heating unit having at least one first radiation source, which is spaced from a given substrate for heating the substrate. The substrate is heated in a heating phase and is cooled in a cooling phase...

20060115969 - Method for controlling lattice defects at junction and method for forming ldd or s/d regions of cmos device: A method for controlling lattice defects at a junction is described, which is used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step. In the method, an extra implantation step is performed to increase the stress in the substrate apart...

20060115970 - Compositions and processes for photoresist stripping and residue removal in wafer level packaging: Improved compositions and processes for removing photoresists, polymers, post etch residues, and post oxygen ashing residues from interconnect, wafer level packaging, and printed circuit board substrates are disclosed. One process comprises contacting such substrates with mixtures containing an effective amount of organic ammonium compound(s); from about 2 to about 20...

20060115971 - Nano- and micro-scale structures: methods, devices and applications thereof: Disclosed are methods for fabricating integrated nano-scale and micro-scale structures. Also disclosed are carbon nanopipettes, shovels, and sheets made by these methods. Nano-scale and micro-scale structures fabricated by the disclosed methods are useful in a variety of application, for example, nanoelectrodes, functionalized probes for chemical and biological sensing, nanopipettes for...

20060115972 - Multi-step process for patterning a metal gate electrode: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on...

20060115973 - Metal polishing composition and method of polishing using the same: A metal polishing composition comprising at least one of the compound represented by formula (1) defined herein and the compound represented by formula (2) defined herein, and an oxidizing agent, and a chemical mechanical polishing method comprising bringing the metal polishing composition into contact with a surface to be polished...

20060115974 - Method of making a circuitized substrate: A circuitized substrate and a method of making the circuitized substrate are provided. The circuitized substrate includes a substrate having a conductive pad thereon. A first layer of solder enhancing material is positioned on the conductive pad, the first layer of solder enhancing material includes a first region and a...

20060115975 - Method for attaching an integrated circuit package to a circuit board: A method for attaching an IC package to a circuit board, the IC package having a plurality of electrical contacts in an arrangement having a perimeter, first positions the IC package adjacent to the circuit board. Then, electrically connects the IC package to the circuit board through the plurality of...

20060115976 - Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition: A method for improving the reliability of integrated circuits. In one embodiment, the method includes forming a dielectric layer on a semiconductor wafer. A trench is then formed in the dielectric. Thereafter, a conductive interconnect is formed within the trench, wherein the conductive interconnect comprises copper. The conductive interconnect is...

20060115977 - Method for forming metal wiring in semiconductor device: Disclosed is a method for forming a metal wiring in a semiconductor device in order to improve the operational speed of the semiconductor device. The method includes the steps of depositing an interlayer dielectric film on a silicon substrate, in which the interlayer dielectric film has a contact hole for...

20060115978 - Charge-trapping memory cell and method for production: The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer...

20060115980 - Method for decreasing a dielectric constant of a low-k film: A method of forming a low dielectric constant film that can be used in a damascene process is disclosed. An organosilicon precursor such as octamethylcyclotrisiloxane (OMCTS) or any other compound that contains Si, C, and H and optionally O is transported into a PECVD chamber with a carrier gas such...

20060115979 - Plasma etch process for multilayer vias having an organic layer with vertical sidewalls: A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer...

20060115981 - Forming a dual damascene structure without ashing-damaged ultra-low-k intermetal dielectric: A new method for forming a single or a double damascene interconnect structure is provided in which after the damascene interconnect structure is formed, in which a plasma ashing process is used to remove the photoresist mask used during the photolithography process, the trench-level intermetal dielectric layer is removed leaving...

20060115982 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a contact hole with an opening having a high aspect ratio can be favorably filled without using a conventional CMP process. It is another object of the present invention to provide...

20060115983 - Method of manufacturing semiconductor device: One of methods of manufacturing a semiconductor device of the present invention is as follows: a first conductive layer is formed, a first insulating layer is formed over the first conductive layer, and a second insulating layer is formed over the first insulating layer; then, a first opening portion is...

20060115984 - Methods of forming metal nitride layers, and methods of forming semiconductor structures having metal nitride layers: Methods of forming metal nitride layers on a substrate include reacting a metal source gas with a nitrogen source gas in a process chamber to form a metal nitride layer on the substrate. The process chamber may have an atmosphere having a pressure of about 0.1 mTorr to about 5...

20060115985 - Methods of forming tungsten contacts by chemical vapor deposition: Described are methods of manufacturing a semiconductor device with tungsten contacts between two conductive layers on different interconnect levels. A barrier adhesion layer is formed over interconnect openings followed by a tungsten nucleation film being deposited at a nucleation temperature and a tungsten bulk deposition film being deposited at a...

20060115986 - Edge removal of silicon-on-insulator transfer wafer: A silicon-on-insulator transfer wafer having a front surface with a circumferential lip around a circular recess is polished. In one version, the circular recess on the front surface of the wafer is masked by filling the recess with spin-on-glass. The front surface of the wafer is exposed to an etchant...

20060115987 - Semiconductor device having recess and planarized layers: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the...

20060115988 - Method of forming sidewall spacers: A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with...

20060115989 - Method of manufacturing a thin-film circuit substrate having penetrating structure, and protecting adhesive tape: A method of manufacturing a thin-film circuit substrate, containing: (a) gouging a surface of a circuit substrate in a depth at least approximately equal to a thickness of a final product of the substrate, to form a section to be formed a penetrating section; (b) providing a protecting adhesive tape...

20060115990 - Pattern forming method, underlayer film forming composition, and method of manufacturing semiconductor device: According to an aspect of the invention, there is provided a pattern forming method comprising forming an underlayer film on a film to be worked which has been formed on a semiconductor substrate, subjecting the underlayer film to an oxidizing treatment, forming an intermediate film which becomes a mask of...

20060115992 - Coating apparatus, coating method and coating-film forming apparatus: A coating apparatus is provided in which a coating liquid supplied onto a surface of a substrate such as a semiconductor wafer and a glass substrate can be easily leveled so as to have a uniform thickness without any edge bead. The coating apparatus comprises a tray, a nozzle for...

20060115991 - Method for controlling the properties of darc and manufacturing darc: A method for controlling the properties of a dielectric anti-reflective coating (DARC) is provided. In the process of forming the DARC, a nitrogen-containing gas is added to a reaction gas comprising silicon-containing gas and oxygen for controlling the n value of the DARC. Furthermore, the proportion of the silicon-containing gas...

20060115993 - Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to...

20060115994 - Pb-free solder-connected structure and electronic device: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder....

20060115995 - Electrode insulator and method for fabricating the same: An electrode insulator and method for fabricating the same, wherein a T-shape electrode insulator made of inorganic dielectric material is fabricated perpendicular to the first electrode formed on the substrate, and insulating the second electrode from the first electrode. Inorganic films are used twice to form the insulator, and the...

20060115996 - Method for enhancing fsg film stability: A method for enhancing stability of a fluorinated silicon glass layer is disclosed. A fluorinated silicon glass layer provided on a substrate is subjected to a phosphorous-containing and hydrogen-containing gas such as phosphine (PH3), for example. The gas forms reactive hydrogen species which removes fluorine radicals and reactive phosphorous species...

20060115998 - Method for forming pattern of organic insulating film: A method for forming a pattern of an organic insulating film by forming an electrode on a substrate, coating an imprintable composition thereon to form an organic insulating film, pressurizing and curing the organic insulating film using a patterned mold to transfer a pattern of the mold to the organic...

20060115997 - Method for patterning thin film, method and apparatus for fabricating flat panel display: Disclosed is a method and apparatus for fabricating a patterned thin film layer within a flat panel display that employs a soft mold and heat treatment in place of a photolithographic process. The disclosed method may reduce process time as well as substantially minimize pattern deformities. A method of fabricating...

20060115999 - Methods of exposure for the purpose of thermal management for imprint lithography processes: The present invention is directed to a method that attenuates, if not avoids, heating of a substrate undergoing imprint lithography process and the deleterious effects associated therewith. To that end, the present invention includes a method of patterning a field of a substrate with a polymeric material that solidifies in...

20060116000 - Manufacturing method of insulating film and semiconductor device: The invention provides a manufacturing method of an insulating film having a plurality of pores, as well as a manufacturing method of a highly integrated semiconductor device with high yield. According to the invention, a porous insulating film is formed by forming a plurality of pores in an interlayer insulating...

20060116001 - Patterning method: A method for patterning a device layer, for example of an organic electronic or optoelectronic device, using a patterned stamp. The method comprising the steps of (a) providing a substrate, (b) bringing the patterned stamp into contact with the substrate, (c) removing the patterned stamp from the substrate, characterized in...

20060116002 - Surface-activation of semiconductor nanostructures for biological applications: The present invention provides means and methods for producing surface-activated semiconductor nanoparticles suitable for in vitro and in vivo applications that can fluoresce in response to light excitation. Semiconductor nanostructures can be produced by generating a porous layer in semiconductor substrate comprising a network of nanostructures. Prior or subsequent to...