Semiconductor device manufacturing: process inventions 05/06

20060110836 - Eliminating systematic process yield loss via precision wafer placement alignment: A method for a semiconductor process includes correlating yield loss for the performance of a processing step in a semiconductor manufacturing process with the mechanical placement of the semiconductor substrate and, based on the correlation, placing semiconductor substrates in a position with sufficient placement precision to reduce yield loss below...

20060110837 - Method and system for topography-aware reticle enhancement: The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC). The reticle enhancement calculations are improved by incorporating post-planarization topography estimates. A planarization process of a wafer layer is simulated to estimate the post-planarization topography. RET calculations, such as sub-resolution...

20060110838 - Multilayered circuit substrate, semiconductor device and method of producing same: A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can...

20060110840 - Functional device and method for producing the same: where Tg is a glass transition temperature of the organic material, ΔE1 is an activation energy for crystallization of the organic material measured while the electrode layer and the insulating layer are not stacked on the functional layer and ΔE2 is an activation energy for crystallization of the organic material...

20060110839 - Micro-leds: An array of light emitting devices, each device comprising a sloped wall mesa (24) of luminescent semiconductor material. Extending over the sloped wall mesas (24) is a metal contact (30). The array can be arranged as a parallel addressable system so that all devices (24) can be stimulated to emit...

20060110841 - Avalanche photodiode: An avalanche photodiode includes at least one crystal layer having a larger band-gap than that of an absorption layer formed by a composition or material different from that of the absorption layer formed on a junction interface between a compound semiconductor absorbing an optical signal and an Si multiplication layer,...

20060110842 - Method and apparatus for preventing metal/silicon spiking in mems devices: The disclosure relates to a method and apparatus for preventing extrusion or spiking of a metal atom from a metallization layer to other layers of a silicon wafer. In one embodiment, the method includes forming a silicon-on-ship device with a MEMS component on the substrate. The MEMS component may include...

20060110843 - Method of manufacturing an external force detection sensor: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole dry etching of an element substrate, and an electrically conductive material is used as an etching stop layer during the dry etching....

20060110844 - Fabrication of thin film germanium infrared sensor by bonding to silicon wafer: A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion...

20060110845 - Method of manufacturing micro-structure element by utilizing molding glass: A method of manufacturing micro-structure elements by utilizing molding glass includes the steps of forming a mold having a micro-structure pattern thereon by using an electroforming process, making a copy of the micro-structuring pattern on a glass structure by using glass molding technology, and filling clothing material on the glass...

20060110846 - Electrically programmable memory element with improved contacts: A method of making an electrically programmable memory element, comprising: providing a conductive sidewall spacer; and forming a phase-change material in electrical communication with said conductive sidewall spacer....

20060110847 - Field effect transistor and its manufacturing method: To provide a method of easily producing TFT in which the orientation of channel molecules or wires is enhanced, compared with conventional type organic TFT at a low price, a lyophilic TFT pattern encircled by a lyophobic area is formed on a substrate, spontaneous movement is made in a droplet...

20060110849 - Method for stacking bga packages and structure from the same: The present invention relates to a method for stacking BGA packages. At first, a first BGA package is provided. The first BGA package includes a first substrate, at least one first chip and a plurality of first connecting balls. The first substrate has a first upper surface and a first...

20060110850 - Method for two-stage transfer molding device to encapsulate mmc module: A method for fabricating a semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined...

20060110848 - Off-width pitch for improved circuit card routing: Enlarged spacing is provided between rows of vias in a ball grid array (BGA) multilayered printed wiring board land pattern in which the lands in the pattern are connected to the vias by a link connector by rotating, elongating, and/or truncating selected consecutive link connectors and rotating their respective corresponding...

20060110851 - Methods for forming co-planar wafer-scale chip packages: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed...

20060110852 - Methods to achieve precision alignment for wafer scale packages: Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed...

20060110853 - Structure of embedded active components and manufacturing method thereof: A structure of embedded active components and the manufacturing method thereof are provided. The manufacturing steps involve providing a molding plate, and setting several active components on the molding plate as first. A dielectric layer covers the molding plate to cap the active components. An electric circuit is formed on...

20060110854 - Methods and systems for providing mems devices with a top cap and upper sense plate: A method for fabricating a MEMS device having a top cap and an upper sense plate is described. The method includes producing a device wafer including an etched substrate, etched MEMS device components, and interconnect metal, a portion of the interconnect metal being bond pads and adding a metal wraparound...

20060110855 - Leadframe with enhanced encapsulation adhesion: A leadframe having a metallic substrate and comprising layers of plated material, and a method of manufacturing said leadframe are provided. The substrate is plated with a layer of oxidizable material comprising nickel and a noble metal is selectively plated on the layer of oxidizable material. Thereafter, an exposed portion...

20060110857 - Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same: A method of fabricating a lead frame for a semiconductor device having a semiconductor chip resin-sealed therein. The lead frame includes a lead to be electrically connected to the semiconductor chip within sealing resin and to be sealed into the sealing resin such that at least a part of its...

20060110856 - Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side...

20060110858 - Ultra-thin semiconductor package device and method for manufacturing the same: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness...

20060110859 - Electronic device and manufacturing method of the same: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature...

20060110861 - Integrated circuit with multi-length power transistor segments: A monolithic power integrated circuit fabricated on a semiconductor die includes a control circuit and a first output high voltage field-effect transistor (HVFET) having source and drain segments substantially equal to a first length. A second output HVFET has source and drain segments substantially equal to a second length. At...

20060110860 - Self-adjusting serial circuit of thin layers and method for production thereof: The invention relates to a self-adjusting serial circuit of thin layers and method for production thereof. The invention is characterised in that electrically conducting conductor tracks (20) are applied to a substrate (10), whereupon several main deposit layers (30, 40, 50) of conducting, semi-conducting or insulating materials are applied to...

20060110864 - Method of fabricating a thin film transistor using dual or multiple gates: A method of fabricating a TFT using dual or multiple gates, and a TFT having superior characteristics and uniformity by providing a method of fabricating a TFT using dual or multiple gates by calculating the probability including Nmax, the maximum number of crystal grain boundaries in active channel regions according...

20060110862 - Method of forming a thin film transistor: A method of forming a thin film transistor comprising a deposition procedure of a microcrystal material layer and performing a plasma treatment procedure. The deposition procedure and the plasma treatment procedure are repeated. A buffer layer is thus formed on the gate electrode....

20060110863 - Semiconductor device, and method for manufacturing the same: It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor,...

20060110867 - Field effect transistor manufacturing method: Provided is a novel method for manufacturing a field effect transistor. Prior to forming an amorphous oxide layer on a substrate, ultraviolet rays are irradiated onto the substrate surface in an ozone atmosphere, plasma is irradiated onto the substrate surface, or the substrate surface is cleaned by a chemical solution...

20060110866 - Method for fabricating thin film transistors: Thin film transistor fabrication methods. A gate electrode is formed on a substrate. The surface of metal gate is subjected to a hydrogen plasma treatment to remove a native oxide formed thereon. A nitride layer as a buffer layer is formed to cover the metal gate. A gate insulating layer...

20060110865 - Method of forming ultra thin silicon oxynitride for gate dielectric applications: A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A...

20060110868 - Production of lightly doped drain of low-temperature poly-silicon thin film transistor: A method is disclosed to make a lightly doped drain of a low-temperature poly-silicon thin film transistor. Nitrogen is implanted during steps of doping the source and the drain so as to suppress the spreading of the other types of dope so that the poly-silicon layer forms a shallow interface...

20060110869 - Semiconductor device including a tft having large-grain polycrystalline active layer, lcd employing the same and method of fabricating them: A display device includes a pixel region having a plurality of pixels and a peripheral circuit region disposed at a periphery of the pixel region for driving the pixels. The peripheral circuit region includes transistors fabricated from polycrystalline semiconductor and having a semiconductor crystalline grain of a first kind in...

20060110872 - Method for fabricating a semiconductor structure: A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. The mask layer is patterned...

20060110871 - Methods for fabricating thin film transistors: Fabrication methods for thin film transistors. A metal gate stack structure is formed on an insulating substrate. The substrate is performed using thermal annealing to create an oxide layer on the sidewalls of the metal gate stack structure. A gate insulating layer is formed on the substrate covering the metal...

20060110870 - Scalable integrated logic and non-volatile memory: A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers....

20060110873 - Method for fabricating cmos image sensor: Form a gate electrode on a transistor region of a first conductivity type semiconductor substrate including a photodiode region and the transistor region. Form lightly-doped second conductivity type diffusion areas at both sides of the gate electrode in the photodiode region and the transistor region. Form a screen layer over...

20060110874 - Method of forming source contact of flash memory device: The present invention relates to a method of forming a source contact of a flash memory device. According to the present invention, the method includes the steps of forming a first interlayer insulating film on a semiconductor substrate in which first junction regions and second junction regions both of which...

20060110875 - Trench lateral power mosfet and a method of manufacturing the same: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with...

20060110876 - Mos transistor with reduced kink effect and method for the manufacture thereof: A lateral MOS transistor is provided with a channel region, which has a channel width delimited by dielectric-filled trenches and which is covered with a gate dielectric, whose layer thickness varies over the channel width. An outer layer thickness, which the gate dielectric has over junctions of the channel region...

20060110877 - Memory device including resistance change layer as storage node and method(s) for making the same: A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise)...

20060110878 - Side wall active pin memory and manufacturing method: A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with...

20060110881 - Method of manufacturing a select transistor in a nand flash memory: Disclosed herein is a method of manufacturing a flash memory device. According to the present invention, a method of manufacturing a NAND flash memory device having a memory cell and a select transistor, wherein a graph showing the relation between the length of a gate electrode of the select transistor...

20060110882 - Methods of forming gate structure and flash memory having the same: A method of forming a gate structure, including forming sequentially a gate dielectric layer, a conductive layer, a protective layer, a sacrificial layer, and a patterned mask layer over a substrate. The exposed sacrificial layer is removed by using the patterned mask layer as an etching mask and the protective...

20060110879 - Non-volatile memory and fabricating method thereof: A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of...

20060110880 - Self-aligned trench filling with high coupling ratio: Self-aligned trench filling to isolate active regions in high-density integrated circuits is provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide. The oxide grows from the substrate to fill the trench and into...

20060110883 - Method for forming a memory device: A method of forming a storage device is disclosed. A sacrificial layer is formed over a semiconductor substrate. Impurities are introduced into sacrificial layer. The substrate is annealed to precipitate discrete storage elements in the sacrificial layer. The sacrificial layer is selectively removed using a process that leaves the discrete...

20060110884 - Method of manufacturing a transistor and a method of forming a memory device: A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the isolation trenches at a position adjacent to the groove so that the two plate-like portions will be...

20060110885 - Body having angle scaling: A monolithic body having angle scaling is rotatable about an axis to measure the rotational position of a machine part. The body has a first annular region which has a flange-type configuration for connection to the machine part, and a second annular region on which the angle scaling is arranged,...

20060110886 - Mosfet structure and method of fabricating the same: A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a bird's beak structure. The gate-to-drain overlap capacitance is reduced by the bird's beak structure....

20060110887 - Microelectronic device and a method for its manufacture: Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor substrate layer with multiple openings exposing portions of the surface of...

20060110888 - Phase changeable memory device and method of formation thereof: In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to...

20060110889 - Method for fabricating a mim capacitor having increased capacitance density and related structure: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited...

20060110890 - Cut-and-paste imprint lithographic mold and method therefor: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure....

20060110891 - Method for rounding bottom corners of trench and shallow trench isolation process: A method for rounding the bottom corners of a trench is described. In the method, an etching process is performed using a fluorocarbon compound with at least two carbon atoms, He and O2 as an etching gas to round the bottom corners of the trench....

20060110892 - Semiconductor process for forming stress absorbent shallow trench isolation structures: A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to...

20060110893 - Glass-type planar substrate, use thereof, and method for the production thereof: The invented method is distinguished by a combination of the following method steps: provision of a semiconductor planar substrate composed of a semiconductor material, reduction of the thickness of the semiconductor planar substrate inside at least one surface region of the semiconductor planar substrate in order to form a raised...

20060110894 - Manufacturing method of semiconductor laser devices and manufacturing apparatus of the same: The present invention is to provide a semiconductor laser device manufacturing method for realizing highly reliable semiconductor laser devices. The semiconductor laser device manufacturing method includes: cutting a wafer into bar-shaped wafers by scanning an electron beam on the front side of the wafer on which a semiconductor laser structure...

20060110895 - Method of fabricating silicon-based mems devices: A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure...

20060110896 - Compound semiconductor particles and production process therefor: There are provided: compound semiconductor particles that can display more excellent performance in functions peculiar to the compound semiconductor (e.g. luminosity and luminescence efficiency); and a production process for obtaining such compound semiconductor particles with economy, good productivity, and ease. Compound semiconductor particles, according to the present invention, are characterized...

20060110898 - Circuitized substrates utilizing smooth-sided conductive layers as part thereof, method of making same, and electrical assemblies and information handling systems utilizing same: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer...

20060110899 - Methods for fabricating a germanium on insulator wafer: Improved fabrication processes for manufacturing GeOI type wafers are disclosed. In an implementation, a method for fabricating a germanium on insulator wafer includes providing a source substrate having a surface, at least a layer of germanium and a weakened area. The weakened area is located at a predetermined depth in...

20060110900 - Method of forming a gate of a semiconductor device: In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is...

20060110902 - Method and system for metal barrier and seed integration: A method for making an electrode in a semiconductor device. The method includes forming a trench in a first layer. The first layer is associated with a top surface, and the trench is associated with a bottom surface and a side surface. Additionally, the method includes depositing a diffusion barrier...

20060110903 - Method for formation of a contact in a semiconductor wafer: In order to form a contact in a layer on a substrate, in particular a contact in a logic circuit in a semiconductor component, the mask layer is structured for etching of the contact holes with a photoresist layer which is exposed using two masks, with the first mask containing...

20060110901 - Minimizing resist poisoning in the manufacture of semiconductor devices: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via...

20060110904 - Multiple shadow mask structure for deposition shadow mask protection and method of making and using same: The present invention is a multi-layer shadow mask and method of use thereof. The multi-layer shadow mask includes a sacrificial mask bonded to a deposition mask. The sacrificial mask provides protection against an accumulation of evaporant on the deposition mask which would cause the deposition mask to deform....

20060110905 - High surface area aluminum bond pad for through-wafer connections to an electronic package: A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads....

20060110907 - Method for removing resin mask layer and method for manufacturing solder bumped substrate: Using a dry film resist that is a photosensitive resin, a resin mask layer is formed around electrodes on a substrate. A solder precipitating composition is applied on the substrate, and this solder precipitating composition is heated to precipitate solder on the surface of the electrodes. Subsequently, in removing the...

20060110906 - Wafer alignment method: The present invention relates to a wafer alignment method. The wafer alignment method includes the steps of forming first bonding pads and first wafer alignment marks of a convex shape on predetermined regions of a first semiconductor substrate in which a first device is formed, forming second bonding pads on...

20060110908 - Method for forming wiring pattern, method for manufacturing device, device, electro-optic apparatus, and electronic equipment: A method for forming a wiring pattern according to an aspect of the invention forms a wiring pattern in a certain area on a substrate by using a droplet discharge technique, and comprises forming a bank surrounding the certain area on the substrate; discharging a first functional liquid containing a...

20060110909 - Dendrite growth control circuit: A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is...

20060110910 - Method for forming landing plug poly of semiconductor device: Disclosed is a method for forming a landing plug poly of a semiconductor device. In such a method, there is provided a substrate formed with gates, each of which has a nitride film as a gate hard mask and nitride film spacers. An insulating interlayer is formed over the entire...

20060110911 - Controlled electroless plating: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine...

20060110912 - Semiconductor devices with composite etch stop layers and methods of fabrication thereof: Semiconductor devices with composite etch stop layers and methods of fabrication thereof. An semiconductor device with a composite etch stop layer includes a substrate having a conductive member, a first etch stop layer on the substrate and the conductive member, a second etch stop layer and a dielectric layer sequentially...

20060110914 - Direct imprinting of etch barriers using step and flash imprint lithography: A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier...

20060110913 - Gate structure having diffusion barrier layer: The present invention provides a gate structure having a diffusion barrier layer and the process for fabrication thereof. A diffusion barrier layer is formed between the polysilicon layer and the tungsten silicide metal layer by using ion implantation, thereby preventing silicon ion diffusion between the polysilicon layer and the tungsten...

20060110915 - Semiconductor device having low-k dielectric film in pad region and method for manufacture thereof: A low-k dielectric film is formed on an entire surface of a substrate having a pad region and a circuit region. A resist pattern is formed on the low-k dielectric film, and an opening is formed in the low-k dielectric film of the pad region using the resist pattern as...

20060110916 - Forming an intermediate layer in interconnect joints and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise forming a first adhesion layer on a conductive layer, forming an intermediate layer on the first adhesion layer, and forming a barrier layer on the intermediate layer, wherein the intermediate layer comprises a coefficient of thermal expansion that is...

20060110917 - Method of metallization in the fabrication of integrated circuit devices: The method of metallization in the fabrication of an integrated circuit device comprises the steps as follows. First, a dielectric layer overlying a semiconductor substrate is provided. The dielectric layer has a top surface and a plurality of openings. Next, a metal layer is formed on the dielectric layer and...

20060110918 - Method and deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors: A method and a deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors using CO gas and a dilution gas. The method includes providing a substrate in a process chamber of a processing system, forming a process gas containing a metal-carbonyl precursor vapor and a CO gas,...

20060110920 - Low temperature nitride used as cu barrier layer: A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in...

20060110919 - Method of forming a wiring pattern, method of manufacturing a device, device, electro-optic device, and electronic instrument: A method of forming a wiring pattern in a predetermined area on a substrate using a droplet ejection process, including the steps of (a) forming a recess section for disposing a functional fluid in the predetermined area so that the predetermined area has a first region, a second region connected...

20060110921 - Methods for forming a structured tungsten layer and forming a semiconductor device using the same: A method for forming a structured tungsten layer and a method for forming a semiconductor device using the same. A first tungsten layer is formed with an atomic layer deposition (ALD) method. A second tungsten layer is formed on the first tungsten layer with a chemical vapor deposition (CVD) method....

20060110922 - Metallic chromonic compounds: m

20060110924 - Abrasive-free chemical mechanical polishing compositions and methods relating thereto: An aqueous abrasive-free composition is useful for chemical mechanical polishing of a patterned semiconductor wafer containing a nonferrous metal. The composition comprises an oxidizer, an inhibitor for the nonferrous metal, 0 to 15 weight percent water soluble modified cellulose, 0 to 15 weight percent phosphorus compound, 0.005 to 5 weight...

20060110923 - Barrier polishing solution: The polishing solution is useful for preferentially removing barrier materials in the presence of nonferrous interconnect metals with limited erosion of dielectrics. The polishing solution comprises 0 to 20 weight percent oxidizer, inhibitor for reducing removal rate of the nonferrous interconnect metals, ammonium salt, 0.1 to 50 weight percent silica...

20060110925 - Dry etching method and diffractive optical element: A dry etching method is provided, in which dry etching is performed in such a manner that a conductor to which an insulative substrate is attached is brought in electric, intimate contact with an electrode. In the dry etching method, the insulative substrate is attached to the conductor by means...

20060110926 - Control of photoelectrochemical (pec) etching by modification of the local electrochemical potential of the semiconductor structure relative to the electrolyte: A method for locally controlling an electrical potential of a semiconductor structure or device, and hence locally controlling lateral and/or vertical photoelectrochemical (PEC) etch rates, by appropriate placement of electrically resistive layers or layers that impede electron flow within the semiconductor structure, and/or by positioning a cathode in contact with...

20060110927 - Package for a semiconductor device: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a...

20060110928 - Etching of structures with high topography: The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatile memory applications, and for...

20060110929 - Anhydrous film for lip make-up or care: The present invention relates to a method for cladding a simple or complex surface, electrically conducting or semiconducting, by means of an organic film from at least one precursor of said organic film, characterised in that the cladding of the surface by the organic film is carried out by electro-initiated...

20060110930 - Direct liquid injection system and method for forming multi-component dielectric films: The present invention provides methods and systems for atomic layer deposition (ALD). In some embodiments a system is provided comprising: at least one direct liquid injection system configured to inject one or more deposition precursors into one or more vaporization chambers, at least one bubble system configured to vaporize one...

20060110931 - Method for forming insulation film: A method for forming an insulation film on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma CVD processing; and...

20060110932 - Method and apparatus for oxidizing nitrides: A method for oxidizing a nitride film is disclosed, which includes the steps of: providing a nitride film formed on an electrically conductive substrate; irradiating the nitride film with a light beam and getting close to the nitride film with a electrically conductive probe; and exerting a bias between the...

20060110939 - Enhanced thin-film oxidation process: A method is provided for additionally oxidizing a thin-film oxide. The method includes: providing a substrate; depositing an MyOx (M oxide) layer overlying the substrate, where M is a solid element having an oxidation state in a range of +2 to +5; treating the MyOx layer to a high density...

20060110938 - Etch stop layer: A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to...

20060110934 - Method and apparatus for forming insulating film: The present invention provides a method and apparatus for forming an insulating film having good reliability, in accordance with a process without high-temperature heating. In accordance with the present invention, in a process for forming an insulating film for a semiconductor device by oxidizing a material to be processed, exposed...

20060110937 - Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that...

20060110936 - Method of increasing deposition rate of silicon dioxide on a catalyst: Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of...

20060110933 - Plasma control method and plasma control apparatus: A method that controls the distribution of a plasma generated in a vacuum chamber, for example as part of a plasma thin film deposition or plasma etching process. For thin film deposition, the method serves to minimize variations in film thickness caused by the variations of the film deposition conditions....

20060110935 - Semiconductor device and manufacturing method thereof: A semiconductor device with a fuse 3a to be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first insulating film 11 with high filling capability and a second insulating film 12 blocking penetration of moisture or...

20060110940 - Method of preparing mesoporous thin film having low dielectric constant: A method of preparing a mesoporous thin film having a low dielectric constant, which includes mixing a cyclic siloxane-based monomer, an organic solvent, an acid catalyst or a base catalyst, and water, to prepare a coating solution, which is then applied on a substrate and heat cured. The mesoporous thin...

20060110941 - Method of improving via filling uniformity in isolated and dense via-pattern regions: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps....

20060110942 - Method of manufacturing flash memory device: A method of manufacturing flash memory devices, comprises the steps of forming an oxide film on a semiconductor substrate, performing a pre-annealing process under N2 gas atmosphere, nitrifying the oxide film by performing a main annealing process under N2O atmosphere having the flow rate of 5 to 15 slm for...

20060110943 - Remote plasma activated nitridation: A nitrogen precursor that has been activated by exposure to a remotely excited species is used as a reactant to form nitrogen-containing layers. The remotely excited species can be, e.g., N2, Ar, and/or He, which has been excited in a microwave radical generator. Downstream of the microwave radical generator and...

20060110944 - Dummy substrate for thermal reactor: A single substrate reactor system for processing batches of product substrates one at a time is provided with at least one dummy substrate. In the time after one batch of product substrates is processed and before another batch of product substrates is ready for processing, the dummy substrate is used...

20060110945 - Method using specific contact angle for immersion lithography: A method for performing immersion lithography on a semiconductor wafer is disclosed. The method includes positioning the semiconductor wafer beneath a lens and applying a fluid between a top surface of the semiconductor wafer and the lens. An additive can be provided to the top surface so that any droplet...

20060105473 - Substrate processing system, substrate processing method, sealed container storing apparatus, program for implementing the substrate processing method, and storage medium storing the program: A substrate processing system which is capable of preventing dust from becoming attached to substrates without increasing the degree of cleanliness of a clean room to a predetermined level, and also capable of increasing the substrate processing throughput without increasing the burden on workers. a plasma processing apparatus 2 that...

20060105474 - Method for manufacturing a magnetic memory device, and a magnetic memory device: In bit line cladding structure formation, stability and margin of the process are secured and further shrinking is achieved, and the magnetic memory device is improved in speed, reliability and yield. Method for manufacturing a magnetic memory device, comprising the steps of: forming a word line; forming a magnetoresistance effect...

20060105475 - Fast localization of electrical failures on an integrated circuit system and method: Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested employing a parallel electrical tester. The results of the electrical testing are analyzed to localize...

20060105476 - Photoresist pattern, method of fabricating the same, and method of assuring the quality thereof: A photoresist pattern and a method of fabricating the same make it easy to quickly identify a particular portion of a photolithography process that is responsible for causing process defects. The method of fabricating the photoresist pattern includes forming main patterns having a predetermined critical dimension in device-forming regions of...

20060105477 - Device and method for manufacturing wafer-level package: In an embodiment of the invention, a device for manufacturing a wafer-level package includes a wafer sawing unit, a sorting unit, a pickup unit, and a placing unit. The wafer sawing unit cuts a wafer into wafer-level packages. The sorting unit performs a sorting process on the wafer-level packages to...

20060105482 - Array of light emitting devices to produce a white light source: A device is provided with an array of a plurality of phosphor converted light emitting devices (LEDs) that produce broad spectrum light. The phosphor converted LEDs may produce light with different correlated color temperature (CCT) and are covered with an optical element that assists in mixing the light from the...

20060105478 - Bonding an optical element to a light emitting device: A device is provided with at least one light emitting device (LED) die mounted on a submount with an optical element subsequently thermally bonded to the LED die. The LED die is electrically coupled to the submount through contact bumps that have a higher temperature melting point than is used...

20060105479 - Method of integrating optical devices and electronic devices on an integrated circuit: A method for integrating an optical device and an electronic device on a semiconductor substrate comprises forming openings within an active semiconductor layer in a first region of the semiconductor substrate, wherein the first region corresponds to an electronic device portion and the second region corresponds to an optical device...

20060105480 - Method of making light emitting device with silicon-containing encapsulant: A method of making a light emitting device is disclosed. The method includes providing a light emitting diode and forming an encapsulant in contact with the light emitting diode; wherein forming the encapsulant includes contacting the light emitting diode with a photopolymerizable composition consisting of a silicon-containing resin and a...

20060105481 - Method of making light emitting device with silicon-containing encapsulant: A method of making a light emitting device is disclosed. The method includes the steps of providing a light emitting diode and forming an encapsulant in contact with the light emitting diode; wherein forming the encapsulant includes contacting the light emitting diode with a photopolymerizable composition consisting of a silicon-containing...

20060105483 - Encapsulated light emitting diodes and methods of making: Methods for making encapsulated light emitting diodes, and light emitting articles prepared thereby are disclosed. The methods include activating a light emitting diode to emit light to at least partially polymerize a photopolymerizable encapsulant....

20060105484 - Molded lens over led die: One or more LED dice are mounted on a support structure. The support structure may be a submount with the LED dice already electrically connected to leads on the submount. A mold has indentations in it corresponding to the positions of the LED dice on the support structure. The indentations...

20060105485 - Overmolded lens over led die: One or more LED dice are mounted on a support structure. The support structure may be a submount with the LED dice already electrically connected to leads on the submount. A mold has indentations in it corresponding to the positions of the LED dice on the support structure. The indentations...

20060105486 - Method of fabricating a liquid crystal display device: A method of fabricating a liquid crystal display device according to an embodiment of the present invention includes forming first and second conductive layers on a substrate, wherein the first layer is transparent; patterning the second conductive layer and the first conductive layer using the photo-resist pattern as a mask;...

20060105487 - Method and apparatus for fabricating flat panel display: A fabricating method of a flat panel display includes the steps of spreading an etch-resist on a thin film formed on a substrate, a polarity of the etch-resist changed by irradiation with a first light; providing a soft mold having a projected surface and a groove at an upper surface...

20060105489 - Method and apparatus providing cmos imager device pixel with transistor having lower threshold voltage than other imager device transistors: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions...

20060105488 - Method of integrating optical devices and electronic devices on an integrated circuit: A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately...

20060105490 - Microlens manufacturing method: The present invention provides a method for manufacturing a microlens in a semiconductor substrate having a first surface and a second surface, comprising the steps of preparing the semiconductor substrate, forming a first resist layer approximately cylindrical in form on the first surface of the semiconductor substrate, reflowing the first...

20060105491 - Method for treating a photovoltaic active layer and organic photovoltaic element: The invention relates to an organically based photovoltaic element, in particular a solar cell comprising a photovoltaically active layer whose absorption maximum can be shifted into the longer wavelength region and/or whose efficiency can be increased....

20060105493 - Encapsulation of organic devices: A method for encapsulating devices, in particular organic devices such as OLED-devices, comprising the steps of depositing organic active material on an active region of a substrate; providing a cap to enclose said organic active material within a space defined by a cap periphery adapted to adhere to the substrate;...

20060105492 - Organic electronic devices: A method for forming an organic electronic device, which method comprises the steps of: a) forming a negative image of a desired pattern on a substrate or device layer with a lift-off ink; b) coating a first device layer to be patterned on top of the negative image; c) coating...

20060105496 - Device and method for fabricating double-sided soi wafer scale package with through via connections: A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. A through buried oxide via connects the chip(s) to the...

20060105495 - Device and method for reshaping the interconnection elements of an electronic module using the stress reflow method and, in particular, for restoring the flatness thereof: A method and device are provided to reshape a set of conducting elements which are distributed over the inner face of an electronic module, said set of conducting elements forming means of positioning the module on a motherboard and/or electromagnetic armour means for the inner face of the module and/or...

20060105494 - Method and apparatus for cleaning and sealing display packages: A method and apparatus for cleaning and sealing components of a display utilizes continuous isolation of the components between the cleaning step and the sealing step. This limits exposure of the components to contaminants and isolates the components from oxidizing agents which can cause an oxide to form on the...

20060105497 - Forming a stress compensation layer and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening....

20060105498 - Wafer stack separator: An integrated circuit wafer container and separator combination. The separator comprises a substantially flat main area and a plurality of elevated projections in the periphery thereof. The elevated projections sustain the weight of the wafer stacks, avoid vacuum adhesion, and minimize contact with wafers....

20060105499 - Chip packaging systems and methods: An automated process for performing MEMS packaging including automatically attaching a die to a chip carrier, resulting in a chip carrier assembly, automatically moving the chip carrier assembly into a vacuum chamber, wherein the vacuum chamber includes one or more lids therein, automatically securing a lid to the chip carrier...

20060105500 - Process for fabricating chip embedded package structure: A process for fabricating a chip embedded package structure is provided. A stiffener is disposed on a tape. A chip is disposed on the tape inside a chip opening of the stiffener such that an active surface of the chip faces the tape. Through holes are formed passing the tape...

20060105501 - Electronic device with high lead density: An electronic device moldable to form a leadless electronic package and a method of forming the electronic device are provided. The electronic device comprises a die pad adapted for attachment of a die and a frame surrounding the die pad. A plurality of leads extend from the frame towards the...

20060105502 - Assembly process: An assembly process. The process includes providing a conductive substrate comprising opposing first and second surfaces, recessing the conductive substrate, forming a plurality of traces in the first surface, disposing an electronic device electrically connecting the traces, forming a patterned mask layer covering parts of the second surface of the...

20060105503 - Wafer-level sealed microdevice having trench isolation and methods for making the same: A microdevice (20) having a hermetically sealed cavity (22) to house a microstructure (26). The microdevice (20) comprises a substrate (30), a cap (40), an isolation layer (70), at least one conductive island (60), and an isolation trench (50). The substrate (30) has a top side (32) with a plurality...

20060105504 - Fabrication method of semiconductor integrated circuit device: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in...

20060105505 - Method for producing a semiconductor component and semiconductor component produced by the same: A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode....

20060105506 - Method of manufacturing a thin film transistor: A method of manufacturing a thin film transistor is described. A polysilicon island is formed over a substrate. A gate insulating layer is formed over the substrate to cover the polysilicin island. A gate is formed on the gate insulating layer above the polysilicon island. A passivation layer is formed...

20060105507 - Method to form si-containing soi and underlying substrate with different orientations: A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing...

20060105508 - Method of forming a semiconductor device: A method for integrating first and second type devices on a semiconductor substrate includes forming openings within an active semiconductor layer of a dual semiconductor-on-insulator in first and second regions of the semiconductor substrate. First and second non-MOS transistor device implant regions are formed within portions of an intermediate semiconductor...

20060105509 - Method of forming a semiconductor device: A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a non-MOS transistor device portion and the second region corresponds to...

20060105510 - Transistor or semiconductor device and method of fabricating the same: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive...

20060105513 - Device comprising doped nano-component and method of forming the device: A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising...

20060105511 - Method of manufacturing a mos transistor: A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region...

20060105512 - Method to improve drive current by increasing the effective area of an electrode: The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the...

20060105514 - Thin film semiconductor device and method of manufacturing the same: Two kinds of a thin film semiconductor unit are disposed over a substrate. A first thin film semiconductor unit includes a polycrystalline semiconductor thin film, and a second thin film semiconductor unit includes an amorphous semiconductor thin film....

20060105516 - Oxidation method for altering a film structure: A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed...

20060105515 - Process options of forming silicided metal gates for advanced cmos devices: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top...

20060105517 - Method in the fabrication of an integrated injection logic circuit: A method in the fabrication of an I2L circuit comprises (i) forming a common base of a lateral bipolar transistor and emitter of a vertical bipolar multicollector transistor, a common collector of the lateral transistor and base of the vertical multicollector transistor, and an emitter of the lateral transistor in...

20060105518 - Ultra-shallow arsenic junction formation in silicon germanium: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20)....

20060105519 - Dram on soi: In a semiconductor manufacturing process for a dynamic random access memory, a buried insulator layer such as a buried SIMOX layer between trench capacitors isolates the capacitor from the access transistor, limiting leakage, improving device performance and simplifying manufacturing....

20060105520 - Structure and method to fabricate a protective sidewall liner for an optical mask: Methods and structures for optical masks that have a liner on the trench sidewalls. An example embodiment comprises a mask structure for use with light at a wavelength comprising: a substrate having a first region, a second region and a third region; a first trench in the first region; a...

20060105521 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating layer corresponding to a capacitor forming region so that the lower electrode is not...

20060105523 - Chemical doping of nano-components: A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided for forming a field effect transistor comprising a nano-component that has been doped using such a dopant....

20060105525 - Method for forming non-volatile memory device: A method for forming a non-volatile memory device is provided. According to the method, a device isolation layer defining an active region is formed on the device isolation layer. An upper surface of the device isolation layer is formed higher than a surface of the substrate to form a gap...

20060105522 - Method of forming a nanocluster charge storage device: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer...

20060105524 - Non-volatile device manufactured using ion-implantation and method of manufacture the same: Embodiments of the invention include a non-volatile memory device manufactured using ion-implantation, and a method of manufacturing the same. A dielectric layer may be formed on a semiconductor substrate, and an ion implantation layer, which may be used as a charge trapping site, may be formed by ion implantation with...

20060105526 - Method of fabricating a bottle trench and a bottle trench capacitor: A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent...

20060105528 - High voltage mosfet having si/sige heterojunction structure and method of manufacturing the same: Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a...

20060105527 - Semiconductor device and manufacturing method therefor: A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film; forming a mask material so as to expose an upper surface of the first gate electrode while keeping...

20060105529 - Methods of forming mos transistors having buried gate electrodes therein: Methods of forming field effect transistors having buried gate electrodes include the steps of forming a semiconductor substrate having a sacrificial gate electrode buried beneath a surface of the semiconductor substrate and then removing the sacrificial gate electrode to define a gate electrode cavity beneath the surface. The gate electrode...

20060105530 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device with high-k materials. A high-k dielectric layer is formed on a substrate, followed by a fluorine-containing treatment of the high-k dielectric layer, forming an interface containing Si—F bonds....

20060105531 - Method of forming notched gate structure: A method of forming a notched gate structure comprising a semiconductor substrate having a first oxide layer formed thereon. A first conductive layer is formed on the semiconductor substrate. A portion of the first conductive layer and a portion of the first oxide layer are removed to form first gate...

20060105532 - Integrated circuit and method for manufacturing an integrated circuit on a chip: An integrated circuit and method for manufacturing an integrated circuit on a chip is provided, whereby a first bipolar transistor has a first collector region of a first conductivity type and a second bipolar transistor has a second collector region of the first conductivity type. The method includes the steps...

20060105533 - Method for engineering hybrid orientation/material semiconductor substrate: The embodiments provide a structure and a method of manufacturing a semiconductor structure that has a different material in the area where PMOS devices will be formed than in the area where NMOS devices will be formed which is characterized as follows. An embodiment comprises the following steps. A substrate...

20060105534 - High q factor integrated circuit inductor: An inductor and a method of forming and the inductor, the method including: (a) forming a dielectric layer on a top surface of a substrate; (b) forming a lower trench in the dielectric layer; (c) forming a resist layer on a top surface of the dielectric layer; (d) forming an...

20060105535 - Integrated circuit and method for manufacturing an integrated circuit on a semiconductor chip: An integrated circuit on a semiconductor chip is provided with a first bipolar transistor and a second bipolar transistor. The first bipolar transistor has a first collector region of a first conductivity type, grown by at least one epitaxial layer, and the second bipolar transistor has a second collector region...

20060105536 - Trench capacitor with hybrid surface orientation substrate: Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI arrays and logic transistors on (100) surface orientation silicon,...

20060105538 - Method for forming semiconductor device capable of preventing bunker defect: Disclosed is a method for preventing a bunker defect generation on a lower portion of a cylinder type metal bottom electrode. The method includes the steps of: forming an etch stop layer on a bottom structure with a conductive region and an insulation region; forming a capacitor insulation layer on...

20060105537 - Method for forming storage electrode of semiconductor device: A method for forming a storage electrode of a semiconductor device is provided, the method including forming an oxide film on a lower insulating layer disposed on a semiconductor substrate, forming a hard mask silicide layer pattern defining a strode electrode region on the oxide film, subjecting the hard mask...

20060105539 - Method of detecting etching end-point: A method of detecting an etching end-point includes the steps of: forming a mask on a pattern area of an etching object; forming an etching indicator on an etching area of the etching object, which is not covered by the mask; etching the etching object using the mask; and evaluating...

20060105540 - Method for manufacturing semiconductor element: A method for manufacturing a semiconductor element comprised of an SOI structure including an SOI layer comprises the steps of preparing the SOI layer having a transistor forming area and an element isolation area on a surface thereof, forming an oxidation-resistant mask layer on the surface of the SOI layer,...

20060105541 - Trench isolation method for semiconductor devices: A trench isolation method for semiconductor devices, the method includes the steps of: successively depositing a pad oxide film and a nitride film on a semiconductor substrate and then selectively removing the pad oxide film and the nitride film to form a mask pattern; forming trench regions in the semiconductor...

20060105542 - Method for fabricating and separating semiconductor devices: A method of fabricating and separating semiconductor structures comprises the steps of: (a) partially forming a semiconductor structure attached to a support structure, the partially formed semiconductor structure comprising a plurality of partially formed devices, where the partially formed devices are attached to one another by at least one connective...

20060105543 - Cmos-mems process: A fully CMOS compatible MEMS multi-project wafer process comprises coating a layer of thick photoresist on a wafer surface, patterning the photoresist to define a micromachining region, and performing a micromachining in the micromachining region to form suspended microstructures....

20060105545 - Methods for dicing a released cmos-mems multi-project wafer: Simple but practical methods to dice a CMOS-MEMS multi-project wafer are proposed. On this wafer, micromachined microstructures have been fabricated and released. In a method, a photoresist is spun on the full wafer surface, and this photoresist is thick enough to cover all cavities and structures on the wafer, such...

20060105544 - Protective film agent for laser dicing and wafer processing method using the protective film agent: A protective film agent for laser dicing according to the present invention comprises a solution having, dissolved therein, a water-soluble resin and at least one laser light absorber selected from the group consisting of a water-soluble dye, a water-soluble coloring matter, and a water-soluble ultraviolet absorber. The protective film agent...

20060105546 - Wafer dividing method: A method of dividing a wafer having a plurality of micro electro mechanical systems and a plurality of streets for partitioning the micro electro mechanical systems formed on the front surface of a wafer substrate, the method comprising a protective tape affixing step for affixing a protective tape to the...

20060105547 - Application of a thermally conductive thin film to a wafer backside prior to dicing to prevent chipping and cracking: A thermally conductive protective film or layer is applied to the backside surface of a semiconductor wafer prior to a subsequent dicing operation performed on the wafer to singulate the wafer into diced semiconductor chips, during which the thin thermally conductive film minimizes and prevents chipping and cracking damage to...

20060105548 - Substrate processing apparatus, program for performing operation and control method thereof, and computer readable storage medium storing the program: A computer readable storage medium storing a program for performing an operation method of a substrate processing apparatus is provided. The operation method includes the steps of introducing a nonreactive gas into the vacuum preparation chamber before the gate valve is opened while the substrate is transferred between the vacuum...

20060105549 - Manipulation of micrometer-sized electronic objects with liquid droplets: A system for manipulating a small object (3) comprising a substrate to receive the small object (3), a liquid droplet (4), which carries the small object (3) on the substrate, and a pre-treated surface structure of the substrate in the vicinity (1,2) of the placement position (1) of the small...

20060105550 - Method of depositing material on a substrate for a device: The present invention provides a method of depositing material on a substrate for a device. The method includes providing the substrate having a deformable surface. The method also includes imprinting a structure into the deformable surface in a manner such that a base surface and at least one projection is...

20060105551 - Method of manufacturing a polysilicon layer and a mask used therein: A method of manufacturing a polysilicon layer is provided. Firstly, a substrate is provided. Next, an amorphous silicon having a first region and a second region is formed on the substrate. After that, the amorphous silicon layer in the first region is completely melted and the amorphous silicon layer in...

20060105552 - Apparatus and method of activating impurity atom in manufacture of semiconductor device: An apparatus and a method of activating an impurity atom doped into a semiconductor material use of a resonant principle. Impurity atoms are doped into the semiconductor material, and microwaves having the same frequency as a natural frequency of vibration of the impurity are applied to the semiconductor material. The...

20060105553 - Reversible oxidation protection of microcomponents: In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to protect it against oxidation, an insulation layer is applied to the silicon nitride layer, and a reoxidation process is carried out. In the reoxidation...

20060105554 - Method for solid phase diffusion of zinc into an inp-based photodiode and an inp photodiode made with the method: In order to form a p-region in an InP-based photodiode, zinc doping must be performed. Due to the current trend toward the implementation of larger-sized InP wafers, there is a need for a solid phase diffusion method in which a ZnO thin film is applied to an epitaxial wafer, the...

20060105555 - Display apparatus and control method thereof: A gantry apparatus includes a pair of first guides disposed parallely each other, a pair of sliders respectively coupled to the pair of first guides to move together with the first guides; a second guide coupled to the pair of sliders to move along the sliders; a head coupled to...

20060105556 - Semiconductor device and method of manufacturing the same: The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due...

20060105557 - Method of making fully silicided gate electrode: A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon...

20060105558 - Inter-metal dielectric scheme for semiconductors: System and method for providing an inter-metal dielectric that prevents or reduces film delamination and contact corrosion defects is provided. A preferred embodiment comprises forming a chemical-mechanical polishing (CMP) stop layer over the surface of an inter-metal dielectric prior to forming interconnects and vias. Interconnect and vias may be formed...

20060105559 - Ultrathin buried insulators in si or si-containing material: A method for forming an ultra thin buried oxide layer is described incorporating the steps of forming a first epitaxial layer containing Si on a Si containing substrate having a thickness from about 10 to about 300 angstroms thick, forming a second epitaxial layer containing Si having a thickness from...

20060105560 - Method for forming solder bumps of increased height: A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is...

20060105561 - Method of manufacturing a self-aligned contact structure: The present invention provides a method of manufacturing a self-aligned contact structure comprising a semiconductor substrate having at least two gate stack structures formed thereon. A dielectric layer is formed over the gate stack structures. Each gate stack structure has a nitride layer surface. A portion of the dielectric layer...

20060105562 - Method to make nano structure below 25 nanometer with high uniformity on large scale: A method of making a nano structure smaller than 25 nanometers utilizing atomic layer deposition, planarizing, and etching techniques....

20060105564 - Method and system for reducing inter-layer capacitance in integrated circuits: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer....

20060105563 - Method of forming a semiconductor device: A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding dishing above the semiconductor device during chemical mechanical polishing. The...

20060105565 - Method and apparatus for copper film quality enhancement with two-step deposition: The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for a duration of time to remove any impurities, depositing...

20060105567 - Method for forming a dual-damascene structure: A dual-damascene structure is formed in a porous dielectric material using an anti-reflective coating. In accordance with one embodiment, during patterning and etching if the trench portions of the dual-damascene structure, the anti-reflective coating has a first density. After patterning and etching, the anti-reflective coating density is reduced. The reduction...

20060105566 - Ultraviolet assisted pore sealing of porous low k dielectric films: Processes for sealing porous low k dielectric film generally comprises exposing the porous surface of the porous low k dielectric film to ultraviolet (UV) radiation at intensities, times, wavelengths and in an atmosphere effective to seal the porous dielectric surface by means of carbonization, oxidation, and/or film densification. The surface...

20060105568 - Plasma treatment for surface of semiconductor device: A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about...

20060105569 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is disclosed. The method for manufacturing a semiconductor device provides performing the CMP process using the acid slurry for metal during formation of the landing plug to minimize the step difference....

20060105570 - Copper interconnect wiring and method of forming thereof: Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods of forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and the use...

20060105571 - Pneumatic method and apparatus for nano imprint lithography: A method (and apparatus) for nano lithography, includes applying a pneumatic pressure to at least one of a surface of a semi-rigid mask or template and a portion of a surface of a resist-coated workpiece, and, by the applying of the pneumatic pressure, transferring a pattern from the mask to...

20060105573 - Method for selective plasma etch of an oxide layer: The present invention provides, in one embodiment, a method of forming an opening in a dielectric layer 150. In this embodiment, the method comprises forming a dielectric layer 150 over a target layer 130 located over a microelectronic substrate 110 and subjecting the dielectric layer 150 to a plasma etch...

20060105574 - Process for defining integrated circuits in semiconductor electronic devices: A process for the definition of integrated circuits on a wafer having at least one silicon semiconductor layer includes masking the wafer with a photoresist layer. The process includes a development step of the photoresist with definition of a lithographic pattern, a hardening step of the photoresist with a plasma...

20060105575 - Small volume process chamber with hot inner surfaces: A system and method of processing a substrate including loading a substrate into a plasma chamber and setting a pressure of the plasma chamber to a pre-determined pressure set point. Several inner surfaces that define a plasma zone are heated to a processing temperature of greater than about 200 degrees...

20060105572 - Via reactive ion etching process: Methods of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor. The methods include the provision of tetrafluoro methane (CF4) in a photoresist strip. In addition, the methods may provide an increased amount of tetrafluoro methane (CF4) in a dielectric...

20060105576 - High ion energy and reative species partial pressure plasma ash process: A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than...

20060105577 - Aspect ratio controlled etch selectivity using time modulated dc bias voltage: A modulated bias power etching method for etching a substrate is disclosed. The method alternatively deposits and etches material from a low aspect area of an integrated circuit device to form a static area while etching material from a high aspect area. The modulation pulse period and repetition rate are...

20060105578 - High-selectivity etching process: The present invention provides a high-selectivity etching process for fabricating openings for a contact structure or a dual damascene structure in combination with a Si-rich silicon oxynitride (SiON) barrier layer. The process of this invention is suitable for forming at least an opening for a dual damascene opening or a...

20060105579 - Etchant for etching metal wiring layers and method for forming thin film transistor by using the same: The present invention discloses an etchant for etching at least two different metal layers, the etchant comprising hydrogen peroxide (H2O2) and one of carboxylic acid, carboxylate salt, and acetyl group (CH3CO—). The present invention also discloses a method of fabricating a metal wiring on a substrate, the method comprising forming...

20060105580 - Method and apparatus for thermally processing microelectronic workpieces: An apparatus for thermally processing a microelectronic workpiece is provided. The apparatus comprises a rotatable carousel assembly configured to support at least one workpiece. A driver is coupled to the carousel assembly and rotates the carousel assembly, moving the workpiece between a loading station, a heating station and a cooling...

20060105581 - Glycol doping agents in carbon doped oxide films: A method for forming a carbon doped oxide (CDO) film comprises doping an organosilane precursor material with a glycol material and using the doped organosilane precursor material in a deposition process to form the CDO film. The glycol material may be propylene glycol (PD). The PD-doped CDO films formed using...

20060105582 - Semiconductor device and method for fabricating same: A method is provided with: arranging nitrogen atoms on a surface of a silicon substrate; performing a heat treatment in a hydrogen atmosphere so that the nitrogen atoms and silicon atoms existing on the surface of the silicon substrate are brought into a three-coordinate bond state; and forming a silicon...

20060105583 - Formation technology of nano-particle films having low dielectric constant: A method for forming a low dielectric constant film includes the steps of: introducing reaction gas comprising an organo Si gas and an inert gas into a reactor of a capacitively-coupled CVD apparatus; adjusting a size of fine particles being generated in the vapor phase to a nanometer order size...

20060105585 - Autofocus for high power laser diode based annealing system: Apparatus for thermally processing a substrate includes a source of laser radiation comprising a plurality diode lasers arranged along a slow axis, optics directing the laser radiation from the source to the substrate, and an array of photodetectors arranged along a fast axis perpendicular to the slow axis and receiving...

20060105584 - Device and method for thermally treating semiconductor wafers: A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatment chamber receiving the substrate, with at least...

20060099723 - Compositions for removal of processing byproducts and method for using same: A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The non-aqueous composition includes a non-aqueous solvent and one or more components including a fluoride compound and a pyridine compound. The semi-aqueous composition includes glacial acetic acid and one...

20060099722 - Ferroelectric memory and its manufacturing method: A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode successively laminated; (c) forming a conductive hard mask above...

20060099724 - Memory cell with buffered layer: A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor...

20060099725 - Semiconductor device and process for producing the same: A semiconductor device is manufactured by the steps of generating a film forming gas by setting a flow rate ratio of H2O to any one of a silicon-contained organic compound having a siloxane bond and a silicon-contained organic compound having a CH3 group to 4 or more and adjusting a...

20060099726 - Capacitance detection type sensor and manufacturing method thereof: Capacitance sensor electrodes are arranged in a form of matrix on a semiconductor substrate and coated with a cover film. These capacitance sensor electrodes are connected to a drive circuit. ESD electrodes are arranged in the vicinities of corner portions of the capacitance sensor electrodes. Each ESD electrode is composed...

20060099727 - Method of making a circuitized substrate having a plurality of solder connection sites thereon: A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different...

20060099728 - Method of manufacturing a substrate structure for increasing cutting precision and strength thereof: A method of manufacturing a substrate structure includes the steps of: (1) providing a metal substrate having a metal portion; (2) chemically etching a plurality of trenches in the metal substrate; (3) applying a polymer composite material into the trenches to form a substrate having a polymer composite portion abutted...

20060099729 - Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern: Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited...

20060099730 - Method of fabricating vertical structure leds: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate,...

20060099732 - Field effect transistor and method of producing the same: A field effect transistor having a high field effect mobility is provided which can be obtained by a simple method. The field effect transistor includes an organic semiconductor layer composed of a crystallized film of a naphthoporphyrin compound represented by formula (2), which is obtained by the conversion by heating...

20060099731 - Method of patterning a functional material on to a substrate: A method of patterning a functional material (150) onto a substrate (100) comprises the steps of (a) applying a layer of protective material (130), soluble in a solvent in which the functional material is insoluble, to at least one major surface of said substrate; (b) removing areas of said layer...

20060099733 - Semiconductor package and fabrication method: The present invention provides a first wafer and a second wafer having a device. A separation layer is formed on the first wafer. A cap is formed on the separation layer. The cap and the second wafer are bonded using a gasket. The first wafer is separated from the cap...

20060099734 - Cpu power delivery system: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout....

20060099735 - Method for wafer level stack die placement: A method for wafer level stack die placement is disclosed. At first, a wafer including a plurality of dice is provided. The wafer is adhered to a photosensitive adhesive tape. The wafer is attached on a die carrier to fix at least one die from the wafer on the die...

20060099736 - Flip chip underfilling: A method of underfilling an integrated circuit that is mounted to a first side of a package substrate having an opposing second side. A void is provided, which extends completely through the package substrate and is disposed under the integrated circuit. The package substrate is disposed with the second side...

20060099737 - Flip-chip semiconductor device utilizing an elongated tip bump: A flip-chip type semiconductor device includes a semiconductor chip having electrode pads formed and arranged on a chip surface thereof. Sprout-shaped metal bumps are bonded to the electrode pads on the chip, and an adhesive resin layer is formed on the chip surface of the chip such that tip ends...

20060099738 - Semiconductor device and method for manufacturing the same, and electric appliance: The present invention provides a semiconductor device having a plurality of functions and a method for manufacturing the semiconductor device. The semiconductor device comprises a thin film integrated circuit, a first substrate having a sensor or an antenna, and a second substrate having an antenna, wherein the thin film integrated...

20060099739 - Semiconductor device and method of manufacture thereof, circuit board and electronic instrument: A method of manufacturing a semiconductor device includes (a) interposing an adhesive between a surface of a substrate on which an interconnect pattern is formed and a surface of a semiconductor chip on which electrodes are formed; and (b) applying pressure between the semiconductor chip and the substrate, and covering...

20060099741 - Fabricating surface mountable semiconductor components with leadeframe strips: The invention relates to a method for producing an electrical leadframe (10), in particular for a light-emitting diode component, having at least one first electrical connection conductor (2) and at least one second electrical connection conductor (3)....

20060099740 - High density direct connect loc assembly: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces...

20060099742 - Electronic device and method of manufacturing same: The electronic device (100) is a chip-on-chip construction on a lead frame (10) comprising a heat sink (13) in an encapsulation (80). The first chip (20) and the second chip (30) are mutually connected by first conductive interconnections (24) and the first chip (20) is connected to the lead frame...

20060099743 - Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method: A method of fabricating a chalcogenide memory cell is described. The cross-sectional area of a chalcogenide memory element within the cell is controlled by the thickness of a bottom electrode and the width of a word line. The method allows the formation of ultra small chalcogenide memory cells....

20060099744 - System and method for improved dopant profiles in cmos transistors: According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first recess is formed in an outer...

20060099745 - Method for forming integrated advanced semiconductor device using sacrificial stress layer: An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a...

20060099746 - Mask reduction of lpts-tft array by use of photo-sensitive low-k dielectrics: The present invention discloses a method of mask reduction of low-temperature polysilicon thin film transistor array by use of photo-sensitive low-K dielectric, which comprises the steps of: defining a polysilicon-island on a preprocessed glass substrate; forming a gate oxide layer and a first metal layer in sequence; patterning the first...

20060099747 - Thin film etching method and method of fabricating liquid crystal display device using the same: A thin film etching method includes forming a layer on a substrate, aligning a mask having a pattern defined thereon above the layer, and removing a portion of the layer by irradiating the substrate with a femtosecond laser through the mask....

20060099748 - Method for fabricating semiconductor device: After the implantation of fluorine ions into a semiconductor substrate, a gate insulating film, a gate electrode and a protective film are formed on the semiconductor substrate. Thereafter, fluorine ions are again implanted into the semiconductor substrate. Furthermore, p-type source/drain extension regions and source/drain regions are formed in the semiconductor...

20060099749 - Semiconductor device and method of fabricating the same: According to the present invention, there is provided a semiconductor device having: first and second fins formed on a semiconductor substrate to oppose each other, and made of a semiconductor layer; an active region which is formed on the semiconductor substrate so as to be connected to the first and...

20060099750 - Patterned thin film graphite devices and method for making same: In a method of making graphite devices, a preselected crystal face of a crystal is annealed to create a thin-film graphitic layer disposed against selected face. A preselected pattern is generated on the thin-film graphitic layer. A functional structure includes a crystalline substrate having a preselected crystal face. A thin-film...

20060099751 - Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method: An RF amplifier circuit 21 for amplifying AM broadcast signals is constituted by use of cascaded P channel MOSFETs 4 and 5. This cascade connection realizes a reduction of the feedback capacitance between the source and gate of the P channel MOSFET 4, thereby providing a stable operation. Further, using...

20060099752 - Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor...

20060099753 - Method of forming devices having three different operation voltages: The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a deep well encompassing the LV region and the MV region is formed in the substrate. Afterward, a...

20060099754 - Light guiding device: A light emitting end face side front end part of an optical fiber bundle 16 is covered by a sleeve member 13 and an emitting part outer cover 14. A glass rod holding member 42, which holds a glass rod 40, is mounted to emitting part outer cover 14. Glass...

20060099756 - Methods of forming non-volatile memory device having floating gate: Embodiments of the present invention are directed to methods for forming non-volatile memory devices. A substrate is provided that has a cell region, a first peripheral region, and second peripheral region. A tunnel insulating layer is formed on the substrate in the cell region. A preliminary floating gate is formed...

20060099755 - Semiconductor memory integrated circuit and its manufacturing method: A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage...

20060099757 - Method of fabricating a bipolar junction transistor: A method for fabricating a bipolar junction transistor on a wafer is disclosed. The wafer has a N-type doped area and a plurality of isolated structures. A protection layer is formed on the wafer and portions of the protection layer are then removed to expose portions of the doped area....

20060099758 - Iridium oxide nanotubes and method for forming same: A method is provided for forming iridium oxide (IrOx) nanotubes. The method comprises: providing a substrate; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; introducing oxygen as a precursor reaction gas; establishing a final pressure in the range of 1 to 50 Torr; establishing a substrate, or chamber temperature in the range of 200...

20060099759 - Pattern formation method and pattern formation apparatus, method for manufacturing device, electro-optical device, electronic device, and method for manufacturing active matrix substrate: A pattern formation method for forming a film pattern upon a substrate, including the steps of: forming banks in a predetermined pattern upon the substrate; disposing liquid drops of a functional liquid at the end portions of groove portions which are defined between the banks; and after having disposed the...

20060099760 - Storage capacitors for semiconductor devices and methods of forming the same: Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening therethrough on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to...

20060099761 - Dual-damascene process to fabricate thick wire structure: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch...

20060099762 - Method for manufacturing mosfet device in peripheral region: Disclosed is a method for manufacturing a MOSFET device in a peripheral region capable of avoiding degradation of electrical characteristics of the MOSFET device in the peripheral region. The method stabilizes the characteristics of the MOSFET device in the peripheral region by forming a MOSFET device selectively having a recess...

20060099763 - Method of manufacturing semiconductor mos transistor device: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface....

20060099764 - Method of fabricating a lateral double-diffused mosfet (ldmos) transistor: A method of monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow....

20060099765 - Method to enhance cmos transistor performance by inducing strain in the gate and channel: A method of manufacturing complementary metal oxide semiconductor transistors forms different types of transistors such as N-type metal oxide semiconductor (NMOS) transistors and P-type metal oxide semiconductor (PMOS) transistors (first and second type transistors) on a substrate. The method forms an optional oxide layer on the NMOS transistors and the...

20060099766 - Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance: In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion...

20060099767 - Method of fabricating heterojunction bipolar transistor: Provided is a method of fabricating a heterojunction bipolar transistor (HBT). The method includes: sequentially depositing a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer on a substrate; forming an emitter electrode on the emitter capping layer; forming a mesa type emitter...

20060099768 - Method of manufacturing a capacitor: A method of manufacturing a stack capacitance type capacitor is provided, which prevents the problem that the capacitor cannot be formed because a lower electrode collapses with the external wall thereof exposed in forming the lower electrode of the capacitor in a deep hole formed in silicon oxide, and removing...

20060099769 - Method for forming capacitor of semiconductor device: Disclosed is a method for forming a capacitor of a semiconductor device, which can ensure charging capacity required as well as an excellent leakage current characteristic. In such a method, a storage electrode consisting of TiN is formed on a semiconductor substrate. Then, a first HfO2 thin film, an HfxAlyOz...

20060099770 - Semiconductor article and method for manufacturing the semiconductor article: A method for manufacturing a semiconductor article and a semiconductor article is provided, wherein a base region of a first semiconductor material is applied, a silicide layer is applied above the base region, after the application of the silicide layer, an opening is created in the suicide layer by removing...

20060099771 - Selective nitride liner formation for shallow trench isolation: A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said...

20060099773 - Fabrication of a low defect germanium film by direct wafer bonding: A method of fabricating a low defect germanium thin film includes preparing a silicon wafer for germanium deposition; forming a germanium film using a two-step CVD process, annealing the germanium thin film using a multiple cycle process; implanting hydrogen ions; depositing and smoothing a layer of tetraethylorthosilicate oxide (TEOS); preparing...

20060099772 - Method with mechanically strained silicon for enhancing speed of integrated circuits of devices: A method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices is disclosed. The method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices includes the following steps: (a) providing a substrate, (b) fixing the substrate, (c) applying a stress...

20060099774 - Method of laser processing a gallium nitride substrate: A method of laser processing a gallium nitride substrate, for forming a dividing groove along dividing lines that section devices formed on a gallium nitride substrate, the method comprising the step of applying a pulse laser beam having a wavelength of 200 to 365 nm along the dividing lines that...

20060099775 - Crack stop for low k dielectrics: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC...

20060099777 - Method of fabricating single-crystal silicon film and method of fabricating tft adopting the same: A method for forming a single-crystal silicon film of high quality is provided. The method includes the operations of: growing single-crystal silicon to a predetermined thickness of a crystal growth plate; depositing a buffer layer on the single-crystal silicon layer; forming a partition layer at a predetermined depth in the...

20060099776 - Methods for fabricating compound material wafers: Methods for fabricating compound material wafers are described. An embodiment of the method includes providing a donor substrate having a surface, forming a weakened zone in the donor substrate to define a transfer layer that includes the donor substrate surface, bonding the surface of the transfer layer to a handle...

20060099778 - Method of preparing semiconductor film on a substrate: A method of preparing a semiconductor film on a substrate is disclosed. The method includes arranging an insulating substrate in a deposition chamber and depositing a semiconductor film onto the insulating substrate using ion beam deposition, wherein a temperature of the insulating substrate during the depositing does not exceed 250°...

20060099779 - Method for transferring a thin layer including a controlled disturbance of a crystalline structure: The present invention relates to a method for transferring a thin useful layer from a donor substrate having an ordered crystalline structure to a receiver substrate. The method includes creation of a weakened zone in the donor substrate to define the layer to be transferred from the donor substrate. The...

20060099780 - Method for fabricating a semiconductor device: Concentration of metal element which promotes crystallization of silicon and which exists within a crystalline silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is performed after introducing nickel to an amorphous silicon film 103. Then, laser light is irradiated to diffuse nickel...

20060099781 - Method for producing by vapour-phase epitaxy a gallium nitride film with low defect density: The invention concerns a method for preparing gallium nitride films by vapour-phase epitaxy with low defect densities. The invention concerns a method for producing a gallium nitride (GaN) film from a substrate by vapour-phase epitaxy deposition of gallium nitride. The invention is characterized in that the gallium nitride deposition comprises...

20060099782 - Method for forming an interface between germanium and other materials: Interfaces that are portions of semiconductor structures used in integrated circuits and optoelectronic devices are described. In one instance, the semiconductor structure has an interface including a semiconductor surface, an interfacial layer including sulfur, and an electrically active layer (e.g., a dielectric or a metal). Such an interface can inhibit...

20060099783 - Self-aligned low-k gate cap: A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric...

20060099784 - Semiconductor device manufacturing method: A semiconductor device manufacturing method is provided in which, in the dummy gate pattern formation process, the pattern formation process is simplified and costs are reduced. A semiconductor device manufacturing method including: forming a mask element on a substrate; patterning the mask element into a prescribed shape, and forming a...

20060099786 - Copper interconnect structure with modulated topography and method for forming the same: A copper interconnect structure used in semiconductor devices includes surfaces having a surface roughness greater than 20 angstroms and which may be greater than 100 angstroms. The conformal surface of the copper interconnect structure confronts a surface roughened by ion bombardment. The copper interconnect structure is resistant to electromigration and...

20060099785 - De-fluorination after via etch to preserve passivation: Novel interconnect structures possessing a dense OSG material for 90 nm and beyond BEOL technologies in which a low power density oxygen-based de-fluorination plasma process is utilized to increase NBLoK selectivity are presented. These BEOL interconnect structures are capable of delivering enhanced reliability and performance due to the reduced risk...

20060099788 - Injection molded metal bonding tray for integrated circuit device fabrication: An injection molded metal bonding tray may be utilized in the fabrication of integrated circuit devices. In one embodiment, a substrate of an integrated circuit device is placed in a pocket of an injection molded metal bonding tray. A plurality of conductors is placed on the substrate and the conductors...

20060099787 - Method for damascene formation using plug materials having varied etching rates: Methods for forming openings in damascene structures, such as dual damascene structures are provided, using plug materials having varied etching rates. In one embodiment, a semiconductor substrate is provided with a low-k material layer formed thereabove, the low-k material layer having an upper surface and at least one via opening...

20060099791 - Bonded wafer and method of producing bonded wafer: The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal plane orientation of {100}. The present...

20060099790 - Method of implanting at least one solder bump on a printed circuit board: A method of implanting at least one solder bump on a surface of a printed circuit board (PCB) on which at least one soldering pad is exposed since the solder bump intended to be formed thereon is missing is described. The method comprises the steps of: first, forming at least...

20060099789 - Micro lead frame packages and methods of manufacturing the same: Microelectronic packages include a microelectronic element and portions of a lead frame disposed beneath the microelectronic element. The lead frame may be laminated with a dielectric element and the resulting laminate may be punched to remove the bus bar included in the lead frame, thereby forming an in-process unit having...

20060099792 - Tolerance bondwire inductors for analog circuitry: Disclosed are wirebonding methods wherein bondwires are positioned using dynamically determined variations in die placement. Preferred methods of the invention include steps for placing a die on the prepared substrate using selected ideal placement coordinates. Deviation of the actual die placement from the selected ideal placement coordinates is monitored, and...

20060099793 - Contact for dual liner product: A structure is provided which includes a semiconductor device region including a first portion and a second portion. A current-conducting member is provided, which extends horizontally over the first portion but not over the second portion. A first film, such as a stress-imparting film, extends over the second portion and...

20060099795 - I-shaped and l-shaped contact structures and their fabrication methods: Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the...

20060099797 - Integrated circuits with contemporaneously formed array electrodes and logic interconnects: The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting...

20060099794 - Interconnect structure to reduce stress induced voiding effect: An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce...

20060099796 - Method of forming a multi-layer semiconductor structure having a seam-less bonding interface: A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined...

20060099798 - Semiconductor device and manufacturing method of the same: Disclosed is a method of manufacturing a semiconductor device, including the steps of: forming on a second insulating film a first resist pattern having a first window; employing the first resist pattern as an etching mask to form first openings exposed from contact regions CR; forming, on a second conductive...

20060099799 - Plasma processing method and film forming method: A plasma processing method of carrying out curing processing on a low dielectric constant film produced on a to-be-processed substrate by applying plasma thereto in a processing chamber of a plasma processing apparatus, includes the steps of: a) introducing, in the plasma processing chamber, a first gas having a function...

20060099800 - Method for fabricating low leakage interconnect layers in integrated circuits: A method for fabricating a low leakage integrated circuit structure. An antireflective layer is disposed without intervening layers directly onto the top of an interconnect conductor, and a dielectric layer is disposed over the antireflective layer. The interconnect conductor is aluminum; the antireflective layer is titanium nitride, and the antireflective...

20060099802 - Diffusion barrier for damascene structures: A semiconductor structure having a via formed in a dielectric layer is provided. The exposed pores of the dielectric material along the sidewalls of the via are partially or completely sealed. Thereafter, one or more barrier layers may be formed and the via may be filled with a conductive material....

20060099801 - Method and structure to wire electronic devices: An integrated circuit structure and a method of manufacturing, wherein the method comprises forming a first via in an interconnect layer of the substrate, wherein the first via comprises a first size diameter; and forming a second via in the interconnect layer, wherein the second via comprises a second size...

20060099803 - Thin film capacitor: A method including forming a barrier material on a surface of an electrode of a capacitor structure; forming a ceramic material on the electrode material; and annealing the ceramic material, wherein the barrier material comprises a material having a property that inhibits the oxidation of a material for the electrode...

20060099804 - Post-polish treatment for inhibiting copper corrosion: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as...

20060099805 - Heat treating system and heat treating method: A thermal processing unit of the present invention includes: a holder that holds a plurality of substrates; a reaction container into which the holder is conveyed; a process-gas supplying mechanism that supplies a process gas into the reaction container; and a heating mechanism that heats the reaction container to conduct...

20060099806 - Method of forming electrode for compound semiconductor device: Provided is a method of forming an electrode for a compound semiconductor device. The method includes forming a first electrode layer on a p-type compound semiconductor layer, and performing plasma treatment on the first electrode layer in an oxygen (O2)-containing atmosphere....

20060099807 - Methods for fabricating one or more metal damascene structures in a semiconductor wafer: Methods for fabricating one or more metal (e.g., copper) damascene structures in a semiconductor wafer use at least three polishing steps to reduce erosion topography in the resulting metal damascene structures and/or increase throughput. The polishing steps may be performed at four polishing units of a polishing apparatus, which may...

20060099808 - Electric viscous fluid device and electronic equipment: An electrorheological fluid device and an electronic apparatus, which realize various hardness or tension in a portion of the device or apparatus to which a human body touches, enabling application to a product that needs to have portability. An electrorheological fluid device is formed by including: a container capable of...

20060099809 - Method of flip-chip mounting a semiconductor chip and mounting apparatus using the same: A method of flip-chip mounting a semiconductor chip can carry out bonding at normal temperature and improves the positional accuracy of bonding. The method of flip-chip bonding a semiconductor chip 52 includes a step of providing a hardening trigger that is not heat to insulating adhesive 51 either before the...

20060099810 - Laser micromachining method: A laser micromachining method is disclosed wherein a workpiece is milled using an incident beam from a laser beam focused above the surface of the workpiece. The incident beam is guided by a plasma channel generated by the incident beam. The plasma channel, which has a relatively constant diameter over...

20060099811 - Method for structuring of silicon substrates for microsystem technological device elements and associated silicon substrate: A method for structuring of silicon substrates for microsystem technological device elements, wherein the silicon substrate is covered with an etching mask and wherein the structures are furnished with a predetermined etching profile in the micrometer region with side walls and an etching depth At. For the generation of a...

20060099812 - Semiconductor device and method of fabricating a semiconductor device: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation....

20060099813 - Chemical mechanical polish of pcmo thin films for rram applications: A method of fabricating a CMR layer in a CMOS device using CMP to pattern the CMR layer includes preparing a silicon substrate, including fabrication of a bottom electrode in the silicon substrate; depositing a layer of SiNx on the substrate; patterning and etching the SiNx layer to form a...

20060099814 - Polishing composition and method for high silicon nitride to silicon oxide removal rate ratios: The invention provides a chemical-mechanical polishing composition comprising a cationic abrasive, a cationic polymer, a carboxylic acid, and water. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition. The polishing composition exhibits selectivity for removal of silicon nitride over removal of silicon oxide....

20060099815 - Cooling system for a semiconductor device and method of fabricating same: A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a...

20060099816 - System and method for plasma induced modification and improvement of critical dimension uniformity: Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved...

20060099817 - Novel slurry for chemical mechanical polishing of metals: A slurry for removing metals, useful in the manufacture of integrated circuits generally, and for the chemical mechanical polishing of noble metals particularly, may be formed by combining periodic acid, an abrasive, and a buffer system, wherein the pH of the slurry is between about 4 to about 8....

20060099818 - Dual-tank etch method for oxide thickness control: A dual-tank etch method which is suitable for the stripping of a silicon nitride layer from a pad oxide layer provided on a substrate, and etching of the pad oxide layer to a desired target thickness, is disclosed. The method includes providing a first processing tank containing a silicon nitride-stripping...

20060099823 - Active area bonding compatible high current structures: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively...

20060099821 - Apparatus for detecting an amount of strain and method for manufacturing same: An apparatus for detecting an amount of strain comprises a strain generating part, an electrical insulating layer and sensing elements. The strain generating part is a member to which strain is to be applied. The electrical insulating layer is formed on the strain generating part. The sensing elements are formed...

20060099820 - Deposition method and apparatus: A deposition method and apparatus provide a uniform deposition rate and good reproducibility in a process used to deposit a material onto a substrate. The deposition method includes preparing a substrate on which a thin film is deposited, preparing a line source that includes a plurality of heating crucibles are...

20060099824 - High density plasma chemical vapor deposition process: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be...

20060099819 - Low dielectric constant compositions and methods of use thereof: Low dielectric compositions and methods of use thereof in integrated circuits are disclosed. The low dielectric compositions are derived from carbosilane polymers and oligomers containing imbedded sila- or disilacyclobutane rings and, after heating to induce cross-linking, may be used as an interlayer dielectric as well as a capping layer within...

20060099822 - Method of making a memory cell: An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material....

20060099825 - Quantum device, manufacturing method of the same and controlling method of the same: By bringing a tip of an AFM into contact with the surface of a GaAs substrate or an AlGaAs substrate, for example, applying a negative bias to the tip, and applying a positive bias to the GaAs substrate or the AlGaAs substrate, a donut-shaped oxide film is formed. Then, the...

20060099826 - Method of forming an insulation film and semiconductor device having the insulation film: In a method which forms an insulation film using ALD (Atomic Layer Deposition) and which includes a first step of forming deposited silicon atoms on an objective surface by depositing silicon atoms on the objective surface and a second step of forming a nitride film as the insulation film by...

20060099827 - Photo-enhanced uv treatment of dielectric films: A dielectric or oxide layer, such as a thin gate oxide, is formed by supplying a wafer in a processing chamber with thermal energy to heat the wafer and light energy, such as ultraviolet light, to improve the quality of the resulting layer....

20060099829 - Photoresist application over hydrophobic surfaces: A method of forming a layer of photoresist 28 over a surface 30 of a semiconductor wafer 10 by forming a layer of pre-wet solvent 52 over the surface 30 and forming the layer of photoresist 28 over the layer of pre-wet solvent 52. Also, a layer of photoresist 28...

20060099828 - Semiconductor process and photoresist coating process: A semiconductor process is disclosed, wherein before photoresist is coated on a substrate, a chemical is applied to dampen the substrate. Further, the chemical is applied on the substrate while the substrate is kept in a spinning state. In addition, a photoresist coating process is also provided. Wherein, a substrate...

20060099830 - Plasma implantation using halogenated dopant species to limit deposition of surface layers: Methods and apparatus for plasma implantation of a workpiece, such as a semiconductor wafer, are provided. A method includes introducing into a plasma doping chamber a dopant gas selected from the group consisting of PF3, AsF3, AsF5 and mixtures thereof, forming in the plasma doping chamber a plasma containing ions...

20060099831 - Silicon source reagent compositions, and method of making and using same for microelectronic device structure: A method of synthesizing an aminosilane source reagent composition, by reacting an aminosilane precursor compound with an amine source reagent compound in a solvent medium comprising at least one activating solvent component, to yield an aminosilane source reagent composition having less than 1000 ppm halogen....

20060099832 - System and method for determining line widths of free-standing structures resulting from a semiconductor manufacturing process: A apparatus and method for determining minimum line widths of free standing structures built by a semiconductor (S/C) manufacturing process. Free standing structures are created in a semiconductor device and subjected to an aerosol process which is tuned and centered with respect to a critical line width for the free...

20060094130 - Method for manufacturing a magnetic memory device, and a magnetic memory device: In bit line cladding structure formation, stability and margin of the process are secured and further shrinking is achieved, and the magnetic memory device is improved in speed, reliability and yield. Method for manufacturing a magnetic memory device, comprising the steps of: forming a word line; forming a magnetoresistance effect...

20060094129 - Methods of making a current-perpendicular-to-the-planes (cpp) type sensor by ion milling to the spacer layer using a mask without undercuts: Methods for use in forming current-perpendicular-to-the-planes (CPP) type sensors, including CPP giant magnetoresistance (GMR) type and CPP magnetic tunnel junction (MTJ) type sensors are disclosed. In one particular example, a plurality of CPP type sensor layers are formed over a wafer and a mask without undercuts is formed over the...

20060094133 - Method and apparatus for measuring surface carrier recombination velocity and surface fermi level: A pump beam irradiates the surface of a semiconductor sample through modulator while irradiating the surface with a probe beam so that a detector measures a light-modulated spectrum of the probe beam reflected from the surface of the semiconductor sample. Then, surface electric field strength is calculated from the period...

20060094132 - Method for analyzing the structure of deep trench capacitors and a preparation method thereof: A method for analyzing the structure of deep trench capacitors and a preparation method thereof are described. A protective layer is formed on a selected inspection area. Overlying circuit layers and an upper portion of a substrate, surrounding the selected inspection area, of the die are removed. A chemical etchant...

20060094135 - Method of making semiconductor devices: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed...

20060094134 - Method of manufacturing inspection unit: A conductive member having a first face adapted to be mounted on a board on which an inspection circuit is arranged, and a second face adapted to be opposed to a device to be inspected is prepared. The conductive member is formed with a first through hole having a first...

20060094131 - System and method for critical dimension control in semiconductor manufacturing: Provided are a system and method for modifying a fabrication process based on inline measurement information during manufacture of a semiconductor device. In one example, the method includes exposing a photoresist layer on the device, performing post-exposure baking on the photoresist layer, and obtaining at least one critical dimension (CD)...

20060094136 - Evaluation of openings in a dielectric layer: A patterned dielectric layer is evaluated by measuring reflectance of a region which has openings. A heating beam may be chosen for having reflectance from an underlying conductive layer that is several times greater than absorptance, to provide a heightened sensitivity to presence of residue and/or changes in dimension of...

20060094137 - Method of manufacturing ceramic led packages: Methods of forming LED packages and light emitting devices are provided. LED packages and light emitting devices are preferably formed from ceramic layers, such as AlN, though layers of non-ceramic materials can also be used. The layers are formed to include vias, apertures, and metallization layers. The layers are then...

20060094140 - Manufacturing method for semiconductor light emitting device: A manufacturing method for a semiconductor light emitting device is provided. The method includes preparing a first wafer in which at least one semiconductor layer including the emitter layer is formed; disposing a second wafer transparent to an emission wavelength of the emitter layer on the surface of the first...

20060094139 - Method for making a semiconductor light emitting device: A method for making a semiconductor light emitting device comprises the steps of: (a) forming a plurality of buttresses on a first supporting substrate such that the buttresses are separated by a plurality of intercommunicated spaces thereamong; (b) forming a base layer on top end portions of the buttresses in...

20060094138 - Method for manufacturing high efficiency light-emitting diodes: A method for manufacturing a high efficiency light-emitting diode (LED) is disclosed. In the method, a substrate is provided, in which an N-type buffer layer, an N-type cladding layer and an active layer are stacked on the substrate in sequence. A first P-type cladding layer is formed on the active...

20060094141 - Method for manufacturing semiconductor laser device: A method for manufacturing a semiconductor laser device is provided in which deformation of a cap layer and a third cladding layer is inhibited and a protruding portion of an intermediate layer is removed. By coating outer peripheral portions facing an intermediate layer of a third cladding layer and an...

20060094142 - Fabricating method of semiconductor optical device for flip-chip bonding: Disclosed is a method for manufacturing a semiconductor optical device for flip-chip bonding. The method includes the steps of: etching an active layer and clad which are sequentially stacked on a semiconductor substrate into first and second alignment keys and an optical area, which has a mesa structure; growing at...

20060094143 - Micro-displays and their manufacture: A method of forming a micro-display includes forming a device that includes forming a partially reflecting layer on a first substrate and forming a plate overlying the partially reflecting layer, and adhering the device to a second substrate....

20060094144 - Programmable mask and method for fabricating biomolecule array using the same: A programmable mask used in a photolithography process for fabricating a biomolecule array and a method for fabricating a biomolecule array using the same are disclosed. Particularly, a TFT-LCD type programmable mask for selectively transmitting incident light in accordance with an electrical signal applied thereto and a method for fabricating...

20060094146 - Emissive plastic optical fiber using phase separation and backlight unit for liquid crystal display using the same: An emissive plastic optical fiber using phase separation and a backlight unit for a liquid crystal display using the emissive plastic optical fiber. The emissive plastic optical fiber is fabricated by inducing phase separation in a polymer which forms a core and/or a clad, which can be applied to the...

20060094145 - Nitride-based semiconductor device and method of fabrication: A light-emitting diode is built on a silicon substrate doped with a p-type impurity to possess sufficient conductivity to provide a current path. The p-type silicon substrate has epitaxially grown thereon two superposed buffer layers of aluminum nitride and n-type indium gallium nitride. Further grown epitaxially on the buffer layers...

20060094147 - Metal-insulator-metal device: A method for forming a metal-insulator-metal device includes imprinting at least one first layer to form a first impression, removing a portion of at least one second layer through the first depression to form a recess in the at least one second layer bordered by a first side, a first...

20060094149 - Micro electrical mechanical system: This disclosure relates to lids and methods for forming and using them. One embodiment of these lids enables MEMS protected by the lids to be smaller. Another of these lids enables testing of a group of conjoined, lidded MEMS. Also, processes for forming and using these lids are also disclosed....

20060094148 - Semiconductor acceleration sensor and process for manufacturing the same: The present invention provides a semiconductor acceleration sensor wherein a semiconductor element is prevented from being damaged even when at least part of a weight is disposed in an internal space of a semiconductor sensor element and the mass of a weight is accordingly increased. An inner peripheral surface of...

20060094150 - Method of enhancing connection strength for suspended membrane leads and substrate contacts: A method to enhance the connection strength of suspended membrane leads and substrate contacts is described. A reading circuit chip is provided and a sacrificial layer is formed thereon. Subsequently, an electrical contact window is created in the sacrificial layer to expose a conductive layer of the reading circuit chip....

20060094151 - Solid-state image sensor and method for manufacturing thereof as well as semiconductor device and method for manufacturing thereof: A solid-state image sensor and a method for manufacturing thereof and a semiconductor device and a method for manufacturing thereof are provided. A semiconductor substrate is made to be the thin film without using an SOI substrate and cost is reduced. An edge detection portion having hardness larger than that...

20060094152 - Cmos power sensor: A CMOS power sensor is disclosed in the present invention. The CMOS power sensor includes a current coil, a high voltage device circuit, and a Hall device. The current coil is fabricated during the process steps of forming gold bumps of a CMOS device. One end of the current coil...

20060094153 - Semiconductor device and method for manufacturing the same: The present invention provides a method by which molecules in an organic semiconductor layer can be oriented so as to make molecules in an organic semiconductor layer be oriented without damaging the organic semiconductor layer by rubbing and by which molecules in an organic semiconductor layer are oriented without losing...

20060094154 - Common word line edge contact phase-change memory: A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a first dimension of a bottom electrode and a second dimension controlled by an etch process. The contact area is a product of...

20060094158 - Fabrication method of packaging substrate and packaging method using the packaging substrate: A fabrication method of a packaging substrate includes the steps of: forming a recess by etching a predetermined area of a lower surface of a substrate; depositing a seed layer on an upper surface of the substrate; in the recess, etching predetermined area(s) of the lower surface of the substrate...

20060094155 - Method of manufacturing a wafer assembly: A method of manufacturing a wafer assembly involves a chip wafer onto which a cover wafer is deposited, the chip wafer includes an active face and an inactive face, the active face includes chip elements, the cover wafer being provided with a chip-element-receiving cavity located above a chip element, the...

20060094159 - Methods of manufacturing interposers with flexible solder pad elements: Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer may absorb thermally induced stresses and conform to warped...

20060094156 - Semiconductor package substrate with embedded resistors and method for fabricating the same: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on...

20060094157 - Structure of mounting electronic component and method of mounting the same: The structure of mounting an electronic component on a circuit board is capable of securely flip-chip-bonding the electronic component having bumps, whose separations are very short, to the circuit board without displacement. The structure of mounting an electronic component on a circuit board is characterized in that bumps of the...

20060094160 - Die stacking scheme: An improved semiconductor die stacking scheme is provided. In accordance with one embodiment of the present invention, a method of stacking a plurality of semiconductor die is provided. In accordance with another embodiment of the present invention a multiple die semiconductor assembly is provided. Each embodiment relates generally to a...

20060094161 - Thermal enhance package and manufacturing method thereof: A thermal enhance package mainly comprises a chip, a substrate unit, a heat spreader unit and a plurality of pellets. The chip is disposed above the substrate unit and electrically connected to the substrate unit, and an encapsulation unit encapsulates the chip, the substrate unit, the heat spreader unit and...

20060094163 - Low resistance and inductance backside through vias and methods of fabricating same: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench...

20060094162 - Thin film probe sheet and semiconductor chip inspection system: In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film...

20060094164 - Semiconductor integrated device, design method thereof, designing apparatus thereof, program thereof, manufacturing method thereof, and manufacturing apparatus thereof: Semiconductor integrated circuit that prevents breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof is provided. The circuit includes a gate 12 provided insulated from a transistor diffusion layer 11, wirings 13 and 14 connected to the gate 12, a wiring 15 parallel to...

20060094165 - Method for fabricating semiconductor components: In a method for fabricating semiconductor components a first carrier is provided and at least one semiconductor component is arranged on the first carrier between ist boundary lines. The semiconductor has at least one semiconductor contact-connection region which is located on a first surface of the first carrier. Then conical...

20060094167 - Embedded rom device using substrate leakage: A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques...

20060094166 - Method of manufacturing a thin film transistor, a thin film transistor manufactured by the method, a method of manufacturing flat panel display device, and a flat panel display device manufactured by the method: Provided are a method of manufacturing a plastic substrate having a TFT, a substrate manufactured thereby, a method of manufacturing a flat panel display device, and a flat display device manufactured thereby, which can be used for a flexible flat display device. The method includes: preparing a film in which...

20060094171 - Isolation trench thermal annealing method for non-bulk silicon semiconductor substrate: A method for fabricating a semiconductor product employs a semiconductor substrate other than a bulk silicon semiconductor substrate. The semiconductor substrate is etched to form an etched semiconductor substrate having an isolation trench adjoining an active region. The etched semiconductor substrate is thermally annealed prior to forming a semiconductor device...

20060094170 - Memory capable of storing information and the method of forming and operating the same: The present invention discloses a method for manufacturing memory unit capable of storing multi-bits binary information. Firstly, a gate is formed on a dielectric layer over a semiconductor substrate. Next, a first etching is performed to etch the semiconductor substrate by using the gate acting as an etching mask to...

20060094173 - Method for forming semiconductor device: In a method for forming a silicon-on-insulator FET providing a contact to be given a fixed potential to a substrate, substrate-biasing between an SOI transistor and the silicon substrate is performed via a plug. As a result, the contact hole for the substrate-biasing does not need to pass through an...

20060094172 - Method of fabricating thin film transistor: A method of fabricating a thin film transistor, in which source and drain electrodes are formed through a solution process, thus all stages which include formation of electrodes on a substrate, formation of an insulator layer, and formation of an organic semiconductor layer are conducted through the solution process. In...

20060094168 - Method of forming a thin film component: Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film component are described....

20060094169 - Semiconductor device structure and method therefor: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially...

20060094174 - Method of fabricating a tft device formed by printing: A thin-film transistor for an active matrix display is fabricated using printing means, such as a gravure offset printer. First and second pattern layers (251, 252; 30) are formed on a layer structure (4) wherein at least one of the layers is printed. The printed layers (251, 252; 30) mask...

20060094175 - In-place bonding of microstructures: A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the...

20060094179 - Igbt with amorphous silicon transparent collector: The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom...

20060094176 - Method for the production of a short channel field-effect transistor: The invention relates to a method for fabricating a short channel field-effect transistor, comprising the steps of: forming a sublithographic gate sacrificial layer (3M), forming spacers (7S) at the side walls of the gate sacrificial layer (3M), removing the gate sacrificial layer (3M) to form a gate recess and forming...

20060094178 - Method of fabricating mos transistor by millisecond anneal: A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite...

20060094177 - Semiconductor device and method for fabricating the same: The semiconductor device comprises gate electrodes 50 formed on a silicon substrate 32 with a gate insulation film 48 formed therebetween, source/drain diffused layers 66n, 66p formed in the silicon substrate 32 on both sides of the gate electrodes 50, a skirt-like insulation film 58 formed on a lower part...

20060094181 - Method for fabricating semiconductor device having a trench structure: Disclosed is a method for fabricating a semiconductor device capable of preventing a residue from being generated during etching a gate conductive layer and forming a plurality of trenches having an identical width in a substrate. The method includes: selectively etching a substrate by employing tetramethylammoniumhydroxide (TMAH) solution, thereby forming...

20060094180 - Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, forming a barrier layer on the high-k gate dielectric layer, and forming a fully silicided gate electrode on the barrier layer....

20060094182 - Transistor structure having interconnect to side of diffusion and related method: A transistor structure is disclosed including at least one transistor including a diffusion and an interconnect electrically connected to a side of the diffusion and a conductor in electrical contact with the interconnect. The low-resistivity local interconnect is advantageous for use with stressed liner films since a conductor can contact...

20060094183 - Cmos gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure: By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate material. The improved uniformity of the dopant distribution results...

20060094184 - Semiconductor storage device and method for manufacturing the same: There is disclosed a semiconductor storage device comprising a trench capacitor wherein a high dielectric-constant insulator is used and formation of a depletion layer in a capacitor electrode is suppressed. The semiconductor storage device comprises a trench formed in a semiconductor substrate, a high dielectric-constant insulator formed on an inner...

20060094185 - Capacitor including a dielectric layer having an inhomogeneous crystalline region and method of fabricating the same: In a capacitor, and a method of fabricating the same, the capacitor includes a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer, wherein the dielectric layer includes a lower dielectric region contacting the lower electrode, an upper dielectric region contacting the...

20060094186 - Semiconductor device and method of manufacturing the same: A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28)...

20060094187 - Method of changing an electrically programmable resistance cross point memory bit: Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower...

20060094188 - Methods of fabricating flash memory devices and flash memory devices fabricated thereby: Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on...

20060094189 - Nanoparticles and method for making the same: A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanoparticles and a metal oxide matrix. The nanoparticles are then isolated...

20060094190 - Semiconductor device, pattern design method of a semiconductor device and program for a pattern design method: According to an aspect of the present invention, there is provided a pattern design method of a semiconductor device, including preparing design pattern data, separating a pattern region of a semiconductor device on the basis of the design pattern data into a dummy pattern region and a dummy pattern prohibition...

20060094191 - Methods of manufacturing a semiconductor device including a dielectric layer including zirconium: A method of manufacturing a semiconductor device can include forming a tunnel oxide layer on a substrate, forming a floating gate on the tunnel oxide layer and forming a dielectric layer pattern on the floating gate using an ALD process. The dielectric layer pattern can include a metal precursor that...

20060094192 - Method for treating base oxide to improve high-k material deposition: A method for forming a high-K material layer in a semiconductor device fabrication process including providing a silicon semiconductor substrate or thermally growing interfacial oxide layer comprising silicon dioxide over the silicon substrate; treating with an aqueous base solution or nitridation and depositing a high-K material layer....

20060094193 - Semiconductor device including semiconductor regions having differently strained channel regions and a method of manufacturing the same: By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS...

20060094194 - Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90nm cmos technology: A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy...

20060094195 - Method of manufacturing semiconductor mos transistor device: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface....

20060094196 - Method of fabricating semiconductor device, and semiconductor device: Disclosed is a method of fabricating a semiconductor device that includes field effect transistors each having a gate electrode formed only of a metal suicide which overcomes the problem of depletion of the gate and makes adjustment of a work function easier, and that has a high integration with the...

20060094198 - Integrated analog circuit using switched capacitor technology: An integrated analog circuit using switched capacitor technology includes an integrated capacitor device that includes a first electrode device, a second electrode device, and a dielectric region formed between the first and second electrode devices. The dielectric region is made from or with an organic material....

20060094197 - Method of trimming semiconductor elements with electrical resistance feedback: A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion...

20060094199 - Method for forming capacitor of semiconductor device: Disclosed is a method for forming a capacitor of a semiconductor device, which can improve a leakage current characteristic in applying HfxAlyOz as a dielectric film. In such a method, HfxAlyOz thin films are deposited on a storage electrode to form an HfxAlyOz dielectric film and a plate electrode is...

20060094201 - Method for forming isolation film in semiconductor device: A method for forming an isolation film of a semiconductor device is disclosed which includes forming trenches in a semiconductor substrate, forming a first HDP oxide film in the formed trenches, performing an etch-back process using a mixing gas of C2F6 gas and O2 gas to form vertical walls in...

20060094203 - Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same: In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so...

20060094200 - Methods for controlling feature dimensions in crystalline substrates: A method of forming a slot in a substrate comprises growing an oxide layer on a first side of a substrate, patterning and etching the oxide layer to form an opening, forming a material overlying the opening and the oxide layer, removing substrate material through a second side to a...

20060094202 - Semiconductor array and method for manufacturing a semiconductor array: A process for manufacturing a semiconductor array, wherein a trench structure is introduced into a first monocrystalline semiconductor region, the trench structure is filled with an insulator, whereby a number of layers of the insulator together have a heat conductance greater than 20 W/mK, an amorphous silicon layer, which is...

20060094204 - Planarization material, anti-reflection coating material, and method for manufacturing semiconductor device thereby: A material including a photo acid generator or thermal acid generator is used to at least one of a planarization material for a chemically amplified resist film and an anti-reflection coating film material applied under the chemically amplified resist film. In case of the photo acid generator, acid substances are...

20060094205 - Method of forming isolation trench with spacer formation: A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the...

20060094206 - Packaging and manufacturing of an integrated circuit: Apparatus, packaging, and methods of manufacture of an integrated circuit are provided. The integrated circuit includes a component of a first type fabricated on a first substrate containing a first material, and a component of a second type fabricated on a second substrate containing a second material. The first material...

20060094207 - Method of fabricating vertical devices using a metal support film: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal techniques. Trenches that define the boundaries of the individual devices are formed through the semiconductor layers and into the insulating substrate, beneficially by inductive...

20060094208 - Method for reducing semiconductor die warpage: An anti-warpage backgrinding tape (11) is secured to the circuit side (12) of a semiconductor wafer (14). The backside (16) of the wafer is background. The backside of the wafer is secured to dicing tape (18) so that the anti-warpage backgrinding tape is exposed. The wafer is diced to create...

20060094210 - Semiconductor wafer processing method and processing apparatus: A method of processing a semiconductor wafer having circuits which are formed in a plurality of rectangular areas sectioned by streets arranged in a lattice pattern on the front surface, comprising: a grinding step of grinding the back surface of the semiconductor wafer to a predetermined thickness; and an oxide...

20060094209 - Wafer processing method: To divide into individual devices efficiently in dicing a wafer without causing quality of the devices to lower, a wafer processing method includes steps of coating a rear surface of the wafer with a resist film, exposing and sensitizing portions of the resist film other than regions corresponding to the...

20060094211 - Method of hydrogenating a poly-silicon layer: A method of hydrogenating a poly-silicon layer is disclosed, which is used to improve characteristics of a thin film transistor (TFT) having a poly-silicon thin film. In the method, the poly-silicon layer is first subject to a plasma pre-process and then a hydrogenating process is undertaken thereon where a hydrogen-containing...

20060094212 - Thin film transistor and method of manufacturing the same: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film...

20060094213 - Method for crystallizing silicon using a ramp shaped laser beam: A crystallization method, includes: forming an amorphous silicon layer on a substrate; forming a first crystallization region by irradiating the amorphous silicon layer with a laser beam having a ramp shaped cross sectional profile that decreases in a scanning direction; and performing a second crystallization by moving a predetermined length...

20060094214 - Semiconductor doping process: A semiconductor doping process uses hydrogen in a diffusion furnace to prevent platinum/gold atoms from gathering around a defect area of the semiconductor wafer. Platinum/gold atom aggregation caused by a micro defect in the semiconductor wafer is prevented in order to stabilize the semiconductor doping process and to improve reverse...

20060094215 - Technique for forming a dielectric etch stop layer above a structure including closely spaced lines: When forming line structures of semiconductor devices in accordance with the 90 nm technology, sidewall spacers of the lines are reduced in size immediately prior to the deposition of an etch stop layer that is formed on the device layer. Due to the reduced spacer elements or due to a...

20060094216 - Method for fabricating semiconductor device with gate spacer: The present invention relates to a method for fabricating a semiconductor device with gate spacers. The method includes the steps of: forming a plurality of gate structures on a substrate; forming an insulation layer on the gate structures and the substrate; and etching the insulation layer to form gate spacers...

20060094218 - Apparatus for plasma chemical vapor deposition and method for fabricating semiconductor device by using the same: An apparatus for use in a plasma chemical vapor deposition (CVD) includes a chamber; a cooling gas inlet passing through an electrostatic chuck for supplying a cooling gas to the bottom surface of a wafer when the plasma CVD process is performed; and a clamping unit for clamping the wafer...

20060094217 - Method for contacting parts of a component integrated into a semiconductor substrate: The invention relates to a method for contacting pans of a component integrated into a semiconductor substrate (1). According to the inventive method, a first contact hole is produced in an insulating layer (2), said contact hole being then filled with contact material (16) and connected to a line. The...

20060094219 - Method for manufacturing electronic device: The method for manufacturing an electronic device is provided. The method includes: applying an active hydrogen species over a surface of an underlying interconnect formed on a substrate and having an anti-corrosion material formed on the surface thereof and containing copper, to remove the anti-corrosion material; and forming an insulating...

20060094221 - Method for manufacturing electronic device: A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The...

20060094220 - Methods of forming a metal line in a semiconductor device: Methods of forming a metal line in a semiconductor device are disclosed. An illustrated method includes: depositing a first etch stop layer, an interlayer insulating layer, a second etch stop layer, and a line insulating layer on a semiconductor substrate; forming a contact hole pattern on the line insulating layer;...

20060094222 - Integrated circuit die configuration for packaging: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package...

20060094224 - Bumping process and structure thereof: A bumping process is provided. The bumping process comprises the steps of: firstly, providing a wafer; next forming an under bump metallurgy (UBM) on the active surface of the wafer; then, forming a photo-resist layer on the active surface of the wafer and forming at least an opening in the...

20060094223 - Fabrication method of a wafer structure: A wafer fabricating method at least includes the steps of providing a wafer having an active surface with a plurality of pads, forming a plurality of bumps on the pad, and forming an organic protective layer on the bump and the active surface. Besides improving the quality of the wafer,...

20060094226 - Bumping process: A bumping process is provided as following: at first, providing a wafer, then forming a first photo-resist layer on a active surface of the wafer and forming at least a first opening on the first photo-resist layer; and forming a copper pillar in the first opening; then forming a second...

20060094225 - Methods for forming solder bumps on circuit boards: This invention relates to a method for forming solder bumps on a circuit board, which is formed with a solder resist and pads thereon and the pads are exposed from the solder resist. The steps of the method mainly are: Firstly, strengthen the solder resist by ultraviolet rays and then...

20060094227 - Method of forming a contact in a semiconductor device: Deterioration of yield may be prevented when a contact in a semiconductor device is made by a method including forming a contact hole by selectively removing an insulating layer from a semiconductor substrate, depositing a barrier layer on the insulating layer and on the surface of (or in) the contact...

20060094228 - Structure and method for contact pads having an overcoat-protected bondable metal plug over copper-metallized integrated circuits: A metal structure for a contact pad of an integrated circuit (IC), which has copper interconnecting metallization (311). A portion (301) of this metallization is exposed to provide a contact pad to the IC. A conductive barrier layer (330) is positioned on the exposed portion o the copper metallization. A...

20060094229 - Semiconductor device and method of manufacturing the same: A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make...

20060094233 - Device and method for determining an edge coverage during coating processes: In a method for determining an edge coverage during coating processes a substrate is provided, a mask layer is deposited on the substrate, at least one through hole is formed in the mask layer and at least one first trench-type depression is formed in the substrate by patterning the substrate...

20060094231 - Method of creating a tapered via using a receding mask and resulting structure: Embodiments of a method of forming a tapered via using a receding mask are disclosed. In one embodiment, an etch mask formed on a substrate includes a first aperture in a first photoresist layer and a second, larger aperture in an overlying second photoresist layer. Peripheries of the first and...

20060094232 - Methods of forming planarized multilevel metallization in an integrated circuit: A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium...

20060094230 - Multiple layer resist scheme implementing etch recipe particular to each layer: Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the...

20060094234 - Method for manufacturing electonic device: A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The...

20060094235 - Method for fabricating gate electrode in semiconductor device: Disclosed is a method for fabricating a gate electrode in a semiconductor device. The method includes the steps of: forming a plurality of trenches on a substrate in a cell region; sequentially forming a gate oxide layer, a polysilicon layer, a metal silicide layer and an insulation layer for a...

20060094236 - Electroless plating of metal caps for chalcogenide-based memory devices: A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer...

20060094237 - Methods to completely eliminate or significantly reduce defects in copper metallization in ic manufacturing: A method for the improved electroplating of copper on to a copper seed layer provides treating the surface of a copper seed layer with nitrogen or another anaerobic gas. In another aspect, a burnishing treatment is used to enhance the platability of the copper seed layer. According to another aspect,...

20060094238 - Deposition of tungsten nitride: Methods for depositing a tungsten nitride layer are described. The methods form a tungsten nitride layer using a carefully controlled deposition technique such as pulsed nucleation layer (PNL). Initially, a tungsten layer is formed on a substrate surface. The tungsten layer is then exposed to a nitriding agent to form...

20060094239 - Dense seed layer and method of formation: Methods of forming dense seed layers and structures thereof. Seed layers comprising a monolayer of molecules having a density of about 0.5 or greater may be manufactured over a metal layer, resulting in a well defined interface region between the metal layer and a subsequently formed material layer. A seed...

20060094240 - Neo-wafer device comprised of multiple singulated integrated circuit die: A neo-wafer made from integrated circuit die and methods for making a neo-wafer are disclosed. Recesses are formed on a substrate and a dielectric layer with conductive pads is created for the receiving of one or more die. Die are flip-chip bonded to the conductive pads and all voids under-filled....

20060094241 - Etchant for conductive materials and method of manufacturing a thin film transistor array panel using the same: The present invention provides a method for manufacturing a thin film transistor (TFT) array panel by forming a gate line having a gate electrode on an insulating substrate; sequentially depositing a gate insulating layer and a semiconductor layer on the gate line; forming a drain electrode and a data line...

20060094242 - Chemical mechanical polishing method, and washing/rinsing method associated therewith: In a chemical mechanical polishing method for polishing a low-k material insulating layer formed on a semiconductor wafer, aqueous abrasive slurry composed of a water component, an abrasive component, a first additive for making the low-k material insulating layer of the semiconductor wafer hydrophilic in nature, and a second additive...

20060094243 - Compositions including perhydro-polysilazane used in a semiconductor manufacturing process and methods of manufacturing semiconductor devices using the same: Compositions that can be used in semiconductor manufacturing processes, comprising perhydro-polysilazane having a weight average molecular weight of about 300 to about 3,000 and a polydispersity index of about 1.8 to about 3.0 are provided. Solutions comprising the compositions of the present invention, methods of forming films in a semiconductor...

20060094245 - Methods of fabricating metal wiring in semiconductor devices: Manufacturing costs may be reduced and yield may be improved when metal wiring in a semiconductor device is fabricated by a disclosed method including: sequentially forming an etch stop layer, an intermetal insulation layer, an anti-reflection coating layer, and a mask pattern on a semiconductor substrate formed with a lower...

20060094244 - Nitride semiconductor device and fabrication method thereof: A nitride semiconductor device is provided that prevents development of cracks, that has nitride semiconductor thin films with uniform thicknesses and good growth surface flatness, and is thus consistent in characteristics, and that can be fabricated at a satisfactory yield. In this nitride semiconductor device, the nitride semiconductor thin films...

20060094246 - Method of wafer patterning for reducing edge exclusion zone: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing...

20060094247 - Method for producing a stepped edge profile comprised of a layered construction: In a method for forming a stepped profile from a layer sequence comprising a first patterning step, in which a first layer partial sequence is removed apart from a first residual layer partial sequence, a second patterning step, in which a second layer partial sequence located below the first layer...

20060094250 - Method for fabricating semiconductor device: Disclosed is a method for fabricating a semiconductor device. The method includes: forming a first inter-layer insulation layer on a substrate provided with a plurality of cell contact plugs; selectively etching the first inter-layer insulation layer to form a plurality of first contact holes; performing a cleaning process to remove...

20060094248 - Method of oxidizing member to be treated: In a method for oxidation of a surface of an object to be processed in a single processing container 8 which can contain a plurality of objects to be processed, at least a nitride film is exposed on said surface, and said oxidation is performed by mainly using active hydroxyl/oxygen...

20060094252 - Methods to form electronic devices and methods to form a material over a semiconductive substrate: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure...

20060094251 - Multi-layer film stack for extinction of substrate reflections during patterning: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric...

20060094249 - Semiconductor structure having a metallic buffer layer and method for forming: A method for forming a semiconductor structure including providing a semiconductor substrate, forming a metallic buffer layer over the semiconductor substrate, forming an amorphous semiconductor layer over the metallic buffer layer, and recrystallizing the amorphous semiconductor layer to form a crystalline semiconductor layer. A semiconductor structure includes a semiconductor substrate,...

20060094253 - Semiconductor memory devices and methods for making the same: Methods for making memory devices are disclosed for forming germanium nanocrystals in an oxynitride layer. The method includes: forming a first dielectric layer over a substrate; forming an oxynitride layer containing germanium nanocrystals over the first dielectric layer; forming a second dielectric layer over the oxynitride layer; forming a gate...

20060094254 - Method for forming field oxide: A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substrate in a region not covered with...

20060094255 - Semiconductor device and method of fabricating the same: m

20060094257 - Low thermal budget dielectric stack for sonos nonvolatile memories: A method of forming an oxide-nitride-oxide (ONO) structure for use in a non-volatile memory cell, which includes (1) forming a first oxide layer over a substrate, (2) forming a silicon nitride layer over the first oxide layer, (3) introducing oxygen into a top interface of the silicon nitride layer, and...

20060094256 - Using polydentate ligands for sealing pores in low-k dielectrics: In preferred embodiments, a polydentate pore-sealing ligand is used to seal or repair pores damaged by plasma processing. The polydentate ligand includes bidentate ligands corresponding to the general formula X—CH2—(CH2)n—CH2—X or X—Si(CH3)2—(CH2)n—Si(CH3)2—X. The polydentate ligand also includes tridendate ligands corresponding to the general formula X—CH2—(CH2)m(CXH)(CH2)o—CH2—X or X—Si(CH3)2—(CH2)m(CXH)(CH2)o—Si(CH3)2—X. Alternative embodiments may...

20060094258 - Cyclic olefin polymers and catalyst for semiconductor applications: An embodiment is a cyclic olefin semiconductor package. Further an embodiment is a combination of a cyclic olefin monomer and a ruthenium-based catalyst that is stable at approximately room temperature and humidity for extended storage life and pot life, and that can be screen printed or valve/jet deposited....

20060094259 - Forming gas anneal process for high dielectric constant gate dielectrics in a semiconductor fabrication process: A semiconductor fabrication annealing process includes depositing a high dielectric constant gate dielectric over a substrate and annealing the gate dielectric. Annealing the gate dielectric includes exposing the gate dielectric to an inert ambient and ramping the inert ambient to an annealing temperature. A passivating gas is then introduced into...

20060094260 - Method for laser processing of wafer: A method of carrying out the laser processing of a wafer with a laser beam processing machine comprising a chuck table for holding a wafer, a laser beam application means for applying a laser beam to the wafer held on the chuck table and a processing-feed means for processing-feeding the...

20060094261 - Method for in-situ uniformity optimization in a rapid thermal processing system: The present invention is directed to a method for thermally processing a substrate in a thermal processing system. The method comprises providing an amount of heat to the substrate and obtaining information associated with the substrate when the amount of heat is provided. For example, the substrate is provided at...