Semiconductor device manufacturing: process inventions 05/06

20060110836 - Eliminating systematic process yield loss via precision wafer placement alignment: A method for a semiconductor process includes correlating yield loss for the performance of a processing step in a semiconductor manufacturing process with the mechanical placement of the semiconductor substrate and, based on the correlation, placing semiconductor substrates in a position with sufficient placement precision to reduce yield loss below...

20060110837 - Method and system for topography-aware reticle enhancement: The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC). The reticle enhancement calculations are improved by incorporating post-planarization topography estimates. A planarization process of a wafer layer is simulated to estimate the post-planarization topography. RET calculations, such as sub-resolution...

20060110838 - Multilayered circuit substrate, semiconductor device and method of producing same: A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can...

20060110840 - Functional device and method for producing the same: where Tg is a glass transition temperature of the organic material, ΔE1 is an activation energy for crystallization of the organic material measured while the electrode layer and the insulating layer are not stacked on the functional layer and ΔE2 is an activation energy for crystallization of the organic material...

20060110839 - Micro-leds: An array of light emitting devices, each device comprising a sloped wall mesa (24) of luminescent semiconductor material. Extending over the sloped wall mesas (24) is a metal contact (30). The array can be arranged as a parallel addressable system so that all devices (24) can be stimulated to emit...

20060110841 - Avalanche photodiode: An avalanche photodiode includes at least one crystal layer having a larger band-gap than that of an absorption layer formed by a composition or material different from that of the absorption layer formed on a junction interface between a compound semiconductor absorbing an optical signal and an Si multiplication layer,...

20060110842 - Method and apparatus for preventing metal/silicon spiking in mems devices: The disclosure relates to a method and apparatus for preventing extrusion or spiking of a metal atom from a metallization layer to other layers of a silicon wafer. In one embodiment, the method includes forming a silicon-on-ship device with a MEMS component on the substrate. The MEMS component may include...

20060110843 - Method of manufacturing an external force detection sensor: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole dry etching of an element substrate, and an electrically conductive material is used as an etching stop layer during the dry etching....

20060110844 - Fabrication of thin film germanium infrared sensor by bonding to silicon wafer: A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion...

20060110845 - Method of manufacturing micro-structure element by utilizing molding glass: A method of manufacturing micro-structure elements by utilizing molding glass includes the steps of forming a mold having a micro-structure pattern thereon by using an electroforming process, making a copy of the micro-structuring pattern on a glass structure by using glass molding technology, and filling clothing material on the glass...

20060110846 - Electrically programmable memory element with improved contacts: A method of making an electrically programmable memory element, comprising: providing a conductive sidewall spacer; and forming a phase-change material in electrical communication with said conductive sidewall spacer....

20060110847 - Field effect transistor and its manufacturing method: To provide a method of easily producing TFT in which the orientation of channel molecules or wires is enhanced, compared with conventional type organic TFT at a low price, a lyophilic TFT pattern encircled by a lyophobic area is formed on a substrate, spontaneous movement is made in a droplet...

20060110849 - Method for stacking bga packages and structure from the same: The present invention relates to a method for stacking BGA packages. At first, a first BGA package is provided. The first BGA package includes a first substrate, at least one first chip and a plurality of first connecting balls. The first substrate has a first upper surface and a first...

20060110850 - Method for two-stage transfer molding device to encapsulate mmc module: A method for fabricating a semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined...

20060110848 - Off-width pitch for improved circuit card routing: Enlarged spacing is provided between rows of vias in a ball grid array (BGA) multilayered printed wiring board land pattern in which the lands in the pattern are connected to the vias by a link connector by rotating, elongating, and/or truncating selected consecutive link connectors and rotating their respective corresponding...

20060110851 - Methods for forming co-planar wafer-scale chip packages: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed...

20060110852 - Methods to achieve precision alignment for wafer scale packages: Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed...

20060110853 - Structure of embedded active components and manufacturing method thereof: A structure of embedded active components and the manufacturing method thereof are provided. The manufacturing steps involve providing a molding plate, and setting several active components on the molding plate as first. A dielectric layer covers the molding plate to cap the active components. An electric circuit is formed on...

20060110854 - Methods and systems for providing mems devices with a top cap and upper sense plate: A method for fabricating a MEMS device having a top cap and an upper sense plate is described. The method includes producing a device wafer including an etched substrate, etched MEMS device components, and interconnect metal, a portion of the interconnect metal being bond pads and adding a metal wraparound...

20060110855 - Leadframe with enhanced encapsulation adhesion: A leadframe having a metallic substrate and comprising layers of plated material, and a method of manufacturing said leadframe are provided. The substrate is plated with a layer of oxidizable material comprising nickel and a noble metal is selectively plated on the layer of oxidizable material. Thereafter, an exposed portion...

20060110857 - Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same: A method of fabricating a lead frame for a semiconductor device having a semiconductor chip resin-sealed therein. The lead frame includes a lead to be electrically connected to the semiconductor chip within sealing resin and to be sealed into the sealing resin such that at least a part of its...

20060110856 - Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side...

20060110858 - Ultra-thin semiconductor package device and method for manufacturing the same: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness...

20060110859 - Electronic device and manufacturing method of the same: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature...

20060110861 - Integrated circuit with multi-length power transistor segments: A monolithic power integrated circuit fabricated on a semiconductor die includes a control circuit and a first output high voltage field-effect transistor (HVFET) having source and drain segments substantially equal to a first length. A second output HVFET has source and drain segments substantially equal to a second length. At...

20060110860 - Self-adjusting serial circuit of thin layers and method for production thereof: The invention relates to a self-adjusting serial circuit of thin layers and method for production thereof. The invention is characterised in that electrically conducting conductor tracks (20) are applied to a substrate (10), whereupon several main deposit layers (30, 40, 50) of conducting, semi-conducting or insulating materials are applied to...

20060110864 - Method of fabricating a thin film transistor using dual or multiple gates: A method of fabricating a TFT using dual or multiple gates, and a TFT having superior characteristics and uniformity by providing a method of fabricating a TFT using dual or multiple gates by calculating the probability including Nmax, the maximum number of crystal grain boundaries in active channel regions according...

20060110862 - Method of forming a thin film transistor: A method of forming a thin film transistor comprising a deposition procedure of a microcrystal material layer and performing a plasma treatment procedure. The deposition procedure and the plasma treatment procedure are repeated. A buffer layer is thus formed on the gate electrode....

20060110863 - Semiconductor device, and method for manufacturing the same: It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor,...

20060110867 - Field effect transistor manufacturing method: Provided is a novel method for manufacturing a field effect transistor. Prior to forming an amorphous oxide layer on a substrate, ultraviolet rays are irradiated onto the substrate surface in an ozone atmosphere, plasma is irradiated onto the substrate surface, or the substrate surface is cleaned by a chemical solution...

20060110866 - Method for fabricating thin film transistors: Thin film transistor fabrication methods. A gate electrode is formed on a substrate. The surface of metal gate is subjected to a hydrogen plasma treatment to remove a native oxide formed thereon. A nitride layer as a buffer layer is formed to cover the metal gate. A gate insulating layer...

20060110865 - Method of forming ultra thin silicon oxynitride for gate dielectric applications: A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A...

20060110868 - Production of lightly doped drain of low-temperature poly-silicon thin film transistor: A method is disclosed to make a lightly doped drain of a low-temperature poly-silicon thin film transistor. Nitrogen is implanted during steps of doping the source and the drain so as to suppress the spreading of the other types of dope so that the poly-silicon layer forms a shallow interface...

20060110869 - Semiconductor device including a tft having large-grain polycrystalline active layer, lcd employing the same and method of fabricating them: A display device includes a pixel region having a plurality of pixels and a peripheral circuit region disposed at a periphery of the pixel region for driving the pixels. The peripheral circuit region includes transistors fabricated from polycrystalline semiconductor and having a semiconductor crystalline grain of a first kind in...

20060110872 - Method for fabricating a semiconductor structure: A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. The mask layer is patterned...

20060110871 - Methods for fabricating thin film transistors: Fabrication methods for thin film transistors. A metal gate stack structure is formed on an insulating substrate. The substrate is performed using thermal annealing to create an oxide layer on the sidewalls of the metal gate stack structure. A gate insulating layer is formed on the substrate covering the metal...

20060110870 - Scalable integrated logic and non-volatile memory: A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers....

20060110873 - Method for fabricating cmos image sensor: Form a gate electrode on a transistor region of a first conductivity type semiconductor substrate including a photodiode region and the transistor region. Form lightly-doped second conductivity type diffusion areas at both sides of the gate electrode in the photodiode region and the transistor region. Form a screen layer over...

20060110874 - Method of forming source contact of flash memory device: The present invention relates to a method of forming a source contact of a flash memory device. According to the present invention, the method includes the steps of forming a first interlayer insulating film on a semiconductor substrate in which first junction regions and second junction regions both of which...

20060110875 - Trench lateral power mosfet and a method of manufacturing the same: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with...

20060110876 - Mos transistor with reduced kink effect and method for the manufacture thereof: A lateral MOS transistor is provided with a channel region, which has a channel width delimited by dielectric-filled trenches and which is covered with a gate dielectric, whose layer thickness varies over the channel width. An outer layer thickness, which the gate dielectric has over junctions of the channel region...

20060110877 - Memory device including resistance change layer as storage node and method(s) for making the same: A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise)...

20060110878 - Side wall active pin memory and manufacturing method: A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with...

20060110881 - Method of manufacturing a select transistor in a nand flash memory: Disclosed herein is a method of manufacturing a flash memory device. According to the present invention, a method of manufacturing a NAND flash memory device having a memory cell and a select transistor, wherein a graph showing the relation between the length of a gate electrode of the select transistor...

20060110882 - Methods of forming gate structure and flash memory having the same: A method of forming a gate structure, including forming sequentially a gate dielectric layer, a conductive layer, a protective layer, a sacrificial layer, and a patterned mask layer over a substrate. The exposed sacrificial layer is removed by using the patterned mask layer as an etching mask and the protective...

20060110879 - Non-volatile memory and fabricating method thereof: A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of...

20060110880 - Self-aligned trench filling with high coupling ratio: Self-aligned trench filling to isolate active regions in high-density integrated circuits is provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide. The oxide grows from the substrate to fill the trench and into...

20060110883 - Method for forming a memory device: A method of forming a storage device is disclosed. A sacrificial layer is formed over a semiconductor substrate. Impurities are introduced into sacrificial layer. The substrate is annealed to precipitate discrete storage elements in the sacrificial layer. The sacrificial layer is selectively removed using a process that leaves the discrete...

20060110884 - Method of manufacturing a transistor and a method of forming a memory device: A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the isolation trenches at a position adjacent to the groove so that the two plate-like portions will be...

20060110885 - Body having angle scaling: A monolithic body having angle scaling is rotatable about an axis to measure the rotational position of a machine part. The body has a first annular region which has a flange-type configuration for connection to the machine part, and a second annular region on which the angle scaling is arranged,...

20060110886 - Mosfet structure and method of fabricating the same: A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a bird's beak structure. The gate-to-drain overlap capacitance is reduced by the bird's beak structure....

20060110887 - Microelectronic device and a method for its manufacture: Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor substrate layer with multiple openings exposing portions of the surface of...

20060110888 - Phase changeable memory device and method of formation thereof: In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to...

20060110889 - Method for fabricating a mim capacitor having increased capacitance density and related structure: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited...

20060110890 - Cut-and-paste imprint lithographic mold and method therefor: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure....

20060110891 - Method for rounding bottom corners of trench and shallow trench isolation process: A method for rounding the bottom corners of a trench is described. In the method, an etching process is performed using a fluorocarbon compound with at least two carbon atoms, He and O2 as an etching gas to round the bottom corners of the trench....

20060110892 - Semiconductor process for forming stress absorbent shallow trench isolation structures: A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to...

20060110893 - Glass-type planar substrate, use thereof, and method for the production thereof: The invented method is distinguished by a combination of the following method steps: provision of a semiconductor planar substrate composed of a semiconductor material, reduction of the thickness of the semiconductor planar substrate inside at least one surface region of the semiconductor planar substrate in order to form a raised...

20060110894 - Manufacturing method of semiconductor laser devices and manufacturing apparatus of the same: The present invention is to provide a semiconductor laser device manufacturing method for realizing highly reliable semiconductor laser devices. The semiconductor laser device manufacturing method includes: cutting a wafer into bar-shaped wafers by scanning an electron beam on the front side of the wafer on which a semiconductor laser structure...

20060110895 - Method of fabricating silicon-based mems devices: A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure...

20060110896 - Compound semiconductor particles and production process therefor: There are provided: compound semiconductor particles that can display more excellent performance in functions peculiar to the compound semiconductor (e.g. luminosity and luminescence efficiency); and a production process for obtaining such compound semiconductor particles with economy, good productivity, and ease. Compound semiconductor particles, according to the present invention, are characterized...

20060110898 - Circuitized substrates utilizing smooth-sided conductive layers as part thereof, method of making same, and electrical assemblies and information handling systems utilizing same: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer...

20060110899 - Methods for fabricating a germanium on insulator wafer: Improved fabrication processes for manufacturing GeOI type wafers are disclosed. In an implementation, a method for fabricating a germanium on insulator wafer includes providing a source substrate having a surface, at least a layer of germanium and a weakened area. The weakened area is located at a predetermined depth in...

20060110900 - Method of forming a gate of a semiconductor device: In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is...

20060110902 - Method and system for metal barrier and seed integration: A method for making an electrode in a semiconductor device. The method includes forming a trench in a first layer. The first layer is associated with a top surface, and the trench is associated with a bottom surface and a side surface. Additionally, the method includes depositing a diffusion barrier...

20060110903 - Method for formation of a contact in a semiconductor wafer: In order to form a contact in a layer on a substrate, in particular a contact in a logic circuit in a semiconductor component, the mask layer is structured for etching of the contact holes with a photoresist layer which is exposed using two masks, with the first mask containing...

20060110901 - Minimizing resist poisoning in the manufacture of semiconductor devices: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via...

20060110904 - Multiple shadow mask structure for deposition shadow mask protection and method of making and using same: The present invention is a multi-layer shadow mask and method of use thereof. The multi-layer shadow mask includes a sacrificial mask bonded to a deposition mask. The sacrificial mask provides protection against an accumulation of evaporant on the deposition mask which would cause the deposition mask to deform....

20060110905 - High surface area aluminum bond pad for through-wafer connections to an electronic package: A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads....

20060110907 - Method for removing resin mask layer and method for manufacturing solder bumped substrate: Using a dry film resist that is a photosensitive resin, a resin mask layer is formed around electrodes on a substrate. A solder precipitating composition is applied on the substrate, and this solder precipitating composition is heated to precipitate solder on the surface of the electrodes. Subsequently, in removing the...

20060110906 - Wafer alignment method: The present invention relates to a wafer alignment method. The wafer alignment method includes the steps of forming first bonding pads and first wafer alignment marks of a convex shape on predetermined regions of a first semiconductor substrate in which a first device is formed, forming second bonding pads on...

20060110908 - Method for forming wiring pattern, method for manufacturing device, device, electro-optic apparatus, and electronic equipment: A method for forming a wiring pattern according to an aspect of the invention forms a wiring pattern in a certain area on a substrate by using a droplet discharge technique, and comprises forming a bank surrounding the certain area on the substrate; discharging a first functional liquid containing a...

20060110909 - Dendrite growth control circuit: A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is...

20060110910 - Method for forming landing plug poly of semiconductor device: Disclosed is a method for forming a landing plug poly of a semiconductor device. In such a method, there is provided a substrate formed with gates, each of which has a nitride film as a gate hard mask and nitride film spacers. An insulating interlayer is formed over the entire...

20060110911 - Controlled electroless plating: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine...

20060110912 - Semiconductor devices with composite etch stop layers and methods of fabrication thereof: Semiconductor devices with composite etch stop layers and methods of fabrication thereof. An semiconductor device with a composite etch stop layer includes a substrate having a conductive member, a first etch stop layer on the substrate and the conductive member, a second etch stop layer and a dielectric layer sequentially...

20060110914 - Direct imprinting of etch barriers using step and flash imprint lithography: A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier...

20060110913 - Gate structure having diffusion barrier layer: The present invention provides a gate structure having a diffusion barrier layer and the process for fabrication thereof. A diffusion barrier layer is formed between the polysilicon layer and the tungsten silicide metal layer by using ion implantation, thereby preventing silicon ion diffusion between the polysilicon layer and the tungsten...

20060110915 - Semiconductor device having low-k dielectric film in pad region and method for manufacture thereof: A low-k dielectric film is formed on an entire surface of a substrate having a pad region and a circuit region. A resist pattern is formed on the low-k dielectric film, and an opening is formed in the low-k dielectric film of the pad region using the resist pattern as...

20060110916 - Forming an intermediate layer in interconnect joints and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise forming a first adhesion layer on a conductive layer, forming an intermediate layer on the first adhesion layer, and forming a barrier layer on the intermediate layer, wherein the intermediate layer comprises a coefficient of thermal expansion that is...

20060110917 - Method of metallization in the fabrication of integrated circuit devices: The method of metallization in the fabrication of an integrated circuit device comprises the steps as follows. First, a dielectric layer overlying a semiconductor substrate is provided. The dielectric layer has a top surface and a plurality of openings. Next, a metal layer is formed on the dielectric layer and...

20060110918 - Method and deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors: A method and a deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors using CO gas and a dilution gas. The method includes providing a substrate in a process chamber of a processing system, forming a process gas containing a metal-carbonyl precursor vapor and a CO gas,...

20060110920 - Low temperature nitride used as cu barrier layer: A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in...

20060110919 - Method of forming a wiring pattern, method of manufacturing a device, device, electro-optic device, and electronic instrument: A method of forming a wiring pattern in a predetermined area on a substrate using a droplet ejection process, including the steps of (a) forming a recess section for disposing a functional fluid in the predetermined area so that the predetermined area has a first region, a second region connected...

20060110921 - Methods for forming a structured tungsten layer and forming a semiconductor device using the same: A method for forming a structured tungsten layer and a method for forming a semiconductor device using the same. A first tungsten layer is formed with an atomic layer deposition (ALD) method. A second tungsten layer is formed on the first tungsten layer with a chemical vapor deposition (CVD) method....

20060110922 - Metallic chromonic compounds: m

20060110924 - Abrasive-free chemical mechanical polishing compositions and methods relating thereto: An aqueous abrasive-free composition is useful for chemical mechanical polishing of a patterned semiconductor wafer containing a nonferrous metal. The composition comprises an oxidizer, an inhibitor for the nonferrous metal, 0 to 15 weight percent water soluble modified cellulose, 0 to 15 weight percent phosphorus compound, 0.005 to 5 weight...

20060110923 - Barrier polishing solution: The polishing solution is useful for preferentially removing barrier materials in the presence of nonferrous interconnect metals with limited erosion of dielectrics. The polishing solution comprises 0 to 20 weight percent oxidizer, inhibitor for reducing removal rate of the nonferrous interconnect metals, ammonium salt, 0.1 to 50 weight percent silica...

20060110925 - Dry etching method and diffractive optical element: A dry etching method is provided, in which dry etching is performed in such a manner that a conductor to which an insulative substrate is attached is brought in electric, intimate contact with an electrode. In the dry etching method, the insulative substrate is attached to the conductor by means...

20060110926 - Control of photoelectrochemical (pec) etching by modification of the local electrochemical potential of the semiconductor structure relative to the electrolyte: A method for locally controlling an electrical potential of a semiconductor structure or device, and hence locally controlling lateral and/or vertical photoelectrochemical (PEC) etch rates, by appropriate placement of electrically resistive layers or layers that impede electron flow within the semiconductor structure, and/or by positioning a cathode in contact with...

20060110927 - Package for a semiconductor device: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a...

20060110928 - Etching of structures with high topography: The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatile memory applications, and for...

20060110929 - Anhydrous film for lip make-up or care: The present invention relates to a method for cladding a simple or complex surface, electrically conducting or semiconducting, by means of an organic film from at least one precursor of said organic film, characterised in that the cladding of the surface by the organic film is carried out by electro-initiated...

20060110930 - Direct liquid injection system and method for forming multi-component dielectric films: The present invention provides methods and systems for atomic layer deposition (ALD). In some embodiments a system is provided comprising: at least one direct liquid injection system configured to inject one or more deposition precursors into one or more vaporization chambers, at least one bubble system configured to vaporize one...

20060110931 - Method for forming insulation film: A method for forming an insulation film on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma CVD processing; and...

20060110932 - Method and apparatus for oxidizing nitrides: A method for oxidizing a nitride film is disclosed, which includes the steps of: providing a nitride film formed on an electrically conductive substrate; irradiating the nitride film with a light beam and getting close to the nitride film with a electrically conductive probe; and exerting a bias between the...

20060110939 - Enhanced thin-film oxidation process: A method is provided for additionally oxidizing a thin-film oxide. The method includes: providing a substrate; depositing an MyOx (M oxide) layer overlying the substrate, where M is a solid element having an oxidation state in a range of +2 to +5; treating the MyOx layer to a high density...

20060110938 - Etch stop layer: A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to...

20060110934 - Method and apparatus for forming insulating film: The present invention provides a method and apparatus for forming an insulating film having good reliability, in accordance with a process without high-temperature heating. In accordance with the present invention, in a process for forming an insulating film for a semiconductor device by oxidizing a material to be processed, exposed...

20060110937 - Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that...

20060110936 - Method of increasing deposition rate of silicon dioxide on a catalyst: Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of...

20060110933 - Plasma control method and plasma control apparatus: A method that controls the distribution of a plasma generated in a vacuum chamber, for example as part of a plasma thin film deposition or plasma etching process. For thin film deposition, the method serves to minimize variations in film thickness caused by the variations of the film deposition conditions....

20060110935 - Semiconductor device and manufacturing method thereof: A semiconductor device with a fuse 3a to be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first insulating film 11 with high filling capability and a second insulating film 12 blocking penetration of moisture or...

20060110940 - Method of preparing mesoporous thin film having low dielectric constant: A method of preparing a mesoporous thin film having a low dielectric constant, which includes mixing a cyclic siloxane-based monomer, an organic solvent, an acid catalyst or a base catalyst, and water, to prepare a coating solution, which is then applied on a substrate and heat cured. The mesoporous thin...

20060110941 - Method of improving via filling uniformity in isolated and dense via-pattern regions: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps....

20060110942 - Method of manufacturing flash memory device: A method of manufacturing flash memory devices, comprises the steps of forming an oxide film on a semiconductor substrate, performing a pre-annealing process under N2 gas atmosphere, nitrifying the oxide film by performing a main annealing process under N2O atmosphere having the flow rate of 5 to 15 slm for...

20060110943 - Remote plasma activated nitridation: A nitrogen precursor that has been activated by exposure to a remotely excited species is used as a reactant to form nitrogen-containing layers. The remotely excited species can be, e.g., N2, Ar, and/or He, which has been excited in a microwave radical generator. Downstream of the microwave radical generator and...

20060110944 - Dummy substrate for thermal reactor: A single substrate reactor system for processing batches of product substrates one at a time is provided with at least one dummy substrate. In the time after one batch of product substrates is processed and before another batch of product substrates is ready for processing, the dummy substrate is used...

20060110945 - Method using specific contact angle for immersion lithography: A method for performing immersion lithography on a semiconductor wafer is disclosed. The method includes positioning the semiconductor wafer beneath a lens and applying a fluid between a top surface of the semiconductor wafer and the lens. An additive can be provided to the top surface so that any droplet...

20060105473 - Substrate processing system, substrate processing method, sealed container storing apparatus, program for implementing the substrate processing method, and storage medium storing the program: A substrate processing system which is capable of preventing dust from becoming attached to substrates without increasing the degree of cleanliness of a clean room to a predetermined level, and also capable of increasing the substrate processing throughput without increasing the burden on workers. a plasma processing apparatus 2 that...

20060105474 - Method for manufacturing a magnetic memory device, and a magnetic memory device: In bit line cladding structure formation, stability and margin of the process are secured and further shrinking is achieved, and the magnetic memory device is improved in speed, reliability and yield. Method for manufacturing a magnetic memory device, comprising the steps of: forming a word line; forming a magnetoresistance effect...

20060105475 - Fast localization of electrical failures on an integrated circuit system and method: Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested employing a parallel electrical tester. The results of the electrical testing are analyzed to localize...

20060105476 - Photoresist pattern, method of fabricating the same, and method of assuring the quality thereof: A photoresist pattern and a method of fabricating the same make it easy to quickly identify a particular portion of a photolithography process that is responsible for causing process defects. The method of fabricating the photoresist pattern includes forming main patterns having a predetermined critical dimension in device-forming regions of...

20060105477 - Device and method for manufacturing wafer-level package: In an embodiment of the invention, a device for manufacturing a wafer-level package includes a wafer sawing unit, a sorting unit, a pickup unit, and a placing unit. The wafer sawing unit cuts a wafer into wafer-level packages. The sorting unit performs a sorting process on the wafer-level packages to...

20060105482 - Array of light emitting devices to produce a white light source: A device is provided with an array of a plurality of phosphor converted light emitting devices (LEDs) that produce broad spectrum light. The phosphor converted LEDs may produce light with different correlated color temperature (CCT) and are covered with an optical element that assists in mixing the light from the...

20060105478 - Bonding an optical element to a light emitting device: A device is provided with at least one light emitting device (LED) die mounted on a submount with an optical element subsequently thermally bonded to the LED die. The LED die is electrically coupled to the submount through contact bumps that have a higher temperature melting point than is used...

20060105479 - Method of integrating optical devices and electronic devices on an integrated circuit: A method for integrating an optical device and an electronic device on a semiconductor substrate comprises forming openings within an active semiconductor layer in a first region of the semiconductor substrate, wherein the first region corresponds to an electronic device portion and the second region corresponds to an optical device...

20060105480 - Method of making light emitting device with silicon-containing encapsulant: A method of making a light emitting device is disclosed. The method includes providing a light emitting diode and forming an encapsulant in contact with the light emitting diode; wherein forming the encapsulant includes contacting the light emitting diode with a photopolymerizable composition consisting of a silicon-containing resin and a...

20060105481 - Method of making light emitting device with silicon-containing encapsulant: A method of making a light emitting device is disclosed. The method includes the steps of providing a light emitting diode and forming an encapsulant in contact with the light emitting diode; wherein forming the encapsulant includes contacting the light emitting diode with a photopolymerizable composition consisting of a silicon-containing...

20060105483 - Encapsulated light emitting diodes and methods of making: Methods for making encapsulated light emitting diodes, and light emitting articles prepared thereby are disclosed. The methods include activating a light emitting diode to emit light to at least partially polymerize a photopolymerizable encapsulant....

20060105484 - Molded lens over led die: One or more LED dice are mounted on a support structure. The support structure may be a submount with the LED dice already electrically connected to leads on the submount. A mold has indentations in it corresponding to the positions of the LED dice on the support structure. The indentations...

20060105485 - Overmolded lens over led die: One or more LED dice are mounted on a support structure. The support structure may be a submount with the LED dice already electrically connected to leads on the submount. A mold has indentations in it corresponding to the positions of the LED dice on the support structure. The indentations...

20060105486 - Method of fabricating a liquid crystal display device: A method of fabricating a liquid crystal display device according to an embodiment of the present invention includes forming first and second conductive layers on a substrate, wherein the first layer is transparent; patterning the second conductive layer and the first conductive layer using the photo-resist pattern as a mask;...

20060105487 - Method and apparatus for fabricating flat panel display: A fabricating method of a flat panel display includes the steps of spreading an etch-resist on a thin film formed on a substrate, a polarity of the etch-resist changed by irradiation with a first light; providing a soft mold having a projected surface and a groove at an upper surface...

20060105489 - Method and apparatus providing cmos imager device pixel with transistor having lower threshold voltage than other imager device transistors: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions...

20060105488 - Method of integrating optical devices and electronic devices on an integrated circuit: A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately...

20060105490 - Microlens manufacturing method: The present invention provides a method for manufacturing a microlens in a semiconductor substrate having a first surface and a second surface, comprising the steps of preparing the semiconductor substrate, forming a first resist layer approximately cylindrical in form on the first surface of the semiconductor substrate, reflowing the first...

20060105491 - Method for treating a photovoltaic active layer and organic photovoltaic element: The invention relates to an organically based photovoltaic element, in particular a solar cell comprising a photovoltaically active layer whose absorption maximum can be shifted into the longer wavelength region and/or whose efficiency can be increased....

20060105493 - Encapsulation of organic devices: A method for encapsulating devices, in particular organic devices such as OLED-devices, comprising the steps of depositing organic active material on an active region of a substrate; providing a cap to enclose said organic active material within a space defined by a cap periphery adapted to adhere to the substrate;...

20060105492 - Organic electronic devices: A method for forming an organic electronic device, which method comprises the steps of: a) forming a negative image of a desired pattern on a substrate or device layer with a lift-off ink; b) coating a first device layer to be patterned on top of the negative image; c) coating...

20060105496 - Device and method for fabricating double-sided soi wafer scale package with through via connections: A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. A through buried oxide via connects the chip(s) to the...

20060105495 - Device and method for reshaping the interconnection elements of an electronic module using the stress reflow method and, in particular, for restoring the flatness thereof: A method and device are provided to reshape a set of conducting elements which are distributed over the inner face of an electronic module, said set of conducting elements forming means of positioning the module on a motherboard and/or electromagnetic armour means for the inner face of the module and/or...

20060105494 - Method and apparatus for cleaning and sealing display packages: A method and apparatus for cleaning and sealing components of a display utilizes continuous isolation of the components between the cleaning step and the sealing step. This limits exposure of the components to contaminants and isolates the components from oxidizing agents which can cause an oxide to form on the...

20060105497 - Forming a stress compensation layer and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening....

20060105498 - Wafer stack separator: An integrated circuit wafer container and separator combination. The separator comprises a substantially flat main area and a plurality of elevated projections in the periphery thereof. The elevated projections sustain the weight of the wafer stacks, avoid vacuum adhesion, and minimize contact with wafers....

20060105499 - Chip packaging systems and methods: An automated process for performing MEMS packaging including automatically attaching a die to a chip carrier, resulting in a chip carrier assembly, automatically moving the chip carrier assembly into a vacuum chamber, wherein the vacuum chamber includes one or more lids therein, automatically securing a lid to the chip carrier...

20060105500 - Process for fabricating chip embedded package structure: A process for fabricating a chip embedded package structure is provided. A stiffener is disposed on a tape. A chip is disposed on the tape inside a chip opening of the stiffener such that an active surface of the chip faces the tape. Through holes are formed passing the tape...

20060105501 - Electronic device with high lead density: An electronic device moldable to form a leadless electronic package and a method of forming the electronic device are provided. The electronic device comprises a die pad adapted for attachment of a die and a frame surrounding the die pad. A plurality of leads extend from the frame towards the...

20060105502 - Assembly process: An assembly process. The process includes providing a conductive substrate comprising opposing first and second surfaces, recessing the conductive substrate, forming a plurality of traces in the first surface, disposing an electronic device electrically connecting the traces, forming a patterned mask layer covering parts of the second surface of the...

20060105503 - Wafer-level sealed microdevice having trench isolation and methods for making the same: A microdevice (20) having a hermetically sealed cavity (22) to house a microstructure (26). The microdevice (20) comprises a substrate (30), a cap (40), an isolation layer (70), at least one conductive island (60), and an isolation trench (50). The substrate (30) has a top side (32) with a plurality...

20060105504 - Fabrication method of semiconductor integrated circuit device: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in...

20060105505 - Method for producing a semiconductor component and semiconductor component produced by the same: A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode....

20060105506 - Method of manufacturing a thin film transistor: A method of manufacturing a thin film transistor is described. A polysilicon island is formed over a substrate. A gate insulating layer is formed over the substrate to cover the polysilicin island. A gate is formed on the gate insulating layer above the polysilicon island. A passivation layer is formed...

20060105507 - Method to form si-containing soi and underlying substrate with different orientations: A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing...

20060105508 - Method of forming a semiconductor device: A method for integrating first and second type devices on a semiconductor substrate includes forming openings within an active semiconductor layer of a dual semiconductor-on-insulator in first and second regions of the semiconductor substrate. First and second non-MOS transistor device implant regions are formed within portions of an intermediate semiconductor...

20060105509 - Method of forming a semiconductor device: A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a non-MOS transistor device portion and the second region corresponds to...

20060105510 - Transistor or semiconductor device and method of fabricating the same: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive...

20060105513 - Device comprising doped nano-component and method of forming the device: A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising...

20060105511 - Method of manufacturing a mos transistor: A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region...

20060105512 - Method to improve drive current by increasing the effective area of an electrode: The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the...

20060105514 - Thin film semiconductor device and method of manufacturing the same: Two kinds of a thin film semiconductor unit are disposed over a substrate. A first thin film semiconductor unit includes a polycrystalline semiconductor thin film, and a second thin film semiconductor unit includes an amorphous semiconductor thin film....

20060105516 - Oxidation method for altering a film structure: A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed...

20060105515 - Process options of forming silicided metal gates for advanced cmos devices: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top...

20060105517 - Method in the fabrication of an integrated injection logic circuit: A method in the fabrication of an I2L circuit comprises (i) forming a common base of a lateral bipolar transistor and emitter of a vertical bipolar multicollector transistor, a common collector of the lateral transistor and base of the vertical multicollector transistor, and an emitter of the lateral transistor in...

20060105518 - Ultra-shallow arsenic junction formation in silicon germanium: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20)....

20060105519 - Dram on soi: In a semiconductor manufacturing process for a dynamic random access memory, a buried insulator layer such as a buried SIMOX layer between trench capacitors isolates the capacitor from the access transistor, limiting leakage, improving device performance and simplifying manufacturing....

20060105520 - Structure and method to fabricate a protective sidewall liner for an optical mask: Methods and structures for optical masks that have a liner on the trench sidewalls. An example embodiment comprises a mask structure for use with light at a wavelength comprising: a substrate having a first region, a second region and a third region; a first trench in the first region; a...

20060105521 - Method of manufacturing semiconductor device: Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating layer corresponding to a capacitor forming region so that the lower electrode is not...

20060105523 - Chemical doping of nano-components: A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided for forming a field effect transistor comprising a nano-component that has been doped using such a dopant....

20060105525 - Method for forming non-volatile memory device: A method for forming a non-volatile memory device is provided. According to the method, a device isolation layer defining an active region is formed on the device isolation layer. An upper surface of the device isolation layer is formed higher than a surface of the substrate to form a gap...

20060105522 - Method of forming a nanocluster charge storage device: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer...

20060105524 - Non-volatile device manufactured using ion-implantation and method of manufacture the same: Embodiments of the invention include a non-volatile memory device manufactured using ion-implantation, and a method of manufacturing the same. A dielectric layer may be formed on a semiconductor substrate, and an ion implantation layer, which may be used as a charge trapping site, may be formed by ion implantation with...

20060105526 - Method of fabricating a bottle trench and a bottle trench capacitor: A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent...

20060105528 - High voltage mosfet having si/sige heterojunction structure and method of manufacturing the same: Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a...

20060105527 - Semiconductor device and manufacturing method therefor: A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film; forming a mask material so as to expose an upper surface of the first gate electrode while keeping...

20060105529 - Methods of forming mos transistors having buried gate electrodes therein: Methods of forming field effect transistors having buried gate electrodes include the steps of forming a semiconductor substrate having a sacrificial gate electrode buried beneath a surface of the semiconductor substrate and then removing the sacrificial gate electrode to define a gate electrode cavity beneath the surface. The gate electrode...

20060105530 - Method for fabricating semiconductor device: A method for fabricating a semiconductor device with high-k materials. A high-k dielectric layer is formed on a substrate, followed by a fluorine-containing treatment of the high-k dielectric layer, forming an interface containing Si—F bonds....

20060105531 - Method of forming notched gate structure: A method of forming a notched gate structure comprising a semiconductor substrate having a first oxide layer formed thereon. A first conductive layer is formed on the semiconductor substrate. A portion of the first conductive layer and a portion of the first oxide layer are removed to form first gate...

20060105532 - Integrated circuit and method for manufacturing an integrated circuit on a chip: An integrated circuit and method for manufacturing an integrated circuit on a chip is provided, whereby a first bipolar transistor has a first collector region of a first conductivity type and a second bipolar transistor has a second collector region of the first conductivity type. The method includes the steps...

20060105533 - Method for engineering hybrid orientation/material semiconductor substrate: The embodiments provide a structure and a method of manufacturing a semiconductor structure that has a different material in the area where PMOS devices will be formed than in the area where NMOS devices will be formed which is characterized as follows. An embodiment comprises the following steps. A substrate...

20060105534 - High q factor integrated circuit inductor: An inductor and a method of forming and the inductor, the method including: (a) forming a dielectric layer on a top surface of a substrate; (b) forming a lower trench in the dielectric layer; (c) forming a resist layer on a top surface of the dielectric layer; (d) forming an...

20060105535 - Integrated circuit and method for manufacturing an integrated circuit on a semiconductor chip: An integrated circuit on a semiconductor chip is provided with a first bipolar transistor and a second bipolar transistor. The first bipolar transistor has a first collector region of a first conductivity type, grown by at least one epitaxial layer, and the second bipolar transistor has a second collector region...

20060105536 - Trench capacitor with hybrid surface orientation substrate: Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI arrays and logic transistors on (100) surface orientation silicon,...

20060105538 - Method for forming semiconductor device capable of preventing bunker defect: Disclosed is a method for preventing a bunker defect generation on a lower portion of a cylinder type metal bottom electrode. The method includes the steps of: forming an etch stop layer on a bottom structure with a conductive region and an insulation region; forming a capacitor insulation layer on...

20060105537 - Method for forming storage electrode of semiconductor device: A method for forming a storage electrode of a semiconductor device is provided, the method including forming an oxide film on a lower insulating layer disposed on a semiconductor substrate, forming a hard mask silicide layer pattern defining a strode electrode region on the oxide film, subjecting the hard mask...

20060105539 - Method of detecting etching end-point: A method of detecting an etching end-point includes the steps of: forming a mask on a pattern area of an etching object; forming an etching indicator on an etching area of the etching object, which is not covered by the mask; etching the etching object using the mask; and evaluating...

20060105540 - Method for manufacturing semiconductor element: A method for manufacturing a semiconductor element comprised of an SOI structure including an SOI layer comprises the steps of preparing the SOI layer having a transistor forming area and an element isolation area on a surface thereof, forming an oxidation-resistant mask layer on the surface of the SOI layer,...

20060105541 - Trench isolation method for semiconductor devices: A trench isolation method for semiconductor devices, the method includes the steps of: successively depositing a pad oxide film and a nitride film on a semiconductor substrate and then selectively removing the pad oxide film and the nitride film to form a mask pattern; forming trench regions in the semiconductor...

20060105542 - Method for fabricating and separating semiconductor devices: A method of fabricating and separating semiconductor structures comprises the steps of: (a) partially forming a semiconductor structure attached to a support structure, the partially formed semiconductor structure comprising a plurality of partially formed devices, where the partially formed devices are attached to one another by at least one connective...

20060105543 - Cmos-mems process: A fully CMOS compatible MEMS multi-project wafer process comprises coating a layer of thick photoresist on a wafer surface, patterning the photoresist to define a micromachining region, and performing a micromachining in the micromachining region to form suspended microstructures....

20060105545 - Methods for dicing a released cmos-mems multi-project wafer: Simple but practical methods to dice a CMOS-MEMS multi-project wafer are proposed. On this wafer, micromachined microstructures have been fabricated and released. In a method, a photoresist is spun on the full wafer surface, and this photoresist is thick enough to cover all cavities and structures on the wafer, such...

20060105544 - Protective film agent for laser dicing and wafer processing method using the protective film agent: A protective film agent for laser dicing according to the present invention comprises a solution having, dissolved therein, a water-soluble resin and at least one laser light absorber selected from the group consisting of a water-soluble dye, a water-soluble coloring matter, and a water-soluble ultraviolet absorber. The protective film agent...

20060105546 - Wafer dividing method: A method of dividing a wafer having a plurality of micro electro mechanical systems and a plurality of streets for partitioning the micro electro mechanical systems formed on the front surface of a wafer substrate, the method comprising a protective tape affixing step for affixing a protective tape to the...

20060105547 - Application of a thermally conductive thin film to a wafer backside prior to dicing to prevent chipping and cracking: A thermally conductive protective film or layer is applied to the backside surface of a semiconductor wafer prior to a subsequent dicing operation performed on the wafer to singulate the wafer into diced semiconductor chips, during which the thin thermally conductive film minimizes and prevents chipping and cracking damage to...

20060105548 - Substrate processing apparatus, program for performing operation and control method thereof, and computer readable storage medium storing the program: A computer readable storage medium storing a program for performing an operation method of a substrate processing apparatus is provided. The operation method includes the steps of introducing a nonreactive gas into the vacuum preparation chamber before the gate valve is opened while the substrate is transferred between the vacuum...

20060105549 - Manipulation of micrometer-sized electronic objects with liquid droplets: A system for manipulating a small object (3) comprising a substrate to receive the small object (3), a liquid droplet (4), which carries the small object (3) on the substrate, and a pre-treated surface structure of the substrate in the vicinity (1,2) of the placement position (1) of the small...

20060105550 - Method of depositing material on a substrate for a device: The present invention provides a method of depositing material on a substrate for a device. The method includes providing the substrate having a deformable surface. The method also includes imprinting a structure into the deformable surface in a manner such that a base surface and at least one projection is...

20060105551 - Method of manufacturing a polysilicon layer and a mask used therein: A method of manufacturing a polysilicon layer is provided. Firstly, a substrate is provided. Next, an amorphous silicon having a first region and a second region is formed on the substrate. After that, the amorphous silicon layer in the first region is completely melted and the amorphous silicon layer in...

20060105552 - Apparatus and method of activating impurity atom in manufacture of semiconductor device: An apparatus and a method of activating an impurity atom doped into a semiconductor material use of a resonant principle. Impurity atoms are doped into the semiconductor material, and microwaves having the same frequency as a natural frequency of vibration of the impurity are applied to the semiconductor material. The...

20060105553 - Reversible oxidation protection of microcomponents: In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to protect it against oxidation, an insulation layer is applied to the silicon nitride layer, and a reoxidation process is carried out. In the reoxidation...

20060105554 - Method for solid phase diffusion of zinc into an inp-based photodiode and an inp photodiode made with the method: In order to form a p-region in an InP-based photodiode, zinc doping must be performed. Due to the current trend toward the implementation of larger-sized InP wafers, there is a need for a solid phase diffusion method in which a ZnO thin film is applied to an epitaxial wafer, the...

20060105555 - Display apparatus and control method thereof: A gantry apparatus includes a pair of first guides disposed parallely each other, a pair of sliders respectively coupled to the pair of first guides to move together with the first guides; a second guide coupled to the pair of sliders to move along the sliders; a head coupled to...

20060105556 - Semiconductor device and method of manufacturing the same: The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due...

20060105557 - Method of making fully silicided gate electrode: A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon...

20060105558 - Inter-metal dielectric scheme for semiconductors: System and method for providing an inter-metal dielectric that prevents or reduces film delamination and contact corrosion defects is provided. A preferred embodiment comprises forming a chemical-mechanical polishing (CMP) stop layer over the surface of an inter-metal dielectric prior to forming interconnects and vias. Interconnect and vias may be formed...

20060105559 - Ultrathin buried insulators in si or si-containing material: A method for forming an ultra thin buried oxide layer is described incorporating the steps of forming a first epitaxial layer containing Si on a Si containing substrate having a thickness from about 10 to about 300 angstroms thick, forming a second epitaxial layer containing Si having a thickness from...

20060105560 - Method for forming solder bumps of increased height: A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is...

20060105561 - Method of manufacturing a self-aligned contact structure: The present invention provides a method of manufacturing a self-aligned contact structure comprising a semiconductor substrate having at least two gate stack structures formed thereon. A dielectric layer is formed over the gate stack structures. Each gate stack structure has a nitride layer surface. A portion of the dielectric layer...

20060105562 - Method to make nano structure below 25 nanometer with high uniformity on large scale: A method of making a nano structure smaller than 25 nanometers utilizing atomic layer deposition, planarizing, and etching techniques....

20060105564 - Method and system for reducing inter-layer capacitance in integrated circuits: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer....

20060105563 - Method of forming a semiconductor device: A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding dishing above the semiconductor device during chemical mechanical polishing. The...

20060105565 - Method and apparatus for copper film quality enhancement with two-step deposition: The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for a duration of time to remove any impurities, depositing...

20060105567 - Method for forming a dual-damascene structure: A dual-damascene structure is formed in a porous dielectric material using an anti-reflective coating. In accordance with one embodiment, during patterning and etching if the trench portions of the dual-damascene structure, the anti-reflective coating has a first density. After patterning and etching, the anti-reflective coating density is reduced. The reduction...

20060105566 - Ultraviolet assisted pore sealing of porous low k dielectric films: Processes for sealing porous low k dielectric film generally comprises exposing the porous surface of the porous low k dielectric film to ultraviolet (UV) radiation at intensities, times, wavelengths and in an atmosphere effective to seal the porous dielectric surface by means of carbonization, oxidation, and/or film densification. The surface...

20060105568 - Plasma treatment for surface of semiconductor device: A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about...

20060105569 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device is disclosed. The method for manufacturing a