Semiconductor device manufacturing: process inventions 04/06

20060088947 - Magnetoresistive random access memory device structures and methods for fabricating the same: Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched...

20060088949 - Early detection of metal wiring reliability using a noise spectrum: The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspect a substrate for various noise spectrum signatures....

20060088948 - Fluid storage and dispensing system including dynamic fluid monitoring of fluid storage and dispensing vessel: A monitoring system for monitoring fluid in a fluid supply vessel during operation including dispensing of fluid from the fluid supply vessel. The monitoring system includes (i) one or more sensors for monitoring a characteristic of the fluid supply vessel or the fluid dispensed therefrom, (ii) a data acquisition module...

20060088950 - Fabrication method of multi-wavelength semiconductor laser device: The present invention relates to a two-wavelength semiconductor laser device, more particularly, to a fabrication method of a multi-wavelength semiconductor laser device. In this method, a substrate having an upper surface separated into at least first and second areas is provided. Then, a first dielectric mask on the substrate is...

20060088951 - Method of manufacturing organic electroluminescent device and organic electroluminescent device: A method of manufacturing an organic electroluminescent device, which, on a substrate, has a plurality of first electrodes, a light-emitting functional layer disposed to correspond to formation positions of the first electrodes, and a second electrode covering the light-emitting functional layer, includes forming a buffering layer that covers the second...

20060088952 - Method and system for focused ion beam directed self-assembly of metal oxide island structures: A process for guiding the growth of metal oxide islands of material which involves: presenting a metal oxide surface to a charged particle beam; impinging the metal oxide surface with ions from the charged particle beam; presenting said metal oxide surface to a deposition chamber; coating said surface with vapor...

20060088953 - Method for flip chip bonding by utilizing an interposer with embedded bumps: The present invention relates to a method for flip chip bonding by utilizing an interposer with embedded bumps. The method comprises (a) providing a first element having a first surface; (b) forming an interposer onto the first surface; (c) forming a plurality of openings on the interposer; (d) forming a...

20060088955 - Chip package, chip packaging, chip carrier and process thereof: A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductive plugs. Based on the above-described design, the chip package is capable of...

20060088954 - Electronic component with cavity fillers made from thermoplast and method for production thereof: An electronic component and a method for fabricating it is disclosed, where the component comprises a semiconductor chips which has flip-chip contacts. These contacts are fixed on a rewiring substrate, the interspace between the rewiring substrate and the semiconductor chip being filled with a thermoplastic. The glass transition temperature of...

20060088956 - Method for fabricating semiconductor package with short-prevented lead frame: A short-prevented lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein each lead of the lead frame is formed with a thickness-reduced portion at a peripheral position of the lead frame, allowing thickness-reduced portions of adjacent leads to be arranged in a...

20060088957 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device formed by stacking a plurality of semiconductor elements on a substrate, comprises the steps of stacking the plurality of semiconductor elements on the substrate to form plural stages, placing the substrate substantially vertically and charging an underfill agent into spaces defined between the...

20060088958 - Integrated circuit with multi-length output transistor segment: A monolithic integrated circuit fabricated on a semiconductor die includes a control circuit and a first output transistor having segments substantially equal to a first length. A second output transistor has segments substantially equal to a second length. The first and second output transistors occupy an L-shaped area of the...

20060088959 - Processing method and processing apparatus: A processing method of subjecting at least two stacked films, which comprise a first film and a second film of a target object to be processed, to a removing process by wet etching comprises bringing a first process liquid into contact with the first film of the target object, thereby...

20060088961 - Method of fabricating poly crystalline silicon tft: A method of fabricating a poly crystalline silicon thin film transistor (TFT) is provided. The method includes the operations of forming a poly crystalline silicon having a source, a drain, and a channel region between the source and the drain on a substrate in a predetermined pattern; forming an insulating...

20060088960 - Semiconductor material, field effect transistor and manufacturing method thereof: The silicon wires formed around metal particles by crystal growth have the problem of metal pollution. For its solution, in the present invention, a silicon bridge is formed through standard silicon processes such as the lithography and the wet etching using hydrofluoric acid performed to an SOI substrate. Thereafter, a...

20060088962 - Method of forming a solution processed transistor having a multilayer dielectric: Embodiments of methods, apparatuses, devices, and/or systems for forming a solution processed transistor having a multilayer dielectric are described....

20060088963 - Method of manufacturing semiconductor device: An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus, the oxide...

20060088964 - Method of forming sram cell: A method of forming an SRAM cell, having two transfer transistors, two driver transistors, and two load devices which are connected with one another in the form of a flip-flop is provided. In particular, after defining an active region and an inactive region on a silicon substrate, a gate electrode...

20060088965 - Method of fabricating flash memory device: A method of fabricating a flash memory device is disclosed where a trench formation process and a wall oxide film formation process are performed separately depending on a pattern density, and wall oxide films are formed with different thicknesses. Accordingly, an increase in a thickness of the wall oxide films...

20060088966 - Semiconductor device having a smooth epi layer and a method for its manufacture: Provided are a semiconductor device and a method for manufacturing such a device by varying the pressure used to form silicon-germanium (SiGe) layers on a substrate such that a first layer is formed at a substantially higher pressure than a second layer that is formed on the first layer....

20060088967 - Finfet transistor process: The present invention provides a method of manufacturing a FinFET transistor, comprising the steps of: forming a plurality of trenches in a semiconductor substrate, forming a dielectric layer on the semiconductor substrate and filling the trenches, and etching back the dielectric layer to a level below the surface of the...

20060088968 - Methods of fabricating a semiconductor device using a selective epitaxial growth technique: Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an...

20060088969 - Solid phase epitaxy recrystallization by laser annealing: Methods (70) are described for fabricating shallow and abrupt gradient drain extensions for MOS type transistors, in which a solid phase epitaxial recrystallization is performed within the drain extensions utilizing a laser SPER annealing process in the manufacture of semiconductor products. One method (70) includes a preamorphizing process (74) of...

20060088970 - Apparatus and method for the low-contamination, automatic crushing of silicon fragments: A crusher for producing fine silicon fragments for semiconductor or solar applications from silicon fragments suitable for semiconductor or solar applications, comprises a plurality of crushing tools, the crushing tools having a surface made from a hard, wear-resistant material, wherein the crusher has a comminution ratio e of from 1.5...

20060088972 - Electrode for electrolytic capacitor, electrolytic capacitor, and manufacturing method therefor: An electrode for electrolytic capacitors having a large capacitance and having excellent tan δ, heat resistance, humidity resistance and stability. An electrolytic capacitor using the electrode. An electrode obtained by attaching a compound having a siloxane bond onto the surface of an electrode body comprising a valve-acting metal having formed...

20060088971 - Integrated inductor and method of fabrication: An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section....

20060088973 - Methods of fabricating integrated circuit devices having resistors with different resistivities and devices formed thereby: Methods of forming integrated circuit devices include forming patterned layers having different resistivities on semiconductor substrates. These methods include forming a first electrically conductive layer having a first resistivity on first and second portions of a semiconductor substrate. The first portion of the semiconductor substrate may include a memory cell...

20060088974 - Method of affecting rram characteristics by doping pcmo thin films: A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer....

20060088975 - Method for fabricating semiconductor device and semiconductor device: A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first...

20060088977 - Method of forming an isolation layer in a semiconductor device: Disclosed herein is a method of forming an element isolation film of a semiconductor device. An aluminum oxide film of a high wet etch rate is used as a pad oxide film, a trench is formed, and top and bottom edges of the trench is made rounded while removing some...

20060088976 - Methods and compositions for chemical mechanical polishing substrates: Methods and compositions are provided for planarizing a substrate surface with reduced or minimal defects in surface topography. In one aspect, a method is provided for processing a substrate comprising a dielectric material and polysilicon material disposed thereon, polishing the polysilicon material with a high topography selective polishing composition, and...

20060088978 - Method of making a semiconductor structure for high power semiconductor devices: A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiO2 and a third layer of Si, has its third layer of Si...

20060088979 - Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same: A method for fabricating a semiconductor structure having a high-strained crystalline layer with a low crystal defect density is disclosed. The structure includes a substrate having a first material comprising germanium or a Group(III)-Group(V)-semiconductor or alloy thereof. In addition, a crystalline epitaxial first layer, comprising a graded buffer layer and...

20060088980 - Method of singulating electronic devices: A method of singulating electronic devices, including aligning a saw blade over a lid street disposed on a lid substrate that is disposed over a device substrate. An electronic device that includes a bond pad is disposed on the device substrate, wherein the lid street is disposed over the bond...

20060088982 - System method and apparatus for dry-in, dry-out, low defect laser dicing using proximity technology: A substrate processing system includes a first, movable surface tension gradient device, a dicing device and a system controller. The first, movable surface tension gradient device is capable of supporting a first process within a first meniscus. The first meniscus being supported between the first surface tension gradient device and...

20060088981 - Wafer packaging and singulation method: A method includes providing a micro device wafer having micro devices supported by a wafer substrate and a multi-device lid substrate coupled to and spaced from the wafer substrate. The method further includes sawing through the multi-device lid substrate to a depth between the wafer substrate and the lid substrate....

20060088983 - Method of dividing wafer: In order to efficiently divide the wafer into individual devices in dicing the wafer without deteriorating the quality of the devices, the front surface of the wafer is coated with a resist film except the regions corresponding to the streets, grooves of a depth corresponding to the finished thickness of...

20060088984 - Laser ablation method: A combination of specific laser pulse durations and repetition rates are incorporated into a semiconductor wafer laser scribing/dicing process. The disclosed combination can reduce factors that contribute to thermal effects, explosive melting and evaporation, and laser/plasma interactions, thereby reducing problems with microcracks, delamination, and particles that can affect semiconductor die...

20060088985 - Low temperature silicon compound deposition: Sequential processes are conducted in a batch reaction chamber to form ultra high quality silicon-containing compound layers, e.g., silicon nitride layers, at low temperatures. Under reaction rate limited conditions, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. Trisilane flow is interrupted. A silicon nitride...

20060088986 - Method of enhancing laser crystallization for polycrystalline silicon fabrication: An amorphous silicon layer and at least a heat-retaining layer are formed on a substrate in turn. Wherein, the heat-retaining layer is controlled to have an anti-reflective thickness for reducing the threshold laser energy to effect the melting of the amorphous silicon layer. Then, a laser irradiation process is performed...

20060088987 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes forming an insulation pattern over a substrate. The insulation pattern has at least one opening that exposes a surface of the substrate. Then, a first polysilicon layer is formed over the substrates such that the first polysilicon layer fills the opening. The...

20060088988 - Method for forming silicon-germanium in the upper portion of a silicon substrate: A method for forming silicon-germanium in the upper portion of a silicon substrate, including the steps of: depositing a germanium layer doped at a concentration in dopant elements greater than 1019 atoms per cm3 on a silicon substrate; heating to have the germanium diffuse into the silicon substrate to form...

20060088989 - Method of introducing impurity, device and element: A method of introducing an impurity and an apparatus for introducing the impurity forms an impurity layer easily in a shallower profile. Component devices manufactured taking advantage of these method or apparatus are also disclosed. When introducing a material to a solid substance which has an oxidized film or other...

20060088990 - Local interconnect manufacturing process: The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a...

20060088991 - Method of forming metal line in semiconductor memory device: The present invention relates to a method of forming a metal line of a semiconductor memory device. According to the present invention, after a drain contact plug formed within an interlayer insulating film protrudes, a nitride film is formed on the top of the drain contact plug, and a trench...

20060088992 - Bumping process and structure thereof: A bumping process is provided as following: at first, providing a wafer, then forming a first photo-resist layer on a active surface of the wafer and forming at least a first opening on the first photo-resist layer; and forming a first copper pillar in the first opening; then forming a...

20060088993 - Iridium oxide nanostructure patterning: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas...

20060088994 - Manufacturing method to construct semiconductor-on-insulator with conductor layer sandwiched between buried dielectric layer and semiconductor layers: A method for treating exposed metal in a semiconductor wafer (301) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer (307) and a substrate (303), wherein a portion of the metal layer is exposed at the edge...

20060088995 - Metal barrier cap fabrication by polymer lift-off: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects....

20060088996 - Buffer zone for the prevention of metal migration: Particle migration, such as silver electro-migration, on a flat ceramic surface is effectively eliminated by an upward vertical barrier formed on the surface or a groove formed in the surface between two silver conductors....

20060088997 - Method to produce low strength temporary solder joints: The present invention provides a method for producing a temporary chip carrier for semiconductor chip burn-in test and speed sorting. A multi-layered substrate or card, usually comprised of one of various materials is made by offsetting the conductor-filled vias or holes in the outer few layers with the outer most...

20060088998 - Wiring pattern forming method, film pattern forming method, semiconductor device, electro-optical device, and electronic equipment: A wiring pattern forming method which is a method of forming a wiring pattern by using a liquid droplet ejection method on a preset area on a substrate, includes: forming a bank on the preset area on the substrate; ejecting a functional liquid including a wiring pattern material on an...

20060088999 - Methods and compositions for chemical mechanical polishing substrates: Methods and compositions are provided for planarizing a substrate surface with reduced or minimal defects in surface topography. In one aspect, a method is provided for processing a substrate comprising a dielectric material and polysilicon material disposed thereon, polishing the polysilicon material with a high topography selective polishing composition, and...

20060089000 - Material and process for etched structure filling and planarizing: In the back end of integrated circuits employing low-k interlevel dielectrics, etched structures are filled with a planarizing material comprising a cyclic olefin polymer and solvent; the next pattern to be etched is defined in a photosensitive layer above the planarizing layer; the pattern is etched in the dielectric and...

20060089001 - Localized use of high-k dielectric for high performance capacitor structures: Techniques are provided for localized use of high-K dielectric material within a capacitor structure. Low-K dielectric is deposited or spun on as usual. Then, a larger area is etched back and then filled with high-K dielectric material. The high-K dielectric material is then patterned and copper routing lines are trenched...

20060089002 - Method to form etch and/or cmp stop layers: In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is non-conformal in that the oxide is thicker over the gate and over the substrate than it is on the side of the gate. A...

20060089003 - Method for removing polymer as etching residue: A method for removing polymer as an etching residue is described. A substrate with polymer as an etching residue thereon is provided, and a hydrogen-containing plasma is used to treat the substrate. A wet clean step is then performed to remove the polymer from the substrate. The treatment using hydrogen-containing...

20060089004 - Adhering and releasing method for protective tape: In a protective tape applying and separating method according to this invention, a protective tape applied by a tape applying mechanism to a surface of a wafer suction-supported by a chuck table is cut to a wafer configuration by a cutter unit. Subsequently, a protective tape having a weaker adhesion...

20060089005 - Photoresist conditioning with hydrogen ramping: A method for etching a feature in an etch layer through a photoresist mask over a substrate is provided. A substrate with an etch layer disposed below a photoresist mask is placed in a process chamber. The photoresist mask is conditioned, wherein the conditioning comprises providing a conditioning gas comprising...

20060089006 - Metal oxide layer formed on substrates and its fabrication methods: The present invention is directed to a new semiconductor film comprising of metal oxide grown on a substrate and its fabrication method. The metal oxide is comprised of molybdenum oxide which is very useful to fabricate electronic devices with high withstand voltages and photonic and electronic hostile-environment devices. An important...

20060089007 - In situ deposition of a low k dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application: The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier...

20060089008 - Methods of manufacturing silicon oxide isolation layers and semiconductor devices that include such isolation layers: Methods of manufacturing silicon oxide layers for semiconductor devices are provided in which a substrate having a recess is coated with a spin-on-glass film so that the recess is filled with the spin-on-glass film. A main thermal treatment is performed on the spin-on-glass film at about 600 to about 1,000°...

20060084187 - Starved source diffusion for avalanche photodiode: This disclosure is concerned with starved source diffusion methods for forming avalanche photodiodes are provided for controlling an edge effect. In one example, a method for manufacturing an avalanche photodiode includes forming an absorber layer and an avalanche layer over a substrate. Next, a patterned mask defining one or more...

20060084189 - Characterizing the integrity of interconnects: The present invention provides for a system and method of characterizing the integrity of a barrier structure. The barrier structure is an interconnect comprising a porous dielectric layer sandwiched between at least one barrier layer and at least one conducting layer. The method of characterizing the integrity of such an...

20060084188 - Method for temperature control in a rapid thermal processing system: A method is disclosed for a multi-zone interference correction processing for a rapid thermal processing (RTP) system. This processing allows for improved calibration/tuning of RTP systems by accounting for zone coupling. The disclosed method includes establishing baseline characteristic data and zone characteristic data, and then using the baseline and zone...

20060084190 - Process for the surface treatment of a component, and apparatus for the surface treatment of a component: Components which are subject to operating loads can often be passed for refurbishment by means of an acid treatment. The time for which the components remain in the acid has hitherto been determined empirically, which means that individual loads are not taken into account. The process according to the invention...

20060084191 - Packaging method for an electronic element: A packaging method for an electronic element has: etching portions of a top surface of a metal board to form recesses between raised unetched segments and filling the recesses with a dielectric material of high density polymer; forming multiple solder balls respectively on the raised unetched segments; coating the solder...

20060084192 - Process for forming sharp silicon structures: A method of forming a sharp silicon structure, such as a silicon field emitter, includes oxidizing the silicon structure to form an oxide layer thereon, then removing the oxide layer. Oxidizing may occur at a low temperature and form a relatively thin (e.g., about 20 Å to about 40 Å)...

20060084193 - Method for fabricating liquid crystal displays with plastic film substrate: A method for fabricating LCDs based on a plastic film is disclosed. The disclosed method comprise the steps of: attaching a double-sided adhesive tape to a supporting plate using one side thereof; fixing a plastic film substrate onto the supporting plate using an unused side of the double-sided adhesive tape...

20060084195 - Methods for fabricating solid state image sensor devices having non-planar transistors: Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current....

20060084194 - Photosensitive structure and method of fabricating the same: A photosensitive structure and method of fabricating the same. A substrate with at least an insulator layer formed thereon is provided. The insulator layer comprises a plurality of photoreceiving regions, and a plurality of conductive patterns are formed thereon without covering the photoreceiving regions. A dielectric layer is formed on...

20060084196 - Method for regeneration of an electrolysis bath for the production of a compound i-iii-vi sb in thin layers: The invention relates to the regeneration of an electrolysis bath for the production of I-III-VI<SB>Y</SB> compounds in thin layers, where y is approaching 2 and VI is an element including selenium, whereby selenium is regenerated in the form Se(IV) and/or with addition of oxygenated water to reoxidise the selenium in...

20060084197 - Wafer-level diamond spreader: An embodiment of the present invention is a technique to heat spread at wafer level. A silicon wafer is thinned. A chemical vapor deposition diamond (CVDD) wafer processed. The CVDD wafer is bonded to the thinned silicon wafer to form a bonded wafer. Metallization is plated on back side of...

20060084198 - Electrostatically actuated low response time power commutation micro-switches: The field of the invention is that of microsystems of the electrostatically actuated microswitch type that are used in electronics to carry out switching functions, especially in the microwave field for mobile telephony and radars. The object of the invention is to improve the performance of the switch by reducing...

20060084200 - Individually adaptable device surface: The invention relates to device with electronic component which covers at least a part of a surface of the device. In order, even with large-scale mass production of a device, to allow the greatest possible individualization there is provision for the electronic component to feature both a number of switch...

20060084199 - Processing method during a package process: A processing method for preventing the lead fingers of a lead-frame from over-wetting and the conductive bumps from necking. After a flip chip is mounted to the lead fingers and before the reflowing process is conducted, the whole package structure is reversed so that conductive bumps are inclined to flow...

20060084201 - Parts for deposition reactors: Processing methods and internal reactor parts avoid peeling and particle generation caused by differences in the coefficients of thermal expansion (CTE's) between reactor parts and films deposited on the reactor parts in hot wall CVD chambers. Conventional materials for reactor parts have relatively low CTE's, resulting in significant CTE differences...

20060084202 - Wafer level process for manufacturing leadframes and device from the same: A wafer level process for fabricating leadframes is disclosed. A first mask is formed over an active surface of a wafer. The first mask includes a plurality of openings aligned with the wafer electrodes for forming a plurality of first leads on the wafer. A second mask is formed over...

20060084203 - Method for fabricating quad flat non-leaded package: The present invention discloses a method for fabricating a quad flat non-leaded package. A lead frame is disposed on a lower mold equipped with a resilient film. The lead frame includes at least a package unit comprising a chip pedestal and a plurality of pins spatially disposed around the chip...

20060084204 - Method of manufacturing a thin film transistor: A method of manufacturing a thin film transistor is provided. The method includes forming an amorphous silicon layer on a substrate, forming a source region, a drain region, and a region of a plurality of channels electrically interposed between the source region and the drain region by patterning the amorphous...

20060084205 - Method of manufacturing thin film device electro-optic device, and electronic instrument: A method of manufacturing a thin film device, comprises: forming a pair of multi-layered structures each formed by bonding a transfer layer including a thin film device to a temporary transfer substrate, including; forming the transfer layer on a transfer-source substrate via a first separation layer separated in accordance with...

20060084206 - Thin-film pattern forming method, semiconductor device, electro-optic device, and electronic apparatus: A thin-film pattern forming method that deposits a plurality of thin films on a substrate to form a thin-film pattern, includes: forming a second thin film on the substrate, the second thin film having an affinity for a functional liquid containing a thin-film material that makes up a first thin...

20060084207 - Channel orientation to enhance transistor performance: P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their...

20060084208 - Semiconductor device and its manufacture method: A simplified method of manufacturing a multi-voltage semiconductor integrated circuit device. A method of manufacturing a semiconductor device includes the steps of: forming a first gate insulating film with a first thickness in a first area of a semiconductor substrate: forming a second gate insulating film with a second thickness...

20060084213 - Light emitting device and method for manufacturing the same: A light emitting element containing an organic compound has a disadvantage in that it tends to be deteriorated by various factors, so that the greatest problem thereof is to increase its reliability (make longer its life span). The present invention provides a method for manufacturing an active matrix type light...

20060084211 - Method for fabricating a body contact in a finfet structure and a device including the same: A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two...

20060084209 - Method for fabricating power mosfet: A method for fabricating a power MOSFET, comprising an epitaxial layer, a gate dielectric layer and a gate layer formed on a substrate, the gate dielectric layer and the gate layer defined to form a gate structure, a stacked mask and the surface of the epitaxial layer partially exposed between...

20060084210 - Method of forming a low thermal resistance device and structure: A semiconductor device is formed to have a shape that reduces the thermal resistance of the semiconductor device....

20060084212 - Planar substrate devices integrated with finfets and method of manufacture: A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semiconductor layer over the buried insulator layer. The structure further comprises a FinFET over the buried insulator...

20060084214 - Scalable gate and storage dielectric: Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with...

20060084215 - Semiconductor device and method for manufacturing the same: Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the...

20060084216 - Transistor with strain-inducing structure in channel: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which...

20060084217 - Plasma impurification of a metal gate in a semiconductor fabrication process: A semiconductor fabrication includes forming a gate dielectric overlying a semiconductor substrate and depositing a metal gate film overlying the gate dielectric. Following deposition of the metal gate film, nitrogen, carbon, and/or oxygen is introduced into the metal gate film by exposing the metal gate film to a nitrogen, carbon,...

20060084219 - Advanced nrom structure and method of fabrication: A method for creating a non-volatile memory array includes generating polysilicon columns on top of an oxide-nitride-oxide (ONO) layer, creating spacing elements on the sides of the polysilicon columns, implanting bit lines into the substrate at least between the spacing elements, depositing oxide filler over the bit lines, depositing a...

20060084218 - Method and apparatus for providing an instrument playing service: A method and apparatus for providing an instrument playing service in a portable terminal. In the method, an image of an instrument is projected. User finger movements on the projected instrument image are detected and sound source information corresponding to the user finger movements is read. Thereafter, an audio signal...

20060084220 - Differentially nitrided gate dielectrics in cmos fabrication process: A semiconductor fabrication process includes forming a first plasma nitrided oxide (PNO) gate dielectric overlying a first region of a semiconductor substrate. A second PNO gate dielectric is formed overlying a second region of the substrate. The nitrogen concentration of the second PNO differs from the nitrogen concentration of the...

20060084221 - Semiconductor diode and method therefor: In one embodiment, a diode is formed with anodes on two surfaces of a semiconductor substrate....

20060084225 - Apparatus for forming dielectric structures in integrated circuits: In some embodiments, a multi-layer dielectric structure, such as a capacitor dielectric region, is formed by forming a first dielectric layer on a substrate according to a CVD process and forming a second dielectric layer directly on the first dielectric layer according to an ALD process. In further embodiments, a...

20060084223 - Method for fabricating a trench capacitor with an insulation collar and corresponding trench capacitor: The present invention provides a method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar selection transistor that is provided in the substrate...

20060084222 - Process for fabricating a semiconductor device having deep trench structures: A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the first portion of the trench, a protective layer...

20060084224 - Semiconductor device and method of fabricating the same: According to the present invention, there is provided a semiconductor devise comprising: a gate electrode formed via a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a source region and drain region formed in a surface portion of said semiconductor substrate on two sides of...

20060084226 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side...

20060084227 - Increasing adherence of dielectrics to phase change materials: A phase change material is formed over a dielectric material. An impurity is introduced into the dielectric to improve the adherence of said dielectric to said phase change material....

20060084228 - Low thermal resistance semiconductor device and method therefor: A semiconductor device is formed to have a shape that reduces the thermal resistance of the semiconductor device....

20060084230 - Application of different isolation schemes for logic and embedded memory: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth...

20060084229 - Post high voltage gate oxide pattern high-vacuum outgas surface treatment: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within...

20060084231 - Method of inhibiting degradation of gate oxide film: A method of inhibiting degradation of a transistor gate oxide film by high density plasma is disclosed. After a gate electrode is formed, impurity is implanted on the surface of an oxide film, thereby changing surface characteristics of the oxide film to scatter ultraviolet rays which are factors of degradation...

20060084232 - Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor: Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process...

20060084233 - Method for forming sti structures with controlled step height: STI structures with step height control are produced using a relatively thin nitrogen-containing layer formed over a substrate. The nitrogen-containing layer may consist of SiN and SiON films with a combined thickness of 900 angstroms or less. Trench openings are formed to extend through the nitrogen-containing layer and into the...

20060084234 - Method for producing a spacer structure: A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is...

20060084235 - Low rc product transistors in soi semiconductor process: A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches....

20060084236 - Plasma-enhanced chemical vapour deposition process for depositing silicon nitride or silicon oxynitride, process for producing one such layer arrangement, and layer arrangement: A plasma-enhanced chemical vapor deposition process for depositing relatively high dielectric constant silicon nitride or oxynitride to form an MIM capacitor is described. The flow rate ratios for the silicon nitride layer are: silane-to-ammonia between 1:20 and 6:5 and silane-to-nitrogen flow between 1:40 and 3:5. A pressure in the process...

20060084237 - Solid electrolytic capacitor and method of manufacturing the same: A solid electrolytic capacitor using a conductive polymer compound as a solid electrolyte includes an anode body, a dielectric oxide coating formed on a surface of the anode body, a first conductive polymer compound layer formed on a portion of the dielectric oxide coating, a silane coupling agent treatment layer...

20060084238 - Method for bonding wafers: A first wafer is provided, and a photosensitive masking-and-bonding pattern is formed on the surface of the first wafer. Then, an etching process using the photosensitive masking-and-bonding pattern as a hard mask is performed to form a wafer pattern on the surface of the first wafer. Finally, the first wafer...

20060084240 - Apparatus and method for packaging circuits: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each...

20060084241 - Apparatus for controlled fracture substrate singulation: An apparatus and a system for separating dice from a substrate are described herein....

20060084239 - Wafer dividing method: A method of dividing a wafer having a plurality of dividing lines formed in a lattice pattern on the front surface, into individual chips along the dividing lines, the method comprising: a deteriorated layer forming step for forming a deteriorated layer in the inside of the wafer by applying a...

20060084242 - Memory device and method of manufacturing including deuterated oxynitride charge trapping structure: A method for manufacturing a charge storage stack including a bottom dielectric layer, a charge trapping structure on the bottom dielectric layer, and a top dielectric layer, each comprising silicon oxynitride, are formed using reactant gases that comprise hydrogen, where the hydrogen comprises at least 90 percent deuterium isotope. The...

20060084243 - Oxidation sidewall image transfer patterning method: A method is presented for patterning a MOSFET gate which includes the steps of: forming a layer of gate material over a gate dielectric, depositing an amorphous Si layer over the gate material, depositing a nitride cap-layer on top of the amorphous Si layer, patterning the nitride cap-layer and the...

20060084245 - Semiconductor device, semiconductor device production method, and substrate for the semiconductor device: A semiconductor device production method includes the steps of: forming a linear gallium nitride stripe pattern on a major surface of a substrate, the major surface of the substrate being offset from a predetermined crystal plane by offset angles of 0.1 degree to 0.5 degrees respectively defined with respect to...

20060084244 - Silicon-on-insulator chip with multiple crystal orientations: A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the...

20060084246 - Manufacturing method for crystalline semiconductor material and manufacturing method for semiconductor device: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the...

20060084247 - Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation: A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116). The process (200) involves totally consuming (271) the doped precursor (124, 126N and/or 126P) thereby driving dopants (126N and/or 126P) from the doped precursor...

20060084248 - Methods of optimization of implant conditions to minimize channeling and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise implanting a first concentration of a species into an active area with a first energy, wherein the species pre-damages a portion of the active area, and then implanting a second concentration of the species into the active area with...

20060084249 - Method for manufacturing a hybrid semiconductor wafer having a buried oxide film: A method for manufacturing a hybrid semiconductor wafer having a BOX film, includes: depositing a first masking film on a silicon based substrate; depositing a second masking film on the first masking film; forming a window portion having a perpendicular sidewall by selectively removing a part of the second masking...

20060084250 - Methods of making microelectronic packages with conductive elastomeric posts: A method of making a microelectronic assembly includes providing a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface; providing a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface, forming a plurality of...

20060084252 - Method for fabricating a gold contact on a microswith: Described is a process to pattern adhesion and top contact layers in such a way that at least some portion of the top contact layers overlaps the adhesion layer, while another portion of the top contact layer overlaps with the bottom contacts, but does not overlap with the adhesion layer....

20060084254 - Method for making electronic packages: A process for fabricating an electronic package for a Thermally Enhanced BGA package including the steps of fabricating a thermally conductive support member, an adhesive bonding member, and a circuitized member; sandwiching the members together, forming a cavity therein; bonding adhesively the members together with heat and pressure; bonding adhesively...

20060084251 - Plating method, semiconductor device fabrication method and circuit board fabrication method: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 so that the ten-point height of irregularities of the surface of the resin layer 10 is 0.5-5 μm; the step of forming...

20060084253 - Plating method, semiconductor device fabrication method and circuit board fabrication method: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and...

20060084255 - Semiconductor device and method of manufacturing the same: A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including...

20060084256 - Method of forming low resistance and reliable via in inter-level dielectric interconnect: A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an...

20060084257 - Dye sensitization photoelectric converter and process for fabricating the same: In a dye-sensitized photoelectric transfer device having a semiconductor layer and an electrolyte layer between a transparent conductive substrate and a counter conductive substrate, the semiconductor layer is composed of titania nanotubes, and a sensitizing dye is retained by the titania nanotubes. The titania nanotubes preferably have an anatase-type crystalline...

20060084258 - Semiconductor device and method of manufacturing the same: Semiconductor device includes a pair of substrates (1, 2) disposed oppositely, semiconductor elements (5, 6) formed in the substrates (1, 2), respectively, and having semiconductor circuits (3, 4) and electrodes (7, 8), respectively, a wiring conductor (9) interposed between the electrodes (7, 8), and a through electrode (12) extending through...

20060084259 - Manufacturing method of passivation layer on wafer and manufacturing method of bumps on wafer: A manufacturing method of wafer passivation layer and manufacturing method of wafer bump. First, a wafer is provided with an active surface, which has a passivation layer and reveals a plurality of bonding pads on said passivation. Next, a redistribution layer is formed on the wafer and is electrically connected...

20060084260 - Copper processing using an ozone-solvent solution: The present invention relates to a method and apparatus for treating materials such as copper or copper based metal alloys, used in fabricating semiconductor devices with an ozone solvent solution and avoiding damage to metals by corrosion. The invention is also applicable to treating of materials such as copper and...

20060084261 - Interconnect layout method: An interconnect layout method capable of reducing variations in shape of gate patterns and improving yield of a semiconductor device is provided. In an interconnect layout 100, the first gate pattern, the second gate pattern, the first dummy pattern, and the second dummy pattern are arranged so that, if a...

20060084262 - Low-k dielectric process for multilevel interconnection using microcavity engineering during electric circuit manufacture: One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned masking layer such as silicon nitride on the silicon dioxide. Using the patterned nitride layer as a pattern, the silicon dioxide is etched to form...

20060084264 - Method for applying metal features onto metallized layers using electrochemical deposition and alloy treatment: The present invention is directed to a process for producing structures containing metallized features for use in microelectronic workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and metallized features according to...

20060084263 - Method of forming metal layer used in the fabrication of semiconductor device: A method of forming a metal layer on the conductive region of a semiconductor device includes concurrently supplying a mixture gas including a hydrogen gas and a metal chloride compound gas, and a purge gas into a chamber having a sealed space for a predetermined time, thereby forming a first...

20060084265 - Method for electrochemically fabricating three-dimensional structures including pseudo-rasterization of data: Some embodiments of the invention are directed to techniques for electrochemically fabricating multi-layer three-dimensional structures where selective patterning of at least one or more layers occurs via a mask which is formed using data representing cross-sections of the three-dimensional structure which has been modified to place it in a polygonal...

20060084266 - Film formation method: A film formation method of forming a film on a fine-pattern by supplying a processing medium that is in the supercritical state in which a precursor is dissolved on a target substrate is disclosed. The film formation method includes a first process of supplying the processing medium on the target...

20060084267 - Method for fabricating planar semiconductor wafers: The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is...

20060084269 - Apparatus for generating gas plasma, gas composition for generating plasma and method for manufacturing semiconductor device using the same: A method for manufacturing a semiconductor device may include: forming a main magnetic field having an axis, and forming a subsidiary magnetic field substantially parallel to the axis; applying an alternating current along a path between the main and the subsidiary magnetic fields; allowing a gas to flow along a...

20060084268 - Method for production of charge-trapping memory cells: An oxide layer, a nitride layer, and a layer of amorphous silicon are applied to a surface of a semiconductor substrate. A resist mask is applied and implantations are performed to form doped regions of source and drain and doped regions within the amorphous silicon layer. The resist mask and...

20060084270 - Composition for selectively polishing silicon nitride layer and polishing method employing it: To provide a polishing composition whereby the stock removal rate of a silicon nitride layer is higher than the stock removal rate of a silicon oxide layer, there is substantially no adverse effect against polishing planarization, and a sufficient stock removal rate of a silicon nitride layer is obtainable, and...

20060084272 - Polishing slurries for copper and associated materials: A chemical mechanical polishing slurry and method for using the slurry for polishing copper, barrier material and dielectric material that includes a first and second slurry. The first slurry has a high removal rate on copper and a low removal rate on barrier material. The second slurry has a high...

20060084271 - Systems, methods and slurries for chemical mechanical polishing: Process, slurries formulation and polishing mechanism are disclosed for the formation of silver (Ag) or Ag alloy film features on a substrate using CMP. The process and slurries can achieve Ag or Ag alloy film features with good planarization, low roughness, high reflectivity, and low defectivity....

20060084273 - Semiconductor device using damascene technique and manufacturing method therefor: A gate insulation film is formed on a semiconductor substrate, gate electrodes are formed on the gate insulation film, and source/drain diffusion layers are formed. A silicon nitride films is formed on a side wall of the gate electrodes, a silicon oxide film is formed on the overall surface, and...

20060084274 - Edge protection process for semiconductor device fabrication: An edge protection process for semiconductor device fabrication includes forming a protective layer on the circumferential edge region of a semiconductor substrate. The semiconductor substrate is placed in a plasma atmosphere and trench structures, such as deep trenches and shallow trench isolation structures are etched in the substrate. The protective...

20060084275 - Etch stop structure and method of manufacture, and semiconductor device and method of manufacture: An etch stop layer is formed over a first structure by depositing a metal oxide material over the first structure and annealing the deposited metal oxide material. A second structure is formed over the etch stop layer, and a formation is etched through the second structure using the etch stop...

20060084276 - Methods for surface treatment and structure formed therefrom: A method for patterning a resist protection oxide (RPO) layer and a structure formed therefrom are disclosed. The method forms a RPO layer over a substrate. A patterned photoresist layer is formed over the RPO layer. A process is performed for bombarding a surface of the RPO layer by using...

20060084277 - Method of forming amorphous silica-based coating film with low dielectric constant and thus obtained silica-based coating film: The present invention relates to an amorphous silica-based coating film with a low specific dielectric constant of 2.5 or below and the Young's modulus of 6.0 GPa or more and having excellent hydrophobic property, and to a method of forming the same. A liquid composition containing a silicon compound obtained...

20060084278 - Metal oxide-containing nanoparticles: The present invention provides a copper oxide-containing composition that includes copper oxide nanoparticles and one or more heteroatom donor ligands bonded to the surface of the nanoparticles, where x and y are numbers having a ratio that is equal to the ratio of the average number of M atoms to...

20060084279 - Method for forming a multi-layer low-k dual damascene: A damascene structure and method for forming the same in a multi-density dielectric insulating layer the method including providing a substrate; forming at least a first layer comprising silicon oxide according to a first process having a first density; forming at least a second layer comprising silicon oxide according to...

20060084280 - Method of forming a carbon polymer film using plasma cvd: A method of forming a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (CαHβXγ, wherein α and β are natural numbers of 5 or more; γ is an integer including zero; X is O,...

20060084281 - Novel deposition of high-k msion dielectric films: This disclosure discusses the forming of gate dielectrics in semi conductor devices, and more specifically to forming thin high-k dielectric films on silicon substrates typically using chemical vapor deposition or atomic layer deposition processes. The current invention forms a high-k dielectric film in a single film-forming step using a vapor...

20060084282 - Porous organosilicates with improved mechanical properties: Oxycarbosilane materials make excellent matrix materials for the formation of porous low-k materials using incorporated pore generators (porogens). The elastic modulus numbers measured for porous samples prepared in this fashion are 3-6 times higher than porous organosilicates prepared using the sacrificial porogen route. The oxycarbosilane materials are used to produce...

20060084283 - Low temperature sin deposition methods: A silicon nitride layer is deposited on a substrate within a processing region by introducing a silicon containing precursor into the processing region, exhausting gases in the processing region including the silicon containing precursor while uniformly, gradually reducing a pressure of the processing region, introducing a nitrogen containing precursor into...

20060079004 - Method for electrical doping a semiconductor material with cesium: The invention relates to a method for doping a semiconductor material with Cesium, wherein said semiconductor material is exposed to a cesium vapor. Said Cesium vapor is provided by Cesium sublimation from a Cesium alloy. There is also provided an organic light emitting diode comprising at least one layer of...

20060079006 - Method for forming polarization reversal: A method for forming a ferroelectric spontaneous polarization reversal in a desired region of a ferroelectric substrate 1 has a feature that said desired region 20 of a surface of said ferroelectric substrate is sprayed with micro-hard materials, made an impact by using a striking member that has micro tip...

20060079005 - Method for making a semiconductor device having a high-k gate dielectric: A method for making a semiconductor device is described. That method comprises converting a hydrophobic surface of a substrate into a hydrophilic surface, and forming a high-k gate dielectric layer on the hydrophilic surface....

20060079007 - System, method, and medium for an endpoint detection scheme for copper low-dielectric damascene structures for improved dielectric and copper loss: A system, method and medium of detecting a transition interface between a first dielectric material and an adjacent second dielectric material in a semiconductor wafer during a chemical-mechanical polishing process includes impinging an incident light of a predetermined wavelength on the semiconductor wafer at a first time, detecting at least...

20060079008 - Inspection method of bonded status of ball in wire bonding: An inspection method of a bonded status of a ball bonded to a pad of a semiconductor chip in wire bonding which attains wiring between the pad of the semiconductor chip and an external electrode is disclosed, wherein an image of a bonding portion between the pad and the ball...

20060079009 - Fine-pitch electronic socket for temporary or permanent attachments: An electronic socket is described for providing either or both temporary and permanent attachments of electronic components to a substrate having interconnection circuits. The socket includes wells filled with a conductive fluid or paste for temporary attachment to the mesas of an electronic circuit. The wells are connected to selected...

20060079011 - Methods for marking a bare semiconductor die: A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including back grinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having...

20060079010 - Transfer base substrate and method of semiconductor device: A transfer base substrate comprises: a substrate; a plurality of transfer thin film circuits formed on the substrate via removing layer; a test circuit formed on the substrate for checking circuit operation; and a wiring coupling each of transfer thin film circuits with a test circuit....

20060079012 - Method of manufacturing carbon nanotube field emission device: A carbon nanotube emitter and a method of manufacturing a carbon nanotube field emission device using the carbon nanotube emitter. Powdered carbon nanotubes are adsorbed onto a first substrate. A metal is deposited on the carbon nanotubes. The resultant structure is pressure-bonded to a surface of a cathode. The first...

20060079014 - Method of manufacturing an led: The present invention relates to a method of manufacturing an LED, comprising the steps of: first, forming a tape coppery metal strip; then, continuously pressing circuits on the tape coppery metal strip so as to form a carrier having circuit patterns of electric contacts on which the diode dies can...

20060079013 - Point source light-emitting diode and manufacturing method thereof: A point source light emitting-diode (LED) comprises a substrate, an epitaxy structure, a first electrode, an isolation layer, a bonding layer, a contact layer, and a connection bridge. The epitaxy structure is located on the substrate, and the substrate has a pattern including a light emitting area located on the...

20060079015 - Manufacturing method of pickup device: In a manufacturing method of a pickup device, a hologram element is positioned on a package by turning the hologram element around the Z axis and then by moving the element in the Y-axis direction so as to maximize the light reception intensity of reflected light from the hologram element...

20060079016 - Method of forming a seal between a housing and a diaphragm of a capacitance sensor: The axial distance between opposing conductors of a capacitance pressure transducer can depend, in part, upon the thickness of a seal that is disposed between a housing and a diaphragm of the capacitance pressure transducer. The present invention utilizes spacer elements and sealing beads to form a seal that is...

20060079017 - Method for manufacturing a microlens: A method for manufacturing a microlens formed on a semiconductor substrate includes the steps of preparing the semiconductor substrate, forming an insulating film, which has high etching selectivity with the semiconductor substrate, on the semiconductor substrate, forming a first resist layer, which has an opening that exposes a part of...

20060079018 - Method for producing an optical or electronic module provided with a plastic package: A method for producing an optical or electronic module provided with a plastic package in which at least one optical or electronic component having an operative region is encapsulated with at least one polymer compound to form the plastic package. Portions of the polymer compound are then removed by a...

20060079019 - Method for manufacturing wafer level chip scale package using redistribution substrate: The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substrate is produced separately from a wafer and then bonded to the wafer. One...

20060079020 - Semiconductor device and a method of assembling a semiconductor device: A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to...

20060079022 - Frame attaching process: A frame attaching process is described. The frame attaching process is adapted for attaching a transparent substrate to an active area of a chip using a frame, wherein the active area of the chip has a functional area. In the frame attaching process, the frame can be formed on the...

20060079021 - Method for flip chip package and structure thereof: A method for flip chip package and structure thereof is disclosed. The present invention is using an eutectic bonding process to connect a chip and a heatsink for enhancing thermal dissipation capability from the chip to the heatsink and ensuring the chip working well. The method for flip chip package...

20060079023 - Semiconductor device and manufacturing method for the same: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip,...

20060079024 - Methods relating to singulating semiconductor wafers and wafer scale assemblies: Methods relating to the singulation of dice from semiconductor wafers. Trenches or channels are formed in the bottom surface of a semiconductor wafer, corresponding in location to the wafer streets. The trenches may be formed by etching or through an initial laser cut. The wafer is then singulated along the...

20060079025 - Polymer encapsulated dicing lane (pedl) technology for cu/low/ultra-low k devices: A process for packaging semiconductor devices for flip chip and wire bond applications, wherein specific materials of the semiconductor devices are protected during device processing sequences and dicing procedures, has been developed. After definition of copper interconnect structures surrounded by a low k insulator layer, a protective, first photosensitive polymer...

20060079026 - Method of the film substrate, a method of the semiconductor device using the same, a method of the display device using the same, and a method of the electric device using the same: A method of manufacture is provided in which position deviations during mounting are eliminated, and in which fine connections on the order of a 30 μm pitch can be stabilized. A low cost device can thus be realized by cost reductions that accompany smaller ICs. Mounting is performed in a...

20060079027 - Semiconductor device and its manufacturing method: A manufacturing method of a thin and small-sized semiconductor device, which is integrated into an electronic instrument. A silicon wafer is prepared, and oxide films are formed on the main face and the rear face of the wafer. An insulating film is selectively formed on the main face of the...

20060079028 - Manufacturing method of a semiconductor device: The package size of a semiconductor device is brought close to chip size, and a miniaturization is aimed at. Including a semiconductor chip having a plurality of pads, a plurality of leads having a mounting surface and a wire connection surface, having a thick portion, and the thin portion whose...

20060079029 - Flexible circuit board processing method: It is an object of this invention to provide a flexible circuit board processing method which controls an outflow of a sealing material to be appropriate when packaging a component on a flexible circuit board. There is provided a flexible circuit board processing method for, when packaging a chip component...

20060079030 - Method of fabricating t-type gate: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking...

20060079033 - Method for making thin-film semiconductor device: A method for making a thin-film semiconductor device includes an annealing step of irradiating an amorphous semiconductor thin film with a laser beam so as to crystallize the amorphous semiconductor thin film. In the annealing step, the semiconductor thin film is continuously irradiated with the laser beam while shifting the...

20060079032 - Method of manufacturing thin film transistor: A method of manufacturing a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; forming a semiconductor layer on the gate insulating film; forming a bank including a first bank portion and a second bank portion, the first bank...

20060079031 - Semiconductor device and manufacturing method thereof: An insulating film layer is formed between a channel region of an MOS element formed in a monocrystal silicon layer of an SOS substrate in which the monocrystal silicon layer is laminated on a sapphire substrate, and the sapphire substrate, thereby to bring a stress state of the monocrystal silicon...

20060079034 - Method to form a passivation layer: Embodiments of methods, apparatuses, devices, and/or systems for forming a passivation layer are described....

20060079035 - Method of manufacturing thin film semiconductor device, thin film semiconductor device, electro-optical device, and electronic apparatus: A method of manufacturing a thin film semiconductor device which includes a thin film transistor having a first semiconductor layer, a gate insulating layer, and a gate electrode which are laminated in this order on a substrate, and a capacitive element having a lower electrode that conductively connects a second...

20060079038 - Method of fabricating an electronic device: A method of fabricating an electronic device includes the following steps: a) providing a substrate; b) forming a first strip on the substrate; c) coating an insulation layer on the first strip and the substrate while completely overlaying the first strip and the substrate with the same; d) forming a...

20060079036 - Method of manufacturing gate, thin film transistor and pixel: A method of manufacturing a gate, a thin film transistor and a pixel. First, a patterned mask layer is formed on a substrate. The mask layer exposes an area for forming the gate. A gate is formed on the exposed area of the substrate and then the mask layer is...

20060079037 - Thin-film transistor and methods: A thin-film transistor (TFT) is fabricated by providing a substrate, depositing and patterning a metal gate, anodizing the patterned metal gate to form a gate dielectric on the metal gate, depositing and patterning a channel layer comprising a multi-cation oxide over at least a portion of the gate dielectric, and...

20060079039 - Semiconductor device and manufacturing method thereof: An object of the invention is to form an insulating film having favorable insulation and planarity. An insulating film is formed by performing heat treatment a resin containing a siloxane polymer after application, in an atmosphere including an inert gas as its main component and having an oxygen concentration of...

20060079040 - Laser processing unit, laser processing method, and method for manufacturing semiconductor device: Objects of the present invention is to reduce a number of scanning a linear laser, to shorten the amount of time for laser annealing, and to reduce a manufacturing process, a manufacturing time, and manufacturing cost of a semiconductor device. In this invention, a gas at high temperature is locally...

20060079041 - Manufacturing method for a semiconductor device: Position control of a crystal grain in accordance with an arrangement of a TFT is achieved, and at the same time, a processing speed during a crystallization process is increased. More specifically, there is provided a manufacturing method for a semiconductor device, in which crystal having a large grain size...

20060079045 - Electrically erasable programmable read-only memory (eeprom) device and methods of fabricating the same: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation...

20060079044 - Method for fabricating electronic device: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the...

20060079043 - Method of manufacturing semiconductor integrated circuit device: A method of manufacturing a MOS transistor having sufficiently many Vth's is provided by selectively arranging a nitride film to overlap with the source and the gate electrode of the MOS transistor, and by varying an overlap amount of the nitride film with respect to the gate electrode in a...

20060079042 - Thin film transistor and manufacturing method thereof: A method for manufacturing a thin film transistor is provided. In the method, a gate electrode is formed on a substrate. A crystalline gate insulating layer is formed on an entire surface of the substrate having the gate electrode formed thereon. A microcrystalline silicon layer and a doped amorphous silicon...

20060079047 - Integration of multiple gate dielectrics by surface protection: A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate (203) having a sacrificial oxide layer (207) thereon; (b) depositing and patterning a first layer of photoresist (209) on the sacrificial oxide layer, thereby forming a first region in which the sacrificial...

20060079046 - Method and structure for improving cmos device reliability using combinations of insulating materials: A method for improving hot carrier effects in complementary metal oxide semiconductor (CMOS) devices includes forming a first configuration of insulating material over a first group of the CMOS devices, and forming a second configuration of insulating material over a second group of the CMOS devices. The first and said...

20060079048 - Method of making prestructure for mems systems: A method of making an interferometric modulator element includes forming at least two posts, such as posts formed from spin-on glass, on a substrate. In alternate embodiments, the posts may be formed after certain layers of the modulator element have been deposited on the substrate. An interferometric modulator element includes...

20060079049 - Method for fabricating a capacitor: In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is...

20060079050 - Capacitor structure: Structures including a capacitor dielectric material disposed on the surface of an electrode suitable for use in forming capacitors are disclosed. Methods of forming such structures are also disclosed....

20060079051 - Method for forming a multi-bit non-volatile memory device: Forming a non-volatile memory device includes providing a semiconductor substrate, forming a masking layer having a first plurality of openings overlying the semiconductor substrate, forming diffusion regions in the semiconductor substrate at locations determined by the masking layer, forming a dielectric within the first plurality of openings, removing the masking...

20060079052 - Semiconductor memory device and manufacturing method thereof: Disclosed is a semiconductor memory device including a plurality of diffusion regions, select gates, word lines, and common diffusion regions. The plurality of diffusion regions are extended in the surface of a substrate in a memory cell area, being spaced apart to one another in one direction, and constitute bit...

20060079053 - Nrom device and method of making same: A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments...

20060079054 - Non-volatile memory device and methods of forming the same: A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. A second insulation layer is interposed between the floating gate...

20060079055 - Method of forming a split programming virtual ground sonos memory: A method of forming an SPVG SONOS memory. First, a substrate having a well and a plurality of select gate structures is provided. Then, a plurality of sacrificial spacers are formed alongside each select gate structure, and an implantation process is performed to form a doped region in the well...

20060079056 - Semiconductor structures having a strained silicon layer on a silicon-germanium layer and related fabrication methods: A semiconductor structure including a SiGe layer and a method of fabricating the same are provided. The structure includes a silicon layer heavily doped with impurities. A SiGe layer is disposed on the silicon layer. A strained silicon layer is disposed on the SiGe layer. The impurities may be boron....

20060079057 - Field effect transistor and method of fabricating the same: Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of...

20060079058 - Method for inspecting semiconductor device: A wafer is irradiated with laser light having a wavelength which is transmitted through an inside of a crystal of the wafer and does not generate an electromotive force due to photo-excitation while the laser light is scanned. When a temperature of the wafer is increased by the irradiation, a...

20060079059 - Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric...

20060079060 - Semiconductor device having elevated source/drain and method of fabricating the same: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second...

20060079061 - Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in...

20060079062 - Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate: The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a...

20060079063 - Semiconductor device and method for manufacturing the same: A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, which has a STI structure, the method comprises; first—ion implanting fist ions onto...

20060079064 - Fabrication method for a trench capacitor having an insulation collar which on one side is electrically connected to a substrate via a buried contact, in particular for a semiconductor memory cell, and corresponding trench capacitor: The present invention provides a fabrication method for a trench capacitor having an insulation collar (10; 10a, 10b) in a substrate (1), which on one side is electrically connected to the substrate (1) via a buried contact (15a, 15b), comprising the steps of: providing a trench (5) in the substrate...

20060079065 - Capacitor having reaction preventing layer and methods of forming the same: The present invention is directed to a capacitor having a reaction preventing layer and a method forming the same. A lower electrode of silicon is formed on a substrate. An assistance layer of metal oxide or metal nitride is formed on the lower electrode. A nitridation process is performed to...

20060079066 - Semiconductor device and method for fabricating the same: A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the...

20060079067 - Methods for aligning patterns on a substrate based on optical properties of a mask layer and related devices: A method of fabricating a semiconductor device includes forming a material layer on a substrate, forming a mask layer on the material layer, and implanting ions into the mask layer to reduce light absorption thereof. An alignment key may be formed between the material layer and the substrate, and a...

20060079068 - Narrow width effect improvement with photoresist plug process and sti corner ion implantation: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the...

20060079069 - Silicon wafer laser processing method and laser beam processing machine: A silicon wafer laser processing method for forming a deteriorated layer along dividing lines formed on a silicon wafer in the inside of the silicon wafer by applying a laser beam along the dividing lines, wherein the wavelength of the laser beam is set to 1,100 to 2,000 nm....

20060079070 - Substrate for stressed systems and method of making same: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer....

20060079071 - Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b)...

20060079072 - Method for precision integrated circuit die singulation using differential etch rates: A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material A second anisotropic etch process is...

20060079073 - Fabrication method of nitride semiconductors and nitride semiconductor structure fabricated thereby: Disclosed is a method of fabricating nitride semiconductors in a MOCVD reactor. GaN is first deposited on an inner wall of the MOCVD reactor, and a sapphire substrate is loaded into the MOCVD reactor. The sapphire substrate is heated and etching gas is injected into the MOCVD reactor. NH3 gas...

20060079074 - Method of forming relatively continuous silicide layers for semiconductor devices: Methods of forming metal suicide layers in a semiconductor device are provided in which a first metal silicide layer may be formed on a substrate, where the first metal silicide layer comprises a plurality of fragments of a metal silicide that are separated by one or more gaps. A conductive...

20060079075 - Gate structures with silicide sidewall barriers and methods of manufacturing the same: A gate structure includes a gate insulation layer on a substrate, a polysilicon layer pattern on the gate insulation layer, a composite metal layer pattern on the polysilicon layer pattern, and a metal silicide layer pattern on a sidewall of the composite metal layer pattern....

20060079076 - Methods of forming field effect transistors having t-shaped gate electrodes using carbon-based etching masks: Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using...

20060079077 - Semiconductor device manufacturing method: A manufacturing method for semiconductor devices having MOSFET gate insulation films. The method includes forming a silicon oxide film, forming a silicon nitride film, nitriding the silicon nitride film, and heat treatment....

20060079078 - Method of producing a semiconductor device having an oxide film: A semiconductor device having excellent characteristics is provided without deteriorated film quality. A first oxide film is divided into three regions A, B and C. Lengths I, II and III of the regions A, B and C in a plane direction of the silicon substrate are set equal to each...

20060079081 - Method for fabricating electrical connection structure of circuit board: A method for fabricating an electrical connection structure of a circuit board is proposed. A patterned resist layer is formed on the circuit board having a plurality of conductive pads, and a plurality of openings is formed in the resist layer to expose the conductive pads. A first conductive material...

20060079079 - Method of manufacturing of thin based substrate: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die....

20060079080 - Method of providing contact via to a surface: A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an...

20060079082 - Trench cut light emitting diodes and methods of fabricating same: A method is provided for forming semiconductor devices using a semiconductor substrate having first and second opposed sides, and at least one device layer on the second side of the substrate, the at least one device layer including first and second device portions. A first trench is formed in the...

20060079085 - Method for applying metal features onto metallized layers using electrochemical deposition: The present invention is directed to a process for producing structures containing metallized features for use in microelectronic workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and metallized features according to...

20060079084 - Method for applying metal features onto metallized layers using electrochemical deposition and electrolytic treatment: The present invention is directed to a process for producing structures containing metallized features for use in microelectronic workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and metallized features according to...

20060079083 - Method for applying metal features onto metallized layers using electrochemical deposition using acid treatment: The present invention is directed to a process for producing structures containing metallized features for use in microelectronic workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and metallized features according to...

20060079086 - Apparatus and method of forming silicide in a localized manner: Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor...

20060079087 - Method of producing semiconductor device: A method of producing a semiconductor device is disclosed that is able to reduce fluctuations of a sheet resistance of a silicide layer in the semiconductor device formed by a salicide process. When depositing a titanium nitride film on a cobalt film in the salicide process, the thickness of the...

20060079088 - Methods of forming a contact opening in a semiconductor assembly using a disposable hard mask: Methods to form contact openings and allow the formation of self-aligned contacts for use in the manufacture of semiconductor devices are described. During formation of a multi-layered resist, a hard mask material is introduced beneath an anti-reflective coating to be used as an etch stop layer. The multi-layered resist is...

20060079089 - Coated semiconductor wafer, and process and apparatus for producing the semiconductor wafer: A susceptor configured to receive a semiconductor wafer for deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD) has a gas-permeable structure with a porosity of at least 15%, a density of from 0.5 to 1.5 g/cm3, a pore diameter of less...

20060079090 - Method for depositing nanolaminate thin films on sensitive surfaces: The present method provides tools for growing conformal metal nitride, metal carbide and metal thin films, and nanolaminate structures incorporating these films, from aggressive chemicals. The amount of corrosive chemical compounds, such as hydrogen halides, is reduced during the deposition of transition metal, transition metal carbide and transition metal nitride...

20060079091 - Mask, method of producing the same, and method of producing semiconductor device: To provide a mask able to reduce the thickness of a membrane and maintain the mask strength and a method of producing a semiconductor device able to form a fine pattern with a high accuracy and a method of producing the mask. A mask comprising a thin film, holes formed...

20060079092 - Polishing method: The present invention is relates to a polishing method for polishing a semiconductor wafer (W) by pressing the semiconductor wafer (W) against a polishing surface (10) with use of a top ring (23) for holding the semiconductor wafer (W). A pressure chamber (70) is defined in the top ring (23)...

20060079093 - Method for fabricating semiconductor device using tungsten as sacrificial hard mask: The present invention relates to a method for fabricating a semiconductor device using tungsten as a sacrificial hard mask material. The method includes the steps of: forming a layer on an etch target layer; forming a photoresist pattern on the layer; etching the layer by using the photoresist pattern as...

20060079094 - Method for microstructuring flat glass substrates: In the method for microstructuring flat glass substrates a substrate surface of a glass substrate is coated with at least one structured mask layer and subsequently exposed to a chemically reactive ion etching process (RIE) with at least one chemical etching gas. In order to provide the same or a...

20060079095 - Method of removing a polymer coating from an etched trench: A method of removing a polymeric coating from sidewalls of an etched trench defined in a silicon wafer is provided. The method comprises etching the wafer in a biased plasma etching chamber using an O2 plasma. The chamber temperature is in the range of 90 to 180° C....

20060079096 - Substrate processing method and substrate processing apparatus: A substrate processing method for removing a resist film from a substrate having the resist film formed thereon comprises maintaining the inner region of the chamber at a prescribed temperature by putting a substrate in a chamber, denaturing the resist film by supplying ozone and a water vapor in such...

20060079098 - Method and system for sealing a substrate: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate a...

20060079097 - Method of forming dielectric layer in semiconductor device: A method of forming an insulating film of a semiconductor device is disclosed. Where an insulating film is formed and an annealing process is then performed to remove out-gassing sources contained in the insulating film. Spot-shaped defects and by-products or CH-radicals, which are formed on the surface of the insulating...

20060079099 - Ultra low k plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a sicoh matrix functionality and organic porogen functionality: A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having...

20060079100 - High density plasma grown silicon nitride: A method is provided for forming a silicon nitride (SiNx) film. The method comprises: providing a Si substrate or Si film layer; optionally maintaining a substrate temperature of about 400 degrees C., or less; performing a high-density (HD) nitrogen plasma process where a top electrode is connected to an inductively...

20060073616 - Ferroelectric capacitor and its manufacturing method, and ferroelectric memory device: A method for manufacturing a ferroelectric capacitor includes successively disposing a lower electrode, at least one intermediate electrode and an upper electrode over a base substrate, and providing ferroelectric films between the electrodes, respectively. In the step of forming the intermediate electrode, (a) a first metal film is formed by...

20060073614 - Ferroelectric capacitor structure and manufacturing method thereof: The present invention provides a ferroelectric capacitor structure comprising a ferroelectric capacitor which is constituted in such a manner that a lower electrode is formed, a ferroelectric film is formed on the lower electrode and an upper electrode is formed on the ferroelectric film, and which is formed in a...

20060073613 - Ferroelectric memory cells and methods for fabricating ferroelectric memory cells and ferroelectric capacitors thereof: Methods (100) are provided for fabricating a ferroelectric capacitor in a semiconductor device wafer, comprising forming (118) a lower electrode, depositing (126) PZT ferroelectric material on the lower electrode at a temperature below 450 degrees C., and forming (128) an upper electrode on the PZT. Methods are also provided for...

20060073615 - Method of manufacturing capacitor in semiconductor device: Provided is a method of manufacturing a capacitor in a semiconductor device, comprising the steps of: forming a first metal film of noble series for the bottom electrode; forming a ferroelectric film on the first metal film; conducting a first thermal process on the resultant structure where the ferroelectric film...

20060073618 - Method of fabricating thin film calibration features for electron/ion beam image based metrology: A method of making and using thin film calibration features is described. To fabricate a calibration standard according to the invention raised features are first formed from an electrically conductive material with a selected atomic number. A conformal thin film layer is deposited over the exposed sidewalls of the raised...

20060073617 - Surface coordinate system: A method for creating a reference for a first position on a substrate edge. A first reference point is selected relative to a circumference of the substrate edge, and a second reference point is selected relative to a bevel of the substrate edge. A first distance along the circumference of...

20060073619 - Semiconductor fabricating apparatus and method and apparatus for determining state of semiconductor fabricating process: In a semiconductor device fabrication apparatus for performing an etching process for a semiconductor wafer having a plurality of films formed on a surface thereof and disposed in a chamber, by using plasma generated in the chamber, a change in light of multi-wavelength from the surface of the semiconductor wafer...

20060073620 - Methods and structures for critical dimension and profile measurement: Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD)...

20060073621 - Group iii-nitride based hemt device with insulating gan/algan buffer layer: Various exemplary embodiments of the devices and methods for this invention provide for a semiconductor structure and a method of manufacturing a semiconductor structure that includes providing an aluminum nitride nucleation layer over a substrate, providing an undoped AlGaN buffer layer over the aluminum nitride nucleation layer, providing an undoped...

20060073622 - Digital light valve semiconductor processing: A system and method are provided for crystallizing a semiconductor film using a digital light valve. The method comprises: enabling pixel elements from an array of selectable pixel elements; in response to enabling the pixel elements, gating a light; sequentially exposing adjacent areas of a semiconductor film, such as Si,...

20060073623 - Methods of forming a microlens array over a substrate employing a cmp stop: A method of forming a microlens structure is provided along with a CCD array structure employing a microlens array. An embodiment of the method comprises providing a substrate having a surface with photo-elements on the surface; depositing a transparent material overlying the surface of the substrate; depositing a CMP stop...

20060073624 - Die-attach films for chip-scale packaging, packages made therewith, and methods of assembling same: A die-attach composition includes a resin such as a thermosetting resin, a hardener, and a low molecular weight oligomer diluent. A die-attach composition includes a polyimide in a major amount and a resin such as a thermosetting resin in a minor amount. The die-attach composition also includes a reactive polymer...

20060073625 - Method for manufacturing semiconductor light emitting device: A method for manufacturing a semiconductor light emitting device can result in a device that includes a housing having a cavity, a light emitting element on a bottom face of the cavity, and a wavelength conversion layer provided within the cavity. The wavelength conversion layer can include particles of a...

20060073626 - Method for producing optical element, optical element, and optical element array: A method for manufacturing an optical element comprises a step of press molding an optical element material 6 disposed between an upper press head (7) and its paired lower press head (8), wherein in the upper press head (7) and/or the lower press head (8) is formed a groove-like component...

20060073627 - Probe for a scanning probe microscope and method for fabricating same: A method for fabricating a probe for a scanning probe microscope, wherein the probe includes a mounting block, a cantilever and a tip, includes the steps of: forming a first mask to define a pattern for the tip and a second mask to define a pattern for the cantilever on...

20060073628 - Solid-state imaging device and method of manufacturing the same: The invention reduces dark current of a solid-state imaging device. A solid-state imaging device containing photodiode comprises: a diffusion layer placed side by side with the photodiode on the surface of an N-type semiconductor substrate; a first polycrystalline silicon electrode provided on the diffusion layer; a first Al interconnect provided...

20060073629 - Light guide for image sensor: A new method to form an image sensor device is achieved. The method comprises forming an image sensing array in a substrate comprising a plurality of light detecting diodes with spaces between the diodes. A first dielectric layer is formed overlying the diodes but not the spaces. The first dielectric...

20060073630 - Image sensor packaging method and structure thereof: A method for packaging an image sensor includes the steps of providing a substrate, forming a first adhesive on one surface of the substrate, attaching a transparent material on the first adhesive, cutting or carving the surface of the transparent material to a depth penetrating the transparent material while not...

20060073631 - Phase change memory with damascene memory element: A phase change material may be formed within a trench in a first layer to form a damascene memory element and in an overlying layer to form a threshold device. Below the first layer may be a wall heater. The wall heater that heats the overlying phase change material may...

20060073632 - Die handling system: A system may include singulation of a semiconductor wafer to separate a plurality of integrated circuit die that are integrated into the semiconductor wafer; coupling of a support to an integrated circuit substrate of one of the plurality of integrated circuit die, and decoupling of the one integrated circuit die...

20060073633 - Protective interleaf for stacked wafer shipping: A package includes a first and a second wafer stored therein in a stacked configuration. The first wafer has interconnection conductor material portions extending from a first surface thereof. The interconnection conductor material portions have a maximum height. An interleaf member is located between the first and second wafers. A...

20060073634 - Mechanism and process for compressing chips: A chip compressing mechanism is provided. The chip compressing mechanism essentially comprises a loading component, a head component and a gimbal. The head component is disposed under the loading component, with a gap in-between. The gimbal is disposed between the loading component and the head component to support the gap...

20060073636 - Fabrication of stacked die and structures formed thereby: Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, wherein forming the bond between the non-device side of the first die and the non-device side of the second die...

20060073637 - Method for manufacturing semiconductor device and semiconductor device: A semiconductor device includes: a connecting body including a connecting electrode; and at least one semiconductor chip stacked on the connecting body, the semiconductor chip including: a substrate; and a trans-substrate conductive plug that penetrates the substrate, the trans-substrate conductive plug having a first terminal that is provided on an...

20060073635 - Three dimensional package type stacking for thinner package application: A stacked semiconductor device, and method of making, having a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a first substrate. Solder balls are connected to contacts on the upper surface of the first substrate and a non-conductive layer is...

20060073638 - Semiconductor electrical connection structure and method of fabricating the same: A semiconductor electrical connection structure and a method of fabricating the same are provided. A wafer formed with a plurality of gold bumps thereon is divided into a plurality of individual chips. A carrier is prepared, and at least one of the chips is mounted on the carrier via a...

20060073639 - Electronic parts packaging structure and method of manufacturing the same: There is provided a electronic parts packaging structure that includes a mounted body on which an electronic parts is mounted, the electronic parts having a connection pad, which has an etching stopper film (a copper film, a gold film, a silver film, or a conductive past film) as an uppermost...

20060073640 - Diamond substrate formation for electronic assemblies: Electronic assemblies and methods for forming assemblies including a diamond substrate are described. One embodiment includes providing a diamond support and forming a porous layer of SiO2 on the diamond support. A diamond layer is formed by chemical vapor deposition on the porous layer so that the porous layer is...

20060073641 - Techniques for manufacturing a circuit board with an improved layout for decoupling capacitors: A circuit board module has an IC device, discrete components, and a circuit board structure in electrical communication with the IC device and the discrete component. The circuit board structure includes non-conductive material defining a top surface of the circuit board structure and a bottom surface of the circuit board...

20060073642 - Method for manufacturing a multiple-bit-per-cell memory: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer...

20060073643 - Transistor with doped gate dielectric: A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process or during subsequent anneal processes used to manufacture the transistor, dopant species from the doped region of the workpiece are outdiffused into the gate dielectric, creating a...

20060073644 - Method of manufacturing bonded substrate stack: A method of manufacturing a bonded substrate stack includes a bonding surface processing step of processing at least one of first and second substrates each containing silicon and having a bonding surface, and a bonding step of bonding the bonding surface of the first substrate and the bonding surface of...

20060073645 - Manufacturing method of a thin film transistor array panel: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe, forming a data line including a...

20060073646 - Hybrid orientation cmos with partial insulation process: The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of the devices is improved in the present invention by forming the source/drain...

20060073647 - Semiconductor device and manufacturing method thereof: A semiconductor device comprising a multi Fin-FET structure capable of suppressing short channel effects, controlling a threshold voltage, driving a high current, and operating in a high-speed comprises a source region and a drain region disposed on a semiconductor substrate, a plurality of fins interconnecting the source region and drain...

20060073648 - Thin film transistor and method of fabricating the same: Provided are a thin film transistor and method of fabricating the same, in which an amorphous silicon layer is formed on a substrate, a capping layer containing a metal catalyst having a different concentration according to its thickness is formed on the amorphous silicon layer, the capping layer is patterned...

20060073649 - Method for reduced n+ diffusion in strained si on sige substrate: Method for manufacturing a semiconductor device. The method includes forming source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Reducing vacancy concentration in the source and drain extension regions to decrease diffusion of the N...

20060073651 - Method for manufacturing electronic circuits integrated on a semiconductor substrate: A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary...

20060073650 - Method to selectively strain nmos devices using a cap poly layer: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply tensile strain to channel regions of devices while mitigating masking operations employed. A cap poly layer is formed over NMOS and PMOS regions of a semiconductor device. Then, a resist mask is employed to remove a...

20060073653 - Methods of fabricating flash memory devices with floating gates that have reduced seams: Methods of fabricating a floating gate of a flash memory cell are provided in which a first polysilicon layer is formed between first and second isolation layers. An upper region of the first polysilicon layer is then oxidized. The oxidized upper region of the first polysilicon layer is subsequently removed....

20060073652 - Phase change memory with ovonic threshold switch: A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in...

20060073654 - Maintenance system, substrate processing device, remote operation device, and communication method: An object of the present invention is to maintain a coating and developing system by remotely operating it more safely. The present invention is a maintenance system of a substrate processing apparatus, including a remote operation unit for operating the substrate processing apparatus from a remote place by transmitting a...

20060073655 - Phase change memory with a select device having a breakdown layer: A select device may have its threshold current reduced relative to the threshold current of a phase change memory element by providing within the select device a breakdown layer. Because the breakdown layer forms a breakdown filament along its length, the relative area between layers may be reduced, reducing the...

20060073656 - Method and system for improved nickel silicide: According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the...

20060073657 - Junction diode comprising varying semiconductor compositions: The invention provides for a junction diode including a heavily doped first region having a first conductivity type, a second lightly doped or intrinsic region having a second conductivity type, and a third heavily doped region having a second conductivity type. The junction diode comprises more than one semiconductor or...

20060073658 - Method for making a ferroelectric memory cell in a ferroelectric memory device, and a ferroelectric memory device: In a method for making ferroelectric memory cells in a ferroelectric memory device a first electrode comprising at least one metal layer and optionally at least one metal oxide layer is formed on a silicon substrate which has an optional insulating layer of silicon dioxide. A ferroelectric layer consisting of...

20060073659 - Method for fabricating a storage capacitor: The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode....

20060073660 - Method of manufacturing flash memory device: A method of manufacturing a flash memory device, including the steps of forming a floating gate electrode that is a doped polysilicon film on a semiconductor substrate, forming a polysilicon layer in the pattern of HSG on the doped polysilicon film, conducting a nitrifying process after forming the HSG polysilicon...

20060073661 - Method for forming wall oxide layer and isolation layer in flash memory device: Disclosed herein are methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam Generation) oxidization process is performed to form wall oxide films on sidewalls of the trenches. This process prohibits formation of...

20060073662 - Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method: A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is...

20060073663 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a semiconductor region containing silicon and an insulator region on a major surface of a semiconductor substrate containing silicon as a main component; depositing a semiconductor film containing silicon as a main component on the semiconductor region and the insulator region;...

20060073664 - Semiconductor device and manufacturing method of the same: Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted...

20060073666 - Non-volatile memory device with conductive sidewall spacer and method for fabricating the same: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed...

20060073665 - Source/drain extensions having highly activated and extremely abrupt junctions: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed....

20060073667 - Stabilized silver nanoparticles and their use: A process comprising: reacting a silver compound with a reducing agent comprising a hydrazine compound in the presence of a thermally removable stabilizer in a reaction mixture comprising the silver compound, the reducing agent, the stabilizer, and an optional solvent, to form a plurality of silver-containing nanoparticles with molecules of...

20060073668 - Production method for electric double-layer capacitor: A method of manufacturing electric double layer capacitors is disclosed. The method assumes a model in which solute is dissolved in solvent before preparing electrolyte, and estimates a withstanding voltage through a simulation. The electrolyte, of which withstanding voltage is expected to exceed a target value, is selectively prepared. The...

20060073669 - Method of manufacturing a semiconductor device: In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole...

20060073670 - Method of manufacturing a semiconductor device: In one embodiment, first and second multi-layer pattern structures are formed over first and second regions of a substrate, respectively. The first and second multi-layer pattern structures include first and second support layer patterns, respectively. The first and second multi-layer pattern structures define first and second openings, respectively. The first...

20060073671 - Method of producing element separation structure: A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an element separation structure forming region;...

20060073672 - Integrated bicmos semiconductor circuit: An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which...

20060073673 - Ammonium hydroxide treatments for semiconductor substrates: Embodiments of the current invention describe ammonia hydroxide treatments for surfaces. In one embodiment, a method and a cleaning solution including ammonium hydroxide (NH4OH), water (H2O), a chelating agent, and a surfactant for cleaning silicon germanium substrates are described. The cleaning solution does not include hydrogen peroxide (H2O2) because hydrogen...

20060073675 - Semiconductor device and method of manufacturing thereof: A method of manufacturing a semiconductor device, comprises; fixing a plurality of semiconductor substrates to a surface of a wiring substrate in which a perforated line, a grooved portion or grooved portion like the a perforated line is formed in advance; splitting the wiring substrate into a plurality of pieces...

20060073674 - Strained gettering layers for semiconductor processes: A method and structure for forming semiconductor structures using tensilely strained gettering layers. The method includes forming a donor wafer comprising a tensilely strained gettering layer disposed over a substrate, and at least one material layer disposed over the tensilely strained gettering layer. Additionally, the donor wafer may possess a...

20060073676 - Pre-process before cutting a wafer and method of cutting a wafer: A pre-process before cutting a wafer is described. The wafer comprises a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the...

20060073677 - Wafer dividing method and dividing apparatus: A method of dividing a wafer whose strength is reduced along a plurality of dividing lines formed in a lattice pattern on the front surface, along the dividing lines, comprising the steps of: a tape affixing step for affixing a protective tape to one side of the wafer; a wafer...

20060073678 - System and method for hydrogen exfoliation gettering: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting...

20060073679 - Cvd doped structures: A new clean CVD growing process of dopant doped silicon layers comprising epitaxial silicon or polycrystalline silicon, has been developed. The process is occurring advantageously at a high growing temperature of 600-1250° C., having a phase in which silicon comprised halide is used as a silicon source gas with a...

20060073680 - Epitaxial growth of aligned algainn nanowires by metal-organic chemical vapor deposition: Highly ordered and aligned epitaxy of III-Nitride nanowires is demonstrated in this work. <1010> M-axis is identified as a preferential nanowire growth direction through a detailed study of GaN/AlN trunk/branch nanostructures by transmission electron microscopy. Crystallographic selectivity can be used to achieve spatial and orientational control of nanowire growth. Vertically...

20060073681 - Nanoheteroepitaxy of ge on si as a foundation for group iii-v and ii-vi integration: A method of forming a virtually defect free lattice mismatched nanoheteroepitaxial layer is disclosed. The method includes forming an interface layer on a portion of a substrate. The interface layer can be, for example, SiO2, Si3N4, Al2O3, or W. A template can then be made by forming a plurality of...

20060073682 - Low-k dielectric material based upon carbon nanotubes and methods of forming such low-k dielectric materials: A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic...

20060073683 - Plasma immersion ion implantation process using a capacitively coupled plasma source having low dissociation and low minimum plasma voltage: A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking voltage to the electrostatic chuck. The...

20060073684 - Method for fabricating a doped zone in a semiconductor body: One embodiment of the invention relates to a method for fabricating a doped semiconductor zone in a semiconductor body. The method includes implanting dopant particles via one side into the semiconductor body or applying a layer containing dopant particles to one side of the semiconductor body. The method also includes...

20060073685 - Method for implanting dopants within a substrate by tilting the substrate relative to the implant source: The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate (310) located on or over an implant platen (305) about an axis in a first direction...

20060073686 - Method and system for reducing the impact of across-wafer variations on critical dimension measurements: First and second exposures of a mask onto a wafer are performed such that the exposure field of the second exposure partially overlaps the exposure field of the first exposure. A characteristic of a set of features is determined, and a value of a parameter of an optical proximity correction...

20060073687 - Method for maskless fabrication of self-aligned structures comprising a metal oxide: The present invention describes a method for fabricating micro-devices comprising aluminumoxide structures without the need for an extra lithographical processing step. So, no extra mask is needed. It appears that under certain circumstances, aluminumoxide walls arise in the etching process, just above sloped walls of underlying metal structures. The fact...

20060073688 - Gate stacks: A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in...

20060073689 - Method for fabricating doped polysilicon lines: A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about...

20060073690 - Apparatus and method for metal plasma vapor deposition and re-sputter with source and bias power frequencies applied through the workpiece: Physical vapor deposition and re-sputtering of a barrier layer in an integrated circuit is performed by providing a metal target near a ceiling of the chamber and a wafer support pedestal facing the target near a floor of the chamber. A process gas is introduced into said vacuum chamber. A...

20060073691 - Methods of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device including a capacitor, a first mold layer is formed on a semiconductor substrate. The first mold layer is partially etched to form a first mold layer pattern including an opening for a capacitor. A first lower electrode layer is formed on the...

20060073692 - Method for forming an electrode: In a semiconductor light-emitting device 100, a buffer layer 102, a undoped GaN layer 103, a high carrier concentration n+-layer 104, an n-type layer 105, an emission layer 106, a p-type layer 107, and a p-type contact layer 108 are deposited in sequence on a sapphire substrate. The semiconductor light-emitting...

20060073693 - Redistribution layer of wafer and the fabricating method thereof: A wafer comprises a wafer, a conductor, a first passivation layer, a second passivation layer, a redistribution layer, and a third passivation layer. The conductor is disposed on the wafer. The first passivation layer covers the wafer, and exposes the surface of the conductor. The second passivation layer having an...

20060073694 - Method for isolating semiconductor device structures and structures thereof: An array of continuous diffusion regions and continuous gate electrode structures is formed over a semiconductor substrate. Interconnecting diffusion region portions and interconnecting gate electrode portions are removed to electrically isolate transistor circuitry. The removal of interconnecting diffusion region portions and gate electrode portions can be performed sequentially, at substantially...

20060073695 - Gas dielectric structure forming methods: Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the...

20060073696 - Semiconductor device and manufacturing method thereof: A result of formation of an opening in a semiconductor substrate can be judged without cutting a semiconductor wafer and observing a cross-section of the cut wafer. A semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, an opening formed in the...

20060073697 - Method for improving low-k dielectrics by supercritical fluid treatments: A method for treating an inter-metal dielectric (IMD) layer to improve a mechanical strength and/or repair plasma etching damage including providing a low-K silicon oxide containing dielectric insulating layer; and carrying out a super critical fluid treatment of the low-K dielectric insulating layer including supercritical CO2 and a solvent including...

20060073698 - Plasma enhanced nitride layer: An etch stop layer located over a plasma enhanced nitride (PEN) layer. Interlayer dielectric material is then formed over the etched stop layer. The etch stop layer is used as an etch stop for etching openings in the interlayer dielectric. In some embodiments, integrated circuits built with the PEN layer...

20060073699 - Method for fabricating semiconductor device: Disclosed is a method for fabricating a semiconductor device. The method includes the steps of: forming a plurality of conductive patterns on a substrate; depositing an insulation layer on the substrate; recessing the insulation layer until a vertical height of the insulation layer becomes lower than that of the plurality...

20060073700 - Method for forming a barrier layer in an integrated circuit in a plasma with source and bias power frequencies applied through the workpiece: A barrier layer is formed in an integrated circuit by providing a metal target near a ceiling of the chamber and a wafer support pedestal facing the target near a floor of the chamber. A process gas is introduced into the vacuum chamber. A target-sputtering plasma is maintained at the...

20060073701 - Method of manufacturing a substrate with through electrodes: A method of manufacturing a substrate with through electrodes of the present invention, includes the steps of forming a metal post over a temporal substrate in a state that the metal post is peelable from the temporal substrate, placing a normal substrate in which a through hole is provided in...

20060073702 - Memory structure and manufacturing as well as programming method thereof: A memory structure includes a floating gate and a nitride gate dielectric on a semiconductor substrate, wherein the floating gate and nitride gate dielectric function as two memory cells. In addition to the floating gate and nitride gate dielectric, the memory structure further comprises two bitlines and a select gate....

20060073703 - Dynamic edge bead removal: A method of removing an edge bead of a coated material on a substrate. The substrate is rotated, and a fluid that solvates the coated material is delivered. The delivery of the fluid is directed radially inward on the substrate at a rate of between about three millimeters per second...

20060073705 - Method for dividing semiconductor wafer along streets: A method for dividing a semiconductor wafer along a plurality of streets, the semiconductor wafer having a face on which a plurality of rectangular regions are defined by the streets arranged in a lattice pattern, and a semiconductor device is formed in each of the rectangular regions. This method comprises...

20060073704 - Method of forming bump that may reduce possibility of losing contact pad material: A method of forming a bump may involve providing a seed layer on a contact pad of a wafer. A shielding layer and a photosensitive mask layer may be formed on the seed layer. The photosensitive mask layer may be exposed and developed to form a mask pattern. An exposed...

20060073706 - Selective etching processes of silicon nitride and indium oxide thin films for feram device applications: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in...

20060073707 - Low 1c screw dislocation 3 inch silicon carbide wafer: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density of less than about 2000 cm−2....

20060073708 - Strained silicon on insulator from film transfer and relaxation by hydrogen implantation: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention...