Semiconductor device manufacturing: process inventions 03/06

20060068508 - Method for operating an mfis ferroelectric memory array: An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels...

20060068507 - Methods of forming a material film, methods of forming a capacitor, and methods of forming a semiconductor memory device using the same: A method of forming a material (e.g., ferroelectric) film, a method of manufacturing a capacitor, and a method of forming a semiconductor memory device using the method of forming the (e.g., ferroelectric) film are provided. Pursuant to an example embodiment of the present invention, a method of forming a ferroelectric...

20060068509 - Mfis ferroelectric memory array: An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels...

20060068510 - Layer system with a silicon layer and a passivation layer, method for production of a passivation layer on a silicon layer and use thereof: A layer system and a method for producing the layer system are provided, the layer system having a silicon layer, on which at least regionally a passivating layer is superficially deposited, the passivating layer having a first, at least largely inorganic partial layer and a second, at least largely polymer...

20060068511 - Cmp process metrology test structures: A method for forming metrology structures for a CMP process is described. A trench edge is formed in a base material or stack of materials which are preferably deposited as part of the process of fabricating the production structures on the wafer. A covering film of a second material with...

20060068513 - Film forming condition determination method, film forming method, and film structure manufacturing method: Among a plurality of parameters concerning a film forming condition, different parameter values are set for one parameter and the same predetermined values are set for other parameters to manufacture two pieces of film structures including a high-dielectric constant film or ferroelectric film formed on a substrate. The film characteristics...

20060068512 - Method and apparatus for detecting defects: An inspection apparatus projects a laser beam on the surface of a SOI wafer and detects foreign matter on and defects in the surface of the SOI wafer by receiving scattered light reflected from the surface of the SOI wafer. The wavelength of the laser beam used by the inspection...

20060068514 - Method of detecting un-annealed ion implants: A current-voltage response of at least one site of a semiconductor wafer where ions have been implanted in the semiconducting material of the semiconductor wafer is measured prior to annealing the semiconductor wafer. From the measured response, a determination is made whether the ion implantation is within acceptable tolerance(s)....

20060068515 - Method for manufacturing a gan based led of a back hole structure: This invention relates to a method for manufacturing a GaN based LED of a back hole structure, and the method comprises: epitaxially growing an N type GaN layer, a multi-quantum wells emitting active region and a P type GaN layer in turn on an insulation substrate made of sapphire or...

20060068516 - Method for producing nitride semiconductor laser light source and apparatus for producing nitride semiconductor laser light source: A method for producing a nitride semiconductor laser light source is provided. The nitride semiconductor laser light source has a nitride semiconductor laser chip, a stem for mounting the laser chip thereon, and a cap for covering the laser chip. The laser chip is encapsulated in a sealed container composed...

20060068517 - Optical device and method for making the same: A method for making an optical device includes the steps of: rubbing an orienting film so as to stretch the molecular structure thereof and so as to permit the molecular units of the molecular structure to be aligned along a first axis and to permit the orienting space between each...

20060068518 - Forming vertically aligned liquid crystal mixtures: Vertically aligned liquid crystal molecules may be formed using spin-on-glass deposition. After deposition, the molecules may be exposed to an oblique ion beam or e-beam bombardment. Other techniques for alignment involve microstructure formation such as using a double sided scrubber or high oxygen plasma processing. As a result, more conventional...

20060068519 - Method for making electronic devices having a dielectric layer surface treatment: A method of making an electronic device by (a) depositing a substantially nonfluorinated polymeric layer onto a dielectric layer using a plasma-based deposition technique selected from the group consisting of (i) plasma polymerizing a precursor comprising monomers, and (ii) sputtering from a target comprising one or more polymers of interpolymerized...

20060068520 - Method of fabricating organic light emitting display: A method of fabricating a donor substrate for a laser induced thermal imaging (LITI) process. A base substrate is prepared. A light-to-heat conversion layer is formed on the base substrate. A buffer layer is formed on the light-to-heat conversion layer. The surface roughness of the buffer layer is increased by...

20060068521 - Method of fabricating microelectronic package using no-flow underfill technology and microelectronic package formed according to the method: A method of fabricating a microelectronic package, a package fabricated according to the method, and a system including the package. The method comprises: providing a substrate and a die each having pre-solder bumps thereon; placing a patterned underfill film onto the substrate, the film having a filler therein, being substantially...

20060068522 - Semiconductor device with improved heat dissipation, and a method of making semiconductor device: A semiconductor device includes a semiconductor chip, a heat dissipation member for dissipating heat generated by the semiconductor chip, and a coupling member which thermally couples the semiconductor chip to the heat dissipation member, wherein the coupling member is made of metal and deformable to absorb a stress generated between...

20060068523 - Integrated circuit package: Two integrated circuits 1, 3, 101, 103 having circuitry on one of their major surfaces 11, 31, 111, 131 are ground on their opposite major surfaces 13, 33 to reduce their thickness. The ground integrated circuits are then adhered together to form a composite body 7 and placed in a...

20060068524 - Protective tape separation method, and apparatus using the same: The invention relates to an apparatus for separating a protective tape joined to a semiconductor wafer. Before joining a separation tape to a protective tape on a surface of a semiconductor wafer held, from its back side, by a ring frame via a dicing tape while pressing the separation tape...

20060068525 - Method of manufacturing a wiring substrate and an electronic instrument: A method of manufacturing a wiring substrate having a wiring layer formation step that includes: a first surface processing step in which surface processing is performed on a film formation area of a substrate; a wiring formation step in which a wiring pattern is formed by placing a first liquid...

20060068526 - Acrylic polymer-containing gap filler forming composition for lithography: There is provided a gap fill material forming composition for lithography that is used in dual damascene process and is excellent in flattening property and fill property. Concretely, it is a gap fill material forming composition characterized in that the composition is used in manufacture of semiconductor device by a...

20060068527 - Molded stiffener for thin substrates: A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate...

20060068528 - Method for manufacturing a cbram semiconductor memory: A method for manufacturing CBRAM switching elements and CBRAM semiconductor memories with improved switching characteristics so as to remove superfluous, weak, cluster-like, or unbound selenium at the surface of a GeSe layer is solved by the present invention in that, after the generation of an active matrix material or GeSe...

20060068529 - Self-aligned split-gate nand flash memory and fabrication process: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with...

20060068532 - Dual-gate thin-film transistor: A dual-gate thin film transistor (DG-TFT) and associated fabrication method are provided. The method comprises: forming a first (back) gate in a first horizontal plane; forming source/drain (S/D) regions and an intervening channel region in a second horizontal plane, overlying the first plane; and, forming a second (top) gate in...

20060068531 - Finfet sram cell using inverted finfet thin film transistors: An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a...

20060068530 - Semiconductor device and method of manufacturing same: at least a first, in particular planar, metallization region (40) arranged between the isolating layer (10) and the component (30), in particular between the isolating layer (10) and the slightly doped zone (34) of the component (30), as well as a method of manufacturing at least one semiconductor device (100)...

20060068533 - Thin film circuit device, manufacturing method thereof, electro-optical apparatus, and electronic system: To provide a thin film circuit device in which a three-dimensional circuit structure is realized, a thin film circuit device is formed of a first thin film circuit layer and a second thin film circuit layer laminated to each other. The first thin film circuit layer contains a first thin...

20060068534 - Method for manufacturing semiconductor device: Laser is applied onto part on an SOS substrate using a sapphire layer to form an identifying mark. The sapphire layer on the surface of the SOS substrate, which has been exposed upon laser application, is covered with an insulating film formed by heat treatment at 700° C. or less,...

20060068538 - Manufacturing method of semiconductor device: A method of manufacturing a semiconductor device comprises the following steps: a step of depositing a silicon oxide film on the top surface of an epitaxial layer of the region where a high withstand voltage MOS transistor is formed; a step of subsequently depositing a silicon oxide film on the...

20060068536 - Method for manufacturing semiconductor device, and semiconductor device and electronic device: It is an object of the present invention to manufacture a semiconductor device easily and to provide a semiconductor device whose cost is reduced. According to the present invention, a thin film integrated circuit provided over a base insulating layer can be prevented from scattering by providing a region where...

20060068537 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer...

20060068535 - Methods of fabricating semiconductor devices: Methods of forming semiconductor devices are provided. A preliminary gate structure is formed on a semiconductor substrate. The preliminary gate structure includes a gate insulation layer pattern, a polysilicon layer pattern and a conductive layer pattern. A first oxidation process is performed on the preliminary gate structure using an oxygen...

20060068539 - Method of fabricating cmos type semiconductor device having dual gates: According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating...

20060068540 - Sequential chemical vapor deposition - spin-on dielectric deposition process: A method to fill a valley on a substrate comprises depositing a first material onto the substrate using a chemical vapor deposition process to partially fill the valley and depositing a second material onto the substrate using a spin-on deposition process to completely fill the valley. The chemical vapor deposition...

20060068541 - Integration scheme to improve nmos with poly cap while mitigating pmos degradation: A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer...

20060068542 - Isolation trench perimeter implant for threshold voltage control: A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of...

20060068543 - Electro-and electroless plating of metal in the manufacture of pcram devices: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a...

20060068544 - Semiconductor device with dram cell and method of manufacturing the same: A method of manufacturing a semiconductor device includes forming a trench in a semiconductor substrate, isotropically forming a trench surface insulating film on an inner surface of the trench, the trench surface insulating film including a deep part functioning as a capacitor insulating film, forming a surface layer side insulating...

20060068545 - Fabricating transistor structures for dram semiconductor components: A method for fabricating transistor structures for DRAM semiconductor components includes forming gate conductor structures in a cell array of a DRAM semiconductor component and covering the structures with a spacer liner. The gate conductor structures lie on a silicon semiconductor substrate. A masked spacer etch produces a spacer mask...

20060068548 - Memory cell and method for forming the same: A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and...

20060068547 - Methods of forming self-aligned floating gates using multi-etching: A method of forming a floating gate of a non-volatile memory device can include etching a mask pattern formed between field isolation regions in a field isolation pattern on a substrate to recess a surface of the mask pattern below an upper surface of adjacent field isolation regions to form...

20060068546 - Self-aligned non-volatile memory and method of forming the same: A non-volatile memory is described. A substrate comprising a stacked layer is provided. A sacrificial layer is deposited and patterned to form a first opening. A first spacer is formed on sidewalls of the first opening, and the stacked layer is etched using the first spacer as a first mask...

20060068549 - Image display device: An image display device includes a first substrate having a phosphor screen, and a second substrate opposed to the first substrate across a gap and having a plurality of electron emission sources which excite the phosphor screen. A spacer assembly which supports atmospheric load acting on the first and second...

20060068550 - Independently accessed double-gate and tri-gate transistors in same process flow: A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member...

20060068551 - Method for embedding nrom: A method for embedding non-volatile memories with logic circuitry, without changing performance of both the logic circuitry and the NVM elements (and/or without changing a sequence of manufacturing steps for both the logic circuitry and the NVM elements). The embedding process includes insertion of NVM device and array process steps...

20060068552 - Method of manufacturing semiconductor device: In a semiconductor device manufacturing method of the present invention, a polysilicon film and a silicon nitride film are deposited on an upper surface of an epitaxial layer. Patterning is performed so that the polysilicon film and the silicon nitride film are left in regions in which a LOCOS oxide...

20060068553 - Method for forming a semiconductor device having a strained channel and a heterojunction source/drain: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material...

20060068554 - Process for etching trenches in an integrated optical device: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas...

20060068555 - Structure and method for manufacturing mosfet with super-steep retrograded island: The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure...

20060068556 - Semiconductor device and method for fabricating the same: The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode....

20060068557 - Semiconductor device and method for fabricating the same: On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon...

20060068558 - Process and installation for doping an etched pattern of resistive elements: A process for selectively doping predetermined resistive elements on an electronic chip is provided. The resistive elements are arranged in a pattern, and there are three phases in the process. The first phase electrically charges selected elements of the pattern. The second phase adds doping atoms to the charged elements...

20060068559 - Method of fabricating capacitor: A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a single doped region as a lower...

20060068560 - Bst integration using thin buffer layer grown directly onto sio2/si substrate: A BST microwave device includes a substrate and an insulating layer that is formed on the substrate. A buffer layer is formed on the insulating layer. A BST layer is formed on the buffer layer with a selected orientation for high tunability and possesses a low loss in a wavelength...

20060068561 - Semiconductor device and method for manufacturing thereof: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the...

20060068562 - Trench isolation structure and method of manufacture therefor: The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. In one aspect, the method includes forming a hardmask over a substrate, etching a trench in the substrate through the hardmask,...

20060068563 - Method of manufacturing and structure of polycrystalline semiconductor thin-film heterostructures on dissimilar substrates: According to various exemplary embodiments of this invention, a method of producing a semiconductor structure is provided that includes providing a layered structure on a first substrate, the layered structure including a silicon layer that is provided over a first dielectric layer, a first dielectric layer that is provided over...

20060068564 - Micromachined electromechanical device: A method for fabricating a MEMS device comprises providing a substrate having a back side, a front side opposite to the back side and a periphery portion. A desired microstructure is formed on the back side of the substrate. The substrate is then supported for rotation. A precursor solution is...

20060068565 - System and method for hydrogen exfoliation: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming...

20060068566 - Film sticking method and film sticking device: There is provided a film sticking method for sticking a film on a pattern forming face of a wafer, on the pattern forming face (21) of which a circuit pattern (C) is formed, comprising the steps of: positioning the wafer (20) so that a sticking direction of a film sticking...

20060068567 - Method for chip singulation: The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and...

20060068569 - Semiconductor device and method for manufacturing the same: A semiconductor device using a crystalline semiconductor film is manufactured. The crystalline semiconductor film is formed by providing an amorphous silicon film with a catalyst metal for promoting a crystallization thereof and then heated for performing a thermal crystallization, following which the crystallized film is further exposed to a laser...

20060068568 - Silicon epitaxial wafer and method for manufacturing the same: This method for manufacturing a silicon epitaxial wafer includes: a step of growing an epitaxial layer having silicon on a silicon wafer having a main surface of {110}; and a cooling step of cooling the silicon wafer after growing the epitaxial layer. In a first aspect, in the cooling step,...

20060068570 - Structure with through hole, production method thereof, and liquid discharge head: A structure is constructed having a through hole in a substrate of silicon or the like by a decreased number of steps in production and with improved reliability. A silicon nitride film is formed in contact with an upper surface of a silicon oxide film at least on a portion...

20060068571 - Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same: A semiconductor device includes a graded junction termination extension. A method for fabricating the device includes providing a semiconductor layer having a pn junction, providing a mask layer adjacent to the semiconductor layer, etching the mask layer to form at least two laterally adjacent steps associated with different mask thicknesses...

20060068572 - Semiconductor device manufacturing method: The invention is directed to improvement of reliability of a chip size package type semiconductor device in a manufacturing method thereof. A support body is formed on a front surface of a semiconductor substrate with a first insulation film therebetween. Then, a part of the semiconductor substrate is selectively etched...

20060068573 - Multilayer structure forming method, method of manufacturing wiring board, and method manufacturing of electronic apparatus: A droplet discharge apparatus is used in a multilayer structure forming method of the invention. The multilayer structure forming method includes: discharging droplets of a first conductive material to form a first conductive material pattern on a surface of an object; baking the first conductive material pattern to form a...

20060068574 - Post passivation interconnection schemes on top of the ic chips: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick...

20060068575 - Gate electrode forming methods using conductive hard mask: Methods related to formation of a gate electrode are disclosed that employ a conductive hard mask as a protective layer during a photoresist removal process. In preferred embodiments, the conductive hard mask includes a metal containing conductor or a metal silicide. The invention prevents process damage on the gate dielectric...

20060068576 - Lithography transfer for high density interconnect circuits: A method for fabricating an interconnect comprising providing a carrier substrate, wherein the carrier substrate comprises a plurality of interconnect traces and a plurality of input/output contacts; providing a flexible substrate having a first side and a second side, disposing the second side of the sacrificial layer onto the first...

20060068578 - Manufacturing method of semiconductor device and semiconductor device: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to be patterned to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end...

20060068577 - Method for fabricating electrical interconnect structure: A method for fabricating an electrical interconnect structure is adapted for a circuit board manufacturing process. The circuit board comprises a conductive substrate, which comprises a first conductive layer and a bump conductive layer. The bump conductive layer is patterned to form at least one bump over the first conductive...

20060068580 - Semiconductor device and fabrication method thereof: The semiconductor device of the present invention and the method of the present invention, for forming the semiconductor device, form: a penetrating hole in a semiconductor wafer which has a first insulating film and an electrode pad formed on a first face of the semiconductor wafer, the penetrating hole being...

20060068579 - Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to...

20060068582 - Method for decreasing impedance of a power source in a printed circuit board: A method for decreasing impedance of a power source in a printed circuit board includes: (a) forming a first metal plane over a first layer of the printed circuit board; (b) forming a second metal plane and a third metal plane over a second layer of the printed circuit board;...

20060068581 - Method of forming via hole in resin layer: To reliably expose an underlying layer at a bottom surface of a via hole to form a via hole even at a resin layer including an inorganic filler. A method of forming a via hole by firing a laser beam at a resin layer (10) including an inorganic filler (12)...

20060068583 - A method for supercritical carbon dioxide processing of fluoro-carbon films: A method for treating a fluoro-carbon dielectric film for integration of the dielectric film into a semiconductor device. The method includes providing a substrate having a fluoro-carbon film deposited thereon, the film having an exposed surface containing contaminants, and treating the exposed surface with a supercritical carbon dioxide fluid to...

20060068584 - Low k interlevel dielectric layer fabrication methods: A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it...

20060068585 - Method for forming a metal silicide layer in a semiconductor device: On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that...

20060068586 - Method for implementation of back-illuminated cmos or ccd imagers: A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the...

20060068587 - Copper alloy for semiconductor interconnections, fabrication method thereof, semiconductor device having copper alloy interconnections fabricated by the method, and sputtering target for fabricating copper alloy interconnections for semiconductors: A Cu alloy for semiconductor interconnections contains at least one selected from the group consisting of 0.10 to 10 atomic percent of Sb, 0.010 to 1.0 atomic percent of Bi, and 0.01 to 3 atomic percent of Dy, with the balance being Cu and inevitable impurities. The Cu alloy can...

20060068588 - Low-pressure deposition of ruthenium and rhenium metal layers from metal carbonyl precursors: A method for depositing Ru and Re metal layers on substrates with high deposition rates, low particulate contamination, and good step coverage on patterned substrates is presented. The method includes providing a substrate in a process chamber, introducing a process gas in the process chamber in which the process gas...

20060068591 - Fabrication of channel wraparound gate structure for field-effect transistor: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is...

20060068590 - Metal gate transistors with epitaxial source and drain regions: An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor....

20060068589 - Selective barrier slurry for chemical mechanical polishing: The polishing solution is useful for removing a barrier from a semiconductor substrate. The solution contains by weight percent 0.001 to 25 oxidizer, 0.0001 to 5 anionic surfactant, 0 to 15 inhibitor for a nonferrous metal, 0 to 40 abrasive, 0 to 20 complexing agent for the nonferrous metal, 0.01...

20060068592 - Method for etch-stop layer etching during damascene dielectric etching with low polymerization: The present invention provides a method for etching a substrate 100. The method includes conducting a first etch through a dielectric layer 130 located over an etch-stop layer 140, the dielectric layer having a photoresist layer 170 located thereover and the first etch being selective to the etch-stop layer 140....

20060068593 - Patterning method: A patterning method is provided. First, a substrate comprising a film formed thereon is provided. Then, a photoresist layer is formed over the film. Next, the photoresist layer is developed to form a patterned photoresist layer. Then, the film is etched using a dry etching method. In addition, the dry...

20060068594 - Method for line etch roughness (ler) reduction for low-k interconnect damascene trench etching: The present invention provides a method for etching a substrate 100. The method includes conducting a first etch on an anti-reflective layer 170 and a portion of a hardmask layer 140, 150 to form an opening 162 in the substrate 100. The first etch is designed to be selective to...

20060068595 - Semiconductor substrate thinning method for manufacturing thinned die: In a method according to the present invention, a substrate thinning process is performed on a bumped substrate prior to the ultimate solder reflow process to heal bump defects caused by the substrate thinning process. Concurrently, the risk of substrate breakage is reduced compared to the prior art process since...

20060068596 - Formation of controlled sublithographic structures: A process for forming sublithographic structures such as fins employs a hardmask protective layer above a hardmask to absorb damage during a dry etching step, thereby preserving symmetry in the hardmask and eliminating a source of defects....

20060068597 - Method for texturing surfaces of silicon wafers: In a method for texturing surfaces of silicon wafers comprising the steps of dipping the silicon wafers in an etching solution of water, concentrated hydrofluoric acid and concentrated nitric acid and setting a temperature for the etching solution, it is provided that the etching solution comprises, in percent, 20% to...

20060068598 - Film formation apparatus and method of using the same: A method of using a film formation apparatus for a semiconductor process includes removing by a cleaning gas a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus, and then chemically planarizing the inner surface of the reaction chamber by a planarizing gas....

20060068599 - Methods of forming a thin layer for a semiconductor device and apparatus for performing the same: The present invention can provide methods of forming a thin layer for a semiconductor device. The methods can include forming a recessed portion on an object, and forming an insulation layer on the object by reacting a water vapor, an oxygen gas including an oxygen radical and an organic silicon...

20060068600 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a plated film on a substrate which has a recessed portion on its surface so as to bury in the recessed portion by a plating method; forming over the plated film a compressive...

20060068601 - Wafer for compound semiconductor devices, and method of fabrication: A wafer for fabrication of nitride semiconductor devices such as LEDs, HEMTs and FETs. The matrices of desired semiconductor devices are grown on a silicon substrate via a buffer region designed to keep the wafer from warping. The buffer region is in the form of alternations of multi-sublayered first buffer...

20060068602 - Electronic device having organic material based insulating layer and method for fabricating the same: In an electronic device, insulating layers (24, 26 and 28) on metal conductors (23 and 27) situated inside the device are formed of insulating layers made of a novolac resin, and an insulating layer made of a polyimide resin is used as an insulating layer (30) covering these insulating layers...

20060068603 - A method for forming a thin complete high-permittivity dielectric layer: A method for forming a thin complete high-k layer for semiconductor applications. The method includes providing a substrate in a process chamber, depositing a thick complete high-k layer on the substrate, and thinning the deposited high-k layer to form a thin complete high-k layer on the substrate. Alternately, the substrate...

20060068604 - Barrier layer and fabrication method thereof: A barrier layer and a fabrication thereof are disclosed. The barrier layer comprises at least one barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one component of oxygen, nitrogen or carbon. A ratio of the component...

20060068605 - Method of manufacturing oxide film and method of manufacturing semiconductor device: A method of manufacturing an oxide film includes jetting onto a substrate a high-pressure solution containing an oxygen source and having a pressure of 5 MPa, and forming an oxide film on the substrate using the jetted high-pressure solution....

20060068606 - Method and apparatus for forming silicon nitride film: A method for forming a silicon nitride film first deposits a silicon nitride film on a target substrate by CVD in a process field within a reaction container. This step is arranged to supply a first process gas containing a silane family gas and a second process gas containing a...

20060068607 - Laser illumination apparatus: A laser illumination apparatus for illuminating a semiconductor film with a linear laser beam while scanning the semiconductor film with the linear laser beam. An optical system generates a linear laser beam having a beam width W by dividing a pulse laser beam that is emitted from a pulsed laser...

20060057742 - Method of forming cnt containing wiring material and sputtering target material used for the method: A method of forming a CNT containing wiring material is conducted by sputtering simultaneously CNT and a metal material on a surface of a substrate to form a CNT containing metal layer, then pattern-etching the CNT containing metal layer to form a wiring pattern. A sputtering target material having a...

20060057744 - Method of manufacturing a semiconductor device: A method of manufacturing a semiconductor device includes: forming a circuit element on a semiconductor substrate; forming a first insulation film on top to cover the circuit element; forming a first electrode on top; forming a ferroelectric film on the first electrode; forming a second electrode on the ferroelectric film;...

20060057745 - Novel oxidation structure/method to fabricate a high-performance magnetic tunneling junction mram: An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) has a tunneling barrier layer of substantially uniform and homogeneous Al2O3 stoichiometry. The barrier layer is formed by depositing Al on a CoFe layer or a CoFe—NiFe bilayer having an oxygen surfactant layer formed thereon, then oxidizing the Al by...

20060057743 - Spintronic device having a carbon nanotube array-based spacer layer and method of forming same: This invention relates to spintronic devices—and electronic devices comprising them, such as spin valves, spin tunnel junctions and spin transistors—which utilize a layer comprised of an array of aligned carbon nanontubes. A spintronic device includes, a bottom electrode, a first ferromagnetic layer, a CNT array, a second ferromagnetic layer and...

20060057746 - Semiconductor device fabrication method and apparatus: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a film made of an insulating material on a surface of a semiconductor substrate; measuring a film thickness and/or composition of the film; setting nitriding conditions or oxidation conditions on the basis of the measurement...

20060057747 - Reloading of die carriers without removal of die carriers from sockets on test boards: A method of testing microelectronic dies is described. A respective set of dies is inserted into die carrier bodies releasably held within a set of sockets secured to a burn-in board. A set of die carrier covers is closed, each die carrier cover being secured to a respective die carrier...

20060057748 - Control of contact resistance in quantium well intermixed devices: A method of performing quantum well intermixing in a semiconductor device structure uses a sacrificial part of a cap layer, that is removed after QWI processing, to restore the cap surface to a condition in which high performance contacts are still possible. The method includes: a) forming a layered quantum...

20060057751 - Led package and method for producing the same: A method for producing an LED package is provided, the LED package includes an LED die, which has a light-emitting surface, a non-light-emitting surface opposite to the light-emitting surface, a first electrode and a second electrode arranged on the non-light-emitting surface, a reverse-voltage protection member arranged on the non-light-emitting surface...

20060057750 - Method and apparatus for manufacturing display: Provided is a method of manufacturing a display which includes an insulating substrate and a structure formed on the insulating substrate and including a display element, including forming a patterned layer as a portion of the structure on the insulating substrate by vapor deposition in vacuum using a mask, and...

20060057749 - Template type substrate and a method of preparing the same: The template type substrate is used for opto-electric or electrical devices and comprises A) a layer of bulk mono-crystal nitride containing at least one element of alkali metals (Group I, IUPAC 1989) and B) a layer of nitride grown by means of vapor phase epitaxy growth wherein the layer A)...

20060057752 - Light emitting diode and method of making the same: A light emitting diode (LED) and a method of making the same are disclosed. The present invention uses a metal layer of high conductivity and high reflectivity to prevent the substrate from absorbing the light emitted. This invention also uses the bonding technology of dielectric material thin film to replace...

20060057753 - Methods for producing phosphor based light sources: Methods for producing phosphor based light sources are disclosed. One method includes measuring an excitation light output of an LED, forming a plurality of phosphor film articles, measuring an optical characteristic of each of the plurality of phosphor film articles, selecting one of the plurality of phosphor film articles based...

20060057755 - Micromechanical component and suitable method for its manufacture: A micromechanical component having a silicon substrate; a cavity provided in the substrate; and a diaphragm, provided on the surface of the substrate, which closes the cavity; the diaphragm featuring a silicon-oxide layer having an opening that is formed by silicon-oxide wedges pointing to each other; and the diaphragm having...

20060057754 - Systems and methods of actuating mems display elements: Methods of writing display data to MEMS display elements are configured to minimize charge buildup and differential aging. The methods may include writing data with opposite polarities, and periodically releasing and/or actuating MEMS elements during the display updating process. Actuating MEMS elements with potential differences higher than those used during...

20060057757 - Method of manufacturing semiconductor probe having resistive tip: A method of manufacturing a semiconductor probe having a resistive tip. The method includes forming first and second mask films having a rectangular shape on a silicon substrate, first etching an upper surface of the silicon substrate, forming a third mask film corresponding to a width of a tip neck...

20060057756 - Surface shape recoginition sensor and method of producing the same: A structure (113b) which includes an overhang and a support portion supporting substantially the center of the overhang, and in which the area of the support portion is smaller than the area of the overhang in the two-dimensional direction of an upper electrode (110b) is formed on the upper electrode...

20060057758 - Semiconductor physical quantity sensor and method for manufacturing the same: A method for manufacturing a semiconductor physical quantity sensor including a support substrate, a movable electrode, a fixed electrode is provided. The method includes the steps of: preparing a multi-layered substrate; forming a compression stress layer on a part of a surface of the semiconductor layer; forming a trench in...

20060057760 - Image sensor and method for forming the same: A reliable image sensor and a method for forming the same are provided. The image sensor includes a photo-detective device. At least one transistor is electrically connected to the photo-detective device for outputting charges stored in the photo-detective device. A transistor directly connected to the photo-detective device includes a gate...

20060057761 - Method for fabricating microstructure and microstructure: A method of making a microstructure with thin wall portions (T1-T3) includes a step of performing a first etching process to a material substrate having a laminate structure including a first conductive layer (11) and a second conductive layer (12) having a thickness of the thin wall portions (T1-T3), where...

20060057759 - System and method to improve image sensor sensitivity: A method is disclosed for forming at least one image sensor with improved sensitivity along with at least one transistor device. The method comprises forming at least a portion of the transistor device on a substrate, forming the image sensor by doping a predetermined area separated from the transistor device...

20060057762 - Method of building electronic label for electronic device: A method for building an electronic label within an electronic device, which packs and incorporates the electronic label into the electronic device, protects the electronic label from separation or damage caused by external force, and thereby facilitates the sale management or manufacture management of various electronic devices. The method includes...

20060057763 - Method of forming a surface mountable ic and its assembly: A flip-chip interconnect structure for a RFID tag is described which permits the use of an isotropic electrically conductive adhesive (ECA) without requirement of critical alignment of the chip terminal pads to antenna terminals on the substrate. The interconnect foot print utilizes design principles of standard discrete SMD terminal footprint,...

20060057764 - Image sensor and fabricating method thereof: An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical...

20060057765 - Image sensor including multiple lenses and method of manufacture thereof: A device includes an image sensing element. The device also includes a Silicon Dioxide (SiO2) layer, located over the image sensing element, exhibiting a first index of refraction. The device further includes a first lens, located over the SiO2 layer, exhibiting a second index of refraction greater than the first...

20060057766 - Method for preparation of semiconductive films: A polymer assisted solution process for deposition of semiconductive thin films is presented. The process can be organic solvent-free. The process includes solutions of necessary metal precursors and soluble polymers. After a coating operation, the resultant coating is fired at high temperatures to yield optical quality metal oxide thin films...

20060057767 - Nanoscale mass conveyors: A mass transport method and device for individually delivering chargeable atoms or molecules from source particles is disclosed. It comprises a channel; at least one source particle of chargeable material fixed to the surface of the channel at a position along its length; a means of heating the channel; and...

20060057771 - Low cost fabrication of microelectrode arrays for cell-based biosensors and drug discovery methods: A method for making a plurality of low-cost microelectrode arrays (MEAs) on one substrate utilizing certain unmodified printed circuit board (PCB) fabrication processes and selected materials. In some embodiments, a MEA device is composed of a thin polymer substrate containing patterned conductive traces. Coverlays on both sides of the substrate...

20060057772 - Method for forming a redistribution layer in a wafer structure: The present invention relates to a method for forming a redistribution layer in a wafer structure. The method comprises: (a) providing a wafer having a plurality of conductive structures and a first passivation layer thereon, wherein the first passivation layer covers the wafer except the conductive surfaces of the conductive...

20060057770 - Method for packaging chip and package assembly produced thereby: A method for packaging a chip is rather than a conventional package technology and can improve the ability of packaging a photoelectric chip in order to save materials and costs. A chip package assembly is produced by preparing a transparent substrate in advance, a chip is electrically connected to a...

20060057768 - Semiconductor element heat dissipating member, semiconductor device using same and manufacturing same: A semiconductor element heat dissipating member is provided which has excellent heat dissipation characteristics and adhesion characteristics and enables production of a semiconductor device at a low cost. A semiconductor device using the same, and a method of producing the same are also provided. The semiconductor element heat dissipating member...

20060057769 - Use of conductive carbon black/graphite mixtures for the production of low-cost electronics: The invention relates to conductive polymer solutions which can be employed for the production of organic electronic components. To this end, particles of carbon black and graphite are used in the form of microplatelets in polymer solutions....

20060057773 - Method for producing a stack of chips, a stack of chips and method for producing a chip for a multi-chip stack: A method for producing a stack of at least two chips that are electrically interconnected, a stack of chips and a method for producing a chip for a multi-chip stack. A capillary channel is routed in a provided chip from its lower to its upper side. The channel is sufficiently...

20060057774 - Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages: A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites accessible for electrical coupling to other electrical structures. A...

20060057775 - Method of forming a wafer backside interconnecting wire: A method of forming a wafer backside interconnecting wire includes forming a mask layer on the back surface, the mask layer including at least an opening corresponding to the bonding pad, performing a first etching process from the back surface to remove the wafer unprotected by the mask layer to...

20060057776 - Wafer stacking package method: A method of wafer stacking packaging. The method comprises providing a die array including a plurality of singulated first dies cut from a first wafer; providing a second wafer with inseparate the second dies and an adhesive layer on an active surface thereof; pre-cuting the second wafer to a specified...

20060057777 - Separating die on a substrate to reduce backside chipping: A method of separating die on a substrate to reduce backside chipping. Two or more microelectronic components are created on a first side of a substrate, wherein a space exists between adjacent components. A trench is created in the other side of the substrate, wherein the location of the trench...

20060057778 - Fabricating method of wafer protection layers: A fabricating method of wafer protection layers and a wafer structure are provided. The fabricating method includes providing a wafer first. The wafer includes pluralities of chips and has an active surface, a corresponding reverse surface and a plurality of pre-cut trenches on the active surface. On the active surface,...

20060057780 - Manufacturing apparatus of semiconductor devices, and method of manufacturing semiconductor devices: A method for manufacturing semiconductor devices, comprises: mounting a substrate on a bonding stage; pressing the substrate to the bonding stage by blowing a compressed air from the upper face side of the substrate; causing the bonding stage to adsorb the substrate by exhausting air from the lower face side...

20060057779 - Silicone-based adhesive sheet, method of bonding a semiconductor chip to a chip attachment component, and a semiconductor device: A silicone-based adhesive sheet has either a layer of clay-like curable silicone composition on one side and a layer of slower curing clay-like curable silicone composition than the first composition layer on the other side, or a cured silicone layer on one side and a layer of clay-like curable silicone...

20060057781 - Plastic leadframe and compliant fastener: Packaging assembly method and systems include the use of a plastic substrate and one or more compliant fasteners, which can be connected to the plastic substrate, such that the compliant fastener provides an electrical connection to one or more electrical components. A plastic leadframe can therefore be formed, which is...

20060057782 - Thin glass chip for an electronic component and manufacturing method: The manufacturing of electronic components on individual substrates made of an insulating material includes molding, in a silicon wafer, an insulating material with a thickness corresponding to the final thickness desired for the substrates, manufacturing the electronic components, and removing the silicon from the rear surface of the wafer after...

20060057783 - Methods of forming fuses using selective etching of capping layers: A method of forming a fuse in a semiconductor device can be provided by selectively removing an inter-metal insulator to expose a fuse capping layer by recessing the inter-metal insulator around the fuse and removing the capping layer from the fuse to expose a fuse metal film thereunder....

20060057784 - Enhanced resurf hvpmos device with stacked hetero-doping rim and gradual drift region: An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on...

20060057786 - Method of manufacturing a semiconductor film and method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor film, nickel elements are first held as indicated by 103 on the surface of an amorphous silicon film 102. Then a crystalline silicon film 104 is obtained by a heat treatment. At this time, the crystallization is remarkably improved by the action of...

20060057785 - Method of manufacturing semiconductor device: Disclosed is a method of manufacturing a semiconductor device, comprising introducing a work piece comprising a semiconductor substrate, a gate insulation film formed on the semiconductor substrate, and a gate electrode film formed on the gate insulation film, into a chamber, and forming a gate electrode by selectively etching the...

20060057787 - Strained finfet cmos device structures: A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS...

20060057788 - Exposure mask pattern for lcd and exposure method using the same: An exposure method for an LCD is provided. In the method, a sub-pixel region of an array substrate is divided into a first exposure region and a second exposure region, and the first exposure region and the second exposure region are sequentially exposed....

20060057789 - Method for manufacturing semiconductor device: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a...

20060057790 - Hemt device and method of making: A HEMT type device which has pillars with vertical walls perpendicular to a substrate. The pillars are of an insulating semiconductor material such as GaN. Disposed on the side surfaces of the pillars is a barrier layer of a semiconductor material such as AlGaN having a bandgap greater than that...

20060057791 - Method of fabricating micro-chips: A method of fabricating micro-chips, including: (a) providing a substrate; (b) forming a first single-crystal layer on a top surface of the substrate; (c) forming a second single-crystal layer on a top surface of the first single-crystal layer; (d) forming integrated circuits in the second single-crystal layer; (e) forming a...

20060057795 - Method of manufacturing a semiconductor integrated circuit device: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a...

20060057793 - Semiconductor device and manufacturing method of the same: The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n+-type source region of an LDMOSFET, and no such metal silicide film is formed on an n−-type offset drain region, an n-type offset drain region,...

20060057792 - Semiconductor device having conductive spacers in sidewall regions and method for forming: A conductive spacer (36, 122) in a sidewall region (30, 16) of a device (10, 100) is formed. The conductive spacer is formed adjacent sidewalls of the current electrode regions (18, 12). In one embodiment, a thin silicide layer (34) is formed at a top surface and a sidewall of...

20060057794 - Semiconductor devices including high-k dielectric materials and methods of forming the same: A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second...

20060057797 - Method for avoiding oxide undercut during pre-silicide clean for thin spacer fets: A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical...

20060057798 - Semiconductor device and its manufacturing method: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage...

20060057796 - Silicon carbide semiconductor device and its method of manufacturing method: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is...

20060057800 - Methods for treating pluralities of discrete semiconductor substrates: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the...

20060057799 - Substrate processing apparatus: A substrate processing apparatus stably and efficiently conducts a film forming process on a substrate to be processed. In the substrate processing apparatus, the substrate to be processed is supported at a position facing a heater portion, and a holding member for holding the substrate is rotated, whereby the temperature...

20060057801 - Thin films and methods for the preparation thereof: Thin films are disclosed that are suitable as dielectrics in IC's and for other similar applications. In particular, the invention concerns thin films comprising compositions obtainable by hydrolysis of two or more silicon compounds, which yield an at least partially cross-linked siloxane structure. The invention also concerns a method for...

20060057802 - Method of making a finfet having suppressed parasitic device characteristics: A finFET (100) having sidwall spacers (136, 140) to suppress parasitic devices in the upper region of a channel and at the bases of source(s) and drain(s) that are artifacts of the fabrication techniques used to make the finFET. The FinFET is formed on an SOI wafer (104) by etching...

20060057803 - Method to reduce a capacitor depletion phenomena: A method of integrating the fabrication of a capacitor cell and a logic device region, wherein the surface area of a capacitor region is increased, and the risk of a capacitor depletion phenomena is reduced, has been developed. After formation of insulator filled STI regions featuring tapered sides, a portion...

20060057804 - Etching method and apparatus: An etching method capable of controlling the film thickness of a hard mask layer uniformly is provided. A plasma etching is performed on a native oxide film by using an etching gas containing, for example, CF4 and Ar while a thickness of a silicon nitride film is being monitored and...

20060057805 - Method for forming a gate electrode in a non volatile memory device: Disclosed herein is a method for forming a gate electrode of a non-volatile memory device. In an etch process of a gate electrode for defining the gate electrode, the etch process is performed by selectively adding an addition gas containing carbon. This prevents undercuts from being formed on a sidewall...

20060057806 - Method for manufacturing flash memory device: Provided is a method for manufacturing a flash memory device, in which an oxidation process is carried out on the disclosed top surface of a semiconductor substrate to form a surface oxide film in the form of bird's beak with an appropriate width before conducting an etching process for trench....

20060057807 - Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive m: A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit...

20060057808 - Reducing oxidation under a high k gate dielectric: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier....

20060057809 - Methods for selective deposition to improve selectivity: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area...

20060057810 - Surface preparation method for selective and non-selective epitaxial growth: According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the drain region, and removing a second portion of...

20060057811 - Selective post-doping of gate structures by means of selective oxide growth: A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited...

20060057812 - Full sequence metal and barrier layer electrochemical mechanical processing: A method and apparatus for electrochemically processing metal and barrier materials is provided. In one embodiment, a method for electrochemically processing a substrate includes the steps of establishing an electrically-conductive path through an electrolyte between an exposed layer of barrier material on the substrate and an electrode, pressing the substrate...

20060057813 - Method of forming a polysilicon resistor: A polysilicon layer is formed on a dielectric layer positioned on a substrate. Then, the polysilicon layer is doped with first type dopants and second type dopants. Portions of the polysilicon layer and the dielectric layer are removed down to the surface of the substrate, so as to define at...

20060057814 - Fabricating a memory cell arrangement: A method is described for fabricating a DRAM memory cell, which includes a trench capacitor and a select transistor. After the capacitor trench has been etched and optionally the first capacitor electrode has been produced, the trench is filled with a dummy filling. After the gate electrode and the first...

20060057815 - Method of manufacturing a semiconductor device: In a method of manufacturing a high-voltage semiconductor device, a mask layer is formed on a semiconductor substrate. The mask layer is patterned to form a stepped portion of the mask layer. A photoresist pattern for defining an active region of the substrate is formed on the substrate using the...

20060057816 - Sensor element with trenched cavity: A micromechanical sensor element and a method for the production of a micromechanical sensor element that is suitable, for example in a micromechanical component, for detecting a physical quantity. Provision is made for the sensor element to include a substrate, an access hole and a buried cavity, at least one...

20060057818 - Package structure and method for optoelectric products: An optoelectric product is packaged according to the technology of wafer level chip scale package. A transparent wafer with multitudes of cavities is bonded onto a device wafer with a plurality of protruding patterns during packaging process. Each slot may receive the protruding patterns corresponding to two adjacent chip units...

20060057817 - Semiconductor device, its manufacture method and electronic component unit: A LED chip having first and second electrodes on opposite principal surfaces, is bonded to a substrate through a composite bonding layer. The composite bonding layer is formed when a support substrate including the substrate and a first bonding layer is bonded to a lamination structure including the LED, the...

20060057819 - Electronic part producing method and electronic part: A conductor portion is formed on the surface of a support member. After the conductor portion is formed, a copper foil on which resin is attached is moved downward from above the conductor portion to pressurize the conductor portion while covering it. the copper foil with the resin is pressed...

20060057820 - Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device: A method for producing an ultra-thin semiconductor chip and an ultra-thin back-illuminated solid-state image pickup device utilizing a semiconductor layer formed on a support substrate via an insulating layer to improve separation performance of a semiconductor layer from a support substrate and thereby improve the productivity and quality. The method...

20060057821 - Low temperature methods of etching semiconductor substrates: Methods of etching a semiconductor substrate may include providing a first gas that is chemically reactive with respect to the semiconductor substrate, and while providing the first gas, providing a second gas different than the first gas. More particularly, a molecule of the second gas may include a hydrogen atom,...

20060057822 - Chip dicing: A semiconductor structure and method for chip dicing. The method comprises the steps of (a) providing a semiconductor substrate; (b) forming first and second device regions of first and second chips, respectively, in and at top of the semiconductor substrate, wherein the first and second chips are separated by a...

20060057823 - Method for manufacturing a moulded mmc multi media card package obtained with laser cutting: A method is provided for manufacturing a fully moulded Multi Media Card package obtained by laser cutting wherein at least some edges and the corners around the package have rounded profile and a sufficient smoothness for a safe handling. The method includes providing a rounded groove on a substrate back...

20060057824 - Apparatus for producing nitride semiconductor, method for producing nitride semiconductor, and semiconductor laser device obtained by the method: The present invention relates to an apparatus for producing a nitride semiconductor by crystal-growing the nitride semiconductor on a substrate by diffusing a gas containing a source gas of group III element and a source gas of group V element. The gas is diffused in parallel with the substrate and...

20060057825 - Semiconductor devices with reduced active region defects and unique contacting schemes: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that...

20060057826 - System and method for suppression of wafer temperature drift in cold-wall cvd systems: An apparatus and corresponding method are disclosed that uses one or more optical fibers in a susceptor that monitor radiation emitted by the backside of the susceptor. The optical fibers are filtered and converted into an electrical signal. A control system is used to maintain a constant wafer temperature by...

20060057827 - Method for manufacturing in electrically conductive pattern: The present invention relates to a method for manufacturing an electrically conductive pattern by printing a layer comprising metal oxide on a carrier substrate (2) and reducing the metal oxide to metal. The reduced layer is transferred to an application substrate (7). The present invention also relates to the use...

20060057828 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces of the gate structure and the major surface of...

20060057830 - Method for producing bumps on an electrical component: A method for producing contacts in the form of bumps on a component that comprises a base body includes, first, positioning a template on the base body. Through holes are produced through the template. By filling the through holes with an electrically conductive material and subsequently hardening, fillers are produced....

20060057829 - Method of forming a damascene structure with integrated planar dielectric layers: Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the dielectric material to expose a portion of the substrate; depositing a barrier metal over the dielectric material and the exposed...

20060057833 - Method of forming solder ball, and fabricating method and structure of semiconductor package using the same: A method of forming solder balls may involve forming bumps through wire boding on land patterns of a circuit substrate. Solder cream may be applied to the bumps through screen printing. The solder cream may be melted via reflow to form solder balls in which the bumps are embedded....

20060057834 - Semiconductor device and fabrication process thereof: A semiconductor device includes a conductive layer with a plurality of wires, and a bonding pad formed in a region overlapping with the plurality of wires of the conductive layer. One of the wires is connected to the bonding pad, and an insulating protective film is formed between the remaining...

20060057832 - Wafer level packages and methods of fabrication: A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least...

20060057831 - Wire bond pads: A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on...

20060057835 - Air-gap insulated interconnections: Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through,...

20060057836 - Method of stacking thin substrates by transfer bonding: This invention describes a method of stacking, bonding, and electrically interconnecting a plurality of thin integrated circuit wafers to form an interconnected stack of integrated circuit layers. The first integrated circuit layer is formed by conventional processing on a silicon wafer to the stage where bond pads are patterned on...

20060057837 - Treating agent materials: A treating agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent which may be an acid, a base, an...

20060057838 - Low k ild layer with a hydrophilic portion: Embodiments of the invention provide a relatively hydrophilic layer in a low k dielectric layer. The hydrophilic layer may be formed by exposing the dielectric layer to light having enough energy to break Si—C and C—C bonds but not enough to break Si—O bonds....

20060057839 - Method and apparatus for forming metal film: A metal film-forming method of the present invention can form a metal film having different film qualities in the thickness direction, in a continuous manner using a single processing solution. The metal film-forming method including: providing a substrate having embedded interconnects formed in interconnect recesses provided in a surface of...

20060057840 - Guard ring for improved matching: A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at...

20060057841 - Interconnection structure for ic metallization: A method for forming an interconnection structure in an integrated circuit includes the following steps. A dielectric layer is formed on a semiconductor substrate. An opening is formed on the dielectric layer. A barrier layer is formed over inner walls of the opening and the dielectric layer. A conductive layer...

20060057843 - Methods and apparatus for forming barrier layers in high aspect ratio vias: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of...

20060057842 - Ultra-thick metal-copper dual damascene process: Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via;...

20060057844 - Structure and method for enhanced uni-directional diffusion of cobalt silicide: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is...

20060057845 - Method of forming nickel-silicon compound, semiconductor device, and semiconductor device manufacturing method: There is disclosed a method of forming a nickel film on a silicon substrate or a silicon film, followed by applying an annealing process such that a final annealing temperature TH is in the range of 500° C.<TH≦600° C. to form a nickel-silicon compound, the method comprising a first annealing...

20060057849 - Apparatus and method for stripping silicon nitride: An apparatus and a metho