Semiconductor device manufacturing: process inventions 02/06

20060040414 - Methods of forming conductive materials: The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to release metal from the precursor, and subsequently the released metal is deposited over...

20060040413 - Pt/pgo etching process for feram applications: A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer...

20060040415 - Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring: An in situ dual-stage etch endpoint detection system is disclosed. The system includes an etch chamber, an interferometry endpoint monitoring system, and a non-IEP endpoint monitoring system. The etch chamber includes an electrostatic chuck (ESC), a top electrode, and a bottom electrode. The ESC is designed to support a wafer...

20060040416 - Method for manufacturing a light emitting device: A method for manufacturing an LED device includes the steps of mounting an LED on a substrate, sealing the LED with a transparent resin including phosphor particles to form an LED device before being dyed, measuring chromaticity of light from the LED device before being dyed; and dyeing the sealing...

20060040418 - Method of correcting amplitude defect in multilayer film of euvl mask: By entering a low acceleration Si ion beam of 500 V or lower or a low acceleration Si ion beam of 500 V-2000 V having been slanted such that an injection depth becomes shallow, which has been mass-separated from a liquid alloy ion source containing Si by a mass separator...

20060040417 - Method to build a wirebond probe card in a many at a time fashion: Resilient spring contacts for use in wafer test probing are provided that can be manufactured with a very fine pitch spacing and precisely located on a support substrate. The resilient contact structures are adapted for wire bonding to an electrical circuit on a space transformer substrate. The support substrates with...

20060040419 - Transflective lcd (liquid crystal display) panel and method of constructing the same: A transflective LCD panel includes a first substrate and a second electrode layer sandwiching a liquid crystal layer therebetween. Two first electrode layer are fabricated on the first substrate facing the second electrode layer. A metal layer fabricated on the first substrate is disposed between two of the first electrode...

20060040420 - Isfet using pbtio3 as sensing film: A PbTiO3/SiO2-gated ISFET device comprising a PbTiO3 thin film as H+-sensing film, and a method of forming the same. The PbTiO3 thin film is formed through a sol-gel process which offers many advantages, such as, low processing temperature, easy control of the composition of the film and easy coating over...

20060040423 - Attachment of integrated circuit structures and other substrates to substrates with vias: Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The...

20060040422 - Microelectronic devices and methods for manufacturing and operating packaged microelectronic device: Packaged microelectronic devices, methods for packaging microelectronic devices, and methods of operating microelectronic devices. In one embodiment, a packaged microelectronic device comprises a die including integrated circuitry, a first casing coating at least a portion of the die, a heat sink proximate to the die, and a second casing on...

20060040424 - Semiconductor device substrate, semiconductor device, and manufacturing method thereof: A method of manufacturing a semiconductor device substrate includes the steps of: arranging on a base a temporary fixing member for temporarily fixing an electronic component; temporarily fixing the electronic component on the base by the temporary fixing member; forming a substrate body on the base and the electronic component;...

20060040421 - Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers: Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors...

20060040425 - Circuit element and method of manufacturing the same: There is provided a circuit element using an organic semiconductor that maintains the characteristics of organic semiconductors in a stable manner for a long period, is highly durable against various kinds of stresses, impacts, etc. from outside and has excellent reliability. The circuit element comprises a circuit portion including an...

20060040426 - Circuitized substrate, method of making same and information handling system using same: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry,...

20060040427 - Multifunction electrode and method of making same: A transcutaneous electrode is disclosed having a sheet electrode of an electrically-conductive material with an electrically conductive layer affixed to a major portion of the lower surface thereof. A pad of electrically-conductive gel is applied to the lower surface of the sheet electrode over the electrically-conductive layer. An electrical conductor...

20060040428 - Conductive structures for microfeature devices and methods for fabricating microfeature devices: Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method...

20060040429 - Fabrication method of thin film transistor: The present invention provides a fabrication method of thin film transistor comprising a step of forming an amorphous silicon layer on a substrate, a step of forming a capping layer on the amorphous silicon layer, a step of forming a metal catalyst layer on the capping layer, a step of...

20060040431 - Supporting member for semiconductor elements, and method for driving supporting member for semiconductor elements: A support member for semiconductor device elements includes a conductive layer separated from the semiconductor elements by an insulative layer. A protective potential lower than any operating potential applied to the semiconductor device elements is applied to the conductive layer. The relatively negative potential on the conductive layer forms an...

20060040430 - System and method for integrating low schottky barrier metal source/drain: According to one embodiment of the invention, a method for integrating low Schottky barrier metal source/drain includes providing a substrate, forming an epitaxial SiGe layer outwardly from the substrate, forming an epitaxial Si layer outwardly from the SiGe layer, and forming a metal source and a metal drain....

20060040433 - Graded semiconductor layer: A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at...

20060040435 - Method for manufacturing semiconductor device: It is an object of the present invention to provide a method for manufacturing a substrate having film patterns such as an insulating film, a semiconductor film, and a conductive film in simple processes. It is another object of the invention to provide a method for manufacturing a semiconductor device...

20060040434 - Method of fabricating thin film transistor: A method of fabricating a thin film transistor includes preparing an insulating substrate; forming a first amorphous silicon layer on the substrate; forming a diffusion barrier layer pattern on the first amorphous silicon layer; forming a second amorphous silicon layer over the whole surface of the substrate; forming a metal...

20060040432 - Thin film trnsistor, method for producing a thin film transistor and electronic device having such a transistor: A thin film transistor (100) is mounted on a substrate (102), which is covered by a semiconductor layer (120). The semiconductor layer (120) has a first doped region (121) and a second doped region (122) with an undoped region (123) in between. In addition, the semiconductor layer (120) has a...

20060040436 - Method and apparatus forming crystallized semiconductor layer, and method for manufacturing semiconductor apparatus: A method for forming a crystallized semiconductor layer includes preparing a non-single-crystal semiconductor layer in which at least one crystal seed is formed, and irradiating with an energy ray the non-single-crystal semiconductor layer having the crystal seed formed therein to allow a crystal to laterally grow from the crystal seed...

20060040437 - Methods of forming field effect transistors: A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material and the semiconductive material. The space comprises an outermost portion and a portion immediately adjacent thereto. The outermost portion has...

20060040438 - Method for improving the thermal stability of silicide: An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110. The method may include forming an interface layer 200 over the semiconductor substrate 20 and performing an anneal to create a silicide 190 on the top surface...

20060040439 - Temperature stable metal nitride gate electrode: An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W,...

20060040440 - Nand flash memory cell row and manufacturing method thereof: A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. Each of...

20060040441 - Method of forming an integrated circuit employable with a power converter: A method of forming an integrated circuit employable with a power converter. In one embodiment, the method of forming the integrated circuit includes forming a transistor employable as a switch of a power train of the power converter by forming a gate over a semiconductor substrate. The method of forming...

20060040442 - Bump inspection apparatus and method for ic component, bump forming method for ic component, and mounting method for ic component: Unidirectional light is irradiated onto a bump-formation surface of an IC component to acquire a first overall image of the IC component, light is irradiated onto the bump-formation surface in respective inclined directions to acquire a second overall image, first bump inspection images are respectively acquired from the first overall...

20060040444 - Method for fabricating a three-dimensional capacitor: A capacitor and a method of fabricating the capacitor are provided herein. The capacitor can be formed by forming two or more dielectric layers and a lower electrode, wherein at least one of the two or more dielectric layers is formed before the lower electrode is formed....

20060040443 - Methods of forming capacitor electrodes using fluorine and oxygen: A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode....

20060040445 - Capacitor having a dielectric layer that reduces leakage current and a method of manufacturing the same: A capacitor having a dielectric layer including a composite oxide, the composite oxide including a transition metal and including a lanthanide group element, a memory device including the same and a method of manufacturing the capacitor are provided. The transition metal may be titanium and the composite oxide may be...

20060040446 - Method for manufacturing interpoly dielectric: Roughly described, a floating gate memory cell is fabricated by forming an oxide-nitride dielectric layer above a floating gate of the memory cell and in an oxide growth region not above a floating gate. The nitride layer is removed in the oxide growth region using a mask that protects the...

20060040447 - Nand memory arrays and methods: NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory...

20060040448 - Method for fabricating a semiconductor device having improved hot carrier immunity ability: The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive...

20060040449 - Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein: A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by...

20060040451 - Method of forming an integrated circuit employable with a power converter: A method of forming an integrated circuit employable with a power converter. In one embodiment, the method of forming the integrated circuit includes forming a power switch of a power train of the power converter on a semiconductor substrate, and forming a driver switch of a driver configured to provide...

20060040452 - Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein: A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a switch on a semiconductor substrate, and forming a driver switch of a driver embodied in a transistor. The method of forming...

20060040450 - Source/drain structure for high performance sub 0.1 micron transistors: An asymmetric transistor structure comprising a gate structure with a drain halo ion implantation region, without any halo ion implantation region source region is provided. Methods of forming a transistor structure are also provided. An angled halo ion implant is preformed at an angle using ions of the same type...

20060040453 - Bipolar transistor: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region,...

20060040455 - Methods of forming integrated circuits, and dram circuitry memory cells: This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation mask defines an active area region and a trench isolation region. An ion...

20060040454 - Semiconductor devices having dram cells and methods of fabricating the same: A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patterns are disposed on the bit...

20060040456 - Method for the production of a bipolar semiconductor component, especially a bipolar transistor, and corresponding bipolar semiconductor component: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component. The inventive method comprises the following steps: a first semiconductor area (32, 34) of a first conductivity type (p) is provided above a semiconductor substrate (1); a connecting...

20060040457 - Methods of forming low leakage currents metal-insulator-metal (mim) capacitors and related mim capacitors: Methods of forming MIM comprise forming a lower electrode on a semiconductor substrate, forming a lower dielectric layer on the lower electrode, and forming an upper dielectric layer on the lower dielectric layer. The lower dielectric layer may be formed of dielectrics having larger energy band gap than that of...

20060040458 - Method to produce thin film resistor using dry etch: A method of fabricating a thin film resistor (100). The resistor material (104), e.g., NiCr, is deposited. A hard mask material (106), e.g., TiW, may be deposited over the resistor material (104). The resistor material (104) and hard mask material (106) are patterned and sputter etched to form the resistor...

20060040459 - Method to produce thin film resistor with no resistor head using dry etch: A method of fabricating a thin film resistor (100) without a hardmask or resistor head. The resistor material (104), e.g., NiCr, is deposited. The resistor material (104) is patterned and sputter etched to form the resistor body without first depositing a hardmask material. For example, a sputter etch chemistry comprising...

20060040460 - Mis capacitor and production method of mis capacitor: Silicon wafer, with diffusion area formed in a predetermined area of one side, consists of the lower electrode of capacitor. The first metal layer is connected to the first power supply wiring VDD and consists of the upper electrode of capacitor. The second metal layers are connected to the second...

20060040461 - Method of forming a capacitor: The present invention relates to a method for fabricating a capacitor employing ALD-TiN as an upper electrode and being suitable for preventing a deterioration of a leakage current property which uses an ALD-TiN as an upper electrode. The method for fabricating the capacitor includes: forming a lower electrode on a...

20060040463 - Manufacturing method of an electronic part built-in substrate: A manufacturing method of an electronic part built-in substrate is disclosed, wherein an electronic part is contained in a build-up layer, the manufacturing method including a step for arranging an electronic part on a conductive supporting object such that the electronic part is electrically connected to the conductive supporting object,...

20060040462 - Novel method to improve sram performance and stability: A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps...

20060040464 - Semiconductor device and method for fabricating the same: A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate,...

20060040465 - Methods of forming conductive lines and methods of forming conductive contacts adjacent conductive lines: This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative material over a semiconductive substrate. The conductive line is laterally spaced...

20060040466 - Methods of forming integrated circuits, and dram circuitry memory cells: This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation mask defines an active area region and a trench isolation region. An ion...

20060040468 - Method for transferring a semiconductor body from a growth substrate to a support material: A method for transferring a semiconductor body selected from the group consisting of a semiconductor layer, a semiconductor layer sequence or a semiconductor layer structure from a growth substrate to a support material. An interface between the growth substrate and the semiconductor body or a region in the vicinity of...

20060040467 - Process and apparatus for thinning a semiconductor workpiece: The present invention provides system and apparatus for use in processing wafers. The new system and apparatus allows for the production of thinner wafers that at same time remain strong. As a result, the wafers produced by the present process are less susceptible to breaking. The unique system also offers...

20060040470 - Methods for minimizing defects when transferring a semiconductor useful layer: A method for minimizing defects when transferring a useful layer from a donor wafer to a receptor wafer is described. The method includes providing a donor wafer having a surface below which a zone of weakness is present to define a useful layer to be transferred, molecularly bonding at a...

20060040469 - Soi wafer manufacturing method: In order to adjust thickness of a bonded silicon single crystal film 15 depending of thickness of an SOI layer 5 to be obtained, depth of formation d1+tx of a separatory ion implanted layer 4, measured from a first main surface J, in the separatory ion implanted layer formation step...

20060040471 - Method of forming vias on a wafer stack using laser ablation: Disclosed are various embodiments of a method of forming vias for backside connections in a wafer stack, wherein the vias are formed by non-thermal laser ablation. Other embodiments are described an claimed....

20060040472 - Method for separating semiconductor substrate: A method of separating a semiconductor substrate having an implementation member attached thereon includes a dividing process for at least the implementation member on the semiconductor substrate along a separation line, a placing process for film member on a same side as the implementation member, a forming process area by...

20060040473 - Laser processing method and laser processing apparatus: A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface...

20060040474 - Low oxygen content photoresist stripping process for low dielectric constant materials: A plasma containing 5-10% oxygen and 90-95% of an inert gas strips photoresist from over a low-k dielectric material formed on or in a semiconductor device. The inert gas may be nitrogen, hydrogen, or a combination thereof, or it may include at least one of nitrogen, hydrogen, NH3, Ar, He,...

20060040475 - Multi-chamber mocvd growth apparatus for high performance/high throughput: In one embodiment the present invention is a method of conducting multiple step multiple chamber chemical vapor deposition while avoiding reactant memory in the relevant reaction chambers. The method includes depositing a layer of semiconductor material on a substrate using vapor deposition in a first deposition chamber followed by evacuation...

20060040476 - Patterning soi with silicon mask to create box at different depths: The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material,...

20060040477 - Method and apparatus for forming expitaxial layers: The present invention provides a method of depositing epitaxial layers based on Group IV elements on a silicon substrate by Chemical Vapor Deposition, wherein nitrogen or one of the noble gases is used as a carrier gas, and the invention further provides a Chemical Vapor Deposition apparatus (10) comprising a...

20060040479 - Method of making semiconductor devices: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed...

20060040478 - Method of producing a calibration wafer: A method of producing a calibration wafer having at least a predetermined emissivity, including providing a wafer of semiconductor material; subjecting the bulk material of the wafer to doping with foreign atoms and/or generating lattice defects to obtain the predetermined emissivity; and coating the wafer to obtain a further optical...

20060040480 - Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic layer deposition...

20060040481 - Methods and structures for preventing gate salicidation and for forming source and drain salicidation and for forming semiconductor device: Methods and structures for preventing salicidation are disclosed. A substrate has an gate electrode on it. Spacers are on sidewalls of the gate electrode, exposing a top portion of the gate electrode. A dielectric layer is formed above the spacers, covering the exposed top portion of the gate electrode. Methods...

20060040482 - Mos transistor and fabrication thereof: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and...

20060040483 - Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing: A method and system for modifying a gate dielectric stack by exposure to a plasma. The method includes providing the gate dielectric stack having a high-k layer formed on a substrate, generating a plasma from a process gas containing an inert gas and one of an oxygen-containing gas or a...

20060040484 - Apparatus and method for staircase raised source/drain structure: A structure, apparatus and method for improving the performance of semiconductor devices is provided. The semiconductor structure includes a raised source/drain region above a planar source/drain. The raised source/drain has at least a first step and a second step with a variety of transitions therebetween. The first step is of...

20060040486 - Method of depositing noble metal electrode using oxidation-reduction reaction: Provided is a method of depositing a noble metal layer using an oxidation-reduction reaction. The method includes flowing a noble metal source gas, an oxidizing gas, and a reducing gas into a reaction chamber; and generating plasma in the reaction chamber to form a noble metal layer or a noble...

20060040488 - Method of electrically connecting a microelectronic component: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first...

20060040485 - Method of forming via structures and method of fabricating phase change memory devices incorporating such via structures: Provided are methods for forming conductive plug structures, such as via plugs, from a plurality of conductive layer patterns and methods of fabricating semiconductor devices, including semiconductor memory devices such as phase change semiconductor memory devices. An example method forms a small via structure by forming a conductive layer on...

20060040487 - Semiconductor device, method for manufacturing the same, and plating solution: The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device has an embedded interconnect structure in which an electric conductor, such as copper or silver, is embedded in fine recesses formed in a surface of a semiconductor substrate, and also has a...

20060040489 - Multi-layered structure forming method, method of manufacturing wiring substrate, and method of manufacturing electronic apparatus: There is provided a multi-layered structure forming method comprising: (A) forming a first insulating material layer containing a first photo-curing material on a substrate; (B) semi-hardening the first insulating material layer by radiating light having a first wavelength to the first insulating material layer; (C) forming a conductive material layer...

20060040490 - Method of fabricating silicon carbide-capped copper damascene interconnect: A dielectric layer overlying a substrate is prepared. A damascene opening is etched into the dielectric layer. The damascene opening is filled with copper or copper alloy. A surface of the copper or copper alloy is treated with hydrogen-containing plasma such as H2 or NH3 plasma. The treated surface of...

20060040491 - Slot designs in wide metal lines: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that...

20060040492 - Formation of air gaps in an interconnect structure using a thin permeable hard mask and resulting structures: A method of forming air gaps in the interconnect structure of an integrated circuit device. The air gaps may be formed by depositing sacrificial layer over a dielectric layer and then depositing a permeable hard mask over the sacrificial layer. The sacrificial layer is subsequently removed to form air gaps....

20060040493 - Iridium etching for feram applications: A method of etching an iridium layer for use in a ferroelectric device includes preparing a substrate; depositing a barrier layer on the substrate; depositing an iridium layer on the barrier layer; depositing a hard mask layer on the iridium layer; depositing, patterning and developing a photoresist layer on the...

20060040494 - Through-hole conductors for semiconductor substrates and method for making same: A method, structure and system for forming a through-hole conductor in a substrate includes forming a hole having an inner surface from a first side of the semiconductor substrate to a second side of the semiconductor substrate and plating the inner surface of the semiconductor substrate to form a conductive...

20060040495 - Deposition method of tin film having a multi-layer structure: Provided is a method of depositing a metal nitride film having a multilayer structure and different deposition speeds on a substrate. The method is performed by forming a first lower metal nitride film on the substrate at a first deposition speed, forming a second lower metal nitride film on the...

20060040497 - Material for contact etch layer to enhance device performance: Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to...

20060040496 - Method of forming a material film: A method of forming a material film is provided. A chemical vapor deposition (CVD) chamber including therein a showerhead coupled to a gas source and a pedestal coupled to a heater is provided. The showerhead is coupled to a radio frequency (RF) power source. A substrate is positioned on the...

20060040498 - Method for manufacturing dual damascene structure with a trench formed first: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer...

20060040499 - In situ surface contaminant removal for ion implanting: Methods and apparatus that introduce, within the ion implant chamber or an isolated chamber in communication therewith, the capability to remove contaminants and oxide surface layers on a wafer surface prior to ion implantation, are disclosed. The mechanisms for removal of contaminants include conducting: a low energy plasma etch, heating...

20060040500 - Nitride semiconductor chip and method for manufacturing nitride semiconductor chip: A method for manufacturing a nitride semiconductor device in which nitride crystals are sequentially grown on a substrate such as sapphire by MOCVD or the like, and p electrode and n electrode are formed. The wafer is not cut along two perpendicular directions, but rather is cut along two directions...

20060040501 - Integrated dual damascene rie process with organic patterning layer: A dual damascene conductor structure is formed on a substrate with an exposed conductor on top covered by a buried cap, a dielectric layer (DL) and an organic layer (OL). Form trench patterning hard mask and via hard mask layers over the OL. Form a trench pattern hole through the...

20060040502 - Method for manufacturing semiconductor device: A wiring material film is formed by depositing a first conductive barrier film, an aluminum film, and a second conductive barrier film on a semiconductor substrate in this order. An organic material film, a silicon oxide film and a resist film are formed on the surface of the second barrier...

20060040503 - Process for fabricating a strained channel mosfet device: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used...

20060040504 - Photoresist trimming process: A photoresist trimming gas compound is provided which will selectively remove a resist foot or scum from the lower portions of sidewalls of a photoresist. Additionally, the trimmer compound hardens or toughens an upper surface of the photoresist thereby strengthening the photoresist. The trimmer compound includes O2 and at least...

20060040505 - Method for manufacturing a micro-electromechanical device and micro-electromechanical device obtained therewith: The invention relates to a method of manufacturing a micro-electromechanical device (10), in which are consecutively deposited on a substrate (1) a first electroconductive layer (2) in which an electrode (2A) is formed, a first electroinsulating layer (3) of a first material, a second electroinsulating layer (4) of a second...

20060040506 - Semiconductor fabrication methods and apparatus: Methods and apparatus for fabricating and cleaning in-process semi-conductor wafers are provided. An in-process wafer is placed within a closed chamber. A reactant gas is incorporated in a liquid solvent to form a “reactant mixture” that is capable of reacting with photoresist material for other material) on a wafer surface...

20060040507 - Method for depositing porous films: A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon to form a porous structure. In a preferred embodiment, the codeposition is carried out by plasma enhanced...

20060040508 - Method to protect internal components of semiconductor processing equipment using layered superlattice materials: This invention relates to apparatus and a method to protect the internal components of semiconductor processing equipment such as a plasma reactor or a reactive species generator against physical and/or chemical damages during etching and/or cleaning processes. Layered superlattice materials having three or more metal elements such as strontium bismuth...

20060040509 - Composition for preparing nanoporous material: Disclosed herein is a composition for preparing a nanoporous material. The composition comprises i) a cyclodextrin derivative, ii) a thermostable matrix precursor, and iii) a solvent for dissolving the components i) and ii). The composition enables the preparation of a low dielectric constant film in which nanopores with a size...

20060040510 - Semiconductor device with silicon dioxide layers formed using atomic layer deposition: Improved methods are disclosed for catalyst-assisted atomic layer deposition (ALD) to form a silicon dioxide layer having superior properties on a semiconductor substrate by using a first reactant component consisting of a silicon compound having at least two silicon atoms, or using a tertiary aliphatic amine as the catalyst component,...

20060040511 - [method of fabricating shallow trench isolation structure for reducing wafer scratch]: A method of fabricating a shallow trench isolation structure for reducing wafer scratch reducing scratch on a wafer surface is provided. A parameter of a processing operation is controlled in a manner to reduce an amassment of material over the wafer surface. Thus, a step height from the surface of...

20060040513 - Duv laser annealing and stabilization of sicoh films: A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties...

20060040512 - Single-shot semiconductor processing system and method having various irradiation patterns: High throughput systems and processes for recrystallizing thin film semiconductors that have been deposited at low temperatures on a substrate are provided. A thin film semiconductor workpiece is irradiated with a laser beam to melt and recrystallize target areas of the surface exposed to the laser beam. The laser beam...

20060040514 - Magnetic processing of electronic materials: The electronic properties (such as electron mobility, resistivity, etc.) of an electronic material can be modified/enhanced when subjected to dynamic or stationary magnetic fields in conjunction with select cycles of heating, cooling and passage of electric current through the material. This “processing” includes one or more cycles using combinations of...

20060035390 - Seed layer processes for mocvd of ferroelectric thin films on high-k gate oxides: A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed...

20060035391 - Manufacturing method of array substrate and manufacturing method of liquid crystal display device using the same: The invention relates to a manufacturing method of an array substrate used for a reflective or transflective liquid crystal display device and a manufacturing method of a liquid crystal display device using the same, and has an object to provide the manufacturing method of the array substrate in which the...

20060035392 - Application of lignin derivatives to photoelectric transducer and photoelectrochemical cell: The invention regards application of lignin derivatives to a photoelectric transducer. The photoelectric transducer of the invention includes a semiconductor film as a thin film electrode, that is photosensitized by one or multiple lignin derivatives selected from the group consisting of: (a) a lignophenol derivative or a phenol derivative of...

20060035394 - Method for improving a drive current for semiconductor devices on a wafer-by-wafer basis: The present invention provides a method for manufacturing semiconductor devices, a method for manufacturing an integrated circuit, and a method for improving a drive current for semiconductor devices on a wafer-by-wafer basis. The method for manufacturing semiconductor devices, among other elements, includes patterning gate structures on a substrate (220), each...

20060035393 - Methods for the determination of film continuity and growth modes in thin dielectric films: The invention provides methods for determining film continuity and growth modes in thin dielectric films. The continuity determining method comprises: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage...

20060035395 - Process endpoint detection method using broadband reflectometry: A method of determining a parameter of interest during processing of a patterned substrate includes obtaining a measured net reflectance spectrum resulting from illuminating at least a portion of the patterned substrate with a light beam having a broadband spectrum, calculating a modeled net reflectance spectrum as a weighted incoherent...

20060035396 - Semiconductor device manufacturing apparatus and a method of controlling a semiconductor device manufacturing process: A particle monitor in the process chamber of a semiconductor device manufacturing apparatus provides a measure of a flux of contaminant particles in the chamber. The flux is measured whilst process conditions are produced in the process chamber and a process parameter is adjusted in response to the measured flux...

20060035397 - Flat panel display device and method of manufacturing the same: A flat panel display includes a pixel electrode having an opening portion formed on an insulating substrate, a semiconductor layer formed over a surface of the insulating substrate, spaced apart from the pixel electrode, having source and drain regions formed to both end portions thereof, a first insulating layer formed...

20060035398 - Fabrication method of transparent electrode on visible light-emitting diode: A method for forming a transparent electrode on a visible light-emitting diode is described. A visible light-emitting diode element is provided, and the visible light-emitting diode element has a substrate, an epitaxial structure and a metal electrode. The metal electrode and the epitaxial structure are located on the same side...

20060035399 - Process for making stacks of islands made of one semiconducting material encapsulated in another semiconducting material: The invention relates to the product ion of a stacked structure of planes of islands of a first semiconducting material encapsulated in a second semiconducting material on a substrate, comprising alternate deposition of planes of islands of a first semiconducting material and encapsulation layers of a second semiconducting material, the...

20060035400 - Apparatus of ion sensitive thin film transistor and method of manufacturing of the same: The present invention discloses an apparatus of ion sensitive thin film transistor and method of manufacturing of the same. The apparatus of the invention, formed on a glass substrate, comprises an ion detector, formed on said glass substrate, including a plurality of ion sensitive transistors and a signal processor with...

20060035401 - Solid state image pickup device capable of suppressing smear: A driving method for a solid state image pickup device, having four or more transfer stages as one transfer unit, includes reading signal charge from the charge accumulation regions to the vertical charge transfer channels. The reading step includes (b-1) applying the barrier forming voltage to a first transfer electrode...

20060035402 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method for manufacturing a plurality of microelectronic imaging units includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include a...

20060035403 - Pcram device with switching glass layer: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method....

20060035404 - Method for manufacturing an electronic device having an electronically determined physical test member: A method for manufacturing an electronic device such as an integrated circuit or display device is provided. A design description of the electronic device is generated using a computer aided design tool. Physical device data representing a physical description of the electronic device are electronically determined based on the design...

20060035405 - Methods of manufacturing a thin film including hafnium titanium oxide and methods of manufacturing a semiconductor device including the same: The present invention can provide methods of manufacturing a thin film including hafnium titanium oxide. The methods can include introducing a first reactant including a hafnium precursor onto a substrate; chemisorbing a first portion of the first reactant to the substrate, and physisorbing a second portion of the first reactant...

20060035406 - Method of forming a composite polymer material inside trenches of a semiconductor substrate to form a composite polymer structure: A semiconductor substrate structure includes a substrate having a trench formed thereon, a polymer composite material supplied into the trench and an electroplate conductive layer formed on the substrate. Further, a semiconductor substrate processing method includes the steps of: providing a substrate forming a trench thereon, supplying a polymer composite...

20060035408 - Methods for designing spacers for use in stacking semiconductor devices or semiconductor device components: A method for designing a spacer to be used in a stacked multi-chip module includes configuring a spacer layer that is nonconfluent or includes voids. The spacer layer is configured to at least partially space the surface of the semiconductor device apart from another semiconductor device assembled in stacked arrangement...

20060035407 - Semiconductor substrate structure and processing method thereof: A semiconductor substrate structure includes a substrate having a trench formed thereon, a polymer composite material supplied into the trench and an electroplate conductive layer formed on the substrate. Further, a semiconductor substrate processing method includes the steps of: providing a substrate forming a trench thereon, supplying a polymer composite...

20060035409 - Methods and apparatuses for providing stacked-die devices: Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and associated wires are protected by an encapsulant leaving an upper portion of each...

20060035410 - Solderless component packaging and mounting: An apparatus and method for providing three-dimensional carrier mounting of one or more electronic components. In accordance with one embodiment, the device mounting apparatus of the present invention includes an elastically resilient plastic substrate having component mounting surfaces in at least two dimensions. At least one press-fit component insertion cavity...

20060035411 - Laser processing method: A laser processing method for forming a laser groove along dividing lines by applying a pulse laser beam along the dividing lines formed on a workpiece, the method comprising the steps of forming the focusing spot of the pulse laser beam in a shape of oval, positioning the long axis...

20060035412 - Semiconductor attachment method: An improved semiconductor attachment method that works with mixed assemblies on printed circuit boards or ceramic substrates maintains reliability and reduces the amount of lead-based solders used. A soft solder layer, which may be high in lead content, is deposited on the terminations of a semiconductor die. The soft solder...

20060035413 - Thermal protection for electronic components during processing: A method and device for cooling an electronic component during its manufacture, repair, or rework. There is a cooling unit in thermal communication with the electronic component which extracts heat therefrom....

20060035414 - Process and lead frame for making leadless semiconductor packages: A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to...

20060035415 - Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages: A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment....

20060035416 - Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities: A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330)...

20060035419 - Low temperature curable materials for optical applications: The invention relates to low temperature curable spin-on glass materials which are useful for electronic applications, such as optical devices. A substantially crack-free and substantially void-free silicon polymer film is produced by (a) preparing a composition comprising at least one silicon containing pre-polymer, a catalyst, and optionally water; (b) coating...

20060035418 - Method for fabricating semiconductor device: First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings,...

20060035417 - Semiconductor device and method for forming the same: The present invention is related to semiconductor device and method for manufacturing the same. In accordance with the semiconductor device and method for manufacturing the same, at least one opening extending between LDD regions and exposing a buried insulating layer is formed so that a gate electrode surrounds the surface...

20060035420 - Ion-sensitive field effect transistor and method for producing an ion-sensitive field effect transistor: An ion-sensitive field effect transistor includes a substrate on which there are formed a source region and a drain region. Above a channel region, the ion-sensitive field effect transistor has a gate with a sensitive layer including a metal oxide nitride mixture and/or a metal oxide nitride mixture compound....

20060035421 - Semiconductor device and method therefore: Where the silicon active layer of an SOI substrate is used as a resistor, it is difficult to form small wells densely in a semiconductor support substrate portion under the resistor because of the presence of a buried insulation film. It is also difficult to control the potential division of...

20060035422 - Integrated pet and schottky device: A semiconductor device including a schottky device and a trench type semiconductor switching device such as a MOSFET formed in a common die....

20060035424 - Electrically alterable non-volatile memory cell: A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region....

20060035423 - Organic electronic component comprising the same organic material for at least two functional layers: The present invention describes an organic electronic component, such as an organic field effect transistor (OFET), in which a single organic material serves for at least two functional layers, for example as conductive and as semiconductive functional material. Moreover, the invention describes an efficient method for producing, in one process...

20060035425 - Application of gate edge liner to maintain gate length cd in a replacement gate transistor flow: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove...

20060035426 - Method and apparatus for polysilicon resistor formation: Some embodiments of the present invention include implanting and annealing polysilicon lines to form a silicide blocking layer that may inhibit silicide formation. The silicide blocking layer may facilitate fabrication of polysilicon resistors....

20060035427 - Semiconductor device and method for fabricating the same: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of...

20060035428 - Dynamic random access memory cell and fabricating method thereof: A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed...

20060035429 - Methods of forming phase-change random access memories including a confined contact hole and integrated circuit devices including the same: Methods of forming a phase-change random access memory (PRAM) include forming a lower electrode layer and a node insulating layer on an active region of a semiconductor substrate. A photoresist pattern is formed on the node insulating layer that includes an opening therein. A polymer layer is formed on the...

20060035430 - Fabrication method for a trench capacitor having an insulation collar: The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of: providing a trench (5) in the silicon substrate (1); providing the insulation collar (10) in the upper trench region as far as the top side...

20060035431 - Memory cell with reduced dibl and vss resistance: According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises...

20060035432 - Method of fabricating non-volatile memory device having local sonos gate structure: in methods of fabricating a non-volatile memory device having a local silicon-oxide-nitride-oxide-silicon (SONOS) gate structure, a semiconductor substrate having a cell transistor area, a high voltage transistor area, and a low voltage transistor area, is prepared. At least one memory storage pattern defining a cell gate insulating area on the...

20060035433 - Non-volatile memory devices and methods for driving the same: Non-volatile memory devices and methods for driving the same are disclosed. An example non-volatile memory device includes a semiconductor substrate; source/drain junctions in a predetermined region of the semiconductor substrate; a main gate oxide layer above a surface of the semiconductor substrate and disposed between the source/drain junctions, a first...

20060035434 - Longitudinal misfet manufacturing method, longitudinal misfet, semiconductor storage device manufacturing method, and semiconductor storage device: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current...

20060035435 - Semiconductor device and manufacturing method for semiconductor device to reduce the lithography masks: Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed...

20060035436 - Method for producing an n-doped field stop zone in a semiconductor body and semiconductor component having a field stop zone: A method for producing an n-doped field stop zone in a semiconductor body. The method includes carrying out a diffusion process for the indiffusion of sulfur, hydrogen or selenium proceeding from one side into the semiconductor body in order to produce a first n-doped semiconductor zone. A second n-doped semiconductor...

20060035437 - Semiconductor device having dual-sti and manufacturing method thereof: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a...

20060035438 - Method and resulting structure for manufacturing semiconductor substrates: A method of manufacturing bonded substrates. The method includes providing a metallic substrate. The metal substrate has a predetermined thickness. The method also includes bonding a first thickness of compound semiconductor material overlying the metallic substrate and reducing a thickness of the first thickness of compound semiconductor material to a...

20060035440 - Method for manufacturing a free-standing substrate made of monocrystalline semiconductor material: A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support....

20060035439 - Method of forming a micromechanical structure: A method of forming a micromechanical structure, wherein at least one micromechanical structural layer is provided above a substrate. The micromechanical structural layer is sustained between a lower sacrificial silicon layer and an upper sacrificial silicon layer, wherein a metal silicide layer is formed between the lower and upper sacrificial...

20060035442 - Layer arrangement and process for producing a layer arrangement: In a process for producing a layer arrangement, a first layer is formed with a thickness on a first side of a substrate, which thickness is greater than a minimum thickness for epitaxial growth, a second layer is epitaxially grown on the first layer, and a third layer is formed...

20060035441 - Method for processing a thin semiconductor substrate: A method for processing a semiconductor substrate less than 200 μm thick has been provided. The substrate has one or a plurality of semiconductor elements, which may be identical or different. The substrate is arranged onto a chuck during processing, the front side of the substrate facing the chuck. During...

20060035443 - Partial wafer bonding and dicing: Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness...

20060035444 - Wafer dividing method: A method of dividing a wafer having a plurality of dividing lines formed on the front surface in a lattice pattern and function elements formed in a plurality of areas sectioned by the plurality of dividing lines into individual chips, along the dividing lines, the method comprising the steps of...

20060035445 - Method of reducing the surface roughness of a semiconductor wafer: The invention provides a method for reducing the roughness of a free surface of a semiconductor wafer that includes removing material from the free surface of the wafer to provide a treated wafer, and performing a first rapid thermal annealing on the treated wafer in a pure argon atmosphere to...

20060035446 - Apparatus of catalytic molecule beam epitaxy and process for growing iii-nitride materials using the apparatus: This invention relates to an apparatus of catalytic molecule beam epitaxy (cat-MBE) and process for growing Group III nitride materials using thereof, characteristically in that said apparatus is equipped with a hot wire to catalytically decompose gaseous ammonium or nitrogen molecule into activated nitrogen radicals as the nitrogen source for...

20060035447 - Semiconductor substrate and manufacturing method for the same: A method of manufacturing a semiconductor substrate includes a growing step of growing a second single crystalline semiconductor on a first single crystalline semiconductor, a blocking layer forming step of forming a blocking layer on the second single crystalline semiconductor, and a relaxing step of generating crystal defects at a...

20060035448 - Process for producing doped semiconductor wafers from silicon, and the wafers produced thereby: A process for producing doped semiconductor wafers from silicon, which contain an electrically active dopant, such as boron, phosphorus, arsenic or antimony, optionally are additionally doped with germanium and have a defined thermal conductivity, involves producing a single crystal from silicon and processing further to form semiconductor wafers, the thermal...

20060035449 - Method of forming ultra shallow junctions: A method of forming ultra shallow junctions in p-type devices uses aluminum ion to implant n-doped silicon, followed a low temperature anneal to activate and diffuse the aluminum. The use of aluminum provides numerous advantages over boron such as the ability to form shallower junctions, lower resistivity, and the ability...

20060035450 - Semiconductor-dielectric-semiconductor device structure fabricated by wafer bonding: A method of forming a gate stack for semiconductor electronic devices utilizing wafer bonding of at least one structure containing a high-k dielectric material is provided. The method of the present invention includes a step of first selecting a first and second structure having a major surface respectively. In accordance...

20060035451 - High-density soi cross-point memory fabricating method: A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method comprises: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas, and top electrode areas; etching to remove the exposed silicon (Si) surfaces; selectively forming metal...

20060035452 - Transparent oxide semiconductor thin film transistor: This invention relates to novel, transparent oxide semiconductor thin film transistors (TFT's) and a process for making them....

20060035453 - Method of forming a solder ball on a board and the board: In the method, a conductive pad of the board is etched to a depth that is greater than 50% and less than 100% of a thickness of the conductive pad. Subsequently, a solder ball may be formed on the etched conductive pad. For example, the conductive pad may be copper....

20060035454 - Fluxless solder transfer and reflow process: Disclosed is a new process that permits the transfer and reflow of solder features produced by Injection Molded Solder (IMS) from a mold plate to a solder receiving substrate without the use of flux. Several embodiments produce solder transfer and reflow separately or together and use either formic acid vapor...

20060035455 - Interconnect dielectric tuning: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all...

20060035456 - Method and apparatus for deep sub-micron design of integrated circuits: A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the IC...

20060035457 - Interconnection capacitance reduction: An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low...

20060035458 - Semiconductor element: The invention relates to a semiconductor component having a semiconductor body (1), to which a metallization (10), which is formed from metallization layers (11, 13, 15, 17) and separating layers (12, 14, 16, 18) arranged alternately in succession, a dielectric (2) and a molding compound (3) joined to the dielectric...

20060035459 - Method of forming narrowly spaced flash memory contact openings and lithography masks: A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the...

20060035460 - Wiring structure for integrated circuit with reduced intralevel capacitance: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The...

20060035461 - Copper line of semiconductor device and method for forming the same: A copper line on a semiconductor device and a method for forming the same is disclosed, wherein an insulating layer is deposited so as to minimize the dishing of IMD without using a dummy area when performing the planarization process. The method of forming the copper line on the semiconductor...

20060035462 - Systems and methods for forming metal-containing layers using vapor deposition processes: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more homoleptic and/or heteroleptic precursor compounds that include, for example, guanidinate, phosphoguanidinate, isoureate, thioisoureate,...

20060035463 - Treatment of silicon prior to nickel silicide formation: A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to...

20060035464 - Method of planarizing a semiconductor substrate: The present invention provides a method of planarizing a substrate, the method including, forming, on the substrate, a patterned layer having a first shape associated therewith; and processing the patterned layer, with the first shape compensating for variations in the processing such that upon processing the patterned layer, the patterned...

20060035465 - Methods for reducing a thickness variation of a nitride layer formed in a shallow trench isolation cmp process and for forming a device isolation film of a semiconductor device: A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at an ISO level, and...

20060035466 - Method for manufacturing plasma display panels: A method for manufacturing a plasma display panel including a dielectric layer that is formed by a vapor deposition method and covers electrodes except their terminal portions, includes the steps of depositing a dielectric on a substrate on which each of the electrodes having a terminal portion at an end...

20060035467 - Method for etching mesa isolation in antimony-based compound semiconductor structures: Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30-42) formed over the substrate structure (10) are dry etched to form device mesas (12) and the buffer cap (26) provides a desirably smooth...

20060035468 - Semiconductor device and method for producing the same: The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying...

20060035469 - Methods for forming an undercut region and electronic devices incorporating the same: An electronic device having a substrate structure having an undercut region is provided and further included is a method for forming an undercut region of a substrate structure. The method includes forming a patterned protective layer over a first electrode. The method also includes forming the substrate structure over the...

20060035472 - Master base for fabrication and method for manufacturing the same: A master base for fabrication includes a substrate, a first photoresist layer disposed on the substrate, and a second photoresist layer disposed on the first photoresist layer, wherein the first photoresist layer attenuates or absorbs rays reflected at the interface between the first photoresist layer and the substrate to prevent...

20060035470 - Method for manufaturing semiconductor device and substrate processing system: To improve throughput of a substrate processing without wastefully using a source as a reactant by repeating supply steps of a plurality of reactants for a plurality of times. A substrate processing apparatus includes a source gas obtained by vaporizing a liquid source as a reactant, and functions to process...

20060035471 - Method of depositing a silicon dioxide comprising layer doped with at least one of p, b and ge: A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over at least two different time periods and under conditions...

20060035473 - Method for stabilizing high pressure oxidation of a semiconductor device: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an...

20060035474 - Increasing retention time for memory devices: This disclosure relates to a doped polymer memory device. In one aspect the doped polymer memory device includes a molecularly doped polymer layer that includes a binder and a dopant. The combination of the binder and the dopant modifies polarizability of the molecularly doped polymer layer in a manner that...

20060035476 - Method to fill the gap between coupled wafers: A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one of...

20060035475 - Semiconductor substrate processing apparatus: According to one aspect of the invention, a semiconductor substrate processing apparatus and a method for processing semiconductor substrates are provided. The semiconductor substrate processing apparatus may include a semiconductor substrate support, a dispense head positioned over the semiconductor substrate support, a liquid container, and a transport subsystem. A semiconductor...

20060035477 - Methods and systems for rapid thermal processing: Methods for rapid thermal processing of semiconductor substrates are provided. An exemplary method comprises directing radiant heat energy emitted from a heat source toward a backside surface of the semiconductor substrate. Systems for rapid thermal processing also are provided....

20060035478 - Variable mask device for crystallizing silicon layer and method for crystallizing using the same: Disclosed are a variable mask device for crystallizing a silicon layer capable of controlling a width and a length of an opening, and a method for crystallizing a silicon using the variable mask device. The variable mask device has a frame with an opening whose width is controlled by an...

20060030058 - High speed low power magnetic devices based on current induced spin-momentum transfer: The present invention generally relates to the field of magnetic devices for memory cells that can serve as non-volatile memory. More specifically, the present invention describes a high speed and low power method by which a spin polarized electrical current can be used to control and switch the magnetization direction...

20060030057 - Insulating film, capacitive element and semiconductor storage device including the insulating film, and fabrication methods thereof: A capacitive element comprises: a lower electrode formed above a semiconductor substrate; a capacitive insulating film formed of a ferroelectric on the lower electrode so as to have a thickness of 100 nm or less; and an upper electrode formed on the capacitive insulating element. In any cross section of...

20060030059 - Apparatus and method for testing defects: A defect inspection method includes radiating an illumination slit-shaped beam having lights substantially parallel to a longitudinal direction to a substrate having circuit patterns in a direction inclined at a predetermined gradient relative to the direction of a line normal to the substrate and inclined at a predetermined gradient on...

20060030060 - Apparatus and method for testing defects: An apparatus for detecting defects on a specimen including am illumination optical unit which obliquely projects a laser onto a region which is longer in one direction than in a direction transverse to said one direction on a surface of a specimen, a table unit which mounts said specimen and...

20060030061 - Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate: A process which addresses the problem of transient defects comprises first processing one or more test chips on a substrate to reveal one or more potential transient defects during subsequent processing of all of the chips on the substrate; identifying the exact locations of such potential transient defects on one...

20060030062 - Micromachined wafer strain gauge: A micromachined strain gauge comprising a plastically deformable piezoresistive microstructure formed on a surface of a substrate so that deformation of the substrate plastically deforms the microstructure to thereby change the resistance of the microstructure. The stress in the substrate can be determined from the change in the resistance of...

20060030063 - Package structure for light emitting diode and method thereof: A package structure of a light emitting diode includes a substrate structure, a connection layer, and at least one conductive passage. The substrate structure sequentially includes a conduction board, an insulation layer, and a conductive layer. The insulation layer is configured to electrically insulate the conduction board from the conductive...

20060030064 - Method and apparatus for addressing thickness variations of a trench floor formed in a semiconductor substrate: A method for utilizing interference fringe patterns generated when milling a trench through a semiconductor substrate by a method such as FIB milling, to determine and optimize the thickness uniformity of the trench bottom. The interference fringes may be mapped and the mapping used to direct the FIB milling to...

20060030065 - Semiconductor optical device