Semiconductor device manufacturing: process inventions 01/06

20060019411 - Storage container for receiving precision substrates such as wafers: A storage container for receiving precision substrates such as wafers, having increased strength and improved drying ability when washed. The storage container has a letter L-shaped circumferential wall (12) projectingly provided on an outer wall face, the circumferential wall functioning as a gasket insertion groove (12a). A first flange (13)...

20060019412 - Method to selectively correct critical dimension errors in the semiconductor industry: A method to correct critical dimension errors during a semiconductor manufacturing process. The method includes providing a first semiconductor device. The first semiconductor device is analyzed to determine at least one critical dimension error within the first semiconductor device. A dose of electron beam exposure to correct the at least...

20060019413 - Method for producing a local coating and combinatory substrate having such coating: A method for producing at least one local coating on a substrate is provided, as well as a combinatory substrate having such a local coating, a mask that is removable in a non-destructive manner being arranged on the substrate in a first step; the mask having at least one perforation,...

20060019416 - Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions: With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from...

20060019415 - Rapid thermal anneal equipment and method using sichrome film: A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a...

20060019417 - Substrate processing method and substrate processing apparatus: A substrate processing method is used to polish a substrate. The substrate processing method includes rotating a substrate 13 by a motor 12, polishing a first surface of a peripheral portion of the substrate 13 by pressing a polishing surface of a polishing mechanism 20 against the first surface, determining...

20060019414 - Wiring structure to minimize stress induced void formation: A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at...

20060019418 - Method for evaluating and modifying solder attach design for integrated circuit packaging assembly: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is...

20060019419 - Method of detecting a defect in a simiconductor device: A method of detecting a defect in a semiconductor device may involve immersing a substrate into a chemical solution. The substrate may support a metal wiring and an insulation layer may cover the metal wiring. The chemical solution may permeate through the defect such as a pinhole and/or a crack...

20060019420 - Mems device polymer film deposition process: A method of depositing polymer thin films on a MEMS device having a wafer stack includes depositing one or more protection films on a polymer thin film layer on the wafer stack, fabricating the MEMS device, and removing the one or more protection films....

20060019421 - Semiconductor mechanical sensor: A semiconductor mechanical sensor having a new structure in which a S/N ratio is improved. In the central portion of a silicon substrate 1, a recess portion 2 is formed which includes a beam structure. A weight is formed at the tip of the beam, and in the bottom surface...

20060019422 - Magnetic shield for integrated circuit packaging: Structures and methods for providing magnetic shielding for integrated circuits are disclosed. The shielding comprises a foil or sheet of magnetically permeable material applied to an outer surface of a molded (e.g., epoxy) integrated circuit package. The foil can be held in place by adhesive or by mechanical means. The...

20060019424 - Image sensor fabrication method and structure: A method is provided for processing a substrate. The substrate has at least one filter region, a plurality of bond pads, and a plurality of scribe lines arranged around the filter region and bond pads. A first planarization layer is formed above the substrate. The planarization layer has a substantially...

20060019423 - Method for manufacturing solid-state image sensor: In a method for manufacturing a solid-state image sensor including forming a photodetector portion for a photoelectric conversion in a semiconductor substrate, and forming a shift register for transferring a signal charge read out from the photodetector portion, an annealing is carried out after an ion implantation for forming a...

20060019425 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor improves the characteristics of device by preventing a pad from being contaminated without damaging a micro-lens. The method includes steps of forming a device protection layer on a semiconductor substrate including at least one photo-sensing device and at least one metal pad...

20060019426 - Method for manufacturing cmos image sensor having microlens therein with high photosensitivity: The method for manufacturing a CMOS image sensor is employed to prevent bridge phenomenon between adjacent microlenses by employing openings between the microlenses. The method includes the steps of: preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process; forming an interlayer dielectric (ILD), metal...

20060019427 - One-pot synthesis of high-quality metal chalcogenide nanocrystals without precursor injection: A method of homogeneously forming metal chalcogenide nanocrystals includes the steps combining a metal source, a chalcogenide source, and at least one solvent at a first temperature to form a liquid comprising assembly, and heating the assembly at a sufficient temperature to initiate nucleation to form a plurality of metal...

20060019428 - Method of and mechanism for peeling adhesive tape bonded to segmented semiconductor wafer: An adhesive tape peeling mechanism has an adhering section and a porous member. The adhering section adheres to a segmented semiconductor wafer bonded to adhesive tape. The porous member is provided on the surface adhering to the semiconductor wafer of the adhering section. The porous member is divided into at...

20060019429 - Method for manufacturing plastic ball grid array package with integral heatsink: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient...

20060019430 - Semiconductor device with improved heat dissipation, and a method of making semiconductor device: A semiconductor device includes a semiconductor chip, a heat dissipation member for dissipating heat generated by the semiconductor chip, and a coupling member which thermally couples the semiconductor chip to the heat dissipation member, wherein the coupling member is made of metal and deformable to absorb a stress generated between...

20060019431 - Encapsulation of conductive lines of semiconductor devices: A method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material comprising TaN, Ta, Ti, TiN, or combinations thereof is disposed over conductive lines of a semiconductor device. The encapsulating protective material protects the conductive lines from harsh etch chemistries when a subsequently deposited...

20060019432 - Method for manufacturing semiconductor device having shielding case, electronic equipment using the semiconductor device, and shielding case attaching method: A shielding case bank has shielding cases that arranged at a pitch twice as large as a pitch of molded articles in a molded article bank. Two shielding case banks are stacked one on the other with displacement from each other by half the pitch so that the shielding cases...

20060019433 - Thin film transistor structure and method of fabricating the same: In a thin film transistor (TFT) structure, formation of a spacer layer is used for isolating the NI junction from an insulating layer comprising a nitride, so as to decrease the amount of current leakage and improve the electric characteristics of TFT. In a back-channel etching (BCE) type TFT device,...

20060019434 - Semiconductor device having body contact through gate and method of fabricating the same: According to an embodiment of the invention, a lower transistor is formed on a semiconductor substrate, and an upper thin film transistor is formed on the lower transistor. A body contact plug is formed to penetrate an upper gate electrode of the upper thin film transistor and a body pattern,...

20060019435 - Methods of fabricating nitride-based transistors with a cap layer and a recessed gate: An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage...

20060019436 - Transistor of semiconductor device and method of manufacturing the same: Disclosed are a semiconductor device and a method of manufacturing the same. According to the present invention, the transistor of the semiconductor device comprises a stack type gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are sequentially stacked on a semiconductor...

20060019437 - Dual work function gate electrodes obtained through local thickness-limited silicidation: The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is...

20060019438 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed, which includes an n-channel MISFET including a first gate electrode and a first spacer formed on a side surface of the first gate electrode, the first spacer having a compressive stress; and a p-channel MISFET comprising a second gate electrode and a second spacer formed...

20060019439 - Process for obtaining spatially-organised nanostructures on thin films: A process for forming nanostructures comprising the step of applying on localised regions of a smooth thin film of bistable or multistable molecules an external perturbation with preset magnitude thereby said film undergoes a collective morphological transformation and nanostructures are formed by selforganisation of said molecules, said nanostructures having preset...

20060019440 - Semiconductor constructions: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying...

20060019441 - Process for fabricating non-volatile memory by tilt-angle ion implantation: A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that...

20060019442 - Method of forming a capacitor: A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with the substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. Such substrate has an exposed...

20060019443 - Top-oxide-early process and array top oxide planarization: Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of...

20060019444 - Flash memory process with high voltage ldmos embedded: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A...

20060019446 - Method for manufacturing a flash memory device: A method of manufacturing a flash memory device by carrying out the process of shallow trench isolation (STI) in a memory cell region, so that it decreases an aspect ratio of pattern by forming a field isolation film so as to reduce gap-filling defects due to high density plasma (HDP)...

20060019445 - Non-volatile memory and manufacturing method thereof: A method of manufacturing a non-volatile memory is provided. A substrate is provided and then a plurality of stacked gate structures is formed on the substrate. Each stacked gate structure includes a tunneling dielectric layer, a floating gate, a first inter-gate dielectric layer, a control gate and a cap layer....

20060019447 - Process for the self-aligning production of a transistor with a u-shaped gate: The present invention provides a process for producing a gate element for a transistor, in which a substrate (101) is provided, an insulation layer (104) and a sacrificial layer (105) are deposited on the substrate (101), the sacrificial layer (105) is patterned and a spacing layer (107) is deposited on...

20060019448 - Termination for trench mis device having implanted drain-drift region: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in...

20060019449 - Reduction of field edge thinning in peripheral devices: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the...

20060019450 - Semiconductor device and method for manufacturing the same: An exemplary method for manufacturing a semiconductor device includes: forming an insulating layer over a semiconductor substrate having a gate insulating layer, a gate, and a spacer, respectively formed thereabove and one or more junction regions formed therein so as to fill a full height of a gap between gates;...

20060019451 - Method for patterning hfo2-containing dielectric: A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas...

20060019452 - Method for patterning hfo2-containing dielectric: A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas...

20060019453 - Nrom flash memory with a high-permittivity gate dielectric: A high permittivity gate dielectric is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of an atomic layer deposited and/or evaporated nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric...

20060019454 - Method for making a semiconductor device comprising a superlattice dielectric interface layer: A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer...

20060019456 - Transistor fabrication methods using dual sidewall spacers: Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after...

20060019455 - Transistor fabrication methods using reduced width sidewall spacers: Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material...

20060019457 - Methods of forming a transistor with an integrated metal silicide gate electrode: Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal silicide. A transistor gate isolation capping layer is formed in the...

20060019458 - Creating increased mobility in a bipolar device: The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by...

20060019459 - Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals localised with precision: e

20060019460 - Method of manufacturing a metal- insulator-metal capacitor: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory...

20060019461 - Methods of forming capacitors: This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first capacitor electrode material is exposed to a nitrogen comprising atmosphere effective to form a dielectric silicon and nitrogen comprising material on the first capacitor electrode material. The dielectric...

20060019462 - Patterned strained semiconductor substrate and device: A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive...

20060019463 - Die attaching method of semiconductor chip using warpage prevention material: A die attaching method of a semiconductor chip simplifies the process of fabricating a package from the chip while preventing the chip form being damaged even when the chip is very thin. Warpage prevention material is adhered to a top surface of a wafer having a plurality of chips formed...

20060019466 - Germanium substrate-type materials and approach therefor: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to...

20060019465 - Method and system for dopant containment: According to one embodiment, a semiconductor device is provided. The semiconductor device includes an oxide layer. The semiconductor device also includes a silicon layer disposed outwardly from the oxide layer and having at least one region comprising a dopant. The semiconductor device also includes a dielectric layer disposed outwardly from...

20060019464 - Method of fabricating silicon on glass via layer transfer: A method of fabricating a silicon-on-glass layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; relaxing the SiGe layer; depositing a layer of silicon on the relaxed SiGe layer; implanting hydrogen ions in a second hydrogen implantation step to facilitate splitting of the wafer; bonding...

20060019467 - Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby: Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein...

20060019468 - Method of manufacturing a plurality of electronic assemblies: A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming...

20060019469 - Deposition of nano-crystal silicon using a single wafer chamber: Numerous embodiments of a method for depositing a layer of nano-crystal silicon on a substrate. In one embodiment of the present invention, a substrate is placed in a single wafer chamber and heated to a temperature between about 300° C. to about 490° C. A silicon source is also fed...

20060019470 - Directionally controlled growth of nanowhiskers: Nanowhiskers are grown in a non-preferential growth direction by regulation of nucleation conditions to inhibit growth in a preferential direction. In a preferred implementation, <001> III-V semiconductor nanowhiskers are grown on an (001) III-V semiconductor substrate surface by effectively inhibiting growth in the preferential <111>B direction. As one example, <001>...

20060019471 - Method for forming silicide nanowire: Methods for forming a silicon-based material layer are disclosed along with silicon-based material layers formed by the method and devices incorporating the silicon-based material layer. The method includes forming an amorphous layer on a silicon-based substrate, doping at least a region of the amorphous layer with a metal ion, and...

20060019473 - Method of crystallizing amorphous si film: A method of crystallizing an amorphous Si film is provided. The method of crystallizing an amorphous Si film may include doping the amorphous Si film formed on a substrate with predetermined metal ions, and annealing the amorphous Si film doped with the metal ions to crystallize the amorphous Si film....

20060019472 - Systems and methods for nanowire growth and harvesting: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality...

20060019474 - Semiconductor thin film crystallization device and semiconductor thin film crystallization method: A first laser beam is emitted from a first laser oscillator in a pulsed manner at a high repetition frequency, and converged onto a substrate by a first intermediate optical system 2 so as to form a slit-like first beam spot. A second laser beam is emitted from a second...

20060019475 - Method of depositing polysilicon: A method of depositing polysilicon includes positioning a substrate within a chemical vapor deposition reactor. The substrate has an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor to provide a reactive atmosphere under conditions effective...

20060019476 - Method for making a detachable semiconductor substrate and for obtaining a semiconductor element: thermal treatment of the substrate to increase the brittleness level of the embrittled layer, said thermal treatment being continued until the appearance of local deformations on said face (2) of the substrate (1) in the form of blisters but without generating exfoliations of the thin layer during this step and...

20060019477 - Plasma immersion ion implantation reactor having an ion shower grid: A plasma immersion ion implantation process for implanting a selected species at a desired ion implantation depth profile in a workpiece is carried out in a reactor chamber with an ion shower grid that divides the chamber into an upper ion generation region and a lower process region, the ion...

20060019478 - Silicide method for cmos integrated circuits: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position...

20060019479 - Feed forward spacer width control in semiconductor manufacturing: A feed-forward method and apparatus for controlling spacer width measures spacer width during processing then further processes the spacers in a spacer width adjustment operation to achieve a desired final spacer width. Silicon nitride spacers may be measured after plasma etching and the measured spacer width is automatically compared to...

20060019480 - Method for fabricating pad redistribution layer: A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over...

20060019481 - Gold bump structure and fabricating method thereof: A flip-chip gold bump structure and a method of fabricating thereof are disclosed. The structure includes a nickel layer formed on a gold bump formed on a chip, and a copper layer formed on the nickel layer for forming a Ni/Cu barrier layer. Because of the formation of the Ni/Cu...

20060019482 - Air gap interconnect structure and method thereof: Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectric layer is thereafter patterned and etched to form a plurality of...

20060019483 - Method for production of an integrated circuit arrangement, in particular with a capacitor arrangement, as well as an integrated circuit arrangement: A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In...

20060019484 - Wafer-leveled chip packaging structure and method thereof: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first...

20060019485 - Multi-layer wiring structure, semiconductor apparatus having multi-layer wiring structure, and methods of manufacturing them: A multi-layer wiring structure including an upper layer wiring (second buried wiring) connected to a buried wiring (first buried wiring) in lower layer wiring grooves (first wiring grooves) through connection conductors, wherein a protective film capable of enduring a cleaning treatment with hydrogen radicals or hydrogen plasma applied to the...

20060019486 - Novel film for copper diffusion barrier: The present invention provides a low dielectric constant copper diffusion barrier film suitable for use in a semiconductor device and methods for fabricating such a film. Some embodiments of the film are formed of a silicon-based material doped with boron. Other embodiments are formed, at least in part, of boron...

20060019487 - Ferromagnetic liner for conductive lines of magnetic memory cells and methods of manufacturing thereof: Methods of forming ferromagnetic liners on the top surface and sidewalls of conductive lines of magnetic memory devices. The ferromagnetic liners increase the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. In one embodiment, an in-bound pole...

20060019489 - Method for forming storage node contact of semiconductor device: Disclosed is a method for forming a storage node contact of a semiconductor device. In such a method, there is provided a substrate formed with gates and source/drain regions. A landing plug poly is formed between the gates, and an insulating interlayer is formed over the entire surface of the...

20060019488 - Method of forming a static random access memory with a buried local interconnect: An SRAM cell includes six transistors. The storage nodes are implemented using local interconnects. A first level of metal overlies the interconnects but is electrically isolated therefrom. Contact plugs are formed to couple the cell to the first level of metal. The contact plugs are preferably formed in a different...

20060019490 - Structure of gold bumps and gold conductors on one ic die and methods of manufacturing the structures: A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first...

20060019491 - Method for manufacturing a semiconductor device: Method for manufacturing a semiconductor device including a semiconductor substrate, an element formed on the substrate, and an insulating film formed on the element, includes: (a) forming a first conductive layer (b) forming a first insulating film on the upper portion of the first conductive layer; (c) forming a second...

20060019492 - Method for preventing a metal corrosion in a semiconductor device: The present invention relates to a method for preventing a metal corrosion in a semiconductor device. The present method includes the steps of etching of a metal layer in a chamber, the metal layer having a photoresist pattern thereon or thereover; oxidizing a surface of the metal layer using a...

20060019493 - Methods of metallization for microelectronic devices utilizing metal oxide: A metal oxide is deposited on a substrate in a semiconductor fabrication metallization process is patterned and subsequently reduced to a more conductive form, such as elemental metal. The metal oxide is reduced by exposure to at least one reducing agent or current that is capable of removing oxygen from...

20060019494 - Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor: Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the...

20060019495 - Atomic layer deposition of tantalum-containing materials using the tantalum precursor taimata: In one example of the invention, a method for depositing a tantalum-containing material on a substrate in a process chamber is provided which includes exposing the substrate to a tantalum precursor that contains TAIMATA and to at least one secondary precursor to deposit a tantalum-containing film during an atomic layer...

20060019496 - Method for fabricating copper-based interconnections for semiconductor device: Cu-based interconnections are fabricated in a semiconductor device by depositing a thin film of Cu or Cu alloy on a dielectric film by sputtering, the dielectric film having trenches and/or via holes at least one groove and being arranged on or above a substrate, and carrying out high temperature and...

20060019497 - Reduced feature-size memory devices and methods for fabricating the same: This disclosure relates to systems and methods for reducing feature sizes. One of these methods enables formation of an original feature having a size in a length or width dimension of between about 100 and about 1000 nanometers with a system capable of patterning features to a minimum size of...

20060019498 - Barc/resist via etchback process: A BARC or other sacrificial fill layer etch comprises a selective etch chemistry of Ar/O2/CO. The BARC etch may be used in a via-first dual damascene method. After via (116) pattern and etch, a BARC/sacrificial fill layer (120) is deposited to fill the via (116) and coat the IMD (110)....

20060019499 - Method of forming passivation layer in semiconductor device: Provided is a method of forming a passivation layer of a semiconductor device, using a high density plasma-enhanced chemical vapor deposition (HDPCVD) in order to form an excellent film without a void between metal lines which are being narrower. During the process of HDPCVD that utilizes SiH4 and O2 gas...

20060019501 - Methods of forming a thin layer including hafnium silicon oxide using atomic layer deposition and methods of forming a gate structure and a capacitor including the same: Methods of forming a thin film include applying a first reactant to a substrate, chemisorbing a first portion of the first reactant and physisorbing a second portion of the first reactant on the substrate, applying a first oxidizer to the substrate, chemically reacting the first oxidizer with the first portion...

20060019500 - Ultraviolet blocking layer: Semiconductor structures and methods of fabricating semiconductor structures are disclosed. The method comprises the steps of: providing an initial semiconductor structure; forming a non-silicon layer overlying the initial semiconductor structure, the non-silicon layer having an extinction coefficient greater than zero at wavelengths below about 300 nanometers; and performing a plasma-based...

20060019502 - Method of controlling the film properties of a cvd-deposited silicon nitride film: We have discovered that adding H2 to a precursor gas composition including SiH4, NH3, and N2 is effective at improving the wet etch rate and the wet etch rate uniformity across the substrate surface of a-SiNx:H films which are deposited on a substrate by PECVD. Wet etch rate is an...

20060019503 - Laser crystallization apparatus and laser crystallization method: A laser crystallization apparatus which capable of correcting both shift in imaging position caused by thermal lens effect of the imaging optical system and shift due to flatness of the substrate comprises an crystallization optical system which irradiates laser light to a thin film disposed on the substrate to melt...

20060019504 - Forming a plurality of thin-film devices: An aspect of the present invention is a method for forming a plurality of thin-film devices. The method includes coarsely patterning at least one thin-film material on a flexible substrate and forming a plurality of thin-film elements on the flexible substrate with a self-aligned imprint lithography (SAIL) process....

20060014303 - Layered ceramic electronic part and manufacturing method thereof: A monolithic ceramic electronic component includes a low-permeability coil portion formed by stacking low-permeability ceramic green sheets, a first coil and a relatively large number of pores, and a high-permeability coil portion formed by stacking high-permeability ceramic green sheets, a second coil and a relatively small number of pores. The...

20060014304 - Superconductor and process for producing the same: A superconductor and a method for producing the same are provided. The method for producing a superconductor includes the step of forming a superconducting layer on a base layer by performing a film deposition at least three times, wherein the film thickness of a superconducting film in each film deposition...

20060014307 - Ferroelectric random access memory capacitor and method for manufacturing the same: The method for manufacturing an FeRAM capacitor with a merged top electrode plate line (MTP) structure is employed to prevent a detrimental impact on the FeRAM and to secure a reliable FeRAM device. The method includes steps of: preparing an active matrix obtained by a predetermined process; forming a first...

20060014306 - Magnetic random access memory array with thin conduction electrical read and write lines: An MTJ MRAM cell is formed between ultra-thin orthogonal word and bit lines of high conductivity material whose thickness is less than 100 nm. Lines of this thickness produce switching magnetic fields at the cell free layer that are enhanced by a factor of approximately two for a given current....

20060014305 - Mtj patterning using free layer wet etching and lift off techniques: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be patterned using a wet etch technique. A cap layer is formed over the free layer after the free layer is patterned. The cap layer is...

20060014308 - Procedure for arranging chips of a first substrate on a second substrate: The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the...

20060014309 - Temporary chip attach method using reworkable conductive adhesive interconnections: A method for temporary chip attach to determine known good die using a reworkable conductive adhesive interconnection between the chip carrier and die. The die is easily separated from the chip carrier after test, without the use of potentially damaging shear forces, by subjecting the TCA assembly to a rework...

20060014310 - Resonant cavity iii-nitride light emitting devices fabricated by growth substrate removal: A semiconductor light emitting device includes an n-type region, a p-type region, and light emitting region disposed between the n- and p-type regions. The n-type, p-type, and light emitting regions form a cavity having a top surface and a bottom surface. Both the top surface and the bottom surface of...

20060014311 - Method of manufacturing semiconductor laser element: A method of manufacturing a semiconductor laser element having an enhanced yield ratio is provided. The semiconductor laser element having a cladding layer, an intermediate layer, and a capping layer is manufactured as follows. At the laminating step, a plurality of lamination layers are laminated in a laminating direction. Subsequently,...

20060014312 - Method for stripping sacrificial layer in mems assembly: The present invention provides methods of manufacturing a MEMS assembly. In one embodiment, the method includes mounting a MEMS device, such as a MEMS mirror array, on an assembly substrate, where the MEMS device has a sacrificial layer over components formed therein. The method also includes coupling an assembly lid...

20060014313 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units: Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality...

20060014314 - Image sensor with light guides: An image sensor device and fabrication method thereof. An image sensing array is formed in a substrate, wherein the image sensing array comprises a plurality of photosensors with spaces therebetween. A first dielectric layer with a first refractive index is formed overlying the spaces but not the photosensors. A conformal...

20060014315 - Stable, water-soluble quantum dot, method of preparation and conjugates thereof: A method for manufacturing powdered quantum dots comprising the steps of: a) reacting quantum dots comprising a core, a cap and a first ligand associated with the outer surfaces thereof with a second ligand, the second ligand displacing the first ligand and attaching to the outer surfaces of the quantum...

20060014318 - Electronic component having at least one semiconductor chip on a circuit carrier and method for producing the same: An electronic component includes at least one semiconductor chip, which has an active chip top side with contact areas and has a chip rear side arranged on a carrier top side of a circuit carrier. The circuit carrier and the chip top side are covered by a common rewiring layer...

20060014317 - Integrated circuit package having reduced interconnects: A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating...

20060014316 - Method of making a semiconductor chip assemby with a metal containment wall and a solder terminal: A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a metal containment wall and a solder layer in which the metal containment wall includes a cavity and the solder terminal contacts the metal containment wall in the cavity, mechanically attaching a semiconductor chip...

20060014319 - Castellation wafer level packaging of integrated circuit chips: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When...

20060014320 - Method of manufacturing semiconductor device: Insulating films (13, 14) are formed on the surface of a semiconductor wafer (30) on the side on which a plurality of devices are formed. Then, conductor layers (15, 16) are formed to cover opening portions from which electrode pads (12) of each device are exposed. Furthermore, a resist layer...

20060014321 - Manufacturing method of semiconductor device and manufacturing method of lead frame: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes...

20060014322 - Methods and apparatuses relating to block configurations and fluidic self-assembly processes: An apparatus and methods of making an electronic assembly. The electronic assembly comprises a functional block having at least one asymmetric feature. The functional block comprises an integrated circuitry to perform a function pertaining to the electronic assembly. The electronic assembly further comprises a substrate having a receptor site to...

20060014324 - Method and apparatus for cutting away excess synthetic resin from synthetic resin package of electronic component: A method is provided for cutting excess synthetic resin 7, which projects from a resin package 6 of an electronic component, at the root connected to the package, the excess synthetic resin being produced in molding the resin package. The excess synthetic resin 7 is cut by laying a thin...

20060014323 - Thermal interface material with fluid: A thermal interface material is provided to insert into a gap (49) between a heat sink (20) and a heat source (30) in order to dissipate heat from the heat source. The gap has air (51) therein. The thermal interface material may include a fluid (11) and a number of...

20060014326 - Method for fabricating a semiconductor component with contacts situated at the underside: A semiconductor component has a housing with a first main area and a second main area opposite to the first main area, which surrounds at least one semiconductor chip. The semiconductor chip has a first metallization layer on a first main side. A second main side of the semiconductor chip...

20060014325 - Method of assembling a semiconductor component and apparatus therefor: A method of assembling a semiconductor component includes providing a pedestal, placing a first piece on the curved pedestal, wherein the first piece comprises a semiconductor die, placing a second piece over the first piece, and providing an adhesive between the first piece and the second piece. The method further...

20060014327 - Method of fabricating pcb including embedded passive chip: Disclosed is a method of fabricating a PCB including an embedded passive chip, in which the passive chip is mounted on the PCB and an insulator is then laminated on the PCB, or in which a blind hole for receiving the passive chip is formed in the PCB and the...

20060014328 - Resin encapsulation molding for semiconductor device: According to a resin encapsulation molding method for a semiconductor device, a resin-encapsulated substrate having a semiconductor device that is mounted on the substrate and that has a portion exposed is formed. With the method, a device-mounted substrate on which the semiconductor device is mounted is prepared and then the...

20060014329 - Nanodots formed on silicon oxide and method of manufacturing the same: A nanodot material including nanodots formed on silicon oxide, and a method of manufacturing the same, is provided. The nanodot material includes a substrate, a silicon oxide layer, and a plurality of nanodots on the silicon oxide layer....

20060014331 - Floating-body dram in tri-gate technology: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A...

20060014330 - Method for manufacturing soi wafer: The present invention provides a manufacturing method for an SOI wafer with a high productivity in which generation of a void is suppressed in manufacturing the SOI wafer. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer...

20060014332 - Soi device having increased reliability and reduced free floating body effects: The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology....

20060014333 - Anchoring, by lateral oxidizing, of patterns of a thin film to prevent the dewetting phenomenon: The invention relates to a thin film having a thickness of less than 10 nm, made of oxidizable semi-conductor material and patterned in the form of patterns. To prevent the dewetting phenomenon of said patterns, lateral oxidized zones are arranged at the periphery of each pattern of the thin film...

20060014334 - Method of fabricating heterojunction devices integrated with cmos: A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may be selective or not and the epitaxial layer may be formed so as to...

20060014335 - Method of manufacturing a semiconductor device: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order...

20060014336 - Method of forming double-gated silicon-on-insulator (soi) transistors with corner rounding: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer,...

20060014337 - Semiconductor device and method for manufacturing the same: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source...

20060014338 - Method and structure for strained finfet devices: A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device....

20060014339 - Method of detecting one or more defects in a string of spaced apart studs: A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each...

20060014340 - Semiconductor device and method of manufacturing the same: According to an aspect of the invention, there is provided a semiconductor device provided with a CMOS-FET circuit, comprising at least one of a tensile stress film disposed in a part of an element isolating film around an NMOS forming region and having a tensile stress, and a compressive stress...

20060014341 - Method for fabricating a gate mask of a semiconductor device: A nitride layer of the gate mask for the semiconductor device is deposited at a temperature higher than 750 deg. C. so as to release hydrogen from the nitride layer. Alternatively, a nitride layer of the gate mask for the semiconductor device is deposited in a gas atmosphere with use...

20060014342 - Method of manufacturing a semiconductor component: A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above...

20060014343 - Method for forming a capacitor for an integrated circuit and integrated circuit: Integrated circuits can include an integrated capacitor with a metal alloy layer. Methods for forming such integrated circuits can include providing a substrate, forming a first electrode including depositing a metal alloy layer having a first surface and an exposed second surface, etching the exposed second surface of the metal...

20060014344 - Methods of forming semiconductor structures and capacitor devices: The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the...

20060014346 - Magnetic random access memory array with thin conduction electrical read and write lines: An MTJ MRAM cell is formed between or below an intersection of ultra-thin orthogonal word and bit lines of high conductivity material whose thickness is less than 100 nm. Lines of this thickness produce switching magnetic fields at the cell free layer that are enhanced by a factor of approximately...

20060014347 - Semiconductor integrated circuit device having single-element type non-volatile memory elements: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is...

20060014345 - Uniform channel programmable erasable flash eeprom: A new method to form a split gate for a flash device in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A film is deposited overlying the substrate. The film comprises a second dielectric layer overlying a first dielectric layer with an electronic-trapping...

20060014348 - Method for fabricating a mask rom: The present invention discloses a method for fabricating a buried bit line of a mask ROM. The method includes providing a semiconductor substrate with a photoresist layer, and patterning the photoresist layer to form a photoresist pattern. A first ion implantation process is performed to form a first doped region...

20060014349 - Planarized and silicided trench contact: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce...

20060014350 - Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions: A method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions is provided. A silicon substrate having thereon a poly gate structure is prepared. The poly gate structure has sidewalls and a top surface. An offset spacer is formed on its sidewall. An ion implantation process is carried out...

20060014351 - Low leakage mos transistor: A method of forming a low leakage MOS transistor. The transistor includes a gate on a substrate with at least two first spacers adjacent to the gate. A first doped region is formed under each first spacer and a second doped region is formed adjacent to each first doped region,...

20060014352 - Method and apparatus providing cmos imager device pixel with transistor having lower threshold voltage than other imager device transistors: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions...

20060014353 - Semiconductor device and manufacturing method therefor: To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method for the semiconductor device, an n-type silicon layer is deposited on a p-type silicon...

20060014354 - Method of making transistor with strained source/drain: A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially...

20060014355 - Semiconductor device and method of manufacturing the same: Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal...

20060014356 - Metal-insulator-metal capacitor and method of fabricating same: A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second...

20060014357 - Structure and method of making an enhanced surface area capacitor: A method of making a capacitor structure having an enhanced plate surface area is provided. In such method, a mandrel is provided which has a major surface having an array of features including at least one of: a plurality of first features protruding upward or a plurality of second features...

20060014358 - Method for microfabricating structures using silicon-on-insulator material: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the...

20060014359 - Formation of active area using semiconductor growth process without sti integration: A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body....

20060014361 - Method for forming device isolation layer of semiconductor device: A method for forming a device isolation device of a semiconductor device is disclosed. The method includes the steps of forming a moat pattern for forming a trench on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermined thickness by using the moat pattern, forming...

20060014360 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes forming a coating type carbon film on a semiconductor substrate, patterning the coating type carbon film according to trenches formed in the semiconductor substrate and having different opening widths, and etching the semiconductor substrate with the patterned coating type carbon film serving...

20060014362 - Methods of forming shallow trench isolation structures in semiconductor devices: Methods of forming a shallow trench isolation structures in semiconductor devices are disclosed. A disclosed method comprises forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate; forming a trench defining first and second active areas by etching the second oxide layer, the nitride...

20060014363 - Thermal treatment of a semiconductor layer: A method for forming a structure that includes a layer that is removed from a donor wafer that has a first layer made of a semiconductor material containing germanium. The method includes the steps of forming a weakness zone in the thickness of the first layer; bonding the donor wafer...

20060014364 - Semiconductor device and semiconductor wafer and a method for manufacturing the same: The semiconductor device 1 has a semiconductor chip 10 (first semiconductor chip) and a semiconductor chip 20 (second semiconductor chip). The semiconductor chip 20 is formed on the semiconductor chip 10. The semiconductor chip 20 is constituted by comprising a semiconductor substrate 22. The semiconductor substrate 22, which is an...

20060014365 - Method for fabricating a semiconductor element from a dispersion of semiconductor particles: Provided is a method for forming a semiconductor element such as film. The method comprises the steps of: (i) depositing a suspension of particles of a first semiconductor and a solution of a second semiconductor or a precursor thereof on a surface of a substrate such that a mixture comprising...

20060014366 - Control of strain in device layers by prevention of relaxation: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance....

20060014367 - Nucleation and deposition of platinum group metal films using ultraviolet irradiation: A method of depositing a platinum based metal film by CVD deposition includes bubbling a non-reactive gas through an organic platinum based metal precursor to facilitate transport of precursor vapor to the chamber. The platinum based film is deposited onto a non-silicon bearing substrate in a CVD deposition chamber in...

20060014368 - Method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes: A method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes includes forming a transparent conductive film on a GaN layer, forming a transparent conductive hetero-junction of opposing electrical characteristics on a transparent conductive film on the surface of the GaN layer through an ion diffusion process, and...

20060014369 - Stud electrode and process for making same: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell...

20060014370 - Methods for processing integrated circuit packages formed using electroplating and apparatus made therefrom: An integrated circuit package is processed by electroplating the integrated circuit package. The electroplating is performed without forming plating traces on a conductive surface of a pad side of the integrated circuit package. Pad areas of the integrated circuit package are thus plated with one or more materials. An integrated...

20060014371 - Method for forming an integrated semiconductor circuit arrangement: Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained....

20060014373 - Method for finishing metal line for semiconductor device: A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface...

20060014372 - Semiconductor device and method for fabricating the same: The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad;...

20060014374 - Layer assembly and method for producing a layer assembly: The invention relates to a layer arrangement and to a process for producing a layer arrangement. The layer arrangement has a layer which is arranged on a substrate and includes a first subregion comprising decomposable material and a second subregion which is arranged next to the first subregion and has...

20060014375 - Soluble carbon nanotubes: A method of solubilizing carbon nanotubes. Carbon nanotubes, and urea are mixed together and then heated....

20060014376 - Stacked via-stud with improved reliability in copper metallurgy: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of...

20060014377 - Method for forming passivation film of semiconductor device and structure of passivation film of semiconductor device: Disclosed are a method of manufacturing a semiconductor device and a structure of a semiconductor device. A method of forming a passivation film of a semiconductor device comprises the steps of forming metal wires on a semiconductor substrate, forming a buffer oxide film being a first passivation film on the...

20060014378 - System and method to form improved seed layer: A method is disclosed to form a seed layer for an integrated circuit. The method may include depositing a metal seed layer (106) over a barrier layer (104) such that the metal seed layer (106) has a greater thickness along a top surface portion (114) of at least one recessed...

20060014380 - Production method for wiring structure of semiconductor device: In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring films formed protrusively above tops of the first insulating film among...

20060014379 - Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a...

20060014382 - Method for forming an interconnection line in a semiconductor device: The CD uniformity of a damascene pattern and the reliability of interconnection lines may be enhanced when a semiconductor device is manufactured by a method including: forming a first insulating layer on a semiconductor substrate, the first insulating layer having a contact hole partially exposing the substrate; forming a photoresist...

20060014381 - Method for forming interconnection line in semiconductor device using a phase-shift photo mask: A method for forming a dual damascene structure. The method includes depositing an interlayer dielectric on an underlying layer, depositing a photoresist on the interlayer dielectric, and exposing and developing the photoresist by using a phase-shift photo mask to form a photoresist pattern having trench patterns and hole patterns. The...

20060014384 - Method of forming a layer and forming a capacitor of a semiconductor device having the same layer: In a method of forming a layer using an atomic layer deposition process, after a substrate is loaded into a chamber, a first reactant is provided onto the substrate. The first reactant is partially chemisorbed on the substrate. A second reactant is introduced into the chamber to form a preliminary...

20060014385 - Method of forming titanium nitride layer and method of fabricating capacitor using the same: A method of fabricating a storage capacitor includes depositing a first titanium nitride layer on a dielectric layer using a chemical vapor deposition technique or an atomic layer deposition technique performed at a first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas at a predetermined...

20060014383 - Method of producing semiconductor single crystal wafer and laser processing device used therefor: A method of manufacturing single-crystal semiconductor wafers is characterized in that a plurality of single-crystal semiconductor wafers of a relatively small diameter desired by users are cut out from a single-crystal semiconductor wafer of a relatively large diameter. Therefore, there can also be obtained a secondary effect that even if...

20060014386 - Small grain size, conformal aluminum interconnects and method for their formation: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain...

20060014387 - Silicide formation using a low temperature anneal process: A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer 10 and performing a first low temperature anneal to create the silicide 160. The method further includes removing an unreacted portion of...

20060014388 - Wafer processing apparatus & methods for depositing cobalt silicide: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti—along with layers of Co—are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence,...

20060014389 - Method of manufacturing semiconductor device: In a MOS semiconductor device in which a SOI substrate made of an extremely thin film is used, a polycrystalline silicon film is formed through contact holes provided in a thin insulating film on a source and a drain. Then, a relatively thick insulating film is provided thereon and formed...

20060014390 - Slurry composition, polishing method using the slurry composition and method of forming a gate pattern using the slurry composition: A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry...

20060014391 - Method of manufacturing a semiconductor device using a cleaning composition: A metal-containing pattern structure is formed on a semiconductor substrate, and a cleaning composition is applied to the semiconductor substrate. The cleaning composition includes, based on a total weight of the cleaning composition, about 78 wt % to about 99.98 wt % of an acidic aqueous solution, about 0.01 wt...

20060014392 - Method for producing a semiconductor component and a semiconductor component produced according to the method: A method is for producing a semiconductor component, e.g., a multilayer semiconductor element, e.g., a micromechanical component, e.g., a pressure sensor, having a semiconductor substrate, e.g., made of silicon, and a semiconductor component produced according to the method. To reduce the production cost of such a semiconductor component, in a...

20060014393 - Process method to facilitate silicidation: The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide...

20060014394 - Process for low temperature, dry etching, and dry planarization of copper: The subject invention pertains to a method and apparatus for etching copper (Cu). The subject invention can involve passing a halide gas over an area of Cu such that CuX, or CuX and CuX2, are formed, where X is the halide. Examples of halides which can be utilized with the...

20060014395 - Method of manufacturing displays and apparatus for manufacturing displays: A method of manufacturing displays, includes at least forming a metal pattern on a surface of an insulating substrate, forming an insulating film on the metal pattern, forming a pattern of a photosensitive resin on the insulating film, and forming a contact hole in the insulating film with the film...

20060014396 - Method for forming a resist protect layer: A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for...

20060014398 - Method of forming dielectric layer using plasma enhanced atomic layer deposition technique: A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the...

20060014397 - Methods for the reduction and elimination of particulate contamination with cvd of amorphous carbon: A method is provided for forming an amorphous carbon layer, deposited on a dielectric material such as oxide, nitride, silicon carbide, carbon doped oxide, etc., or a metal layer such as tungsten, aluminum or poly-silicon. The method includes the use of chamber seasoning, variable thickness of seasoning film, wider spacing,...

20060014399 - Low-temperature plasma-enhanced chemical vapor deposition of silicon-nitrogen-containing films: A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film...

20060014400 - Method for fabricating a buried metallic layer in a semiconductor body and semiconductor component having a buried metallic layer: A method for fabricating a buried metallic layer at a predetermined vertical position in a semiconductor body having a first and second side includes a step of applying a metal layer to one of the first and second sides at least in sections. The method also includes establishing a positive...

20060008927 - Dual gated finfet gain cell: A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device....

20060008925 - Electronic parts cleaning solution: (EO is an oxyethylene group, and PO is an oxypropylene group. x and y, and a and b are positive number, which x(x+y) and a(a+b) are 0.05 to 0.5 respectively, and z and c are positive integers. R is a residue group wherein hydrogen atoms are removed from hydroxyl group...

20060008926 - Semiconductor fabrication that includes surface tension control: In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a surface tension lowering agent....

20060008928 - Process for producing fine particles of bismuth titanate: It is an object to provide fine particles of bismuth titanate having excellent dielectric characteristics, high crystallinity and a small particle diameter, and a process for their production. The object is accomplished by a process which comprises a step of obtaining a melt comprising, as represented by mol % based...

20060008929 - Method and apparatus for the improvement of material/voltage contrast: A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal...

20060008930 - Color filter, manufacturing method thereof, electrooptical device and electronic equipment: A method for manufacturing a color filter having a picture element part surrounded by a partition wall and provided in the plural number on a substrate including a step of forming the partition wall that has a lyophobic quality on the substrate, step of forming a lyophilic layer in the...

20060008931 - Method for electro-luminescent display fabrication: The present invention discloses a method for fabricating a pixel area of an electro-luminescent display device. At least one buffer layer is formed on a substrate. An etch stop layer is formed on the buffer layer. At least one intermediate layer is formed over the etch stop layer. The intermediate...

20060008932 - Liquid crystal display device having driving circuit and method of fabricating the same: A polycrystalline silicon thin film transistor of a bottom gate structure is used as a switching element and a mask having transmissive, half-transmissive and blocking areas is used so that an array substrate for a liquid crystal display device having a monolithic driving circuit can be fabricated through a six-mask...

20060008933 - Method for producing an integrated pin diode and corresponding circuit: An explanation is given of, inter alia, a method for fabricating an integrated pin photodiode which contains a buried region (20) and a terminal region (32) leading to the buried region (20). This fabrication method enables the pin photodiode (14) to be integrated in a simple manner. Moreover, there is...

20060008934 - Micromechanical actuator with multiple-plane comb electrodes and methods of making: A micro-electro-mechanical component comprising a movable element with comb electrodes, and two stationa