Semiconductor device manufacturing: process inventions 01/06

20060019411 - Storage container for receiving precision substrates such as wafers: A storage container for receiving precision substrates such as wafers, having increased strength and improved drying ability when washed. The storage container has a letter L-shaped circumferential wall (12) projectingly provided on an outer wall face, the circumferential wall functioning as a gasket insertion groove (12a). A first flange (13)...

20060019412 - Method to selectively correct critical dimension errors in the semiconductor industry: A method to correct critical dimension errors during a semiconductor manufacturing process. The method includes providing a first semiconductor device. The first semiconductor device is analyzed to determine at least one critical dimension error within the first semiconductor device. A dose of electron beam exposure to correct the at least...

20060019413 - Method for producing a local coating and combinatory substrate having such coating: A method for producing at least one local coating on a substrate is provided, as well as a combinatory substrate having such a local coating, a mask that is removable in a non-destructive manner being arranged on the substrate in a first step; the mask having at least one perforation,...

20060019416 - Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions: With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from...

20060019415 - Rapid thermal anneal equipment and method using sichrome film: A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a...

20060019417 - Substrate processing method and substrate processing apparatus: A substrate processing method is used to polish a substrate. The substrate processing method includes rotating a substrate 13 by a motor 12, polishing a first surface of a peripheral portion of the substrate 13 by pressing a polishing surface of a polishing mechanism 20 against the first surface, determining...

20060019414 - Wiring structure to minimize stress induced void formation: A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at...

20060019418 - Method for evaluating and modifying solder attach design for integrated circuit packaging assembly: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is...

20060019419 - Method of detecting a defect in a simiconductor device: A method of detecting a defect in a semiconductor device may involve immersing a substrate into a chemical solution. The substrate may support a metal wiring and an insulation layer may cover the metal wiring. The chemical solution may permeate through the defect such as a pinhole and/or a crack...

20060019420 - Mems device polymer film deposition process: A method of depositing polymer thin films on a MEMS device having a wafer stack includes depositing one or more protection films on a polymer thin film layer on the wafer stack, fabricating the MEMS device, and removing the one or more protection films....

20060019421 - Semiconductor mechanical sensor: A semiconductor mechanical sensor having a new structure in which a S/N ratio is improved. In the central portion of a silicon substrate 1, a recess portion 2 is formed which includes a beam structure. A weight is formed at the tip of the beam, and in the bottom surface...

20060019422 - Magnetic shield for integrated circuit packaging: Structures and methods for providing magnetic shielding for integrated circuits are disclosed. The shielding comprises a foil or sheet of magnetically permeable material applied to an outer surface of a molded (e.g., epoxy) integrated circuit package. The foil can be held in place by adhesive or by mechanical means. The...

20060019424 - Image sensor fabrication method and structure: A method is provided for processing a substrate. The substrate has at least one filter region, a plurality of bond pads, and a plurality of scribe lines arranged around the filter region and bond pads. A first planarization layer is formed above the substrate. The planarization layer has a substantially...

20060019423 - Method for manufacturing solid-state image sensor: In a method for manufacturing a solid-state image sensor including forming a photodetector portion for a photoelectric conversion in a semiconductor substrate, and forming a shift register for transferring a signal charge read out from the photodetector portion, an annealing is carried out after an ion implantation for forming a...

20060019425 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor improves the characteristics of device by preventing a pad from being contaminated without damaging a micro-lens. The method includes steps of forming a device protection layer on a semiconductor substrate including at least one photo-sensing device and at least one metal pad...

20060019426 - Method for manufacturing cmos image sensor having microlens therein with high photosensitivity: The method for manufacturing a CMOS image sensor is employed to prevent bridge phenomenon between adjacent microlenses by employing openings between the microlenses. The method includes the steps of: preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process; forming an interlayer dielectric (ILD), metal...

20060019427 - One-pot synthesis of high-quality metal chalcogenide nanocrystals without precursor injection: A method of homogeneously forming metal chalcogenide nanocrystals includes the steps combining a metal source, a chalcogenide source, and at least one solvent at a first temperature to form a liquid comprising assembly, and heating the assembly at a sufficient temperature to initiate nucleation to form a plurality of metal...

20060019428 - Method of and mechanism for peeling adhesive tape bonded to segmented semiconductor wafer: An adhesive tape peeling mechanism has an adhering section and a porous member. The adhering section adheres to a segmented semiconductor wafer bonded to adhesive tape. The porous member is provided on the surface adhering to the semiconductor wafer of the adhering section. The porous member is divided into at...

20060019429 - Method for manufacturing plastic ball grid array package with integral heatsink: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient...

20060019430 - Semiconductor device with improved heat dissipation, and a method of making semiconductor device: A semiconductor device includes a semiconductor chip, a heat dissipation member for dissipating heat generated by the semiconductor chip, and a coupling member which thermally couples the semiconductor chip to the heat dissipation member, wherein the coupling member is made of metal and deformable to absorb a stress generated between...

20060019431 - Encapsulation of conductive lines of semiconductor devices: A method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material comprising TaN, Ta, Ti, TiN, or combinations thereof is disposed over conductive lines of a semiconductor device. The encapsulating protective material protects the conductive lines from harsh etch chemistries when a subsequently deposited...

20060019432 - Method for manufacturing semiconductor device having shielding case, electronic equipment using the semiconductor device, and shielding case attaching method: A shielding case bank has shielding cases that arranged at a pitch twice as large as a pitch of molded articles in a molded article bank. Two shielding case banks are stacked one on the other with displacement from each other by half the pitch so that the shielding cases...

20060019433 - Thin film transistor structure and method of fabricating the same: In a thin film transistor (TFT) structure, formation of a spacer layer is used for isolating the NI junction from an insulating layer comprising a nitride, so as to decrease the amount of current leakage and improve the electric characteristics of TFT. In a back-channel etching (BCE) type TFT device,...

20060019434 - Semiconductor device having body contact through gate and method of fabricating the same: According to an embodiment of the invention, a lower transistor is formed on a semiconductor substrate, and an upper thin film transistor is formed on the lower transistor. A body contact plug is formed to penetrate an upper gate electrode of the upper thin film transistor and a body pattern,...

20060019435 - Methods of fabricating nitride-based transistors with a cap layer and a recessed gate: An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage...

20060019436 - Transistor of semiconductor device and method of manufacturing the same: Disclosed are a semiconductor device and a method of manufacturing the same. According to the present invention, the transistor of the semiconductor device comprises a stack type gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gate are sequentially stacked on a semiconductor...

20060019437 - Dual work function gate electrodes obtained through local thickness-limited silicidation: The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is...

20060019438 - Semiconductor device and method of manufacturing the same: A semiconductor device is disclosed, which includes an n-channel MISFET including a first gate electrode and a first spacer formed on a side surface of the first gate electrode, the first spacer having a compressive stress; and a p-channel MISFET comprising a second gate electrode and a second spacer formed...

20060019439 - Process for obtaining spatially-organised nanostructures on thin films: A process for forming nanostructures comprising the step of applying on localised regions of a smooth thin film of bistable or multistable molecules an external perturbation with preset magnitude thereby said film undergoes a collective morphological transformation and nanostructures are formed by selforganisation of said molecules, said nanostructures having preset...

20060019440 - Semiconductor constructions: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying...

20060019441 - Process for fabricating non-volatile memory by tilt-angle ion implantation: A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that...

20060019442 - Method of forming a capacitor: A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with the substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. Such substrate has an exposed...

20060019443 - Top-oxide-early process and array top oxide planarization: Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of...

20060019444 - Flash memory process with high voltage ldmos embedded: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A...

20060019446 - Method for manufacturing a flash memory device: A method of manufacturing a flash memory device by carrying out the process of shallow trench isolation (STI) in a memory cell region, so that it decreases an aspect ratio of pattern by forming a field isolation film so as to reduce gap-filling defects due to high density plasma (HDP)...

20060019445 - Non-volatile memory and manufacturing method thereof: A method of manufacturing a non-volatile memory is provided. A substrate is provided and then a plurality of stacked gate structures is formed on the substrate. Each stacked gate structure includes a tunneling dielectric layer, a floating gate, a first inter-gate dielectric layer, a control gate and a cap layer....

20060019447 - Process for the self-aligning production of a transistor with a u-shaped gate: The present invention provides a process for producing a gate element for a transistor, in which a substrate (101) is provided, an insulation layer (104) and a sacrificial layer (105) are deposited on the substrate (101), the sacrificial layer (105) is patterned and a spacing layer (107) is deposited on...

20060019448 - Termination for trench mis device having implanted drain-drift region: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in...

20060019449 - Reduction of field edge thinning in peripheral devices: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the...

20060019450 - Semiconductor device and method for manufacturing the same: An exemplary method for manufacturing a semiconductor device includes: forming an insulating layer over a semiconductor substrate having a gate insulating layer, a gate, and a spacer, respectively formed thereabove and one or more junction regions formed therein so as to fill a full height of a gap between gates;...

20060019451 - Method for patterning hfo2-containing dielectric: A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas...

20060019452 - Method for patterning hfo2-containing dielectric: A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas...

20060019453 - Nrom flash memory with a high-permittivity gate dielectric: A high permittivity gate dielectric is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of an atomic layer deposited and/or evaporated nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric...

20060019454 - Method for making a semiconductor device comprising a superlattice dielectric interface layer: A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer...

20060019456 - Transistor fabrication methods using dual sidewall spacers: Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after...

20060019455 - Transistor fabrication methods using reduced width sidewall spacers: Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material...

20060019457 - Methods of forming a transistor with an integrated metal silicide gate electrode: Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal silicide. A transistor gate isolation capping layer is formed in the...

20060019458 - Creating increased mobility in a bipolar device: The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by...

20060019459 - Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals localised with precision: e

20060019460 - Method of manufacturing a metal- insulator-metal capacitor: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory...

20060019461 - Methods of forming capacitors: This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first capacitor electrode material is exposed to a nitrogen comprising atmosphere effective to form a dielectric silicon and nitrogen comprising material on the first capacitor electrode material. The dielectric...

20060019462 - Patterned strained semiconductor substrate and device: A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive...

20060019463 - Die attaching method of semiconductor chip using warpage prevention material: A die attaching method of a semiconductor chip simplifies the process of fabricating a package from the chip while preventing the chip form being damaged even when the chip is very thin. Warpage prevention material is adhered to a top surface of a wafer having a plurality of chips formed...

20060019466 - Germanium substrate-type materials and approach therefor: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to...

20060019465 - Method and system for dopant containment: According to one embodiment, a semiconductor device is provided. The semiconductor device includes an oxide layer. The semiconductor device also includes a silicon layer disposed outwardly from the oxide layer and having at least one region comprising a dopant. The semiconductor device also includes a dielectric layer disposed outwardly from...

20060019464 - Method of fabricating silicon on glass via layer transfer: A method of fabricating a silicon-on-glass layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; relaxing the SiGe layer; depositing a layer of silicon on the relaxed SiGe layer; implanting hydrogen ions in a second hydrogen implantation step to facilitate splitting of the wafer; bonding...

20060019467 - Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby: Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein...

20060019468 - Method of manufacturing a plurality of electronic assemblies: A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming...

20060019469 - Deposition of nano-crystal silicon using a single wafer chamber: Numerous embodiments of a method for depositing a layer of nano-crystal silicon on a substrate. In one embodiment of the present invention, a substrate is placed in a single wafer chamber and heated to a temperature between about 300° C. to about 490° C. A silicon source is also fed...

20060019470 - Directionally controlled growth of nanowhiskers: Nanowhiskers are grown in a non-preferential growth direction by regulation of nucleation conditions to inhibit growth in a preferential direction. In a preferred implementation, <001> III-V semiconductor nanowhiskers are grown on an (001) III-V semiconductor substrate surface by effectively inhibiting growth in the preferential <111>B direction. As one example, <001>...

20060019471 - Method for forming silicide nanowire: Methods for forming a silicon-based material layer are disclosed along with silicon-based material layers formed by the method and devices incorporating the silicon-based material layer. The method includes forming an amorphous layer on a silicon-based substrate, doping at least a region of the amorphous layer with a metal ion, and...

20060019473 - Method of crystallizing amorphous si film: A method of crystallizing an amorphous Si film is provided. The method of crystallizing an amorphous Si film may include doping the amorphous Si film formed on a substrate with predetermined metal ions, and annealing the amorphous Si film doped with the metal ions to crystallize the amorphous Si film....

20060019472 - Systems and methods for nanowire growth and harvesting: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality...

20060019474 - Semiconductor thin film crystallization device and semiconductor thin film crystallization method: A first laser beam is emitted from a first laser oscillator in a pulsed manner at a high repetition frequency, and converged onto a substrate by a first intermediate optical system 2 so as to form a slit-like first beam spot. A second laser beam is emitted from a second...

20060019475 - Method of depositing polysilicon: A method of depositing polysilicon includes positioning a substrate within a chemical vapor deposition reactor. The substrate has an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor to provide a reactive atmosphere under conditions effective...

20060019476 - Method for making a detachable semiconductor substrate and for obtaining a semiconductor element: thermal treatment of the substrate to increase the brittleness level of the embrittled layer, said thermal treatment being continued until the appearance of local deformations on said face (2) of the substrate (1) in the form of blisters but without generating exfoliations of the thin layer during this step and...

20060019477 - Plasma immersion ion implantation reactor having an ion shower grid: A plasma immersion ion implantation process for implanting a selected species at a desired ion implantation depth profile in a workpiece is carried out in a reactor chamber with an ion shower grid that divides the chamber into an upper ion generation region and a lower process region, the ion...

20060019478 - Silicide method for cmos integrated circuits: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position...

20060019479 - Feed forward spacer width control in semiconductor manufacturing: A feed-forward method and apparatus for controlling spacer width measures spacer width during processing then further processes the spacers in a spacer width adjustment operation to achieve a desired final spacer width. Silicon nitride spacers may be measured after plasma etching and the measured spacer width is automatically compared to...

20060019480 - Method for fabricating pad redistribution layer: A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over...

20060019481 - Gold bump structure and fabricating method thereof: A flip-chip gold bump structure and a method of fabricating thereof are disclosed. The structure includes a nickel layer formed on a gold bump formed on a chip, and a copper layer formed on the nickel layer for forming a Ni/Cu barrier layer. Because of the formation of the Ni/Cu...

20060019482 - Air gap interconnect structure and method thereof: Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectric layer is thereafter patterned and etched to form a plurality of...

20060019483 - Method for production of an integrated circuit arrangement, in particular with a capacitor arrangement, as well as an integrated circuit arrangement: A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In...

20060019484 - Wafer-leveled chip packaging structure and method thereof: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first...

20060019485 - Multi-layer wiring structure, semiconductor apparatus having multi-layer wiring structure, and methods of manufacturing them: A multi-layer wiring structure including an upper layer wiring (second buried wiring) connected to a buried wiring (first buried wiring) in lower layer wiring grooves (first wiring grooves) through connection conductors, wherein a protective film capable of enduring a cleaning treatment with hydrogen radicals or hydrogen plasma applied to the...

20060019486 - Novel film for copper diffusion barrier: The present invention provides a low dielectric constant copper diffusion barrier film suitable for use in a semiconductor device and methods for fabricating such a film. Some embodiments of the film are formed of a silicon-based material doped with boron. Other embodiments are formed, at least in part, of boron...

20060019487 - Ferromagnetic liner for conductive lines of magnetic memory cells and methods of manufacturing thereof: Methods of forming ferromagnetic liners on the top surface and sidewalls of conductive lines of magnetic memory devices. The ferromagnetic liners increase the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. In one embodiment, an in-bound pole...

20060019489 - Method for forming storage node contact of semiconductor device: Disclosed is a method for forming a storage node contact of a semiconductor device. In such a method, there is provided a substrate formed with gates and source/drain regions. A landing plug poly is formed between the gates, and an insulating interlayer is formed over the entire surface of the...

20060019488 - Method of forming a static random access memory with a buried local interconnect: An SRAM cell includes six transistors. The storage nodes are implemented using local interconnects. A first level of metal overlies the interconnects but is electrically isolated therefrom. Contact plugs are formed to couple the cell to the first level of metal. The contact plugs are preferably formed in a different...

20060019490 - Structure of gold bumps and gold conductors on one ic die and methods of manufacturing the structures: A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first...

20060019491 - Method for manufacturing a semiconductor device: Method for manufacturing a semiconductor device including a semiconductor substrate, an element formed on the substrate, and an insulating film formed on the element, includes: (a) forming a first conductive layer (b) forming a first insulating film on the upper portion of the first conductive layer; (c) forming a second...

20060019492 - Method for preventing a metal corrosion in a semiconductor device: The present invention relates to a method for preventing a metal corrosion in a semiconductor device. The present method includes the steps of etching of a metal layer in a chamber, the metal layer having a photoresist pattern thereon or thereover; oxidizing a surface of the metal layer using a...

20060019493 - Methods of metallization for microelectronic devices utilizing metal oxide: A metal oxide is deposited on a substrate in a semiconductor fabrication metallization process is patterned and subsequently reduced to a more conductive form, such as elemental metal. The metal oxide is reduced by exposure to at least one reducing agent or current that is capable of removing oxygen from...

20060019494 - Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor: Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the...

20060019495 - Atomic layer deposition of tantalum-containing materials using the tantalum precursor taimata: In one example of the invention, a method for depositing a tantalum-containing material on a substrate in a process chamber is provided which includes exposing the substrate to a tantalum precursor that contains TAIMATA and to at least one secondary precursor to deposit a tantalum-containing film during an atomic layer...

20060019496 - Method for fabricating copper-based interconnections for semiconductor device: Cu-based interconnections are fabricated in a semiconductor device by depositing a thin film of Cu or Cu alloy on a dielectric film by sputtering, the dielectric film having trenches and/or via holes at least one groove and being arranged on or above a substrate, and carrying out high temperature and...

20060019497 - Reduced feature-size memory devices and methods for fabricating the same: This disclosure relates to systems and methods for reducing feature sizes. One of these methods enables formation of an original feature having a size in a length or width dimension of between about 100 and about 1000 nanometers with a system capable of patterning features to a minimum size of...

20060019498 - Barc/resist via etchback process: A BARC or other sacrificial fill layer etch comprises a selective etch chemistry of Ar/O2/CO. The BARC etch may be used in a via-first dual damascene method. After via (116) pattern and etch, a BARC/sacrificial fill layer (120) is deposited to fill the via (116) and coat the IMD (110)....

20060019499 - Method of forming passivation layer in semiconductor device: Provided is a method of forming a passivation layer of a semiconductor device, using a high density plasma-enhanced chemical vapor deposition (HDPCVD) in order to form an excellent film without a void between metal lines which are being narrower. During the process of HDPCVD that utilizes SiH4 and O2 gas...

20060019501 - Methods of forming a thin layer including hafnium silicon oxide using atomic layer deposition and methods of forming a gate structure and a capacitor including the same: Methods of forming a thin film include applying a first reactant to a substrate, chemisorbing a first portion of the first reactant and physisorbing a second portion of the first reactant on the substrate, applying a first oxidizer to the substrate, chemically reacting the first oxidizer with the first portion...

20060019500 - Ultraviolet blocking layer: Semiconductor structures and methods of fabricating semiconductor structures are disclosed. The method comprises the steps of: providing an initial semiconductor structure; forming a non-silicon layer overlying the initial semiconductor structure, the non-silicon layer having an extinction coefficient greater than zero at wavelengths below about 300 nanometers; and performing a plasma-based...

20060019502 - Method of controlling the film properties of a cvd-deposited silicon nitride film: We have discovered that adding H2 to a precursor gas composition including SiH4, NH3, and N2 is effective at improving the wet etch rate and the wet etch rate uniformity across the substrate surface of a-SiNx:H films which are deposited on a substrate by PECVD. Wet etch rate is an...

20060019503 - Laser crystallization apparatus and laser crystallization method: A laser crystallization apparatus which capable of correcting both shift in imaging position caused by thermal lens effect of the imaging optical system and shift due to flatness of the substrate comprises an crystallization optical system which irradiates laser light to a thin film disposed on the substrate to melt...

20060019504 - Forming a plurality of thin-film devices: An aspect of the present invention is a method for forming a plurality of thin-film devices. The method includes coarsely patterning at least one thin-film material on a flexible substrate and forming a plurality of thin-film elements on the flexible substrate with a self-aligned imprint lithography (SAIL) process....

20060014303 - Layered ceramic electronic part and manufacturing method thereof: A monolithic ceramic electronic component includes a low-permeability coil portion formed by stacking low-permeability ceramic green sheets, a first coil and a relatively large number of pores, and a high-permeability coil portion formed by stacking high-permeability ceramic green sheets, a second coil and a relatively small number of pores. The...

20060014304 - Superconductor and process for producing the same: A superconductor and a method for producing the same are provided. The method for producing a superconductor includes the step of forming a superconducting layer on a base layer by performing a film deposition at least three times, wherein the film thickness of a superconducting film in each film deposition...

20060014307 - Ferroelectric random access memory capacitor and method for manufacturing the same: The method for manufacturing an FeRAM capacitor with a merged top electrode plate line (MTP) structure is employed to prevent a detrimental impact on the FeRAM and to secure a reliable FeRAM device. The method includes steps of: preparing an active matrix obtained by a predetermined process; forming a first...

20060014306 - Magnetic random access memory array with thin conduction electrical read and write lines: An MTJ MRAM cell is formed between ultra-thin orthogonal word and bit lines of high conductivity material whose thickness is less than 100 nm. Lines of this thickness produce switching magnetic fields at the cell free layer that are enhanced by a factor of approximately two for a given current....

20060014305 - Mtj patterning using free layer wet etching and lift off techniques: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be patterned using a wet etch technique. A cap layer is formed over the free layer after the free layer is patterned. The cap layer is...

20060014308 - Procedure for arranging chips of a first substrate on a second substrate: The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the...

20060014309 - Temporary chip attach method using reworkable conductive adhesive interconnections: A method for temporary chip attach to determine known good die using a reworkable conductive adhesive interconnection between the chip carrier and die. The die is easily separated from the chip carrier after test, without the use of potentially damaging shear forces, by subjecting the TCA assembly to a rework...

20060014310 - Resonant cavity iii-nitride light emitting devices fabricated by growth substrate removal: A semiconductor light emitting device includes an n-type region, a p-type region, and light emitting region disposed between the n- and p-type regions. The n-type, p-type, and light emitting regions form a cavity having a top surface and a bottom surface. Both the top surface and the bottom surface of...

20060014311 - Method of manufacturing semiconductor laser element: A method of manufacturing a semiconductor laser element having an enhanced yield ratio is provided. The semiconductor laser element having a cladding layer, an intermediate layer, and a capping layer is manufactured as follows. At the laminating step, a plurality of lamination layers are laminated in a laminating direction. Subsequently,...

20060014312 - Method for stripping sacrificial layer in mems assembly: The present invention provides methods of manufacturing a MEMS assembly. In one embodiment, the method includes mounting a MEMS device, such as a MEMS mirror array, on an assembly substrate, where the MEMS device has a sacrificial layer over components formed therein. The method also includes coupling an assembly lid...

20060014313 - Microelectronic imaging units and methods of manufacturing microelectronic imaging units: Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality...

20060014314 - Image sensor with light guides: An image sensor device and fabrication method thereof. An image sensing array is formed in a substrate, wherein the image sensing array comprises a plurality of photosensors with spaces therebetween. A first dielectric layer with a first refractive index is formed overlying the spaces but not the photosensors. A conformal...

20060014315 - Stable, water-soluble quantum dot, method of preparation and conjugates thereof: A method for manufacturing powdered quantum dots comprising the steps of: a) reacting quantum dots comprising a core, a cap and a first ligand associated with the outer surfaces thereof with a second ligand, the second ligand displacing the first ligand and attaching to the outer surfaces of the quantum...

20060014318 - Electronic component having at least one semiconductor chip on a circuit carrier and method for producing the same: An electronic component includes at least one semiconductor chip, which has an active chip top side with contact areas and has a chip rear side arranged on a carrier top side of a circuit carrier. The circuit carrier and the chip top side are covered by a common rewiring layer...

20060014317 - Integrated circuit package having reduced interconnects: A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating...

20060014316 - Method of making a semiconductor chip assemby with a metal containment wall and a solder terminal: A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a metal containment wall and a solder layer in which the metal containment wall includes a cavity and the solder terminal contacts the metal containment wall in the cavity, mechanically attaching a semiconductor chip...

20060014319 - Castellation wafer level packaging of integrated circuit chips: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When...

20060014320 - Method of manufacturing semiconductor device: Insulating films (13, 14) are formed on the surface of a semiconductor wafer (30) on the side on which a plurality of devices are formed. Then, conductor layers (15, 16) are formed to cover opening portions from which electrode pads (12) of each device are exposed. Furthermore, a resist layer...

20060014321 - Manufacturing method of semiconductor device and manufacturing method of lead frame: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes...

20060014322 - Methods and apparatuses relating to block configurations and fluidic self-assembly processes: An apparatus and methods of making an electronic assembly. The electronic assembly comprises a functional block having at least one asymmetric feature. The functional block comprises an integrated circuitry to perform a function pertaining to the electronic assembly. The electronic assembly further comprises a substrate having a receptor site to...

20060014324 - Method and apparatus for cutting away excess synthetic resin from synthetic resin package of electronic component: A method is provided for cutting excess synthetic resin 7, which projects from a resin package 6 of an electronic component, at the root connected to the package, the excess synthetic resin being produced in molding the resin package. The excess synthetic resin 7 is cut by laying a thin...

20060014323 - Thermal interface material with fluid: A thermal interface material is provided to insert into a gap (49) between a heat sink (20) and a heat source (30) in order to dissipate heat from the heat source. The gap has air (51) therein. The thermal interface material may include a fluid (11) and a number of...

20060014326 - Method for fabricating a semiconductor component with contacts situated at the underside: A semiconductor component has a housing with a first main area and a second main area opposite to the first main area, which surrounds at least one semiconductor chip. The semiconductor chip has a first metallization layer on a first main side. A second main side of the semiconductor chip...

20060014325 - Method of assembling a semiconductor component and apparatus therefor: A method of assembling a semiconductor component includes providing a pedestal, placing a first piece on the curved pedestal, wherein the first piece comprises a semiconductor die, placing a second piece over the first piece, and providing an adhesive between the first piece and the second piece. The method further...

20060014327 - Method of fabricating pcb including embedded passive chip: Disclosed is a method of fabricating a PCB including an embedded passive chip, in which the passive chip is mounted on the PCB and an insulator is then laminated on the PCB, or in which a blind hole for receiving the passive chip is formed in the PCB and the...

20060014328 - Resin encapsulation molding for semiconductor device: According to a resin encapsulation molding method for a semiconductor device, a resin-encapsulated substrate having a semiconductor device that is mounted on the substrate and that has a portion exposed is formed. With the method, a device-mounted substrate on which the semiconductor device is mounted is prepared and then the...

20060014329 - Nanodots formed on silicon oxide and method of manufacturing the same: A nanodot material including nanodots formed on silicon oxide, and a method of manufacturing the same, is provided. The nanodot material includes a substrate, a silicon oxide layer, and a plurality of nanodots on the silicon oxide layer....

20060014331 - Floating-body dram in tri-gate technology: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A...

20060014330 - Method for manufacturing soi wafer: The present invention provides a manufacturing method for an SOI wafer with a high productivity in which generation of a void is suppressed in manufacturing the SOI wafer. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer...

20060014332 - Soi device having increased reliability and reduced free floating body effects: The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology....

20060014333 - Anchoring, by lateral oxidizing, of patterns of a thin film to prevent the dewetting phenomenon: The invention relates to a thin film having a thickness of less than 10 nm, made of oxidizable semi-conductor material and patterned in the form of patterns. To prevent the dewetting phenomenon of said patterns, lateral oxidized zones are arranged at the periphery of each pattern of the thin film...

20060014334 - Method of fabricating heterojunction devices integrated with cmos: A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may be selective or not and the epitaxial layer may be formed so as to...

20060014335 - Method of manufacturing a semiconductor device: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order...

20060014336 - Method of forming double-gated silicon-on-insulator (soi) transistors with corner rounding: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer,...

20060014337 - Semiconductor device and method for manufacturing the same: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source...

20060014338 - Method and structure for strained finfet devices: A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device....

20060014339 - Method of detecting one or more defects in a string of spaced apart studs: A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each...

20060014340 - Semiconductor device and method of manufacturing the same: According to an aspect of the invention, there is provided a semiconductor device provided with a CMOS-FET circuit, comprising at least one of a tensile stress film disposed in a part of an element isolating film around an NMOS forming region and having a tensile stress, and a compressive stress...

20060014341 - Method for fabricating a gate mask of a semiconductor device: A nitride layer of the gate mask for the semiconductor device is deposited at a temperature higher than 750 deg. C. so as to release hydrogen from the nitride layer. Alternatively, a nitride layer of the gate mask for the semiconductor device is deposited in a gas atmosphere with use...

20060014342 - Method of manufacturing a semiconductor component: A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above...

20060014343 - Method for forming a capacitor for an integrated circuit and integrated circuit: Integrated circuits can include an integrated capacitor with a metal alloy layer. Methods for forming such integrated circuits can include providing a substrate, forming a first electrode including depositing a metal alloy layer having a first surface and an exposed second surface, etching the exposed second surface of the metal...

20060014344 - Methods of forming semiconductor structures and capacitor devices: The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the...

20060014346 - Magnetic random access memory array with thin conduction electrical read and write lines: An MTJ MRAM cell is formed between or below an intersection of ultra-thin orthogonal word and bit lines of high conductivity material whose thickness is less than 100 nm. Lines of this thickness produce switching magnetic fields at the cell free layer that are enhanced by a factor of approximately...

20060014347 - Semiconductor integrated circuit device having single-element type non-volatile memory elements: A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is...

20060014345 - Uniform channel programmable erasable flash eeprom: A new method to form a split gate for a flash device in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A film is deposited overlying the substrate. The film comprises a second dielectric layer overlying a first dielectric layer with an electronic-trapping...

20060014348 - Method for fabricating a mask rom: The present invention discloses a method for fabricating a buried bit line of a mask ROM. The method includes providing a semiconductor substrate with a photoresist layer, and patterning the photoresist layer to form a photoresist pattern. A first ion implantation process is performed to form a first doped region...

20060014349 - Planarized and silicided trench contact: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce...

20060014350 - Method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions: A method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions is provided. A silicon substrate having thereon a poly gate structure is prepared. The poly gate structure has sidewalls and a top surface. An offset spacer is formed on its sidewall. An ion implantation process is carried out...

20060014351 - Low leakage mos transistor: A method of forming a low leakage MOS transistor. The transistor includes a gate on a substrate with at least two first spacers adjacent to the gate. A first doped region is formed under each first spacer and a second doped region is formed adjacent to each first doped region,...

20060014352 - Method and apparatus providing cmos imager device pixel with transistor having lower threshold voltage than other imager device transistors: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions...

20060014353 - Semiconductor device and manufacturing method therefor: To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method for the semiconductor device, an n-type silicon layer is deposited on a p-type silicon...

20060014354 - Method of making transistor with strained source/drain: A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in the semiconductor substrate at respective locations where a source region and a drain region are to be formed, epitaxially...

20060014355 - Semiconductor device and method of manufacturing the same: Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal...

20060014356 - Metal-insulator-metal capacitor and method of fabricating same: A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second...

20060014357 - Structure and method of making an enhanced surface area capacitor: A method of making a capacitor structure having an enhanced plate surface area is provided. In such method, a mandrel is provided which has a major surface having an array of features including at least one of: a plurality of first features protruding upward or a plurality of second features...

20060014358 - Method for microfabricating structures using silicon-on-insulator material: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the...

20060014359 - Formation of active area using semiconductor growth process without sti integration: A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body....

20060014361 - Method for forming device isolation layer of semiconductor device: A method for forming a device isolation device of a semiconductor device is disclosed. The method includes the steps of forming a moat pattern for forming a trench on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermined thickness by using the moat pattern, forming...

20060014360 - Semiconductor device and method of fabricating the same: A method of fabricating a semiconductor device includes forming a coating type carbon film on a semiconductor substrate, patterning the coating type carbon film according to trenches formed in the semiconductor substrate and having different opening widths, and etching the semiconductor substrate with the patterned coating type carbon film serving...

20060014362 - Methods of forming shallow trench isolation structures in semiconductor devices: Methods of forming a shallow trench isolation structures in semiconductor devices are disclosed. A disclosed method comprises forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate; forming a trench defining first and second active areas by etching the second oxide layer, the nitride...

20060014363 - Thermal treatment of a semiconductor layer: A method for forming a structure that includes a layer that is removed from a donor wafer that has a first layer made of a semiconductor material containing germanium. The method includes the steps of forming a weakness zone in the thickness of the first layer; bonding the donor wafer...

20060014364 - Semiconductor device and semiconductor wafer and a method for manufacturing the same: The semiconductor device 1 has a semiconductor chip 10 (first semiconductor chip) and a semiconductor chip 20 (second semiconductor chip). The semiconductor chip 20 is formed on the semiconductor chip 10. The semiconductor chip 20 is constituted by comprising a semiconductor substrate 22. The semiconductor substrate 22, which is an...

20060014365 - Method for fabricating a semiconductor element from a dispersion of semiconductor particles: Provided is a method for forming a semiconductor element such as film. The method comprises the steps of: (i) depositing a suspension of particles of a first semiconductor and a solution of a second semiconductor or a precursor thereof on a surface of a substrate such that a mixture comprising...

20060014366 - Control of strain in device layers by prevention of relaxation: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance....

20060014367 - Nucleation and deposition of platinum group metal films using ultraviolet irradiation: A method of depositing a platinum based metal film by CVD deposition includes bubbling a non-reactive gas through an organic platinum based metal precursor to facilitate transport of precursor vapor to the chamber. The platinum based film is deposited onto a non-silicon bearing substrate in a CVD deposition chamber in...

20060014368 - Method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes: A method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes includes forming a transparent conductive film on a GaN layer, forming a transparent conductive hetero-junction of opposing electrical characteristics on a transparent conductive film on the surface of the GaN layer through an ion diffusion process, and...

20060014369 - Stud electrode and process for making same: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell...

20060014370 - Methods for processing integrated circuit packages formed using electroplating and apparatus made therefrom: An integrated circuit package is processed by electroplating the integrated circuit package. The electroplating is performed without forming plating traces on a conductive surface of a pad side of the integrated circuit package. Pad areas of the integrated circuit package are thus plated with one or more materials. An integrated...

20060014371 - Method for forming an integrated semiconductor circuit arrangement: Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained....

20060014373 - Method for finishing metal line for semiconductor device: A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface...

20060014372 - Semiconductor device and method for fabricating the same: The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad;...

20060014374 - Layer assembly and method for producing a layer assembly: The invention relates to a layer arrangement and to a process for producing a layer arrangement. The layer arrangement has a layer which is arranged on a substrate and includes a first subregion comprising decomposable material and a second subregion which is arranged next to the first subregion and has...

20060014375 - Soluble carbon nanotubes: A method of solubilizing carbon nanotubes. Carbon nanotubes, and urea are mixed together and then heated....

20060014376 - Stacked via-stud with improved reliability in copper metallurgy: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of...

20060014377 - Method for forming passivation film of semiconductor device and structure of passivation film of semiconductor device: Disclosed are a method of manufacturing a semiconductor device and a structure of a semiconductor device. A method of forming a passivation film of a semiconductor device comprises the steps of forming metal wires on a semiconductor substrate, forming a buffer oxide film being a first passivation film on the...

20060014378 - System and method to form improved seed layer: A method is disclosed to form a seed layer for an integrated circuit. The method may include depositing a metal seed layer (106) over a barrier layer (104) such that the metal seed layer (106) has a greater thickness along a top surface portion (114) of at least one recessed...

20060014380 - Production method for wiring structure of semiconductor device: In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring films formed protrusively above tops of the first insulating film among...

20060014379 - Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a...

20060014382 - Method for forming an interconnection line in a semiconductor device: The CD uniformity of a damascene pattern and the reliability of interconnection lines may be enhanced when a semiconductor device is manufactured by a method including: forming a first insulating layer on a semiconductor substrate, the first insulating layer having a contact hole partially exposing the substrate; forming a photoresist...

20060014381 - Method for forming interconnection line in semiconductor device using a phase-shift photo mask: A method for forming a dual damascene structure. The method includes depositing an interlayer dielectric on an underlying layer, depositing a photoresist on the interlayer dielectric, and exposing and developing the photoresist by using a phase-shift photo mask to form a photoresist pattern having trench patterns and hole patterns. The...

20060014384 - Method of forming a layer and forming a capacitor of a semiconductor device having the same layer: In a method of forming a layer using an atomic layer deposition process, after a substrate is loaded into a chamber, a first reactant is provided onto the substrate. The first reactant is partially chemisorbed on the substrate. A second reactant is introduced into the chamber to form a preliminary...

20060014385 - Method of forming titanium nitride layer and method of fabricating capacitor using the same: A method of fabricating a storage capacitor includes depositing a first titanium nitride layer on a dielectric layer using a chemical vapor deposition technique or an atomic layer deposition technique performed at a first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas at a predetermined...

20060014383 - Method of producing semiconductor single crystal wafer and laser processing device used therefor: A method of manufacturing single-crystal semiconductor wafers is characterized in that a plurality of single-crystal semiconductor wafers of a relatively small diameter desired by users are cut out from a single-crystal semiconductor wafer of a relatively large diameter. Therefore, there can also be obtained a secondary effect that even if...

20060014386 - Small grain size, conformal aluminum interconnects and method for their formation: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain...

20060014387 - Silicide formation using a low temperature anneal process: A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer 10 and performing a first low temperature anneal to create the silicide 160. The method further includes removing an unreacted portion of...

20060014388 - Wafer processing apparatus & methods for depositing cobalt silicide: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti—along with layers of Co—are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence,...

20060014389 - Method of manufacturing semiconductor device: In a MOS semiconductor device in which a SOI substrate made of an extremely thin film is used, a polycrystalline silicon film is formed through contact holes provided in a thin insulating film on a source and a drain. Then, a relatively thick insulating film is provided thereon and formed...

20060014390 - Slurry composition, polishing method using the slurry composition and method of forming a gate pattern using the slurry composition: A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry...

20060014391 - Method of manufacturing a semiconductor device using a cleaning composition: A metal-containing pattern structure is formed on a semiconductor substrate, and a cleaning composition is applied to the semiconductor substrate. The cleaning composition includes, based on a total weight of the cleaning composition, about 78 wt % to about 99.98 wt % of an acidic aqueous solution, about 0.01 wt...

20060014392 - Method for producing a semiconductor component and a semiconductor component produced according to the method: A method is for producing a semiconductor component, e.g., a multilayer semiconductor element, e.g., a micromechanical component, e.g., a pressure sensor, having a semiconductor substrate, e.g., made of silicon, and a semiconductor component produced according to the method. To reduce the production cost of such a semiconductor component, in a...

20060014393 - Process method to facilitate silicidation: The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide...

20060014394 - Process for low temperature, dry etching, and dry planarization of copper: The subject invention pertains to a method and apparatus for etching copper (Cu). The subject invention can involve passing a halide gas over an area of Cu such that CuX, or CuX and CuX2, are formed, where X is the halide. Examples of halides which can be utilized with the...

20060014395 - Method of manufacturing displays and apparatus for manufacturing displays: A method of manufacturing displays, includes at least forming a metal pattern on a surface of an insulating substrate, forming an insulating film on the metal pattern, forming a pattern of a photosensitive resin on the insulating film, and forming a contact hole in the insulating film with the film...

20060014396 - Method for forming a resist protect layer: A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for...

20060014398 - Method of forming dielectric layer using plasma enhanced atomic layer deposition technique: A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the...

20060014397 - Methods for the reduction and elimination of particulate contamination with cvd of amorphous carbon: A method is provided for forming an amorphous carbon layer, deposited on a dielectric material such as oxide, nitride, silicon carbide, carbon doped oxide, etc., or a metal layer such as tungsten, aluminum or poly-silicon. The method includes the use of chamber seasoning, variable thickness of seasoning film, wider spacing,...

20060014399 - Low-temperature plasma-enhanced chemical vapor deposition of silicon-nitrogen-containing films: A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film...

20060014400 - Method for fabricating a buried metallic layer in a semiconductor body and semiconductor component having a buried metallic layer: A method for fabricating a buried metallic layer at a predetermined vertical position in a semiconductor body having a first and second side includes a step of applying a metal layer to one of the first and second sides at least in sections. The method also includes establishing a positive...

20060008927 - Dual gated finfet gain cell: A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device....

20060008925 - Electronic parts cleaning solution: (EO is an oxyethylene group, and PO is an oxypropylene group. x and y, and a and b are positive number, which x(x+y) and a(a+b) are 0.05 to 0.5 respectively, and z and c are positive integers. R is a residue group wherein hydrogen atoms are removed from hydroxyl group...

20060008926 - Semiconductor fabrication that includes surface tension control: In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a surface tension lowering agent....

20060008928 - Process for producing fine particles of bismuth titanate: It is an object to provide fine particles of bismuth titanate having excellent dielectric characteristics, high crystallinity and a small particle diameter, and a process for their production. The object is accomplished by a process which comprises a step of obtaining a melt comprising, as represented by mol % based...

20060008929 - Method and apparatus for the improvement of material/voltage contrast: A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal...

20060008930 - Color filter, manufacturing method thereof, electrooptical device and electronic equipment: A method for manufacturing a color filter having a picture element part surrounded by a partition wall and provided in the plural number on a substrate including a step of forming the partition wall that has a lyophobic quality on the substrate, step of forming a lyophilic layer in the...

20060008931 - Method for electro-luminescent display fabrication: The present invention discloses a method for fabricating a pixel area of an electro-luminescent display device. At least one buffer layer is formed on a substrate. An etch stop layer is formed on the buffer layer. At least one intermediate layer is formed over the etch stop layer. The intermediate...

20060008932 - Liquid crystal display device having driving circuit and method of fabricating the same: A polycrystalline silicon thin film transistor of a bottom gate structure is used as a switching element and a mask having transmissive, half-transmissive and blocking areas is used so that an array substrate for a liquid crystal display device having a monolithic driving circuit can be fabricated through a six-mask...

20060008933 - Method for producing an integrated pin diode and corresponding circuit: An explanation is given of, inter alia, a method for fabricating an integrated pin photodiode which contains a buried region (20) and a terminal region (32) leading to the buried region (20). This fabrication method enables the pin photodiode (14) to be integrated in a simple manner. Moreover, there is...

20060008934 - Micromechanical actuator with multiple-plane comb electrodes and methods of making: A micro-electro-mechanical component comprising a movable element with comb electrodes, and two stationary elements with comb electrodes aligned and stacked on each other but electrically insulated by a layer of insulation material. The movable element is supported by multiple torsional hinges and suspended over a cavity such that the element...

20060008936 - Method for manufacturing semiconductor physical quantity sensor: A method for manufacturing a semiconductor physical quantity sensor is provided. The sensor includes a multi-layered substrate, a cavity, a groove, a movable portion and a fixed portion. The multi-layered substrate includes a support substrate, an embedded insulation film, and a semiconductor layer. The method includes the steps of: preparing...

20060008935 - Physical quantity sensor and method for manufacturing the same: A physical quantity sensor includes: a semiconductor substrate; a cavity disposed in the substrate and extending in a horizontal direction of the substrate; a groove disposed on the substrate and reaching the cavity; a movable portion separated by the cavity and the groove so that the movable portion is movably...

20060008937 - Technique for fabricating multilayer color sensing photodetectors: A multilayer color-sensing photodetector is fabricated in a semiconductor wafer having a single crystal structure to form a first, second and third layer of single crystal semiconductor material. A dielectric layer is formed that completely surrounds each single crystal region. A blocking layer is applied to prevent ion implantation where...

20060008938 - Photodiode with ultra-shallow junction for high quantum efficiency cmos image sensor and method of formation: A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019...

20060008939 - Image sensor package: An image sensor package includes a substrate, a frame layer, a photosensitive chip, wires, and transparent layer. The substrate has an upper surface on which first electrodes are formed, and a lower surface on which second electrodes are formed, wherein the each first electrode is curved. The frame layer is...

20060008940 - Method for fabricating photodiode of cmos image sensor: A method for fabricating a photodiode of a CMOS image sensor is disclosed, to improve a charge accumulation capacity in the photodiode, which includes the steps of defining a semiconductor substrate as an active area and a field area by forming an STI layer; firstly implanting impurity ions for formation...

20060008941 - Growth of planar, non-polar a-plane gallium nitride by hydride vapor phase epitaxy: Highly planar non-polar a-plane GaN films are grown by hydride vapor phase epitaxy (HVPE). The resulting films are suitable for subsequent device regrowth by a variety of growth techniques...

20060008942 - Systems and methods for harvesting and integrating nanowires: The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into...

20060008943 - Mounting semiconductor chips: To mount semiconductor chips (3), the chips are placed in a liquid (5), and drops (51) of the liquid containing no more than one semiconductor chip are positioned on a substrate (2). On the substrate are molecules of a first type (1), on the semiconductor chips (3) are molecules of...

20060008946 - Castellation wafer level packaging of integrated circuit chips: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When...

20060008945 - Integrated circuit stacking system and method: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention,...

20060008944 - Substrate having built-in semiconductor apparatus and manufacturing method thereof: A substrate having a built-in semiconductor apparatus includes: a semiconductor apparatus which comprises a first semiconductor chip having a first electrode pad formed on a main surface thereof, a protruding portion which is in contact with the first semiconductor chip and protrudes from a side surface of the first semiconductor...

20060008947 - Semiconductor device: A method of manufacturing a semiconductor device includes the steps of, (1) preparing a conductive substrate having a main surface and a back surface opposite to the main surface, (2) forming at the main surface of the conductive substrate a plurality of first grooves, which are parallel to each other,...

20060008948 - Method of processing a semiconductor wafer for manufacture of semiconductor device: A method of processing a semiconductor wafer that has a first surface and a second surface opposite to the first surface. The method includes forming grooves of a predetermined depth on the second surface on which circuit patterns are formed, attaching a first surface of a protective tape to the...

20060008949 - Electronic package having a folded flexible substrate and method of manufacturing the same: An electronic package is provided and its method of construction. A microelectronic die is mounted to a flexible substrate. A mold cap is injection-molded over the die. The mold cap has a curved convex edge surface around which the flexible substrate wraps. Folding of the flexible substrate is controlled by...

20060008950 - Vertical tunneling transistor: The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an axis through the channel and the quantum dot is substantially perpendicular to the substrate. A gate may be disposed so that an axis...

20060008951 - Process monitor and system for producing semiconductor: A sensor on a semiconductor wafer is used as a process monitor and a capacitor is employed as a power supply for the sensor. The capacitor can be formed by stacking a poly-silicon layer and a silicon nitride layer on the wafer. A timer can be used to specify an...

20060008952 - Fabrication method of thin film transistor: A TFT fabrication method includes: forming a gate insulation layer, a semiconductor layer and a metal layer on a substrate in sequence, which cover a gate; patterning the metal layer and the semiconductor layer; forming a patterned first passivation layer on the substrate and exposing the patterned metal layer; forming...

20060008954 - Methods for integrating replacement metal gate structures: Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate...

20060008953 - Structure of ltps-tft and method of fabricating channel layer thereof: A LTPS-TFT structure comprising a cap layer, a polysilicon film and a gate is provided. The cap layer is disposed over the substrate with a gap between the two. The polysilicon film is disposed over the cap layer and is divided into a channel region and a source/drain region on...

20060008955 - Semiconductor device, method of manufacturing the same, and electro-optical device: The present invention is directed to a method of manufacturing a semiconductor device including a semiconductor layer having a heavily doped source region, a heavily doped drain region, a lightly doped source region, a lightly doped drain region and a channel region, and a gate electrode opposite to the semiconductor...

20060008956 - Method for manufacturing thin film transistor, electro-optical device and electronic apparatus: A method for manufacturing a thin film transistor results in a thin film transistor including a semiconductor film, a channel region provided in the semiconductor film, source and drain regions sandwiching the channel region, and a gate electrode facing the channel region with an intermediary of a gate insulating film....

20060008957 - Method of fabricating poly-crystalline silicon thin film and method of fabricating transistor using the same: A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using ICP-CVD. After the ICP-CVD, ELA is performed while increasing energy by predetermined steps. A poly-Si active layer and...

20060008958 - Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer: A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P...

20060008960 - Fabrication of an eeprom cell with sige source/drain regions: An EEPROM memory cell uses silicon-germanium/silicon and emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage with respect to a well. The source/drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more....

20060008959 - Layer arrangement and memory arrangement: The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a substrate and at least one respectively laterally...

20060008962 - Manufacturing method of semiconductor integrated circuit device: The invention is directed to a semiconductor integrated circuit device having a plurality of gate insulation films of different thicknesses where reliability of the gate insulation films and characteristics of MOS transistors are improved. A photoresist layer is selectively formed on a SiO2 film in first and third regions, and...

20060008963 - Method for forming polysilicon local interconnects: Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity,...

20060008961 - Method of forming mos transistor having fully silicided metal gate electrode: Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is...

20060008964 - Method for manufacturing semiconductor device: In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity in the gate electrodes. After the heat treatment,...

20060008965 - Hardmask for forming ferroelectric capacitors in a semiconductor device and methods for fabricating the same: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack....

20060008966 - Memory utilizing oxide-conductor nanolaminates: Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes...

20060008967 - Thermoplastic molding process and apparatus: A system and method for forming an article from thermoplastic material and fiber. The method includes heating thermoplastic material to form a molten thermoplastic material for blending with the fiber. The molten thermoplastic material is blended with the fibers to form a molten composite material having a concentration of fiber...

20060008968 - Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second...

20060008969 - Method of forming dielectric film: A method of forming a dielectric film by an organic metal CVD method, comprising the step of supplying an organic metal compound into a treating container having a substrate to be treated held therein to form the dielectric film on the substrate, wherein the dielectric film forming step comprises the...

20060008971 - Method for fabricating shallow trench isolation layer of semiconductor device: A method for fabricating an STI layer of a semiconductor device is disclosed, to improve the integration of the semiconductor device in a method of increasing a moat area for a gate line by minimizing an isolation area between moat areas, which includes the steps of forming a sacrificial layer...

20060008970 - Optimized plating process for multilayer printed circuit boards having edge connectors: A process for manufacturing printed wire boards with hard plated sliding contact tabs and soft plated wire bond pads. Sliding contact tabs are covered by a protective coating after being hard plated thus allowing the soft plating of wire bond pads without damaging the hard plated sliding contact tabs. In...

20060008972 - Method of forming trench isolation in the fabrication of integrated circuitry: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing...

20060008973 - Selective oxide trimming to improve metal t-gate transistor: A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers....

20060008974 - Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument: A groove is formed on a semiconductor substrate having integrated circuits and electrodes from a first surface. An insulating layer is formed on an inner surface of the groove. A conductive layer is formed on the insulating layer above the inner surface of the groove. A second surface of the...

20060008975 - Wafer with vertical diode structures: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The...

20060008976 - Novel random access memory (ram) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes: A process for fabricating a novel random access memory (RAM) capacitor in a shallow trench isolation (STI) The method utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel photoresist mask is used to etch bottle-shaped recesses in...

20060008977 - Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of...

20060008978 - Decoupling capacitor for high frequency noise immunity: Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate, and a top plate layer disposed on...

20060008979 - Methods of forming buried bit line dram circuitry: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within...

20060008980 - Zero cost non-volatile memory cell with write and erase features: A memory device includes a coupling capacitor and a field-effect transistor. The coupling capacitor is formed from (1) a first dopant region in a second dopant region on a substrate, (2) a gate dielectric atop the first dopant region, and (3) a first gate conductor atop the gate dielectric. The...

20060008981 - Flash memory cell and fabricating method thereof: A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are...

20060008987 - Method for forming a floating gate memory with polysilicon local interconnects: Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity,...

20060008989 - Method for forming an array with polysilicon local interconnects: Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity,...

20060008983 - Method for manufacturing a multiple-gate charge trapping non-volatile memory: A method for manufacturing a multiple-gate memory cell which comprises a semiconductor body and a plurality of gates arranged in series and the semiconductor body includes first forming a plurality of gates spaced apart by about a gate width, forming an isolation layer on the sidewalls, and filling between the...

20060008988 - Method of forming a memory cell: Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity,...

20060008985 - Method of forming a tunneling insulating layer in nonvolatile memory device: A method of forming a tunneling insulating layer having a size smaller than the size obtained by the resolution of a photolithography process is provided. The method includes the steps of forming a first insulating layer and a second insulating layer on a substrate, forming a re-flowable material layer pattern...

20060008986 - Method of manufacturing a semiconductor device: When memory cells of EEPROM and a capacitor element are formed on a same semiconductor substrate, the number of processes is prevented from increasing and a manufacturing cost is reduced. Furthermore, reliability of the capacitor element is improved, and characteristics of the memory cells, a MOS transistor, and so on...

20060008982 - Method of recording information in nonvolatile semiconductor memory: In one example, a nonvolatile semiconductor memory includes a transistor, one or two resistance-change portions, and one or two charge accumulation portions. The transistor has a control electrode, first main electrode region, and second main electrode region. If two resistance-change portions are provided, one of them is provided in the...

20060008984 - Methods of forming split-gate non-volatile memory cells including raised oxide layers on field oxide regions and split-gate non-volatile memory cells so formed: A method of forming a split-gate non-volatile memory cell can include forming first and second adjacent floating gates self-aligned to a field oxide region therebetween. An oxide layer is formed covering the first and second adjacent floating gates and the field oxide region, the oxide layer electrically isolates the first...

20060008990 - Method for fabricating cell transistor of flash memory: A method for fabricating a cell transistor of a flash memory including a device isolation film is disclosed, to prevent the mouse bite and the residue of a gate electrode, which includes the steps of forming a moat pattern of STI structure on a semiconductor substrate; forming a shallow trench...

20060008991 - Trenched semiconductor devices and their manufacture: In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the...

20060008992 - Semiconductor integrated circuit device and a method of manufacturing the same: The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode...

20060008993 - Method of manufacturing flash memory device: Disclosed is a method of manufacturing a flash memory device using a STI process. Isolation films of a projection structure becomes isolation films of a nipple structure by means of a slant ion implant process and a wet etching process. A polysilicon layer is removed until the tops of the...

20060008994 - Semiconductor device and method of manufacturing the same: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer...

20060008995 - Method for manufacturing semiconductor device: On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural...

20060008997 - Atomic layer deposition of interpoly oxides in a non-volatile memory device: Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer...

20060008999 - Creating a dielectric layer using ald to deposit multiple components: A dielectric layer is created for use with non-volatile memory and/or other devices. The dielectric layer is created using atomic layer deposition to deposit multiple components whose mole fractions change as a function of depth in the dielectric layer in order to create a rounded bottom of a conduction band...

20060008996 - Method for fabricating semiconductor device by using radical oxidation: The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a substrate; forming a nitride layer on the insulation layer; selectively etching...

20060008998 - Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates: The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å...

20060009000 - Method of fabricating coil-embedded inductor: A method of fabricating a coil-embedded inductor provides steps for obtaining uniform density of coil-embedded inductor. The cavity of a first die is filled with dust before being flipped, and then filled with dust a second time. The dust in the cavity is pressed only once for improving the density....

20060009001 - A recessed polysilicon gate structure for a strained silicon mosfet device: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the...

20060009002 - Method for producing a transistor structure: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the...

20060009003 - Methods for nanowire growth: The present invention is directed to methods to produce, process, and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides a method for producing nanowires that includes providing a thin film of a catalyst material with varying thickness on a substrate, heating the substrate and thin film, such that...

20060009004 - Method of forming trench isolation within a semiconductor substrate: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch...

20060009005 - Chemical mechanical polishing for forming a shallow trench isolation structure: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on...

20060009007 - Integrated circuit having a device wafer with a diffused doped backside layer: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or...

20060009006 - Method for wafer bonding (al, in, ga)n and zn(s, se) for optoelectronic applications: A method for producing a wafer bonded structure between (Al, In, Ga)N and Zn(S,Se). A highly reflective and conductive distributed Bragg reflector (DBR) for relatively short optical wave lengths can be fabricated using Zn(S,Se) and MgS/(Zn, Cd)Se materials. Using wafer bonding techniques, these high-quality DBR structures can be combined with...

20060009008 - Method for the laser processing of a wafer: A method for the laser processing of a wafer having a plurality of devices which are composed of a laminate consisting of an insulating film and a functional film on the front surface of a substrate, the method comprising applying a pulse laser beam along streets for sectioning the plurality...

20060009009 - Dicing sheet, manufacturing method thereof, and manufacturing method of semiconductor apparatus: A dicing sheet which supports electronic-component aggregation with adhesive in the case of separating the electronic-component aggregation in which a plurality of electronic components are integrated, has a substrate and an adhesion layer which is formed at one surface side of the substrate, in which a concave portion is formed...

20060009010 - Wafer dividing method: A wafer processing method of dividing a wafer having function elements formed in areas sectioned by dividing lines formed on the front surface in a lattice pattern, into individual chips along the dividing lines, which comprises a deteriorated layer forming step for forming a deteriorated layer in the inside of...

20060009011 - Method for recycling/reclaiming a monitor wafer: The present invention provides a method for recycling/reclaiming a monitor wafer and a method for testing a manufacturing process. The method for recycling/reclaiming the monitor wafer, among other steps, includes providing a monitor wafer having a number of front surface defects thereon (110), and annealing the monitor wafer in a...

20060009012 - Methods of fabricating semiconductor heterostructures: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer...

20060009013 - Method for manufacturing polysilicon layer and a tft using the same: A method for manufacturing polysilicon layer is provided. At first, a substrate is provided. An amorphous silicon layer having a second region and a first region is formed on the substrate. The first region is thicker than the second region. The amorphous silicon layer is completely melted to form a...

20060009014 - Method of fabricating a poly-crystalline silicon thin film and method of fabricating a semiconductor device using the same: A method of fabricating a poly-crystalline silicon thin film, and a method of fabricating a semiconductor device using the same, includes implanting predominantly neutralized ions into an amorphous silicon thin film formed on a substrate. The thin film may be annealed. Glass, silicon and other substrates, such as heat intolerant...

20060009015 - Method of manufacturing a semiconductor device and semiconductor manufacturing apparatus: A technique for manufacturing TFTs having little dispersion in their electrical characteristics is provided. Contamination of a semiconductor film is reduced by performing oxidation processing having an organic matter removing effect, forming a clean oxide film, after removing a natural oxide film formed on a semiconductor film surface. TFTs having...

20060009016 - Laser irradiation method and apparatus: An objective of the present invention is to provide a laser crystallizing method capable of suppressing a thermal damage on a substrate as well as enhancing a substrate processing efficiency, and a laser irradiation apparatus using the laser crystallizing method. Laser lights oscillated from plural laser oscillating apparatuses are synthesized...

20060009017 - Method of crystallizing semiconductor film and method of manufacturing display device: Conventional methods of crystallizing a semiconductor film through scanning with a pulse laser have had a problem in that variation in particle diameter or shape of a crystal grain causes variation in characteristics of a thin film transistor, which lowers display quality of a liquid crystal display. In view of...

20060009018 - Method for manufacturing semiconductor device: [Object] To activate dopant after forming a thermally unstable layer. [Solving Means] A doped region in a semiconductor substrate is activated by irradiation of electromagnetic waves having a main spectrum peak at a wavelength of 1.1 μm or less. The efficiency of electromagnetic wave absorption of the silicon substrate increases...

20060009020 - Method of forming wiring pattern: A photoresist pattern is formed on an insulating substrate so that it has a reverse tapered cross section and a reverse pattern of a wiring pattern to be formed. Next, a nanoparticles-containing ink is injected on a wiring region using an inkjet system, followed by a leveling process, a drying...

20060009019 - Methods of forming metal nitride, and methods of forming capacitor constructions: The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric material is formed from a non-halogenated metal-containing precursor, and the portion...

20060009021 - Structure formation: A method for making a structure includes depositing a solution upon a surface and irradiating the solution with microwaves to crystallize solute of the solution on the surface....

20060009022 - Method for forming robust solder interconnect structures by reducing effects of seed layer underetching: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier...

20060009023 - Methods of forming electronic structures including conductive shunt layers and related structures: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the...

20060009024 - Method for forming a metal line in a semiconductor device: Provided is a method for forming a metal line in a semiconductor device. The method forms round portions at top edges of an insulation film by means of a polymer and then etches the rest portion (i.e., sidewall parts) in an almost vertical direction, which makes it possible to shrink...

20060009025 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device, including the steps of: forming first and second insulation films on a substrate; sequentially forming an organic sacrificing layer and first and second mask layers thereon; forming a wiring groove pattern in the second mask layer; forming a connection hole pattern for forming...

20060009026 - Method of fabricating wiring board: In a wiring board fabrication method including a wiring formation process using a damascene method, via holes reaching an underlying wiring layer are formed in an interlayer insulating layer formed on the underlying wiring layer, smears caused at that time are removed, and then a photosensitive permanent resist layer is...

20060009028 - Anti-reflective coating doped with carbon for use in integrated circuit technology and method of formation: The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies. One particular disclosed film is an anti-reflective coating, and...

20060009027 - Method and structure to improve properties of tunable antireflective coatings: A method for improving the properties of tunable etch resistant anti-reflective coatings (TERA) is disclosed. The method includes annealing the deposited layer of TERA in an environment containing at least one of hydrogen and deuterium. The annealed layer has an increased concentration of hydrogen and/or deuterium as compared to the...

20060009031 - Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrate - therein: The present invention discloses a method including providing a substrate; forming a dielectric over the substrate, the dielectric having a k value of about 2.5 or lower, the dielectric having a Young's modulus of elasticity of about 15 GigaPascals or higher; forming an opening in the dielectric; and forming a...

20060009030 - Novel barrier integration scheme for high-reliability vias: Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a...

20060009029 - Wafer level through-hole plugging using mechanical forming technique: A wafer is provided having at least one through-hole therein. The at least one through-hole is filled with one or more conductive balls. Thereafter, the wafer is compressed wherein the one or more conductive balls form a conductive plug in the at least one through-hole. After forming the conductive plug...

20060009032 - Manufacturing method for semiconductor device having a t-type gate electrode: This invention provides a semiconductor device manufacturing method including forming a T type gate electrode having a wide region in an upper portion, the method including steps of: forming rectangular gate polysilicon; forming a nitride film covering the polysilicon; forming an oxide film thick on the nitride film; etching back...

20060009033 - Defect-free thin and planar film processing: The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely...

20060009034 - Methods for depositing tungsten layers employing atomic layer deposition techniques: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation...

20060009035 - Method for forming polysilicon local interconnects: Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity,...

20060009036 - High thermal cycle conductor system: The present invention provides to a method for the production of metallized ceramic substrates that demonstrate superior adhesion characteristics when surface mounted components are soldered to their surface metallization(s) and that provide superior stability when the completed circuits are exposed to high-temperature storage conditions....

20060009037 - Method for fabricating metal line in a semiconductor: A metal line is fabricated in a semiconductor device by a method including: forming an etch stop layer on a substrate; forming an interlayer insulating layer on the etch stop layer, the interlayer insulating layer including dual damascene patterns, each respectively having a trench and a via contact hole; forming...

20060009038 - Processing for overcoming extreme topography: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to...

20060009039 - Etching method, etching apparatus, and method for manufacturing semiconductor device: In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched....

20060009040 - Method for manufacturing semiconductor device: A method for manufacturing a semiconductor device including a substrate to be processed having a conductive layer essentially consisting of platinum includes etching the conductive layer, and generating plasma and cleaning the substrate, to which an etching product adhere, by means of ions in the plasma. The cleaning includes heating...

20060009041 - Silicon nitride film with stress control: An assembly comprises a multilayer nitride stack having nitride etch stop layers formed on top of one another, each of the nitride etch stop layers is formed using a film forming process. A method of making the multilayer nitride stack includes placing a substrate in a single wafer deposition chamber...

20060009042 - Methods of forming openings, and methods of forming container capacitors: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second...

20060009043 - Methods of forming a composite dielectric structure and methods of manufacturing a semiconductor device including a composite dielectric structure: Some methods that are provided form a composite dielectric structure on a substrate. A first dielectric layer that includes metal and oxygen is formed on a substrate. A preliminary dielectric layer that includes silicon is formed on the first dielectric layer. A plasma nitriding treatment is performed on the preliminary...

20060009044 - Method for forming insulating film on substrate, method for manufacturing semiconductor device and substrate-processing apparatus: A substrate-processing apparatus (100, 40) comprises a radical-forming unit (26) for forming the nitrogen radicals and oxygen radicals through a high-frequency plasma, a processing vessel (21) in which a substrate (W) to be processed is held, and a gas-supplying unit (30) which is connected to the radical-forming unit. The gas-supplying...

20060009045 - Method of manufacturing semiconductor device: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer...

20060009046 - Manufacturing method of polymetal gate electrode: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W...

20060009047 - Modular tool unit for processing microelectronic workpieces: A modular apparatus for thermally processing a microelectronic workpiece is provided. The modular apparatus comprises a mounting module having a rotatable carousel assembly configured to support at least one workpiece. A driver is coupled to the carousel assembly and rotates the carousel assembly, moving the workpiece between a loading station,...

20060003468 - Method for applying a layer to a hydrophobic surface: A method of forming a coating. The method includes: providing a substrate having a surface; forming a layer of water on the surface; and forming a layer of a material on the layer of water....

20060003467 - Method for producing an electromagnetic radiation-emitting semiconductor chip and a corresponding electromagnetic radiation-emitting semiconductor chip: In a method of fabricating a radiation-emitting semiconductor chip based on AlGaInP, comprising the method steps of preparing a substrate, applying to the substrate a semiconductor layer sequence comprising a photon-emitting active layer, and applying a transparent decoupling layer comprising(Gax(InyAl1-y)1-xP wherein 0.8≦x and 0≦y≦1, it is provided according to the...

20060003470 - Phase-change random access memory device and method for manufacturing the same: Disclosed are a phase-change random access memory device and a method for manufacturing the same, capable of improving a driving speed of the phase-change random access memory by reducing a contact surface between a bottom electrode and a phase-change layer. The phase-change random access memory device includes a first insulation...

20060003472 - Polymer-based ferroelectric memory: Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers...

20060003469 - Process for fabrication of a ferrocapacitor: In a process for fabricating a ferrocapacitor comprising providing ferroelectric PZT elements over an Al2O3 layer, the Al2O3 layer is covered with a seed layer comprising layers of PZT and TiO2. Then a thicker layer of PZT is formed over the seed layer and crystallized. By this process, the crystallinity...

20060003471 - Self-aligned, low-resistance, efficient memory array: The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages...

20060003473 - Semiconductor device having ferroelectric material capacitor and method of making the same: The present invention relates to the field of a semiconductor device having a ferroelectric material capacitor and method of making the same. The semiconductor device includes a capacitor having a triple-level oxygen barrier layer pattern formed by an oxygen barrier metal layer, a material layer formed of a conductive solid...

20060003476 - Method for the production of multilayer discs: A Method for manufacturing an optical disc substrate comprises a first substrate with at least one structured surface, on which an anti-adhesive layer, preferably carbon, is deposited and first layer on top of said anti-adhesive layer. On a second substrate with a structured surface also a layer is deposited. Both...

20060003474 - Roll-to-sheet manufacture of oled materials: A method for making organic light-emitting diodes on a flexible substrate includes supplying a flexible substrate, forming a plurality of thin-film layers on the flexible substrate to produce an organic light-emitting diode, disposing the flexible substrate above a barrier base and disposing a barrier cover over the substrate and the...

20060003475 - Semiconductor devices shared element(s) apparatus and method: Two or more semiconductor devices (21 and 22) are formed on a substrate (20) and are each comprised of a plurality of printed components (23 and 24). At least one such printed component (25) is shared by both such semiconductor devices....

20060003477 - Method for producing a light source provided with electroluminescent diodes and comprising a luminescence conversion element: The invention describes a method for producing a light-emitting-diode (LED) light source, particularly comprising mixed-color LEDs, wherein at least a portion of primary radiation emitted by a chip is transformed by luminescence conversion. Said chip comprises a front-side (i.e., the side facing in the direction of radiation) electrical contact to...

20060003478 - Method of manufacturing display device: Arrangements (e.g., methods) for manufacturing a display device, including irradiating an amorphous semiconductor film formed on a substrate with an excimer laser beam to convert the amorphous semiconductor film into a polycrystalline semiconductor film; and irradiating predetermined areas of the polycrystalline semiconductor film intermittently with a continuous wave laser beam...

20060003479 - Method for fabricating liquid crystal display device of color-filter on transistor type: A method for fabricating a color-filter on transistor (COT) type LCD device, to improve the yield by simplifying the fabrication process with diffraction exposure, which includes the steps of forming a gate line, a gate electrode, a gate pad and a data pad on a substrate; depositing a gate insulating...

20060003480 - Method of manufacturing thick dielectric pattern and method of manufacturing image displaying apparatus: In the forming method of a thick dielectric pattern, a photosensitive dielectric paste layer relatively low in a softening point is formed on a substrate, and on this substrate, a photosensitive dielectric paste layer relatively high in a softening point is formed, and these paste layers are exposed and developed...

20060003481 - Method for fabricating semiconductor components using conductive layer and grooves: A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The method includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns...

20060003482 - Elastomeric cmos based micro electromechanical varactor: A micro electro-mechanical system (MEMS) variable capacitor is described, wherein movable comb electrodes of opposing polarity are fabricated simultaneously on the same substrate and are independently actuated. The electrodes are formed in an interdigitated fashion to maximize capacitance. The MEMS variable capacitor includes CMOS manufacturing steps in combination with elastomeric...

20060003483 - Optoelectronic packaging with embedded window: A method and apparatus for encapsulating optoelectronic components. An optical semiconductor die is attached to a lead frame or a substrate. A solid window transparent to light and no larger than the die area, excluding wire bond pads, is cut, scored, or otherwise singulated from glass or plastic. A transparent...

20060003484 - Using deuterated source gasses to fabricate low loss gesion sion waveguides: The present invention provides a method of manufacturing optical devices which includes the steps of providing a substrate and forming at least one optical layer on the substrate. The optical layer is formed by a chemical vapor deposition (CVD) process which includes a deuterated source gas. The present invention also...

20060003485 - Devices and methods of making the same: Devices including a substantially transparent dielectric and methods of forming such devices are disclosed....

20060003486 - Plasma treatment method for electromigration reduction: A plasma treatment method which is capable of extending the MTF (mean-time-to-failure) of metal interconnects fabricated on a semiconductor wafer substrate, is disclosed. The invention includes providing a trench typically in a dielectric layer on a substrate; depositing a metal in the trench; and exposing the metal to a nitrogen-based...

20060003487 - Low power consumption oled material for display applications: Some embodiments of the present invention are directed to OLED materials useful in display devices and processes for making such OLED materials. The OLED materials may comprise polar compounds integrated with one or more substrates. When the polar compounds are simultaneously cured and exposed to an applied voltage or electric...

20060003488 - Display pixel and method of fabricating the same: A display pixel having higher aperture ratio and method of fabricating the same. The method of fabricating a display pixel in accordance with the invention includes the steps of providing a substrate and simultaneously forming a transistor and a rugged capacitor on adjacent portions thereof, wherein the rugged capacitor comprises...

20060003489 - One mask pt/pcmo/pt stack etching process for rram applications: A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top...

20060003491 - Apparatus for ejecting relatively thin ic chip from semiconductor wafer: An apparatus and method for ejecting a thin IC chip from a UV-sensitive tape attached to a bottom face of a semiconductor wafer, includes a vacuum holder that partly supports the UV-sensitive tape by applying vacuum force. The apparatus further includes an ejecting block inserted in the vacuum holder and...

20060003490 - Method of manufacturing nitride semiconductor device: A nitride semiconductor device is manufactured by the step of forming a nitride semiconductor layer form on a GaN substrate main surface, the step of polishing a back surface of the GaN substrate formed with the above-mentioned nitride semiconductor layer, the step of dry etching the back surface of the...

20060003492 - Substrate based unmolded package: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and...

20060003493 - Integrated metallic contact probe storage device: A mass storage device includes a probe that has a cantilever having a first end region operatively connected to a substrate and a second end region rotated in a direction such that the second end region is opposed to the first end region. A tip is disposed on the second...

20060003495 - Method for fabricating an electronic component embedded substrate: A method for fabricating an electronic component embedded substrate including an electronic component that is embedded within a buildup layer is disclosed. The method includes a first buildup layer lamination step of laminating plural first buildup layers on a core substrate such that the total thickness of the first buildup...

20060003494 - Stacked package electronic device: An electrical component includes a substrate, a first integrated circuit attached to the substrate, a metal portion coupled to the first integrated circuit, and a second integrated circuit attached to the first integrated circuit. The metal portion is sandwiched between the first integrated circuit and the second integrated circuit....

20060003496 - Modified chip attach process and apparatus: A method of packaging a die includes reflowing the solder to electrically connect the die to a substrate at a first temperature, cooling the die and substrate to a second temperature, and placing a heated epoxy in contact with the die and the substrate. The method also includes holding the...

20060003497 - Semiconductor device packages including hermetic packaging elements for at least partially encapsulating conductive elements and other package elements for protecting the portions of semiconductor devices not covered by the hermetic package elements, and: A semiconductor device package includes a semiconductor device and at least one conductive element in communication with a contact of the semiconductor device. A hermetic package element encapsulates at least a portion of the conductive element and the contact from which the conductive element protrudes or extends. Another element of...

20060003498 - Designing method for a semiconductor display device, manufacturing method for the semiconductor display device, semiconductor display device, and order receiving system for the semiconductor display device using the designing method: Irrespective of a specification of the controller, a plurality of TFTs are formed for the controller on a substrate in advance. Then, in accordance with a design of the controller, connection is achieved among sources, drains, and gates, which serve as three terminals in each of the plural TFTs, appropriately...

20060003499 - Removing a high-k gate dielectric: A metal oxide layer on a substrate is converted at least partly to a metal layer. At least part of the metal layer is covered by an oxidation resistant cover. The covered layer and underlying metal may be removed, for example, using acid....

20060003500 - Epitaxial siox barrier/insulation layer: A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be...

20060003501 - Method of fabricating semiconductor device and semiconductor fabricated by the same method: A method of fabricating a semiconductor device and a semiconductor device fabricated by the same method are disclosed. The method includes: depositing a silicon layer containing amorphous silicon on a substrate using any one of a plasma enhanced chemical vapor deposition (PECVD) method and a low pressure chemical vapor deposition...

20060003502 - Method of fabricating semiconductor device and semiconductor fabricated by the same method: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; defining source and drain regions by doping the silicon layer with impurity ions; crystallizing the amorphous silicon by an annealing process under an atmosphere of H2O...

20060003505 - Method of fabricating display device: A method of fabricating a display device is provided. The method includes providing a substrate having a pixel region and a circuit region located at the periphery of the pixel region. A first semiconductor layer and a second semiconductor layer are formed on the pixel region and on the circuit...

20060003504 - Method of fabricating thin film transistor using metal induced lateral crystallization by etch-stopper layer patterns: A method of forming wires of a poly-crystalline TFT by crystallizing an amorphous silicon thin film using a metal film is provided. The wires forming method includes the steps of: removing a MILC metal film; forming etch-stopper layer patterns on at least part of respective source and drain regions formed...

20060003503 - Thin film transistor and method for fabricating the same: A thin film transistor that has improved characteristics and uniformity is developed by uniformly controlling low concentration of crystallization catalyst and controlling crystallization position so that no seed exists and no grain boundary exists, or one grain boundary exists in a channel layer of the thin film transistor. The thin...

20060003506 - Crystallization method and apparatus thereof: A method of crystallizing an amorphous silicon thin film on a substrate includes loading a substrate onto a stage, the substrate having an amorphous silicon thin film thereon and having first and second regions, performing a first crystallization by irradiating a laser beam on the first region of the amorphous...

20060003507 - Integrated circuit devices including a dual gate stack structure and methods of forming the same: Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of...

20060003509 - Method of forming a gate structure for a semiconductor device and method of forming a cell gate structure for a non-volatile memory device: In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the...

20060003508 - Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control...

20060003510 - Technique for transferring strain into a semiconductor region: A dislocation region is formed by implanting a light inert species, such as hydrogen, to a specified depth and with a high concentration, and by heat treating the inert species to create “nano” bubbles, which enable a certain mechanical decoupling to underlying device regions, thereby allowing a more efficient creation...

20060003513 - Formation of standard voltage threshold and low voltage threshold mosfet devices: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second...

20060003511 - Method of fabricating a semiconductor device with multiple gate oxide thicknesses: The individual performance of various transistors is optimized by tailoring the thickness of the gate oxide layer to a particular operating voltage. Embodiments include forming transistors with different gate oxide thicknesses by initially depositing one or more gate oxide layers with intermediate etching to remove the deposited oxide from active...

20060003512 - Methods of forming semiconductor circuitry: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive...

20060003514 - Method of forming ohmic contact to a semiconductor body: A process for forming an ohmic contact on the back surface of a semiconductor body includes depositing a donor layer on the back surface of the semiconductor body followed by a sintering step to form a shallow intermetallic region capable of forming a low resistance contact with a contact metal....

20060003515 - Phase-change memory device and method for manufacturing the same: Disclosed are a phase-change memory device and its manufacturing method, which can reduce a contact area between a bottom electrode and a phase-change layer, thereby reducing the quantity of current necessary for phase change. The phase-change memory device comprises: bottom electrodes and top electrodes formed on a dielectric interlayer, each...

20060003516 - Flash memory devices on silicon carbide: A flash memory device is fabricated with a silicon carbide substrate. The substrate has doped source/drain regions for each memory transistor. A tunneling dielectric is formed above the substrate and substantially between the source drain regions. A floating gate is formed on top of the tunneling dielectric with an oxide...

20060003517 - Atomic layer deposited zr-sn-ti-o films using tii4: A dielectric film containing Zr—Sn—Ti—O formed by atomic layer deposition using a TiI4 precursor and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing titanium and oxygen onto a substrate surface by atomic layer deposition...

20060003519 - Method for fabricating cmos image sensor: A method for fabricating a CMOS image sensor is disclosed, to decrease a dark current, which includes the steps of forming a photodiode area in a semiconductor substrate; forming a plurality of gates including a first gate on the semiconductor substrate, wherein the first gate has one side aligned to...

20060003518 - Method for fabricating field-effect transistor structures with gate electrodes with a metal layer: Provided is a method for fabricating gate electrode structures each having at least one individual polysilicon layer and a metal layer. A polysilicon layer is provided and patterned prior to the application of the gate metal. Trenches between the resulting gate structures are filled, and the polysilicon is drawn back...

20060003520 - Method for forming semiconductor device with modified channel compressive stress: A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate....

20060003521 - Method of and apparatus for manufacturing semiconductor device: A damaged layer which is necessarily produced on the exposed surface of an interconnect by flattening of a surface of a substrate for forming interconnect according to a damascene process is restored, making it possible to manufacture semiconductor devices with a high yield. A semiconductor device is manufactured by preparing...

20060003522 - Semiconductor device substrate with embedded capacitor: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a...

20060003523 - Void free, silicon filled trenches in semiconductors: The present invention provides methods of producing substantially void-free trench structures. After deposition of an a-Si or polysilicon layer in a trench formed in a semiconductor, the a-Si or polysilicon is exposed to hydrogen at an elevated temperature....

20060003525 - Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor: A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further...

20060003524 - Method for forming trench memory cell structures for drams: One embodiment of the invention relates to a method for forming trench memory cell structures having trench capacitors and planar selection transistors. An implantation for forming a reinforcement implant for improving the electrical connection of a storage electrode of a trench capacitor to a first source/drain zone of the respective...

20060003526 - Integrated circuit arrangement comprising a capacitor, and production method: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the...

20060003527 - Bird's beak-less or sti- less otp eprom: The present invention facilitates semiconductor fabrication by maintaining uniform thickness of a gate oxide layer (112) during the oxide growth process of non-volatile memory devices (100). The uniform thickness of a gate oxide layer (112) is obtained by defining the boundaries of the source and drain areas (110) of a...

20060003528 - Flash memory with metal-insulator-metal tunneling program and erase: The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the control gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the control gate and a write/erase bit line. In one...

20060003529 - Dielectric storage memory cell having high permittivity top dielectric and method therefor: A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and...

20060003530 - Semiconductor memory device and method for fabricating the same: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed...

20060003531 - Non-volatile memory and method of manufacturing floating gate: A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots....

20060003532 - Semiconductor device and method of manufacturing therefor: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling...

20060003533 - Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer...

20060003534 - Salicide process using bi-metal layer and method of fabricating semiconductor device using the same: A salicide process using a bi-metal layer and method of fabricating a semiconductor substrate using the same are disclosed herein. The salicide process includes forming a main metal layer on a semiconductor substrate containing silicon. A main metal alloy layer containing at least one species of alloy element is formed...

20060003535 - Apparatus and method for controlling diffusion: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host...

20060003536 - Method for fabricating a trench capacitor with an insulation collar which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell: The present invention provides a method for fabricating a trench capacitor with an insulation collar (10) in a substrate (1), which is electrically connected to the substrate (1) on one side via a buried contact, having the steps of: providing a trench (5) in the substrate (1) using a hard...

20060003537 - Methods for forming capacitor structures: The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a substrate. The organic material is contacted with a chemical mechanical polishing pad and a polishing fluid to remove the organic material from the substrate. The polishing fluid...

20060003539 - Method for fabricating capacitor in semiconductor memory device: Disclosed is a method for fabricating a capacitor in a semiconductor memory device. The method includes the steps of: sequentially forming a first insulation layer and a first etch stop layer on a substrate; forming a plurality of contact holes by etching the first insulation layer and the first etch...

20060003538 - Method of forming capacitor of semiconductor device: Disclosed is a method of forming a capacitor of a semiconductor device which can secure a desired leakage current characteristic while securing a desired charging capacitance. The inventive method of forming a capacitor of a semiconductor device comprises steps of: forming a bottom electrode on a semiconductor substrate with a...

20060003540 - Marker for alignment of non-transparent gate layer, method for manufacturing such a marker, and use of such a marker in a lithographic apparatus: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is...

20060003541 - Method for forming device isolation film of semiconductor device: A method for forming device isolation film of semiconductor device is provided, the method including sequentially forming a pad oxide layer and a pad nitride layer on a semiconductor substrate having a cell region and a peripheral circuit region, etching a predetermined region of the pad nitride layer, the pad...

20060003542 - Method of oxidizing object to be processed and oxidation system: A method of oxidizing an object to be processed comprises the steps of: providing an object to be processed W having a groove 4 formed on its surface in a processing vessel 22 capable of forming a vacuum therein, oxidizing the surface of the object to be processed in an...

20060003543 - Methods of forming trench isolation regions: The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to...

20060003544 - Methods of forming trench isolation regions: The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to...

20060003545 - Method of making scratch resistant coated glass article including layer(s) resistant to fluoride-based etchant(s): A method is provided for making a coated article including an anti-etch layer(s) that is resistant to attacks by at least some fluoride-based etchant(s) for at least a period of time. In certain example embodiments, an anti-etch layer(s) is provided on a glass substrate in order to protect the glass...

20060003546 - Gap-filling for isolation: A method of filling high ratio trenches on a substrate is described. First, an oxidizable layer is deposited on the substrate. Thereafter, a trench fill oxide is deposited on the substrate and on the oxidizable layer. Afterwards, the resulting structure is annealed using an oxygen containing gas such that the...

20060003549 - Assemblies including semiconductor substrates of reduced thickness and support structures therefor: A fabrication substrate for use in fabricating integrated circuits and other electronic devices includes a substrate that comprises semiconductor material, as well as a support structure on an active surface of the substrate. The support structure is located at or adjacent to an entire outer peripheral edge of the substrate....

20060003547 - Highly compliant plate for wafer bonding: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer,...

20060003548 - Highly compliant plate for wafer bonding: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer,...

20060003550 - Method for ultra thinning bumped wafers for flip chip: In an improved method for bumped wafer thinning, a wafer is provided having a front side and a back side wherein contact pads are formed on the top surface. A dry film is formed on the front side of the wafer and openings are provided in the dry film to...

20060003553 - Method of separating layers of material: A lift off process is used to separate a layer of material from a substrate by irradiating an interface between the layer of material and the substrate. According to one exemplary process, the layer is separated into a plurality of sections corresponding to dies on the substrate and a homogeneous...

20060003551 - Ultra-thin die and method of fabricating same: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results...

20060003552 - Wafer dividing method: A wafer dividing method for dividing a wafer along a first set of plural streets extending parallel to each other, and a second set of plural streets extending parallel to each other and extending perpendicularly to the first set of the streets, the wafer having a plurality of rectangular regions...

20060003555 - Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting...

20060003554 - Structure and method for manufacturing planar soi substrate with multiple orientations: The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single...

20060003556 - Method of growing semi-insulating gan layer: Disclosed herein is a method for growing a semi-insulating GaN layer with high sheet resistance by controlling the size of grains through changes in growth temperature at the initial growth stage of the layer, without doping of dopants. The method comprises the steps of growing a buffer layer on a...

20060003557 - Atomic layer deposition metallic contacts, gates and diffusion barriers: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic...

20060003559 - Apparatus and method for controlling diffusion: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host...

20060003558 - Method for fabricating semiconductor device and semiconductor device using the same: A method for fabricating a semiconductor device improves off-state leakage current and junction capacitance characteristics in a pMOS transistor. The method includes forming a device isolation layer defining an active area in a semiconductor substrate; and forming a channel ion implantation layer by an implantation of arsenic ions in a...

20060003560 - Method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure: The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the trench; providing a first liner mask layer on the partial filling;...

20060003561 - Method of making a semiconductor device having a strained semiconductor layer: An implant is performed in the P channel regions, while masking the N channel regions, to deeply amorphize a layer at the surface of a semiconductor layer. After this amphorization step, germanium is implanted into the amorphized layer. The germanium is implanted to a depth that is less than the...

20060003562 - Semiconductor-on-insulator constructions; and methods of forming semiconductor-on-insulator constructions: The invention encompasses a method of forming a semiconductor on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon,...

20060003563 - Coaxial cable connector installable with common tools: A coaxial connector may be configured with multiple interleaved concentric threads that reduce connector assembly threading requirements. A cable sheath stripping feature may be incorporated into the connector, eliminating the need for a separate sheath stripping tool. Also, a pair of internal rings may be added which co-operate to couple...

20060003564 - Wiring method: A method of forming a wiring in a thin-film transistor includes a step of providing a bank having a groove defined thereon, a step of placing a liquid material in a wiring formation area of the by depositing droplets of the liquid material, and a step of placing the liquid...

20060003565 - Method and apparatus for manufacturing semiconductor device: A semiconductor manufacturing apparatus has a first layer made of a film having a different component from a film having tungsten and a second layer made of the film having tungsten. The first layer is a polysilicon layer, and the second layer is a tungsten layer. On an exposed surface...

20060003566 - Methods and apparatuses for semiconductor fabrication utilizing through-wafer interconnects: Methods are provided for forming semiconductor packages utilizing a device-ready wafer having a through-wafer via interconnect. One exemplary method comprises etching a via extending from a first surface of the device-ready wafer and terminating within the wafer. The first surface of the device-ready wafer is contacted with a wafer contact...

20060003567 - Mosi2-sic nanocomposite coating, and manufacturing method thereof: Disclosed are the MoSi2—SiC nanocomposite coating layer formed on surfaces of refractory metals such as Mo, Nb, Ta, W and their alloys. The MoSi2—SiC nanocomposite coating layer is manufactured by forming a molybdenum carbide (MoC and MoC2) coating layers on the surfaces of the substrates at high temperature, and the...

20060003568 - Method for manufacturing tape wiring board: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the...

20060003569 - Semiconductor devices with permanent polymer stencil and method for manufacturing the same: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices....

20060003570 - Method and apparatus for electroless capping with vapor drying: Embodiments of the invention relate to a method and apparatus for forming an electroless capping layer over the copper features of a substrate including one or more vapor drying steps. An embodiment of the method includes vapor drying the substrate; optionally applying a dielectric clean solution to the substrate; optionally...

20060003571 - Method for forming contact hole in semiconductor device: Disclosed is a method for forming a plurality of contact holes in a semiconductor device. The method includes the steps of: forming an oxide-based layer on a substrate; forming an organic polymer layer on the oxide-based layer; forming a photoresist pattern on the organic polymer layer to form the plurality...

20060003572 - Method for improving a semiconductor device delamination resistance: A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer...

20060003573 - Method to fabricate aligned dual damacene openings: An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer;...

20060003574 - Method of forming a via contact structure using a dual damascene process: A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via...

20060003575 - Method of manufacturing electronic device: After forming an insulating film on an underlying layer, a resist pattern is formed on the insulating film. The insulating film is etched by using the resist pattern as a mask, thereby forming an insulating film pattern. Without removing the resist pattern, exposed portions of the underlying layer and the...

20060003576 - Dual damascene trench formation to avoid low-k dielectric damage: A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask...

20060003577 - Method of manufacturing a semiconductor device: To effectively reduce the dielectric constant of an interlayer insulation film including a low dielectric constant film of a porous structure, and easily realize a practical application of a semiconductor device having an ultrafine and highly reliable Damascene wiring structure. A first interlayer insulation film including a porous first low...

20060003578 - Method of manufacturing a semiconductor device: The present invention relates to a method of manufacturing a semiconductor device which may stably transfer an electrical signal by forming a plurality of via holes and contact holes to an underlying conductive layer. According to the present invention, even though a contact or via is electrically shorted, it is...

20060003579 - Interconnects with direct metalization and conductive polymer: Embodiments include an interconnect or trace of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a via formed on the dielectric layer and to the contact surface. The via sidewalls and perimeter are layered with a manganese oxide (MnO2) layer which is...

20060003580 - Under bump metallurgy process on passivation opening: A method including electrodepositing a metal layer on a contact pad of a circuit, wherein the metal layer protrudes from the contact pad and has a width dimension greater than a width dimension of the pad. A method including forming a first layer on a contact pad in a contact...

20060003581 - Atomic layer deposited tantalum containing adhesion layer: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including...

20060003582 - Method for fabricating semiconductor device: The present invention relates to a method for fabricating a semiconductor device capable of preventing bridge formation caused by damages to a capacitor oxide structure including a phosphosilicate glass (PSG) layer and a tetraethylorthosilicate (TEOS) layer during a wet cleaning process. The method includes the steps of: forming a PSG...

20060003583 - Semiconductor structures: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy...

20060003585 - Method of making iron silicide and method of making photoelectric transducer: A solar cell comprises a substrate, and a metal electrode layer, a p-i-n junction, and a transparent electrode layer which are successively laminated on the substrate. The p-i-n junction comprises an n layer, an i layer, and a p layer which are laminated in this order. The i layer is...

20060003584 - Nickel-silicon compound forming method, semiconductor device manufacturing method, and semiconductor device: A nickel-silicon compound forming method is disclosed which comprises forming nickel on at least one of only silicon and a compound containing silicon, and performing stepwise-heating of the nickel together with the at least one of only silicon and the compound containing silicon....

20060003586 - Nonselective unpatterned etchback to expose buried patterned features: A method for etching to form a planarized surface is disclosed. Spaced-apart features are formed of a first material, the first material either conductive or insulating. A second material is deposited over and between the first material. The second material is either insulating or conductive, opposite the conductivity of the...

20060003587 - Grinding method for a sapphire wafer: The present invention discloses a grinding method for a sapphire wafer, wherein a sapphire wafer is firstly provided, and the sapphire wafer has a substrate and an electrically-conductive layer; the sapphire wafer is fixed onto a fixing base; the fixing base is further fixed to a machining table, and the...

20060003588 - Flash memory cells with reduced distances between cell elements: An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4...

20060003589 - Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization: A method for the post-etch cleaning of multi-level, damascene structures which minimizes, or substantially prevents, localized corrosion of underlying copper metallization comprises subjecting an intermediate structure in the fabrication of a multi-level, damascene structure, which structure includes an underlying copper metallization layer and an opening etched therein which exposes at...

20060003590 - Process for producing a mask on a substrate: To produce a mask, a first mask layer (40) is applied to the substrate (10). During or after the deposition of the first mask layer (40), the latter is exposed to an etching step. The etching step is carried out in such a manner that the material of the first...

20060003591 - Multi-step ebr process for photoresist removal: An edge bead removal process is disclosed. The process includes providing a wafer having a feature layer, coating a photoresist on the feature layer, rotating the wafer, and removing an edge bead from the wafer by removing an edge bump portion from the edge bead and removing an edge region...

20060003593 - Method and apparatus for stripping photo-resist: A method for stripping a photo-resist includes the steps of: (a) wet stripping a photo-resist off from a substrate; and (b) rinsing the substrate under high-speed conveyance using an aqua knife. A speed of the conveyance of the substrate is 0.2 m/s or higher. Because the aqua knife can rinse...

20060003592 - System and method for processing a substrate using supercritical carbon dioxide processing: A method and system for processing a substrate in a film removal system. The method includes providing the substrate in a substrate chamber of a film removal system, where the substrate has a micro-feature containing a dielectric film on a sidewall of the micro-feature and a photoresist film covering a...

20060003596 - Low temperature process for polysilazane oxidation/densification: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane...

20060003595 - Method of passivating oxide/compound semiconductor interface: The present invention provides a method of passivating an oxide compound disposed on a III-V semiconductor substrate. The method is intended for use with dielectric stacks, gallate compounds, and gallium compounds used in gate quality oxide layers. The method includes heating a semiconductor structure at an elevated temperature of between...

20060003594 - Molecules for langmuir-blodgett deposition of a molecular layer: A molecule for Langmuir-Blodgett (LB) deposition of a molecular layer. The molecule includes at least one switching moiety, a hydrophilicity-modifiable connecting group attached to one end of the moiety, and a hydrophilicity-non-modifiable connecting group attached to the other end of the moiety. The hydrophilicity-modifiable connecting group is transformable to a...

20060003597 - Enhanced nitride layers for metal oxide semiconductors: The performance of NMOS and PMOS regions of integrated circuits is improved. Embodiments of the invention include forming a first dielectric layer optimized for n-doped regions over the n-doped regions and forming a second dielectric layer optimized for p-doped regions over p-doped regions....

20060003598 - Gradient low k material: A thin film dielectric layer comprises a top portion and a bottom portion and has density and permittivity characteristics that vary substantially uniformly from the top portion to the bottom portion. Control over the density and/or permittivity is accomplished through varying deposition parameters such as flow rate of constituent process...

20060003599 - Semiconductor device and method for manufacturing same: A semiconductor device is provided which is capable of improving its reliability by using a material having a high relative dielectric constant as a material for its gate insulating film, by suppressing degradation of an EOT (Equivalent Oxide Thickness) and by preventing crystallization of the material having a high relative...

20060003600 - Contact planarization for integrated circuit processing: A method to form substantially planarized layers on a substrate. In an implementation, the method includes depositing a fluid material having at least one gap control bead onto a surface of the substrate, pressing a contact planarizer into the fluid material with a force sufficient to planarize at least a...

20060003601 - Method of forming fine patterns: It is disclosed a method of forming fine patterns comprising: subjecting a substrate having photoresist patterns to a hydrophilic treatment, covering the substrate having photoresist patterns with an over-coating agent for forming fine patterns, applying heat treatment to cause thermal shrinkage of the over-coating agent so that the spacing between...

20060003603 - Method and apparatus for processing: A method for forming an insulating film low in defects, in high throughput and with high reliability includes a first step of oxidizing an article employing a plasma having oxidizing species including ions to form an oxide film having a desired film thickness, and a second step of controlling an...

20060003602 - Semiconductor structures and methods of fabricating semiconductor structures comprising hafnium oxide modified with lanthanum, a lanthanide-series metal, or a combination thereof: Semiconductor structures and processes for fabricating semiconductor structures comprising hafnium oxide layers modified with lanthanum oxide or a lanthanide-series metal oxide are provided. A semiconductor structure in accordance with an embodiment of the invention comprises an amorphous layer of hafnium oxide overlying a substrate. A lanthanum-containing dopant or a lanthanide-series...