Semiconductor device manufacturing: process inventions 12/05

20050287684 - Apparatus and method for detecting soft breakdown of a dielectric layer of a semiconductor wafer: To detect soft breakdown of a dielectric layer of a semiconductor wafer, a DC current is caused to flow between a top surface of the dielectric layer and the semiconducting material of the semiconductor wafer. The DC current is either a constant value DC current, or a DC current that...

20050287685 - Localizing a temperature of a device for testing: Wafers or other structures comprising a plurality of dies or devices are tested at non-ambient temperatures by inducing a first heat flux through a substantial portion of a surface of the structure to modify a temperature of the structure and inducing a second heat flux through a local area of...

20050287683 - Method and apparatus for determining generation lifetime of product semiconductor wafers: To determine the generation lifetime of a pn junction of a semiconductor wafer, an elastically deformable, electrically conductive contact is caused to touch a surface of the semiconductor wafer over the pn junction. At least one reverse bias voltage is applied to the pn junction via the contact and a...

20050287689 - Method for manufacturing carbon fibers, method for manufacturing electron-emitting device using the same, method for manufacturing electronic device, method for manufacturing image display device, and information display reproduction apparatus using the s: Carbon fibers having superior properties are very uniformly formed on a substrate. A method for manufacturing carbon fibers is provided which has the steps of disposing laminates formed of a first catalyst material and particles containing a second catalyst material on the substrate, causing a reaction between the first and...

20050287687 - Method of fabricating algainp light-emitting diode and structure thereof: A soft transparent adhesive layer is utilized to bond a transparent substrate material onto an AlGaInP light-emitting diode epitaxy on a GaAs substrate, and the GaAs substrate is next removed entirely. Then, a mesa etching process is performed to form a first top surface and a second top surface on...

20050287686 - Method to improve water-barrier performance by changing film surface morphology: A method and apparatus for depositing a material layer onto a substrate is described. The method includes placing the substrate in a process chamber, delivering a mixture of precursors for the material layer into the process chamber, delivering a hydrogen gas into the process chamber to improve water-barrier performance of...

20050287688 - Water-barrier performance of an encapsulating film: A method and apparatus for depositing a material layer onto a substrate is described. The method includes delivering a mixture of precursors for the material layer into a process chamber and depositing the material layer on the substrate at low temperature. The material layer can be used as an encapsulating...

20050287691 - Method for doping quantum dots: A doping method for forming quantum dots is disclosed, which includes following steps: providing a first precursor solution for a group II element and a second precursor solution for a group VI element; heating and mixing the first precursor solution and the second precursor solution for forming a plurality of...

20050287690 - Optical microsystem and method for making same: The invention relates to the fabrication of optical microsystems for miniature cameras or miniature matrix displays. It is proposed that N dot matrix arrays and associated circuits should be collectively fabricated, on the front of a semiconductor wafer, to produce N identical chips, with on the side of each array,...

20050287692 - Method of manufacturing thin film transistor panel: A method of manufacturing a thin film transistor panel is provided, which includes forming a first signal line on a substrate. The method also includes forming in sequence a first insulating layer and a semiconductor layer on the first signal line. The method further includes patterning the semiconductor layer and...

20050287693 - Method for the passivation of the mirror-faces surfaces of optical semi-conductor elements: The aim of the invention is to simplify known passivation methods. According to said method, the semi-conductor elements are heated and cleaned in a high vacuum with a gaseous, reactive low-energy medium. A closed, insulating or slightly conductive, transparent protective layer is applied in-situ, said layer being inert in relation...

20050287694 - Wafer matching methods for use in assembling micromirror array devices: The invention provides a method for matching micromirror wafers and electrode wafers so as to form micromirror array devices while the production yield is maximized. Each micromirror wafer and/or electrode wafer may have one or more non-passing dies and a plurality of good dies. A set of matching schemes are...

20050287695 - Method for producing a for a tfa image sensor: The invention relates to a method for producing a photodiode contact for a TFA image sensor which includes a photodiode, produced by deposition of a multilayer system and a transparent conductive contact layer on an ASIC circuit that has been coated with an intermediate metal dielectric component and that has...

20050287696 - Waveguiding structures with embedded microchannels and method for fabrication thereof: The invention provides a method for fabricating planar waveguiding structures with embedded microchannels. The method includes the step of depositing, over a planar template having at least one indented feature comprising a ridge of a first optical material and a narrow trench adjacent thereto, a second optical material, and the...

20050287697 - Organic semicounductor device, process for producing the same, and organic semiconductor apparatus: The present invention provides an organic semiconductor device, which can be produced uniformly on a large substrate, having a high mobility and capable of greatly modulating the drain current by varying the voltage applied to a gate electrode. The present invention provides an organic semiconductor device having at least a...

20050287698 - Use of chalcogen plasma to form chalcogenide switching materials for nanoscale electronic devices: A method of forming a metal chalcogenide. A metal is provided and exposed to a chalcogen plasma to form the metal chalcogenide....

20050287699 - Electrical package employing segmented connector and solder joint: An electronic package is provided having a connector and a solder joint that is less susceptible to thermal fatigue. The package includes a die including a first electrically conductive connecting surface having a first coefficient of thermal expansion and a substrate including electrical circuitry and a second electrically conductive connecting...

20050287701 - Leadframe for a multi-chip package and method for manufacturing the same: A leadframe for multi-chip package (MCP) including a die pad and a plurality of leads. A dielectric layer is formed on the lower surface of the die pad, so that the die pad is etched to form an interconnecting conductor with a bonding region. An insulation layer is formed on...

20050287700 - Leadframe with a chip pad for two-sided stacking and method for manufacturing the same: A leadframe with a chip pad for two-sided stacking including a chip pad and a plurality of leads is disclosed. A dielectric adhesive layer is formed on the lower surface of the chip pad and is adhered onto a first trace layer, which has a connecting pad. At least a...

20050287702 - Methods for designing carrier substrates with raised terminals: A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The method may also include configuring the carrier substrate to include...

20050287704 - Carrier for substrate film: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments...

20050287703 - Multi-chip semiconductor connector assembly method: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die....

20050287706 - Electronic device package: An electronic device package is described that includes a non-metal die attached adhesive. The die attach is positioned in discrete positions on a surface to which the die will be fixed. The die is placed on the discrete die attach. The die attach, in an embodiment, is an epoxy resin...

20050287705 - Flip chip on leadframe package and method for manufacturing the same: A flip chip on leadframe package includes a leadframe, a non-flow underfilling material and a flip chip. The leadframe has a plurality of inner leads. Each inner lead has an upper surface and a lower surface. A coating region is defined on the upper surfaces. The non-flow underfilling material is...

20050287707 - Method for fabricating semiconductor packages: A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in...

20050287708 - Semiconductor chip package manufacturing method including screen printing process: A method for manufacturing a semiconductor chip package may include screen printing an adhesive on a substrate using a screen printing mask. The adhesive may be heated during a first curing process. A semiconductor chip may be attached to the adhesive on the substrate. The adhesive may be heated during...

20050287709 - Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe: A process for manufacturing a plurality of leadless semiconductor packages includes an electrically testing step to test encapsulated chips in a matrix of a leadless leadframe. Firstly, a leadless leadframe having at least a packaging matrix is provided. The packaging matrix defines a plurality of units and a plurality of...

20050287712 - Leadframe alteration to direct compound flow into package: A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The downset has an upward slope extending from the edge of the frame and levels off with the rest of the frame at...

20050287711 - Leadframe of a leadless flip-chip package and method for manufacturing the same: A leadframe of a leadless flip-chip package includes a plurality of inner leads, a non-conductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower...

20050287710 - Leadless semiconductor package and method for manufacturing the same: A leadless semiconductor package mainly includes a plurality of inner leads, a chip pad, a semiconductor chip and a molding compound. A non-conductive ink is filled between every two of the inner leads, and couples the inner leads to the chip pad so as to be in replacement of the...

20050287713 - Method for fabricating semiconductor packages: A method for fabricating semiconductor packages is proposed. A plurality of substrates are prepared each having a chip thereon. Length and width of each substrate are equal to predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. A protruded portion is formed...

20050287716 - Electronic device package: A packaged assembly including an interposer or substrate supporting on a first side thereof a chip that is encased with an encapsulant is described. A second side of the interposer or substrate includes a barrier that blocks the flow of encapsulant to create a uniform encapsulant edge on the second...

20050287714 - Enhancing epoxy strength using kaolin filler: An embodiment of the present invention is a technique to provide a substrate with enhanced strength. A kaolin filler is added to an epoxy resin. The kaolin filler is mixed with the epoxy resin to form a mixture. A substrate is formed from the mixture. The substrate is processed in...

20050287715 - Method for encapsulating lead frame packages: A method of encapsulating a plurality of IC chips attached to a lead frame strip that includes an outer frame and a plurality of vertical and horizontal connecting bars attached to the outer frame in a manner that defines a plurality of inner frames arranged in a matrix pattern within...

20050287717 - Methods and devices for forming nanostructure monolayers and devices including such monolayers: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices)....

20050287718 - Integrated soi fingered decoupling capacitor: The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ...

20050287721 - Method for manufacturing wiring substrate, thin film transistor, display device and television device: An object of the present invention is to provide a method for manufacturing a display device by improving the utilization efficiency of materials and simplifying manufacturing process. Another object of the invention is to provide a technique for forming a pattern such as a wiring having a predetermined shape included...

20050287722 - Method of fabricating semiconductor device: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to...

20050287720 - Method of fabricating thin film transistor by reverse process: A method of fabricating a thin film transistor is provided. The thin film transistor fabrication method includes the steps of: forming an amorphous silicon film on an insulation substrate; continuously forming a gate oxide film and a gate electrode metal film on the silicon film of the substrate; sequentially patterning...

20050287719 - Organic thin film transistor array panel and manufacturing method thereof: A method of manufacturing a thin film transistor array panel includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a data line and a drain electrode on the gate insulating layer; depositing an organic semiconductor layer on the data line, the...

20050287723 - Semiconductor-on-insulator constructions; and methods of forming semiconductor-on-insulator constructions: The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine,...

20050287724 - Transparent conductive films and processes for forming them: A target containing an indium oxide and a tin oxide is used and sputtered particles from the target are transported by a forced gas flow of a sputter gas onto an organic substrate and deposited on the organic substrate while applying a DC bias voltage or an RF bias voltage...

20050287725 - Plasma processing method, plasma processing apparatus, and computer recording medium: According to the present invention, plasma oxidation processing and plasma nitridation processing are applied at the same time to the surface of a semiconductor substrate by plasma using a microwave. After forming an insulating film by the plasma oxynitridation processing as described above, the plasma nitridation processing is further applied...

20050287726 - Method of crystallizing amorphous semiconductor thin film and method of fabricating poly-crystalline thin film transistor using the same: A method of crystallizing an amorphous semiconductor thin film formed on a substrate is provided. The method includes the steps of: forming a gate insulation film and a gate electrode on an amorphous semiconductor thin film; locally forming first and second crystallization induced metal patterns for inducing crystallization of the...

20050287728 - Method for forming a bottom gate thin film transistor using a blend solution to form a semiconducting layer and an insulating layer: An improved method of forming a semiconducting polymer layer protected by an insulating polymer layer is described. In the method, a material for forming a semiconducting polymer and an insulating polymer are dissolved in a solvent. The blended solution is deposited on a substrate where the semiconducting polymer and insulating...

20050287729 - Method of forming a nanocluster charge storage device: In one embodiment, a method of forming a nanocluster charge storage device is provided. A first region of a semiconductor device is identified for locating one or more non-charge storage devices. A second region of the semiconductor device is identified for locating one or more charge storage devices. A gate...

20050287727 - [mos transistor and fabrication thereof]: A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and...

20050287730 - Schottky barrier cmos device and method: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant...

20050287731 - Isolation trenches for memory devices: A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than...

20050287732 - Method of manufacture of semiconductor device: A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film, by patterning the polycrystalline silicon film, in an active cell area, a...

20050287733 - Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of...

20050287734 - Method for fabricating trench power device: Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method...

20050287736 - Latch-up prevention for memory cells: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always...

20050287735 - Semiconductor storage device and method of manufacturing the same: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming,...

20050287737 - Method for forming storage node electrode of capacitor: Disclosed is a method for forming a storage node electrode of a capacitor, capable of preventing wet chemicals from penetrating into an oxide layer. The method includes the steps of preparing a semiconductor substrate, forming a first oxide layer on the semiconductor substrate, forming conductive plugs for filling the first...

20050287738 - Method of manufacturing a semiconductor memory device: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a...

20050287739 - Isolation structure for a memory cell using al2o3 dielectric: The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure, for example a DRAM memory cell. An aluminum oxide (Al2O3) is used as a gate dielectric, rather than a conventional...

20050287742 - Method of manufacturing a nonvolatile semiconductor memory device: In a method of manufacturing a nonvolatile semiconductor memory device, a preliminary floating gate is formed on a substrate having an active region and an inactive region that extend in a first direction. A dielectric layer and a control gate layer are formed on the substrate. A control gate, a...

20050287741 - Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer: A first dielectric (120) and a first floating gate layer (130.1) are formed on a semiconductor substrate (110). The first dielectric, the first floating gate layer, and the substrate are etched to form isolation trenches (150). The first dielectric (120) is etched to pull the first dielectric away from the...

20050287740 - System and method of forming a split-gate flash memory cell: A system and method for forming a split-gate flash memory cell is disclosed. In one example, a method for forming a semiconductor device includes: supplying a substrate; forming a floating gate with alternate etch and passivation steps; and forming a control gate proximate to and partially overlying the floating gate....

20050287743 - Method of manufacturing semiconductor device having recess channel structure: Disclosed herein is a method of manufacturing a semiconductor device having a recess channel structure, which prevents misalignment of a source/drain, thereby being capable of achieving an improvement in the drive-ability of a gate and preventing a degradation in characteristics of the semiconductor device due to a hot carrier effect....

20050287744 - Semiconductor device: A semiconductor device has a plurality of pillars formed by filling a poly-silicon via an insulating layer in a plurality of trenches arranged substantially in parallel at certain intervals, n+-semiconductor regions and p+-semiconductor regions which are formed between partial pillars among the plurality of pillars and alternately formed along a...

20050287745 - Semiconductor device having multiple gate oxide layers and method of manufacturing thereof: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A...

20050287746 - Facilitating removal of sacrificial layers to form replacement metal gates: In a metal gate replacement process, a gate electrode stack may be formed of a germanium containing layer. In subsequent processing of the source/drains, high temperature steps may be utilized, forming a germinide on said stacks. That germinide may be removed, prior to removing the rest of the stack, using...

20050287747 - Doped nitride film, doped oxide film and other doped films: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the...

20050287749 - Methods for forming openings in doped silicon dioxide: Methods of forming openings in doped silicon dioxide layers and of forming self aligned contact holes are provided. The openings are generally etched in a plasma processing chamber. An etchant gas mixture comprising at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas...

20050287748 - Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics: In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrificial metal layer prevents reactions between the polysilicon gate...

20050287750 - Transistor, method of fabricating the same, and light emitting display comprising the same: A light emitting display comprises: at least one first metal layer; a second metal layer crossing the first metal layer and having a first width; a light emitting device formed adjacent to a region where the first metal layer and the second metal layer cross each other; and a pixel...

20050287752 - Methods for forming a transistor: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate...

20050287751 - Multi-layer reducible sidewall process: The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside...

20050287753 - Mos device for high voltage operation and method of manufacture: A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is overlying the surface region. A gate polysilicon...

20050287754 - Radiation hardened bipolar junction transistor: A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric...

20050287755 - Capacitor assemblies: A method for fabricating a capacitor arrangement which includes at least three electrodes is described. The capacitor arrangement is fabricated using a number of lithography methods that is smaller than the number of electrodes. A capacitor arrangement extending over more than two or more interlayers between metallization layers has a...

20050287756 - Semiconductor device with resistor element and its manufacture method: A first well is formed in the surface layer of a semiconductor substrate, the first layer being of a first conductivity type, the first well being of a second conductivity type opposite to the first conductivity type. A pair of current input/output ports are connected to the first well, the...

20050287757 - Method and structure for integrated stacked capacitor formation: An integrated circuit device structure (and methods). The structure includes a semiconductor substrate comprising a surface. A first doped polysilicon liner is defined within a first trench region formed on a first plug coupled to the surface of the substrate and a second doped polysilicon liner is defined within a...

20050287758 - Method of fabricating capacitor in semiconductor device and semiconductor device using the same: A method of fabricating a capacitor in a semiconductor device is provided. The method includes steps of depositing a metal layer for forming a lower electrode on a semiconductor substrate; forming, using an oxidation rate differential, an uneven structure in correspondence with a grain boundary of the metal layer; forming...

20050287759 - Method and apparatus for a semiconductor device with a high-k gate dielectric: A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric...

20050287760 - Method for fabricating high aspect ratio mems device with integrated circuit on the same substrate using post-cmos process: The invention discloses a novel flexible, modular fabrication method for integrated high aspect ratio single crystal silicon microstructures designed and manufactured in a post conventional CMOS process (Post-CMOS). The method involves the standard circuits formation, the electrical isolation trenched etching and refilling, backside etching, interconnection formation, and structure releasing. Further,...

20050287762 - Formation of removable shroud by anisotropic plasma etch: Isotropic etching of sacrificial oxide that is adjacent to a trench fill step in an STI wafer can lead to undesired etching away of a sidewall of the trench fill material (e.g., HDP oxide). A sidewall protecting method conformably coats the trench fill step and sacrificial oxide with an etch-resistant...

20050287761 - Method for fabricating a capacitor in a semiconductor device: A method for fabricating a capacitor in a semiconductor device that includes providing a semiconductor substrate, forming at least one shallow trench isolation structure in the semiconductor substrate, forming a tunnel oxide layer over the semiconductor substrate, depositing a first polysilicon layer over the tunnel oxide layer, depositing a nitride...

20050287764 - Method of fabricating shallow trench isolation by ultra-thin simox processing: The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen...

20050287763 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation pattern to partially fill up the opening. A sacrificial...

20050287765 - Method for manufacturing semiconductor device: In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing...

20050287767 - Semiconductor substrate and process for producing it: d) splitting the donor wafer along the layer of cavities, resulting in a layer of semiconductor material on the carrier wafer. Semiconductor substrates prepared thusly may have a single-crystalline semiconductor layer having a thickness of 100 nm or less, a layer thickness uniformity of 5% or less, and an HF...

20050287766 - Wafer-level diamond spreader: An embodiment of the present invention is a technique to heat spread at wafer level. A silicon wafer is thinned. A chemical vapor deposition diamond (CVDD) wafer processed. The CVDD wafer is bonded to the thinned silicon wafer to form a bonded wafer. Metallization is plated on back side of...

20050287768 - Method and apparatus for cleaving brittle materials: An apparatus for cleaving a section of a bar of brittle material is provided. The apparatus comprises a support adapted to hold the section of the bar in a position to be cleaved, a blade, an actuator coupled to the blade for driving the blade at least partially through the...

20050287769 - Substrate production apparatus for producing a substrate for a display device: A substrate production apparatus for producing a substrate for a display device is disclosed. The substrate production apparatus includes a first production apparatus including a first scriber to scribe a first mother substrate into at least one first model substrate and at least one second model substrate, a first grinder...

20050287770 - Alternative methods for fabrication of substrates and heterostructures made of silicon compounds and alloys: The present invention relates to alternative methods for the production of crystalline silicon compounds and/or alloys such as silicon carbide layers and substrates. In one embodiment, a method of the present invention comprises heating a porous silicon deposition surface of a porous silicon substrate to a temperature operable for expitaxial...

20050287771 - Liquid precursors for the cvd deposition of amorphous carbon films: Methods are provided for depositing amorphous carbon materials. In one aspect, the invention provides a method for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas into the processing chamber, wherein the processing gas comprises a carrier gas, hydrogen, and one or more precursor...

20050287772 - Process for producing a web of a semiconductor material: Process for producing a web of a semiconductor material The invention relates to a process for producing two webs of a semiconductor material, in which a sacrificial web of a first material is produced on a semiconductor substrate, in which the first material is selected in such a way that...

20050287773 - Laser beam projection mask, and laser beam machining method and laser beam machine using same: The laser beam projection mask 14 has three rectangular-shaped slits 25, 26, 27 as transmission areas. These three slits 25, 26, 27 are formed in sequence in X direction shown by an arrow X in FIG. 2C at specified intervals, and the width in the X direction decreases in the...

20050287774 - Method of improving surface flatness of group-iii nitride crystal, substrate for epitaxial growth, and semiconductor device: A heating process is performed in a nitrogen atmosphere at a temperature of not less than 1650° C. upon an epitaxial substrate including a single crystal base and an upper layer made of a group-III nitride crystal and epitaxially formed on a main surface of the single crystal base. The...

20050287775 - Film formation apparatus and method for semiconductor process: A film formation method for a semiconductor process is arranged to form a thin film on a target substrate by CVD, while supplying a first process gas for film formation and a second process gas for reacting with the first process gas to a process field accommodating the target substrate....

20050287776 - Method of plasma doping: A method of plasma doping in which dilution of B2H6 is maximized for enhanced safety and stable plasma generation and sustention can be carried out without lowering of doping efficiency and in which the amount of dopant injected can be easily controlled. In particular, a method of plasma doping characterized...

20050287777 - Semiconductor device and method of fabrication thereof: A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step...

20050287778 - Method for forming an ultra-shallow junction in a semiconductor substrate using a nuclear stopping layer: A method for forming an ultra-shallow junction in a semiconductor substrate is provided. A semiconductor substrate having a top surface is prepared. A dielectric layer is then formed on the top surface. A first ion implantation process is carried out to implant a plurality of heavy ions into the dielectric...

20050287779 - Integrated circuit structure and method of fabrication: According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy...

20050287780 - Semiconductor constructions: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some...

20050287781 - Method for interconnecting electronic components using a blend solution to from a conducting layer and an insulating layer: An improved method of interconnecting electronic devices is described. In the method a blended material for forming a conducting layer and an insulating layer are deposited between a contact of a first electronic device and a second electronic device. The blended material leads to formation of a conductor overlayed by...

20050287782 - Methods for manufacturing a soft error and defect resistant pre-metal dielectric layer: A method for forming a pre-metallization layer on an underlying micro-structure, and a corresponding micro-structure formed by the method. The micro-structure may be a semiconductor circuit and/or a Micro-Electro-Mechanical Systems (MEMS) device. A first layer of undoped silicate glass is deposited on a micro-structure. Then, a layer of phospho silicate...

20050287783 - Microelectronic devices and methods for forming interconnects in microelectronic devices: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled...

20050287784 - Interconnect junction providing reduced current crowding and method of manufacturing same: Disclosed herein are a junction where electrical interconnects on a semiconductor substrate intersect and a method of manufacturing a junction where electrical interconnects on a semiconductor substrate intersect is disclosed. In one embodiment, the junction includes a portion of at least one current providing electrical interconnect having a length parallel...

20050287785 - Method of stacking wafers with anisotropic conductive adhesive: The present invention includes a method that provides a first wafer; forms a first raised contact from a first plug on the first wafer; provides a second wafer; forms a second raised contact from a second plug on the second wafer; applies an anisotropic conductive adhesive over the first wafer;...

20050287786 - Device and method using isotopically enriched silicon: The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second layer of an isotopically enriched semiconductor material silicon over the first doped...

20050287788 - Manufacturing method of nanowire array: This specification discloses a manufacturing method of nanowire array. The method includes the steps of: providing a substrate; forming an insulating layer on the substrate; forming a metal catalyst layer on the insulating layer by spin on glass (SOG), the metal catalyst being Au, Ag, or Pt; forming a covering...

20050287787 - Porous ceramic materials as low-k films in semiconductor devices: A method for selecting and forming a low-k, relatively high E porous ceramic film in a semiconductor device is described. A ceramic material is selected having a relatively high Young's modulus and relatively lower dielectric constant. The k is reduced by making the film porous....

20050287790 - Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of...

20050287789 - Substrate with patterned conductive layer: A method of processing a substrate is provided. The method includes providing a substrate having a first surface, a second surface, and conductive paths extending from the first surface to the second surface. The method also includes (1) covering a portion of the first surface with a conductive material, and...

20050287791 - Method of forming laminate and method of manufacturing photovoltaic device: A method of forming a laminate and a method of manufacturing a photovoltaic device using the laminate are provided. The laminate forming method includes a first step of forming an intermediate layer on a base member, and a second step of forming a metal layer on the intermediate layer, the...

20050287792 - Method for forming barrier layer of semiconductor device: A method for forming a barrier layer of a semiconductor device is disclosed, to improve the advantageous characteristics of device by obtaining the uniformity on depositing a barrier layer eve in case an etching profile is not in shape of the vertical, which includes the steps of loading a wafer...

20050287793 - Diffusion barrier process for routing polysilicon contacts to a metallization layer: Methods and apparatus are described to facilitate forming of polysilicon contact plugs with an improved diffusion barrier that can be formed in conjunction with other process steps. Embodiments of the present invention are formed by recessing the polysilicon plug below the surface of the insulation layer, allowing the depression formed...

20050287794 - Contact structure: This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more...

20050287795 - Method of forming high aspect ratio structures: An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to its external...

20050287797 - Method of making a semiconductor device manufacturing mask substrate: A method of making a semiconductor device manufacturing mask, which makes it possible to suppress a semiconductor-device global step and simply manufacture a highly reliable semiconductor device. Square dummy patterns each having one side of, for example, 0.25 μm or less are inserted into an area other than an actual...

20050287796 - Methods of fabricating metal lines in semiconductor devices: Methods to form metal lines in semiconductor devices are disclosed. An illustrated method comprises: depositing first and second interlayer dielectric layers on a semiconductor substrate; forming a via hole in the second interlayer dielectric; forming a photoresist pattern, forming a trench, using the photoresist pattern as a mask; removing an...

20050287798 - Preventing cavitation in high aspect ratio dielectric regions of semiconductor device: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing...

20050287799 - Method for fabricating semiconductor device: The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conductive region including a conductive pattern and silicon, and preventing an increase...

20050287800 - Multilayer interconnection structure and method for forming the same: A multilayer interconnection structure of the present invention includes first interconnection, second interconnection belonging to an interconnection layer different from an interconnection layer to which the first layer belongs, and third interconnection for connecting the first and second interconnections, the third interconnection belonging to a different interconnection layer and including...

20050287801 - Method for fabricating semiconductor device having landing plug contact structure: The present invention relates to a method for fabricating a semiconductor device with a landing plug contact structure. The method includes the steps of: forming a plurality of gate structures on a substrate; sequentially forming a first spacer and a second spacer on sidewalls of each gate structure; forming a...

20050287802 - Method for forming metal line in semiconductor memory device having word line strapping structure: The present invention relates to a method for forming a metal line in a semiconductor memory device having a word strapping structure. Especially, the metal line is formed by using a dual hard mask including a tungsten layer and a nitride layer as an etch mask. Also, the metal line...

20050287803 - Semiconductor device having a metal wiring structure and method of manufacturing the same: After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal wiring structure is...

20050287804 - Systems and methods of forming refractory metal nitride layers using organic amines: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on a substrate by using an atomic layer deposition process (a vapor deposition process that includes a plurality of deposition cycles) with a refractory metal precursor compound,...

20050287805 - Electronic device: One embodiment of a method of making an electronic device includes forming on a substrate surface a first layer having a peak-valley-peak profile, and forming a second layer on the first layer by use of a target positioned along a line-of-sight that excludes a floor of the valley such that...

20050287806 - Vertical cvd apparatus and cvd method using the same: A vertical CVD apparatus includes a supply system configured to supply process gases into a process chamber, and a control section configured to control an operation of the apparatus. The supply system includes a plurality of first delivery holes connected to a first reactive gas line to supply a first...

20050287807 - Formation of composite tungsten films: Methods for the deposition of tungsten films are provided. The methods include depositing a nucleation layer by alternatively adsorbing a tungsten precursor and a reducing gas on a substrate, and depositing a bulk layer of tungsten over the nucleation layer....

20050287808 - Lactate-containing corrosion inhibitor: The corrosion of aluminum-based metal films may be minimized by applying a lactate-containing solution to the aluminum-based metal films before the aluminum-based metal films are etched. The lactate-containing solution is applied to the aluminum-based metal film before the film is etched with a corrosive etchant. Minimizing the corrosion of the...

20050287809 - Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region: A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming...

20050287810 - Method for making a semiconductor device with reduced spacing: Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is patterned to leave fences over the isolation regions. A thinning process,...

20050287811 - Semiconductor device fabrication method: A method of performing microfabrication using a hard mask in the manufacture of a semiconductor device having an interlayer dielectric (ILD) film made of low-dielectric constant, K, insulating material is provided. When treating a low-K dielectric film for use in semiconductor integrated circuitry and its underlying etching stopper film, a...

20050287814 - H2o plasma for simultaneous resist removal and charge releasing: An in-situ method of stripping a layer of resist from a substrate or wafer utilizes pure H2O plasma recipe to substantially prevent charges from accumulating on the substrate or wafer during stripping of the layer of resist....

20050287813 - Manufacturing method of semiconductor device and semiconductor manufacturing apparatus: An apparatus for decreasing plasma-induced damage caused by exposure to plasma is provided in an apparatus for manufacturing semiconductor devices using plasma. An apparatus is used for irradiating the semiconductor surface with as least one of X-rays and UV-rays in a vacuum or in an inert atmosphere after plasma processing....

20050287815 - Method and apparatus for reducing aspect ratio dependent etching in time division multiplexed etch processes: The present invention provides a method and an apparatus for reducing aspect ratio dependent etching that is observed when plasma etching deep trenches in a semiconductor substrate through an alternating deposition/etch process. A plurality of different sized features on the substrate are monitored in real time during the alternating deposition/etch...

20050287812 - Method for repairing plasma damage after spacer formation for integrated circuit devices: A method for processing integrated circuit memory devices. The method includes supporting a partially completed substrate, the substrate comprising a plurality of MOS gate structures. Each of the gate structures has substantially vertical regions that define sides of the gate structures. The method forms a conformal dielectric layer overlying the...

20050287817 - Low dielectric constant zinc oxide: Low dielectric constant group II-VI compounds, such as zinc oxide, and fabrication methods are disclosed. Low dielectric constant insulator materials are fabricated by doping zinc oxide with at least one mole % p-type dopant ion. Low dielectric constant zinc oxide insulator materials are fabricated by doping zinc oxide with silicon...

20050287816 - Methods of forming patterned photoresist layers over semiconductor substrates: This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is formed over a semiconductor substrate. A photoresist footer-reducing fluid is provided within pores of the porous antireflective coating. A positive photoresist is formed over the porous antireflective coating having the...

20050287818 - Material and method for forming low-dielectric-constant film: The material contemplated by this invention for the formation of a low-dielectric-constant film contains in all the stereoisomer molecules of 1,3,5,7-tetramethyl cyclotetrasiloxane (TMCTS) not less than 15% and not more than 100% of a stereoisomer having all the four hydrogen atoms forming an Si—H bond fall on the same size...

20050287819 - Systems and methods for forming metal oxides using metal organo-amines and metal organo-oxides: A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposit ion process and one or more precursor compounds that include organo-amine ligands and one or more precursor compounds that include organo-oxide ligands....

20050287820 - Mold for nano imprinting: A metal mold for use in a nano-imprinting process comprises a firmly adhering monomolecular non-sticking layer. The later was obtained by subjecting the mold to a reaction with a fluoroalkyl compound having a mercapto group. As a result of said reaction, the layer comprises an organic sulfide of said metal....

20050287821 - Wafer processing system, coating/developing apparatus, and wafer, processing apparatus: In a coating and developing apparatus that forms a resist film on substrates such as semiconductor wafers, and develops substrates exposed by an aligner, times after the aligner unloads substrates until heating units (PEB) start heating the substrates are kept uniform. Exposed wafers are prevented from being left stagnant in...

20050287822 - Method of forming polysilicon layer in semiconductor device: Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to control abnormal deposition depending upon excessive inflow of the gas. Accordingly, the interfacial properties of...

20050287823 - Dual-frequency silicon nitride for spacer application: A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temperature dual-frequency plasma enhanced CVD...

20050287824 - Ecr-plasma source and methods for treatment of semiconductor structures: The invention relates to microelectronics, more particularly, to methods of manufacturing solid-state devices and integrated circuits utilizing microwave plasma enhancement under conditions of electron cyclotron resonance (ECR), as well as to use of plasma treatment technology in manufacturing of different semiconductor structures. Also proposed are semiconductor device and integrated circuit...

20050287825 - Laser anneal method of a semiconductor layer: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower...

20050287826 - Method of sealing low-k dielectrics and devices made thereby: Methods for sealing porous low-k dielectrics, and devices made thereby, are described, comprising treating the porous low-k dielectrics by atomic layer deposition so as to seal the pores. ALD reactants are chosen in part based on their size, such that they do not deeply penetrate the interconnected pore structures of...

20050282296 - Asymmetrical programming ferroelectric memory transistor: A method of fabricating and programming a ferroelectric memory transistor for asymmetrical programming includes fabricating a ferroelectric memory transistor having a metal oxide layer overlaying a gate region; and programming the ferroelectric memory transistor so that a low threshold voltage is about equal to the intrinsic threshold voltage of the...

20050282295 - Mtj stack with crystallization inhibiting layer: A method of forming a magnetic stack and a structure for a magnetic stack of a resistive memory device. A crystallization inhibiting layer is formed over the free layer of a magnetic stack, improving thermal stability. The crystallization inhibiting layer comprises an amorphous material having a higher crystallization temperature than...

20050282297 - Method and structure for defect monitoring of semiconductor devices using power bus wiring grids: A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first...

20050282300 - Back-end-of-line metallization inspection and metrology microscopy system and method using x-ray fluorescence: Systems and methods for performing inspection and metrology operations on metallization processes such as on back-end-of-line (BEOL) metallization thickness and step coverage are disclosed. Specific examples include measurements of thickness and uniformity of barrier layers, including tantalum for example, and seed layers, including copper for example, in Damascene, including dual-Damascene,...

20050282298 - Transport speed monitoring apparatus and semiconductor processing system utilizing the same: A semiconductor processing system utilizing transport speed monitoring of a wafer boat. The semiconductor processing comprises a process chamber, loading device, and transport speed monitoring device. The loading device transports a boat of wafers into and out of the process chamber where the wafers experience particular treatment. The transport speed...

20050282299 - Wafer inspection system and method thereof: A wafer inspection system includes an electrical testing part to control a probe to be in contact with a pad of a wafer to perform a predetermined electrical test, a defect detecting part to detect a defect in the wafer passing through the electrical test, a defect sorting part to...

20050282301 - Structure and method for field emitter tips: Improved methods and structures are provided for an array of vertical geometries which may be used as emitter tips, as a self aligned gate structure surrounding field emitter tips, or as part of a flat panel display. The present invention offers controlled size in emitter tip formation under a more...

20050282302 - Method of manufacturing a light emitting device: To reduce the number of layers of an EL layer so that it can be manufactured at a reduced cost. An electrode (a) (102) and an EL layer (103) are formed on an insulator (101), and the EL layer (103) is subjected to plasma processing. A carrier injection region (104)...

20050282303 - Liquid crystal display and method of manufacturing the same: The present invention relates to a method for keeping contact resistance of a pad low. The present invention also discloses a structure of the pad and a method for manufacturing the same, for use in circuit boards and LCD displays. The pad terminal comprises a first metal layer and a...

20050282304 - Light-emission device, method of manufacturing same, electro-optical device and electronic device: An organic EL display unit is manufactured in an efficient manner. A light emission device (1000) is manufactured by bonding together a driving circuit substrate (100) formed with driving circuit constituted by thin film transistors 11, and a light emission substrate (300) comprising a successively laminated transparent electrode layer 31,...

20050282305 - Semiconductor element and display device using the same: Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin...

20050282306 - Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device: A method of production of an ultra-thin semiconductor chip and an ultra-thin back-illuminated solid-state image pickup device utilizing a semiconductor layer formed on a support substrate via an insulating layer to improve separation performance of a semiconductor layer from a support substrate and thereby improve the productivity and quality-including the...

20050282307 - Particulate for organic and inorganic light active devices and methods for fabricating the same: A light active electronic device as a component or system for generating light in response to electrical energy (energy-to-light), generating light in response to radiation energy (light-to-light), and generating energy in response to radiation energy (light-to-energy). Methods of making a multi-layered light active particle and making polymer blend light active...

20050282308 - Organic electroluminescent display device and method of producing the same: l

20050282309 - Circuit board with embedded passive component and fabrication process thereof: A process for fabricating a circuit board with embedded passive component is provided. A conductive layer including a first surface and a second surface opposing to the first surface is provided. The conductive layer has first through holes passing through the conductive layer, respectively. At least one passive component material...

20050282310 - Encapsulation of multiple integrated circuits: In one embodiment, a device includes but is not limited to: a first integrated circuit affixed to a substrate; an electronic circuit component affixed to the substrate; a first encapsulation structure encasing the first integrated circuit; a second integrated circuit affixed to the first encapsulation structure; and a second encapsulation...

20050282311 - Flip-chip substrate and flip-chip bonding process thereof: A flip-chip substrate for bonding with a chip is provided. The chip has an active surface with a plurality of bonding pads and each bonding pad has a bump thereon. The flip-chip substrate has a plurality of contact pads that correspond in positions with the bonding pads on the chip...

20050282313 - Methods for modifying semiconductor devices to stabilize the same and semiconductor device assembly: One or more stabilizers are disposed on the surface of a semiconductor device component prior to bonding the same to a higher-level substrate. The one or more stabilizers may be formed on or secured to the surface. Upon assembly of the semiconductor device component face down upon a higher-level substrate...

20050282312 - Semiconductor device and manufacturing method thereof: A semiconductor device is provided which includes a first semiconductor chip, a substrate onto which the first semiconductor chip is flip-chip bonded and on which a concave is formed along one side of the first semiconductor chip which is flip-chip bonded, a second semiconductor chip which is flip-chip bonded onto...

20050282314 - Printed circuit boards and methods for fabricating the same: Printed circuit boards and methods for fabricating the same. A via in a printed circuit board electrically connects to trace lines of the PCB, such that only one plating line is required to electrically connect a plating bus and the plating through hole. Thus, in an electroplating step, current can...

20050282315 - High-reliability solder joint for printed circuit board and semiconductor package module using the same: A printed circuit board and a semiconductor package module using the same in which solder joint reliability (SJR) is improved. The printed circuit board includes: a first terminal exposed to the external of the printed circuit board in a print circuit pattern to be connected to a solder ball of...

20050282316 - Method of manufacturing an electronic device comprising a thin film transistor: A method of manufacturing an electronic device comprising a thin film transistor (42), comprises forming a hydrogen-containing layer (22) over a semiconductor layer (10; 20), irradiating the hydrogen-containing layer so as to hydrogenate the semiconductor layer, and then forming electrodes (24; 26, 28) over the semiconductor layer. A short diffusion...

20050282317 - Thin film semiconductor apparatus and method for driving the same: A thin film semiconductor apparatus comprising thin film transistors integrated on a substrate, and a wiring connecting the thin film transistors to one another, wherein each of the thin film transistors comprises a channel which has a predetermined threshold-voltage and on-off operates depending on a gate voltage applied through a...

20050282318 - Method of forming a transistor with a bottom gate: A transistor having a bottom gate formed from a layer of gate material and a channel region formed from a layer semiconductor material. In some examples, the layer of gate material is patterned separately from the layer of semiconductor material. In some examples the patterning of the layer of gate...

20050282319 - Semiconductor structure processing using multiple laser beam spots overlapping lengthwise on a structure: Methods and systems use laser pulses to process a selected structure on or within a semiconductor substrate. The structure has a surface, a width, and a length. The laser pulses propagate along axes that move along a scan beam path relative to the substrate as the laser pulses process the...

20050282320 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate, forming a resist on the semiconductor substrate so that the resist contacts only one side face of the gate electrode, and tilting the gate electrode by shrinking or expanding the resist....

20050282321 - High-voltage mos device and fabrication thereof: A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying doped...

20050282323 - Hybrid substrate and method for fabricating the same: A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on...

20050282322 - Retaining ring with conductive portion: A retaining ring for use with electrochemical mechanical processing is described. The retaining ring has a generally annular body formed with a conductive portion and a non-conductive portion. The non-conductive portion contacts the substrate during polishing. The conductive portion is electrically biased during polishing to reduce the edge effect that...

20050282324 - Semiconductor device containing distorted silicon layer formed on silicon germanium layer: A semiconductor device includes a silicon germanium layer, a silicon layer and a silicide layer. The silicon germanium layer is formed on a semicon-ductor substrate. The silicon layer is formed on the silicon germanium layer. The silicide layer is formed in a surface region of the silicon layer. A germanium...

20050282326 - Method for fabricating dual-metal gate device: A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the...

20050282325 - Structure and method to improve channel mobility by gate electrode stress modification: In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case...

20050282327 - Flash memory device having a graded composition, high dielectric constant gate insulator: A graded composition, high dielectric constant gate insulator is deposited between a substrate and floating gate in a flash memory cell transistor. If the composition of the gate insulator is closer to the high-k material near the substrate, the electron barrier for hot electron injection will be lower. If the...

20050282328 - Removal of carbon from an insulative layer using ozone: A method of removing residual carbon deposits from an insulative material. The insulative material comprises silicon, carbon, and hydrogen and is a flowable oxide material or a spin-on, flowable oxide material. The residual carbon deposits are removed from the insulative material by exposing the material to ozone. The insulative material...

20050282329 - Cmos transistors with dual high-k gate dielectric and methods of manufacture thereof: CMOS devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over...

20050282330 - Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers: A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer...

20050282331 - Substrate and method of forming substrate for fluid ejection device: A method of forming an opening through a substrate having a first side and a second side opposite the first side includes forming spaced etch stops in the first side of the substrate, etching into the substrate from the second side toward the first side to the spaced etch stops,...

20050282332 - Non-volatile memory cell and method of operating the same: A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region of the three P-type doped regions, a first gate formed on the dielectric layer, a...

20050282333 - Memory cell transistor having different source/drain junction profiles connected to dc node and bc node and manufacturing method thereof: A memory cell transistor of a DRAM device is provided. A gate stack pattern is formed on a semiconductor substrate. A DC node and a BC node are formed substantially under lateral sides of the gate stack pattern in the semiconductor substrate. The DC node and the BC node are...

20050282334 - Nrom flash memory devices on ultrathin silicon: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on...

20050282335 - Method for manufacturing a semiconductor device having polysilicon plugs: A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors;...

20050282337 - High write and erase efficiency embedded flash cell: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating...

20050282338 - Methods of forming gate patterns using isotropic etching of gate insulating layers: A method for forming a gate pattern of a semiconductor device can include isotropically etching a gate insulating layer located between a gate conductive layer pattern and a substrate to recess an exposed side wall of the gate insulating layer pattern beyond a lower corner of the gate conductive layer...

20050282336 - [method of fabricating read only memory and memory cell array]: A method of fabricating a read only memory cell array is described. A patterned film is formed over the substrate to define the predetermined positions of bit lines on the substrate and exposing a plurality of predetermined portions of the substrate. A plurality of field oxide layers is formed on...

20050282339 - Method of forming a field effect transistor: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material...

20050282340 - Semiconductor apparatus with improved esd withstanding voltage: A semiconductor apparatus having an outer ESD protective circuit corresponding to each external connection terminal, the outer ESD protective circuit being formed in a peripheral region around the external connection terminals. The outer ESD protective circuit discharges electrostatic voltage from the external connection terminal and avoids the damaging of an...

20050282341 - High-temperature stable gate structure with metallic electrode: The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has...

20050282342 - Field effect transistor and fabrication method thereof: A field effect transistor of the present invention includes, on a semiconductor substrate, (i) a fin section formed in a fin shape protruding from the substrate, (ii) a gate dielectric for covering a channel region section of the fin section, (iii) a gate electrode that is insulated from the channel...

20050282343 - Method of forming transistor having channel region at sidewall of channel portion hole: According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of...

20050282344 - Mosfet and method of fabricating the same: A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating...

20050282345 - Transistor with vertical dielectric structure: A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure...

20050282346 - Mim capacitors: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned...

20050282347 - Semiconductor device with inductive component and method of making: An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top...

20050282348 - Method of manufacturing thin film capacitor: A first electrode layer having protrusions and depressions on its surface are formed on a lower insulating layer on a semiconductor substrate, and a sacrificial layer is formed on the first electrode layer with a material that is reflowable when heated. After reflowing the sacrificial layer by heat treatment, the...

20050282349 - Method for forming device isolation film of semiconductor device: A method for forming device isolation film of semiconductor device is provided, the method including forming a pad oxide film, a pad nitride film, and an oxide film for device isolation on a semiconductor substrate, etching a predetermined region of the oxide film for device isolation, the pad nitride film,...

20050282350 - Atomic layer deposition for filling a gap between devices: A method is provided for filling a trench or gap between a pair of semiconductor devices formed above a substrate. A liner is applied in a trench or gap between a pair of devices by atomic layer deposition to partially fill the trench or gap. The trench or gap is...

20050282352 - Method of forming dual gate dielectric layer: A method of forming a dual gate dielectric layer increases a performance of a semiconductor device by using a dielectric layer having a high dielectric constant, including forming a first dielectric layer having a predetermined thickness on a semiconductor substrate; removing the first dielectric layer formed on a second region,...

20050282351 - Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication: The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench...

20050282353 - Trench isolation structure and a method of manufacture therefor: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls...

20050282354 - Semiconductor device manufacturing method: A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend...

20050282355 - High density bonding of electrical devices: A method of thermocompressive bonding of one or more electrical devices using individual heating elements and a resilient member to force the individual heating elements into compressive engagement with the electrical devices is provided. The individual heating elements may be Curie-point heating elements or conventional resistive heating elements. A method...

20050282357 - Method of peeling off and method of manufacturing semiconductor device: The invention aims to provide a peeling method without damaging a peeled off layer and to allow separation of not only a peeled off layer having a small surface area but also the entire surface of a peeled off layer having a large surface area. Further, the invention aims to...

20050282356 - Semiconductor layer structure and method of making the same: A method of forming a circuit includes providing a first substrate; positioning an interconnect region on a surface of the first substrate; providing a second substrate; positioning a device structure on a surface of the second substrate, the device structure including a stack of at least three doped semiconductor material...

20050282358 - Method for transferring an electrically active thin layer: A method for transferring an electrically active thin film from an initial substrate to a target substrate including: ion implantation through one face of the initial substrate to create a buried, embrittled film at a determined depth relative to the implanted face of the initial substrate, thus delimiting a thin...

20050282359 - Wafer processing method: A wafer processing method for dividing a wafer having function elements in area sectioned by dividing lines formed on the front surface in a lattice pattern into individual chips along the dividing lines, comprising a deteriorated layer forming step for forming a deteriorated layer on the side of the back...

20050282360 - Semiconductor wafer and manufacturing process for semiconductor device: A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a...

20050282361 - Semiconductor wafer and manufacturing process thereof: A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal...

20050282362 - Tape adhering method and tape adhering apparatus: A method and an apparatus for adhering a tape (3) on a wafer (20) are disclosed. The wafer is supported on a table (31), and the tape is supplied, between a tape adhering surface (20′) and a tape adhering unit (46), from a tape supply unit (42). The table is...

20050282363 - Method of forming fine pattern of semiconductor device using sige layer as sacrificial layer, and method of forming self-aligned contacts using the same: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a...

20050282364 - Method of fabricating a semiconductor thin film and semiconductor thin film fabrication apparatus: A fabrication method of a semiconductor thin film including a polycrystalline semiconductor region by irradiating a precursor semiconductor thin film substrate with at least two types of laser beams, and melting-recrystallizing the precursor semiconductor thin film, wherein the radiation timing or power density of the at least two types of...

20050282365 - Film formation apparatus and method for semiconductor process: A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas...

20050282366 - Method for monitoring ion implant doses: Both the sensitivity and the reproducibility of processes for measuring low density ion implant doses near a semiconductor surface have been improved by first forming a thermal oxide layer on the surface and then adjusting the implant profile so that it peaks at the semiconductor-oxide interface. Additionally, variations in the...

20050282367 - Semiconductor structure processing using multiple laser beam spots spaced on-axis on non-adjacent structures: Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first laser beam that propagates along a first laser beam axis that intersects the semiconductor...

20050282368 - Mask, method for producing the same, deposition method, electronic device, and electronic apparatus: A mask includes a first portion having an opening, a second portion disposed in the opening and surrounded by the opening, and a beam connecting the first portion to the second portion....

20050282369 - Enhanced step coverage of thin films on patterned substrates by oblique angle pvd: A method and an apparatus for fabricating an integrated circuit entail directing a vapor flux toward a substrate surface from a plurality of directions associated with a plurality of azimuth angles, and selecting a deposition angle of the vapor flux, relative to a normal incidence, to obtain a substantially conformal...

20050282370 - Selective salicidation methods: Methods for selective salicidation of a semiconductor device. The invention implements a chemical surface pretreatment by immersion in ozonated water H2O prior to metal deposition. The pretreatment forms an interfacial layer that prevents salicidation over an n-type structure. As a result, the invention does not add any additional process steps...

20050282372 - Semiconductor device and a method of manufacture therefor: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping...

20050282371 - Sequential station tool for wet processing of semiconductor wafers: Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for...

20050282373 - Radiation-emitting semiconductor element and method for producing the same: The invention also describes a production method for a semiconductor component pursuant to the invention. An interlayer (9) is first applied to a substrate (8), and a plurality of GaN layers (1) that constitute the semiconductor body of the component are then applied to this. The substrate (8) and the...

20050282374 - Method of forming a thin wafer stack for a wafer level package: A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or...

20050282376 - Method of making a semiconductor device having improved contacts: A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This...

20050282377 - Method of making a semiconductor device having improved contacts: A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This...

20050282375 - Semiconductor device and manufacturing method thereof: An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of...

20050282378 - Interconnects forming method and interconnects forming apparatus: An interconnects forming method and an interconnects forming apparatus are useful for embedding a conductive material (interconnect material), such as copper or silver, into interconnect recesses provided in a surface of a substrate, such as a semiconductor wafer, to thereby form embedded interconnects, and selectively covering the surfaces of embedded...

20050282379 - Spin transistor, programmable logic circuit, and magnetic memory: A spin transistor includes a first conductive layer that is made of a ferromagnetic material magnetized in a first direction, and functions as one of a source and a drain; a second conductive layer that is made of a ferromagnetic material magnetized in one of the first direction and a...

20050282380 - Method and apparatus for chemical mechanical polishing of semiconductor substrates: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a...

20050282381 - Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer: The disclosure relates to method and apparatus for isolating sensitive regions of a semiconductor device by providing a thermal path or an electromagnetic shield. The thermal path may include vias having different length, depth and configuration such that the thermal path between the two regions is lengthened. In addition, the...

20050282382 - Method of preventing photoresist poisoning of a low-dielectric-constant insulator: A method comprises forming a low-dielectric constant (low-k) layer over a semiconductor substrate, forming an anti-reflective layer over the low-k layer, forming at least one opening in the anti-reflective layer and in the low-k layer, forming a nitrogen-free liner in the at least one opening, and forming at least one...

20050282383 - Systems for forming insulative coatings for via holes in semiconductor devices: An insulative coating for an aperture of a semiconductor device component includes a plurality of adjacent, mutually adhered regions. The adjacent, mutually adhered regions may be formed by programmed material consolidation processes, such as stereolithography. Such an insulative coating may electrically isolate conductive features, such as conductive vias, from the...

20050282384 - Method for forming protective film and electroless plating bath: The present invention provides a method for forming a protective film selectively on metal interconnects, such as copper interconnects, of a substrate having an embedded interconnect structure, without causing the problem of contamination of the interconnects with an-alkali metal. The method for forming a protective film according to the present...

20050282385 - Conductive material patterning methods: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first...

20050282386 - Semiconductor device and fabrication process thereof: A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field effect transistor having a second polysilicon gate electrode...

20050282387 - Metal polish composition, polishing method using the composition and method for producing wafer using the polishing method: wherein m represents an integer of from 1 to 3 and n represents an integer of from 0 to 2, with m and n being such that (3-n-m) is an integer of from 0 to 2; A represents a straight-chained or branched alkylene, phenylene or substituted phenylene group having 1...

20050282388 - Imprinting lithography using the liquid/solid transition of metals and their alloys: A method is provided for imprinting a pattern having nanoscale features from a mold into the patternable layer on a substrate. The method comprises: providing the mold; forming the patternable layer on the substrate; and imprinting the mold into the patternable layer, wherein the patternable layer comprises a metal or...

20050282390 - Polishing composition for semiconductor wafers: An aqueous composition is useful for polishing semiconductor wafers. The composition comprises a nonionic surfactant that suppresses removal rate of silicon carbide-nitride and has a hydrophilic group and a hydrophobic group. The hydrophobic group has a carbon chain length of greater than three. And the nonionic surfactant suppresses silicon carbide-nitride...

20050282389 - Semiconductor device fabrication method: A semiconductor device fabrication method according to the invention comprises the steps of: (1) exposing a silicon layer by removing a portion of an insulating layer above a projected part of the silicon layer, the insulating layer covering the silicon layer; and (2) chemically and mechanically polishing the exposed silicon...

20050282391 - Method of polishing a tungsten-containing substrate: The invention provides a method of chemically-mechanically polishing a substrate comprising tungsten through use of a composition comprising a tungsten etchant, an inhibitor of tungsten etching, and water, wherein the inhibitor of tungsten polishing is a polymer, copolymer, or polymer blend comprising at least one repeating group comprising at least...

20050282392 - Sti formation in semiconductor device including soi and bulk silicon regions: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI...

20050282393 - Structure and method for collar self-aligned to buried plate: A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench....

20050282394 - Method for manufacturing a semiconductor device: In a method for manufacturing a semiconductor device, a first high frequency power of a first frequency is applied to a processing gas to generate a plasma of the processing gas, a second high frequency power of a second frequency smaller than the first frequency is applied to a substrate...

20050282395 - Method for forming an improved low power sram contact: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said...

20050282396 - Micro-etching method to replicate alignment marks for semiconductor wafer photolithography: A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to...

20050282397 - Semiconductor constructions: The invention includes semiconductor processing patterning methods and semiconductor constructions. A semiconductor processing patterning method includes forming a second composition resist layer over a different first composition resist layer. Overlapping portions of the first and second composition resist layers are exposed to actinic energy effective to change solubility of the...

20050282398 - Oxygen plasma treatment for enhanced hdp-cvd gapfill: Methods are provided for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A process gas having a silicon-containing gas, an oxygen-containing gas, and a fluent gas is flowed into the substrate processing chamber. The...

20050282399 - Electroformed metallization: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming...

20050282400 - Method of forming a dielectric film: A method of forming a dielectric film on a substrate surface includes the steps of forming the dielectric film on the substrate surface in plural steps, and reforming, in each of the plural steps of forming the dielectric film, the dielectric film in an ambient primarily of nitrogen....

20050282402 - Resist for forming pattern and method for forming pattern using the same: A method for forming a pattern includes forming an etching object layer on a substrate, applying a resist on an etching object layer, the resist including a photo-initiator, and a liquid pre-polymer including a vinyl functional group and a hydrophilic functional group, shaping the resist using a mold plate having...

20050282401 - Zeolite films for low k applications: A method is provided for making an integrated circuit dielectric. A structure-directing agent (SDA) is provided. Preferably this structure-directing agent is a salt of a polycyclic organic compound. By use of the structure-directing agent, a film of a zeolite having a framework density below 15 T atoms per 1000 cubic...

20050282403 - Ceramic electronic device and the production method: A ceramic electronic device having a dielectric layer, wherein the dielectric layer includes a main component containing a (Ba, Ca (Ti, Zr)O3 based material and a subcomponent containing an oxide of Si; and a content of the Si oxide is 0 to 0.4 wt % (note that 0 is not...

20050282404 - Hermetic cap layers formed on low-k films by plasma enhanced chemical vapor deposition: A method of forming a cap layer over a dielectric layer on a substrate including forming a plasma from a process gas including oxygen and tetraethoxysilane, and depositing the cap layer on the dielectric layer, where the cap layer comprises a thickness of about 600 Å or less, and a...

20050282408 - Method for crystallizing semiconductor with laser beams: Laser beams emitted by a plurality of laser sources are divided into a plurality of sub-beams, which are irradiated onto selected portions of an amorphous semiconductor on a substrate to crystallize the amorphous semiconductor. A difference in diverging angles between the laser beams is corrected by a beam expander. The...

20050282407 - Semiconductor structure processing using multiple laser beam spots spaced on-axis delivered simultaneously: Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first laser beam that propagates along a first laser beam axis that intersects the semiconductor...

20050282406 - Semiconductor structure processing using multiple laterally spaced laser beam spots delivering multiple blows: Methods and systems process a semiconductor substrate having a plurality of structures to be selectively irradiated with multiple laser beams. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The method generates a first laser beam that propagates along a first laser...

20050282405 - Vacuum system for immersion photolithography: A vacuum system for extracting a stream of a multi-phase fluid from a photolithography tool comprises a pumping arrangement for drawing the fluid from the tool, and an extraction tank located upstream from the pumping arrangement for separating the fluid drawn from the tool into gas and liquid phases. The...

20050277207 - Mask schemes for patterning magnetic tunnel junctions: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material...

20050277208 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device, comprising forming an insulating film above a semiconductor substrate having an element formed thereon, forming an anti-reflection layer that is impermeable to hydrogen on the insulating film, the anti-reflection layer comprising a layer formed of at least one material selected from...

20050277206 - Structure and method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory: A method of patterning a magnetic tunnel junction (MTJ) stack is provided. According to such method, an MTJ stack is formed having a free layer, a pinned layer and a tunnel barrier layer disposed between the free layer and the pinned layer. A first area of the MTJ stack is...

20050277209 - Plasma leak monitoring method, plasma processing apparatus and plasma processing method: In a plasma processing apparatus that forms plasma from a process gas by supplying the process gas into a processing container and applying high-frequency power to an electrode provided inside the processing container on which a workpiece is placed and executes specific plasma processing on the processing surface of the...

20050277210 - Sequential unique marking: The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of semiconductor devices therein, reading an ID code on the multi-die handling device, retrieving a tray map file corresponding to the ID code, determining a tray matrix of the multi-die handling...

20050277213 - Process for making light waveguide element: A light waveguide element is made by forming only an upper clad layer (40) and a core layer (32) without etching an optical axis height-adjusting sections. By using plasma chemical vapor deposition (CVD) which is good at controlling the film thickness, it is possible to provide without difficulty a light...

20050277212 - Semiconductor element, semiconductor device, and method for fabrication thereof: A nitride semiconductor growth layer is laid on a substrate having an engraved region provided with a depressed portion....

20050277211 - Semiconductor optical devices and method for forming: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the...

20050277216 - Method for making a semiconductor device: A method of making a semiconductor device comprising a semiconductor element and a support member having a recess for housing the semiconductor element is disclosed. The method includes placing at least two lead electrode portions in the molding die; supplying a molding member to the molding die so that the...

20050277214 - Nitride single crystal and producing method thereof: A method of producing a nitride single crystal includes the step of forming a material transport medium layer containing a compound of rare earth element on a surface of a nitride crystal, and the step of making a seed crystal in contact with the material transport medium layer to grow...

20050277215 - Optically pumped edge-emitting semiconductor laser: A multilayer semiconductor laser includes a substrate on which is formed a semiconductor multilayer heterostructure divided into a plurality of electrically pumped regions and an elongated optically pumped region. The electrically pumped regions generate and deliver optical pump radiation laterally into the elongated optically pumped region. Output radiation is generated...

20050277217 - Method for manufacturing micro-structural unit: A method for manufacturing a micro-structural unit is provided. By the method, micro-machining is performed on a material substrate including first through third conductive layers and two insulating layers, one of which is interposed between the first and the second conductive layers, and the other between the second and the...

20050277218 - Group iii nitride compound semiconductor light-emitting device and method for producing the same: In a Group III nitride compound semiconductor light-emitting device which outputs lights from a semiconductor plane, about 1.5 μm in height of a Group III nitride compound semiconductor projection part 150, which is made of Mg-doped p-type GaN having Mg doping concentration of 8×1019/cm3 and is formed through selective growth,...

20050277219 - Sensor design and process: An accelerometer (305) for measuring seismic data. The accelerometer (305) includes an integrated vent hole for use during a vacuum sealing process and a balanced metal pattern for reducing cap wafer bowing. The accelerometer (305) also includes a top cap press frame recess (405) and a bottom cap press frame...

20050277220 - Encapsulation for particle entrapment: A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents the generation of debris that could interfere with the operation of the micromechanical device (100). Debris-generating regions of the device (100), including debris-creating sidewalls and any debris-harboring cavities, as well as...

20050277221 - Array connector having improved electrical characteristics and increased signal pins with decreased ground pins: An electrical connector includes a connector body, a plurality of rows and columns of conductive pins disposed along the length direction and the width direction of the connector body so as to form an array of signal pins located in a pin field, at least two rows of ground pins...

20050277222 - Organic electroluminescent display device and method of preparing the same: An organic electroluminescent display device and a method of preparing the same are provided. The organic electroluminescent display device may include a first electrode formed on a substrate. A second electrode may be formed so as to be insulated from the first electrode. One or more organic layers may be...

20050277223 - Method of forming metal oxide using an atomic layer deposition process: where M represents a metal, L1 and L2 respectively represents a first and second ligands. In addition, x and y are independently integers and a value of (x+y) is 3 to 5. An oxygen-containing compound is introduced into the chamber to form the metal oxide. The metal oxide is formed...

20050277224 - Base material for forming diamond film and diamond film: There is disclosed a base material for forming a diamond film by vapor phase synthesis, wherein diamond particles having a particle diameter of 2 nm to 100 nm exist at a density of 1 ×108 to 1 ×1013 number/cm2 on a surface of the base material, and spaces among the...

20050277225 - Method for production of semiconductor package: A method for production of a semiconductor package which enables uniform conduction processing for all through holes covered by the conduction processing without being limited to any specific structure, is free from surface relief shapes and internal voids, and enables conduction processing simply, in a short time, at a low...

20050277227 - Chip scale package with open substrate: A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the...

20050277226 - High density flip chip interconnections: A printed circuit board has, on one surface thereof, a plurality of metallic pads forming or leading to wire traces. The printed circuit board surface is solder mask free and a substantially runless soldering alloy is used to connect I/O solder bumps on a flip chip to the metallic pads....

20050277228 - Method and apparatus for forming interposers on integrated circuits: A method and apparatus to stencil interposers on a wafer of dies is described. In one embodiment, an interposer stenciling apparatus includes an interposer forming stencil configured to deposit interposer material onto a backside of a wafer of dies in a predetermined formation. In another embodiment, another interposer forming stencil...

20050277229 - Chip packaging structure and method of making wafer level packaging: The present invention provides a chip packaging structure and method of making wafer level packaging. Chip packaging structure comprises a chip, a dam formed surrounding the perimeter of the chip, and a frame glue coated over the surface of the dam. A transparent cover is formed on the top of...

20050277230 - Process for producing a chip arrangement provided with a molding compound: A semiconductor device includes a semiconductor chip with a plurality of bonding pads at an upper surface and a passivation layer overlying the upper surface. A rewiring layer electrically coupling ones of the bonding pads to corresponding ones of a plurality of contact pads. The rewiring layer is formed by...

20050277231 - Underfill and encapsulation of semicondcutor assemblies with materials having differing properties and methods of fabrication using stereolithography: Polymerized materials for forming the underfill and encapsulation structures for semiconductor package are disclosed. A filler constituent, such as boron nitride, silicates, elemental metals, or alloys, may be added to a liquid photopolymer resin to tailor the physical properties thereof upon curing. The filler constituents may be employed to alter...

20050277232 - Diode junction poly fuse: System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are doped with a first impurity,...

20050277233 - Semiconductor device and method of manufacturing the same: In a method of obtaining a crystalline silicon film having high crystallinity at a low temperature and for a short time by using a catalytic element and using both a heat treatment and irradiation of laser light, a catalytic element which does not require a gettering step is used as...

20050277234 - Flexible carbon-based ohmic contacts for organic transistors: The present invention relates to a system and method of organic thin-film transistors (OTFTs). More specifically, the present invention relates to employing a flexible, conductive particle-polymer composite material for ohmic contacts (i.e. drain and source)....

20050277236 - Method for manufacturing semiconductor device: It is an object of the present invention to control the position in crystal lateral growth of a semiconductor film without making a system cumbersome and complicated. A method for manufacturing a semiconductor device according to the present invention includes the step of forming a semiconductor film over an insulating...

20050277235 - Methods of manufacturing semiconductor devices having single crystalline silicon layers and related semiconductor devices: Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated...

20050277238 - Method of manufacturing a semiconductor device: The present invention provides a method of manufacturing a semiconductor device comprising: preparing a support substrate; forming first and second active regions and a field region in a surface of the support substrate; forming a first gate insulating film in the first and second active regions; covering the entire surface...

20050277237 - Structure from which an integrated circuit may be fabricated and a method of making same: Deep silicidation of a polysilicon gate electrode following high temperature annealing of a source/drain under the gate may damage the gate oxide. This damage is prevented by forming the gate electrode as two polysilicon layers separated by a chemical oxide. During annealing the chemical oxide prevents the grains of one...

20050277239 - Method for manufacturing cmos image sensor: A method for manufacturing a CMOS image sensor is provided. The method includes forming a gate electrode on a semiconductor layer having defined regions of a photodiode region and a logic region, such that a gate oxide film is interposed between the semiconductor layer and the gate electrode; forming sidewall...

20050277240 - Logic components from organic field effect transistors: The invention makes it possible, for the first time, to produce, despite conventional p-type MOS technology, fast logical gates based on organic field effect transistors. This is primarily due to the early saturation effect of OFETs having very thin semi-conducting layers, and, furthermore, to the use of OFETs having specific...

20050277242 - Method for fabricating a deep trench capacitor of dram device: A method for fabricating a deep trench capacitor of DRAM devices is disclosed. A substrate with a deep trench formed therein is provided. The trench is then doped to form a buried plate electrode serving as a first electrode of the deep trench capacitor at a lower portion of the...

20050277241 - Semiconductor device and ic card: In an IC card in which an internal circuit is operated by an internal power supply formed from alternate current from outside received by an antenna, the voltage of the internal power supply sometimes changes due to the operation of the internal circuit. Therefore, the voltage controlling circuit of the...

20050277243 - Flash memory having a high-permittivity tunnel dielectric: A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be...

20050277244 - Method for fastening microtool components to objects: A microtool for embossing structures into a substrate is fastened to an object, such as a press plate, by sintering, preferably pressure sintering. An insight underlying the invention is the fact that such a sintering or pressure sintering method provides a sufficiently reliable, strong, heat conducting and/or dimensionally stable connection,...

20050277245 - Method for forming bump on electrode pad with use of double-layered film: A process for forming bumps on electrode pads for a wiring board including a substrate and a plurality of electrode pads. The process (a) forms a laminated two-layer film on the wiring board and forms a pattern of apertures at positions corresponding to the electrode pads, the laminated two-layer film...

20050277246 - Formation of doped regions and/or ultra-shallow junctions in semiconductor materials by gas-cluster ion irradiation: Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams....

20050277247 - Method for fabricating a trench capacitor of dram: This invention discloses a method for fabricating a deep trench capacitor. A substrate is provided. A pad oxide layer and a pad nitride layer are stacked on a main surface of the substrate. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride...

20050277248 - Methods of forming void-free layers in openings of semiconductor substrates: In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially...

20050277250 - Method for fabricating a floating gate memory device: Roughly described, a device having twin bit floating gate memory cells is fabricated by first providing a substrate having formed thereon, within a memory area, a composite charge storage film and a protective liner layer over the composite film. The memory area further includes oxide features over buried diffusion regions...

20050277251 - Method of manufacturing flash memory device: Provided relates to a method of a flash memory device, which performs a first rapid thermal oxidation process at a H2 rich atmosphere for recovering an etched damage during a gate forming process, and performs a second rapid thermal oxidation process at the H2 rich atmosphere for ion-activating after performing...

20050277249 - Methods for forming semiconductor structures: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as...

20050277252 - Methods of forming a gate structure of a non-volatile memory device and apparatus for performing the same: Methods of forming a gate structure of a non-volatile memory device include forming a gate pattern having a control gate on a semiconductor substrate. An oxidation-preventing layer is formed on the control gate in a process chamber while maintaining a substantially oxygen free atmosphere in the process chamber. An oxide...

20050277253 - Non-volatile memory and method of manufacturing the same: A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating...

20050277254 - Methods of forming device with recessed gate electrodes: Methods are provided for forming a device, such as a semiconductor device. A field region and an active region of a substrate are defined in which the field region has an upper surface that extends further away from the substrate and is higher than an upper surface of the active...

20050277255 - Compound semiconductor device and manufacturing method thereof: A pad electrode of a high electron mobility transistor is formed solely of a pad metal layer without providing a gate metal layer. A high concentration impurity region is provided below the pad electrode, and the pad electrode is directly contacted to a substrate. Predetermined isolation is ensured by the...

20050277256 - Nanolaminates of hafnium oxide and zirconium oxide: A dielectric film containing a HfO2/ZrO2 nanolaminate and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric layer containing a HfO2/ZrO2 nanolaminate may be realized in a wide variety of electronic devices and systems....

20050277257 - Gap filling with a composite layer: A method of filling a gap formed between adjacent raised surfaces on a substrate. In one embodiment the method comprises depositing a boron-doped silica glass (BSG) layer over the substrate to partially fill the gap using a thermal CVD process; exposing the BSG layer to a steam ambient at a...

20050277259 - Manufacturing method of gate oxidation films: After forming a field insulating film 12 on a substrate, sacrificing or gate oxidation films are formed as oxidation films 14a and 14b. An ion implantation layer 18 is formed by one or plurality of implantation process of argon (or fluoride) ion in an element hole 12a using a resist...

20050277258 - Method for forming self-aligned contact in semiconductor device: A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized...

20050277260 - Mixed orientation and mixed material semiconductor-on-insulator wafer: The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations....

20050277261 - Method for manufacturing cell transistor: Disclosed herein is a method of manufacturing a cell transistor which can achieve an improvement in a short-channel effect of a cell transistor as well as an improvement in a refresh characteristic of the transistor, and can also prevent a reduction in the threshold voltage of the transistor, in relation...

20050277262 - Method for manufacturing isolation structures in a semiconductor device: A method for manufacturing isolation structures in a semiconductor device includes providing a substrate with a surface. A plurality of ions are implanted below the surface of the substrate and the substrate is then annealed to form a layer below its surface. Isolation structures may then be formed in the...

20050277263 - Forming shallow trench isolation without the use of cmp: Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so...

20050277264 - Improved process for forming a buried plate: A method is provided for making a buried plate region in a semiconductor substrate. According to such method, a trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed below the upper portion. A dopant source...

20050277265 - Methods of forming trench isolation layers using high density plasma chemical vapor deposition: A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed....

20050277267 - Method for manufacturing a compound material wafer: The invention relates to a method for manufacturing a compound material wafer. The technique includes forming a weakened zone in a source substrate, attaching the source substrate to a handle substrate to form a source-handle assembly, and thermally annealing the source-handle assembly to further weaken the weakened zone. The method...

20050277266 - Process for interfacial adhesion in laminate structures through patterned roughing of a surface: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves,...

20050277268 - Manufacturing method of semiconductor wafer having lid part and manufacturing method of semiconductor device: An adhesive layer containing a photo-curing adhesive and a thermosetting adhesive is formed on a semiconductor wafer in which a plurality of semiconductor elements are formed. The adhesive layer and the semiconductor wafer are adhered together by selectively exposing the adhesive layer to light and curing the photo-curing adhesive contained...

20050277269 - Method of manufacturing a material compound wafer: The invention relates to a method for manufacturing a material compound wafer by forming a predetermined splitting area in a source substrate; attaching the source substrate to a handle substrate to form an assembly; heating the assembly for weakening the predetermined splitting area; and determining a degree of weakening of...

20050277270 - Wafer processing method: A wafer processing method for carrying out processing by applying a laser beam along streets formed on a wafer, comprising a step of applying a laser beam at an incident angle of a predetermined inclination angle to the normal line of a processing surface of the wafer while the wafer...

20050277271 - Raised sti process for multiple gate ox and sidewall protection on strained si/sgoi structure with elevated source/drain: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric...

20050277272 - Low temperature epitaxial growth of silicon-containing films using uv radiation: A method of preparing a clean substrate surface for blanket or selective epitaxial deposition of silicon-containing and/or germanium-containing films. In addition, a method of growing the silicon-containing and/or germanium-containing films, where both the substrate cleaning method and the film growth method are carried out at a temperature below 750° C.,...

20050277273 - Method for introducing impurities and apparatus for introducing impurities: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous...

20050277274 - Method of synthesizing hybrid metal oxide materials and applications thereof: The present invention relates to metal oxide coating materials that can be used as thin film thin film coatings on various substrate surfaces. The invention also concerns a method of making metal oxide material which are stable in aqueous phase and that can be deposited on a substrate by liquid...

20050277275 - Method for forming a semiconductor device having a silicide layer: A method for forming a semiconductor device includes providing a semiconductor substrate, forming an insulating layer over the semiconductor substrate, forming a conductive layer over the insulating layer, forming a first metal silicide layer over the conductive layer, patterning the conductive layer to form a patterned first layer, wherein the...

20050277276 - Decoupled complementary mask patterning transfer method: A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM), then etching a cut mask for a cPSM mask. Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning...

20050277277 - Dual damascene process: A method of photoresist processing includes forming a first photoresist layer over composite layers of dielectric insulation and a top insulating layer and patterning a via hole pattern in the first photoresist layer by exposing to radiation of a first sensitivity. A second photoresist layer is formed over via patterned...

20050277278 - Method of manufacturing a wafer: The present invention relates to a method of manufacturing a semiconductor wafer that includes providing a substrate of a single crystalline first material that has an unfinished or rough surface, and epitaxially growing at least one layer of a second material directly on the unfinished or rough surface of the...

20050277279 - Microfeature devices and methods for manufacturing microfeature devices: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a...

20050277280 - Semiconductor device with a high thermal dissipation efficiency: Provides semiconductor devices and method for fabricating devices having a high thermal dissipation efficiency. An example device comprises a thermally conducting structure attached to a surface of the semiconductor device via soldering. The thermally conducting structure is essentially formed of a thermally conducting material and comprises an array of freestanding...

20050277283 - Chip structure and method for fabricating the same: A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first...

20050277281 - Compliant interconnect and method of formation: A method for making a compliant interconnect with two or more layers of metal is described herein....

20050277282 - Method of manufacturing wiring substrate: A method of manufacturing a wiring substrate of the present invention, includes a step of preparing a substrate containing a semi-cured resin layer or a thermo plastic resin layer, a step of forming a through hole that passes through the substrate, a step of inserting a conductive parts in the...

20050277284 - Method for manufacturing a semiconductor device: A method for manufacturing a semiconductor device includes forming first wirings assigned in a first region and second wirings assigned in a second region having a lower wiring density than the first region; covering the first and second wirings with a sacrificial film; reducing a thickness of the sacrificial film...

20050277285 - Method of fabricating an interconnect structure having reduced internal stress: A copper damascene process is provided. A semiconductor substrate having a base dielectric layer thereon is prepared. A first damascened copper interconnect structure is formed in the base dielectric layer. The first damascened copper interconnect structure is capped with a dielectric barrier; Subsequently, multiple chemical vapor deposition (CVD) cycles within...

20050277287 - Contact etching utilizing multi-layer hard mask: A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard...

20050277289 - Line edge roughness reduction for trench etch: A method for etching a trench to a trench depth in a dielectric layer over a substrate is provided. An ARC is applied over the dielectric layer. A photoresist mask is formed on the ARC, where the photoresist mask has a thickness. The ARC is etched through. A trench is...

20050277286 - Metallic glass microtool: Embodiments of the invention provide microtool made at least partially from a metallic glass material. The metallic glass material may allow formation of smaller features than achieved with other materials. The microtool may be used in some embodiments to form a package substrate with small feature sizes....

20050277288 - Stackable semiconductor chip layer comprising prefabricated trench interconnect vias: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations...

20050277290 - Integration of titanium and titanium nitride layers: Embodiments of the invention generally relate to an apparatus and method of integration of titanium and titanium nitride layers. One embodiment includes providing one or more cycles of a first set of compounds such as a titanium precursor and a reductant, providing one or more cycles of a second set...

20050277291 - Method of manufacturing electronic device: A method of manufacturing an electronic device comprises forming a wiring material layer made of aluminum or an aluminum alloy on the surface of an insulating film on a substrate, patterning the wiring material layer by a reactive ion etching treatment with a resist pattern used as a mask so...

20050277292 - Method for fabricating low resistivity barrier for copper interconnect: A method of reducing the sheet resistivity of an ALD-TaN layer in an interconnect structure. The ALD-TaN layer is treated with a plasma treatment, such as Argon or Tantalum plasma treatment, to increase the Ta/N ratio of the ALD-TaN barrier layer, thereby reducing the sheet resistivity of the ALD-TaN layer....

20050277293 - Fabrication method of wafer level chip scale packages: A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may...

20050277295 - Coating process for patterned substrate surfaces: The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height...

20050277294 - Method for treating a semiconductor surface to form a metal-containing layer: A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor...

20050277296 - Method to reduce impurity elements during semiconductor film deposition: A metal-containing semiconductor layer having a high dielectric constant is formed with a method that avoids inclusion of contaminant elements that reduce dielectric constant of metals. The metal-containing semiconductor layer is formed overlying a substrate in a chamber. A precursor is introduced to deposit at least a portion of the...

20050277298 - Adhesion of copper and etch stop layer for copper alloy: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual...

20050277297 - Copper nanocrystals and methods of producing same: The invention relates to methods of making monodisperse nanocrystals comprising the steps of reducing a copper salt with a reducing agent, providing a passivating agent comprising a nitrogen and/or an oxygen donating moitey and isolating the copper nanocrystals. Moreover, the invention relates to methods for making a copper film comprising...

20050277299 - Methods for fabricating read sensor for magnetic heads with reduced read track width: The fabrication of the read head sensor components where chemical mechanical polishing (CMP) stop layer is deposited above the sensor layers, a first reactive ion etch (RIE) layer and a second RIE layer are deposited, where the second RIE layer is etchable with a different ion species than the first...

20050277300 - Method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits: A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed;...

20050277301 - Method for forming a plane structure: A method for forming a plane structure. It comprises the following steps: forms a liquid material with a thicker thickness on a substrate, rotating both the liquid material and the substrate around the axis of the substrate, applying a solvent on the rotating liquid material to remove partial liquid material....

20050277302 - Advanced low dielectric constant barrier layers: Methods are provided for depositing a doped barrier layer material having a low dielectric constant. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate by introducing a processing gas comprising an organosilicon compound, at least one dopant containing gas,...

20050277303 - Forming porous diamond films for semiconductor applications: The porosity of a diamond film may be increased and its dielectric constant lowered by exposing a film containing sp3 hybridization to ion implantation. The implantation produces a greater concentration of sp2 hybridizations. The sp2 hybridizations may then be selectively etched, for example, using atomic hydrogen plasma to increase the...

20050277304 - Titanium silicate films with high dielectric constant: A method of making a film with a high dielectric constant uses a spin-on sol-gel process to deposit the film on a substrate, the film having a composition (SiO2)x(TiO2)1-x, where 0.50<x<0.75. The resulting film is annealed in an oxygen-containing atmosphere at a temperature lying in the range of 500° C....

20050277305 - Driving method for galvano scanner: A galvano scanner system has a galvano scanner and a scanner driver for driving the scanner, wherein a microcomputer for generating commands in which digital data representing a drive pattern of the scanner is written is mounted in the scanner driver. The microcomputer for generating commands is actuated by an...

20050272171 - Method for manufacturing ferroelectric capacitor, method for manufacturing ferroelectric memory, ferroelectric capacitor and ferroelectric memory: A method for manufacturing a ferroelectric capacitor in accordance with the present invention includes: (a) a step of forming a ferroelectric laminated body by successively laminating a lower electrode layer, a ferroelectric layer and an upper electrode layer over a base substrate; (b) a step of patterning at least the...

20050272170 - Method of manufacturing ferroelectric film capacitor: A method of manufacturing a ferroelectric film capacitor includes forming a platinum film used as an electrode material over a whole surface of a silicon substrate, batch-etching the platinum film to form opposite electrodes that serve as a pair of capacitor electrodes, and embedding a ferroelectric film corresponding to a...

20050272172 - Method of temporarily securing a die to a burn-in carrier: A method of using adhesive tape to temporarily retain a die being temporarily held in a fixture during testing and burn-in. The method of the present invention uses a die cut piece of adhesively coated tape to hold a die in a test and burn-in fixture. Upon subsequent heating of...

20050272173 - Method for testing contact open in semiconductor device: The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching...

20050272174 - Test structures in unused areas of semiconductor integrated circuits and methods for designing the same: The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the...

20050272175 - Laser structuring for manufacture of thin film silicon solar cells: A method of manufacturing thin-film, series connected silicon solar cells having a ZnO TCO layer, for example, using an ultraviolet scribing laser to scribe said ZnO TCO layer to form relatively smooth walls through said TCO layer....

20050272176 - Method for forming led by a substrate removal process: The present invention relates to a method for forming LED. In the present invention, LED dies are defined by photolithography and etching processes to replace a cutting step, and a metal substrate of the LED is formed by chemical or physical method....

20050272178 - Liquid crystal display device and method for fabricating the same: An LCD device including: a gate line on a substrate along a first direction; a data line in a second direction perpendicular to the gate line to define a unit pixel region, wherein the data line has recesses on a first side of the data line; a repair pattern having...

20050272177 - Method and structure for fabricating smooth mirrors for liquid crystal on silicon devices: A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method includes forming an interlayer dielectric layer (e.g.,...

20050272179 - Three-dimensional lithographic fabrication technique: Embodiments of a structure and embodiments of methods for fabricating structures provide three dimensional features defined by exposure to multiple wavelengths of light. In an embodiment, material is exposed to two different wavelengths of light. Embodiments of three dimensional structures may provide a variety of three-dimensional structural features and characteristics....

20050272180 - Semiconductor photodetecting device and method for fabricating the same: A semiconductor photodetecting device including a PIN photodiode formed on an SI—InP substrate; a buried optical waveguide portion formed on the SI—InP substrate and including the film thickness continuously increased toward the PIN photodiode and an InP clad layer covering the upper surface and the side surface of the InGaAsP...

20050272181 - Process for producing a flat panel radiation detector and a flat panel radiation detector: Because a restricting plate 27 is disposed using a spacer 25, an upper plate 15 is allowed to expand upward when resin is injected, but unnecessary overexpansion is restricted by the restricting plate 27. Therefore the injection of a slightly larger amount of resin 37 does not cause a distortion...

20050272182 - Methods of making microelectronic packages: A method of making a microelectronic package includes providing a first substrate having a top surface, providing a second substrate having a top surface including a plurality of conductive pads, a bottom surface remote therefrom and an opening extending between the top and bottom surfaces, and securing the second substrate...

20050272183 - Arrayed ultrasonic transducer: An ultrasonic transducer comprises a stack having a first face, an opposed second face and a longitudinal axis extending therebetween. The stack comprises a plurality of layers, each layer having a top surface and an opposed bottom surface, wherein the plurality of layers of the stack comprises a piezoelectric layer...

20050272184 - Crystallizing method, thin-film transistor manufacturing method, thin-film transistor, and display device: A crystallizing method of causing a phase shifter to phase-modulate a laser beam whose wavelength is 248 nm or 300 nm or more from an excimer laser unit into a laser beam with a light intensity profile having a plurality of inverted triangular peak patterns in cross section and of...

20050272185 - Method of fabricating a semiconductor thin film and semiconductor thin film fabrication apparatus: A fabrication method of a semiconductor thin film including a polycrystalline semiconductor region by irradiating a precursor semiconductor thin film with at least two types of laser beams, and melting-recrystallizing the precursor semiconductor thin film, wherein the precursor semiconductor thin film is irradiated with a predetermined reference laser beam, and...

20050272186 - Method for forming a lightly doped drain in a thin film transistor: In accordance with the present invention, a gate electrode structure with inclined planes is used as a mask when performing an ion implantation process. The inclined planes are used to define the lightly doped drain (LDD) region in the active area. Therefore, the width of the LDD can be defined...

20050272187 - Process for ultra-thin body soi devices that incorporate epi silicon tips and article made thereby: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a...

20050272188 - Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for cmos performance enhancement: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a...

20050272189 - Method of manufacturing thin film transistor array panel: A method of manufacturing a thin film transistor array panel is provided, which includes forming a semiconductor layer of poly silicon, forming a gate insulating layer on the semiconductor layer, forming a conductive layer including a first metal layer and a second metal layer formed on the first metal layer,...

20050272190 - Methods of fabricating fin field-effect transistors having silicide gate electrodes and related devices: A method of fabricating a fin field-effect transistor includes forming a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate, and forming a polysilicon gate electrode on sidewalls of the channel region. Opposing sidewalls of the polysilicon gate...

20050272193 - Method for manufacturing semiconductor device: Disclosed is a method for manufacturing a semiconductor device. According to such a method, in forming a MOSFET to which a double spacer structure is applied, a first spacer of an oxide film is formed after only an upper gate conductive layer is primarily patterned, and then a second spacer...

20050272192 - Methods of forming fin field effect transistors using oxidation barrier layers and related devices: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing...

20050272191 - Replacement gate process for making a semiconductor device that includes a metal gate electrode: A method for making a semiconductor device is described. That method comprises forming a sacrificial layer on a substrate, and forming a trench within the sacrificial layer. After forming a dummy gate electrode within the trench, a hard mask is formed on the dummy gate electrode and within the trench....

20050272194 - Methods of forming integrated circuit devices including raised source/drain structures having different heights: Integrated circuit devices including raised source/drain structures having different heights are disclosed. An integrated circuit device can include a first raised source/drain structure having a first height above a substrate in a first region of the integrated circuit including devices formed at a first density. The integrated circuit device can...

20050272195 - Integrated circuit having pairs of parallel complementary finfets: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also...

20050272196 - Method of depositing a higher permittivity dielectric film: A method of depositing a high permittivity dielectric film on a doped silicon or silicon compound layer of a wafer. The method includes a first step of nitriding a specific element (A) such as hafnium Hf to form a nitride film (AxNy) on the silicon layer, wherein the specific element...

20050272197 - Semiconductor device: A semiconductor device having a dynamically-reconfigurable circuit mounted thereon for maintaining software compatibility independently of the arrangement of the dynamically-reconfigurable circuit is provided. Simultaneously with execution of software, the semiconductor device automatically generates data for reconfiguring the dynamically-reconfigurable circuit and driver software for operating the dynamic circuit, and replaces an...

20050272198 - Method of manufacturing nonvolatile semiconductor memory device: Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This...

20050272199 - Method of manufacturing a semiconductor device: In a method of manufacturing a semiconductor device, a first trench is formed in a first region of a substrate and a second trench is formed in a second region of the substrate different from the first region. A depth of the first trench is less than that of the...

20050272200 - Bismuth titanium silicon oxide, bismuth titanium silicon oxide thin film, and method for forming the thin film: A bismuth titanium silicon oxide having a pyrochlore phase, a thin film formed of the bismuth titanium silicon oxide, a method for forming the bismuth-titanium-silicon oxide thin film, a capacitor and a transistor for a semiconductor device including the bismuth-titanium-silicon oxide thin film, and an electronic device employing the capacitor...

20050272201 - Improved process for forming a buried plate: A method of making a buried plate region in a semiconductor substrate is provided. A trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed below the upper portion. A liner is formed along at least...

20050272203 - Modified source/drain re-oxidation method and system: Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash memory. For flash memory, greater control is gained over programming rates, erase rates,...

20050272202 - Random access memory: A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and...

20050272205 - Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit: A gate dielectric (150) for a gate (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate (140). The dielectric thickness on the other gate is controlled by the dopant concentration in the other gate. The gates may be gates of different MOS...

20050272204 - Method for manufacturing nand flash device: Disclosed is a method for manufacturing a NAND flash device. After a source line plug hole is formed, a drain contact plug hole is formed. The holes are filled with a conductive material film and are then polished. It is therefore possible to simplify the process since a blanket etch...

20050272206 - Nrom memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals: A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of a nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate...

20050272207 - Complementary analog bipolar transistors with trench-constrained isolation diffusion: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density...

20050272208 - Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique: Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance....

20050272209 - Method of isolating the current sense on power devices while maintaining a continuous stripe cell: An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes...

20050272210 - Method for manufacturing gate electrode of semiconductor device using aluminium nitride film: A method for manufacturing gate electrode of semiconductor device using an aluminium nitride film is provided, the method including cleaning a surface of a semiconductor substrate, nitriding the surface of the substrate, forming a gate dielectric film comprising an aluminium nitride film on the surface of a semiconductor substrate, depositing...

20050272211 - Adjustable shims and washers: A method comprising disposing an active device comprising a shape memory polymer upon a first surface; wherein the active device is operative to change at least one physical attribute in response to a thermal activation signal; activating the active device with a thermal activation signal to substantially decrease its modulus,...

20050272212 - Method of high precision printing for manufacturing organic thin film transistor: A method of high precision printing for manufacturing organic thin film transistor, comprising the following steps of: forming a gate on a substrate; forming an insulator layer on the substrate; forming a conducting wire electrode film on the insulator layer; forming a organic interlayer; forming a organic semiconductor layer on...

20050272213 - Method of manufacturing metal-oxide-semiconductor transistor: A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed...

20050272214 - Electrophoretic assembly of electrochemical devices: Methods are provided for making bipolar electrochemical devices, such as batteries, using electrophoresis. A bipolar device is assembled by applying a field that creates a physical separation between two active electrode materials, without requiring insertion of a discrete separator film or electrolyte layer....

20050272215 - Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide: Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer process, a strain compensating dielectric capping layer process during silicide formation, a two...

20050272216 - Method of making a semiconductor device, and semiconductor device made thereby: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540,...

20050272218 - Method of forming metal lower electrode of a capacitor and method of selectively etching a metal layer for the same: A method of forming a cylindrical lower electrode of a capacitor in which metal is used as a lower electrode of a capacitor. A metal capping layer is used in order to protect the inner walls of the cylindrical metal lower electrode. A sacrificial insulating layer is patterned to form...

20050272217 - Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (mis) capacitor: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first...

20050272219 - Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric...

20050272220 - Ultraviolet curing process for spin-on dielectric materials used in pre-metal and/or shallow trench isolation applications: A UV curing process for a dielectric material used in pre-metal and shallow trench isolation applications comprises coating a suitable dielectric material onto a substrate; and exposing the dielectric material to ultraviolet radiation in an amount effective to reduce an organic content and/or increase a density and./or increase a wet...

20050272221 - Method of reducing alignment measurement errors between device layers: An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on the first layer. Portions of the...

20050272222 - Method for the manufacture of electronic devices on substrates and devices related thereto: Methods for manufacturing electronic devices and devices produced by those methods are disclosed. One such method includes releasably bonding a first surface of a device substrate to a face of a first carrier substrate using a first bonding agent to produce a first composite substrate, where the face of the...

20050272223 - Method for dicing substrate: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within...

20050272224 - Method for dividing substrate: The present invention aims at providing a method for dividing a substrate that is capable of dividing each substrate into chips in the same square-like form without causing chip breaking and capable of forming all cleaved facets flat. In the method for dividing a substrate of the present invention, an...

20050272225 - Semiconductor processing: The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality...

20050272226 - Semiconductor wafer having electrically connected passive device chips, passive devices and semiconductor package using the same: A semiconductor wafer includes a plurality of passive device units, which are electrically connected across scribe lines. Passive device chips in the wafer that are adjacent to one another in a first direction are electrically connected in parallel, while passive device units adjacent to one another in a second direction...

20050272227 - Plasma processing apparatus and method: There is provided a plasma processing apparatus including a plasma generating unit for generating a plasma in a processing chamber in which a set processing is performed on a substrate serving as an object to be processed. The plasma processing apparatus further includes a particle moving unit for electrostatically driving...

20050272228 - Annealing apparatus, annealing method, and manufacturing method of a semiconductor device: An annealing apparatus, includes a substrate stage placing a semiconductor substrate; a light source facing the substrate stage, configured to irradiate a pulsed light at a pulse width of approximately 0.1 ms to 100 ms on a surface of the semiconductor substrate; and a mask configured to selectively reduce intensity...

20050272229 - Strained si formed by anneal: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming...

20050272230 - Complementary analog bipolar transistors with trench-constrained isolation diffusion: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density...

20050272231 - Gate-all-around type of semiconductor device and method of fabricating the same: A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a...

20050272232 - Method for forming gate electrode of semiconductor device: A method for forming a gate electrode of a semiconductor device is provided wherein a hard mask layer which is a nitride film is deposited and subjected to an additional surface deposition process so that a matrix structure of a nitride film surface becomes more compact to reduce an etching...

20050272233 - Recessed gate electrodes having covered layer interfaces and methods of forming the same: A gate electrode of a transistor can include an interface between a polysilicon conformal layer and a tungsten layer thereon in a trench in a substrate and a capping layer extending across the trench and covering the interface. Related methods are also disclosed....

20050272234 - Method for fabricating storage electrode of semiconductor device: The present invention discloses improved method for manufacturing semiconductor device wherein a barrier layer is formed by thermally treating a hard mask polysilicon layer for protecting the sacrificial oxide film and the hard mask polysilicon film from damages....

20050272235 - Method of forming silicided gate structure: A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions...

20050272237 - Dual damascene integration structure and method for forming improved dual damascene integration structure: Methods of densifying a porous ultra-low-k (ULK) dielectric material by using gas-cluster ion-beam processing are disclosed. Methods for gas-cluster ion-beam etching, densification, pore sealing and ashing are described that allow simultaneous removal of material and densification of the ULK interfaces. A novel ULK dual damascene structure is disclosed with densified...

20050272238 - Method for depositing and etching ruthenium layers: The present invention provides a method for purifying ruthenium sources to obtain high purity ruthenium metal and form a ruthenium metal pattern on a semiconductor substrate without the need for high temperature processing or a complex series of wet processes. A gas stream including ozone (O3) is brought into contact...

20050272236 - Method for forming bit line contact hole/contact structure: Disclosed is a method for forming a bit line contact hole/contact structure. The method of the present invention comprises steps of providing a substrate; forming a pluarality of word line structures on the substrate; forming a doped dielectric layer on the substrate having the word line structures formed thereon; defining...

20050272239 - Method for making a semiconductor device including band-engineered superlattice using intermediate annealing: A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of...

20050272240 - Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors: Shorting bars are provided for electrostatic discharge protection as a portion of trace deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers having traces in contact...

20050272241 - Method for forming interconnects on thin wafers: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing...

20050272242 - Formation method for conductive bump: A method for forming conductive bumps is applied to a wafer. An under-bump-metallurgy structure and a first photo resist layer are subsequently formed on the wafer. The first photo resist layer, such as a dry film, is patterned to have some openings and then a second photo resist layer is...

20050272243 - Method of manufacturing semiconductor device: A method of manufacturing a semiconductor device includes: (a) forming an insulating layer having a contact hole on a semiconductor section in which an element is formed; (b) forming an electrode pad on the insulating layer so that a depression or a protrusion remains at a position at which the...

20050272244 - Method for manufacturing circuit element, method for manufacturing electronic element, circuit substrate, electronic device, and electro-optical apparatus: The present invention aims to provide a mounting technology that prevents unnecessary consumption of materials. A method for manufacturing a circuit element includes the steps of: setting a semiconductor element on a stage so that a metal pad of the semiconductor element faces a head; changing positions of the head...

20050272246 - Integrated capacitor for rf applications: A precision RF passive component comprising: a silicon substrate; a first dielectric layer deposited above the silicon substrate; a first metal layer formed above the first dielectric layer; a second dielectric layer formed above the first metal layer; and a second metal layer formed above the second dielectric layer. In...

20050272248 - Low-k dielectric structure and method: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a suitable porous or low density permeable material. At an appropriate time, the underlying sacrificial material is decomposed and diffused away through the overlying permeable material. As a result, at least one void is created, contributing to...

20050272245 - Method for forming contact plug of semiconductor device: Disclosed is a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a plurality of contact plugs capable of preventing a self-aligned contact (SAC) fail during forming a plurality of contact holes formed by using a SAC etching process and a defect generation during performing...

20050272247 - Substrate processing method and fabrication process of a semiconductor device: A method of fabricating a semiconductor device includes the steps of forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath the interlayer insulation film is exposed at a bottom of the via-hole, forming a conductive barrier film on the interlayer insulation film so...

20050272249 - Method and system for producing conductive patterns on a substrate: A method of producing a conductive pattern on a substrate, including the steps of providing a surface of the substrate with a conductive layer, which is formed by providing the surface of the substrate at least partly with conductive particles, by directly using the adhesive power of the surface of...

20050272250 - Method of forming self-aligned contact and method of manufacturing semiconductor memory device by using the same: In an embodiment a method of forming self-aligned contacts in a semiconductor memory device includes: forming conductive stacks of conductive layers on a semiconductor substrate; forming insulating spacer layers on sidewalls of the conductive stacks; forming an insulating layer; forming a capping insulating layer covering portions of the insulating layer;...

20050272251 - Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of...

20050272252 - Circuit device: Provided is a circuit device capable of inhibiting an insulating layer from separating from a substrate. This circuit device comprises a substrate mainly constituted of metal including a first metal layer having a first thermal expansion coefficient, a second metal layer, formed on the first metal layer, having a second...

20050272253 - Method for alloy-electroplating group ib metals with refractory metals for interconnections: An electroplated metal alloy including at least three elements. A multilayer interconnection structure that includes a substrate that is an interior of the interconnection structure, a conductive seed layer exterior to the substrate, and an electroplated metal alloy layer including at least three elements exterior to the conductive seed layer....

20050272254 - Method of depositing low resistivity barrier layers for copper interconnects: We have discovered a method of providing a thin approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity,...

20050272255 - Method and structure for low k interlayer dielectric layer: An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overlying the first interlayer dielectric layer. A contact structure including metallization is...

20050272256 - Semiconductor device and fabricating method thereof: A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of...

20050272257 - Semiconductor device with reduced contact resistance: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device....

20050272258 - Method of manufacturing a semiconductor device and semiconductor device: According to one aspect of the present invention, provided is a method of manufacturing a semiconductor device, including: forming a first metal film on a substrate having a recessed portion in a surface thereof, by a plating method so as to bury the first metal film in at least part...

20050272259 - Method of pitch dimension shrinkage: Roughly described, a patterned first layer is provided over a second layer which is formed over a substrate. In a conversion process, first layer material is consumed at feature sidewalls to form third layer material at the feature sidewalls. The width of third layer material at each of the sidewalls...

20050272260 - Novel device structure having enhanced surface adhesion and failure mode analysis: A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness...

20050272261 - Plasma chemical vapor deposition method and plasma chemical vapor deposition device: A method for making the characteristics of the distribution of film thickness uniform is provided, avoiding generation of phase differences among streams of high-frequency electric power by manipulating the electrical characteristics of cables through which the high-frequency electric power is transmitted. Coaxial cables (19a to 19h and 24a to 24h)...

20050272262 - Methods of manufacturing semiconductor devices: Methods for manufacturing semiconductor devices are disclosed. In one example, the semiconductor device has a gate and source/drain regions formed on a substrate. One example method includes introducing transition metal (Ti) source or precursor so that the introduced Ti source is chemisorbed onto the surface of the substrate and Ti...

20050272263 - Roll to roll manufacturing of organic solar modules: The invention discloses for the first time how an organic component can be produced in a process designed entirely as a roll-to-roll process. The advantage of the continuous production method described here is, further, that the active regions of the active semiconductor layer are not exposed to unprotected solvents and/or...

20050272264 - Coupling for corrugated cable conduits for enclosing cables: A coupling is provided for corrugated conduits. The coupling is formed unitarily from a resin material and has first and second coupling halves that are joined unitarily along a living hinged. The halves can be rotated about the living hinge from an open position to a closed position. Ends of...

20050272265 - Dual damascene integration structure and method for forming improved dual damascene integration structure: Methods for forming a dual damascene dielectric structure in a porous ultra-low-k (ULK) dielectric material by using gas-cluster ion-beam processing are disclosed. These methods minimize hard-mask layers during dual damascene ULK processing and eliminate hard-masks in the final ULK dual damascene structure. Methods for gas-cluster ion-beam etching, densification, pore sealing...

20050272266 - Semiconductor device and its manufacturing method: In a fabrication method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of a silicon surface in advance, and the hydrogen is removed by exposing the silicon surface to a first inert gas plasma. Thereafter, plasma is generated...

20050272267 - Method suitable for batch ion etching of copper: A method for etching metal deposited on a substrate, the method comprising: depositing a metal layer above a substrate; coating at least a portion of the deposited metal layer with a photo-resist; pattering the photo-resist; etching the deposited metal layer with an inert gas plasma at an energy density of...

20050272268 - Method of producing substrate having patterned organosilane layer and method of using the substrate having the patterned organosilane layer: Provided are a method of producing a substrate having a patterned organosilane layer and a method of using the substrate having the patterned organosilane layer. The method of producing the substrate having the patterned organosilane layer, includes: coating organosilane on a substrate to obtain an organosilane layer; coating a photoresist...

20050272269 - Oxidizing method and oxidizing unit for object to be processed: An oxidizing method for an object to be processed according to the present invention includes: an arranging step of arranging a plurality of objects to be processed in a processing container whose inside can be vacuumed, the processing container having a predetermined length, a main supplying unit of an oxidative...

20050272270 - Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a p/n junction: A method for making a semiconductor device is described. That method comprises modifying a first surface, and forming a high-k gate dielectric layer on an unmodified second surface....

20050272272 - Semiconductor device and method for manufacturing the same: A semiconductor device and a method for forming the same. A dielectric layer is formed on a semiconductor substrate or on a lower electrode of a capacitor. Vacuum annealing is performed on the dielectric layer. Thus, impurities remaining in the dielectric layer can be effectively removed, and the dielectric layer...

20050272271 - Semiconductor processing method for processing substrate to be processed and its apparatus: A method for processing a target substrate (10) in a semiconductor processing apparatus (1) controls temperature of a first substrate (10) at a process temperature inside a process container (2), while supplying a process gas into the process container, thereby subjecting the first substrate to a semiconductor process, during which...

20050272273 - Method and apparatus for electrostatically maintaining substrate flatness: An apparatus and method for holding a substrate on a support layer in a processing chamber. The method includes the steps of positioning the substrate a predetermined distance from the support layer, introducing a plasma in the processing chamber, lowering the substrate to a point where the substrate engages the...

20050272274 - Apparatus for forming a semiconductor thin film: Disclosed are apparatus for forming a semiconductor film having an excellent crystallinity from a non-single crystal semiconducting layer formed on a base layer made of an insulating material. The apparatus includes a light source, a homogenizer for homogenizing an intensity distribution of the emitted light, an amplitude-modulation means for performing...

20050266586 - Stylus system for modifying small structures: An improved method for rapidly and accurately modifying small structures, including structures on a micron or nanometer scale, suitable for the repair of defects in lithographic photo-masks and semiconductors on a nano-scopic level. Features or samples repaired may be conductive or non-conductive. A single instrument can be employed to both...

20050266587 - Substrate support method: The present invention includes a method for supporting a substrate that features a chuck body having a body surface with a pin extending therefrom having a contact surface lying in a plane, with the pin being movably coupled to the chuck body to move with respect to the plane. To...

20050266588 - Optoelectronic component and method of fabricating same: The invention concerns an optoelectronic component comprising a layer stack that includes at least two active zones and a carrier that is applied to the layer stack. The invention further concerns a method of fabricating such an optoelectronic component....

20050266589 - Formation method of electroconductive pattern, and production method of electron-emitting device, electron source, and image display apparatus using this: In regard to an electroconductive pattern including a high resistivity region partially, by forming a pattern with a photosensitive resin, making the pattern absorb liquid containing a metal component, and baking this, an electroconductive film of metal oxide is formed, this electroconductive film is further covered by a gas shielding...

20050266590 - Electrophoretic display device: A electrophoretic display device is provided, which includes: a thin film transistor array panel including a substrate, gate and data lines formed on the substrate and crossing each other, switching thin film transistors electrically connected to the gate and data lines, a photo sensor formed on the substrate, and pixel...

20050266591 - Manufacturing process for ultra slim electrooptic display device unit: A porous semiconductor layer, a monocrystalline Si layer, and a SiO2 layer are formed on a monocrystalline Si substrate. The SiO2 layer of the peripheral circuit area is removed, leaving the SiO2 layer in the display area. A poly Si layer is formed in the display area by epitaxial growth,...

20050266592 - Method of fabricating an encapsulated chip and chip produced thereby: A method of fabricating an integrated circuit having a window therein for transmitting optical energy to and/or from an optically active area of the underlying die includes depositing a quantity of an uncured optically transmissive material on the die portion of a integrated circuit preform, placing the window on the...

20050266595 - Liquid crystal display device having goldd type tft and ldd type tft and method of making same: A liquid crystal display device includes a display region having unit pixels arranged thereon in a matrix, and a driving circuit unit having at least a LDD (Lightly Doped Drain) type TFT and a GOLDD (Gate overlapped Lightly Doped Drain) type TFT....

20050266594 - Manufacturing method for display device: A manufacturing method for a display device includes: a first thin film transistor that is formed in a first region over a substrate and has a first threshold value according to doping of a first impurity into a semiconductor layer in a channel region; and a second thin film transistor...

20050266593 - Wiring and manufacturing method thereof, semiconductor device comprising said wiring, and dry etching method: A dry etching method for forming tungsten wiring having a tapered shape and having a large specific selectivity with respect to a base film is provided. If the bias power density is suitably regulated, and if desired portions of a tungsten thin film are removed using an etching gas having...

20050266596 - Method of manufacturing electro-optical device: There is provided a method of manufacturing an electro-optical device from a large substrate that is cut into a plurality of first substrates having a chip shape. In the electro-optical device, second substrates of a chip shape are bonded to the first substrates. The method includes adhering a large glass...

20050266597 - Charge sweep operation for reducing image lag: A method and apparatus are disclosed for improving imager lag by using a charge sweep operation in which residual charge is swept out of the photodiode to reduce lag effects. The charge is swept out of the photodiode by activating the reset transistor a second time, substantially simultaneously with the...

20050266598 - Method for fabricating vertical offset structure: A method for fabricating a vertical offset structure that forms a complete vertical offset on a wafer includes a first trench forming step of forming first trenches on a wafer; a first etching step of performing a first patterning for determining etching positions of second and third trenches by depositing...

20050266599 - Method of manufacturing a micro-electrical-mechanical system: Micro-electrical-mechanical systems are fabricated in a substrate having a sacrificial layer sandwiched between two semiconductor layers. The semiconductor layers are selectively etched to create non-etched frames and etched microstructures immobilized within the frames by the sacrificial layer. An adhesive sheet is attached to one surface of the substrate, and the...

20050266600 - Low temperature nano particle preparation and deposition for phase-controlled compound film formation: The present invention is directed to different methods used in the formation of an ink, as well as being directed to the formation of layers used in the fabrication of a solar cell, particularly the absorber layer. In one embodiment, the invention is directed to formulating an ink comprising Cu-rich...

20050266602 - Encapsulated chip and method of fabrication thereof: A method of fabricating an integrated circuit having an optically transmissive window therein includes forming an integrated chip preform structure that includes a plurality of bonding wires connecting pads on a die structure to pads on a lead frame structure, at least some of the bonding wires having a selected...

20050266601 - [photoelectric device grinding process and device grinding process]: A photoelectric device grinding process comprising the following steps is disclosed. A wafer comprising a plurality of chip units is provided. Each chip unit has at least a photoelectric device disposed on a surface layer. A dielectric substrate is attached to the wafer with glue having a plurality of spacers...

20050266603 - Image sensor comprising a pixel array having an optical element positioned relative to each pixel: A method for manufacturing an image sensor including an array of pixels and an imaging lens exit pupil for focusing rays of light onto the array of pixels is provided. Each pixel includes a light sensitive region and at least one optical element associated therewith. The method includes positioning the...

20050266604 - Integrated circuit socket corner relief: In some embodiments, a system includes a socket having a first set of socket contacts exposed on a first side of the socket and a second set of socket contacts exposed on a second side of the socket; and a frame comprising at least one surface to engage two lower...

20050266605 - Process for patterning nanocarbon material, semiconductor device, and method for manufacturing semiconductor device: A process for patterning a nanocarbon material includes a step of forming a nanocarbon layer on a substrate; a step of forming a first metal layer on the nanocarbon layer to pattern the first metal layer, the first metal layer containing at least one selected from the group consisting of...

20050266606 - Method of producing an n-type diamond with high electrical conductivity: The invention relates to a method of producing an n-type diamond. The inventive method comprises an n-doping stage during which a donor species is vacuum diffused in a diamond that was initially doped with an acceptor, in order to form donor groups containing the donor species, at a temperature that...

20050266609 - Method of fabricating a built-in chip type substrate: A method of fabricating a built-in chip type substrate containing a semiconductor chip is disclosed. The method comprises a first step of mounting the semiconductor chip on a substrate; a second step of forming chip connection wiring connected to the semiconductor chip mounted on the substrate; and a step of...

20050266607 - Package warpage control: A method of packaging includes placing a restrainer on a package during processing. The method includes clipping the restrainer in place and then exposing the package to high temperatures. After processing the restrainer is removed. An alternative process attaches a component die to a substrate having a cavity in a...

20050266608 - Packaging substrate without plating bar and a method of forming the same: A packaging substrate without plating bar and a method of forming the same is provided. A substrate is firstly provided with circuit patterns formed thereon. Then, solder masks are formed to define connecting points on the circuit patterns. Afterward, the openings of the solder mask on a bottom surface of...

20050266610 - Manufacturing methods for semiconductor structures having stacked semiconductor devices: Methods of manufacturing a semiconductor structure are provided. The method comprises the steps of providing a first substrate having a first surface, providing a semiconductor device, electrically and physically coupling the semiconductor device to the first surface of said first substrate, providing a second substrate having a first surface, a...

20050266611 - Flip chip packaging method and flip chip assembly thereof: The present invention discloses a semi-etching method, which comprises the steps of etching a flip chip bump when producing a lead frame for packaging; electroplating a metal such as gold, silver, or solder onto the flip chip bump by an electroplating process; electrically connecting the bond pad of a chip...

20050266613 - Integrated circuit packages with reduced stress on die and associated methods: Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed...

20050266612 - Top layers of metal for high performance ic's: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within...

20050266614 - Method of manufacturing semiconductor device and method of manufacturing electronic device: A method of manufacturing a semiconductor device includes mounting a first semiconductor chip on each partitioned region of a frame substrate partitioned for each first semiconductor package; mounting a second semiconductor package, where a second semiconductor chip is mounted, on each partitioned region of the frame substrate so as to...

20050266615 - Chip resistor and method for producing the same: A chip resistor includes a resistive element (1), an insulation layer (4) formed in a back surface of the flat surface, and two electrodes (3) spaced from each other via the insulation layer. Each electrode (3) makes contact with the insulation layer (4). Each electrode (3) has a lower surface...

20050266616 - Method for balancing molding flow during the assembly of semiconductor packages with defective carrying units: A method for balancing molding flow during the assembly of semiconductor packages with defective carrying units includes providing a chip carrier, which includes a number of good carrying units and at least a defective carrying unit. Then, a number of chips are attached to the good carrying units of the...

20050266617 - Module with multiple power amplifiers and power sensors: Systems and methods are disclosed for a device having one or more power amplifier and/or LNA circuits positioned on the amplifier module....

20050266618 - Plasma processing method and method for fabricating electronic component module using the same: According to this plasma processing method, a surface of a micro gap provided between a first subject to be processed and a second subject to be processed is processed. According to this plasma processing method, the first and second subjects to be processed are disposed within a process chamber. Then,...

20050266621 - Gate electrodes of semiconductor devices and methods of manufacturing the same: Gate electrodes of semiconductor devices and methods of manufacturing the same are disclosed. An example method comprises: sequentially forming a gate oxide layer and a sacrificial buffer layer on a semiconductor substrate; patterning the sacrificial buffer layer to form an auxiliary pattern; depositing a polysilicon layer; dry etching the polysilicon...

20050266619 - Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a p/n junction: A method for making a semiconductor device is described. That method comprises forming on a substrate a first gate dielectric layer that has a first substantially vertical component, then forming a first metal layer on the first gate dielectric layer. After forming on the substrate a second gate dielectric layer...

20050266620 - Semiconductor device, electro-optic device, integrated circuit, and electronic apparatus: The present invention is directed to a semiconductor device with a thin film transistor on a substrate and a method of forming that semiconductor device and thin film transistor on a substrate. The thin film transistor on the substrate is created by forming a starting point section to be an...

20050266624 - Boron incorporated diffusion barrier material: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy...

20050266625 - Cmos image sensor and fabricating method thereof: A fabricating method of a CMOS image sensor includes the steps of: forming a transfer gate on a semiconductor substrate where a device isolation layer is formed; forming a first n-type ion implantation region for a photodiode beneath a surface of the semiconductor substrate, the first n-type ion implantation region...

20050266629 - Fabrication method for organic semiconductor transistor having organic polymeric gate insulating layer: Provided is a method for fabricating an organic semiconductor transistor having an organic polymeric gate insulating layer. The method includes forming an organic gate insulating layer on a substrate by a vapor deposition method using organic monomer sources, and causing a polymerization reaction to occur in the organic gate insulating...

20050266622 - Method for forming a low thermal budget spacer: A method of forming a sidewall spacer on a gate electrode of a metal oxide semiconductor device that includes striking a first plasma to form an oxide layer on a side of the gate electrode, where the first plasma is generated from a oxide gas that includes O3 and bis-(tertiarybutylamine)silane,...

20050266626 - Method of fabricating heteroepitaxial microstructures: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial...

20050266628 - Substrate isolation in integrated circuits: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric...

20050266623 - Trench power mosfet in silicon carbide and method of making the same: A structure of accumulated type trench MOSFET in silicon carbide(SiC) and forming method are disclosed. The MOSFET includes a trench gate having a gate oxide layer, a polysilicon layer, a source region, and a drain region. The source region contains a p+ heavily doped region, an n+ heavily doped region...

20050266627 - Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of...

20050266630 - Fabrication process of a semiconductor integrated circuit device: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in...

20050266631 - Semiconductor device fabricating method: Compression stress applying portions 20 of SiGe film are formed in the source/drain regions of the p-MOSA region 30a. Then, impurities are implanted in the p-MOS region 30a and the n-MOS region 30b to form shallow junction regions 22a, 22b and deep junction regions 23a, 23b. The impurity in the...

20050266632 - Integrated circuit with strained and non-strained transistors, and method of forming thereof: Preferred embodiments of the present invention utilize system-level band gap engineering. Device improving structures, such as the strained source/drain regions for PMOS devices and a tensile film for NMOS devices, may be employed only in those selected regions such as where high drive current is necessary or desirable. In other...

20050266635 - Graded gexse100-x concentration in pcram: The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse stoichiometries. The present invention also provides a method of fabricating the disclosed PCRAM structure....

20050266633 - Method for fabricating capacitor: A method for fabricating a capacitor is described. A metal layer is formed on a substrate, and then an insulating layer is formed over the substrate covering the metal layer. At least one opening is formed in the insulating layer exposing a portion of the metal layer, and a metal...

20050266634 - Methods of fabricating semiconductor devices including polysilicon resistors and related devices: Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating layer. The second interlayer insulating layer defines a trench such that at least a...

20050266636 - Semiconductor device and method of manufacturing the same: In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first interconnect provided in an upper...

20050266638 - Methods of forming non-volatile memory cells including fin structures and related devices: A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the...

20050266639 - Techique for controlling mechanical stress in a channel region by spacer removal: During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced...

20050266637 - Tunnel oxynitride in flash memories: Methods for forming a tunnel oxide structure device and methods for forming the structure are described. A structure comprising nitrogen is formed on a semiconductor substrate. The structure is oxidized. Nitrogen of the oxide structure is redistributed to form a region of concentrated nitrogen. Oxidizing the structure and redistributing the...

20050266640 - Method of forming a dielectric layer and method of manufacturing a nonvolatile memory device using the same: A method of forming a dielectric layer having a reduced thickness according to embodiments of the invention includes forming a lower oxide layer on a substrate, and forming a nitride layer on the lower oxide layer. Then, a preliminary oxide layer is formed on the nitride layer. A radical oxidation...

20050266641 - Method of forming films in a trench: A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric...

20050266642 - Semiconductor device and a method of fabricating the same: A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26...

20050266643 - Memory with recessed devices: A memory cell includes devices having associated isolation recesses of differing magnitudes. The effective channel width of a corresponding transistor is substantially equal to a channel top surface width plus twice a sidewall width formed by the isolation recesses. In an SRAM cell, a latch transistor has a larger effective...

20050266644 - Method of manufacturing semiconductor device having multiple gate oxide films: A method of manufacturing a semiconductor device includes forming a first insulating film having a first thickness in a first region on a semiconductor substrate, forming a first gate electrode on the first insulating film, and forming a second insulating film having a second thickness different from the first thickness...

20050266645 - Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels: Integrated circuit field effect transistors are manufactured by forming a pre-active pattern on a surface of a substrate, while refraining from doping the pre-active pattern with phosphorus. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the...

20050266646 - Method of forming trench in semiconductor device: There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of...

20050266647 - Method of manufacturing a semiconductor device: Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of...

20050266648 - Methods of forming field effect transistors having recessed channel regions: Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insulating layer is then patterned to define a first plurality of openings therein...

20050266649 - Electronic device manufacturing apparatus: An electronic device manufacturing apparatus is provided with a support which includes a shelf for supporting a substrate, a sensor which obtains the position of the substrate and a position correcting mechanism which corrects the position of the substrate. Or alternatively, an electronic device manufacturing apparatus is provided with a...

20050266650 - Semiconductor device with flowable insulation layer formed on capacitor and method for fabricating the same: Disclosed is a semiconductor device with a flowable insulation layer formed on a capacitor and a method for fabricating the same. Particularly, the semiconductor device includes: a capacitor formed on a predetermined portion of a substrate; an insulation layer formed by stacking a flowable insulation layer and an undoped silicate...

20050266651 - Integrated via resistor: A method of forming a resistor in an integrated circuit, comprising etching a first via in a first layer of dielectric material, depositing a layer of metal adjacent the first layer of dielectric material, depositing a second layer of dielectric material adjacent the layer of metal, and etching a second...

20050266652 - High density mimcap with a unit repeatable structure: A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second...

20050266653 - Substrate manufacturing method: In a substrate manufacturing method of manufacturing a bonded substrate stack by boding the bonding surfaces of the first and second substrates, a bonding surface having a hydrophobic region and a hydrophilic region is formed by partially processing at least one of the bonding surfaces of the first and second...

20050266654 - Barrier to amorphization implant: A method includes forming a first and a second semiconductor region which are joined at a semiconductor junction. The first and second semiconductor regions are truncated with an isolation trench, with an end of the semiconductor junction being disposed at the isolation trench. The isolation trench is at least partially...

20050266655 - Dielectric gap fill with oxide selectively deposited over silicon liner: A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the...

20050266658 - Glass-based soi structures: Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer (15) of a substantially single-crystal semiconductor (e.g., doped silicon) attached to a support substrate (20) composed of an oxide glass or an oxide glass-ceramic. The oxide glass or oxide glass-ceramic...

20050266656 - Method for producing a multilayer storage media: An inventive method for producing a disc shaped workpiece comprises the steps of producing a first and a second disc-shaped substrate, applying a first adhesive at least partially onto one of the flat sides of said first substrate, curing said first adhesive, applying a second adhesive at least partially onto...

20050266657 - Substrate manufacturing method: A first substrate which has a semiconductor and an insulating layer formed on the surface of the semiconductor is prepared. The periphery of the insulating layer is selectively removed to expose the semiconductor. The first substrate on the insulating layer side is bonded to a second substrate to form a...

20050266659 - Methods for transferring a useful layer of silicon carbide to a receiving substrate: Methods for transferring a useful layer of silicon carbide to a receiving substrate are described. In an embodiment, the invention relates to a method for recycling of a silicon carbide source substrate by removal of the excess zone followed by a finishing step to prepare the source substrate for recycling...

20050266660 - Method for the production of indiviual monolithically integrated semiconductor circuits: A method for the production of individual integrated circuit arrangements from a wafer composite is disclosed, whereby the wafer is fixed with the component side (FS) on a support, the individual circuit arrangements (21) are separated on the support body by the etching of separating trenches (27) and individually lifted...

20050266661 - Semiconductor wafer with ditched scribe street: A semiconductor wafer (10) and associated methods are disclosed in which a plurality of semiconductor dice (14) include a semiconductor substrate (12) overlain by a plurality of upper layers (13) are provided with encompassing scribe streets (20) at the top surface (16) of the wafer (10) defined by inactive areas...

20050266662 - Method of growing semiconductor nanowires with uniform cross-sectional area using chemical vapor deposition: A nanowire of a semiconductor material and having a uniform cross-sectional area along its length is grown using a chemical vapor deposition process. In the method, a substrate is provided, a catalyst nanoparticle is deposited on the substrate, a gaseous precursor mixture comprising a constituent element of the semiconductor material...

20050266663 - Method of forming lattice-matched structure on silicon and structure formed thereby: A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD)....

20050266664 - Method for forming a fully silicided semiconductor device: A method for forming an improved fully silicided gate electrode in a semiconductor device in which the fully silicided gate electrode is formed using indirect heating. One embodiment relates to a method of manufacturing at least one semiconductor device. The method includes depositing silicon to a first thickness, depositing metal...

20050266665 - Methods of manufacturing semiconductor devices with gate structures having an oxide layer on the sidewalls thereof and related processing apparatus: In a method of manufacturing a semiconductor device, a gate structure having a conductive layer pattern is formed on a substrate. The gate structure is then annealed. Oxygen radicals are applied to the gate structure to form an oxide layer on a sidewall of the conductive layer pattern....

20050266666 - Suppression of cross diffusion and gate depletion: According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one...

20050266669 - Method and apparatus to eliminate galvanic corrosion on copper doped aluminum bond pads on integrated circuits: The present invention is an electronic interconnect comprising a bond pad consisting essentially of aluminum and copper and configured for use in semiconductor electronic devices to couple a bond wire to an integrated circuit package. The bond pad has an oxide coating residing on at least a topmost surface of...

20050266668 - Semiconductor device and method of manufacturing the same: A semiconductor device comprises a semiconductor element having first electrode pads and solder bumps, and a substrate having second electrode pads connected to the first electrode pads via the solder bumps. The semiconductor element has an insulating film with a low dielectric constant. The group of the solder bumps is...

20050266667 - Structure and method of forming metal buffering layer: A structure and method of forming a metal buffering layer during the formation of a redistribution layer is provided. It only changes a mask to form the metal buffering layer and circuit traces simultaneously. The metal buffering layer can increase the flatness of the dielectric layer covering on the metal...

20050266670 - Chip bonding process: A bonding process includes the following process. A bump is formed on a first electric device. A patterned insulation layer is formed on a second electric device, wherein the patterned insulation layer has a thickness between 5 μm and 400 μm, and an opening is in the patterned insulation layer...

20050266671 - Manufacturing method of semiconductor device: A manufacturing method of a semiconductor device comprises: (a) setting up a paste including a resin on an electrical connection part which is electrically connected to a semiconductor substrate; (b) setting up a soldering material above the electrical connection part so as to be in contact with the paste; and...

20050266672 - Wire-bonding method for chips with copper interconnects by introducing a thin layer: A wire-bonding method for chips with copper interconnects by introducing a thin layer is provided for solving the problem of oxidizing a copper bonding-pad during bonding processing in order not to deteriorate the bonding strength and yield rate thereof. The wire-bonding method of the present invention comprises: a step for...

20050266673 - Reduced electromigration and stressed induced migration of copper wires by surface coating: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by...

20050266674 - Screen printing method of forming conductive bumps: A screen printing method of conductive material is applied to a wafer with a conductive surface thereon. A dielectric layer on the wafer exposes the conductive surface to a first opening. A mask formed on the dielectric layer has a plurality of second openings corresponding to the first opening. The...

20050266675 - Wafer-level thick film standing-wave clocking: An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points from a clock source such that the receiver end points are substantially electrically equivalent with respect to...

20050266676 - Multi-layer dielectric and method of forming same: A multiple dielectric device and its method of manufacture overlaying a semiconductor material, comprising a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first...

20050266677 - Semiconductor device and method of manufacturing the same: An underlying interconnect including a first barrier metal layer, an interconnect metal layer and a second barrier metal layer is formed on a semiconductor substrate, and an interlayer dielectric is formed thereon. Etching is performed with a photoresist defining an opening for a first via, and an opening for a...

20050266679 - Barrier structure for semiconductor devices: A via having a unique barrier layer structure is provided. In an embodiment, a via is formed by forming a barrier layer in a via. The barrier layer along the bottom of the via is partially or completely removed, and the via is filled with a conductive material. In another...

20050266681 - Formation of low resistance via contacts in interconnect structures: A method of fabricating BEOL interconnect structures on a semiconductor device having a plurality of via contacts with low via contact resistance is provided. The method includes the steps of: a) forming a porous or dense low k dielectric layer on a substrate; b) forming single or dual damascene etched...

20050266682 - Methods and apparatus for forming barrier layers in high aspect ratio vias: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of...

20050266680 - Methods of fabricating complex blade geometries from silicon wafers and strengthening blade geometries: Ophthalmic surgical blades are manufactured from either a single crystal or poly-crystalline material, preferably in the form of a wafer. The method comprises preparing the single crystal or poly-crystalline wafers by mounting them and etching trenches into the wafers using one of several processes. Methods for machining the trenches, which...

20050266678 - Source lines for nand memory devices: Methods and apparatus are provided. A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected...

20050266683 - Remover compositions for dual damascene system: A new remover chemistry based on a choline compound, such as choline hydroxide, is provided in order to address problems related to removal of residues, modified photoresists, photoresists, and polymers such as organic anti-reflective coatings and gap-fill and sacrificial polymers from surfaces involved in dual damascene structures without damaging the...

20050266684 - Methods of fabricating tungsten contacts with tungsten nitride barrier layers in semiconductor devices, tungsten contacts with tungsten nitride barrier layers, and apparatus for fabricating the same: A method forming a tungsten contact can include forming a contact hole in an interlayer dielectric layer to expose a portion of an underlying silicon based substrate and to form a side wall of the contact hole. A tungsten silicide layer can be formed on at least on the exposed...

20050266685 - Method and apparatus for controlling a semiconductor fabrication temperature: In a method for controlling temperatures in a semiconductor manufacturing apparatus including a reaction chamber and a plurality of heating sources, a set of power ratios to be fed to the heating sources is determined for each of two or more selected temperatures. Then, a temperature of the reaction chamber...

20050266686 - Method of substrate surface treatment for rram thin film deposition: A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting...

20050266687 - Method of manufacturing semiconductor device and semiconductor device: A silicon substrate has a protective film formed on each side. A semiconductor surface opening not smaller than a given region is formed by removing the protective film. A through-hole having an inner size smaller than the given region is formed in the opening by laser machining. Thereafter, the inner...

20050266688 - Semiconductor device fabrication method: The semiconductor device fabrication method comprises the step of conditioning the surface of a polishing pad 104 while a liquid 126 is being fed onto the polishing pad 104; the step of spraying water 128 onto the polishing pad 104 to clean the surface of the polishing pad 104 after...

20050266689 - Chemical mechanical polishing composition and process: A composition for chemical mechanical polishing includes a slurry. A sufficient amount of a selectively oxidizing and reducing compound is provided in the composition to produce a differential removal of a metal and a dielectric material. A pH adjusting compound adjusts the pH of the composition to provide a pH...

20050266690 - Manufacture of probe unit having lead probes extending beyond edge of substrate: A sacrificial layer is formed in a recess of a substrate, and leads extending from the substrate into an area of the sacrificial layer are formed. A cut is formed from the bottom surface of the substrate, the cut extending from the bottom surface to the area of the sacrificial...

20050266691 - Carbon-doped-si oxide etch using h2 additive in fluorocarbon etch chemistry: Certain embodiments include an etching method including providing an etch material, applying a gas mixture including hydrogen, forming a plasma, and etching the etch material. The etch material can include a low-k dielectric material. The gas mixture can include a hydrogen gas, a hydrogen-free fluorocarbon, and a nitrogen gas, and...

20050266692 - Method of patterning a film: A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of...

20050266693 - Method for manufacturing semiconductor device: A manufacturing method of a semiconductor device of which cost can be suppressed by using a nanoimprinting method is provided. In the invention, a gate insulating film, a conductive film, and a resist are formed in sequence over a semiconductor film and a resist is hardened while pressing a mold...

20050266694 - Controlling bubble formation during etching: A wafer may be rotated while etching to displace bubbles that may form, for example, from a reaction between silicon and water. As a result, a hydrophobic layer, which would otherwise be created by the bubbles, cannot form, resulting in a more uniform etch rate in some embodiments....

20050266695 - Novel aqueous based metal etchant: The present invention provides an aluminum etchant solution for etching an aluminum surface in the presence of solder bumps. The etchant solution includes about 42% to about 80% phosphoric acid; about 0.1% to about 6% nitric acid; about 5% to about 40% acetic acid; about 0.005% to about 5% of...

20050266697 - Light-emitting nanoparticles and method of making same: A method for the production of a robust, chemically stable, crystalline, passivated nanoparticle and composition containing the same, that emit light with high efficiencies and size-tunable and excitation energy tunable color. The methods include the thermal degradation of a precursor molecule in the presence of a capping agent at high...

20050266696 - [method of forming a silicon nitride layer]: A method of forming a silicon nitride layer is provided. A deposition furnace having an outer tube, a wafer boat, a gas injector and a uniform gas injection apparatus is provided. The wafer boat is positioned within the outer tube for carrying a plurality of wafers. The gas injector is...

20050266698 - Exposed pore sealing post patterning: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings...

20050266699 - Organosilicate polymer and insulating film therefrom: Provided is a process for manufacturing an insulating film for a semiconductor device. The process includes preparing a composition for forming an insulating film, wherein the composition comprises a) an organosilicate polymer and b) an organic solvent. The composition is coated on a substrate of a semiconductor device to prepare...

20050266700 - Codeposition of hafnium-germanium oxides on substrates used in or for semiconductor devices: Methods of film deposition using metals and metal oxides. A thin film of germanium oxide and an oxide of a non-germanium metal is deposited by ALD by alternating deposition of first and second precursor compounds, wherein the first precursor compound includes a metal other than germanium, and the second precursor...