| Semiconductor device including misfet -> Monitor Keywords |
|
|
  Semiconductor device including misfetUSPTO Application #: 20070187767Title: Semiconductor device including misfet Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film, a gate electrode, a source/drain layer, and a germanide layer. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the gate insulating film. The source/drain layer is formed on both sides of the gate electrode, contains silicon germanium, and has a germanium layer in a surface layer portion. The germanide layer is formed on the germanium layer of the source/drain layer. (end of abstract) Agent: Foley And Lardner LLP Suite 500 - Washington, DC, US Inventor: Nobuaki Yasutake USPTO Applicaton #: 20070187767 - Class: 257368000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Field Effect Transistor In Integrated Circuit The Patent Description & Claims data below is from USPTO Patent Application 20070187767. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-034916, filed Feb. 13, 2006, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly to an MISFET (Metal Insulator Semiconductor Field Effect Transistor) [0003] 2. Description of the Related Art [0004] In recent years, with miniaturization of semiconductor devices, an increase in speed of an MISFET has attracted attention. For example, in a CMOSFET (Complementally MOS Field Effect Transistor), a carrier (hole) mobility in a channel region of a p-channel MOSFET (which will be referred to as a pMOS hereinafter) is slower than a carrier (electron) mobility in a channel region of an n-channel MOSFET (which will be referred to as an nMOS hereinafter), and hence increasing a speed of the pMOS is demanded. [0005] On the other hand, in the pMOS, it is known that using a silicon germanium as a compound of silicon and germanium having a larger atomic radius than silicon for a source/drain layer provides a compression stress to a channel region and improves a carrier mobility, and that forming a silicide film on the source/drain layer of silicon germanium can reduce a resistance of the source/drain layer (see, e.g., P. R. Chidambaram et. al.; "35% Drive Current Improvement from Recesed-SiGe Drain Extension on 37 nm Gate Length PMOS", 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 48-49). [0006] In this conventional technology, however, when forming the silicide film on the source/drain layer, since the silicon germanium and the silicide film have poor affinity, an increase in a junction leakage current or a contact failure may possibly occur. That is, when, e.g., a nickel silicide film is formed on the silicon germanium, a ternary compound of NiSiGe is formed between them. However, since this compound is thermally unstable, aggregation of Ni or deterioration in surface morphology occurs, a junction leakage current is increased, and unevenness of a contact resistance becomes considerable on, e.g., an interface of the compound and the nickel silicide film. As a result, a problem of deterioration in transistor characteristics may occur. BRIEF SUMMARY OF THE INVENTION [0007] According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; a source/drain layer formed on both sides of the gate electrode, the source/drain layer containing silicon germanium and having a germanium layer in a surface layer portion; and a germanide layer formed on the germanium layer of the source/drain layer. [0008] According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the gate insulating film; a first sidewall insulating film formed on a side surface of the gate electrode; a second sidewall insulating film formed on a side surface of the first sidewall insulating film; a first source/drain layer formed below the second sidewall insulating film, the first source/drain layer containing silicon germanium; a second source/drain layer formed in contact with the first source/drain layer on an outer side of the second sidewall insulating film, the second source/drain layer containing silicon germanium and having a germanium layer in a surface layer portion; and a germanide layer formed on the germanium layer of the second source/drain layer. [0009] According to a third aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a first silicon germanium layer formed on the semiconductor substrate; a second silicon germanium layer formed on the semiconductor substrate apart from the first silicon germanium layer; a gate insulating film formed on the semiconductor substrate between the first silicon germanium layer and the second silicon germanium layer; a gate electrode formed on the gate insulating film; a first germanium layer formed on the first silicon germanium layer; a first germanide layer formed on the first germanium layer; a second germanium layer formed on the second silicon germanium layer; and a second germanide layer formed on the second germanium layer. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING [0010] FIG. 1 is a cross-sectional view showing a semiconductor device according to Embodiment 1 of the present invention; [0011] FIGS. 2 to 8 are cross-sectional views showing a manufacturing method of a semiconductor device according to Embodiment 1; [0012] FIG. 9 is a process cross-sectional view of a semiconductor device according to a modification of Embodiment 1; [0013] FIG. 10 is a cross-sectional view showing a semiconductor device according to Embodiment 2 of the present invention; [0014] FIGS. 11A, 11B, 11C, 12A, 12B, 12C, 13A, and 13B are cross-sectional views showing a manufacturing method of the semiconductor device according to Embodiment 2; [0015] FIG. 14 is a cross-sectional view showing a semiconductor device according to Modification 1 of Embodiment 2 of the present invention; [0016] FIG. 15 is a cross-sectional view showing a semiconductor device according to Modification 2 of Embodiment 2 of the present invention; [0017] FIG. 16 is a cross-sectional view showing a semiconductor device according to Embodiment 3 of the present invention; and [0018] FIG. 17 is a cross-sectional view showing a semiconductor device according to Modification of Embodiment 3 of the present invention. DETAILED DESCRIPTION OF THE INVENTION [0019] A semiconductor device and a manufacturing method thereof according to embodiments of the present invention will now be explained hereinafter with reference to the accompanying drawings. Continue reading... Full patent description for Semiconductor device including misfet Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor device including misfet patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Semiconductor device including misfet or other areas of interest. ### Previous Patent Application: Nano-enabled memory devices and anisotropic charge carrying arrays Next Patent Application: Semiconductor device and method of manufacturing the same Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Semiconductor device including misfet patent info. IP-related news and info Results in 1.57004 seconds Other interesting Feshpatents.com categories: Computers: Graphics , I/O , Processors , Dyn. Storage , Static Storage , Printers |
||
